From 6b6461456d9895c755af60c52dc9c6240b0b8fa0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Mar 2021 17:08:46 +0000 Subject: [PATCH] create small dff with 4x 4k SRAMs --- .../full_core_4_4ksram_small_dff_ls180.il | 424681 +++++++++++++++ experiments9/non_generated/full_core_ls180.il | 6458 +- 2 files changed, 427923 insertions(+), 3216 deletions(-) create mode 100644 experiments9/non_generated/full_core_4_4ksram_small_dff_ls180.il diff --git a/experiments9/non_generated/full_core_4_4ksram_small_dff_ls180.il b/experiments9/non_generated/full_core_4_4ksram_small_dff_ls180.il new file mode 100644 index 0000000..67be3c9 --- /dev/null +++ b/experiments9/non_generated/full_core_4_4ksram_small_dff_ls180.il @@ -0,0 +1,424681 @@ +# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) +autoidx 15098 +attribute \src "libresoc.v:5.1-335.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" +attribute \generator "nMigen" +module \ALU_dec19 + attribute \src "libresoc.v:284.3-293.6" + wire width 3 $0\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:294.3-303.6" + wire width 3 $0\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:324.3-333.6" + wire width 2 $0\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:224.3-233.6" + wire $0\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:194.3-203.6" + wire width 14 $0\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:264.3-273.6" + wire width 3 $0\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:274.3-283.6" + wire width 4 $0\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:254.3-263.6" + wire width 7 $0\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:204.3-213.6" + wire $0\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:214.3-223.6" + wire $0\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:234.3-243.6" + wire $0\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:304.3-313.6" + wire width 4 $0\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:314.3-323.6" + wire width 2 $0\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:244.3-253.6" + wire $0\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:6.7-6.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:284.3-293.6" + wire width 3 $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:294.3-303.6" + wire width 3 $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:324.3-333.6" + wire width 2 $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:224.3-233.6" + wire $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:194.3-203.6" + wire width 14 $1\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:264.3-273.6" + wire width 3 $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:274.3-283.6" + wire width 4 $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:254.3-263.6" + wire width 7 $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:204.3-213.6" + wire $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:214.3-223.6" + wire $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:234.3-243.6" + wire $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:304.3-313.6" + wire width 4 $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:314.3-323.6" + wire width 2 $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:244.3-253.6" + wire $1\ALU_dec19_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec19_sgn + attribute \src "libresoc.v:6.7-6.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \src "libresoc.v:194.3-203.6" + process $proc$libresoc.v:194$1 + assign { } { } + assign { } { } + assign $0\ALU_dec19_function_unit[13:0] $1\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:195.5-195.29" + switch \initial + attribute \src "libresoc.v:195.9-195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_dec19_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[13:0] + end + attribute \src "libresoc.v:204.3-213.6" + process $proc$libresoc.v:204$2 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:205.5-205.29" + switch \initial + attribute \src "libresoc.v:205.9-205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_a[0:0] 1'0 + case + assign $1\ALU_dec19_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] + end + attribute \src "libresoc.v:214.3-223.6" + process $proc$libresoc.v:214$3 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:215.5-215.29" + switch \initial + attribute \src "libresoc.v:215.9-215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_out[0:0] 1'0 + case + assign $1\ALU_dec19_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] + end + attribute \src "libresoc.v:224.3-233.6" + process $proc$libresoc.v:224$4 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:225.5-225.29" + switch \initial + attribute \src "libresoc.v:225.9-225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_out[0:0] 1'0 + case + assign $1\ALU_dec19_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] + end + attribute \src "libresoc.v:234.3-243.6" + process $proc$libresoc.v:234$5 + assign { } { } + assign { } { } + assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:235.5-235.29" + switch \initial + attribute \src "libresoc.v:235.9-235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_is_32b[0:0] 1'0 + case + assign $1\ALU_dec19_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:244.3-253.6" + process $proc$libresoc.v:244$6 + assign { } { } + assign { } { } + assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:245.5-245.29" + switch \initial + attribute \src "libresoc.v:245.9-245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_sgn[0:0] 1'0 + case + assign $1\ALU_dec19_sgn[0:0] 1'0 + end + sync always + update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] + end + attribute \src "libresoc.v:254.3-263.6" + process $proc$libresoc.v:254$7 + assign { } { } + assign { } { } + assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:255.5-255.29" + switch \initial + attribute \src "libresoc.v:255.9-255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_internal_op[6:0] 7'0100100 + case + assign $1\ALU_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:264.3-273.6" + process $proc$libresoc.v:264$8 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:265.5-265.29" + switch \initial + attribute \src "libresoc.v:265.9-265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:274.3-283.6" + process $proc$libresoc.v:274$9 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:275.5-275.29" + switch \initial + attribute \src "libresoc.v:275.9-275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:284.3-293.6" + process $proc$libresoc.v:284$10 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:285.5-285.29" + switch \initial + attribute \src "libresoc.v:285.9-285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_in[2:0] 3'000 + case + assign $1\ALU_dec19_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:294.3-303.6" + process $proc$libresoc.v:294$11 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:295.5-295.29" + switch \initial + attribute \src "libresoc.v:295.9-295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_out[2:0] 3'000 + case + assign $1\ALU_dec19_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:304.3-313.6" + process $proc$libresoc.v:304$12 + assign { } { } + assign { } { } + assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:305.5-305.29" + switch \initial + attribute \src "libresoc.v:305.9-305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:314.3-323.6" + process $proc$libresoc.v:314$13 + assign { } { } + assign { } { } + assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:315.5-315.29" + switch \initial + attribute \src "libresoc.v:315.9-315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:324.3-333.6" + process $proc$libresoc.v:324$14 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:325.5-325.29" + switch \initial + attribute \src "libresoc.v:325.9-325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_in[1:0] 2'00 + case + assign $1\ALU_dec19_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$15 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:339.1-1785.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" +attribute \generator "nMigen" +module \ALU_dec31 + attribute \src "libresoc.v:1492.3-1513.6" + wire width 3 $0\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1514.3-1535.6" + wire width 3 $0\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1580.3-1601.6" + wire width 2 $0\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1646.3-1667.6" + wire $0\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1712.3-1733.6" + wire width 14 $0\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1756.3-1777.6" + wire width 3 $0\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1470.3-1491.6" + wire width 4 $0\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1734.3-1755.6" + wire width 7 $0\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1602.3-1623.6" + wire $0\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1624.3-1645.6" + wire $0\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1668.3-1689.6" + wire $0\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1536.3-1557.6" + wire width 4 $0\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1558.3-1579.6" + wire width 2 $0\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1690.3-1711.6" + wire $0\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:340.7-340.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:1492.3-1513.6" + wire width 3 $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1514.3-1535.6" + wire width 3 $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1580.3-1601.6" + wire width 2 $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1646.3-1667.6" + wire $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1712.3-1733.6" + wire width 14 $1\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1756.3-1777.6" + wire width 3 $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1470.3-1491.6" + wire width 4 $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1734.3-1755.6" + wire width 7 $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1602.3-1623.6" + wire $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1624.3-1645.6" + wire $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1668.3-1689.6" + wire $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1536.3-1557.6" + wire width 4 $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1558.3-1579.6" + wire width 2 $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1690.3-1711.6" + wire $1\ALU_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \ALU_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \ALU_dec31_dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec31_sgn + attribute \src "libresoc.v:340.7-340.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:1385.22-1401.4" + cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 + connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + connect \opcode_in \ALU_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1402.23-1418.4" + cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 + connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + connect \opcode_in \ALU_dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1419.23-1435.4" + cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 + connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + connect \opcode_in \ALU_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1436.23-1452.4" + cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 + connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + connect \opcode_in \ALU_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1453.22-1469.4" + cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 + connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + connect \opcode_in \ALU_dec31_dec_sub8_opcode_in + end + attribute \src "libresoc.v:1470.3-1491.6" + process $proc$libresoc.v:1470$16 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1471.5-1471.29" + switch \initial + attribute \src "libresoc.v:1471.9-1471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + case + assign $1\ALU_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:1492.3-1513.6" + process $proc$libresoc.v:1492$17 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1493.5-1493.29" + switch \initial + attribute \src "libresoc.v:1493.9-1493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + case + assign $1\ALU_dec31_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:1514.3-1535.6" + process $proc$libresoc.v:1514$18 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1515.5-1515.29" + switch \initial + attribute \src "libresoc.v:1515.9-1515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + case + assign $1\ALU_dec31_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:1536.3-1557.6" + process $proc$libresoc.v:1536$19 + assign { } { } + assign { } { } + assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1537.5-1537.29" + switch \initial + attribute \src "libresoc.v:1537.9-1537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + case + assign $1\ALU_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:1558.3-1579.6" + process $proc$libresoc.v:1558$20 + assign { } { } + assign { } { } + assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1559.5-1559.29" + switch \initial + attribute \src "libresoc.v:1559.9-1559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + case + assign $1\ALU_dec31_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:1580.3-1601.6" + process $proc$libresoc.v:1580$21 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1581.5-1581.29" + switch \initial + attribute \src "libresoc.v:1581.9-1581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + case + assign $1\ALU_dec31_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:1602.3-1623.6" + process $proc$libresoc.v:1602$22 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1603.5-1603.29" + switch \initial + attribute \src "libresoc.v:1603.9-1603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + case + assign $1\ALU_dec31_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:1624.3-1645.6" + process $proc$libresoc.v:1624$23 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1625.5-1625.29" + switch \initial + attribute \src "libresoc.v:1625.9-1625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + case + assign $1\ALU_dec31_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:1646.3-1667.6" + process $proc$libresoc.v:1646$24 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1647.5-1647.29" + switch \initial + attribute \src "libresoc.v:1647.9-1647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + case + assign $1\ALU_dec31_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:1668.3-1689.6" + process $proc$libresoc.v:1668$25 + assign { } { } + assign { } { } + assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1669.5-1669.29" + switch \initial + attribute \src "libresoc.v:1669.9-1669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + case + assign $1\ALU_dec31_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:1690.3-1711.6" + process $proc$libresoc.v:1690$26 + assign { } { } + assign { } { } + assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:1691.5-1691.29" + switch \initial + attribute \src "libresoc.v:1691.9-1691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + case + assign $1\ALU_dec31_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] + end + attribute \src "libresoc.v:1712.3-1733.6" + process $proc$libresoc.v:1712$27 + assign { } { } + assign { } { } + assign $0\ALU_dec31_function_unit[13:0] $1\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1713.5-1713.29" + switch \initial + attribute \src "libresoc.v:1713.9-1713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + case + assign $1\ALU_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:1734.3-1755.6" + process $proc$libresoc.v:1734$28 + assign { } { } + assign { } { } + assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1735.5-1735.29" + switch \initial + attribute \src "libresoc.v:1735.9-1735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + case + assign $1\ALU_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:1756.3-1777.6" + process $proc$libresoc.v:1756$29 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1757.5-1757.29" + switch \initial + attribute \src "libresoc.v:1757.9-1757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + case + assign $1\ALU_dec31_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:340.7-340.20" + process $proc$libresoc.v:340$30 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \ALU_dec31_dec_sub8_opcode_in \opcode_in + connect \ALU_dec31_dec_sub22_opcode_in \opcode_in + connect \ALU_dec31_dec_sub26_opcode_in \opcode_in + connect \ALU_dec31_dec_sub0_opcode_in \opcode_in + connect \ALU_dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:1789.1-2203.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub0 + attribute \src "libresoc.v:2122.3-2137.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2138.3-2153.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2186.3-2201.6" + wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2026.3-2041.6" + wire $0\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1978.3-1993.6" + wire width 14 $0\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:2090.3-2105.6" + wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2106.3-2121.6" + wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2074.3-2089.6" + wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1994.3-2009.6" + wire $0\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:2010.3-2025.6" + wire $0\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2042.3-2057.6" + wire $0\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2154.3-2169.6" + wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2170.3-2185.6" + wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2058.3-2073.6" + wire $0\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:1790.7-1790.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2122.3-2137.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2138.3-2153.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2186.3-2201.6" + wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2026.3-2041.6" + wire $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1978.3-1993.6" + wire width 14 $1\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:2090.3-2105.6" + wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2106.3-2121.6" + wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2074.3-2089.6" + wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1994.3-2009.6" + wire $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:2010.3-2025.6" + wire $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2042.3-2057.6" + wire $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2154.3-2169.6" + wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2170.3-2185.6" + wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2058.3-2073.6" + wire $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:1790.7-1790.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:1790.7-1790.20" + process $proc$libresoc.v:1790$45 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:1978.3-1993.6" + process $proc$libresoc.v:1978$31 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_function_unit[13:0] $1\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:1979.5-1979.29" + switch \initial + attribute \src "libresoc.v:1979.9-1979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[13:0] + end + attribute \src "libresoc.v:1994.3-2009.6" + process $proc$libresoc.v:1994$32 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1995.5-1995.29" + switch \initial + attribute \src "libresoc.v:1995.9-1995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:2010.3-2025.6" + process $proc$libresoc.v:2010$33 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2011.5-2011.29" + switch \initial + attribute \src "libresoc.v:2011.9-2011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:2026.3-2041.6" + process $proc$libresoc.v:2026$34 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:2027.5-2027.29" + switch \initial + attribute \src "libresoc.v:2027.9-2027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:2042.3-2057.6" + process $proc$libresoc.v:2042$35 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2043.5-2043.29" + switch \initial + attribute \src "libresoc.v:2043.9-2043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:2058.3-2073.6" + process $proc$libresoc.v:2058$36 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:2059.5-2059.29" + switch \initial + attribute \src "libresoc.v:2059.9-2059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:2074.3-2089.6" + process $proc$libresoc.v:2074$37 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:2075.5-2075.29" + switch \initial + attribute \src "libresoc.v:2075.9-2075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + case + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:2090.3-2105.6" + process $proc$libresoc.v:2090$38 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2091.5-2091.29" + switch \initial + attribute \src "libresoc.v:2091.9-2091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:2106.3-2121.6" + process $proc$libresoc.v:2106$39 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2107.5-2107.29" + switch \initial + attribute \src "libresoc.v:2107.9-2107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + case + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:2122.3-2137.6" + process $proc$libresoc.v:2122$40 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2123.5-2123.29" + switch \initial + attribute \src "libresoc.v:2123.9-2123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:2138.3-2153.6" + process $proc$libresoc.v:2138$41 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2139.5-2139.29" + switch \initial + attribute \src "libresoc.v:2139.9-2139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + case + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:2154.3-2169.6" + process $proc$libresoc.v:2154$42 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2155.5-2155.29" + switch \initial + attribute \src "libresoc.v:2155.9-2155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:2170.3-2185.6" + process $proc$libresoc.v:2170$43 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2171.5-2171.29" + switch \initial + attribute \src "libresoc.v:2171.9-2171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:2186.3-2201.6" + process $proc$libresoc.v:2186$44 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2187.5-2187.29" + switch \initial + attribute \src "libresoc.v:2187.9-2187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + case + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2207.1-2915.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub10 + attribute \src "libresoc.v:2729.3-2765.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2766.3-2802.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2877.3-2913.6" + wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2507.3-2543.6" + wire $0\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2396.3-2432.6" + wire width 14 $0\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2655.3-2691.6" + wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2692.3-2728.6" + wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2618.3-2654.6" + wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2433.3-2469.6" + wire $0\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2470.3-2506.6" + wire $0\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2544.3-2580.6" + wire $0\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2803.3-2839.6" + wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2840.3-2876.6" + wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2581.3-2617.6" + wire $0\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2208.7-2208.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2729.3-2765.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2766.3-2802.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2877.3-2913.6" + wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2507.3-2543.6" + wire $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2396.3-2432.6" + wire width 14 $1\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2655.3-2691.6" + wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2692.3-2728.6" + wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2618.3-2654.6" + wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2433.3-2469.6" + wire $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2470.3-2506.6" + wire $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2544.3-2580.6" + wire $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2803.3-2839.6" + wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2840.3-2876.6" + wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2581.3-2617.6" + wire $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:2208.7-2208.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2208.7-2208.20" + process $proc$libresoc.v:2208$60 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:2396.3-2432.6" + process $proc$libresoc.v:2396$46 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_function_unit[13:0] $1\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2397.5-2397.29" + switch \initial + attribute \src "libresoc.v:2397.9-2397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[13:0] + end + attribute \src "libresoc.v:2433.3-2469.6" + process $proc$libresoc.v:2433$47 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2434.5-2434.29" + switch \initial + attribute \src "libresoc.v:2434.9-2434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:2470.3-2506.6" + process $proc$libresoc.v:2470$48 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2471.5-2471.29" + switch \initial + attribute \src "libresoc.v:2471.9-2471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:2507.3-2543.6" + process $proc$libresoc.v:2507$49 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2508.5-2508.29" + switch \initial + attribute \src "libresoc.v:2508.9-2508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:2544.3-2580.6" + process $proc$libresoc.v:2544$50 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2545.5-2545.29" + switch \initial + attribute \src "libresoc.v:2545.9-2545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:2581.3-2617.6" + process $proc$libresoc.v:2581$51 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2582.5-2582.29" + switch \initial + attribute \src "libresoc.v:2582.9-2582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:2618.3-2654.6" + process $proc$libresoc.v:2618$52 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2619.5-2619.29" + switch \initial + attribute \src "libresoc.v:2619.9-2619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:2655.3-2691.6" + process $proc$libresoc.v:2655$53 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2656.5-2656.29" + switch \initial + attribute \src "libresoc.v:2656.9-2656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:2692.3-2728.6" + process $proc$libresoc.v:2692$54 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2693.5-2693.29" + switch \initial + attribute \src "libresoc.v:2693.9-2693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:2729.3-2765.6" + process $proc$libresoc.v:2729$55 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2730.5-2730.29" + switch \initial + attribute \src "libresoc.v:2730.9-2730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:2766.3-2802.6" + process $proc$libresoc.v:2766$56 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2767.5-2767.29" + switch \initial + attribute \src "libresoc.v:2767.9-2767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] + end + attribute \src "libresoc.v:2803.3-2839.6" + process $proc$libresoc.v:2803$57 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2804.5-2804.29" + switch \initial + attribute \src "libresoc.v:2804.9-2804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:2840.3-2876.6" + process $proc$libresoc.v:2840$58 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2841.5-2841.29" + switch \initial + attribute \src "libresoc.v:2841.9-2841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:2877.3-2913.6" + process $proc$libresoc.v:2877$59 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2878.5-2878.29" + switch \initial + attribute \src "libresoc.v:2878.9-2878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2919.1-3501.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub22 + attribute \src "libresoc.v:3360.3-3387.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3388.3-3415.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3472.3-3499.6" + wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3192.3-3219.6" + wire $0\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3108.3-3135.6" + wire width 14 $0\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3304.3-3331.6" + wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3332.3-3359.6" + wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3276.3-3303.6" + wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3136.3-3163.6" + wire $0\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3164.3-3191.6" + wire $0\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3220.3-3247.6" + wire $0\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3416.3-3443.6" + wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3444.3-3471.6" + wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3248.3-3275.6" + wire $0\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:2920.7-2920.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3360.3-3387.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3388.3-3415.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3472.3-3499.6" + wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3192.3-3219.6" + wire $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3108.3-3135.6" + wire width 14 $1\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3304.3-3331.6" + wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3332.3-3359.6" + wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3276.3-3303.6" + wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3136.3-3163.6" + wire $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3164.3-3191.6" + wire $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3220.3-3247.6" + wire $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3416.3-3443.6" + wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3444.3-3471.6" + wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3248.3-3275.6" + wire $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec31_dec_sub22_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:2920.7-2920.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2920.7-2920.20" + process $proc$libresoc.v:2920$75 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3108.3-3135.6" + process $proc$libresoc.v:3108$61 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_function_unit[13:0] $1\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3109.5-3109.29" + switch \initial + attribute \src "libresoc.v:3109.9-3109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[13:0] + end + attribute \src "libresoc.v:3136.3-3163.6" + process $proc$libresoc.v:3136$62 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3137.5-3137.29" + switch \initial + attribute \src "libresoc.v:3137.9-3137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:3164.3-3191.6" + process $proc$libresoc.v:3164$63 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3165.5-3165.29" + switch \initial + attribute \src "libresoc.v:3165.9-3165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:3192.3-3219.6" + process $proc$libresoc.v:3192$64 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3193.5-3193.29" + switch \initial + attribute \src "libresoc.v:3193.9-3193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:3220.3-3247.6" + process $proc$libresoc.v:3220$65 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3221.5-3221.29" + switch \initial + attribute \src "libresoc.v:3221.9-3221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:3248.3-3275.6" + process $proc$libresoc.v:3248$66 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:3249.5-3249.29" + switch \initial + attribute \src "libresoc.v:3249.9-3249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:3276.3-3303.6" + process $proc$libresoc.v:3276$67 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3277.5-3277.29" + switch \initial + attribute \src "libresoc.v:3277.9-3277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:3304.3-3331.6" + process $proc$libresoc.v:3304$68 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3305.5-3305.29" + switch \initial + attribute \src "libresoc.v:3305.9-3305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:3332.3-3359.6" + process $proc$libresoc.v:3332$69 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3333.5-3333.29" + switch \initial + attribute \src "libresoc.v:3333.9-3333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:3360.3-3387.6" + process $proc$libresoc.v:3360$70 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3361.5-3361.29" + switch \initial + attribute \src "libresoc.v:3361.9-3361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:3388.3-3415.6" + process $proc$libresoc.v:3388$71 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3389.5-3389.29" + switch \initial + attribute \src "libresoc.v:3389.9-3389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:3416.3-3443.6" + process $proc$libresoc.v:3416$72 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3417.5-3417.29" + switch \initial + attribute \src "libresoc.v:3417.9-3417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:3444.3-3471.6" + process $proc$libresoc.v:3444$73 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3445.5-3445.29" + switch \initial + attribute \src "libresoc.v:3445.9-3445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:3472.3-3499.6" + process $proc$libresoc.v:3472$74 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3473.5-3473.29" + switch \initial + attribute \src "libresoc.v:3473.9-3473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3505.1-3919.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub26 + attribute \src "libresoc.v:3838.3-3853.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3854.3-3869.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3902.3-3917.6" + wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3742.3-3757.6" + wire $0\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3694.3-3709.6" + wire width 14 $0\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3806.3-3821.6" + wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3822.3-3837.6" + wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3790.3-3805.6" + wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3710.3-3725.6" + wire $0\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3726.3-3741.6" + wire $0\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3758.3-3773.6" + wire $0\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3870.3-3885.6" + wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3886.3-3901.6" + wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3774.3-3789.6" + wire $0\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3506.7-3506.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3838.3-3853.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3854.3-3869.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3902.3-3917.6" + wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3742.3-3757.6" + wire $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3694.3-3709.6" + wire width 14 $1\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3806.3-3821.6" + wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3822.3-3837.6" + wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3790.3-3805.6" + wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3710.3-3725.6" + wire $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3726.3-3741.6" + wire $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3758.3-3773.6" + wire $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3870.3-3885.6" + wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3886.3-3901.6" + wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3774.3-3789.6" + wire $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:3506.7-3506.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3506.7-3506.20" + process $proc$libresoc.v:3506$90 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3694.3-3709.6" + process $proc$libresoc.v:3694$76 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_function_unit[13:0] $1\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3695.5-3695.29" + switch \initial + attribute \src "libresoc.v:3695.9-3695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[13:0] + end + attribute \src "libresoc.v:3710.3-3725.6" + process $proc$libresoc.v:3710$77 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3711.5-3711.29" + switch \initial + attribute \src "libresoc.v:3711.9-3711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:3726.3-3741.6" + process $proc$libresoc.v:3726$78 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3727.5-3727.29" + switch \initial + attribute \src "libresoc.v:3727.9-3727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:3742.3-3757.6" + process $proc$libresoc.v:3742$79 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3743.5-3743.29" + switch \initial + attribute \src "libresoc.v:3743.9-3743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:3758.3-3773.6" + process $proc$libresoc.v:3758$80 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3759.5-3759.29" + switch \initial + attribute \src "libresoc.v:3759.9-3759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:3774.3-3789.6" + process $proc$libresoc.v:3774$81 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3775.5-3775.29" + switch \initial + attribute \src "libresoc.v:3775.9-3775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:3790.3-3805.6" + process $proc$libresoc.v:3790$82 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3791.5-3791.29" + switch \initial + attribute \src "libresoc.v:3791.9-3791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + case + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:3806.3-3821.6" + process $proc$libresoc.v:3806$83 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3807.5-3807.29" + switch \initial + attribute \src "libresoc.v:3807.9-3807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:3822.3-3837.6" + process $proc$libresoc.v:3822$84 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3823.5-3823.29" + switch \initial + attribute \src "libresoc.v:3823.9-3823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:3838.3-3853.6" + process $proc$libresoc.v:3838$85 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3839.5-3839.29" + switch \initial + attribute \src "libresoc.v:3839.9-3839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:3854.3-3869.6" + process $proc$libresoc.v:3854$86 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3855.5-3855.29" + switch \initial + attribute \src "libresoc.v:3855.9-3855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:3870.3-3885.6" + process $proc$libresoc.v:3870$87 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3871.5-3871.29" + switch \initial + attribute \src "libresoc.v:3871.9-3871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:3886.3-3901.6" + process $proc$libresoc.v:3886$88 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3887.5-3887.29" + switch \initial + attribute \src "libresoc.v:3887.9-3887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:3902.3-3917.6" + process $proc$libresoc.v:3902$89 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3903.5-3903.29" + switch \initial + attribute \src "libresoc.v:3903.9-3903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3923.1-4715.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub8 + attribute \src "libresoc.v:4499.3-4541.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4542.3-4584.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4671.3-4713.6" + wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4241.3-4283.6" + wire $0\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4112.3-4154.6" + wire width 14 $0\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4413.3-4455.6" + wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4456.3-4498.6" + wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4370.3-4412.6" + wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4155.3-4197.6" + wire $0\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4198.3-4240.6" + wire $0\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4284.3-4326.6" + wire $0\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4585.3-4627.6" + wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4628.3-4670.6" + wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4327.3-4369.6" + wire $0\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:3924.7-3924.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4499.3-4541.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4542.3-4584.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4671.3-4713.6" + wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4241.3-4283.6" + wire $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4112.3-4154.6" + wire width 14 $1\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4413.3-4455.6" + wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4456.3-4498.6" + wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4370.3-4412.6" + wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4155.3-4197.6" + wire $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4198.3-4240.6" + wire $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4284.3-4326.6" + wire $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4585.3-4627.6" + wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4628.3-4670.6" + wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4327.3-4369.6" + wire $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_dec31_dec_sub8_sgn + attribute \src "libresoc.v:3924.7-3924.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3924.7-3924.20" + process $proc$libresoc.v:3924$105 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4112.3-4154.6" + process $proc$libresoc.v:4112$91 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_function_unit[13:0] $1\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4113.5-4113.29" + switch \initial + attribute \src "libresoc.v:4113.9-4113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[13:0] + end + attribute \src "libresoc.v:4155.3-4197.6" + process $proc$libresoc.v:4155$92 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4156.5-4156.29" + switch \initial + attribute \src "libresoc.v:4156.9-4156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:4198.3-4240.6" + process $proc$libresoc.v:4198$93 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4199.5-4199.29" + switch \initial + attribute \src "libresoc.v:4199.9-4199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:4241.3-4283.6" + process $proc$libresoc.v:4241$94 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4242.5-4242.29" + switch \initial + attribute \src "libresoc.v:4242.9-4242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:4284.3-4326.6" + process $proc$libresoc.v:4284$95 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4285.5-4285.29" + switch \initial + attribute \src "libresoc.v:4285.9-4285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:4327.3-4369.6" + process $proc$libresoc.v:4327$96 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:4328.5-4328.29" + switch \initial + attribute \src "libresoc.v:4328.9-4328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:4370.3-4412.6" + process $proc$libresoc.v:4370$97 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4371.5-4371.29" + switch \initial + attribute \src "libresoc.v:4371.9-4371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:4413.3-4455.6" + process $proc$libresoc.v:4413$98 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4414.5-4414.29" + switch \initial + attribute \src "libresoc.v:4414.9-4414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:4456.3-4498.6" + process $proc$libresoc.v:4456$99 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4457.5-4457.29" + switch \initial + attribute \src "libresoc.v:4457.9-4457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:4499.3-4541.6" + process $proc$libresoc.v:4499$100 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4500.5-4500.29" + switch \initial + attribute \src "libresoc.v:4500.9-4500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:4542.3-4584.6" + process $proc$libresoc.v:4542$101 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4543.5-4543.29" + switch \initial + attribute \src "libresoc.v:4543.9-4543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] + end + attribute \src "libresoc.v:4585.3-4627.6" + process $proc$libresoc.v:4585$102 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4586.5-4586.29" + switch \initial + attribute \src "libresoc.v:4586.9-4586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:4628.3-4670.6" + process $proc$libresoc.v:4628$103 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4629.5-4629.29" + switch \initial + attribute \src "libresoc.v:4629.9-4629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:4671.3-4713.6" + process $proc$libresoc.v:4671$104 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4672.5-4672.29" + switch \initial + attribute \src "libresoc.v:4672.9-4672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:4719.1-5003.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" +attribute \generator "nMigen" +module \BRANCH_dec19 + attribute \src "libresoc.v:4922.3-4937.6" + wire width 3 $0\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4938.3-4953.6" + wire width 3 $0\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4874.3-4889.6" + wire width 14 $0\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4906.3-4921.6" + wire width 4 $0\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4890.3-4905.6" + wire width 7 $0\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4970.3-4985.6" + wire $0\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4986.3-5001.6" + wire $0\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4954.3-4969.6" + wire width 2 $0\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4720.7-4720.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4922.3-4937.6" + wire width 3 $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4938.3-4953.6" + wire width 3 $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4874.3-4889.6" + wire width 14 $1\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4906.3-4921.6" + wire width 4 $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4890.3-4905.6" + wire width 7 $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4970.3-4985.6" + wire $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4986.3-5001.6" + wire $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4954.3-4969.6" + wire width 2 $1\BRANCH_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 7 \BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \BRANCH_dec19_rc_sel + attribute \src "libresoc.v:4720.7-4720.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4720.7-4720.20" + process $proc$libresoc.v:4720$114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4874.3-4889.6" + process $proc$libresoc.v:4874$106 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_function_unit[13:0] $1\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4875.5-4875.29" + switch \initial + attribute \src "libresoc.v:4875.9-4875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 + case + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000000000 + end + sync always + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[13:0] + end + attribute \src "libresoc.v:4890.3-4905.6" + process $proc$libresoc.v:4890$107 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4891.5-4891.29" + switch \initial + attribute \src "libresoc.v:4891.9-4891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + case + assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:4906.3-4921.6" + process $proc$libresoc.v:4906$108 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4907.5-4907.29" + switch \initial + attribute \src "libresoc.v:4907.9-4907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + case + assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:4922.3-4937.6" + process $proc$libresoc.v:4922$109 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4923.5-4923.29" + switch \initial + attribute \src "libresoc.v:4923.9-4923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + case + assign $1\BRANCH_dec19_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:4938.3-4953.6" + process $proc$libresoc.v:4938$110 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4939.5-4939.29" + switch \initial + attribute \src "libresoc.v:4939.9-4939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + case + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:4954.3-4969.6" + process $proc$libresoc.v:4954$111 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4955.5-4955.29" + switch \initial + attribute \src "libresoc.v:4955.9-4955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:4970.3-4985.6" + process $proc$libresoc.v:4970$112 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4971.5-4971.29" + switch \initial + attribute \src "libresoc.v:4971.9-4971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + case + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:4986.3-5001.6" + process $proc$libresoc.v:4986$113 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4987.5-4987.29" + switch \initial + attribute \src "libresoc.v:4987.9-4987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + case + assign $1\BRANCH_dec19_lk[0:0] 1'0 + end + sync always + update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5007.1-5309.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" +attribute \generator "nMigen" +module \CR_dec19 + attribute \src "libresoc.v:5206.3-5239.6" + wire width 3 $0\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5240.3-5273.6" + wire width 3 $0\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5138.3-5171.6" + wire width 14 $0\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5172.3-5205.6" + wire width 7 $0\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5274.3-5307.6" + wire width 2 $0\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:5008.7-5008.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5206.3-5239.6" + wire width 3 $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5240.3-5273.6" + wire width 3 $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5138.3-5171.6" + wire width 14 $1\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5172.3-5205.6" + wire width 7 $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5274.3-5307.6" + wire width 2 $1\CR_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \CR_dec19_rc_sel + attribute \src "libresoc.v:5008.7-5008.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \src "libresoc.v:5008.7-5008.20" + process $proc$libresoc.v:5008$120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5138.3-5171.6" + process $proc$libresoc.v:5138$115 + assign { } { } + assign { } { } + assign $0\CR_dec19_function_unit[13:0] $1\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5139.5-5139.29" + switch \initial + attribute \src "libresoc.v:5139.9-5139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 + case + assign $1\CR_dec19_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_dec19_function_unit $0\CR_dec19_function_unit[13:0] + end + attribute \src "libresoc.v:5172.3-5205.6" + process $proc$libresoc.v:5172$116 + assign { } { } + assign { } { } + assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5173.5-5173.29" + switch \initial + attribute \src "libresoc.v:5173.9-5173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + case + assign $1\CR_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:5206.3-5239.6" + process $proc$libresoc.v:5206$117 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5207.5-5207.29" + switch \initial + attribute \src "libresoc.v:5207.9-5207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + case + assign $1\CR_dec19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:5240.3-5273.6" + process $proc$libresoc.v:5240$118 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5241.5-5241.29" + switch \initial + attribute \src "libresoc.v:5241.9-5241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + case + assign $1\CR_dec19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:5274.3-5307.6" + process $proc$libresoc.v:5274$119 + assign { } { } + assign { } { } + assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:5275.5-5275.29" + switch \initial + attribute \src "libresoc.v:5275.9-5275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5313.1-6067.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" +attribute \generator "nMigen" +module \CR_dec31 + attribute \src "libresoc.v:6023.3-6041.6" + wire width 3 $0\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:6042.3-6060.6" + wire width 3 $0\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5985.3-6003.6" + wire width 14 $0\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:6004.3-6022.6" + wire width 7 $0\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5966.3-5984.6" + wire width 2 $0\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5314.7-5314.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6023.3-6041.6" + wire width 3 $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:6042.3-6060.6" + wire width 3 $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5985.3-6003.6" + wire width 14 $1\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:6004.3-6022.6" + wire width 7 $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5966.3-5984.6" + wire width 2 $1\CR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \CR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \CR_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \CR_dec31_dec_sub15_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \CR_dec31_dec_sub16_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \CR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \CR_dec31_rc_sel + attribute \src "libresoc.v:5314.7-5314.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:5934.21-5941.4" + cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 + connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + connect \opcode_in \CR_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5942.22-5949.4" + cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 + connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + connect \opcode_in \CR_dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5950.22-5957.4" + cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 + connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + connect \opcode_in \CR_dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5958.22-5965.4" + cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 + connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + connect \opcode_in \CR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:5314.7-5314.20" + process $proc$libresoc.v:5314$126 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5966.3-5984.6" + process $proc$libresoc.v:5966$121 + assign { } { } + assign { } { } + assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5967.5-5967.29" + switch \initial + attribute \src "libresoc.v:5967.9-5967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + case + assign $1\CR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:5985.3-6003.6" + process $proc$libresoc.v:5985$122 + assign { } { } + assign { } { } + assign $0\CR_dec31_function_unit[13:0] $1\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:5986.5-5986.29" + switch \initial + attribute \src "libresoc.v:5986.9-5986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + case + assign $1\CR_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_dec31_function_unit $0\CR_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:6004.3-6022.6" + process $proc$libresoc.v:6004$123 + assign { } { } + assign { } { } + assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:6005.5-6005.29" + switch \initial + attribute \src "libresoc.v:6005.9-6005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + case + assign $1\CR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:6023.3-6041.6" + process $proc$libresoc.v:6023$124 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:6024.5-6024.29" + switch \initial + attribute \src "libresoc.v:6024.9-6024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + case + assign $1\CR_dec31_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:6042.3-6060.6" + process $proc$libresoc.v:6042$125 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:6043.5-6043.29" + switch \initial + attribute \src "libresoc.v:6043.9-6043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + case + assign $1\CR_dec31_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] + end + connect \CR_dec31_dec_sub16_opcode_in \opcode_in + connect \CR_dec31_dec_sub15_opcode_in \opcode_in + connect \CR_dec31_dec_sub19_opcode_in \opcode_in + connect \CR_dec31_dec_sub0_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:6071.1-6253.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" +attribute \generator "nMigen" +module \CR_dec31_dec_sub0 + attribute \src "libresoc.v:6222.3-6231.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6232.3-6241.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6202.3-6211.6" + wire width 14 $0\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6212.3-6221.6" + wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6242.3-6251.6" + wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:6072.7-6072.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6222.3-6231.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6232.3-6241.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6202.3-6211.6" + wire width 14 $1\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6212.3-6221.6" + wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6242.3-6251.6" + wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:6072.7-6072.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6072.7-6072.20" + process $proc$libresoc.v:6072$132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6202.3-6211.6" + process $proc$libresoc.v:6202$127 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_function_unit[13:0] $1\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6203.5-6203.29" + switch \initial + attribute \src "libresoc.v:6203.9-6203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000001000000 + case + assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[13:0] + end + attribute \src "libresoc.v:6212.3-6221.6" + process $proc$libresoc.v:6212$128 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6213.5-6213.29" + switch \initial + attribute \src "libresoc.v:6213.9-6213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:6222.3-6231.6" + process $proc$libresoc.v:6222$129 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6223.5-6223.29" + switch \initial + attribute \src "libresoc.v:6223.9-6223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:6232.3-6241.6" + process $proc$libresoc.v:6232$130 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6233.5-6233.29" + switch \initial + attribute \src "libresoc.v:6233.9-6233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:6242.3-6251.6" + process $proc$libresoc.v:6242$131 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:6243.5-6243.29" + switch \initial + attribute \src "libresoc.v:6243.9-6243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6257.1-6904.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" +attribute \generator "nMigen" +module \CR_dec31_dec_sub15 + attribute \src "libresoc.v:6594.3-6696.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6697.3-6799.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6388.3-6490.6" + wire width 14 $0\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6491.3-6593.6" + wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6800.3-6902.6" + wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6258.7-6258.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6594.3-6696.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6697.3-6799.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6388.3-6490.6" + wire width 14 $1\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6491.3-6593.6" + wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6800.3-6902.6" + wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:6258.7-6258.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6258.7-6258.20" + process $proc$libresoc.v:6258$138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6388.3-6490.6" + process $proc$libresoc.v:6388$133 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_function_unit[13:0] $1\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6389.5-6389.29" + switch \initial + attribute \src "libresoc.v:6389.9-6389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + case + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[13:0] + end + attribute \src "libresoc.v:6491.3-6593.6" + process $proc$libresoc.v:6491$134 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6492.5-6492.29" + switch \initial + attribute \src "libresoc.v:6492.9-6492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:6594.3-6696.6" + process $proc$libresoc.v:6594$135 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6595.5-6595.29" + switch \initial + attribute \src "libresoc.v:6595.9-6595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:6697.3-6799.6" + process $proc$libresoc.v:6697$136 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6698.5-6698.29" + switch \initial + attribute \src "libresoc.v:6698.9-6698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] + end + attribute \src "libresoc.v:6800.3-6902.6" + process $proc$libresoc.v:6800$137 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6801.5-6801.29" + switch \initial + attribute \src "libresoc.v:6801.9-6801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6908.1-7090.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" +attribute \generator "nMigen" +module \CR_dec31_dec_sub16 + attribute \src "libresoc.v:7059.3-7068.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:7069.3-7078.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:7039.3-7048.6" + wire width 14 $0\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7049.3-7058.6" + wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:7079.3-7088.6" + wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:6909.7-6909.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7059.3-7068.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:7069.3-7078.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:7039.3-7048.6" + wire width 14 $1\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7049.3-7058.6" + wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:7079.3-7088.6" + wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:6909.7-6909.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6909.7-6909.20" + process $proc$libresoc.v:6909$144 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7039.3-7048.6" + process $proc$libresoc.v:7039$139 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_function_unit[13:0] $1\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7040.5-7040.29" + switch \initial + attribute \src "libresoc.v:7040.9-7040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000001000000 + case + assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[13:0] + end + attribute \src "libresoc.v:7049.3-7058.6" + process $proc$libresoc.v:7049$140 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:7050.5-7050.29" + switch \initial + attribute \src "libresoc.v:7050.9-7050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:7059.3-7068.6" + process $proc$libresoc.v:7059$141 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:7060.5-7060.29" + switch \initial + attribute \src "libresoc.v:7060.9-7060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:7069.3-7078.6" + process $proc$libresoc.v:7069$142 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:7070.5-7070.29" + switch \initial + attribute \src "libresoc.v:7070.9-7070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] + end + attribute \src "libresoc.v:7079.3-7088.6" + process $proc$libresoc.v:7079$143 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:7080.5-7080.29" + switch \initial + attribute \src "libresoc.v:7080.9-7080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:7094.1-7276.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" +attribute \generator "nMigen" +module \CR_dec31_dec_sub19 + attribute \src "libresoc.v:7245.3-7254.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7255.3-7264.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7225.3-7234.6" + wire width 14 $0\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7235.3-7244.6" + wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7265.3-7274.6" + wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:7095.7-7095.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7245.3-7254.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7255.3-7264.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7225.3-7234.6" + wire width 14 $1\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7235.3-7244.6" + wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7265.3-7274.6" + wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:7095.7-7095.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:7095.7-7095.20" + process $proc$libresoc.v:7095$150 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7225.3-7234.6" + process $proc$libresoc.v:7225$145 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_function_unit[13:0] $1\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7226.5-7226.29" + switch \initial + attribute \src "libresoc.v:7226.9-7226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000001000000 + case + assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[13:0] + end + attribute \src "libresoc.v:7235.3-7244.6" + process $proc$libresoc.v:7235$146 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7236.5-7236.29" + switch \initial + attribute \src "libresoc.v:7236.9-7236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 + case + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:7245.3-7254.6" + process $proc$libresoc.v:7245$147 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7246.5-7246.29" + switch \initial + attribute \src "libresoc.v:7246.9-7246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:7255.3-7264.6" + process $proc$libresoc.v:7255$148 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7256.5-7256.29" + switch \initial + attribute \src "libresoc.v:7256.9-7256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:7265.3-7274.6" + process $proc$libresoc.v:7265$149 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:7266.5-7266.29" + switch \initial + attribute \src "libresoc.v:7266.9-7266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:7280.1-8033.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" +attribute \generator "nMigen" +module \DIV_dec31 + attribute \src "libresoc.v:8003.3-8015.6" + wire width 3 $0\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:8016.3-8028.6" + wire width 3 $0\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7873.3-7885.6" + wire width 2 $0\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7912.3-7924.6" + wire $0\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7951.3-7963.6" + wire width 14 $0\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7977.3-7989.6" + wire width 3 $0\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7990.3-8002.6" + wire width 4 $0\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7964.3-7976.6" + wire width 7 $0\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire $0\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7899.3-7911.6" + wire $0\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7925.3-7937.6" + wire $0\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire width 4 $0\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire width 2 $0\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7938.3-7950.6" + wire $0\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7281.7-7281.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:8003.3-8015.6" + wire width 3 $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:8016.3-8028.6" + wire width 3 $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7873.3-7885.6" + wire width 2 $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7912.3-7924.6" + wire $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7951.3-7963.6" + wire width 14 $1\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7977.3-7989.6" + wire width 3 $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7990.3-8002.6" + wire width 4 $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7964.3-7976.6" + wire width 7 $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7899.3-7911.6" + wire $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7925.3-7937.6" + wire $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire width 4 $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire width 2 $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7938.3-7950.6" + wire $1\DIV_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \DIV_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + 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"OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + 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\DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \DIV_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute 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\enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute 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\enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \DIV_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \DIV_dec31_sgn + attribute \src "libresoc.v:7281.7-7281.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:7813.23-7829.4" + cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 + connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + connect \opcode_in \DIV_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:7830.22-7846.4" + cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 + connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + connect \opcode_in \DIV_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:7281.7-7281.20" + process $proc$libresoc.v:7281$165 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7847.3-7859.6" + process $proc$libresoc.v:7847$151 + assign { } { } + assign { } { } + assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7848.5-7848.29" + switch \initial + attribute \src "libresoc.v:7848.9-7848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + case + assign $1\DIV_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:7860.3-7872.6" + process $proc$libresoc.v:7860$152 + assign { } { } + assign { } { } + assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7861.5-7861.29" + switch \initial + attribute \src "libresoc.v:7861.9-7861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + case + assign $1\DIV_dec31_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:7873.3-7885.6" + process $proc$libresoc.v:7873$153 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7874.5-7874.29" + switch \initial + attribute \src "libresoc.v:7874.9-7874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + case + assign $1\DIV_dec31_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:7886.3-7898.6" + process $proc$libresoc.v:7886$154 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7887.5-7887.29" + switch \initial + attribute \src "libresoc.v:7887.9-7887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + case + assign $1\DIV_dec31_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:7899.3-7911.6" + process $proc$libresoc.v:7899$155 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7900.5-7900.29" + switch \initial + attribute \src "libresoc.v:7900.9-7900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + case + assign $1\DIV_dec31_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:7912.3-7924.6" + process $proc$libresoc.v:7912$156 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7913.5-7913.29" + switch \initial + attribute \src "libresoc.v:7913.9-7913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + case + assign $1\DIV_dec31_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:7925.3-7937.6" + process $proc$libresoc.v:7925$157 + assign { } { } + assign { } { } + assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7926.5-7926.29" + switch \initial + attribute \src "libresoc.v:7926.9-7926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + case + assign $1\DIV_dec31_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:7938.3-7950.6" + process $proc$libresoc.v:7938$158 + assign { } { } + assign { } { } + assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7939.5-7939.29" + switch \initial + attribute \src "libresoc.v:7939.9-7939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + case + assign $1\DIV_dec31_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] + end + attribute \src "libresoc.v:7951.3-7963.6" + process $proc$libresoc.v:7951$159 + assign { } { } + assign { } { } + assign $0\DIV_dec31_function_unit[13:0] $1\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7952.5-7952.29" + switch \initial + attribute \src "libresoc.v:7952.9-7952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + case + assign $1\DIV_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:7964.3-7976.6" + process $proc$libresoc.v:7964$160 + assign { } { } + assign { } { } + assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7965.5-7965.29" + switch \initial + attribute \src "libresoc.v:7965.9-7965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + case + assign $1\DIV_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:7977.3-7989.6" + process $proc$libresoc.v:7977$161 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7978.5-7978.29" + switch \initial + attribute \src "libresoc.v:7978.9-7978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + case + assign $1\DIV_dec31_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:7990.3-8002.6" + process $proc$libresoc.v:7990$162 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7991.5-7991.29" + switch \initial + attribute \src "libresoc.v:7991.9-7991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + case + assign $1\DIV_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:8003.3-8015.6" + process $proc$libresoc.v:8003$163 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:8004.5-8004.29" + switch \initial + attribute \src "libresoc.v:8004.9-8004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + case + assign $1\DIV_dec31_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:8016.3-8028.6" + process $proc$libresoc.v:8016$164 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:8017.5-8017.29" + switch \initial + attribute \src "libresoc.v:8017.9-8017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + case + assign $1\DIV_dec31_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] + end + connect \DIV_dec31_dec_sub11_opcode_in \opcode_in + connect \DIV_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:8037.1-8745.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub11 + attribute \src "libresoc.v:8559.3-8595.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8596.3-8632.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8707.3-8743.6" + wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8337.3-8373.6" + wire $0\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8226.3-8262.6" + wire width 14 $0\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8485.3-8521.6" + wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8522.3-8558.6" + wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8448.3-8484.6" + wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8263.3-8299.6" + wire $0\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8300.3-8336.6" + wire $0\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8374.3-8410.6" + wire $0\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8633.3-8669.6" + wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8670.3-8706.6" + wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8411.3-8447.6" + wire $0\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:8038.7-8038.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:8559.3-8595.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8596.3-8632.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8707.3-8743.6" + wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8337.3-8373.6" + wire $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8226.3-8262.6" + wire width 14 $1\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8485.3-8521.6" + wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8522.3-8558.6" + wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8448.3-8484.6" + wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8263.3-8299.6" + wire $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8300.3-8336.6" + wire $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8374.3-8410.6" + wire $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8633.3-8669.6" + wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8670.3-8706.6" + wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8411.3-8447.6" + wire $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \DIV_dec31_dec_sub11_sgn + attribute \src "libresoc.v:8038.7-8038.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:8038.7-8038.20" + process $proc$libresoc.v:8038$180 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8226.3-8262.6" + process $proc$libresoc.v:8226$166 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_function_unit[13:0] $1\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8227.5-8227.29" + switch \initial + attribute \src "libresoc.v:8227.9-8227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + case + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 + end + sync always + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[13:0] + end + attribute \src "libresoc.v:8263.3-8299.6" + process $proc$libresoc.v:8263$167 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8264.5-8264.29" + switch \initial + attribute \src "libresoc.v:8264.9-8264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:8300.3-8336.6" + process $proc$libresoc.v:8300$168 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8301.5-8301.29" + switch \initial + attribute \src "libresoc.v:8301.9-8301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:8337.3-8373.6" + process $proc$libresoc.v:8337$169 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8338.5-8338.29" + switch \initial + attribute \src "libresoc.v:8338.9-8338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:8374.3-8410.6" + process $proc$libresoc.v:8374$170 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8375.5-8375.29" + switch \initial + attribute \src "libresoc.v:8375.9-8375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:8411.3-8447.6" + process $proc$libresoc.v:8411$171 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:8412.5-8412.29" + switch \initial + attribute \src "libresoc.v:8412.9-8412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:8448.3-8484.6" + process $proc$libresoc.v:8448$172 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8449.5-8449.29" + switch \initial + attribute \src "libresoc.v:8449.9-8449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:8485.3-8521.6" + process $proc$libresoc.v:8485$173 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8486.5-8486.29" + switch \initial + attribute \src "libresoc.v:8486.9-8486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:8522.3-8558.6" + process $proc$libresoc.v:8522$174 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8523.5-8523.29" + switch \initial + attribute \src "libresoc.v:8523.9-8523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:8559.3-8595.6" + process $proc$libresoc.v:8559$175 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8560.5-8560.29" + switch \initial + attribute \src "libresoc.v:8560.9-8560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:8596.3-8632.6" + process $proc$libresoc.v:8596$176 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8597.5-8597.29" + switch \initial + attribute \src "libresoc.v:8597.9-8597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:8633.3-8669.6" + process $proc$libresoc.v:8633$177 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8634.5-8634.29" + switch \initial + attribute \src "libresoc.v:8634.9-8634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:8670.3-8706.6" + process $proc$libresoc.v:8670$178 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8671.5-8671.29" + switch \initial + attribute \src "libresoc.v:8671.9-8671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:8707.3-8743.6" + process $proc$libresoc.v:8707$179 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8708.5-8708.29" + switch \initial + attribute \src "libresoc.v:8708.9-8708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:8749.1-9457.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub9 + attribute \src "libresoc.v:9271.3-9307.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9308.3-9344.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9419.3-9455.6" + wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:9049.3-9085.6" + wire $0\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8938.3-8974.6" + wire width 14 $0\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:9197.3-9233.6" + wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9234.3-9270.6" + wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9160.3-9196.6" + wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8975.3-9011.6" + wire $0\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:9012.3-9048.6" + wire $0\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:9086.3-9122.6" + wire $0\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9345.3-9381.6" + wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9382.3-9418.6" + wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9123.3-9159.6" + wire $0\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:8750.7-8750.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:9271.3-9307.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9308.3-9344.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9419.3-9455.6" + wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:9049.3-9085.6" + wire $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8938.3-8974.6" + wire width 14 $1\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:9197.3-9233.6" + wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9234.3-9270.6" + wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9160.3-9196.6" + wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8975.3-9011.6" + wire $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:9012.3-9048.6" + wire $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:9086.3-9122.6" + wire $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9345.3-9381.6" + wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9382.3-9418.6" + wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9123.3-9159.6" + wire $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:8750.7-8750.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:8750.7-8750.20" + process $proc$libresoc.v:8750$195 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8938.3-8974.6" + process $proc$libresoc.v:8938$181 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_function_unit[13:0] $1\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:8939.5-8939.29" + switch \initial + attribute \src "libresoc.v:8939.9-8939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + case + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 + end + sync always + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[13:0] + end + attribute \src "libresoc.v:8975.3-9011.6" + process $proc$libresoc.v:8975$182 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8976.5-8976.29" + switch \initial + attribute \src "libresoc.v:8976.9-8976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:9012.3-9048.6" + process $proc$libresoc.v:9012$183 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:9013.5-9013.29" + switch \initial + attribute \src "libresoc.v:9013.9-9013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:9049.3-9085.6" + process $proc$libresoc.v:9049$184 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:9050.5-9050.29" + switch \initial + attribute \src "libresoc.v:9050.9-9050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:9086.3-9122.6" + process $proc$libresoc.v:9086$185 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9087.5-9087.29" + switch \initial + attribute \src "libresoc.v:9087.9-9087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:9123.3-9159.6" + process $proc$libresoc.v:9123$186 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:9124.5-9124.29" + switch \initial + attribute \src "libresoc.v:9124.9-9124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:9160.3-9196.6" + process $proc$libresoc.v:9160$187 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:9161.5-9161.29" + switch \initial + attribute \src "libresoc.v:9161.9-9161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:9197.3-9233.6" + process $proc$libresoc.v:9197$188 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9198.5-9198.29" + switch \initial + attribute \src "libresoc.v:9198.9-9198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:9234.3-9270.6" + process $proc$libresoc.v:9234$189 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9235.5-9235.29" + switch \initial + attribute \src "libresoc.v:9235.9-9235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:9271.3-9307.6" + process $proc$libresoc.v:9271$190 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9272.5-9272.29" + switch \initial + attribute \src "libresoc.v:9272.9-9272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:9308.3-9344.6" + process $proc$libresoc.v:9308$191 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9309.5-9309.29" + switch \initial + attribute \src "libresoc.v:9309.9-9309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:9345.3-9381.6" + process $proc$libresoc.v:9345$192 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9346.5-9346.29" + switch \initial + attribute \src "libresoc.v:9346.9-9346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:9382.3-9418.6" + process $proc$libresoc.v:9382$193 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9383.5-9383.29" + switch \initial + attribute \src "libresoc.v:9383.9-9383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:9419.3-9455.6" + process $proc$libresoc.v:9419$194 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:9420.5-9420.29" + switch \initial + attribute \src "libresoc.v:9420.9-9420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:9461.1-10647.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" +attribute \generator "nMigen" +module \LDST_dec31 + attribute \src "libresoc.v:10489.3-10507.6" + wire $0\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10394.3-10412.6" + wire width 3 $0\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10413.3-10431.6" + wire width 3 $0\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10565.3-10583.6" + wire width 14 $0\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10603.3-10621.6" + wire width 3 $0\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10622.3-10640.6" + wire width 4 $0\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10584.3-10602.6" + wire width 7 $0\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10527.3-10545.6" + wire $0\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10432.3-10450.6" + wire width 4 $0\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10470.3-10488.6" + wire width 2 $0\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10546.3-10564.6" + wire $0\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10508.3-10526.6" + wire $0\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10451.3-10469.6" + wire width 2 $0\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:9462.7-9462.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10489.3-10507.6" + wire $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10394.3-10412.6" + wire width 3 $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10413.3-10431.6" + wire width 3 $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10565.3-10583.6" + wire width 14 $1\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10603.3-10621.6" + wire width 3 $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10622.3-10640.6" + wire width 4 $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10584.3-10602.6" + wire width 7 $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10527.3-10545.6" + wire $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10432.3-10450.6" + wire width 4 $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10470.3-10488.6" + wire width 2 $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10546.3-10564.6" + wire $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10508.3-10526.6" + wire $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10451.3-10469.6" + wire width 2 $1\LDST_dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec31_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" 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"OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \LDST_dec31_dec_sub23_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec31_upd + attribute \src "libresoc.v:9462.7-9462.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:10330.24-10345.4" + cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 + connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + connect \LDST_dec31_dec_sub20_cr_out \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + connect \LDST_dec31_dec_sub20_function_unit \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + connect \LDST_dec31_dec_sub20_in1_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + connect \LDST_dec31_dec_sub20_in2_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + connect \LDST_dec31_dec_sub20_internal_op \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + connect \LDST_dec31_dec_sub20_is_32b \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + connect \LDST_dec31_dec_sub20_ldst_len \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + connect \LDST_dec31_dec_sub20_rc_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + connect \LDST_dec31_dec_sub20_sgn \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + connect \LDST_dec31_dec_sub20_sgn_ext \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + connect \LDST_dec31_dec_sub20_upd \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + connect \opcode_in \LDST_dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10346.24-10361.4" + cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 + connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + connect \LDST_dec31_dec_sub21_cr_out \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + connect \LDST_dec31_dec_sub21_function_unit \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + connect \LDST_dec31_dec_sub21_in1_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + connect \LDST_dec31_dec_sub21_in2_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + connect \LDST_dec31_dec_sub21_internal_op \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + connect \LDST_dec31_dec_sub21_is_32b \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + connect \LDST_dec31_dec_sub21_ldst_len \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + connect \LDST_dec31_dec_sub21_rc_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + connect \LDST_dec31_dec_sub21_sgn \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + connect \LDST_dec31_dec_sub21_sgn_ext \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + connect \LDST_dec31_dec_sub21_upd \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + connect \opcode_in \LDST_dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10362.24-10377.4" + cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 + connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + connect \opcode_in \LDST_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10378.24-10393.4" + cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 + connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + connect \opcode_in \LDST_dec31_dec_sub23_opcode_in + end + attribute \src "libresoc.v:10394.3-10412.6" + process $proc$libresoc.v:10394$196 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10395.5-10395.29" + switch \initial + attribute \src "libresoc.v:10395.9-10395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + case + assign $1\LDST_dec31_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:10413.3-10431.6" + process $proc$libresoc.v:10413$197 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10414.5-10414.29" + switch \initial + attribute \src "libresoc.v:10414.9-10414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + case + assign $1\LDST_dec31_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:10432.3-10450.6" + process $proc$libresoc.v:10432$198 + assign { } { } + assign { } { } + assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10433.5-10433.29" + switch \initial + attribute \src "libresoc.v:10433.9-10433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + case + assign $1\LDST_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:10451.3-10469.6" + process $proc$libresoc.v:10451$199 + assign { } { } + assign { } { } + assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:10452.5-10452.29" + switch \initial + attribute \src "libresoc.v:10452.9-10452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + case + assign $1\LDST_dec31_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] + end + attribute \src "libresoc.v:10470.3-10488.6" + process $proc$libresoc.v:10470$200 + assign { } { } + assign { } { } + assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10471.5-10471.29" + switch \initial + attribute \src "libresoc.v:10471.9-10471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + case + assign $1\LDST_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:10489.3-10507.6" + process $proc$libresoc.v:10489$201 + assign { } { } + assign { } { } + assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10490.5-10490.29" + switch \initial + attribute \src "libresoc.v:10490.9-10490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + case + assign $1\LDST_dec31_br[0:0] 1'0 + end + sync always + update \LDST_dec31_br $0\LDST_dec31_br[0:0] + end + attribute \src "libresoc.v:10508.3-10526.6" + process $proc$libresoc.v:10508$202 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10509.5-10509.29" + switch \initial + attribute \src "libresoc.v:10509.9-10509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + case + assign $1\LDST_dec31_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:10527.3-10545.6" + process $proc$libresoc.v:10527$203 + assign { } { } + assign { } { } + assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10528.5-10528.29" + switch \initial + attribute \src "libresoc.v:10528.9-10528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + case + assign $1\LDST_dec31_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:10546.3-10564.6" + process $proc$libresoc.v:10546$204 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10547.5-10547.29" + switch \initial + attribute \src "libresoc.v:10547.9-10547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + case + assign $1\LDST_dec31_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] + end + attribute \src "libresoc.v:10565.3-10583.6" + process $proc$libresoc.v:10565$205 + assign { } { } + assign { } { } + assign $0\LDST_dec31_function_unit[13:0] $1\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10566.5-10566.29" + switch \initial + attribute \src "libresoc.v:10566.9-10566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + case + assign $1\LDST_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:10584.3-10602.6" + process $proc$libresoc.v:10584$206 + assign { } { } + assign { } { } + assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10585.5-10585.29" + switch \initial + attribute \src "libresoc.v:10585.9-10585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + case + assign $1\LDST_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:10603.3-10621.6" + process $proc$libresoc.v:10603$207 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10604.5-10604.29" + switch \initial + attribute \src "libresoc.v:10604.9-10604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + case + assign $1\LDST_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:10622.3-10640.6" + process $proc$libresoc.v:10622$208 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10623.5-10623.29" + switch \initial + attribute \src "libresoc.v:10623.9-10623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + case + assign $1\LDST_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:9462.7-9462.20" + process $proc$libresoc.v:9462$209 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \LDST_dec31_dec_sub23_opcode_in \opcode_in + connect \LDST_dec31_dec_sub21_opcode_in \opcode_in + connect \LDST_dec31_dec_sub20_opcode_in \opcode_in + connect \LDST_dec31_dec_sub22_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:10651.1-11164.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub20 + attribute \src "libresoc.v:10863.3-10887.6" + wire $0\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:11038.3-11062.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:11063.3-11087.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10838.3-10862.6" + wire width 14 $0\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10988.3-11012.6" + wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:11013.3-11037.6" + wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10963.3-10987.6" + wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10913.3-10937.6" + wire $0\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:11088.3-11112.6" + wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:11138.3-11162.6" + wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10938.3-10962.6" + wire $0\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10888.3-10912.6" + wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:11113.3-11137.6" + wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:10652.7-10652.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10863.3-10887.6" + wire $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:11038.3-11062.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:11063.3-11087.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10838.3-10862.6" + wire width 14 $1\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10988.3-11012.6" + wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:11013.3-11037.6" + wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10963.3-10987.6" + wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10913.3-10937.6" + wire $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:11088.3-11112.6" + wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:11138.3-11162.6" + wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10938.3-10962.6" + wire $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10888.3-10912.6" + wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:11113.3-11137.6" + wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:10652.7-10652.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:10652.7-10652.20" + process $proc$libresoc.v:10652$223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:10838.3-10862.6" + process $proc$libresoc.v:10838$210 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_function_unit[13:0] $1\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10839.5-10839.29" + switch \initial + attribute \src "libresoc.v:10839.9-10839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[13:0] + end + attribute \src "libresoc.v:10863.3-10887.6" + process $proc$libresoc.v:10863$211 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10864.5-10864.29" + switch \initial + attribute \src "libresoc.v:10864.9-10864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:10888.3-10912.6" + process $proc$libresoc.v:10888$212 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10889.5-10889.29" + switch \initial + attribute \src "libresoc.v:10889.9-10889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:10913.3-10937.6" + process $proc$libresoc.v:10913$213 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10914.5-10914.29" + switch \initial + attribute \src "libresoc.v:10914.9-10914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:10938.3-10962.6" + process $proc$libresoc.v:10938$214 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10939.5-10939.29" + switch \initial + attribute \src "libresoc.v:10939.9-10939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:10963.3-10987.6" + process $proc$libresoc.v:10963$215 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10964.5-10964.29" + switch \initial + attribute \src "libresoc.v:10964.9-10964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:10988.3-11012.6" + process $proc$libresoc.v:10988$216 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10989.5-10989.29" + switch \initial + attribute \src "libresoc.v:10989.9-10989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:11013.3-11037.6" + process $proc$libresoc.v:11013$217 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:11014.5-11014.29" + switch \initial + attribute \src "libresoc.v:11014.9-11014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:11038.3-11062.6" + process $proc$libresoc.v:11038$218 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:11039.5-11039.29" + switch \initial + attribute \src "libresoc.v:11039.9-11039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:11063.3-11087.6" + process $proc$libresoc.v:11063$219 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:11064.5-11064.29" + switch \initial + attribute \src "libresoc.v:11064.9-11064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] + end + attribute \src "libresoc.v:11088.3-11112.6" + process $proc$libresoc.v:11088$220 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:11089.5-11089.29" + switch \initial + attribute \src "libresoc.v:11089.9-11089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:11113.3-11137.6" + process $proc$libresoc.v:11113$221 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:11114.5-11114.29" + switch \initial + attribute \src "libresoc.v:11114.9-11114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:11138.3-11162.6" + process $proc$libresoc.v:11138$222 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:11139.5-11139.29" + switch \initial + attribute \src "libresoc.v:11139.9-11139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:11168.1-11993.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub21 + attribute \src "libresoc.v:11404.3-11452.6" + wire $0\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11747.3-11795.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11796.3-11844.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11355.3-11403.6" + wire width 14 $0\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11649.3-11697.6" + wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11698.3-11746.6" + wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11600.3-11648.6" + wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11502.3-11550.6" + wire $0\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11845.3-11893.6" + wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11943.3-11991.6" + wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11551.3-11599.6" + wire $0\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11453.3-11501.6" + wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11894.3-11942.6" + wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:11169.7-11169.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:11404.3-11452.6" + wire $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11747.3-11795.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11796.3-11844.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11355.3-11403.6" + wire width 14 $1\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11649.3-11697.6" + wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11698.3-11746.6" + wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11600.3-11648.6" + wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11502.3-11550.6" + wire $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11845.3-11893.6" + wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11943.3-11991.6" + wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11551.3-11599.6" + wire $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11453.3-11501.6" + wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11894.3-11942.6" + wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:11169.7-11169.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:11169.7-11169.20" + process $proc$libresoc.v:11169$237 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:11355.3-11403.6" + process $proc$libresoc.v:11355$224 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_function_unit[13:0] $1\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11356.5-11356.29" + switch \initial + attribute \src "libresoc.v:11356.9-11356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[13:0] + end + attribute \src "libresoc.v:11404.3-11452.6" + process $proc$libresoc.v:11404$225 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11405.5-11405.29" + switch \initial + attribute \src "libresoc.v:11405.9-11405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:11453.3-11501.6" + process $proc$libresoc.v:11453$226 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11454.5-11454.29" + switch \initial + attribute \src "libresoc.v:11454.9-11454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:11502.3-11550.6" + process $proc$libresoc.v:11502$227 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11503.5-11503.29" + switch \initial + attribute \src "libresoc.v:11503.9-11503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:11551.3-11599.6" + process $proc$libresoc.v:11551$228 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11552.5-11552.29" + switch \initial + attribute \src "libresoc.v:11552.9-11552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:11600.3-11648.6" + process $proc$libresoc.v:11600$229 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11601.5-11601.29" + switch \initial + attribute \src "libresoc.v:11601.9-11601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:11649.3-11697.6" + process $proc$libresoc.v:11649$230 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11650.5-11650.29" + switch \initial + attribute \src "libresoc.v:11650.9-11650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:11698.3-11746.6" + process $proc$libresoc.v:11698$231 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11699.5-11699.29" + switch \initial + attribute \src "libresoc.v:11699.9-11699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:11747.3-11795.6" + process $proc$libresoc.v:11747$232 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11748.5-11748.29" + switch \initial + attribute \src "libresoc.v:11748.9-11748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:11796.3-11844.6" + process $proc$libresoc.v:11796$233 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11797.5-11797.29" + switch \initial + attribute \src "libresoc.v:11797.9-11797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] + end + attribute \src "libresoc.v:11845.3-11893.6" + process $proc$libresoc.v:11845$234 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11846.5-11846.29" + switch \initial + attribute \src "libresoc.v:11846.9-11846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:11894.3-11942.6" + process $proc$libresoc.v:11894$235 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:11895.5-11895.29" + switch \initial + attribute \src "libresoc.v:11895.9-11895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:11943.3-11991.6" + process $proc$libresoc.v:11943$236 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11944.5-11944.29" + switch \initial + attribute \src "libresoc.v:11944.9-11944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:11997.1-12588.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub22 + attribute \src "libresoc.v:12215.3-12245.6" + wire $0\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12432.3-12462.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12463.3-12493.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12184.3-12214.6" + wire width 14 $0\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12370.3-12400.6" + wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12401.3-12431.6" + wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12339.3-12369.6" + wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12277.3-12307.6" + wire $0\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12494.3-12524.6" + wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12556.3-12586.6" + wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12308.3-12338.6" + wire $0\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12246.3-12276.6" + wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12525.3-12555.6" + wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:11998.7-11998.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12215.3-12245.6" + wire $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12432.3-12462.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12463.3-12493.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12184.3-12214.6" + wire width 14 $1\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12370.3-12400.6" + wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12401.3-12431.6" + wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12339.3-12369.6" + wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12277.3-12307.6" + wire $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12494.3-12524.6" + wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12556.3-12586.6" + wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12308.3-12338.6" + wire $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12246.3-12276.6" + wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12525.3-12555.6" + wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:11998.7-11998.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:11998.7-11998.20" + process $proc$libresoc.v:11998$251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12184.3-12214.6" + process $proc$libresoc.v:12184$238 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_function_unit[13:0] $1\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12185.5-12185.29" + switch \initial + attribute \src "libresoc.v:12185.9-12185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[13:0] + end + attribute \src "libresoc.v:12215.3-12245.6" + process $proc$libresoc.v:12215$239 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12216.5-12216.29" + switch \initial + attribute \src "libresoc.v:12216.9-12216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:12246.3-12276.6" + process $proc$libresoc.v:12246$240 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12247.5-12247.29" + switch \initial + attribute \src "libresoc.v:12247.9-12247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:12277.3-12307.6" + process $proc$libresoc.v:12277$241 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12278.5-12278.29" + switch \initial + attribute \src "libresoc.v:12278.9-12278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:12308.3-12338.6" + process $proc$libresoc.v:12308$242 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12309.5-12309.29" + switch \initial + attribute \src "libresoc.v:12309.9-12309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:12339.3-12369.6" + process $proc$libresoc.v:12339$243 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12340.5-12340.29" + switch \initial + attribute \src "libresoc.v:12340.9-12340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:12370.3-12400.6" + process $proc$libresoc.v:12370$244 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12371.5-12371.29" + switch \initial + attribute \src "libresoc.v:12371.9-12371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:12401.3-12431.6" + process $proc$libresoc.v:12401$245 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12402.5-12402.29" + switch \initial + attribute \src "libresoc.v:12402.9-12402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:12432.3-12462.6" + process $proc$libresoc.v:12432$246 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12433.5-12433.29" + switch \initial + attribute \src "libresoc.v:12433.9-12433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:12463.3-12493.6" + process $proc$libresoc.v:12463$247 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12464.5-12464.29" + switch \initial + attribute \src "libresoc.v:12464.9-12464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + case + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:12494.3-12524.6" + process $proc$libresoc.v:12494$248 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12495.5-12495.29" + switch \initial + attribute \src "libresoc.v:12495.9-12495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:12525.3-12555.6" + process $proc$libresoc.v:12525$249 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:12526.5-12526.29" + switch \initial + attribute \src "libresoc.v:12526.9-12526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:12556.3-12586.6" + process $proc$libresoc.v:12556$250 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12557.5-12557.29" + switch \initial + attribute \src "libresoc.v:12557.9-12557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + case + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:12592.1-13417.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub23 + attribute \src "libresoc.v:12828.3-12876.6" + wire $0\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:13171.3-13219.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13220.3-13268.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12779.3-12827.6" + wire width 14 $0\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:13073.3-13121.6" + wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:13122.3-13170.6" + wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:13024.3-13072.6" + wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12926.3-12974.6" + wire $0\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13269.3-13317.6" + wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13367.3-13415.6" + wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12975.3-13023.6" + wire $0\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12877.3-12925.6" + wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13318.3-13366.6" + wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:12593.7-12593.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12828.3-12876.6" + wire $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:13171.3-13219.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13220.3-13268.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12779.3-12827.6" + wire width 14 $1\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:13073.3-13121.6" + wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:13122.3-13170.6" + wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:13024.3-13072.6" + wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12926.3-12974.6" + wire $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13269.3-13317.6" + wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13367.3-13415.6" + wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12975.3-13023.6" + wire $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12877.3-12925.6" + wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13318.3-13366.6" + wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec31_dec_sub23_upd + attribute \src "libresoc.v:12593.7-12593.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:12593.7-12593.20" + process $proc$libresoc.v:12593$265 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12779.3-12827.6" + process $proc$libresoc.v:12779$252 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_function_unit[13:0] $1\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:12780.5-12780.29" + switch \initial + attribute \src "libresoc.v:12780.9-12780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[13:0] + end + attribute \src "libresoc.v:12828.3-12876.6" + process $proc$libresoc.v:12828$253 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12829.5-12829.29" + switch \initial + attribute \src "libresoc.v:12829.9-12829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:12877.3-12925.6" + process $proc$libresoc.v:12877$254 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:12878.5-12878.29" + switch \initial + attribute \src "libresoc.v:12878.9-12878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:12926.3-12974.6" + process $proc$libresoc.v:12926$255 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:12927.5-12927.29" + switch \initial + attribute \src "libresoc.v:12927.9-12927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:12975.3-13023.6" + process $proc$libresoc.v:12975$256 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12976.5-12976.29" + switch \initial + attribute \src "libresoc.v:12976.9-12976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:13024.3-13072.6" + process $proc$libresoc.v:13024$257 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:13025.5-13025.29" + switch \initial + attribute \src "libresoc.v:13025.9-13025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:13073.3-13121.6" + process $proc$libresoc.v:13073$258 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:13074.5-13074.29" + switch \initial + attribute \src "libresoc.v:13074.9-13074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:13122.3-13170.6" + process $proc$libresoc.v:13122$259 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:13123.5-13123.29" + switch \initial + attribute \src "libresoc.v:13123.9-13123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:13171.3-13219.6" + process $proc$libresoc.v:13171$260 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13172.5-13172.29" + switch \initial + attribute \src "libresoc.v:13172.9-13172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:13220.3-13268.6" + process $proc$libresoc.v:13220$261 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:13221.5-13221.29" + switch \initial + attribute \src "libresoc.v:13221.9-13221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] + end + attribute \src "libresoc.v:13269.3-13317.6" + process $proc$libresoc.v:13269$262 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13270.5-13270.29" + switch \initial + attribute \src "libresoc.v:13270.9-13270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:13318.3-13366.6" + process $proc$libresoc.v:13318$263 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:13319.5-13319.29" + switch \initial + attribute \src "libresoc.v:13319.9-13319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:13367.3-13415.6" + process $proc$libresoc.v:13367$264 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:13368.5-13368.29" + switch \initial + attribute \src "libresoc.v:13368.9-13368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:13421.1-13817.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" +attribute \generator "nMigen" +module \LDST_dec58 + attribute \src "libresoc.v:13624.3-13639.6" + wire $0\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13736.3-13751.6" + wire width 3 $0\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13752.3-13767.6" + wire width 3 $0\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13608.3-13623.6" + wire width 14 $0\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13704.3-13719.6" + wire width 3 $0\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13720.3-13735.6" + wire width 4 $0\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13688.3-13703.6" + wire width 7 $0\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13656.3-13671.6" + wire $0\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13768.3-13783.6" + wire width 4 $0\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13800.3-13815.6" + wire width 2 $0\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13672.3-13687.6" + wire $0\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13640.3-13655.6" + wire $0\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13784.3-13799.6" + wire width 2 $0\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13422.7-13422.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13624.3-13639.6" + wire $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13736.3-13751.6" + wire width 3 $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13752.3-13767.6" + wire width 3 $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13608.3-13623.6" + wire width 14 $1\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13704.3-13719.6" + wire width 3 $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13720.3-13735.6" + wire width 4 $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13688.3-13703.6" + wire width 7 $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13656.3-13671.6" + wire $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13768.3-13783.6" + wire width 4 $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13800.3-13815.6" + wire width 2 $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13672.3-13687.6" + wire $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13640.3-13655.6" + wire $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13784.3-13799.6" + wire width 2 $1\LDST_dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec58_upd + attribute \src "libresoc.v:13422.7-13422.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13422.7-13422.20" + process $proc$libresoc.v:13422$279 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13608.3-13623.6" + process $proc$libresoc.v:13608$266 + assign { } { } + assign { } { } + assign $0\LDST_dec58_function_unit[13:0] $1\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13609.5-13609.29" + switch \initial + attribute \src "libresoc.v:13609.9-13609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[13:0] + end + attribute \src "libresoc.v:13624.3-13639.6" + process $proc$libresoc.v:13624$267 + assign { } { } + assign { } { } + assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13625.5-13625.29" + switch \initial + attribute \src "libresoc.v:13625.9-13625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + case + assign $1\LDST_dec58_br[0:0] 1'0 + end + sync always + update \LDST_dec58_br $0\LDST_dec58_br[0:0] + end + attribute \src "libresoc.v:13640.3-13655.6" + process $proc$libresoc.v:13640$268 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13641.5-13641.29" + switch \initial + attribute \src "libresoc.v:13641.9-13641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'1 + case + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:13656.3-13671.6" + process $proc$libresoc.v:13656$269 + assign { } { } + assign { } { } + assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13657.5-13657.29" + switch \initial + attribute \src "libresoc.v:13657.9-13657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + case + assign $1\LDST_dec58_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] + end + attribute \src "libresoc.v:13672.3-13687.6" + process $proc$libresoc.v:13672$270 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13673.5-13673.29" + switch \initial + attribute \src "libresoc.v:13673.9-13673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + case + assign $1\LDST_dec58_sgn[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] + end + attribute \src "libresoc.v:13688.3-13703.6" + process $proc$libresoc.v:13688$271 + assign { } { } + assign { } { } + assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13689.5-13689.29" + switch \initial + attribute \src "libresoc.v:13689.9-13689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + case + assign $1\LDST_dec58_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] + end + attribute \src "libresoc.v:13704.3-13719.6" + process $proc$libresoc.v:13704$272 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13705.5-13705.29" + switch \initial + attribute \src "libresoc.v:13705.9-13705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec58_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:13720.3-13735.6" + process $proc$libresoc.v:13720$273 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13721.5-13721.29" + switch \initial + attribute \src "libresoc.v:13721.9-13721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec58_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:13736.3-13751.6" + process $proc$libresoc.v:13736$274 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13737.5-13737.29" + switch \initial + attribute \src "libresoc.v:13737.9-13737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + case + assign $1\LDST_dec58_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] + end + attribute \src "libresoc.v:13752.3-13767.6" + process $proc$libresoc.v:13752$275 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13753.5-13753.29" + switch \initial + attribute \src "libresoc.v:13753.9-13753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + case + assign $1\LDST_dec58_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] + end + attribute \src "libresoc.v:13768.3-13783.6" + process $proc$libresoc.v:13768$276 + assign { } { } + assign { } { } + assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13769.5-13769.29" + switch \initial + attribute \src "libresoc.v:13769.9-13769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec58_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:13784.3-13799.6" + process $proc$libresoc.v:13784$277 + assign { } { } + assign { } { } + assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13785.5-13785.29" + switch \initial + attribute \src "libresoc.v:13785.9-13785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + case + assign $1\LDST_dec58_upd[1:0] 2'00 + end + sync always + update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] + end + attribute \src "libresoc.v:13800.3-13815.6" + process $proc$libresoc.v:13800$278 + assign { } { } + assign { } { } + assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13801.5-13801.29" + switch \initial + attribute \src "libresoc.v:13801.9-13801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:13821.1-14178.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" +attribute \generator "nMigen" +module \LDST_dec62 + attribute \src "libresoc.v:14021.3-14033.6" + wire $0\LDST_dec62_br[0:0] + attribute \src "libresoc.v:14112.3-14124.6" + wire width 3 $0\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:14125.3-14137.6" + wire width 3 $0\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:14008.3-14020.6" + wire width 14 $0\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14086.3-14098.6" + wire width 3 $0\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:14099.3-14111.6" + wire width 4 $0\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:14073.3-14085.6" + wire width 7 $0\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:14047.3-14059.6" + wire $0\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:14138.3-14150.6" + wire width 4 $0\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:14164.3-14176.6" + wire width 2 $0\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:14060.3-14072.6" + wire $0\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:14034.3-14046.6" + wire $0\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:14151.3-14163.6" + wire width 2 $0\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:13822.7-13822.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:14021.3-14033.6" + wire $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:14112.3-14124.6" + wire width 3 $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:14125.3-14137.6" + wire width 3 $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:14008.3-14020.6" + wire width 14 $1\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14086.3-14098.6" + wire width 3 $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:14099.3-14111.6" + wire width 4 $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:14073.3-14085.6" + wire width 7 $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:14047.3-14059.6" + wire $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:14138.3-14150.6" + wire width 4 $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:14164.3-14176.6" + wire width 2 $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:14060.3-14072.6" + wire $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:14034.3-14046.6" + wire $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:14151.3-14163.6" + wire width 2 $1\LDST_dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LDST_dec62_upd + attribute \src "libresoc.v:13822.7-13822.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13822.7-13822.20" + process $proc$libresoc.v:13822$293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14008.3-14020.6" + process $proc$libresoc.v:14008$280 + assign { } { } + assign { } { } + assign $0\LDST_dec62_function_unit[13:0] $1\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14009.5-14009.29" + switch \initial + attribute \src "libresoc.v:14009.9-14009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[13:0] + end + attribute \src "libresoc.v:14021.3-14033.6" + process $proc$libresoc.v:14021$281 + assign { } { } + assign { } { } + assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:14022.5-14022.29" + switch \initial + attribute \src "libresoc.v:14022.9-14022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + case + assign $1\LDST_dec62_br[0:0] 1'0 + end + sync always + update \LDST_dec62_br $0\LDST_dec62_br[0:0] + end + attribute \src "libresoc.v:14034.3-14046.6" + process $proc$libresoc.v:14034$282 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:14035.5-14035.29" + switch \initial + attribute \src "libresoc.v:14035.9-14035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:14047.3-14059.6" + process $proc$libresoc.v:14047$283 + assign { } { } + assign { } { } + assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:14048.5-14048.29" + switch \initial + attribute \src "libresoc.v:14048.9-14048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + case + assign $1\LDST_dec62_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] + end + attribute \src "libresoc.v:14060.3-14072.6" + process $proc$libresoc.v:14060$284 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:14061.5-14061.29" + switch \initial + attribute \src "libresoc.v:14061.9-14061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + case + assign $1\LDST_dec62_sgn[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] + end + attribute \src "libresoc.v:14073.3-14085.6" + process $proc$libresoc.v:14073$285 + assign { } { } + assign { } { } + assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:14074.5-14074.29" + switch \initial + attribute \src "libresoc.v:14074.9-14074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec62_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] + end + attribute \src "libresoc.v:14086.3-14098.6" + process $proc$libresoc.v:14086$286 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:14087.5-14087.29" + switch \initial + attribute \src "libresoc.v:14087.9-14087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec62_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:14099.3-14111.6" + process $proc$libresoc.v:14099$287 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:14100.5-14100.29" + switch \initial + attribute \src "libresoc.v:14100.9-14100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec62_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:14112.3-14124.6" + process $proc$libresoc.v:14112$288 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:14113.5-14113.29" + switch \initial + attribute \src "libresoc.v:14113.9-14113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + case + assign $1\LDST_dec62_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] + end + attribute \src "libresoc.v:14125.3-14137.6" + process $proc$libresoc.v:14125$289 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:14126.5-14126.29" + switch \initial + attribute \src "libresoc.v:14126.9-14126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + case + assign $1\LDST_dec62_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] + end + attribute \src "libresoc.v:14138.3-14150.6" + process $proc$libresoc.v:14138$290 + assign { } { } + assign { } { } + assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:14139.5-14139.29" + switch \initial + attribute \src "libresoc.v:14139.9-14139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec62_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:14151.3-14163.6" + process $proc$libresoc.v:14151$291 + assign { } { } + assign { } { } + assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:14152.5-14152.29" + switch \initial + attribute \src "libresoc.v:14152.9-14152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'01 + case + assign $1\LDST_dec62_upd[1:0] 2'00 + end + sync always + update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] + end + attribute \src "libresoc.v:14164.3-14176.6" + process $proc$libresoc.v:14164$292 + assign { } { } + assign { } { } + assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:14165.5-14165.29" + switch \initial + attribute \src "libresoc.v:14165.9-14165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:14182.1-14935.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \generator "nMigen" +module \LOGICAL_dec31 + attribute \src "libresoc.v:14905.3-14917.6" + wire width 3 $0\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14918.3-14930.6" + wire width 3 $0\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14775.3-14787.6" + wire width 2 $0\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14814.3-14826.6" + wire $0\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14853.3-14865.6" + wire width 14 $0\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14879.3-14891.6" + wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14892.3-14904.6" + wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14866.3-14878.6" + wire width 7 $0\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14788.3-14800.6" + wire $0\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14801.3-14813.6" + wire $0\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14827.3-14839.6" + wire $0\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14749.3-14761.6" + wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14762.3-14774.6" + wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14840.3-14852.6" + wire $0\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:14183.7-14183.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:14905.3-14917.6" + wire width 3 $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14918.3-14930.6" + wire width 3 $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14775.3-14787.6" + wire width 2 $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14814.3-14826.6" + wire $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14853.3-14865.6" + wire width 14 $1\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14879.3-14891.6" + wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14892.3-14904.6" + wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14866.3-14878.6" + wire width 7 $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14788.3-14800.6" + wire $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14801.3-14813.6" + wire $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14827.3-14839.6" + wire $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14749.3-14761.6" + wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14762.3-14774.6" + wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14840.3-14852.6" + wire $1\LOGICAL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LOGICAL_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \LOGICAL_dec31_sgn + attribute \src "libresoc.v:14183.7-14183.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:14715.27-14731.4" + cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 + connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:14732.27-14748.4" + cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 + connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in + end + attribute \src "libresoc.v:14183.7-14183.20" + process $proc$libresoc.v:14183$308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14749.3-14761.6" + process $proc$libresoc.v:14749$294 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14750.5-14750.29" + switch \initial + attribute \src "libresoc.v:14750.9-14750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + case + assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:14762.3-14774.6" + process $proc$libresoc.v:14762$295 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14763.5-14763.29" + switch \initial + attribute \src "libresoc.v:14763.9-14763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + case + assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:14775.3-14787.6" + process $proc$libresoc.v:14775$296 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14776.5-14776.29" + switch \initial + attribute \src "libresoc.v:14776.9-14776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + case + assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:14788.3-14800.6" + process $proc$libresoc.v:14788$297 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14789.5-14789.29" + switch \initial + attribute \src "libresoc.v:14789.9-14789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + case + assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:14801.3-14813.6" + process $proc$libresoc.v:14801$298 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14802.5-14802.29" + switch \initial + attribute \src "libresoc.v:14802.9-14802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + case + assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:14814.3-14826.6" + process $proc$libresoc.v:14814$299 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14815.5-14815.29" + switch \initial + attribute \src "libresoc.v:14815.9-14815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + case + assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:14827.3-14839.6" + process $proc$libresoc.v:14827$300 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14828.5-14828.29" + switch \initial + attribute \src "libresoc.v:14828.9-14828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + case + assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:14840.3-14852.6" + process $proc$libresoc.v:14840$301 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:14841.5-14841.29" + switch \initial + attribute \src "libresoc.v:14841.9-14841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + case + assign $1\LOGICAL_dec31_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:14853.3-14865.6" + process $proc$libresoc.v:14853$302 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_function_unit[13:0] $1\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14854.5-14854.29" + switch \initial + attribute \src "libresoc.v:14854.9-14854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + case + assign $1\LOGICAL_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:14866.3-14878.6" + process $proc$libresoc.v:14866$303 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14867.5-14867.29" + switch \initial + attribute \src "libresoc.v:14867.9-14867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + case + assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:14879.3-14891.6" + process $proc$libresoc.v:14879$304 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14880.5-14880.29" + switch \initial + attribute \src "libresoc.v:14880.9-14880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + case + assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:14892.3-14904.6" + process $proc$libresoc.v:14892$305 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14893.5-14893.29" + switch \initial + attribute \src "libresoc.v:14893.9-14893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + case + assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:14905.3-14917.6" + process $proc$libresoc.v:14905$306 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14906.5-14906.29" + switch \initial + attribute \src "libresoc.v:14906.9-14906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + case + assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:14918.3-14930.6" + process $proc$libresoc.v:14918$307 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14919.5-14919.29" + switch \initial + attribute \src "libresoc.v:14919.9-14919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + case + assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] + end + connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in + connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:14939.1-15605.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub26 + attribute \src "libresoc.v:15434.3-15467.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15468.3-15501.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15570.3-15603.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15230.3-15263.6" + wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15128.3-15161.6" + wire width 14 $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15366.3-15399.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15400.3-15433.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15332.3-15365.6" + wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15162.3-15195.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:15196.3-15229.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15264.3-15297.6" + wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15502.3-15535.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15536.3-15569.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15298.3-15331.6" + wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:14940.7-14940.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:15434.3-15467.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15468.3-15501.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15570.3-15603.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15230.3-15263.6" + wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15128.3-15161.6" + wire width 14 $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15366.3-15399.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15400.3-15433.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15332.3-15365.6" + wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15162.3-15195.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:15196.3-15229.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15264.3-15297.6" + wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15502.3-15535.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15536.3-15569.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15298.3-15331.6" + wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \LOGICAL_dec31_dec_sub26_sgn + attribute \src "libresoc.v:14940.7-14940.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:14940.7-14940.20" + process $proc$libresoc.v:14940$323 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:15128.3-15161.6" + process $proc$libresoc.v:15128$309 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15129.5-15129.29" + switch \initial + attribute \src "libresoc.v:15129.9-15129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + case + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] + end + attribute \src "libresoc.v:15162.3-15195.6" + process $proc$libresoc.v:15162$310 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:15163.5-15163.29" + switch \initial + attribute \src "libresoc.v:15163.9-15163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:15196.3-15229.6" + process $proc$libresoc.v:15196$311 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15197.5-15197.29" + switch \initial + attribute \src "libresoc.v:15197.9-15197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:15230.3-15263.6" + process $proc$libresoc.v:15230$312 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15231.5-15231.29" + switch \initial + attribute \src "libresoc.v:15231.9-15231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:15264.3-15297.6" + process $proc$libresoc.v:15264$313 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15265.5-15265.29" + switch \initial + attribute \src "libresoc.v:15265.9-15265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:15298.3-15331.6" + process $proc$libresoc.v:15298$314 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:15299.5-15299.29" + switch \initial + attribute \src "libresoc.v:15299.9-15299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:15332.3-15365.6" + process $proc$libresoc.v:15332$315 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15333.5-15333.29" + switch \initial + attribute \src "libresoc.v:15333.9-15333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + case + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:15366.3-15399.6" + process $proc$libresoc.v:15366$316 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15367.5-15367.29" + switch \initial + attribute \src "libresoc.v:15367.9-15367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:15400.3-15433.6" + process $proc$libresoc.v:15400$317 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15401.5-15401.29" + switch \initial + attribute \src "libresoc.v:15401.9-15401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:15434.3-15467.6" + process $proc$libresoc.v:15434$318 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15435.5-15435.29" + switch \initial + attribute \src "libresoc.v:15435.9-15435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:15468.3-15501.6" + process $proc$libresoc.v:15468$319 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15469.5-15469.29" + switch \initial + attribute \src "libresoc.v:15469.9-15469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:15502.3-15535.6" + process $proc$libresoc.v:15502$320 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15503.5-15503.29" + switch \initial + attribute \src "libresoc.v:15503.9-15503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:15536.3-15569.6" + process $proc$libresoc.v:15536$321 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15537.5-15537.29" + switch \initial + attribute \src "libresoc.v:15537.9-15537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:15570.3-15603.6" + process $proc$libresoc.v:15570$322 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15571.5-15571.29" + switch \initial + attribute \src "libresoc.v:15571.9-15571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:15609.1-16317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub28 + attribute \src "libresoc.v:16131.3-16167.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:16168.3-16204.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16279.3-16315.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15909.3-15945.6" + wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15798.3-15834.6" + wire width 14 $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:16057.3-16093.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:16094.3-16130.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:16020.3-16056.6" + wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15835.3-15871.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15872.3-15908.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15946.3-15982.6" + wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:16205.3-16241.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16242.3-16278.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15983.3-16019.6" + wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15610.7-15610.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16131.3-16167.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:16168.3-16204.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16279.3-16315.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15909.3-15945.6" + wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15798.3-15834.6" + wire width 14 $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:16057.3-16093.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:16094.3-16130.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:16020.3-16056.6" + wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15835.3-15871.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15872.3-15908.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15946.3-15982.6" + wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:16205.3-16241.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16242.3-16278.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15983.3-16019.6" + wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:15610.7-15610.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:15610.7-15610.20" + process $proc$libresoc.v:15610$338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:15798.3-15834.6" + process $proc$libresoc.v:15798$324 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:15799.5-15799.29" + switch \initial + attribute \src "libresoc.v:15799.9-15799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + case + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] + end + attribute \src "libresoc.v:15835.3-15871.6" + process $proc$libresoc.v:15835$325 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15836.5-15836.29" + switch \initial + attribute \src "libresoc.v:15836.9-15836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:15872.3-15908.6" + process $proc$libresoc.v:15872$326 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15873.5-15873.29" + switch \initial + attribute \src "libresoc.v:15873.9-15873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:15909.3-15945.6" + process $proc$libresoc.v:15909$327 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15910.5-15910.29" + switch \initial + attribute \src "libresoc.v:15910.9-15910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:15946.3-15982.6" + process $proc$libresoc.v:15946$328 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15947.5-15947.29" + switch \initial + attribute \src "libresoc.v:15947.9-15947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:15983.3-16019.6" + process $proc$libresoc.v:15983$329 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15984.5-15984.29" + switch \initial + attribute \src "libresoc.v:15984.9-15984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:16020.3-16056.6" + process $proc$libresoc.v:16020$330 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:16021.5-16021.29" + switch \initial + attribute \src "libresoc.v:16021.9-16021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:16057.3-16093.6" + process $proc$libresoc.v:16057$331 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:16058.5-16058.29" + switch \initial + attribute \src "libresoc.v:16058.9-16058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:16094.3-16130.6" + process $proc$libresoc.v:16094$332 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:16095.5-16095.29" + switch \initial + attribute \src "libresoc.v:16095.9-16095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:16131.3-16167.6" + process $proc$libresoc.v:16131$333 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:16132.5-16132.29" + switch \initial + attribute \src "libresoc.v:16132.9-16132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:16168.3-16204.6" + process $proc$libresoc.v:16168$334 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16169.5-16169.29" + switch \initial + attribute \src "libresoc.v:16169.9-16169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:16205.3-16241.6" + process $proc$libresoc.v:16205$335 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16206.5-16206.29" + switch \initial + attribute \src "libresoc.v:16206.9-16206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:16242.3-16278.6" + process $proc$libresoc.v:16242$336 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:16243.5-16243.29" + switch \initial + attribute \src "libresoc.v:16243.9-16243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:16279.3-16315.6" + process $proc$libresoc.v:16279$337 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:16280.5-16280.29" + switch \initial + attribute \src "libresoc.v:16280.9-16280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:16321.1-16894.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" +attribute \generator "nMigen" +module \MUL_dec31 + attribute \src "libresoc.v:16851.3-16863.6" + wire width 3 $0\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16864.3-16876.6" + wire width 3 $0\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16812.3-16824.6" + wire width 14 $0\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16838.3-16850.6" + wire width 4 $0\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16825.3-16837.6" + wire width 7 $0\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16786.3-16798.6" + wire $0\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16877.3-16889.6" + wire width 2 $0\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16799.3-16811.6" + wire $0\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16322.7-16322.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16851.3-16863.6" + wire width 3 $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16864.3-16876.6" + wire width 3 $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16812.3-16824.6" + wire width 14 $1\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16838.3-16850.6" + wire width 4 $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16825.3-16837.6" + wire width 7 $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16786.3-16798.6" + wire $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16877.3-16889.6" + wire width 2 $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16799.3-16811.6" + wire $1\MUL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \MUL_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \MUL_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \MUL_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 7 \MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \MUL_dec31_sgn + attribute \src "libresoc.v:16322.7-16322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16764.23-16774.4" + cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 + connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + connect \opcode_in \MUL_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16775.22-16785.4" + cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 + connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + connect \opcode_in \MUL_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:16322.7-16322.20" + process $proc$libresoc.v:16322$347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16786.3-16798.6" + process $proc$libresoc.v:16786$339 + assign { } { } + assign { } { } + assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16787.5-16787.29" + switch \initial + attribute \src "libresoc.v:16787.9-16787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + case + assign $1\MUL_dec31_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:16799.3-16811.6" + process $proc$libresoc.v:16799$340 + assign { } { } + assign { } { } + assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16800.5-16800.29" + switch \initial + attribute \src "libresoc.v:16800.9-16800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + case + assign $1\MUL_dec31_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:16812.3-16824.6" + process $proc$libresoc.v:16812$341 + assign { } { } + assign { } { } + assign $0\MUL_dec31_function_unit[13:0] $1\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16813.5-16813.29" + switch \initial + attribute \src "libresoc.v:16813.9-16813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + case + assign $1\MUL_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:16825.3-16837.6" + process $proc$libresoc.v:16825$342 + assign { } { } + assign { } { } + assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16826.5-16826.29" + switch \initial + attribute \src "libresoc.v:16826.9-16826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + case + assign $1\MUL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:16838.3-16850.6" + process $proc$libresoc.v:16838$343 + assign { } { } + assign { } { } + assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16839.5-16839.29" + switch \initial + attribute \src "libresoc.v:16839.9-16839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + case + assign $1\MUL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:16851.3-16863.6" + process $proc$libresoc.v:16851$344 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16852.5-16852.29" + switch \initial + attribute \src "libresoc.v:16852.9-16852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + case + assign $1\MUL_dec31_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:16864.3-16876.6" + process $proc$libresoc.v:16864$345 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16865.5-16865.29" + switch \initial + attribute \src "libresoc.v:16865.9-16865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + case + assign $1\MUL_dec31_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:16877.3-16889.6" + process $proc$libresoc.v:16877$346 + assign { } { } + assign { } { } + assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16878.5-16878.29" + switch \initial + attribute \src "libresoc.v:16878.9-16878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + case + assign $1\MUL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] + end + connect \MUL_dec31_dec_sub11_opcode_in \opcode_in + connect \MUL_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:16898.1-17254.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub11 + attribute \src "libresoc.v:17128.3-17152.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:17153.3-17177.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:17053.3-17077.6" + wire width 14 $0\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17103.3-17127.6" + wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:17078.3-17102.6" + wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:17203.3-17227.6" + wire $0\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:17178.3-17202.6" + wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:17228.3-17252.6" + wire $0\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:16899.7-16899.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17128.3-17152.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:17153.3-17177.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:17053.3-17077.6" + wire width 14 $1\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17103.3-17127.6" + wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:17078.3-17102.6" + wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:17203.3-17227.6" + wire $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:17178.3-17202.6" + wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:17228.3-17252.6" + wire $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 7 \MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \MUL_dec31_dec_sub11_sgn + attribute \src "libresoc.v:16899.7-16899.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:16899.7-16899.20" + process $proc$libresoc.v:16899$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17053.3-17077.6" + process $proc$libresoc.v:17053$348 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_function_unit[13:0] $1\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17054.5-17054.29" + switch \initial + attribute \src "libresoc.v:17054.9-17054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + case + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 + end + sync always + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[13:0] + end + attribute \src "libresoc.v:17078.3-17102.6" + process $proc$libresoc.v:17078$349 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:17079.5-17079.29" + switch \initial + attribute \src "libresoc.v:17079.9-17079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:17103.3-17127.6" + process $proc$libresoc.v:17103$350 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:17104.5-17104.29" + switch \initial + attribute \src "libresoc.v:17104.9-17104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:17128.3-17152.6" + process $proc$libresoc.v:17128$351 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:17129.5-17129.29" + switch \initial + attribute \src "libresoc.v:17129.9-17129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:17153.3-17177.6" + process $proc$libresoc.v:17153$352 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:17154.5-17154.29" + switch \initial + attribute \src "libresoc.v:17154.9-17154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:17178.3-17202.6" + process $proc$libresoc.v:17178$353 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:17179.5-17179.29" + switch \initial + attribute \src "libresoc.v:17179.9-17179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:17203.3-17227.6" + process $proc$libresoc.v:17203$354 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:17204.5-17204.29" + switch \initial + attribute \src "libresoc.v:17204.9-17204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:17228.3-17252.6" + process $proc$libresoc.v:17228$355 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:17229.5-17229.29" + switch \initial + attribute \src "libresoc.v:17229.9-17229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17258.1-17614.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub9 + attribute \src "libresoc.v:17488.3-17512.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17513.3-17537.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17413.3-17437.6" + wire width 14 $0\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17463.3-17487.6" + wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17438.3-17462.6" + wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17563.3-17587.6" + wire $0\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17538.3-17562.6" + wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17588.3-17612.6" + wire $0\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17259.7-17259.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17488.3-17512.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17513.3-17537.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17413.3-17437.6" + wire width 14 $1\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17463.3-17487.6" + wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17438.3-17462.6" + wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17563.3-17587.6" + wire $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17538.3-17562.6" + wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17588.3-17612.6" + wire $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 7 \MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:17259.7-17259.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:17259.7-17259.20" + process $proc$libresoc.v:17259$365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17413.3-17437.6" + process $proc$libresoc.v:17413$357 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_function_unit[13:0] $1\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17414.5-17414.29" + switch \initial + attribute \src "libresoc.v:17414.9-17414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + case + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 + end + sync always + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[13:0] + end + attribute \src "libresoc.v:17438.3-17462.6" + process $proc$libresoc.v:17438$358 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17439.5-17439.29" + switch \initial + attribute \src "libresoc.v:17439.9-17439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:17463.3-17487.6" + process $proc$libresoc.v:17463$359 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17464.5-17464.29" + switch \initial + attribute \src "libresoc.v:17464.9-17464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:17488.3-17512.6" + process $proc$libresoc.v:17488$360 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17489.5-17489.29" + switch \initial + attribute \src "libresoc.v:17489.9-17489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:17513.3-17537.6" + process $proc$libresoc.v:17513$361 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17514.5-17514.29" + switch \initial + attribute \src "libresoc.v:17514.9-17514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:17538.3-17562.6" + process $proc$libresoc.v:17538$362 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17539.5-17539.29" + switch \initial + attribute \src "libresoc.v:17539.9-17539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:17563.3-17587.6" + process $proc$libresoc.v:17563$363 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17564.5-17564.29" + switch \initial + attribute \src "libresoc.v:17564.9-17564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:17588.3-17612.6" + process $proc$libresoc.v:17588$364 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17589.5-17589.29" + switch \initial + attribute \src "libresoc.v:17589.9-17589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17618.1-18194.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +attribute \generator "nMigen" +module \SHIFT_ROT_dec30 + attribute \src "libresoc.v:17971.3-18007.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:18008.3-18044.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:18082.3-18118.6" + wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:18156.3-18192.6" + wire $0\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17786.3-17822.6" + wire width 14 $0\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17934.3-17970.6" + wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17897.3-17933.6" + wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:18119.3-18155.6" + wire $0\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17823.3-17859.6" + wire $0\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:18045.3-18081.6" + wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17860.3-17896.6" + wire $0\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17619.7-17619.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17971.3-18007.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:18008.3-18044.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:18082.3-18118.6" + wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:18156.3-18192.6" + wire $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17786.3-17822.6" + wire width 14 $1\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17934.3-17970.6" + wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17897.3-17933.6" + wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:18119.3-18155.6" + wire $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17823.3-17859.6" + wire $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:18045.3-18081.6" + wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17860.3-17896.6" + wire $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 7 \SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 9 \SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:17619.7-17619.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 4 \opcode_switch + attribute \src "libresoc.v:17619.7-17619.20" + process $proc$libresoc.v:17619$377 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17786.3-17822.6" + process $proc$libresoc.v:17786$366 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_function_unit[13:0] $1\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17787.5-17787.29" + switch \initial + attribute \src "libresoc.v:17787.9-17787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 + case + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000000000 + end + sync always + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[13:0] + end + attribute \src "libresoc.v:17823.3-17859.6" + process $proc$libresoc.v:17823$367 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17824.5-17824.29" + switch \initial + attribute \src "libresoc.v:17824.9-17824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + end + attribute \src "libresoc.v:17860.3-17896.6" + process $proc$libresoc.v:17860$368 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17861.5-17861.29" + switch \initial + attribute \src "libresoc.v:17861.9-17861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] + end + attribute \src "libresoc.v:17897.3-17933.6" + process $proc$libresoc.v:17897$369 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17898.5-17898.29" + switch \initial + attribute \src "libresoc.v:17898.9-17898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + case + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] + end + attribute \src "libresoc.v:17934.3-17970.6" + process $proc$libresoc.v:17934$370 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17935.5-17935.29" + switch \initial + attribute \src "libresoc.v:17935.9-17935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:17971.3-18007.6" + process $proc$libresoc.v:17971$371 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17972.5-17972.29" + switch \initial + attribute \src "libresoc.v:17972.9-17972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] + end + attribute \src "libresoc.v:18008.3-18044.6" + process $proc$libresoc.v:18008$372 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:18009.5-18009.29" + switch \initial + attribute \src "libresoc.v:18009.9-18009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] + end + attribute \src "libresoc.v:18045.3-18081.6" + process $proc$libresoc.v:18045$373 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:18046.5-18046.29" + switch \initial + attribute \src "libresoc.v:18046.9-18046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:18082.3-18118.6" + process $proc$libresoc.v:18082$374 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:18083.5-18083.29" + switch \initial + attribute \src "libresoc.v:18083.9-18083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] + end + attribute \src "libresoc.v:18119.3-18155.6" + process $proc$libresoc.v:18119$375 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:18120.5-18120.29" + switch \initial + attribute \src "libresoc.v:18120.9-18120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] + end + attribute \src "libresoc.v:18156.3-18192.6" + process $proc$libresoc.v:18156$376 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:18157.5-18157.29" + switch \initial + attribute \src "libresoc.v:18157.9-18157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:18198.1-19050.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31 + attribute \src "libresoc.v:19013.3-19028.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:19029.3-19044.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18885.3-18900.6" + wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18917.3-18932.6" + wire $0\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18965.3-18980.6" + wire width 14 $0\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18997.3-19012.6" + wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18981.3-18996.6" + wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18901.3-18916.6" + wire $0\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18933.3-18948.6" + wire $0\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18869.3-18884.6" + wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18949.3-18964.6" + wire $0\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:18199.7-18199.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19013.3-19028.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:19029.3-19044.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18885.3-18900.6" + wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18917.3-18932.6" + wire $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18965.3-18980.6" + wire width 14 $1\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18997.3-19012.6" + wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18981.3-18996.6" + wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18901.3-18916.6" + wire $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18933.3-18948.6" + wire $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18869.3-18884.6" + wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18949.3-18964.6" + wire $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 7 \SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 9 \SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:18199.7-18199.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:18827.29-18840.4" + cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 + connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + connect \SHIFT_ROT_dec31_dec_sub24_inv_a \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18841.29-18854.4" + cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 + connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + connect \SHIFT_ROT_dec31_dec_sub26_inv_a \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18855.29-18868.4" + cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 + connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + connect \SHIFT_ROT_dec31_dec_sub27_inv_a \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in + end + attribute \src "libresoc.v:18199.7-18199.20" + process $proc$libresoc.v:18199$389 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18869.3-18884.6" + process $proc$libresoc.v:18869$378 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18870.5-18870.29" + switch \initial + attribute \src "libresoc.v:18870.9-18870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + case + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:18885.3-18900.6" + process $proc$libresoc.v:18885$379 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18886.5-18886.29" + switch \initial + attribute \src "libresoc.v:18886.9-18886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + case + assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:18901.3-18916.6" + process $proc$libresoc.v:18901$380 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18902.5-18902.29" + switch \initial + attribute \src "libresoc.v:18902.9-18902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + case + assign $1\SHIFT_ROT_dec31_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:18917.3-18932.6" + process $proc$libresoc.v:18917$381 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18918.5-18918.29" + switch \initial + attribute \src "libresoc.v:18918.9-18918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + case + assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:18933.3-18948.6" + process $proc$libresoc.v:18933$382 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18934.5-18934.29" + switch \initial + attribute \src "libresoc.v:18934.9-18934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + case + assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:18949.3-18964.6" + process $proc$libresoc.v:18949$383 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:18950.5-18950.29" + switch \initial + attribute \src "libresoc.v:18950.9-18950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + case + assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] + end + attribute \src "libresoc.v:18965.3-18980.6" + process $proc$libresoc.v:18965$384 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_function_unit[13:0] $1\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18966.5-18966.29" + switch \initial + attribute \src "libresoc.v:18966.9-18966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + case + assign $1\SHIFT_ROT_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:18981.3-18996.6" + process $proc$libresoc.v:18981$385 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18982.5-18982.29" + switch \initial + attribute \src "libresoc.v:18982.9-18982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + case + assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:18997.3-19012.6" + process $proc$libresoc.v:18997$386 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18998.5-18998.29" + switch \initial + attribute \src "libresoc.v:18998.9-18998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + case + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:19013.3-19028.6" + process $proc$libresoc.v:19013$387 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:19014.5-19014.29" + switch \initial + attribute \src "libresoc.v:19014.9-19014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + case + assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:19029.3-19044.6" + process $proc$libresoc.v:19029$388 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:19030.5-19030.29" + switch \initial + attribute \src "libresoc.v:19030.9-19030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + case + assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] + end + connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:19054.1-19432.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub24 + attribute \src "libresoc.v:19317.3-19335.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19336.3-19354.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19374.3-19392.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19412.3-19430.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19222.3-19240.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19298.3-19316.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19279.3-19297.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19393.3-19411.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19241.3-19259.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19355.3-19373.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19260.3-19278.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:19055.7-19055.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19317.3-19335.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19336.3-19354.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19374.3-19392.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19412.3-19430.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19222.3-19240.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19298.3-19316.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19279.3-19297.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19393.3-19411.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19241.3-19259.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19355.3-19373.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19260.3-19278.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "libresoc.v:19055.7-19055.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19055.7-19055.20" + process $proc$libresoc.v:19055$401 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19222.3-19240.6" + process $proc$libresoc.v:19222$390 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19223.5-19223.29" + switch \initial + attribute \src "libresoc.v:19223.9-19223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + end + attribute \src "libresoc.v:19241.3-19259.6" + process $proc$libresoc.v:19241$391 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19242.5-19242.29" + switch \initial + attribute \src "libresoc.v:19242.9-19242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:19260.3-19278.6" + process $proc$libresoc.v:19260$392 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:19261.5-19261.29" + switch \initial + attribute \src "libresoc.v:19261.9-19261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:19279.3-19297.6" + process $proc$libresoc.v:19279$393 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19280.5-19280.29" + switch \initial + attribute \src "libresoc.v:19280.9-19280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:19298.3-19316.6" + process $proc$libresoc.v:19298$394 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19299.5-19299.29" + switch \initial + attribute \src "libresoc.v:19299.9-19299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:19317.3-19335.6" + process $proc$libresoc.v:19317$395 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19318.5-19318.29" + switch \initial + attribute \src "libresoc.v:19318.9-19318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:19336.3-19354.6" + process $proc$libresoc.v:19336$396 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19337.5-19337.29" + switch \initial + attribute \src "libresoc.v:19337.9-19337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + end + attribute \src "libresoc.v:19355.3-19373.6" + process $proc$libresoc.v:19355$397 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19356.5-19356.29" + switch \initial + attribute \src "libresoc.v:19356.9-19356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:19374.3-19392.6" + process $proc$libresoc.v:19374$398 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19375.5-19375.29" + switch \initial + attribute \src "libresoc.v:19375.9-19375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:19393.3-19411.6" + process $proc$libresoc.v:19393$399 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19394.5-19394.29" + switch \initial + attribute \src "libresoc.v:19394.9-19394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:19412.3-19430.6" + process $proc$libresoc.v:19412$400 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19413.5-19413.29" + switch \initial + attribute \src "libresoc.v:19413.9-19413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19436.1-19781.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub26 + attribute \src "libresoc.v:19684.3-19699.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19700.3-19715.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19732.3-19747.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19764.3-19779.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19604.3-19619.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19668.3-19683.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19652.3-19667.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19748.3-19763.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19620.3-19635.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19716.3-19731.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19636.3-19651.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19437.7-19437.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19684.3-19699.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19700.3-19715.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19732.3-19747.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19764.3-19779.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19604.3-19619.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19668.3-19683.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19652.3-19667.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19748.3-19763.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19620.3-19635.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19716.3-19731.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19636.3-19651.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:19437.7-19437.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19437.7-19437.20" + process $proc$libresoc.v:19437$413 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19604.3-19619.6" + process $proc$libresoc.v:19604$402 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19605.5-19605.29" + switch \initial + attribute \src "libresoc.v:19605.9-19605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + end + attribute \src "libresoc.v:19620.3-19635.6" + process $proc$libresoc.v:19620$403 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19621.5-19621.29" + switch \initial + attribute \src "libresoc.v:19621.9-19621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:19636.3-19651.6" + process $proc$libresoc.v:19636$404 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19637.5-19637.29" + switch \initial + attribute \src "libresoc.v:19637.9-19637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:19652.3-19667.6" + process $proc$libresoc.v:19652$405 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19653.5-19653.29" + switch \initial + attribute \src "libresoc.v:19653.9-19653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:19668.3-19683.6" + process $proc$libresoc.v:19668$406 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19669.5-19669.29" + switch \initial + attribute \src "libresoc.v:19669.9-19669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:19684.3-19699.6" + process $proc$libresoc.v:19684$407 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19685.5-19685.29" + switch \initial + attribute \src "libresoc.v:19685.9-19685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:19700.3-19715.6" + process $proc$libresoc.v:19700$408 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19701.5-19701.29" + switch \initial + attribute \src "libresoc.v:19701.9-19701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:19716.3-19731.6" + process $proc$libresoc.v:19716$409 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19717.5-19717.29" + switch \initial + attribute \src "libresoc.v:19717.9-19717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:19732.3-19747.6" + process $proc$libresoc.v:19732$410 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19733.5-19733.29" + switch \initial + attribute \src "libresoc.v:19733.9-19733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:19748.3-19763.6" + process $proc$libresoc.v:19748$411 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19749.5-19749.29" + switch \initial + attribute \src "libresoc.v:19749.9-19749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:19764.3-19779.6" + process $proc$libresoc.v:19764$412 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19765.5-19765.29" + switch \initial + attribute \src "libresoc.v:19765.9-19765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19785.1-20163.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub27 + attribute \src "libresoc.v:20048.3-20066.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:20067.3-20085.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:20105.3-20123.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:20143.3-20161.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19953.3-19971.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:20029.3-20047.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:20010.3-20028.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20124.3-20142.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19972.3-19990.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:20086.3-20104.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19991.3-20009.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19786.7-19786.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20048.3-20066.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:20067.3-20085.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:20105.3-20123.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:20143.3-20161.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19953.3-19971.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:20029.3-20047.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:20010.3-20028.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20124.3-20142.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19972.3-19990.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:20086.3-20104.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19991.3-20009.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:19786.7-19786.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19786.7-19786.20" + process $proc$libresoc.v:19786$425 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19953.3-19971.6" + process $proc$libresoc.v:19953$414 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:19954.5-19954.29" + switch \initial + attribute \src "libresoc.v:19954.9-19954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + end + attribute \src "libresoc.v:19972.3-19990.6" + process $proc$libresoc.v:19972$415 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19973.5-19973.29" + switch \initial + attribute \src "libresoc.v:19973.9-19973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:19991.3-20009.6" + process $proc$libresoc.v:19991$416 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19992.5-19992.29" + switch \initial + attribute \src "libresoc.v:19992.9-19992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:20010.3-20028.6" + process $proc$libresoc.v:20010$417 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20011.5-20011.29" + switch \initial + attribute \src "libresoc.v:20011.9-20011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:20029.3-20047.6" + process $proc$libresoc.v:20029$418 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:20030.5-20030.29" + switch \initial + attribute \src "libresoc.v:20030.9-20030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:20048.3-20066.6" + process $proc$libresoc.v:20048$419 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:20049.5-20049.29" + switch \initial + attribute \src "libresoc.v:20049.9-20049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:20067.3-20085.6" + process $proc$libresoc.v:20067$420 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:20068.5-20068.29" + switch \initial + attribute \src "libresoc.v:20068.9-20068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + end + attribute \src "libresoc.v:20086.3-20104.6" + process $proc$libresoc.v:20086$421 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:20087.5-20087.29" + switch \initial + attribute \src "libresoc.v:20087.9-20087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:20105.3-20123.6" + process $proc$libresoc.v:20105$422 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:20106.5-20106.29" + switch \initial + attribute \src "libresoc.v:20106.9-20106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:20124.3-20142.6" + process $proc$libresoc.v:20124$423 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:20125.5-20125.29" + switch \initial + attribute \src "libresoc.v:20125.9-20125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:20143.3-20161.6" + process $proc$libresoc.v:20143$424 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:20144.5-20144.29" + switch \initial + attribute \src "libresoc.v:20144.9-20144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "SPBlock_512W64B8W.v:2.1-7.10" +attribute \cells_not_processed 1 +attribute \blackbox 1 +module \SPBlock_512W64B8W + attribute \src "SPBlock_512W64B8W.v:2.38-2.39" + wire width 9 input 1 \a + attribute \src "SPBlock_512W64B8W.v:6.11-6.14" + wire input 5 \clk + attribute \src "SPBlock_512W64B8W.v:3.18-3.19" + wire width 64 input 2 \d + attribute \src "SPBlock_512W64B8W.v:4.19-4.20" + wire width 64 output 3 \q + attribute \src "SPBlock_512W64B8W.v:5.17-5.19" + wire width 8 input 4 \we +end +attribute \src "libresoc.v:20167.1-20499.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" +attribute \generator "nMigen" +module \SPR_dec31 + attribute \src "libresoc.v:20456.3-20465.6" + wire width 3 $0\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20466.3-20475.6" + wire width 3 $0\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20436.3-20445.6" + wire width 14 $0\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20446.3-20455.6" + wire width 7 $0\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20486.3-20495.6" + wire $0\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20476.3-20485.6" + wire width 2 $0\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:20168.7-20168.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20456.3-20465.6" + wire width 3 $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20466.3-20475.6" + wire width 3 $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20436.3-20445.6" + wire width 14 $1\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20446.3-20455.6" + wire width 7 $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20486.3-20495.6" + wire $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20476.3-20485.6" + wire width 2 $1\SPR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SPR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SPR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 6 \SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \SPR_dec31_rc_sel + attribute \src "libresoc.v:20168.7-20168.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:20427.23-20435.4" + cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 + connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + connect \opcode_in \SPR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:20168.7-20168.20" + process $proc$libresoc.v:20168$432 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20436.3-20445.6" + process $proc$libresoc.v:20436$426 + assign { } { } + assign { } { } + assign $0\SPR_dec31_function_unit[13:0] $1\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20437.5-20437.29" + switch \initial + attribute \src "libresoc.v:20437.9-20437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_function_unit[13:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + case + assign $1\SPR_dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[13:0] + end + attribute \src "libresoc.v:20446.3-20455.6" + process $proc$libresoc.v:20446$427 + assign { } { } + assign { } { } + assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20447.5-20447.29" + switch \initial + attribute \src "libresoc.v:20447.9-20447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + case + assign $1\SPR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:20456.3-20465.6" + process $proc$libresoc.v:20456$428 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20457.5-20457.29" + switch \initial + attribute \src "libresoc.v:20457.9-20457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + case + assign $1\SPR_dec31_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:20466.3-20475.6" + process $proc$libresoc.v:20466$429 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20467.5-20467.29" + switch \initial + attribute \src "libresoc.v:20467.9-20467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + case + assign $1\SPR_dec31_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:20476.3-20485.6" + process $proc$libresoc.v:20476$430 + assign { } { } + assign { } { } + assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:20477.5-20477.29" + switch \initial + attribute \src "libresoc.v:20477.9-20477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + case + assign $1\SPR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:20486.3-20495.6" + process $proc$libresoc.v:20486$431 + assign { } { } + assign { } { } + assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20487.5-20487.29" + switch \initial + attribute \src "libresoc.v:20487.9-20487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + case + assign $1\SPR_dec31_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] + end + connect \SPR_dec31_dec_sub19_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:20503.1-20716.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" +attribute \generator "nMigen" +module \SPR_dec31_dec_sub19 + attribute \src "libresoc.v:20663.3-20675.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20676.3-20688.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20637.3-20649.6" + wire width 14 $0\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20650.3-20662.6" + wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20702.3-20714.6" + wire $0\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20689.3-20701.6" + wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20504.7-20504.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20663.3-20675.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20676.3-20688.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20637.3-20649.6" + wire width 14 $1\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20650.3-20662.6" + wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20702.3-20714.6" + wire $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20689.3-20701.6" + wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 6 \SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:20504.7-20504.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20504.7-20504.20" + process $proc$libresoc.v:20504$439 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20637.3-20649.6" + process $proc$libresoc.v:20637$433 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_function_unit[13:0] $1\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20638.5-20638.29" + switch \initial + attribute \src "libresoc.v:20638.9-20638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 + case + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 + end + sync always + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[13:0] + end + attribute \src "libresoc.v:20650.3-20662.6" + process $proc$libresoc.v:20650$434 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20651.5-20651.29" + switch \initial + attribute \src "libresoc.v:20651.9-20651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:20663.3-20675.6" + process $proc$libresoc.v:20663$435 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20664.5-20664.29" + switch \initial + attribute \src "libresoc.v:20664.9-20664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:20676.3-20688.6" + process $proc$libresoc.v:20676$436 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20677.5-20677.29" + switch \initial + attribute \src "libresoc.v:20677.9-20677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:20689.3-20701.6" + process $proc$libresoc.v:20689$437 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20690.5-20690.29" + switch \initial + attribute \src "libresoc.v:20690.9-20690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:20702.3-20714.6" + process $proc$libresoc.v:20702$438 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20703.5-20703.29" + switch \initial + attribute \src "libresoc.v:20703.9-20703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20720.1-20992.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" +attribute \generator "nMigen" +module \_fsm + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $0\fsm_state$next[3:0]$464 + attribute \src "libresoc.v:20806.3-20807.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:20721.7-20721.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20812.3-20839.6" + wire $0\isdr$next[0:0]$460 + attribute \src "libresoc.v:20808.3-20809.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:20955.3-20982.6" + wire $0\isir$next[0:0]$477 + attribute \src "libresoc.v:20810.3-20811.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $10\fsm_state$next[3:0]$474 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $11\fsm_state$next[3:0]$475 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20761.13-20761.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:20812.3-20839.6" + wire $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20766.7-20766.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:20955.3-20982.6" + wire $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20771.7-20771.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $2\fsm_state$next[3:0]$466 + attribute \src "libresoc.v:20812.3-20839.6" + wire $2\isdr$next[0:0]$462 + attribute \src "libresoc.v:20955.3-20982.6" + wire $2\isir$next[0:0]$479 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $3\fsm_state$next[3:0]$467 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $4\fsm_state$next[3:0]$468 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $5\fsm_state$next[3:0]$469 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $6\fsm_state$next[3:0]$470 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $7\fsm_state$next[3:0]$471 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $8\fsm_state$next[3:0]$472 + attribute \src "libresoc.v:20840.3-20954.6" + wire width 4 $9\fsm_state$next[3:0]$473 + attribute \src "libresoc.v:20790.17-20790.110" + wire $eq$libresoc.v:20790$440_Y + attribute \src "libresoc.v:20791.18-20791.111" + wire $eq$libresoc.v:20791$441_Y + attribute \src "libresoc.v:20792.18-20792.111" + wire $eq$libresoc.v:20792$442_Y + attribute \src "libresoc.v:20793.18-20793.111" + wire $eq$libresoc.v:20793$443_Y + attribute \src "libresoc.v:20794.18-20794.111" + wire $eq$libresoc.v:20794$444_Y + attribute \src "libresoc.v:20795.17-20795.108" + wire $eq$libresoc.v:20795$445_Y + attribute \src "libresoc.v:20796.18-20796.111" + wire $eq$libresoc.v:20796$446_Y + attribute \src "libresoc.v:20797.18-20797.111" + wire $eq$libresoc.v:20797$447_Y + attribute \src "libresoc.v:20798.18-20798.111" + wire $eq$libresoc.v:20798$448_Y + attribute \src "libresoc.v:20799.18-20799.111" + wire $eq$libresoc.v:20799$449_Y + attribute \src "libresoc.v:20800.18-20800.111" + wire $eq$libresoc.v:20800$450_Y + attribute \src "libresoc.v:20801.18-20801.111" + wire $eq$libresoc.v:20801$451_Y + attribute \src "libresoc.v:20802.18-20802.112" + wire $eq$libresoc.v:20802$452_Y + attribute \src "libresoc.v:20803.17-20803.108" + wire $eq$libresoc.v:20803$453_Y + attribute \src "libresoc.v:20804.17-20804.108" + wire $eq$libresoc.v:20804$454_Y + attribute \src "libresoc.v:20805.17-20805.108" + wire $eq$libresoc.v:20805$455_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:20721.7-20721.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 11 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20790$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20790$440_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20791$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20791$441_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + cell $eq $eq$libresoc.v:20792$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20792$442_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + cell $eq $eq$libresoc.v:20793$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20793$443_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20794$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20794$444_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + cell $eq $eq$libresoc.v:20795$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:20795$445_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20796$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20796$446_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + cell $eq $eq$libresoc.v:20797$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20797$447_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + cell $eq $eq$libresoc.v:20798$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20798$448_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + cell $eq $eq$libresoc.v:20799$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20799$449_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + cell $eq $eq$libresoc.v:20800$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20800$450_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + cell $eq $eq$libresoc.v:20801$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20801$451_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + cell $eq $eq$libresoc.v:20802$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20802$452_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:20803$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:20803$453_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:20804$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:20804$454_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:20805$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:20805$455_Y + end + attribute \src "libresoc.v:20721.7-20721.20" + process $proc$libresoc.v:20721$480 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20761.13-20761.29" + process $proc$libresoc.v:20761$481 + assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:20766.7-20766.18" + process $proc$libresoc.v:20766$482 + assign { } { } + assign $1\isdr[0:0] 1'0 + sync always + sync init + update \isdr $1\isdr[0:0] + end + attribute \src "libresoc.v:20771.7-20771.18" + process $proc$libresoc.v:20771$483 + assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:20806.3-20807.35" + process $proc$libresoc.v:20806$456 + assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:20808.3-20809.25" + process $proc$libresoc.v:20808$457 + assign { } { } + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:20810.3-20811.25" + process $proc$libresoc.v:20810$458 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] + end + attribute \src "libresoc.v:20812.3-20839.6" + process $proc$libresoc.v:20812$459 + assign { } { } + assign { } { } + assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20813.5-20813.29" + switch \initial + attribute \src "libresoc.v:20813.9-20813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$461 $2\isdr$next[0:0]$462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$462 1'1 + case + assign $2\isdr$next[0:0]$462 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + case + assign $1\isdr$next[0:0]$461 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$460 + end + attribute \src "libresoc.v:20840.3-20954.6" + process $proc$libresoc.v:20840$463 + assign { } { } + assign { } { } + assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20841.5-20841.29" + switch \initial + attribute \src "libresoc.v:20841.9-20841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $2\fsm_state$next[3:0]$466 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$466 4'0001 + case + assign $2\fsm_state$next[3:0]$466 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $3\fsm_state$next[3:0]$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$467 4'0010 + case + assign $3\fsm_state$next[3:0]$467 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $4\fsm_state$next[3:0]$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$468 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$468 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $5\fsm_state$next[3:0]$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$469 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$469 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $6\fsm_state$next[3:0]$470 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$470 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$470 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $7\fsm_state$next[3:0]$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$471 4'0110 + case + assign $7\fsm_state$next[3:0]$471 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $8\fsm_state$next[3:0]$472 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$472 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$472 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $9\fsm_state$next[3:0]$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$473 4'1001 + case + assign $9\fsm_state$next[3:0]$473 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $10\fsm_state$next[3:0]$474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$474 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$474 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $11\fsm_state$next[3:0]$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$475 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$475 4'0010 + end + case + assign $1\fsm_state$next[3:0]$465 \fsm_state + end + sync always + update \fsm_state$next $0\fsm_state$next[3:0]$464 + end + attribute \src "libresoc.v:20955.3-20982.6" + process $proc$libresoc.v:20955$476 + assign { } { } + assign { } { } + assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20956.5-20956.29" + switch \initial + attribute \src "libresoc.v:20956.9-20956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$479 1'1 + case + assign $2\isir$next[0:0]$479 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + case + assign $1\isir$next[0:0]$478 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$477 + end + connect \$9 $eq$libresoc.v:20790$440_Y + connect \$11 $eq$libresoc.v:20791$441_Y + connect \$13 $eq$libresoc.v:20792$442_Y + connect \$15 $eq$libresoc.v:20793$443_Y + connect \$17 $eq$libresoc.v:20794$444_Y + connect \$1 $eq$libresoc.v:20795$445_Y + connect \$19 $eq$libresoc.v:20796$446_Y + connect \$21 $eq$libresoc.v:20797$447_Y + connect \$23 $eq$libresoc.v:20798$448_Y + connect \$25 $eq$libresoc.v:20799$449_Y + connect \$27 $eq$libresoc.v:20800$450_Y + connect \$29 $eq$libresoc.v:20801$451_Y + connect \$31 $eq$libresoc.v:20802$452_Y + connect \$3 $eq$libresoc.v:20803$453_Y + connect \$5 $eq$libresoc.v:20804$454_Y + connect \$7 $eq$libresoc.v:20805$455_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:20996.1-21068.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:21041.3-21061.6" + wire width 32 $0\TAP_id_sr$next[31:0]$489 + attribute \src "libresoc.v:21039.3-21040.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:20997.7-20997.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21041.3-21061.6" + wire width 32 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:21007.14-21007.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:21041.3-21061.6" + wire width 32 $2\TAP_id_sr$next[31:0]$491 + attribute \src "libresoc.v:21036.17-21036.110" + wire $and$libresoc.v:21036$484_Y + attribute \src "libresoc.v:21037.17-21037.108" + wire $and$libresoc.v:21037$485_Y + attribute \src "libresoc.v:21038.17-21038.109" + wire $and$libresoc.v:21038$486_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire input 1 \id_bypass + attribute \src "libresoc.v:20997.7-20997.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire input 9 \select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:21036$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \capture + connect \Y $and$libresoc.v:21036$484_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:21037$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \shift + connect \Y $and$libresoc.v:21037$485_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $and$libresoc.v:21038$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \update + connect \Y $and$libresoc.v:21038$486_Y + end + attribute \src "libresoc.v:20997.7-20997.20" + process $proc$libresoc.v:20997$492 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21007.14-21007.31" + process $proc$libresoc.v:21007$493 + assign { } { } + assign $1\TAP_id_sr[31:0] 0 + sync always + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:21039.3-21040.35" + process $proc$libresoc.v:21039$487 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:21041.3-21061.6" + process $proc$libresoc.v:21041$488 + assign { } { } + assign { } { } + assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:21042.5-21042.29" + switch \initial + attribute \src "libresoc.v:21042.9-21042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\TAP_id_sr$next[31:0]$490 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$490 $2\TAP_id_sr$next[31:0]$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$491 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$491 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$491 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$490 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 + end + connect \$1 $and$libresoc.v:21036$484_Y + connect \$3 $and$libresoc.v:21037$485_Y + connect \$5 $and$libresoc.v:21038$486_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \id_bypass + connect \_update \$5 + connect \_shift \$3 + connect \_capture \$1 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:21072.1-21156.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:21073.7-21073.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21134.3-21154.6" + wire width 4 $0\ir$next[3:0]$506 + attribute \src "libresoc.v:21117.3-21118.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:21121.3-21133.6" + wire width 4 $0\shift_ir$next[3:0]$503 + attribute \src "libresoc.v:21119.3-21120.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:21134.3-21154.6" + wire width 4 $1\ir$next[3:0]$507 + attribute \src "libresoc.v:21092.13-21092.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:21121.3-21133.6" + wire width 4 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:21104.13-21104.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:21134.3-21154.6" + wire width 4 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:21111.17-21111.103" + wire $and$libresoc.v:21111$494_Y + attribute \src "libresoc.v:21112.18-21112.105" + wire $and$libresoc.v:21112$495_Y + attribute \src "libresoc.v:21113.17-21113.105" + wire $and$libresoc.v:21113$496_Y + attribute \src "libresoc.v:21114.17-21114.103" + wire $and$libresoc.v:21114$497_Y + attribute \src "libresoc.v:21115.17-21115.104" + wire $and$libresoc.v:21115$498_Y + attribute \src "libresoc.v:21116.17-21116.105" + wire $and$libresoc.v:21116$499_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 1 \capture + attribute \src "libresoc.v:21073.7-21073.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:21111$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:21111$494_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:21112$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:21112$495_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:21113$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:21113$496_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:21114$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:21114$497_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:21115$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:21115$498_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:21116$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:21116$499_Y + end + attribute \src "libresoc.v:21073.7-21073.20" + process $proc$libresoc.v:21073$509 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21092.13-21092.22" + process $proc$libresoc.v:21092$510 + assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:21104.13-21104.28" + process $proc$libresoc.v:21104$511 + assign { } { } + assign $1\shift_ir[3:0] 4'0000 + sync always + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:21117.3-21118.21" + process $proc$libresoc.v:21117$500 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:21119.3-21120.33" + process $proc$libresoc.v:21119$501 + assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:21121.3-21133.6" + process $proc$libresoc.v:21121$502 + assign { } { } + assign { } { } + assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:21122.5-21122.29" + switch \initial + attribute \src "libresoc.v:21122.9-21122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$504 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\shift_ir$next[3:0]$504 { \TAP_bus__tdi \shift_ir [3:1] } + case + assign $1\shift_ir$next[3:0]$504 \shift_ir + end + sync always + update \shift_ir$next $0\shift_ir$next[3:0]$503 + end + attribute \src "libresoc.v:21134.3-21154.6" + process $proc$libresoc.v:21134$505 + assign { } { } + assign { } { } + assign { } { } + assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:21135.5-21135.29" + switch \initial + attribute \src "libresoc.v:21135.9-21135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$507 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$507 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\ir$next[3:0]$507 \shift_ir + case + assign $1\ir$next[3:0]$507 \ir + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ir$next[3:0]$508 4'0001 + case + assign $2\ir$next[3:0]$508 $1\ir$next[3:0]$507 + end + sync always + update \ir$next $0\ir$next[3:0]$506 + end + connect \$9 $and$libresoc.v:21111$494_Y + connect \$11 $and$libresoc.v:21112$495_Y + connect \$1 $and$libresoc.v:21113$496_Y + connect \$3 $and$libresoc.v:21114$497_Y + connect \$5 $and$libresoc.v:21115$498_Y + connect \$7 $and$libresoc.v:21116$499_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:21160.1-21218.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" +attribute \generator "nMigen" +module \adr_l + attribute \src "libresoc.v:21161.7-21161.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21206.3-21214.6" + wire $0\q_int$next[0:0]$522 + attribute \src "libresoc.v:21204.3-21205.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:21206.3-21214.6" + wire $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:21185.7-21185.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:21196.17-21196.96" + wire $and$libresoc.v:21196$512_Y + attribute \src "libresoc.v:21201.17-21201.96" + wire $and$libresoc.v:21201$517_Y + attribute \src "libresoc.v:21198.18-21198.93" + wire $not$libresoc.v:21198$514_Y + attribute \src "libresoc.v:21200.17-21200.92" + wire $not$libresoc.v:21200$516_Y + attribute \src "libresoc.v:21203.17-21203.92" + wire $not$libresoc.v:21203$519_Y + attribute \src "libresoc.v:21197.18-21197.98" + wire $or$libresoc.v:21197$513_Y + attribute \src "libresoc.v:21199.18-21199.99" + wire $or$libresoc.v:21199$515_Y + attribute \src "libresoc.v:21202.17-21202.97" + wire $or$libresoc.v:21202$518_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:21161.7-21161.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:21196$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:21196$512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:21201$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:21201$517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:21198$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \Y $not$libresoc.v:21198$514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:21200$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:21200$516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:21203$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:21203$519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:21197$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_adr + connect \Y $or$libresoc.v:21197$513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:21199$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \B \q_int + connect \Y $or$libresoc.v:21199$515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:21202$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_adr + connect \Y $or$libresoc.v:21202$518_Y + end + attribute \src "libresoc.v:21161.7-21161.20" + process $proc$libresoc.v:21161$524 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21185.7-21185.19" + process $proc$libresoc.v:21185$525 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:21204.3-21205.27" + process $proc$libresoc.v:21204$520 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:21206.3-21214.6" + process $proc$libresoc.v:21206$521 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:21207.5-21207.29" + switch \initial + attribute \src "libresoc.v:21207.9-21207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$523 1'0 + case + assign $1\q_int$next[0:0]$523 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$522 + end + connect \$9 $and$libresoc.v:21196$512_Y + connect \$11 $or$libresoc.v:21197$513_Y + connect \$13 $not$libresoc.v:21198$514_Y + connect \$15 $or$libresoc.v:21199$515_Y + connect \$1 $not$libresoc.v:21200$516_Y + connect \$3 $and$libresoc.v:21201$517_Y + connect \$5 $or$libresoc.v:21202$518_Y + connect \$7 $not$libresoc.v:21203$519_Y + connect \qlq_adr \$15 + connect \qn_adr \$13 + connect \q_adr \$11 +end +attribute \src "libresoc.v:21222.1-21280.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" +attribute \generator "nMigen" +module \adrok_l + attribute \src "libresoc.v:21223.7-21223.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21268.3-21276.6" + wire $0\q_int$next[0:0]$536 + attribute \src "libresoc.v:21266.3-21267.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:21268.3-21276.6" + wire $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:21247.7-21247.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:21258.17-21258.96" + wire $and$libresoc.v:21258$526_Y + attribute \src "libresoc.v:21263.17-21263.96" + wire $and$libresoc.v:21263$531_Y + attribute \src "libresoc.v:21260.18-21260.100" + wire $not$libresoc.v:21260$528_Y + attribute \src "libresoc.v:21262.17-21262.99" + wire $not$libresoc.v:21262$530_Y + attribute \src "libresoc.v:21265.17-21265.99" + wire $not$libresoc.v:21265$533_Y + attribute \src "libresoc.v:21259.18-21259.105" + wire $or$libresoc.v:21259$527_Y + attribute \src "libresoc.v:21261.18-21261.106" + wire $or$libresoc.v:21261$529_Y + attribute \src "libresoc.v:21264.17-21264.104" + wire $or$libresoc.v:21264$532_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 6 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:21223.7-21223.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 5 \q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire output 4 \qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:21258$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:21258$526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:21263$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:21263$531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:21260$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \Y $not$libresoc.v:21260$528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:21262$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:21262$530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:21265$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:21265$533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:21259$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:21259$527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:21261$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \B \q_int + connect \Y $or$libresoc.v:21261$529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:21264$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:21264$532_Y + end + attribute \src "libresoc.v:21223.7-21223.20" + process $proc$libresoc.v:21223$538 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21247.7-21247.19" + process $proc$libresoc.v:21247$539 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:21266.3-21267.27" + process $proc$libresoc.v:21266$534 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:21268.3-21276.6" + process $proc$libresoc.v:21268$535 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:21269.5-21269.29" + switch \initial + attribute \src "libresoc.v:21269.9-21269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$537 1'0 + case + assign $1\q_int$next[0:0]$537 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$536 + end + connect \$9 $and$libresoc.v:21258$526_Y + connect \$11 $or$libresoc.v:21259$527_Y + connect \$13 $not$libresoc.v:21260$528_Y + connect \$15 $or$libresoc.v:21261$529_Y + connect \$1 $not$libresoc.v:21262$530_Y + connect \$3 $and$libresoc.v:21263$531_Y + connect \$5 $or$libresoc.v:21264$532_Y + connect \$7 $not$libresoc.v:21265$533_Y + connect \qlq_addr_acked \$15 + connect \qn_addr_acked \$13 + connect \q_addr_acked \$11 +end +attribute \src "libresoc.v:21284.1-22615.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" +attribute \generator "nMigen" +module \alu0 + attribute \src "libresoc.v:22126.3-22127.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 + attribute \src "libresoc.v:22098.3-22099.67" + wire width 4 $0\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 14 $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 + attribute \src "libresoc.v:22068.3-22069.65" + wire width 14 $0\alu_alu0_alu_op__fn_unit[13:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + attribute \src "libresoc.v:22070.3-22071.79" + wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + attribute \src "libresoc.v:22072.3-22073.75" + wire $0\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + attribute \src "libresoc.v:22090.3-22091.73" + wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 + attribute \src "libresoc.v:22100.3-22101.59" + wire width 32 $0\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + attribute \src "libresoc.v:22066.3-22067.69" + wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + attribute \src "libresoc.v:22082.3-22083.69" + wire $0\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + attribute \src "libresoc.v:22086.3-22087.71" + wire $0\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + attribute \src "libresoc.v:22094.3-22095.67" + wire $0\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + attribute \src "libresoc.v:22096.3-22097.69" + wire $0\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + attribute \src "libresoc.v:22078.3-22079.63" + wire $0\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + attribute \src "libresoc.v:22080.3-22081.63" + wire $0\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + attribute \src "libresoc.v:22092.3-22093.75" + wire $0\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + attribute \src "libresoc.v:22076.3-22077.63" + wire $0\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + attribute \src "libresoc.v:22074.3-22075.63" + wire $0\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + attribute \src "libresoc.v:22088.3-22089.69" + wire $0\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + attribute \src "libresoc.v:22084.3-22085.63" + wire $0\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:22124.3-22125.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:22514.3-22522.6" + wire $0\alu_l_r_alu$next[0:0]$784 + attribute \src "libresoc.v:22034.3-22035.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22505.3-22513.6" + wire $0\alui_l_r_alui$next[0:0]$781 + attribute \src "libresoc.v:22036.3-22037.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:22355.3-22376.6" + wire width 64 $0\data_r0__o$next[63:0]$729 + attribute \src "libresoc.v:22062.3-22063.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:22355.3-22376.6" + wire $0\data_r0__o_ok$next[0:0]$730 + attribute \src "libresoc.v:22064.3-22065.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:22377.3-22398.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$737 + attribute \src "libresoc.v:22058.3-22059.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:22377.3-22398.6" + wire $0\data_r1__cr_a_ok$next[0:0]$738 + attribute \src "libresoc.v:22060.3-22061.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22399.3-22420.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$745 + attribute \src "libresoc.v:22054.3-22055.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22399.3-22420.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$746 + attribute \src "libresoc.v:22056.3-22057.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22421.3-22442.6" + wire width 2 $0\data_r3__xer_ov$next[1:0]$753 + attribute \src "libresoc.v:22050.3-22051.47" + wire width 2 $0\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22421.3-22442.6" + wire $0\data_r3__xer_ov_ok$next[0:0]$754 + attribute \src "libresoc.v:22052.3-22053.53" + wire $0\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22443.3-22464.6" + wire $0\data_r4__xer_so$next[0:0]$761 + attribute \src "libresoc.v:22046.3-22047.47" + wire $0\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22443.3-22464.6" + wire $0\data_r4__xer_so_ok$next[0:0]$762 + attribute \src "libresoc.v:22048.3-22049.53" + wire $0\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22523.3-22532.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:22533.3-22542.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:22543.3-22552.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:22553.3-22562.6" + wire width 2 $0\dest4_o[1:0] + attribute \src "libresoc.v:22563.3-22572.6" + wire $0\dest5_o[0:0] + attribute \src "libresoc.v:21285.7-21285.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:22271.3-22279.6" + wire $0\opc_l_r_opc$next[0:0]$671 + attribute \src "libresoc.v:22110.3-22111.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:22262.3-22270.6" + wire $0\opc_l_s_opc$next[0:0]$668 + attribute \src "libresoc.v:22112.3-22113.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22573.3-22581.6" + wire width 5 $0\prev_wr_go$next[4:0]$792 + attribute \src "libresoc.v:22122.3-22123.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:22216.3-22225.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:22307.3-22315.6" + wire width 5 $0\req_l_r_req$next[4:0]$683 + attribute \src "libresoc.v:22102.3-22103.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:22298.3-22306.6" + wire width 5 $0\req_l_s_req$next[4:0]$680 + attribute \src "libresoc.v:22104.3-22105.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:22235.3-22243.6" + wire $0\rok_l_r_rdok$next[0:0]$659 + attribute \src "libresoc.v:22118.3-22119.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:22226.3-22234.6" + wire $0\rok_l_s_rdok$next[0:0]$656 + attribute \src "libresoc.v:22120.3-22121.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:22253.3-22261.6" + wire $0\rst_l_r_rst$next[0:0]$665 + attribute \src "libresoc.v:22114.3-22115.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:22244.3-22252.6" + wire $0\rst_l_s_rst$next[0:0]$662 + attribute \src "libresoc.v:22116.3-22117.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:22289.3-22297.6" + wire width 4 $0\src_l_r_src$next[3:0]$677 + attribute \src "libresoc.v:22106.3-22107.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:22280.3-22288.6" + wire width 4 $0\src_l_s_src$next[3:0]$674 + attribute \src "libresoc.v:22108.3-22109.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:22465.3-22474.6" + wire width 64 $0\src_r0$next[63:0]$769 + attribute \src "libresoc.v:22044.3-22045.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:22475.3-22484.6" + wire width 64 $0\src_r1$next[63:0]$772 + attribute \src "libresoc.v:22042.3-22043.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:22485.3-22494.6" + wire $0\src_r2$next[0:0]$775 + attribute \src "libresoc.v:22040.3-22041.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:22495.3-22504.6" + wire width 2 $0\src_r3$next[1:0]$778 + attribute \src "libresoc.v:22038.3-22039.29" + wire width 2 $0\src_r3[1:0] + attribute \src "libresoc.v:21423.7-21423.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + attribute \src "libresoc.v:21431.13-21431.45" + wire width 4 $1\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 14 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 + attribute \src "libresoc.v:21450.14-21450.49" + wire width 14 $1\alu_alu0_alu_op__fn_unit[13:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + attribute \src "libresoc.v:21454.14-21454.68" + wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + attribute \src "libresoc.v:21458.7-21458.43" + wire $1\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + attribute \src "libresoc.v:21466.13-21466.48" + wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 + attribute \src "libresoc.v:21470.14-21470.43" + wire width 32 $1\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + attribute \src "libresoc.v:21549.13-21549.47" + wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + attribute \src "libresoc.v:21553.7-21553.40" + wire $1\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + attribute \src "libresoc.v:21557.7-21557.41" + wire $1\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + attribute \src "libresoc.v:21561.7-21561.39" + wire $1\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + attribute \src "libresoc.v:21565.7-21565.40" + wire $1\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + attribute \src "libresoc.v:21569.7-21569.37" + wire $1\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + attribute \src "libresoc.v:21573.7-21573.37" + wire $1\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + attribute \src "libresoc.v:21577.7-21577.43" + wire $1\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + attribute \src "libresoc.v:21581.7-21581.37" + wire $1\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + attribute \src "libresoc.v:21585.7-21585.37" + wire $1\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + attribute \src "libresoc.v:21589.7-21589.40" + wire $1\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + attribute \src "libresoc.v:21593.7-21593.37" + wire $1\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:21625.7-21625.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:22514.3-22522.6" + wire $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:21633.7-21633.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22505.3-22513.6" + wire $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:21645.7-21645.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:22355.3-22376.6" + wire width 64 $1\data_r0__o$next[63:0]$731 + attribute \src "libresoc.v:21679.14-21679.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:22355.3-22376.6" + wire $1\data_r0__o_ok$next[0:0]$732 + attribute \src "libresoc.v:21683.7-21683.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:22377.3-22398.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$739 + attribute \src "libresoc.v:21687.13-21687.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:22377.3-22398.6" + wire $1\data_r1__cr_a_ok$next[0:0]$740 + attribute \src "libresoc.v:21691.7-21691.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22399.3-22420.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$747 + attribute \src "libresoc.v:21695.13-21695.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22399.3-22420.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$748 + attribute \src "libresoc.v:21699.7-21699.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22421.3-22442.6" + wire width 2 $1\data_r3__xer_ov$next[1:0]$755 + attribute \src "libresoc.v:21703.13-21703.35" + wire width 2 $1\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22421.3-22442.6" + wire $1\data_r3__xer_ov_ok$next[0:0]$756 + attribute \src "libresoc.v:21707.7-21707.32" + wire $1\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22443.3-22464.6" + wire $1\data_r4__xer_so$next[0:0]$763 + attribute \src "libresoc.v:21711.7-21711.29" + wire $1\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22443.3-22464.6" + wire $1\data_r4__xer_so_ok$next[0:0]$764 + attribute \src "libresoc.v:21715.7-21715.32" + wire $1\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22523.3-22532.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:22533.3-22542.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:22543.3-22552.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:22553.3-22562.6" + wire width 2 $1\dest4_o[1:0] + attribute \src "libresoc.v:22563.3-22572.6" + wire $1\dest5_o[0:0] + attribute \src "libresoc.v:22271.3-22279.6" + wire $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:21738.7-21738.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:22262.3-22270.6" + wire $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:21742.7-21742.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22573.3-22581.6" + wire width 5 $1\prev_wr_go$next[4:0]$793 + attribute \src "libresoc.v:21876.13-21876.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:22216.3-22225.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:22307.3-22315.6" + wire width 5 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:21884.13-21884.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:22298.3-22306.6" + wire width 5 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:21888.13-21888.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:22235.3-22243.6" + wire $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:21900.7-21900.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:22226.3-22234.6" + wire $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:21904.7-21904.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:22253.3-22261.6" + wire $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:21908.7-21908.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:22244.3-22252.6" + wire $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:21912.7-21912.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:22289.3-22297.6" + wire width 4 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:21928.13-21928.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:22280.3-22288.6" + wire width 4 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:21932.13-21932.31" + wire width 4 $1\src_l_s_src[3:0] + attribute \src "libresoc.v:22465.3-22474.6" + wire width 64 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:21940.14-21940.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:22475.3-22484.6" + wire width 64 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:21944.14-21944.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:22485.3-22494.6" + wire $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:21948.7-21948.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:22495.3-22504.6" + wire width 2 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:21952.13-21952.26" + wire width 2 $1\src_r3[1:0] + attribute \src "libresoc.v:22316.3-22354.6" + wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + attribute \src "libresoc.v:22316.3-22354.6" + wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + attribute \src "libresoc.v:22316.3-22354.6" + wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + attribute \src "libresoc.v:22316.3-22354.6" + wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + attribute \src "libresoc.v:22316.3-22354.6" + wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + attribute \src "libresoc.v:22316.3-22354.6" + wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22355.3-22376.6" + wire width 64 $2\data_r0__o$next[63:0]$733 + attribute \src "libresoc.v:22355.3-22376.6" + wire $2\data_r0__o_ok$next[0:0]$734 + attribute \src "libresoc.v:22377.3-22398.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$741 + attribute \src "libresoc.v:22377.3-22398.6" + wire $2\data_r1__cr_a_ok$next[0:0]$742 + attribute \src "libresoc.v:22399.3-22420.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$749 + attribute \src "libresoc.v:22399.3-22420.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$750 + attribute \src "libresoc.v:22421.3-22442.6" + wire width 2 $2\data_r3__xer_ov$next[1:0]$757 + attribute \src "libresoc.v:22421.3-22442.6" + wire $2\data_r3__xer_ov_ok$next[0:0]$758 + attribute \src "libresoc.v:22443.3-22464.6" + wire $2\data_r4__xer_so$next[0:0]$765 + attribute \src "libresoc.v:22443.3-22464.6" + wire $2\data_r4__xer_so_ok$next[0:0]$766 + attribute \src "libresoc.v:22355.3-22376.6" + wire $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22377.3-22398.6" + wire $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22399.3-22420.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22421.3-22442.6" + wire $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22443.3-22464.6" + wire $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:21968.18-21968.134" + wire $and$libresoc.v:21968$541_Y + attribute \src "libresoc.v:21969.19-21969.133" + wire $and$libresoc.v:21969$542_Y + attribute \src "libresoc.v:21970.19-21970.161" + wire width 4 $and$libresoc.v:21970$543_Y + attribute \src "libresoc.v:21973.19-21973.134" + wire width 4 $and$libresoc.v:21973$546_Y + attribute \src "libresoc.v:21975.19-21975.115" + wire width 4 $and$libresoc.v:21975$548_Y + attribute \src "libresoc.v:21976.19-21976.125" + wire $and$libresoc.v:21976$549_Y + attribute \src "libresoc.v:21977.19-21977.125" + wire $and$libresoc.v:21977$550_Y + attribute \src "libresoc.v:21978.18-21978.110" + wire $and$libresoc.v:21978$551_Y + attribute \src "libresoc.v:21979.19-21979.125" + wire $and$libresoc.v:21979$552_Y + attribute \src "libresoc.v:21980.19-21980.125" + wire $and$libresoc.v:21980$553_Y + attribute \src "libresoc.v:21981.19-21981.125" + wire $and$libresoc.v:21981$554_Y + attribute \src "libresoc.v:21982.19-21982.157" + wire width 5 $and$libresoc.v:21982$555_Y + attribute \src "libresoc.v:21983.19-21983.121" + wire width 5 $and$libresoc.v:21983$556_Y + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \alu_alu0_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_alu0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_alu0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_alu0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_alu0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_alu0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_alu0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_alu0_xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_alu0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_alu0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_alu0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 31 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 30 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 32 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 34 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 36 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 38 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 40 \dest5_o + attribute \src "libresoc.v:21285.7-21285.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 14 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 \req_l_s_req + attribute \src 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:22001$574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:22012$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:22012$585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:22013$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:22013$586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:22014$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:22014$587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:22015$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:22015$588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:22019$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:22019$592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:22028$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:22028$601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:21967$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:21967$540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:21996$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:21996$569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21999$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:21999$572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:22000$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:22000$573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:22025$598 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:22025$598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:22026$599 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:22026$599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:22027$600 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:22027$600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:22029$602 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_alu0_alu_op__imm_data__data + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:22029$602_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22030$603 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:22030$603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22031$604 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$88 + connect \S \src_sel$85 + connect \Y $ternary$libresoc.v:22031$604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22032$605 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:22032$605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:22033$606 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:22033$606_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22128.12-22167.4" + cell \alu_alu0 \alu_alu0 + connect \alu_op__data_len \alu_alu0_alu_op__data_len + connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit + connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data + connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok + connect \alu_op__input_carry \alu_alu0_alu_op__input_carry + connect \alu_op__insn \alu_alu0_alu_op__insn + connect \alu_op__insn_type \alu_alu0_alu_op__insn_type + connect \alu_op__invert_in \alu_alu0_alu_op__invert_in + connect \alu_op__invert_out \alu_alu0_alu_op__invert_out + connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit + connect \alu_op__is_signed \alu_alu0_alu_op__is_signed + connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe + connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok + connect \alu_op__output_carry \alu_alu0_alu_op__output_carry + connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok + connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc + connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 + connect \alu_op__zero_a \alu_alu0_alu_op__zero_a + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_alu0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_alu0_n_ready_i + connect \n_valid_o \alu_alu0_n_valid_o + connect \o \alu_alu0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_alu0_p_ready_o + connect \p_valid_i \alu_alu0_p_valid_i + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_ca \alu_alu0_xer_ca + connect \xer_ca$2 \alu_alu0_xer_ca$2 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_alu0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_alu0_xer_so + connect \xer_so$1 \alu_alu0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22168.9-22174.4" + cell \alu_l \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22175.10-22181.4" + cell \alui_l \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22182.9-22188.4" + cell \opc_l \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22189.9-22195.4" + cell \req_l \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22196.9-22202.4" + cell \rok_l \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22203.9-22208.4" + cell \rst_l \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22209.9-22215.4" + cell \src_l \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:21285.7-21285.20" + process $proc$libresoc.v:21285$794 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21423.7-21423.24" + process $proc$libresoc.v:21423$795 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:21431.13-21431.45" + process $proc$libresoc.v:21431$796 + assign { } { } + assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21450.14-21450.49" + process $proc$libresoc.v:21450$797 + assign { } { } + assign $1\alu_alu0_alu_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[13:0] + end + attribute \src "libresoc.v:21454.14-21454.68" + process $proc$libresoc.v:21454$798 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21458.7-21458.43" + process $proc$libresoc.v:21458$799 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21466.13-21466.48" + process $proc$libresoc.v:21466$800 + assign { } { } + assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21470.14-21470.43" + process $proc$libresoc.v:21470$801 + assign { } { } + assign $1\alu_alu0_alu_op__insn[31:0] 0 + sync always + sync init + update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21549.13-21549.47" + process $proc$libresoc.v:21549$802 + assign { } { } + assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21553.7-21553.40" + process $proc$libresoc.v:21553$803 + assign { } { } + assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21557.7-21557.41" + process $proc$libresoc.v:21557$804 + assign { } { } + assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21561.7-21561.39" + process $proc$libresoc.v:21561$805 + assign { } { } + assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21565.7-21565.40" + process $proc$libresoc.v:21565$806 + assign { } { } + assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21569.7-21569.37" + process $proc$libresoc.v:21569$807 + assign { } { } + assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21573.7-21573.37" + process $proc$libresoc.v:21573$808 + assign { } { } + assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21577.7-21577.43" + process $proc$libresoc.v:21577$809 + assign { } { } + assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21581.7-21581.37" + process $proc$libresoc.v:21581$810 + assign { } { } + assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21585.7-21585.37" + process $proc$libresoc.v:21585$811 + assign { } { } + assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21589.7-21589.40" + process $proc$libresoc.v:21589$812 + assign { } { } + assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21593.7-21593.37" + process $proc$libresoc.v:21593$813 + assign { } { } + assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21625.7-21625.26" + process $proc$libresoc.v:21625$814 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:21633.7-21633.25" + process $proc$libresoc.v:21633$815 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21645.7-21645.27" + process $proc$libresoc.v:21645$816 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21679.14-21679.47" + process $proc$libresoc.v:21679$817 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:21683.7-21683.27" + process $proc$libresoc.v:21683$818 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21687.13-21687.33" + process $proc$libresoc.v:21687$819 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21691.7-21691.30" + process $proc$libresoc.v:21691$820 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21695.13-21695.35" + process $proc$libresoc.v:21695$821 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21699.7-21699.32" + process $proc$libresoc.v:21699$822 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21703.13-21703.35" + process $proc$libresoc.v:21703$823 + assign { } { } + assign $1\data_r3__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21707.7-21707.32" + process $proc$libresoc.v:21707$824 + assign { } { } + assign $1\data_r3__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21711.7-21711.29" + process $proc$libresoc.v:21711$825 + assign { } { } + assign $1\data_r4__xer_so[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so $1\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21715.7-21715.32" + process $proc$libresoc.v:21715$826 + assign { } { } + assign $1\data_r4__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21738.7-21738.25" + process $proc$libresoc.v:21738$827 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21742.7-21742.25" + process $proc$libresoc.v:21742$828 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21876.13-21876.31" + process $proc$libresoc.v:21876$829 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:21884.13-21884.32" + process $proc$libresoc.v:21884$830 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21888.13-21888.32" + process $proc$libresoc.v:21888$831 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21900.7-21900.26" + process $proc$libresoc.v:21900$832 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21904.7-21904.26" + process $proc$libresoc.v:21904$833 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21908.7-21908.25" + process $proc$libresoc.v:21908$834 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21912.7-21912.25" + process $proc$libresoc.v:21912$835 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21928.13-21928.31" + process $proc$libresoc.v:21928$836 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21932.13-21932.31" + process $proc$libresoc.v:21932$837 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21940.14-21940.43" + process $proc$libresoc.v:21940$838 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:21944.14-21944.43" + process $proc$libresoc.v:21944$839 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:21948.7-21948.20" + process $proc$libresoc.v:21948$840 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:21952.13-21952.26" + process $proc$libresoc.v:21952$841 + assign { } { } + assign $1\src_r3[1:0] 2'00 + sync always + sync init + update \src_r3 $1\src_r3[1:0] + end + attribute \src "libresoc.v:22034.3-22035.39" + process $proc$libresoc.v:22034$607 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:22036.3-22037.43" + process $proc$libresoc.v:22036$608 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:22038.3-22039.29" + process $proc$libresoc.v:22038$609 + assign { } { } + assign $0\src_r3[1:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[1:0] + end + attribute \src "libresoc.v:22040.3-22041.29" + process $proc$libresoc.v:22040$610 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:22042.3-22043.29" + process $proc$libresoc.v:22042$611 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:22044.3-22045.29" + process $proc$libresoc.v:22044$612 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:22046.3-22047.47" + process $proc$libresoc.v:22046$613 + assign { } { } + assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next + sync posedge \coresync_clk + update \data_r4__xer_so $0\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:22048.3-22049.53" + process $proc$libresoc.v:22048$614 + assign { } { } + assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next + sync posedge \coresync_clk + update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:22050.3-22051.47" + process $proc$libresoc.v:22050$615 + assign { } { } + assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next + sync posedge \coresync_clk + update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:22052.3-22053.53" + process $proc$libresoc.v:22052$616 + assign { } { } + assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:22054.3-22055.47" + process $proc$libresoc.v:22054$617 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:22056.3-22057.53" + process $proc$libresoc.v:22056$618 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:22058.3-22059.43" + process $proc$libresoc.v:22058$619 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:22060.3-22061.49" + process $proc$libresoc.v:22060$620 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:22062.3-22063.37" + process $proc$libresoc.v:22062$621 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:22064.3-22065.43" + process $proc$libresoc.v:22064$622 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:22066.3-22067.69" + process $proc$libresoc.v:22066$623 + assign { } { } + assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:22068.3-22069.65" + process $proc$libresoc.v:22068$624 + assign { } { } + assign $0\alu_alu0_alu_op__fn_unit[13:0] \alu_alu0_alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[13:0] + end + attribute \src "libresoc.v:22070.3-22071.79" + process $proc$libresoc.v:22070$625 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:22072.3-22073.75" + process $proc$libresoc.v:22072$626 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:22074.3-22075.63" + process $proc$libresoc.v:22074$627 + assign { } { } + assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:22076.3-22077.63" + process $proc$libresoc.v:22076$628 + assign { } { } + assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:22078.3-22079.63" + process $proc$libresoc.v:22078$629 + assign { } { } + assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:22080.3-22081.63" + process $proc$libresoc.v:22080$630 + assign { } { } + assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:22082.3-22083.69" + process $proc$libresoc.v:22082$631 + assign { } { } + assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:22084.3-22085.63" + process $proc$libresoc.v:22084$632 + assign { } { } + assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:22086.3-22087.71" + process $proc$libresoc.v:22086$633 + assign { } { } + assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:22088.3-22089.69" + process $proc$libresoc.v:22088$634 + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:22090.3-22091.73" + process $proc$libresoc.v:22090$635 + assign { } { } + assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:22092.3-22093.75" + process $proc$libresoc.v:22092$636 + assign { } { } + assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:22094.3-22095.67" + process $proc$libresoc.v:22094$637 + assign { } { } + assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:22096.3-22097.69" + process $proc$libresoc.v:22096$638 + assign { } { } + assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:22098.3-22099.67" + process $proc$libresoc.v:22098$639 + assign { } { } + assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:22100.3-22101.59" + process $proc$libresoc.v:22100$640 + assign { } { } + assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:22102.3-22103.39" + process $proc$libresoc.v:22102$641 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:22104.3-22105.39" + process $proc$libresoc.v:22104$642 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:22106.3-22107.39" + process $proc$libresoc.v:22106$643 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:22108.3-22109.39" + process $proc$libresoc.v:22108$644 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:22110.3-22111.39" + process $proc$libresoc.v:22110$645 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:22112.3-22113.39" + process $proc$libresoc.v:22112$646 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:22114.3-22115.39" + process $proc$libresoc.v:22114$647 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:22116.3-22117.39" + process $proc$libresoc.v:22116$648 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:22118.3-22119.41" + process $proc$libresoc.v:22118$649 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:22120.3-22121.41" + process $proc$libresoc.v:22120$650 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:22122.3-22123.37" + process $proc$libresoc.v:22122$651 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:22124.3-22125.40" + process $proc$libresoc.v:22124$652 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:22126.3-22127.25" + process $proc$libresoc.v:22126$653 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:22216.3-22225.6" + process $proc$libresoc.v:22216$654 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:22217.5-22217.29" + switch \initial + attribute \src "libresoc.v:22217.9-22217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:22226.3-22234.6" + process $proc$libresoc.v:22226$655 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:22227.5-22227.29" + switch \initial + attribute \src "libresoc.v:22227.9-22227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$657 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$657 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 + end + attribute \src "libresoc.v:22235.3-22243.6" + process $proc$libresoc.v:22235$658 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:22236.5-22236.29" + switch \initial + attribute \src "libresoc.v:22236.9-22236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$660 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$660 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 + end + attribute \src "libresoc.v:22244.3-22252.6" + process $proc$libresoc.v:22244$661 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:22245.5-22245.29" + switch \initial + attribute \src "libresoc.v:22245.9-22245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$663 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$663 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 + end + attribute \src "libresoc.v:22253.3-22261.6" + process $proc$libresoc.v:22253$664 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:22254.5-22254.29" + switch \initial + attribute \src "libresoc.v:22254.9-22254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$666 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$666 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 + end + attribute \src "libresoc.v:22262.3-22270.6" + process $proc$libresoc.v:22262$667 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:22263.5-22263.29" + switch \initial + attribute \src "libresoc.v:22263.9-22263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$669 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$669 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 + end + attribute \src "libresoc.v:22271.3-22279.6" + process $proc$libresoc.v:22271$670 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:22272.5-22272.29" + switch \initial + attribute \src "libresoc.v:22272.9-22272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$672 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$672 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 + end + attribute \src "libresoc.v:22280.3-22288.6" + process $proc$libresoc.v:22280$673 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:22281.5-22281.29" + switch \initial + attribute \src "libresoc.v:22281.9-22281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$675 4'0000 + case + assign $1\src_l_s_src$next[3:0]$675 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 + end + attribute \src "libresoc.v:22289.3-22297.6" + process $proc$libresoc.v:22289$676 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:22290.5-22290.29" + switch \initial + attribute \src "libresoc.v:22290.9-22290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$678 4'1111 + case + assign $1\src_l_r_src$next[3:0]$678 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 + end + attribute \src "libresoc.v:22298.3-22306.6" + process $proc$libresoc.v:22298$679 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:22299.5-22299.29" + switch \initial + attribute \src "libresoc.v:22299.9-22299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$681 5'00000 + case + assign $1\req_l_s_req$next[4:0]$681 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 + end + attribute \src "libresoc.v:22307.3-22315.6" + process $proc$libresoc.v:22307$682 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:22308.5-22308.29" + switch \initial + attribute \src "libresoc.v:22308.9-22308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$684 5'11111 + case + assign $1\req_l_r_req$next[4:0]$684 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 + end + attribute \src "libresoc.v:22316.3-22354.6" + process $proc$libresoc.v:22316$685 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + assign $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + assign $0\alu_alu0_alu_op__insn$next[31:0]$691 $1\alu_alu0_alu_op__insn$next[31:0]$709 + assign $0\alu_alu0_alu_op__insn_type$next[6:0]$692 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + assign $0\alu_alu0_alu_op__invert_in$next[0:0]$693 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + assign $0\alu_alu0_alu_op__invert_out$next[0:0]$694 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + assign $0\alu_alu0_alu_op__is_signed$next[0:0]$696 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__output_carry$next[0:0]$699 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + assign $0\alu_alu0_alu_op__zero_a$next[0:0]$703 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22317.5-22317.29" + switch \initial + attribute \src "libresoc.v:22317.9-22317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + case + assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len + assign $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data + assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok + assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry + assign $1\alu_alu0_alu_op__insn$next[31:0]$709 \alu_alu0_alu_op__insn + assign $1\alu_alu0_alu_op__insn_type$next[6:0]$710 \alu_alu0_alu_op__insn_type + assign $1\alu_alu0_alu_op__invert_in$next[0:0]$711 \alu_alu0_alu_op__invert_in + assign $1\alu_alu0_alu_op__invert_out$next[0:0]$712 \alu_alu0_alu_op__invert_out + assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 \alu_alu0_alu_op__is_32bit + assign $1\alu_alu0_alu_op__is_signed$next[0:0]$714 \alu_alu0_alu_op__is_signed + assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 \alu_alu0_alu_op__oe__oe + assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 \alu_alu0_alu_op__oe__ok + assign $1\alu_alu0_alu_op__output_carry$next[0:0]$717 \alu_alu0_alu_op__output_carry + assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 \alu_alu0_alu_op__rc__ok + assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 \alu_alu0_alu_op__rc__rc + assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 \alu_alu0_alu_op__write_cr0 + assign $1\alu_alu0_alu_op__zero_a$next[0:0]$721 \alu_alu0_alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 1'0 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 1'0 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 1'0 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 1'0 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 1'0 + case + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + end + sync always + update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 + update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$691 + update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + end + attribute \src "libresoc.v:22355.3-22376.6" + process $proc$libresoc.v:22355$728 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22356.5-22356.29" + switch \initial + attribute \src "libresoc.v:22356.9-22356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$732 $1\data_r0__o$next[63:0]$731 } { \o_ok \alu_alu0_o } + case + assign $1\data_r0__o$next[63:0]$731 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$732 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$734 $2\data_r0__o$next[63:0]$733 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$733 $1\data_r0__o$next[63:0]$731 + assign $2\data_r0__o_ok$next[0:0]$734 $1\data_r0__o_ok$next[0:0]$732 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$735 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$735 $2\data_r0__o_ok$next[0:0]$734 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$729 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 + end + attribute \src "libresoc.v:22377.3-22398.6" + process $proc$libresoc.v:22377$736 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22378.5-22378.29" + switch \initial + attribute \src "libresoc.v:22378.9-22378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$740 $1\data_r1__cr_a$next[3:0]$739 } { \cr_a_ok \alu_alu0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$739 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$740 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$742 $2\data_r1__cr_a$next[3:0]$741 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$741 $1\data_r1__cr_a$next[3:0]$739 + assign $2\data_r1__cr_a_ok$next[0:0]$742 $1\data_r1__cr_a_ok$next[0:0]$740 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$743 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$743 $2\data_r1__cr_a_ok$next[0:0]$742 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 + end + attribute \src "libresoc.v:22399.3-22420.6" + process $proc$libresoc.v:22399$744 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22400.5-22400.29" + switch \initial + attribute \src "libresoc.v:22400.9-22400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$748 $1\data_r2__xer_ca$next[1:0]$747 } { \xer_ca_ok \alu_alu0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$747 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$748 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$750 $2\data_r2__xer_ca$next[1:0]$749 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$749 $1\data_r2__xer_ca$next[1:0]$747 + assign $2\data_r2__xer_ca_ok$next[0:0]$750 $1\data_r2__xer_ca_ok$next[0:0]$748 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$751 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$751 $2\data_r2__xer_ca_ok$next[0:0]$750 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 + end + attribute \src "libresoc.v:22421.3-22442.6" + process $proc$libresoc.v:22421$752 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 + assign { } { } + assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22422.5-22422.29" + switch \initial + attribute \src "libresoc.v:22422.9-22422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_ov_ok$next[0:0]$756 $1\data_r3__xer_ov$next[1:0]$755 } { \xer_ov_ok \alu_alu0_xer_ov } + case + assign $1\data_r3__xer_ov$next[1:0]$755 \data_r3__xer_ov + assign $1\data_r3__xer_ov_ok$next[0:0]$756 \data_r3__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_ov_ok$next[0:0]$758 $2\data_r3__xer_ov$next[1:0]$757 } 3'000 + case + assign $2\data_r3__xer_ov$next[1:0]$757 $1\data_r3__xer_ov$next[1:0]$755 + assign $2\data_r3__xer_ov_ok$next[0:0]$758 $1\data_r3__xer_ov_ok$next[0:0]$756 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_ov_ok$next[0:0]$759 1'0 + case + assign $3\data_r3__xer_ov_ok$next[0:0]$759 $2\data_r3__xer_ov_ok$next[0:0]$758 + end + sync always + update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 + update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 + end + attribute \src "libresoc.v:22443.3-22464.6" + process $proc$libresoc.v:22443$760 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 + assign { } { } + assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:22444.5-22444.29" + switch \initial + attribute \src "libresoc.v:22444.9-22444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_so_ok$next[0:0]$764 $1\data_r4__xer_so$next[0:0]$763 } { \xer_so_ok \alu_alu0_xer_so } + case + assign $1\data_r4__xer_so$next[0:0]$763 \data_r4__xer_so + assign $1\data_r4__xer_so_ok$next[0:0]$764 \data_r4__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_so_ok$next[0:0]$766 $2\data_r4__xer_so$next[0:0]$765 } 2'00 + case + assign $2\data_r4__xer_so$next[0:0]$765 $1\data_r4__xer_so$next[0:0]$763 + assign $2\data_r4__xer_so_ok$next[0:0]$766 $1\data_r4__xer_so_ok$next[0:0]$764 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_so_ok$next[0:0]$767 1'0 + case + assign $3\data_r4__xer_so_ok$next[0:0]$767 $2\data_r4__xer_so_ok$next[0:0]$766 + end + sync always + update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 + update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 + end + attribute \src "libresoc.v:22465.3-22474.6" + process $proc$libresoc.v:22465$768 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:22466.5-22466.29" + switch \initial + attribute \src "libresoc.v:22466.9-22466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$770 \src_or_imm + case + assign $1\src_r0$next[63:0]$770 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$769 + end + attribute \src "libresoc.v:22475.3-22484.6" + process $proc$libresoc.v:22475$771 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:22476.5-22476.29" + switch \initial + attribute \src "libresoc.v:22476.9-22476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$773 \src_or_imm$88 + case + assign $1\src_r1$next[63:0]$773 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$772 + end + attribute \src "libresoc.v:22485.3-22494.6" + process $proc$libresoc.v:22485$774 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:22486.5-22486.29" + switch \initial + attribute \src "libresoc.v:22486.9-22486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$776 \src3_i + case + assign $1\src_r2$next[0:0]$776 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$775 + end + attribute \src "libresoc.v:22495.3-22504.6" + process $proc$libresoc.v:22495$777 + assign { } { } + assign { } { } + assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:22496.5-22496.29" + switch \initial + attribute \src "libresoc.v:22496.9-22496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[1:0]$779 \src4_i + case + assign $1\src_r3$next[1:0]$779 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[1:0]$778 + end + attribute \src "libresoc.v:22505.3-22513.6" + process $proc$libresoc.v:22505$780 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:22506.5-22506.29" + switch \initial + attribute \src "libresoc.v:22506.9-22506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$782 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$782 \$99 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 + end + attribute \src "libresoc.v:22514.3-22522.6" + process $proc$libresoc.v:22514$783 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:22515.5-22515.29" + switch \initial + attribute \src "libresoc.v:22515.9-22515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$785 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$785 \$101 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 + end + attribute \src "libresoc.v:22523.3-22532.6" + process $proc$libresoc.v:22523$786 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:22524.5-22524.29" + switch \initial + attribute \src "libresoc.v:22524.9-22524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:22533.3-22542.6" + process $proc$libresoc.v:22533$787 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:22534.5-22534.29" + switch \initial + attribute \src "libresoc.v:22534.9-22534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$131 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:22543.3-22552.6" + process $proc$libresoc.v:22543$788 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:22544.5-22544.29" + switch \initial + attribute \src "libresoc.v:22544.9-22544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:22553.3-22562.6" + process $proc$libresoc.v:22553$789 + assign { } { } + assign { } { } + assign $0\dest4_o[1:0] $1\dest4_o[1:0] + attribute \src "libresoc.v:22554.5-22554.29" + switch \initial + attribute \src "libresoc.v:22554.9-22554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[1:0] \data_r3__xer_ov + case + assign $1\dest4_o[1:0] 2'00 + end + sync always + update \dest4_o $0\dest4_o[1:0] + end + attribute \src "libresoc.v:22563.3-22572.6" + process $proc$libresoc.v:22563$790 + assign { } { } + assign { } { } + assign $0\dest5_o[0:0] $1\dest5_o[0:0] + attribute \src "libresoc.v:22564.5-22564.29" + switch \initial + attribute \src "libresoc.v:22564.9-22564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[0:0] \data_r4__xer_so + case + assign $1\dest5_o[0:0] 1'0 + end + sync always + update \dest5_o $0\dest5_o[0:0] + end + attribute \src "libresoc.v:22573.3-22581.6" + process $proc$libresoc.v:22573$791 + assign { } { } + assign { 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\enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 24 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 28 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 37 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len$20 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_alu_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok$7 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_alu_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ov$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ov_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 35 \xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 34 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:23536.5-23539.4" + cell \n \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23540.5-23543.4" + cell \p \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23544.9-23603.4" + cell \pipe1 \pipe1 + connect \alu_op__data_len \pipe1_alu_op__data_len + connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 + connect \alu_op__fn_unit \pipe1_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 + connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 + connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 + connect \alu_op__input_carry \pipe1_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 + connect \alu_op__insn \pipe1_alu_op__insn + connect \alu_op__insn$19 \pipe1_alu_op__insn$21 + connect \alu_op__insn_type \pipe1_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 + connect \alu_op__invert_in \pipe1_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 + connect \alu_op__invert_out \pipe1_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 + connect \alu_op__is_32bit \pipe1_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 + connect \alu_op__is_signed \pipe1_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 + connect \alu_op__oe__oe \pipe1_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 + connect \alu_op__oe__ok \pipe1_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 + connect \alu_op__output_carry \pipe1_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 + connect \alu_op__rc__ok \pipe1_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 + connect \alu_op__rc__rc \pipe1_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 + connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 + connect \alu_op__zero_a \pipe1_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$21 \pipe1_xer_ca$23 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_ov \pipe1_xer_ov + connect \xer_ov_ok \pipe1_xer_ov_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$20 \pipe1_xer_so$22 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23604.9-23669.4" + cell \pipe2 \pipe2 + connect \alu_op__data_len \pipe2_alu_op__data_len + connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 + connect \alu_op__fn_unit \pipe2_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 + connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 + connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 + connect \alu_op__input_carry \pipe2_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 + connect \alu_op__insn \pipe2_alu_op__insn + connect \alu_op__insn$19 \pipe2_alu_op__insn$42 + connect \alu_op__insn_type \pipe2_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 + connect \alu_op__invert_in \pipe2_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 + connect \alu_op__invert_out \pipe2_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 + connect \alu_op__is_32bit \pipe2_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 + connect \alu_op__is_signed \pipe2_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 + connect \alu_op__oe__oe \pipe2_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 + connect \alu_op__oe__ok \pipe2_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 + connect \alu_op__output_carry \pipe2_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 + connect \alu_op__rc__ok \pipe2_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 + connect \alu_op__rc__rc \pipe2_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 + connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 + connect \alu_op__zero_a \pipe2_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$22 \pipe2_cr_a$45 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$23 \pipe2_cr_a_ok$46 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$24 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$20 \pipe2_o$43 + connect \o_ok \pipe2_o_ok + connect \o_ok$21 \pipe2_o_ok$44 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$24 \pipe2_xer_ca$47 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 + connect \xer_ov \pipe2_xer_ov + connect \xer_ov$26 \pipe2_xer_ov$49 + connect \xer_ov_ok \pipe2_xer_ov_ok + connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 + connect \xer_so \pipe2_xer_so + connect \xer_so$28 \pipe2_xer_so$51 + connect \xer_so_ok \pipe2_xer_so_ok + connect \xer_so_ok$29 \pipe2_xer_so_ok$52 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } + connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } + connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } + connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } + connect \muxid$53 \pipe2_muxid$24 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$23 \xer_ca$2 + connect \pipe1_xer_so$22 \xer_so$1 + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:23701.1-24248.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" +attribute \generator "nMigen" +module \alu_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 10 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 22 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_br_op__fn_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_p_valid_i + attribute \module_not_derived 1 + attribute \src "libresoc.v:24190.10-24193.4" + cell \n$18 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24194.10-24197.4" + cell \p$17 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24198.13-24232.4" + cell \pipe$19 \pipe + connect \br_op__cia \pipe_br_op__cia + connect \br_op__cia$2 \pipe_br_op__cia$4 + connect \br_op__fn_unit \pipe_br_op__fn_unit + connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 + connect \br_op__imm_data__data \pipe_br_op__imm_data__data + connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 + connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 + connect \br_op__insn \pipe_br_op__insn + connect \br_op__insn$5 \pipe_br_op__insn$7 + connect \br_op__insn_type \pipe_br_op__insn_type + connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 + connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 + connect \br_op__lk \pipe_br_op__lk + connect \br_op__lk$8 \pipe_br_op__lk$10 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + end + connect \muxid 2'00 + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_a \cr_a + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:24252.1-24767.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" +attribute \generator "nMigen" +module \alu_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 12 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 16 \cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 17 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 18 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 8 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 9 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 11 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 15 \full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 10 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 20 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 19 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe_cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_cr_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \pipe_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \pipe_full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \module_not_derived 1 + attribute \src "libresoc.v:24713.9-24716.4" + cell \n$6 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24717.9-24720.4" + cell \p$5 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24721.8-24748.4" + cell \pipe \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \cr_a$6 \pipe_cr_a$8 + connect \cr_a_ok \pipe_cr_a_ok + connect \cr_b \pipe_cr_b + connect \cr_c \pipe_cr_c + connect \cr_op__fn_unit \pipe_cr_op__fn_unit + connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 + connect \cr_op__insn \pipe_cr_op__insn + connect \cr_op__insn$4 \pipe_cr_op__insn$6 + connect \cr_op__insn_type \pipe_cr_op__insn_type + connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 + connect \full_cr \pipe_full_cr + connect \full_cr$5 \pipe_full_cr$7 + connect \full_cr_ok \pipe_full_cr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } + connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + connect \muxid$9 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_c \cr_c + connect \pipe_cr_b \cr_b + connect \pipe_cr_a \cr_a$2 + connect \pipe_full_cr \full_cr$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:24771.1-26236.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" +attribute \generator "nMigen" +module \alu_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 35 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 24 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$88 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$75 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$89 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_end_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_end_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_end_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_end_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_end_logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_end_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_end_muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_end_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_so$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_middle_0_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_middle_0_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_middle_0_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_middle_0_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_middle_0_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_middle_0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_middle_0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_middle_0_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_middle_0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_middle_0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_middle_0_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_start_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_start_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_start_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len$19 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_start_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_start_logical_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_start_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_start_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 32 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:25992.10-25995.4" + cell \n$75 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25996.10-25999.4" + cell \p$74 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:26000.12-26063.4" + cell \pipe_end \pipe_end + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \div_by_zero \pipe_end_div_by_zero + connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 + connect \dividend_neg \pipe_end_dividend_neg + connect \divisor_neg \pipe_end_divisor_neg + connect \logical_op__data_len \pipe_end_logical_op__data_len + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 + connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 + connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 + connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 + connect \logical_op__input_carry \pipe_end_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 + connect \logical_op__insn \pipe_end_logical_op__insn + connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 + connect \logical_op__insn_type \pipe_end_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 + connect \logical_op__invert_in \pipe_end_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 + connect \logical_op__invert_out \pipe_end_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 + connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 + connect \logical_op__is_signed \pipe_end_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 + connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 + connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 + connect \logical_op__output_carry \pipe_end_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 + connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 + connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 + connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 + connect \logical_op__zero_a \pipe_end_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 + connect \muxid \pipe_end_muxid + connect \muxid$1 \pipe_end_muxid$51 + connect \n_ready_i \pipe_end_n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \p_ready_o \pipe_end_p_ready_o + connect \p_valid_i \pipe_end_p_valid_i + connect \quotient_root \pipe_end_quotient_root + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \remainder \pipe_end_remainder + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so \pipe_end_xer_so + connect \xer_so$20 \pipe_end_xer_so$70 + connect \xer_so_ok \pipe_end_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:26064.17-26130.4" + cell \pipe_middle_0 \pipe_middle_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \dividend \pipe_middle_0_dividend + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \muxid \pipe_middle_0_muxid + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \operation \pipe_middle_0_operation + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \quotient_root \pipe_middle_0_quotient_root + connect \ra \pipe_middle_0_ra + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb \pipe_middle_0_rb + connect \rb$21 \pipe_middle_0_rb$44 + connect \remainder \pipe_middle_0_remainder + connect \xer_so \pipe_middle_0_xer_so + connect \xer_so$22 \pipe_middle_0_xer_so$45 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:26131.14-26190.4" + cell \pipe_start \pipe_start + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_start_div_by_zero + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \dividend \pipe_start_dividend + connect \dividend_neg \pipe_start_dividend_neg + connect \divisor_neg \pipe_start_divisor_neg + connect \divisor_radicand \pipe_start_divisor_radicand + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 + connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__insn \pipe_start_logical_op__insn + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \muxid \pipe_start_muxid + connect \muxid$1 \pipe_start_muxid$2 + connect \n_ready_i \pipe_start_n_ready_i + connect \n_valid_o \pipe_start_n_valid_o + connect \operation \pipe_start_operation + connect \p_ready_o \pipe_start_p_ready_o + connect \p_valid_i \pipe_start_p_valid_i + connect \ra \pipe_start_ra + connect \ra$20 \pipe_start_ra$21 + connect \rb \pipe_start_rb + connect \rb$21 \pipe_start_rb$22 + connect \xer_so \pipe_start_xer_so + connect \xer_so$22 \pipe_start_xer_so$23 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } + connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } + connect \muxid$71 \pipe_end_muxid$51 + connect \pipe_end_n_ready_i \n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \pipe_start_xer_so$23 \xer_so$1 + connect \pipe_start_rb$22 \rb + connect \pipe_start_ra$21 \ra + connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \pipe_start_muxid$2 2'00 + connect \p_ready_o \pipe_start_p_ready_o + connect \pipe_start_p_valid_i \p_valid_i + connect \pipe_end_remainder \pipe_middle_0_remainder + connect \pipe_end_quotient_root \pipe_middle_0_quotient_root + connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 + connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 + connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 + connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 + connect \pipe_end_rb \pipe_middle_0_rb$44 + connect \pipe_end_ra \pipe_middle_0_ra$43 + connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + connect \pipe_end_muxid \pipe_middle_0_muxid$24 + connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o + connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o + connect \pipe_middle_0_operation \pipe_start_operation + connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + connect \pipe_middle_0_dividend \pipe_start_dividend + connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + connect \pipe_middle_0_xer_so \pipe_start_xer_so + connect \pipe_middle_0_rb \pipe_start_rb + connect \pipe_middle_0_ra \pipe_start_ra + connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + connect \pipe_middle_0_muxid \pipe_start_muxid + connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o +end +attribute \src "libresoc.v:26240.1-26298.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" +attribute \generator "nMigen" +module \alu_l + attribute \src "libresoc.v:26241.7-26241.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26286.3-26294.6" + wire $0\q_int$next[0:0]$852 + attribute \src "libresoc.v:26284.3-26285.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26286.3-26294.6" + wire $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:26265.7-26265.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26276.17-26276.96" + wire $and$libresoc.v:26276$842_Y + attribute \src "libresoc.v:26281.17-26281.96" + wire $and$libresoc.v:26281$847_Y + attribute \src "libresoc.v:26278.18-26278.93" + wire $not$libresoc.v:26278$844_Y + attribute \src "libresoc.v:26280.17-26280.92" + wire $not$libresoc.v:26280$846_Y + attribute \src "libresoc.v:26283.17-26283.92" + wire $not$libresoc.v:26283$849_Y + attribute \src "libresoc.v:26277.18-26277.98" + wire $or$libresoc.v:26277$843_Y + attribute \src "libresoc.v:26279.18-26279.99" + wire $or$libresoc.v:26279$845_Y + attribute \src "libresoc.v:26282.17-26282.97" + wire $or$libresoc.v:26282$848_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26241.7-26241.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26276$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26276$842_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26281$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26281$847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26278$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26278$844_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26280$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26280$846_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26283$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26283$849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26277$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26277$843_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26279$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26279$845_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26282$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26282$848_Y + end + attribute \src "libresoc.v:26241.7-26241.20" + process $proc$libresoc.v:26241$854 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26265.7-26265.19" + process $proc$libresoc.v:26265$855 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26284.3-26285.27" + process $proc$libresoc.v:26284$850 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26286.3-26294.6" + process $proc$libresoc.v:26286$851 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:26287.5-26287.29" + switch \initial + attribute \src "libresoc.v:26287.9-26287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$853 1'0 + case + assign $1\q_int$next[0:0]$853 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$852 + end + connect \$9 $and$libresoc.v:26276$842_Y + connect \$11 $or$libresoc.v:26277$843_Y + connect \$13 $not$libresoc.v:26278$844_Y + connect \$15 $or$libresoc.v:26279$845_Y + connect \$1 $not$libresoc.v:26280$846_Y + connect \$3 $and$libresoc.v:26281$847_Y + connect \$5 $or$libresoc.v:26282$848_Y + connect \$7 $not$libresoc.v:26283$849_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26302.1-26360.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" +attribute \generator "nMigen" +module \alu_l$107 + attribute \src "libresoc.v:26303.7-26303.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26348.3-26356.6" + wire $0\q_int$next[0:0]$866 + attribute \src "libresoc.v:26346.3-26347.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26348.3-26356.6" + wire $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:26327.7-26327.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26338.17-26338.96" + wire $and$libresoc.v:26338$856_Y + attribute \src "libresoc.v:26343.17-26343.96" + wire $and$libresoc.v:26343$861_Y + attribute \src "libresoc.v:26340.18-26340.93" + wire $not$libresoc.v:26340$858_Y + attribute \src "libresoc.v:26342.17-26342.92" + wire $not$libresoc.v:26342$860_Y + attribute \src "libresoc.v:26345.17-26345.92" + wire $not$libresoc.v:26345$863_Y + attribute \src "libresoc.v:26339.18-26339.98" + wire $or$libresoc.v:26339$857_Y + attribute \src "libresoc.v:26341.18-26341.99" + wire $or$libresoc.v:26341$859_Y + attribute \src "libresoc.v:26344.17-26344.97" + wire $or$libresoc.v:26344$862_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26303.7-26303.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26338$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26338$856_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26343$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26343$861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26340$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26340$858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26342$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26342$860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26345$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26345$863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26339$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26339$857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26341$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26341$859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26344$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26344$862_Y + end + attribute \src "libresoc.v:26303.7-26303.20" + process $proc$libresoc.v:26303$868 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26327.7-26327.19" + process $proc$libresoc.v:26327$869 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26346.3-26347.27" + process $proc$libresoc.v:26346$864 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26348.3-26356.6" + process $proc$libresoc.v:26348$865 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:26349.5-26349.29" + switch \initial + attribute \src "libresoc.v:26349.9-26349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$867 1'0 + case + assign $1\q_int$next[0:0]$867 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$866 + end + connect \$9 $and$libresoc.v:26338$856_Y + connect \$11 $or$libresoc.v:26339$857_Y + connect \$13 $not$libresoc.v:26340$858_Y + connect \$15 $or$libresoc.v:26341$859_Y + connect \$1 $not$libresoc.v:26342$860_Y + connect \$3 $and$libresoc.v:26343$861_Y + connect \$5 $or$libresoc.v:26344$862_Y + connect \$7 $not$libresoc.v:26345$863_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26364.1-26422.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" +attribute \generator "nMigen" +module \alu_l$125 + attribute \src "libresoc.v:26365.7-26365.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26410.3-26418.6" + wire $0\q_int$next[0:0]$880 + attribute \src "libresoc.v:26408.3-26409.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26410.3-26418.6" + wire $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26389.7-26389.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26400.17-26400.96" + wire $and$libresoc.v:26400$870_Y + attribute \src "libresoc.v:26405.17-26405.96" + wire $and$libresoc.v:26405$875_Y + attribute \src "libresoc.v:26402.18-26402.93" + wire $not$libresoc.v:26402$872_Y + attribute \src "libresoc.v:26404.17-26404.92" + wire $not$libresoc.v:26404$874_Y + attribute \src "libresoc.v:26407.17-26407.92" + wire $not$libresoc.v:26407$877_Y + attribute \src "libresoc.v:26401.18-26401.98" + wire $or$libresoc.v:26401$871_Y + attribute \src "libresoc.v:26403.18-26403.99" + wire $or$libresoc.v:26403$873_Y + attribute \src "libresoc.v:26406.17-26406.97" + wire $or$libresoc.v:26406$876_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26365.7-26365.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26400$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26400$870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26405$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26405$875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26402$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26402$872_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26404$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26404$874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26407$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26407$877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26401$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26401$871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26403$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26403$873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26406$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26406$876_Y + end + attribute \src "libresoc.v:26365.7-26365.20" + process $proc$libresoc.v:26365$882 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26389.7-26389.19" + process $proc$libresoc.v:26389$883 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26408.3-26409.27" + process $proc$libresoc.v:26408$878 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26410.3-26418.6" + process $proc$libresoc.v:26410$879 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26411.5-26411.29" + switch \initial + attribute \src "libresoc.v:26411.9-26411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$881 1'0 + case + assign $1\q_int$next[0:0]$881 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$880 + end + connect \$9 $and$libresoc.v:26400$870_Y + connect \$11 $or$libresoc.v:26401$871_Y + connect \$13 $not$libresoc.v:26402$872_Y + connect \$15 $or$libresoc.v:26403$873_Y + connect \$1 $not$libresoc.v:26404$874_Y + connect \$3 $and$libresoc.v:26405$875_Y + connect \$5 $or$libresoc.v:26406$876_Y + connect \$7 $not$libresoc.v:26407$877_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26426.1-26484.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" +attribute \generator "nMigen" +module \alu_l$128 + attribute \src "libresoc.v:26427.7-26427.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26472.3-26480.6" + wire $0\q_int$next[0:0]$894 + attribute \src "libresoc.v:26470.3-26471.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26472.3-26480.6" + wire $1\q_int$next[0:0]$895 + attribute \src "libresoc.v:26451.7-26451.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26462.17-26462.96" + wire $and$libresoc.v:26462$884_Y + attribute \src "libresoc.v:26467.17-26467.96" + wire $and$libresoc.v:26467$889_Y + attribute \src "libresoc.v:26464.18-26464.93" + wire $not$libresoc.v:26464$886_Y + attribute \src "libresoc.v:26466.17-26466.92" + wire $not$libresoc.v:26466$888_Y + attribute \src "libresoc.v:26469.17-26469.92" + wire $not$libresoc.v:26469$891_Y + attribute \src "libresoc.v:26463.18-26463.98" + wire $or$libresoc.v:26463$885_Y + attribute \src "libresoc.v:26465.18-26465.99" + wire $or$libresoc.v:26465$887_Y + attribute \src "libresoc.v:26468.17-26468.97" + wire $or$libresoc.v:26468$890_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26427.7-26427.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26462$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26462$884_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26467$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26467$889_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26464$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26464$886_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26466$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26466$888_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26469$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26469$891_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26463$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26463$885_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26465$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26465$887_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26468$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26468$890_Y + end + attribute \src "libresoc.v:26427.7-26427.20" + process $proc$libresoc.v:26427$896 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26451.7-26451.19" + process $proc$libresoc.v:26451$897 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + 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connect \$15 $or$libresoc.v:26465$887_Y + connect \$1 $not$libresoc.v:26466$888_Y + connect \$3 $and$libresoc.v:26467$889_Y + connect \$5 $or$libresoc.v:26468$890_Y + connect \$7 $not$libresoc.v:26469$891_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26488.1-26546.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" +attribute \generator "nMigen" +module \alu_l$16 + attribute \src "libresoc.v:26489.7-26489.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26534.3-26542.6" + wire $0\q_int$next[0:0]$908 + attribute \src "libresoc.v:26532.3-26533.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26534.3-26542.6" + wire $1\q_int$next[0:0]$909 + attribute \src "libresoc.v:26513.7-26513.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26524.17-26524.96" + wire $and$libresoc.v:26524$898_Y + attribute \src "libresoc.v:26529.17-26529.96" + wire $and$libresoc.v:26529$903_Y + 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\src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26524$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26524$898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26529$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26529$903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26526$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26526$900_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26528$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26528$902_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26531$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26531$905_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26525$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26525$899_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26527$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26527$901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26530$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26530$904_Y + end + attribute \src "libresoc.v:26489.7-26489.20" + process $proc$libresoc.v:26489$910 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26513.7-26513.19" + process $proc$libresoc.v:26513$911 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26532.3-26533.27" + process $proc$libresoc.v:26532$906 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26534.3-26542.6" + process $proc$libresoc.v:26534$907 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 + attribute \src "libresoc.v:26535.5-26535.29" + switch \initial + attribute \src "libresoc.v:26535.9-26535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$909 1'0 + case + assign $1\q_int$next[0:0]$909 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$908 + end + connect \$9 $and$libresoc.v:26524$898_Y + connect \$11 $or$libresoc.v:26525$899_Y + connect \$13 $not$libresoc.v:26526$900_Y + connect \$15 $or$libresoc.v:26527$901_Y + connect \$1 $not$libresoc.v:26528$902_Y + connect \$3 $and$libresoc.v:26529$903_Y + connect \$5 $or$libresoc.v:26530$904_Y + connect \$7 $not$libresoc.v:26531$905_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26550.1-26608.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" +attribute \generator "nMigen" +module \alu_l$29 + attribute \src "libresoc.v:26551.7-26551.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26596.3-26604.6" + wire $0\q_int$next[0:0]$922 + attribute \src "libresoc.v:26594.3-26595.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26596.3-26604.6" + wire $1\q_int$next[0:0]$923 + attribute \src "libresoc.v:26575.7-26575.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26586.17-26586.96" + wire $and$libresoc.v:26586$912_Y + attribute \src "libresoc.v:26591.17-26591.96" + wire $and$libresoc.v:26591$917_Y + attribute \src "libresoc.v:26588.18-26588.93" + wire $not$libresoc.v:26588$914_Y + attribute \src "libresoc.v:26590.17-26590.92" + wire $not$libresoc.v:26590$916_Y + attribute \src "libresoc.v:26593.17-26593.92" + wire $not$libresoc.v:26593$919_Y + attribute \src "libresoc.v:26587.18-26587.98" + wire $or$libresoc.v:26587$913_Y + attribute \src "libresoc.v:26589.18-26589.99" + wire $or$libresoc.v:26589$915_Y + attribute \src "libresoc.v:26592.17-26592.97" + wire $or$libresoc.v:26592$918_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26551.7-26551.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26586$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26586$912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26591$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26591$917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26588$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26588$914_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26590$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26590$916_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26593$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26593$919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26587$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26587$913_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26589$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26589$915_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26592$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26592$918_Y + end + attribute \src "libresoc.v:26551.7-26551.20" + process $proc$libresoc.v:26551$924 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26575.7-26575.19" + process $proc$libresoc.v:26575$925 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26594.3-26595.27" + process $proc$libresoc.v:26594$920 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26596.3-26604.6" + process $proc$libresoc.v:26596$921 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 + attribute \src "libresoc.v:26597.5-26597.29" + switch \initial + attribute \src "libresoc.v:26597.9-26597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$923 1'0 + case + assign $1\q_int$next[0:0]$923 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$922 + end + connect \$9 $and$libresoc.v:26586$912_Y + connect \$11 $or$libresoc.v:26587$913_Y + connect \$13 $not$libresoc.v:26588$914_Y + connect \$15 $or$libresoc.v:26589$915_Y + connect \$1 $not$libresoc.v:26590$916_Y + connect \$3 $and$libresoc.v:26591$917_Y + connect \$5 $or$libresoc.v:26592$918_Y + connect \$7 $not$libresoc.v:26593$919_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26612.1-26670.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" +attribute \generator "nMigen" +module \alu_l$45 + attribute \src "libresoc.v:26613.7-26613.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26658.3-26666.6" + wire $0\q_int$next[0:0]$936 + attribute \src "libresoc.v:26656.3-26657.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26658.3-26666.6" + wire $1\q_int$next[0:0]$937 + attribute \src "libresoc.v:26637.7-26637.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26648.17-26648.96" + wire $and$libresoc.v:26648$926_Y + attribute \src "libresoc.v:26653.17-26653.96" + wire $and$libresoc.v:26653$931_Y + attribute \src "libresoc.v:26650.18-26650.93" + wire $not$libresoc.v:26650$928_Y + attribute \src "libresoc.v:26652.17-26652.92" + wire $not$libresoc.v:26652$930_Y + attribute \src "libresoc.v:26655.17-26655.92" + wire $not$libresoc.v:26655$933_Y + attribute \src "libresoc.v:26649.18-26649.98" + wire $or$libresoc.v:26649$927_Y + attribute \src "libresoc.v:26651.18-26651.99" + wire $or$libresoc.v:26651$929_Y + attribute \src "libresoc.v:26654.17-26654.97" + wire $or$libresoc.v:26654$932_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26613.7-26613.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26648$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26648$926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26653$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26653$931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26650$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26650$928_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26652$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26652$930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26655$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26655$933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26649$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26649$927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26651$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26651$929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26654$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26654$932_Y + end + attribute \src "libresoc.v:26613.7-26613.20" + process $proc$libresoc.v:26613$938 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26637.7-26637.19" + process $proc$libresoc.v:26637$939 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26656.3-26657.27" + process $proc$libresoc.v:26656$934 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26658.3-26666.6" + process $proc$libresoc.v:26658$935 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 + attribute \src "libresoc.v:26659.5-26659.29" + switch \initial + attribute \src "libresoc.v:26659.9-26659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$937 1'0 + case + assign $1\q_int$next[0:0]$937 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$936 + end + connect \$9 $and$libresoc.v:26648$926_Y + connect \$11 $or$libresoc.v:26649$927_Y + connect \$13 $not$libresoc.v:26650$928_Y + connect \$15 $or$libresoc.v:26651$929_Y + connect \$1 $not$libresoc.v:26652$930_Y + connect \$3 $and$libresoc.v:26653$931_Y + connect \$5 $or$libresoc.v:26654$932_Y + connect \$7 $not$libresoc.v:26655$933_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26674.1-26732.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" +attribute \generator "nMigen" +module \alu_l$61 + attribute \src "libresoc.v:26675.7-26675.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26720.3-26728.6" + wire $0\q_int$next[0:0]$950 + attribute \src "libresoc.v:26718.3-26719.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26720.3-26728.6" + wire $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26699.7-26699.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26710.17-26710.96" + wire $and$libresoc.v:26710$940_Y + attribute \src "libresoc.v:26715.17-26715.96" + wire $and$libresoc.v:26715$945_Y + attribute \src "libresoc.v:26712.18-26712.93" + wire $not$libresoc.v:26712$942_Y + attribute \src "libresoc.v:26714.17-26714.92" + wire $not$libresoc.v:26714$944_Y + attribute \src "libresoc.v:26717.17-26717.92" + wire $not$libresoc.v:26717$947_Y + attribute \src "libresoc.v:26711.18-26711.98" + wire $or$libresoc.v:26711$941_Y + attribute \src "libresoc.v:26713.18-26713.99" + wire $or$libresoc.v:26713$943_Y + attribute \src "libresoc.v:26716.17-26716.97" + wire $or$libresoc.v:26716$946_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26675.7-26675.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26710$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26710$940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26715$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26715$945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26712$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26712$942_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26714$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26714$944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26717$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26717$947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26711$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26711$941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26713$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26713$943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26716$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26716$946_Y + end + attribute \src "libresoc.v:26675.7-26675.20" + process $proc$libresoc.v:26675$952 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26699.7-26699.19" + process $proc$libresoc.v:26699$953 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26718.3-26719.27" + process $proc$libresoc.v:26718$948 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26720.3-26728.6" + process $proc$libresoc.v:26720$949 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26721.5-26721.29" + switch \initial + attribute \src "libresoc.v:26721.9-26721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$951 1'0 + case + assign $1\q_int$next[0:0]$951 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$950 + end + connect \$9 $and$libresoc.v:26710$940_Y + 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$and$libresoc.v:26772$954_Y + attribute \src "libresoc.v:26777.17-26777.96" + wire $and$libresoc.v:26777$959_Y + attribute \src "libresoc.v:26774.18-26774.93" + wire $not$libresoc.v:26774$956_Y + attribute \src "libresoc.v:26776.17-26776.92" + wire $not$libresoc.v:26776$958_Y + attribute \src "libresoc.v:26779.17-26779.92" + wire $not$libresoc.v:26779$961_Y + attribute \src "libresoc.v:26773.18-26773.98" + wire $or$libresoc.v:26773$955_Y + attribute \src "libresoc.v:26775.18-26775.99" + wire $or$libresoc.v:26775$957_Y + attribute \src "libresoc.v:26778.17-26778.97" + wire $or$libresoc.v:26778$960_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src 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"OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe1_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe1_logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe1_muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \logical_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \logical_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \logical_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \logical_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \logical_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \logical_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \logical_pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_cr_a_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe2_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe2_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \logical_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \logical_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \logical_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \logical_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 5 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 4 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 28 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:27733.17-27787.4" + cell \logical_pipe1 \logical_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe1_cr_a + connect \cr_a_ok \logical_pipe1_cr_a_ok + connect \logical_op__data_len \logical_pipe1_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 + connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 + connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 + connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 + connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 + connect \logical_op__insn \logical_pipe1_logical_op__insn + connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 + connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 + connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 + connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 + connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 + connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 + connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 + connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 + connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 + connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 + connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 + connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 + connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 + connect \muxid \logical_pipe1_muxid + connect \muxid$1 \logical_pipe1_muxid$1 + connect \n_ready_i \logical_pipe1_n_ready_i + connect \n_valid_o \logical_pipe1_n_valid_o + connect \o \logical_pipe1_o + connect \o_ok \logical_pipe1_o_ok + connect \p_ready_o \logical_pipe1_p_ready_o + connect \p_valid_i \logical_pipe1_p_valid_i + connect \ra \logical_pipe1_ra + connect \rb \logical_pipe1_rb + connect \xer_so \logical_pipe1_xer_so + connect \xer_so$20 \logical_pipe1_xer_so$20 + connect \xer_so_ok \logical_pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27788.17-27843.4" + cell \logical_pipe2 \logical_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe2_cr_a + connect \cr_a$22 \logical_pipe2_cr_a$42 + connect \cr_a_ok \logical_pipe2_cr_a_ok + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 + connect \logical_op__data_len \logical_pipe2_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 + connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 + connect \logical_op__insn \logical_pipe2_logical_op__insn + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 + connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 + connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 + connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 + connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 + connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 + connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 + connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 + connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 + connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 + connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 + connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 + connect \muxid \logical_pipe2_muxid + connect \muxid$1 \logical_pipe2_muxid$21 + connect \n_ready_i \logical_pipe2_n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \o \logical_pipe2_o + connect \o$20 \logical_pipe2_o$40 + connect \o_ok \logical_pipe2_o_ok + connect \o_ok$21 \logical_pipe2_o_ok$41 + connect \p_ready_o \logical_pipe2_p_ready_o + connect \p_valid_i \logical_pipe2_p_valid_i + connect \xer_so \logical_pipe2_xer_so + connect \xer_so_ok \logical_pipe2_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27844.10-27847.4" + cell \n$47 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27848.10-27851.4" + cell \p$46 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } + connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } + connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } + connect \muxid$44 \logical_pipe2_muxid$21 + connect \logical_pipe2_n_ready_i \n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \logical_pipe1_xer_so$20 \xer_so + connect \logical_pipe1_rb \rb + connect \logical_pipe1_ra \ra + connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \logical_pipe1_muxid$1 2'00 + connect \p_ready_o \logical_pipe1_p_ready_o + connect \logical_pipe1_p_valid_i \p_valid_i + connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } + connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } + connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } + connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } + connect \logical_pipe2_muxid \logical_pipe1_muxid + connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o + connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o +end +attribute \src "libresoc.v:27877.1-29094.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" +attribute \generator "nMigen" +module \alu_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$58 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe1_mul_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \mul_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \mul_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \mul_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \mul_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so$17 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe2_mul_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe2_muxid$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \mul_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \mul_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe2_neg_res$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe2_neg_res32$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \mul_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \mul_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \mul_pipe3_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe3_mul_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn$46 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe3_muxid$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \mul_pipe3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \mul_pipe3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe3_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \mul_pipe3_o$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \mul_pipe3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \mul_pipe3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \mul_pipe3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 26 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:28922.13-28963.4" + cell \mul_pipe1 \mul_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 + connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 + connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 + connect \mul_op__insn \mul_pipe1_mul_op__insn + connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 + connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 + connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 + connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 + connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 + connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 + connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 + connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 + connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 + connect \muxid \mul_pipe1_muxid + connect \muxid$1 \mul_pipe1_muxid$2 + connect \n_ready_i \mul_pipe1_n_ready_i + connect \n_valid_o \mul_pipe1_n_valid_o + connect \neg_res \mul_pipe1_neg_res + connect \neg_res32 \mul_pipe1_neg_res32 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \p_valid_i \mul_pipe1_p_valid_i + connect \ra \mul_pipe1_ra + connect \ra$14 \mul_pipe1_ra$15 + connect \rb \mul_pipe1_rb + connect \rb$15 \mul_pipe1_rb$16 + connect \xer_so \mul_pipe1_xer_so + connect \xer_so$16 \mul_pipe1_xer_so$17 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28964.13-29006.4" + cell \mul_pipe2 \mul_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 + connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 + connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 + connect \mul_op__insn \mul_pipe2_mul_op__insn + connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 + connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 + connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 + connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 + connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 + connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 + connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 + connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 + connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 + connect \muxid \mul_pipe2_muxid + connect \muxid$1 \mul_pipe2_muxid$18 + connect \n_ready_i \mul_pipe2_n_ready_i + connect \n_valid_o \mul_pipe2_n_valid_o + connect \neg_res \mul_pipe2_neg_res + connect \neg_res$15 \mul_pipe2_neg_res$32 + connect \neg_res32 \mul_pipe2_neg_res32 + connect \neg_res32$16 \mul_pipe2_neg_res32$33 + connect \o \mul_pipe2_o + connect \p_ready_o \mul_pipe2_p_ready_o + connect \p_valid_i \mul_pipe2_p_valid_i + connect \ra \mul_pipe2_ra + connect \rb \mul_pipe2_rb + connect \xer_so \mul_pipe2_xer_so + connect \xer_so$14 \mul_pipe2_xer_so$31 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29007.13-29052.4" + cell \mul_pipe3 \mul_pipe3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \mul_pipe3_cr_a + connect \cr_a_ok \mul_pipe3_cr_a_ok + connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 + connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 + connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 + connect \mul_op__insn \mul_pipe3_mul_op__insn + connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 + connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 + connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 + connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 + connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 + connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 + connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 + connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 + connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 + connect \muxid \mul_pipe3_muxid + connect \muxid$1 \mul_pipe3_muxid$34 + connect \n_ready_i \mul_pipe3_n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \neg_res \mul_pipe3_neg_res + connect \neg_res32 \mul_pipe3_neg_res32 + connect \o \mul_pipe3_o + connect \o$14 \mul_pipe3_o$47 + connect \o_ok \mul_pipe3_o_ok + connect \p_ready_o \mul_pipe3_p_ready_o + connect \p_valid_i \mul_pipe3_p_valid_i + connect \xer_ov \mul_pipe3_xer_ov + connect \xer_ov_ok \mul_pipe3_xer_ov_ok + connect \xer_so \mul_pipe3_xer_so + connect \xer_so$15 \mul_pipe3_xer_so$48 + connect \xer_so_ok \mul_pipe3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29053.10-29056.4" + cell \n$92 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29057.10-29060.4" + cell \p$91 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } + connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } + connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + connect \muxid$49 \mul_pipe3_muxid$34 + connect \mul_pipe3_n_ready_i \n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \mul_pipe1_xer_so$17 \xer_so$1 + connect \mul_pipe1_rb$16 \rb + connect \mul_pipe1_ra$15 \ra + connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul_pipe1_muxid$2 2'00 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \mul_pipe1_p_valid_i \p_valid_i + connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 + connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 + connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 + connect \mul_pipe3_o \mul_pipe2_o + connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + connect \mul_pipe3_muxid \mul_pipe2_muxid$18 + connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + connect \mul_pipe2_neg_res \mul_pipe1_neg_res + connect \mul_pipe2_xer_so \mul_pipe1_xer_so + connect \mul_pipe2_rb \mul_pipe1_rb + connect \mul_pipe2_ra \mul_pipe1_ra + connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + connect \mul_pipe2_muxid \mul_pipe1_muxid + connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o + connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o +end +attribute \src "libresoc.v:29098.1-30131.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" +attribute \generator "nMigen" +module \alu_shift_rot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 33 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 32 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rc + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_sr_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe2_p_valid_i + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_sr_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 28 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 29 \rc + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 8 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$50 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 31 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 30 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:29983.11-29986.4" + cell \n$109 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29987.11-29990.4" + cell \p$108 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29991.15-30047.4" + cell \pipe1$110 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$2 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \rc \pipe1_rc + connect \sr_op__fn_unit \pipe1_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 + connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 + connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 + connect \sr_op__input_carry \pipe1_sr_op__input_carry + connect \sr_op__input_carry$12 \pipe1_sr_op__input_carry$13 + connect \sr_op__input_cr \pipe1_sr_op__input_cr + connect \sr_op__input_cr$14 \pipe1_sr_op__input_cr$15 + connect \sr_op__insn \pipe1_sr_op__insn + connect \sr_op__insn$18 \pipe1_sr_op__insn$19 + connect \sr_op__insn_type \pipe1_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__invert_in \pipe1_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe1_sr_op__invert_in$12 + connect \sr_op__is_32bit \pipe1_sr_op__is_32bit + connect \sr_op__is_32bit$16 \pipe1_sr_op__is_32bit$17 + connect \sr_op__is_signed \pipe1_sr_op__is_signed + connect \sr_op__is_signed$17 \pipe1_sr_op__is_signed$18 + connect \sr_op__oe__oe \pipe1_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 + connect \sr_op__oe__ok \pipe1_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 + connect \sr_op__output_carry \pipe1_sr_op__output_carry + connect \sr_op__output_carry$13 \pipe1_sr_op__output_carry$14 + connect \sr_op__output_cr \pipe1_sr_op__output_cr + connect \sr_op__output_cr$15 \pipe1_sr_op__output_cr$16 + connect \sr_op__rc__ok \pipe1_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 + connect \sr_op__rc__rc \pipe1_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 + connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$20 \pipe1_xer_ca$21 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$19 \pipe1_xer_so$20 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30048.15-30105.4" + cell \pipe2$115 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$21 \pipe2_cr_a$42 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$22 \pipe2_cr_a_ok$43 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$22 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$19 \pipe2_o$40 + connect \o_ok \pipe2_o_ok + connect \o_ok$20 \pipe2_o_ok$41 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \sr_op__fn_unit \pipe2_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$24 + connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$25 + connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$26 + connect \sr_op__input_carry \pipe2_sr_op__input_carry + connect \sr_op__input_carry$12 \pipe2_sr_op__input_carry$33 + connect \sr_op__input_cr \pipe2_sr_op__input_cr + connect \sr_op__input_cr$14 \pipe2_sr_op__input_cr$35 + connect \sr_op__insn \pipe2_sr_op__insn + connect \sr_op__insn$18 \pipe2_sr_op__insn$39 + connect \sr_op__insn_type \pipe2_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$23 + connect \sr_op__invert_in \pipe2_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe2_sr_op__invert_in$32 + connect \sr_op__is_32bit \pipe2_sr_op__is_32bit + connect \sr_op__is_32bit$16 \pipe2_sr_op__is_32bit$37 + connect \sr_op__is_signed \pipe2_sr_op__is_signed + connect \sr_op__is_signed$17 \pipe2_sr_op__is_signed$38 + connect \sr_op__oe__oe \pipe2_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$29 + connect \sr_op__oe__ok \pipe2_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$30 + connect \sr_op__output_carry \pipe2_sr_op__output_carry + connect \sr_op__output_carry$13 \pipe2_sr_op__output_carry$34 + connect \sr_op__output_cr \pipe2_sr_op__output_cr + connect \sr_op__output_cr$15 \pipe2_sr_op__output_cr$36 + connect \sr_op__rc__ok \pipe2_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$28 + connect \sr_op__rc__rc \pipe2_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$27 + connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$31 + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$23 \pipe2_xer_ca$44 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$24 \pipe2_xer_ca_ok$45 + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$45 \pipe2_xer_ca$44 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$43 \pipe2_cr_a$42 } + connect { \o_ok \o } { \pipe2_o_ok$41 \pipe2_o$40 } + connect { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 \sr_op__invert_in$56 \sr_op__write_cr0$55 \sr_op__oe__ok$54 \sr_op__oe__oe$53 \sr_op__rc__ok$52 \sr_op__rc__rc$51 \sr_op__imm_data__ok$50 \sr_op__imm_data__data$49 \sr_op__fn_unit$48 \sr_op__insn_type$47 } { \pipe2_sr_op__insn$39 \pipe2_sr_op__is_signed$38 \pipe2_sr_op__is_32bit$37 \pipe2_sr_op__output_cr$36 \pipe2_sr_op__input_cr$35 \pipe2_sr_op__output_carry$34 \pipe2_sr_op__input_carry$33 \pipe2_sr_op__invert_in$32 \pipe2_sr_op__write_cr0$31 \pipe2_sr_op__oe__ok$30 \pipe2_sr_op__oe__oe$29 \pipe2_sr_op__rc__ok$28 \pipe2_sr_op__rc__rc$27 \pipe2_sr_op__imm_data__ok$26 \pipe2_sr_op__imm_data__data$25 \pipe2_sr_op__fn_unit$24 \pipe2_sr_op__insn_type$23 } + connect \muxid$46 \pipe2_muxid$22 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$21 \xer_ca$1 + connect \pipe1_xer_so$20 \xer_so + connect \pipe1_rc \rc + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_sr_op__insn$19 \pipe1_sr_op__is_signed$18 \pipe1_sr_op__is_32bit$17 \pipe1_sr_op__output_cr$16 \pipe1_sr_op__input_cr$15 \pipe1_sr_op__output_carry$14 \pipe1_sr_op__input_carry$13 \pipe1_sr_op__invert_in$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \pipe1_muxid$2 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__invert_in \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__invert_in \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:30135.1-30693.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" +attribute \generator "nMigen" +module \alu_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 9 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 8 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_spr_op__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_xer_ov$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_so$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 15 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 21 \spr1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 11 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 10 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 19 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 25 \xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 18 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:30628.10-30631.4" + cell \n$63 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30632.10-30635.4" + cell \p$62 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30636.13-30671.4" + cell \pipe$64 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$7 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$6 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \spr_op__fn_unit \pipe_spr_op__fn_unit + connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 + connect \spr_op__insn \pipe_spr_op__insn + connect \spr_op__insn$4 \pipe_spr_op__insn$9 + connect \spr_op__insn_type \pipe_spr_op__insn_type + connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 + connect \spr_op__is_32bit \pipe_spr_op__is_32bit + connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 + connect \xer_ca \pipe_xer_ca + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok + connect \xer_ov \pipe_xer_ov + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_so \pipe_xer_so + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } + connect \muxid$16 \pipe_muxid$6 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_xer_ca \xer_ca$5 + connect \pipe_xer_ov \xer_ov$4 + connect \pipe_xer_so \xer_so$3 + connect \pipe_fast1 \fast1$2 + connect \pipe_spr1 \spr1$1 + connect \pipe_ra \ra + connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:30697.1-31570.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" +attribute \generator "nMigen" +module \alu_trap0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 19 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast1$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__cia$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_trap_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_trap_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_trap_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_trap_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__ldst_exc$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__msr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_trap_op__trapaddr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__traptype$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_fast2$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__cia$22 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_trap_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_trap_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 13 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$34 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 10 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 11 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$32 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 17 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 12 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 16 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 15 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$36 + attribute \module_not_derived 1 + attribute \src "libresoc.v:31458.10-31461.4" + cell \n$31 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31462.10-31465.4" + cell \p$30 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31466.14-31501.4" + cell \pipe1$32 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe1_fast1 + connect \fast1$13 \pipe1_fast1$15 + connect \fast2 \pipe1_fast2 + connect \fast2$14 \pipe1_fast2$16 + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \ra$11 \pipe1_ra$13 + connect \rb \pipe1_rb + connect \rb$12 \pipe1_rb$14 + connect \trap_op__cia \pipe1_trap_op__cia + connect \trap_op__cia$6 \pipe1_trap_op__cia$8 + connect \trap_op__fn_unit \pipe1_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe1_trap_op__fn_unit$5 + connect \trap_op__insn \pipe1_trap_op__insn + connect \trap_op__insn$4 \pipe1_trap_op__insn$6 + connect \trap_op__insn_type \pipe1_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe1_trap_op__insn_type$4 + connect \trap_op__is_32bit \pipe1_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe1_trap_op__is_32bit$9 + connect \trap_op__ldst_exc \pipe1_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe1_trap_op__ldst_exc$12 + connect \trap_op__msr \pipe1_trap_op__msr + connect \trap_op__msr$5 \pipe1_trap_op__msr$7 + connect \trap_op__trapaddr \pipe1_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe1_trap_op__trapaddr$11 + connect \trap_op__traptype \pipe1_trap_op__traptype + connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31502.14-31543.4" + cell \pipe2$35 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe2_fast1 + connect \fast1$11 \pipe2_fast1$27 + connect \fast1_ok \pipe2_fast1_ok + connect \fast2 \pipe2_fast2 + connect \fast2$12 \pipe2_fast2$28 + connect \fast2_ok \pipe2_fast2_ok + connect \msr \pipe2_msr + connect \msr_ok \pipe2_msr_ok + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$17 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \nia \pipe2_nia + connect \nia_ok \pipe2_nia_ok + connect \o \pipe2_o + connect \o_ok \pipe2_o_ok + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \ra \pipe2_ra + connect \rb \pipe2_rb + connect \trap_op__cia \pipe2_trap_op__cia + connect \trap_op__cia$6 \pipe2_trap_op__cia$22 + connect \trap_op__fn_unit \pipe2_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe2_trap_op__fn_unit$19 + connect \trap_op__insn \pipe2_trap_op__insn + connect \trap_op__insn$4 \pipe2_trap_op__insn$20 + connect \trap_op__insn_type \pipe2_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe2_trap_op__insn_type$18 + connect \trap_op__is_32bit \pipe2_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe2_trap_op__is_32bit$23 + connect \trap_op__ldst_exc \pipe2_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe2_trap_op__ldst_exc$26 + connect \trap_op__msr \pipe2_trap_op__msr + connect \trap_op__msr$5 \pipe2_trap_op__msr$21 + connect \trap_op__trapaddr \pipe2_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe2_trap_op__trapaddr$25 + connect \trap_op__traptype \pipe2_trap_op__traptype + connect \trap_op__traptype$8 \pipe2_trap_op__traptype$24 + end + connect \muxid 2'00 + connect { \msr_ok \msr } { \pipe2_msr_ok \pipe2_msr } + connect { \nia_ok \nia } { \pipe2_nia_ok \pipe2_nia } + connect { \fast2_ok \fast2 } { \pipe2_fast2_ok \pipe2_fast2$28 } + connect { \fast1_ok \fast1 } { \pipe2_fast1_ok \pipe2_fast1$27 } + connect { \o_ok \o } { \pipe2_o_ok \pipe2_o } + connect { \trap_op__ldst_exc$38 \trap_op__trapaddr$37 \trap_op__traptype$36 \trap_op__is_32bit$35 \trap_op__cia$34 \trap_op__msr$33 \trap_op__insn$32 \trap_op__fn_unit$31 \trap_op__insn_type$30 } { \pipe2_trap_op__ldst_exc$26 \pipe2_trap_op__trapaddr$25 \pipe2_trap_op__traptype$24 \pipe2_trap_op__is_32bit$23 \pipe2_trap_op__cia$22 \pipe2_trap_op__msr$21 \pipe2_trap_op__insn$20 \pipe2_trap_op__fn_unit$19 \pipe2_trap_op__insn_type$18 } + connect \muxid$29 \pipe2_muxid$17 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_fast2$16 \fast2$2 + connect \pipe1_fast1$15 \fast1$1 + connect \pipe1_rb$14 \rb + connect \pipe1_ra$13 \ra + connect { \pipe1_trap_op__ldst_exc$12 \pipe1_trap_op__trapaddr$11 \pipe1_trap_op__traptype$10 \pipe1_trap_op__is_32bit$9 \pipe1_trap_op__cia$8 \pipe1_trap_op__msr$7 \pipe1_trap_op__insn$6 \pipe1_trap_op__fn_unit$5 \pipe1_trap_op__insn_type$4 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect \pipe2_fast2 \pipe1_fast2 + connect \pipe2_fast1 \pipe1_fast1 + connect \pipe2_rb \pipe1_rb + connect \pipe2_ra \pipe1_ra + connect { \pipe2_trap_op__ldst_exc \pipe2_trap_op__trapaddr \pipe2_trap_op__traptype \pipe2_trap_op__is_32bit \pipe2_trap_op__cia \pipe2_trap_op__msr \pipe2_trap_op__insn \pipe2_trap_op__fn_unit \pipe2_trap_op__insn_type } { \pipe1_trap_op__ldst_exc \pipe1_trap_op__trapaddr \pipe1_trap_op__traptype \pipe1_trap_op__is_32bit \pipe1_trap_op__cia \pipe1_trap_op__msr \pipe1_trap_op__insn \pipe1_trap_op__fn_unit \pipe1_trap_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:31574.1-31632.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" +attribute \generator "nMigen" +module \alui_l + attribute \src "libresoc.v:31575.7-31575.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31620.3-31628.6" + wire $0\q_int$next[0:0]$992 + attribute \src "libresoc.v:31618.3-31619.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31620.3-31628.6" + wire $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31599.7-31599.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31610.17-31610.96" + wire $and$libresoc.v:31610$982_Y + attribute \src "libresoc.v:31615.17-31615.96" + wire $and$libresoc.v:31615$987_Y + attribute \src "libresoc.v:31612.18-31612.94" + wire $not$libresoc.v:31612$984_Y + attribute \src "libresoc.v:31614.17-31614.93" + wire $not$libresoc.v:31614$986_Y + attribute \src "libresoc.v:31617.17-31617.93" + wire $not$libresoc.v:31617$989_Y + attribute \src "libresoc.v:31611.18-31611.99" + wire $or$libresoc.v:31611$983_Y + attribute \src "libresoc.v:31613.18-31613.100" + wire $or$libresoc.v:31613$985_Y + attribute \src "libresoc.v:31616.17-31616.98" + wire $or$libresoc.v:31616$988_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31575.7-31575.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31610$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31610$982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31615$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31615$987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31612$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31612$984_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31614$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31614$986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31617$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31617$989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31611$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31611$983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31613$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31613$985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31616$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31616$988_Y + end + attribute \src "libresoc.v:31575.7-31575.20" + process $proc$libresoc.v:31575$994 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31599.7-31599.19" + process $proc$libresoc.v:31599$995 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31618.3-31619.27" + process $proc$libresoc.v:31618$990 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31620.3-31628.6" + process $proc$libresoc.v:31620$991 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31621.5-31621.29" + switch \initial + attribute \src "libresoc.v:31621.9-31621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$993 1'0 + case + assign $1\q_int$next[0:0]$993 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$992 + end + connect \$9 $and$libresoc.v:31610$982_Y + connect \$11 $or$libresoc.v:31611$983_Y + connect \$13 $not$libresoc.v:31612$984_Y + connect \$15 $or$libresoc.v:31613$985_Y + connect \$1 $not$libresoc.v:31614$986_Y + connect \$3 $and$libresoc.v:31615$987_Y + connect \$5 $or$libresoc.v:31616$988_Y + connect \$7 $not$libresoc.v:31617$989_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31636.1-31694.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" +attribute \generator "nMigen" +module \alui_l$106 + attribute \src "libresoc.v:31637.7-31637.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31682.3-31690.6" + wire $0\q_int$next[0:0]$1006 + attribute \src "libresoc.v:31680.3-31681.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31682.3-31690.6" + wire $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31661.7-31661.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31672.17-31672.96" + wire $and$libresoc.v:31672$996_Y + attribute \src "libresoc.v:31677.17-31677.96" + wire $and$libresoc.v:31677$1001_Y + attribute \src "libresoc.v:31674.18-31674.94" + wire $not$libresoc.v:31674$998_Y + attribute \src "libresoc.v:31676.17-31676.93" + wire $not$libresoc.v:31676$1000_Y + attribute \src "libresoc.v:31679.17-31679.93" + wire $not$libresoc.v:31679$1003_Y + attribute \src "libresoc.v:31673.18-31673.99" + wire $or$libresoc.v:31673$997_Y + attribute \src "libresoc.v:31675.18-31675.100" + wire $or$libresoc.v:31675$999_Y + attribute \src "libresoc.v:31678.17-31678.98" + wire $or$libresoc.v:31678$1002_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31637.7-31637.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31672$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31672$996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31677$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31677$1001_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31674$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31674$998_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31676$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31676$1000_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31679$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31679$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31673$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31673$997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31675$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31675$999_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31678$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31678$1002_Y + end + attribute \src "libresoc.v:31637.7-31637.20" + process $proc$libresoc.v:31637$1008 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31661.7-31661.19" + process $proc$libresoc.v:31661$1009 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31680.3-31681.27" + process $proc$libresoc.v:31680$1004 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31682.3-31690.6" + process $proc$libresoc.v:31682$1005 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31683.5-31683.29" + switch \initial + attribute \src "libresoc.v:31683.9-31683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1007 1'0 + case + assign $1\q_int$next[0:0]$1007 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1006 + end + connect \$9 $and$libresoc.v:31672$996_Y + connect \$11 $or$libresoc.v:31673$997_Y + connect \$13 $not$libresoc.v:31674$998_Y + connect \$15 $or$libresoc.v:31675$999_Y + connect \$1 $not$libresoc.v:31676$1000_Y + connect \$3 $and$libresoc.v:31677$1001_Y + connect \$5 $or$libresoc.v:31678$1002_Y + connect \$7 $not$libresoc.v:31679$1003_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31698.1-31756.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" +attribute \generator "nMigen" +module \alui_l$124 + attribute \src "libresoc.v:31699.7-31699.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31744.3-31752.6" + wire $0\q_int$next[0:0]$1020 + attribute \src "libresoc.v:31742.3-31743.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31744.3-31752.6" + wire $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31723.7-31723.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31734.17-31734.96" + wire $and$libresoc.v:31734$1010_Y + attribute \src "libresoc.v:31739.17-31739.96" + wire $and$libresoc.v:31739$1015_Y + attribute \src "libresoc.v:31736.18-31736.94" + wire $not$libresoc.v:31736$1012_Y + attribute \src "libresoc.v:31738.17-31738.93" + wire $not$libresoc.v:31738$1014_Y + attribute \src "libresoc.v:31741.17-31741.93" + wire $not$libresoc.v:31741$1017_Y + attribute \src "libresoc.v:31735.18-31735.99" + wire $or$libresoc.v:31735$1011_Y + attribute \src "libresoc.v:31737.18-31737.100" + wire $or$libresoc.v:31737$1013_Y + attribute \src "libresoc.v:31740.17-31740.98" + wire $or$libresoc.v:31740$1016_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31699.7-31699.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31734$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31734$1010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31739$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31739$1015_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31736$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31736$1012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31738$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31738$1014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31741$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31741$1017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31735$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31735$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31737$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31737$1013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31740$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31740$1016_Y + end + attribute \src "libresoc.v:31699.7-31699.20" + process $proc$libresoc.v:31699$1022 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31723.7-31723.19" + process $proc$libresoc.v:31723$1023 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31742.3-31743.27" + process $proc$libresoc.v:31742$1018 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31744.3-31752.6" + process $proc$libresoc.v:31744$1019 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31745.5-31745.29" + switch \initial + attribute \src "libresoc.v:31745.9-31745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1021 1'0 + case + assign $1\q_int$next[0:0]$1021 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1020 + end + connect \$9 $and$libresoc.v:31734$1010_Y + connect \$11 $or$libresoc.v:31735$1011_Y + connect \$13 $not$libresoc.v:31736$1012_Y + connect \$15 $or$libresoc.v:31737$1013_Y + connect \$1 $not$libresoc.v:31738$1014_Y + connect \$3 $and$libresoc.v:31739$1015_Y + connect \$5 $or$libresoc.v:31740$1016_Y + connect \$7 $not$libresoc.v:31741$1017_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31760.1-31818.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" +attribute \generator "nMigen" +module \alui_l$15 + attribute \src "libresoc.v:31761.7-31761.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31806.3-31814.6" + wire $0\q_int$next[0:0]$1034 + attribute \src "libresoc.v:31804.3-31805.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31806.3-31814.6" + wire $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31785.7-31785.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31796.17-31796.96" + wire $and$libresoc.v:31796$1024_Y + attribute \src "libresoc.v:31801.17-31801.96" + wire $and$libresoc.v:31801$1029_Y + attribute \src "libresoc.v:31798.18-31798.94" + wire $not$libresoc.v:31798$1026_Y + attribute \src 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31761.7-31761.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31796$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31796$1024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31801$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31801$1029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31798$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31798$1026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31800$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31800$1028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31803$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31803$1031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31797$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31797$1025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31799$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31799$1027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31802$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31802$1030_Y + end + attribute \src "libresoc.v:31761.7-31761.20" + process $proc$libresoc.v:31761$1036 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31785.7-31785.19" + process $proc$libresoc.v:31785$1037 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31804.3-31805.27" + process $proc$libresoc.v:31804$1032 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31806.3-31814.6" + process $proc$libresoc.v:31806$1033 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31807.5-31807.29" + switch \initial + attribute \src "libresoc.v:31807.9-31807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1035 1'0 + case + assign $1\q_int$next[0:0]$1035 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1034 + end + connect \$9 $and$libresoc.v:31796$1024_Y + connect \$11 $or$libresoc.v:31797$1025_Y + connect \$13 $not$libresoc.v:31798$1026_Y + connect \$15 $or$libresoc.v:31799$1027_Y + connect \$1 $not$libresoc.v:31800$1028_Y + connect \$3 $and$libresoc.v:31801$1029_Y + connect \$5 $or$libresoc.v:31802$1030_Y + connect \$7 $not$libresoc.v:31803$1031_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31822.1-31880.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" +attribute \generator "nMigen" +module \alui_l$28 + attribute \src "libresoc.v:31823.7-31823.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31868.3-31876.6" + wire $0\q_int$next[0:0]$1048 + attribute \src "libresoc.v:31866.3-31867.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31868.3-31876.6" + wire $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31847.7-31847.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31858.17-31858.96" + wire $and$libresoc.v:31858$1038_Y + attribute \src "libresoc.v:31863.17-31863.96" + wire $and$libresoc.v:31863$1043_Y + attribute \src "libresoc.v:31860.18-31860.94" + wire $not$libresoc.v:31860$1040_Y + attribute \src "libresoc.v:31862.17-31862.93" + wire $not$libresoc.v:31862$1042_Y + attribute \src "libresoc.v:31865.17-31865.93" + wire $not$libresoc.v:31865$1045_Y + attribute \src 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\coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31823.7-31823.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31858$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31858$1038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31863$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31863$1043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31860$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31860$1040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31862$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31862$1042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31865$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31865$1045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31859$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31859$1039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31861$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31861$1041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31864$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31864$1044_Y + end + attribute \src "libresoc.v:31823.7-31823.20" + process $proc$libresoc.v:31823$1050 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31847.7-31847.19" + process $proc$libresoc.v:31847$1051 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31866.3-31867.27" + process $proc$libresoc.v:31866$1046 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31868.3-31876.6" + process $proc$libresoc.v:31868$1047 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31869.5-31869.29" + switch \initial + attribute \src "libresoc.v:31869.9-31869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1049 1'0 + case + assign $1\q_int$next[0:0]$1049 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1048 + end + connect \$9 $and$libresoc.v:31858$1038_Y + connect \$11 $or$libresoc.v:31859$1039_Y + connect \$13 $not$libresoc.v:31860$1040_Y + connect \$15 $or$libresoc.v:31861$1041_Y + connect \$1 $not$libresoc.v:31862$1042_Y + connect \$3 $and$libresoc.v:31863$1043_Y + connect \$5 $or$libresoc.v:31864$1044_Y + connect \$7 $not$libresoc.v:31865$1045_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31884.1-31942.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" +attribute \generator "nMigen" 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"libresoc.v:31926.17-31926.98" + wire $or$libresoc.v:31926$1058_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31885.7-31885.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31920$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31920$1052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31925$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31925$1057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31922$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31922$1054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31924$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31924$1056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31927$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31927$1059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31921$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31921$1053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31923$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31923$1055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31926$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31926$1058_Y + end + attribute \src "libresoc.v:31885.7-31885.20" + process $proc$libresoc.v:31885$1064 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31909.7-31909.19" + process $proc$libresoc.v:31909$1065 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31928.3-31929.27" + process $proc$libresoc.v:31928$1060 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31930.3-31938.6" + process $proc$libresoc.v:31930$1061 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31931.5-31931.29" + switch \initial + attribute \src "libresoc.v:31931.9-31931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1063 1'0 + case + assign $1\q_int$next[0:0]$1063 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1062 + end + connect \$9 $and$libresoc.v:31920$1052_Y + connect \$11 $or$libresoc.v:31921$1053_Y + connect \$13 $not$libresoc.v:31922$1054_Y + connect \$15 $or$libresoc.v:31923$1055_Y + connect \$1 $not$libresoc.v:31924$1056_Y + connect \$3 $and$libresoc.v:31925$1057_Y + connect \$5 $or$libresoc.v:31926$1058_Y + connect \$7 $not$libresoc.v:31927$1059_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31946.1-32004.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" +attribute \generator "nMigen" +module \alui_l$60 + attribute \src "libresoc.v:31947.7-31947.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31992.3-32000.6" + wire $0\q_int$next[0:0]$1076 + attribute \src "libresoc.v:31990.3-31991.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31992.3-32000.6" + wire $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31971.7-31971.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31982.17-31982.96" + wire $and$libresoc.v:31982$1066_Y + attribute \src "libresoc.v:31987.17-31987.96" + wire $and$libresoc.v:31987$1071_Y + attribute \src "libresoc.v:31984.18-31984.94" + wire $not$libresoc.v:31984$1068_Y + attribute \src "libresoc.v:31986.17-31986.93" + wire $not$libresoc.v:31986$1070_Y + attribute \src "libresoc.v:31989.17-31989.93" + wire $not$libresoc.v:31989$1073_Y + attribute \src "libresoc.v:31983.18-31983.99" + wire $or$libresoc.v:31983$1067_Y + attribute \src "libresoc.v:31985.18-31985.100" + wire $or$libresoc.v:31985$1069_Y + attribute \src "libresoc.v:31988.17-31988.98" + wire $or$libresoc.v:31988$1072_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31947.7-31947.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31982$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31982$1066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31987$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31987$1071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31984$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31984$1068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31986$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31986$1070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31989$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31989$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31983$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31983$1067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31985$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31985$1069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31988$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31988$1072_Y + end + attribute \src "libresoc.v:31947.7-31947.20" + process $proc$libresoc.v:31947$1078 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31971.7-31971.19" + process $proc$libresoc.v:31971$1079 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31990.3-31991.27" + process $proc$libresoc.v:31990$1074 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31992.3-32000.6" + process $proc$libresoc.v:31992$1075 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31993.5-31993.29" + switch \initial + attribute \src "libresoc.v:31993.9-31993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1077 1'0 + case + assign $1\q_int$next[0:0]$1077 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1076 + end + connect \$9 $and$libresoc.v:31982$1066_Y + connect \$11 $or$libresoc.v:31983$1067_Y + connect \$13 $not$libresoc.v:31984$1068_Y + connect \$15 $or$libresoc.v:31985$1069_Y + connect \$1 $not$libresoc.v:31986$1070_Y + connect \$3 $and$libresoc.v:31987$1071_Y + connect \$5 $or$libresoc.v:31988$1072_Y + connect \$7 $not$libresoc.v:31989$1073_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:32008.1-32066.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" +attribute \generator "nMigen" +module \alui_l$72 + attribute \src "libresoc.v:32009.7-32009.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32054.3-32062.6" + wire $0\q_int$next[0:0]$1090 + attribute \src "libresoc.v:32052.3-32053.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:32054.3-32062.6" + wire $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:32033.7-32033.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:32044.17-32044.96" + wire $and$libresoc.v:32044$1080_Y + attribute \src "libresoc.v:32049.17-32049.96" + wire $and$libresoc.v:32049$1085_Y + attribute \src "libresoc.v:32046.18-32046.94" + wire $not$libresoc.v:32046$1082_Y + attribute \src "libresoc.v:32048.17-32048.93" + wire $not$libresoc.v:32048$1084_Y + attribute \src "libresoc.v:32051.17-32051.93" + wire $not$libresoc.v:32051$1087_Y + attribute \src "libresoc.v:32045.18-32045.99" + wire $or$libresoc.v:32045$1081_Y + attribute \src "libresoc.v:32047.18-32047.100" + wire $or$libresoc.v:32047$1083_Y + attribute \src "libresoc.v:32050.17-32050.98" + wire $or$libresoc.v:32050$1086_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:32009.7-32009.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:32044$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:32044$1080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:32049$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:32049$1085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:32046$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:32046$1082_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:32048$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:32048$1084_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:32051$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:32051$1087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:32045$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:32045$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:32047$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:32047$1083_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:32050$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:32050$1086_Y + end + attribute \src "libresoc.v:32009.7-32009.20" + process $proc$libresoc.v:32009$1092 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32033.7-32033.19" + process $proc$libresoc.v:32033$1093 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:32052.3-32053.27" + process $proc$libresoc.v:32052$1088 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:32054.3-32062.6" + process $proc$libresoc.v:32054$1089 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:32055.5-32055.29" + switch \initial + attribute \src "libresoc.v:32055.9-32055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1091 1'0 + case + assign $1\q_int$next[0:0]$1091 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1090 + end + connect \$9 $and$libresoc.v:32044$1080_Y + connect \$11 $or$libresoc.v:32045$1081_Y + connect \$13 $not$libresoc.v:32046$1082_Y + connect \$15 $or$libresoc.v:32047$1083_Y + connect \$1 $not$libresoc.v:32048$1084_Y + connect \$3 $and$libresoc.v:32049$1085_Y + connect \$5 $or$libresoc.v:32050$1086_Y + connect \$7 $not$libresoc.v:32051$1087_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:32070.1-32128.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" +attribute \generator "nMigen" +module \alui_l$89 + attribute \src "libresoc.v:32071.7-32071.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32116.3-32124.6" + wire $0\q_int$next[0:0]$1104 + attribute \src "libresoc.v:32114.3-32115.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:32116.3-32124.6" + wire $1\q_int$next[0:0]$1105 + attribute \src "libresoc.v:32095.7-32095.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:32106.17-32106.96" + wire $and$libresoc.v:32106$1094_Y + attribute \src "libresoc.v:32111.17-32111.96" + wire $and$libresoc.v:32111$1099_Y + attribute \src "libresoc.v:32108.18-32108.94" + wire $not$libresoc.v:32108$1096_Y + attribute \src "libresoc.v:32110.17-32110.93" + wire $not$libresoc.v:32110$1098_Y + attribute \src "libresoc.v:32113.17-32113.93" + wire $not$libresoc.v:32113$1101_Y + attribute \src "libresoc.v:32107.18-32107.99" + wire $or$libresoc.v:32107$1095_Y + attribute \src "libresoc.v:32109.18-32109.100" + wire $or$libresoc.v:32109$1097_Y + attribute \src "libresoc.v:32112.17-32112.98" + wire $or$libresoc.v:32112$1100_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:32071.7-32071.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:32106$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:32106$1094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:32111$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:32111$1099_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:32108$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:32108$1096_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:32110$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:32110$1098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:32113$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:32113$1101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:32107$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:32107$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:32109$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:32109$1097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:32112$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:32112$1100_Y + end + attribute \src "libresoc.v:32071.7-32071.20" + process $proc$libresoc.v:32071$1106 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32095.7-32095.19" + process $proc$libresoc.v:32095$1107 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:32114.3-32115.27" + process $proc$libresoc.v:32114$1102 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:32116.3-32124.6" + process $proc$libresoc.v:32116$1103 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 + attribute \src "libresoc.v:32117.5-32117.29" + switch \initial + attribute \src "libresoc.v:32117.9-32117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1105 1'0 + case + assign $1\q_int$next[0:0]$1105 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1104 + end + connect \$9 $and$libresoc.v:32106$1094_Y + connect \$11 $or$libresoc.v:32107$1095_Y + connect \$13 $not$libresoc.v:32108$1096_Y + connect \$15 $or$libresoc.v:32109$1097_Y + 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"libresoc.v:32310.3-33401.6" + wire $15\perm[7:7] + attribute \src "libresoc.v:32310.3-33401.6" + wire $16\perm[7:7] + attribute \src "libresoc.v:32310.3-33401.6" + wire $1\perm[0:0] + attribute \src "libresoc.v:32310.3-33401.6" + wire $2\perm[0:0] + attribute \src "libresoc.v:32310.3-33401.6" + wire $3\perm[1:1] + attribute \src "libresoc.v:32310.3-33401.6" + wire $4\perm[1:1] + attribute \src "libresoc.v:32310.3-33401.6" + wire $5\perm[2:2] + attribute \src "libresoc.v:32310.3-33401.6" + wire $6\perm[2:2] + attribute \src "libresoc.v:32310.3-33401.6" + wire $7\perm[3:3] + attribute \src "libresoc.v:32310.3-33401.6" + wire $8\perm[3:3] + attribute \src "libresoc.v:32310.3-33401.6" + wire $9\perm[4:4] + attribute \src "libresoc.v:32302.17-32302.104" + wire $lt$libresoc.v:32302$1108_Y + attribute \src "libresoc.v:32303.18-32303.105" + wire $lt$libresoc.v:32303$1109_Y + attribute \src "libresoc.v:32304.18-32304.105" + wire $lt$libresoc.v:32304$1110_Y + attribute \src "libresoc.v:32305.18-32305.105" + wire $lt$libresoc.v:32305$1111_Y + attribute \src "libresoc.v:32306.17-32306.104" + wire $lt$libresoc.v:32306$1112_Y + attribute \src "libresoc.v:32307.17-32307.104" + wire $lt$libresoc.v:32307$1113_Y + attribute \src "libresoc.v:32308.17-32308.104" + wire $lt$libresoc.v:32308$1114_Y + attribute \src "libresoc.v:32309.17-32309.104" + wire $lt$libresoc.v:32309$1115_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_7 + attribute \src "libresoc.v:32133.7-32133.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" + wire width 64 \perm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 output 2 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 input 1 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32302$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_4 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32302$1108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32303$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_5 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32303$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32304$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_6 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32304$1110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32305$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_7 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32305$1111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32306$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_0 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32306$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32307$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_1 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32307$1113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32308$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_2 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32308$1114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32309$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_3 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32309$1115_Y + end + attribute \src "libresoc.v:32133.7-32133.20" + process $proc$libresoc.v:32133$1117 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32310.3-33401.6" + process $proc$libresoc.v:32310$1116 + assign { } { } + assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 + assign $0\perm[63:0] [0] $1\perm[0:0] + assign $0\perm[63:0] [1] $3\perm[1:1] + assign $0\perm[63:0] [2] $5\perm[2:2] + assign $0\perm[63:0] [3] $7\perm[3:3] + assign $0\perm[63:0] [4] $9\perm[4:4] + assign $0\perm[63:0] [5] $11\perm[5:5] + assign $0\perm[63:0] [6] $13\perm[6:6] + assign $0\perm[63:0] [7] $15\perm[7:7] + attribute \src "libresoc.v:32311.5-32311.29" + switch \initial + attribute \src "libresoc.v:32311.9-32311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\perm[0:0] $2\perm[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $2\perm[0:0] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $2\perm[0:0] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $2\perm[0:0] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $2\perm[0:0] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $2\perm[0:0] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $2\perm[0:0] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $2\perm[0:0] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $2\perm[0:0] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $2\perm[0:0] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $2\perm[0:0] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $2\perm[0:0] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $2\perm[0:0] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $2\perm[0:0] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $2\perm[0:0] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $2\perm[0:0] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $2\perm[0:0] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $2\perm[0:0] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $2\perm[0:0] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $2\perm[0:0] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $2\perm[0:0] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $2\perm[0:0] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $2\perm[0:0] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $2\perm[0:0] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $2\perm[0:0] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $2\perm[0:0] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $2\perm[0:0] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $2\perm[0:0] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $2\perm[0:0] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $2\perm[0:0] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $2\perm[0:0] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $2\perm[0:0] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $2\perm[0:0] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $2\perm[0:0] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $2\perm[0:0] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $2\perm[0:0] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $2\perm[0:0] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $2\perm[0:0] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $2\perm[0:0] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $2\perm[0:0] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $2\perm[0:0] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $2\perm[0:0] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $2\perm[0:0] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $2\perm[0:0] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $2\perm[0:0] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $2\perm[0:0] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $2\perm[0:0] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $2\perm[0:0] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $2\perm[0:0] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $2\perm[0:0] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $2\perm[0:0] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $2\perm[0:0] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $2\perm[0:0] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $2\perm[0:0] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $2\perm[0:0] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $2\perm[0:0] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $2\perm[0:0] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $2\perm[0:0] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $2\perm[0:0] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $2\perm[0:0] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $2\perm[0:0] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $2\perm[0:0] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $2\perm[0:0] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $2\perm[0:0] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $2\perm[0:0] \rb64_63 + case + assign $2\perm[0:0] 1'0 + end + case + assign $1\perm[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\perm[1:1] $4\perm[1:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $4\perm[1:1] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $4\perm[1:1] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $4\perm[1:1] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $4\perm[1:1] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $4\perm[1:1] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $4\perm[1:1] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $4\perm[1:1] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $4\perm[1:1] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $4\perm[1:1] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $4\perm[1:1] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $4\perm[1:1] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $4\perm[1:1] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $4\perm[1:1] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $4\perm[1:1] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $4\perm[1:1] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $4\perm[1:1] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $4\perm[1:1] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $4\perm[1:1] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $4\perm[1:1] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $4\perm[1:1] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $4\perm[1:1] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $4\perm[1:1] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $4\perm[1:1] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $4\perm[1:1] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $4\perm[1:1] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $4\perm[1:1] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $4\perm[1:1] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $4\perm[1:1] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $4\perm[1:1] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $4\perm[1:1] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $4\perm[1:1] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $4\perm[1:1] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $4\perm[1:1] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $4\perm[1:1] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $4\perm[1:1] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $4\perm[1:1] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $4\perm[1:1] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $4\perm[1:1] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $4\perm[1:1] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $4\perm[1:1] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $4\perm[1:1] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $4\perm[1:1] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $4\perm[1:1] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $4\perm[1:1] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $4\perm[1:1] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $4\perm[1:1] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $4\perm[1:1] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $4\perm[1:1] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $4\perm[1:1] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $4\perm[1:1] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $4\perm[1:1] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $4\perm[1:1] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $4\perm[1:1] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $4\perm[1:1] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $4\perm[1:1] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $4\perm[1:1] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $4\perm[1:1] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $4\perm[1:1] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $4\perm[1:1] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $4\perm[1:1] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $4\perm[1:1] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $4\perm[1:1] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $4\perm[1:1] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $4\perm[1:1] \rb64_63 + case + assign $4\perm[1:1] 1'0 + end + case + assign $3\perm[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\perm[2:2] $6\perm[2:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $6\perm[2:2] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $6\perm[2:2] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $6\perm[2:2] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $6\perm[2:2] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $6\perm[2:2] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $6\perm[2:2] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $6\perm[2:2] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $6\perm[2:2] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $6\perm[2:2] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $6\perm[2:2] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $6\perm[2:2] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $6\perm[2:2] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $6\perm[2:2] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $6\perm[2:2] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $6\perm[2:2] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $6\perm[2:2] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $6\perm[2:2] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $6\perm[2:2] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $6\perm[2:2] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $6\perm[2:2] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $6\perm[2:2] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $6\perm[2:2] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $6\perm[2:2] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $6\perm[2:2] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $6\perm[2:2] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $6\perm[2:2] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $6\perm[2:2] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $6\perm[2:2] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $6\perm[2:2] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $6\perm[2:2] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $6\perm[2:2] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $6\perm[2:2] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $6\perm[2:2] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $6\perm[2:2] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $6\perm[2:2] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $6\perm[2:2] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $6\perm[2:2] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $6\perm[2:2] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $6\perm[2:2] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $6\perm[2:2] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $6\perm[2:2] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $6\perm[2:2] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $6\perm[2:2] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $6\perm[2:2] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $6\perm[2:2] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $6\perm[2:2] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $6\perm[2:2] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $6\perm[2:2] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $6\perm[2:2] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $6\perm[2:2] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $6\perm[2:2] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $6\perm[2:2] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $6\perm[2:2] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $6\perm[2:2] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $6\perm[2:2] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $6\perm[2:2] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $6\perm[2:2] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $6\perm[2:2] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $6\perm[2:2] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $6\perm[2:2] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $6\perm[2:2] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $6\perm[2:2] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $6\perm[2:2] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $6\perm[2:2] \rb64_63 + case + assign $6\perm[2:2] 1'0 + end + case + assign $5\perm[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\perm[3:3] $8\perm[3:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $8\perm[3:3] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $8\perm[3:3] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $8\perm[3:3] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $8\perm[3:3] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $8\perm[3:3] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $8\perm[3:3] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $8\perm[3:3] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $8\perm[3:3] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $8\perm[3:3] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $8\perm[3:3] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $8\perm[3:3] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $8\perm[3:3] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $8\perm[3:3] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $8\perm[3:3] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $8\perm[3:3] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $8\perm[3:3] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $8\perm[3:3] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $8\perm[3:3] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $8\perm[3:3] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $8\perm[3:3] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $8\perm[3:3] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $8\perm[3:3] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $8\perm[3:3] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $8\perm[3:3] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $8\perm[3:3] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $8\perm[3:3] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $8\perm[3:3] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $8\perm[3:3] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $8\perm[3:3] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $8\perm[3:3] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $8\perm[3:3] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $8\perm[3:3] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $8\perm[3:3] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $8\perm[3:3] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $8\perm[3:3] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $8\perm[3:3] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $8\perm[3:3] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $8\perm[3:3] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $8\perm[3:3] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $8\perm[3:3] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $8\perm[3:3] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $8\perm[3:3] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $8\perm[3:3] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $8\perm[3:3] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $8\perm[3:3] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $8\perm[3:3] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $8\perm[3:3] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $8\perm[3:3] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $8\perm[3:3] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $8\perm[3:3] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $8\perm[3:3] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $8\perm[3:3] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $8\perm[3:3] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $8\perm[3:3] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $8\perm[3:3] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $8\perm[3:3] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $8\perm[3:3] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $8\perm[3:3] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $8\perm[3:3] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $8\perm[3:3] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $8\perm[3:3] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $8\perm[3:3] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $8\perm[3:3] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $8\perm[3:3] \rb64_63 + case + assign $8\perm[3:3] 1'0 + end + case + assign $7\perm[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\perm[4:4] $10\perm[4:4] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $10\perm[4:4] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $10\perm[4:4] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $10\perm[4:4] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $10\perm[4:4] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $10\perm[4:4] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $10\perm[4:4] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $10\perm[4:4] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $10\perm[4:4] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $10\perm[4:4] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $10\perm[4:4] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $10\perm[4:4] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $10\perm[4:4] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $10\perm[4:4] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $10\perm[4:4] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $10\perm[4:4] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $10\perm[4:4] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $10\perm[4:4] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $10\perm[4:4] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $10\perm[4:4] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $10\perm[4:4] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $10\perm[4:4] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $10\perm[4:4] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $10\perm[4:4] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $10\perm[4:4] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $10\perm[4:4] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $10\perm[4:4] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $10\perm[4:4] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $10\perm[4:4] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $10\perm[4:4] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $10\perm[4:4] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $10\perm[4:4] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $10\perm[4:4] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $10\perm[4:4] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $10\perm[4:4] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $10\perm[4:4] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $10\perm[4:4] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $10\perm[4:4] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $10\perm[4:4] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $10\perm[4:4] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $10\perm[4:4] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $10\perm[4:4] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $10\perm[4:4] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $10\perm[4:4] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $10\perm[4:4] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $10\perm[4:4] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $10\perm[4:4] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $10\perm[4:4] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $10\perm[4:4] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $10\perm[4:4] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $10\perm[4:4] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $10\perm[4:4] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $10\perm[4:4] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $10\perm[4:4] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $10\perm[4:4] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $10\perm[4:4] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $10\perm[4:4] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $10\perm[4:4] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $10\perm[4:4] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $10\perm[4:4] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $10\perm[4:4] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $10\perm[4:4] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $10\perm[4:4] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $10\perm[4:4] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $10\perm[4:4] \rb64_63 + case + assign $10\perm[4:4] 1'0 + end + case + assign $9\perm[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\perm[5:5] $12\perm[5:5] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $12\perm[5:5] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $12\perm[5:5] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $12\perm[5:5] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $12\perm[5:5] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $12\perm[5:5] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $12\perm[5:5] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $12\perm[5:5] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $12\perm[5:5] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $12\perm[5:5] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $12\perm[5:5] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $12\perm[5:5] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $12\perm[5:5] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $12\perm[5:5] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $12\perm[5:5] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $12\perm[5:5] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $12\perm[5:5] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $12\perm[5:5] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $12\perm[5:5] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $12\perm[5:5] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $12\perm[5:5] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $12\perm[5:5] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $12\perm[5:5] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $12\perm[5:5] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $12\perm[5:5] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $12\perm[5:5] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $12\perm[5:5] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $12\perm[5:5] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $12\perm[5:5] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $12\perm[5:5] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $12\perm[5:5] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $12\perm[5:5] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $12\perm[5:5] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $12\perm[5:5] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $12\perm[5:5] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $12\perm[5:5] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $12\perm[5:5] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $12\perm[5:5] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $12\perm[5:5] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $12\perm[5:5] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $12\perm[5:5] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $12\perm[5:5] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $12\perm[5:5] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $12\perm[5:5] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $12\perm[5:5] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $12\perm[5:5] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $12\perm[5:5] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $12\perm[5:5] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $12\perm[5:5] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $12\perm[5:5] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $12\perm[5:5] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $12\perm[5:5] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $12\perm[5:5] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $12\perm[5:5] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $12\perm[5:5] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $12\perm[5:5] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $12\perm[5:5] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $12\perm[5:5] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $12\perm[5:5] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $12\perm[5:5] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $12\perm[5:5] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $12\perm[5:5] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $12\perm[5:5] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $12\perm[5:5] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $12\perm[5:5] \rb64_63 + case + assign $12\perm[5:5] 1'0 + end + case + assign $11\perm[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\perm[6:6] $14\perm[6:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $14\perm[6:6] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $14\perm[6:6] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $14\perm[6:6] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $14\perm[6:6] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $14\perm[6:6] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $14\perm[6:6] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $14\perm[6:6] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $14\perm[6:6] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $14\perm[6:6] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $14\perm[6:6] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $14\perm[6:6] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $14\perm[6:6] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $14\perm[6:6] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $14\perm[6:6] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $14\perm[6:6] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $14\perm[6:6] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $14\perm[6:6] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $14\perm[6:6] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $14\perm[6:6] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $14\perm[6:6] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $14\perm[6:6] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $14\perm[6:6] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $14\perm[6:6] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $14\perm[6:6] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $14\perm[6:6] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $14\perm[6:6] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $14\perm[6:6] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $14\perm[6:6] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $14\perm[6:6] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $14\perm[6:6] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $14\perm[6:6] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $14\perm[6:6] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $14\perm[6:6] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $14\perm[6:6] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $14\perm[6:6] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $14\perm[6:6] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $14\perm[6:6] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $14\perm[6:6] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $14\perm[6:6] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $14\perm[6:6] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $14\perm[6:6] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $14\perm[6:6] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $14\perm[6:6] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $14\perm[6:6] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $14\perm[6:6] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $14\perm[6:6] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $14\perm[6:6] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $14\perm[6:6] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $14\perm[6:6] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $14\perm[6:6] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $14\perm[6:6] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $14\perm[6:6] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $14\perm[6:6] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $14\perm[6:6] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $14\perm[6:6] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $14\perm[6:6] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $14\perm[6:6] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $14\perm[6:6] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $14\perm[6:6] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $14\perm[6:6] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $14\perm[6:6] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $14\perm[6:6] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $14\perm[6:6] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $14\perm[6:6] \rb64_63 + case + assign $14\perm[6:6] 1'0 + end + case + assign $13\perm[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\perm[7:7] $16\perm[7:7] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $16\perm[7:7] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $16\perm[7:7] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $16\perm[7:7] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $16\perm[7:7] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $16\perm[7:7] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $16\perm[7:7] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $16\perm[7:7] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $16\perm[7:7] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $16\perm[7:7] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $16\perm[7:7] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $16\perm[7:7] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $16\perm[7:7] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $16\perm[7:7] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $16\perm[7:7] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $16\perm[7:7] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $16\perm[7:7] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $16\perm[7:7] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $16\perm[7:7] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $16\perm[7:7] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $16\perm[7:7] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $16\perm[7:7] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $16\perm[7:7] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $16\perm[7:7] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $16\perm[7:7] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $16\perm[7:7] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $16\perm[7:7] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $16\perm[7:7] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $16\perm[7:7] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $16\perm[7:7] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $16\perm[7:7] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $16\perm[7:7] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $16\perm[7:7] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $16\perm[7:7] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $16\perm[7:7] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $16\perm[7:7] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $16\perm[7:7] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $16\perm[7:7] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $16\perm[7:7] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $16\perm[7:7] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $16\perm[7:7] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $16\perm[7:7] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $16\perm[7:7] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $16\perm[7:7] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $16\perm[7:7] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $16\perm[7:7] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $16\perm[7:7] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $16\perm[7:7] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $16\perm[7:7] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $16\perm[7:7] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $16\perm[7:7] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $16\perm[7:7] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $16\perm[7:7] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $16\perm[7:7] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $16\perm[7:7] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $16\perm[7:7] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $16\perm[7:7] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $16\perm[7:7] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $16\perm[7:7] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $16\perm[7:7] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $16\perm[7:7] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $16\perm[7:7] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $16\perm[7:7] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $16\perm[7:7] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $16\perm[7:7] \rb64_63 + case + assign $16\perm[7:7] 1'0 + end + case + assign $15\perm[7:7] 1'0 + end + sync always + update \perm $0\perm[63:0] + end + connect \$9 $lt$libresoc.v:32302$1108_Y + connect \$11 $lt$libresoc.v:32303$1109_Y + connect \$13 $lt$libresoc.v:32304$1110_Y + connect \$15 $lt$libresoc.v:32305$1111_Y + connect \$1 $lt$libresoc.v:32306$1112_Y + connect \$3 $lt$libresoc.v:32307$1113_Y + connect \$5 $lt$libresoc.v:32308$1114_Y + connect \$7 $lt$libresoc.v:32309$1115_Y + connect \ra [7:0] \perm [7:0] + connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 + connect \idx_7 \rs [63:56] + connect \idx_6 \rs [55:48] + connect \idx_5 \rs [47:40] + connect \idx_4 \rs [39:32] + connect \idx_3 \rs [31:24] + connect \idx_2 \rs [23:16] + connect \idx_1 \rs [15:8] + connect \idx_0 \rs [7:0] + connect \rb64_63 \rb [0] + connect \rb64_62 \rb [1] + connect \rb64_61 \rb [2] + connect \rb64_60 \rb [3] + connect \rb64_59 \rb [4] + connect \rb64_58 \rb [5] + connect \rb64_57 \rb [6] + connect \rb64_56 \rb [7] + connect \rb64_55 \rb [8] + connect \rb64_54 \rb [9] + connect \rb64_53 \rb [10] + connect \rb64_52 \rb [11] + connect \rb64_51 \rb [12] + connect \rb64_50 \rb [13] + connect \rb64_49 \rb [14] + connect \rb64_48 \rb [15] + connect \rb64_47 \rb [16] + connect \rb64_46 \rb [17] + connect \rb64_45 \rb [18] + connect \rb64_44 \rb [19] + connect \rb64_43 \rb [20] + connect \rb64_42 \rb [21] + connect \rb64_41 \rb [22] + connect \rb64_40 \rb [23] + connect \rb64_39 \rb [24] + connect \rb64_38 \rb [25] + connect \rb64_37 \rb [26] + connect \rb64_36 \rb [27] + connect \rb64_35 \rb [28] + connect \rb64_34 \rb [29] + connect \rb64_33 \rb [30] + connect \rb64_32 \rb [31] + connect \rb64_31 \rb [32] + connect \rb64_30 \rb [33] + connect \rb64_29 \rb [34] + connect \rb64_28 \rb [35] + connect \rb64_27 \rb [36] + connect \rb64_26 \rb [37] + connect \rb64_25 \rb [38] + connect \rb64_24 \rb [39] + connect \rb64_23 \rb [40] + connect \rb64_22 \rb [41] + connect \rb64_21 \rb [42] + connect \rb64_20 \rb [43] + connect \rb64_19 \rb [44] + connect \rb64_18 \rb [45] + connect \rb64_17 \rb [46] + connect \rb64_16 \rb [47] + connect \rb64_15 \rb [48] + connect \rb64_14 \rb [49] + connect \rb64_13 \rb [50] + connect \rb64_12 \rb [51] + connect \rb64_11 \rb [52] + connect \rb64_10 \rb [53] + connect \rb64_9 \rb [54] + connect \rb64_8 \rb [55] + connect \rb64_7 \rb [56] + connect \rb64_6 \rb [57] + connect \rb64_5 \rb [58] + connect \rb64_4 \rb [59] + connect \rb64_3 \rb [60] + connect \rb64_2 \rb [61] + connect \rb64_1 \rb [62] + connect \rb64_0 \rb [63] +end +attribute \src "libresoc.v:33480.1-34535.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" +attribute \generator "nMigen" +module \branch0 + attribute \src "libresoc.v:34152.3-34153.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 + attribute \src "libresoc.v:34112.3-34113.61" + wire width 64 $0\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire width 14 $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 + attribute \src "libresoc.v:34116.3-34117.69" + wire width 14 $0\alu_branch0_br_op__fn_unit[13:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + attribute \src "libresoc.v:34120.3-34121.83" + wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + attribute \src "libresoc.v:34122.3-34123.79" + wire $0\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 + attribute \src "libresoc.v:34118.3-34119.63" + wire width 32 $0\alu_branch0_br_op__insn[31:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + attribute \src "libresoc.v:34114.3-34115.73" + wire width 7 $0\alu_branch0_br_op__insn_type[6:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + attribute \src "libresoc.v:34126.3-34127.71" + wire $0\alu_branch0_br_op__is_32bit[0:0] + attribute \src "libresoc.v:34327.3-34351.6" + wire $0\alu_branch0_br_op__lk$next[0:0]$1246 + attribute \src "libresoc.v:34124.3-34125.59" + wire $0\alu_branch0_br_op__lk[0:0] + attribute \src "libresoc.v:34150.3-34151.43" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:34457.3-34465.6" + wire $0\alu_l_r_alu$next[0:0]$1294 + attribute \src "libresoc.v:34090.3-34091.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:34448.3-34456.6" + wire $0\alui_l_r_alui$next[0:0]$1291 + attribute \src "libresoc.v:34092.3-34093.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:34352.3-34373.6" + wire width 64 $0\data_r0__fast1$next[63:0]$1258 + attribute \src "libresoc.v:34108.3-34109.45" + wire width 64 $0\data_r0__fast1[63:0] + attribute \src "libresoc.v:34352.3-34373.6" + wire $0\data_r0__fast1_ok$next[0:0]$1259 + attribute \src "libresoc.v:34110.3-34111.51" + wire $0\data_r0__fast1_ok[0:0] + attribute \src "libresoc.v:34374.3-34395.6" + wire width 64 $0\data_r1__fast2$next[63:0]$1266 + attribute \src "libresoc.v:34104.3-34105.45" + wire width 64 $0\data_r1__fast2[63:0] + attribute \src "libresoc.v:34374.3-34395.6" + wire $0\data_r1__fast2_ok$next[0:0]$1267 + attribute \src "libresoc.v:34106.3-34107.51" + wire $0\data_r1__fast2_ok[0:0] + attribute \src "libresoc.v:34396.3-34417.6" + wire width 64 $0\data_r2__nia$next[63:0]$1274 + attribute \src "libresoc.v:34100.3-34101.41" + wire width 64 $0\data_r2__nia[63:0] + attribute \src "libresoc.v:34396.3-34417.6" + wire $0\data_r2__nia_ok$next[0:0]$1275 + attribute \src "libresoc.v:34102.3-34103.47" + wire $0\data_r2__nia_ok[0:0] + attribute \src "libresoc.v:34466.3-34475.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:34476.3-34485.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:34486.3-34495.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:33481.7-33481.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34282.3-34290.6" + wire $0\opc_l_r_opc$next[0:0]$1224 + attribute \src "libresoc.v:34136.3-34137.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:34273.3-34281.6" + wire $0\opc_l_s_opc$next[0:0]$1221 + attribute \src "libresoc.v:34138.3-34139.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:34496.3-34504.6" + wire width 3 $0\prev_wr_go$next[2:0]$1300 + attribute \src "libresoc.v:34148.3-34149.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:34227.3-34236.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:34318.3-34326.6" + wire width 3 $0\req_l_r_req$next[2:0]$1236 + attribute \src "libresoc.v:34128.3-34129.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:34309.3-34317.6" + wire width 3 $0\req_l_s_req$next[2:0]$1233 + attribute \src "libresoc.v:34130.3-34131.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:34246.3-34254.6" + wire $0\rok_l_r_rdok$next[0:0]$1212 + attribute \src "libresoc.v:34144.3-34145.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:34237.3-34245.6" + wire $0\rok_l_s_rdok$next[0:0]$1209 + attribute \src "libresoc.v:34146.3-34147.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:34264.3-34272.6" + wire $0\rst_l_r_rst$next[0:0]$1218 + attribute \src "libresoc.v:34140.3-34141.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:34255.3-34263.6" + wire $0\rst_l_s_rst$next[0:0]$1215 + attribute \src "libresoc.v:34142.3-34143.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:34300.3-34308.6" + wire width 3 $0\src_l_r_src$next[2:0]$1230 + attribute \src "libresoc.v:34132.3-34133.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:34291.3-34299.6" + wire width 3 $0\src_l_s_src$next[2:0]$1227 + attribute \src "libresoc.v:34134.3-34135.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:34418.3-34427.6" + wire width 64 $0\src_r0$next[63:0]$1282 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:34046$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:34046$1131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:34049$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:34049$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:34052$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:34052$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:34058$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_ready_i + connect \Y $not$libresoc.v:34058$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:34073$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:34073$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:34087$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_br_op__imm_data__ok + connect \Y $not$libresoc.v:34087$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:34089$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:34089$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:34056$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:34056$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:34067$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:34067$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:34068$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:34068$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:34069$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:34069$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:34070$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:34070$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:34074$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:34074$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:34084$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:34084$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:34033$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:34033$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:34051$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:34051$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:34054$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:34054$1139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:34055$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:34055$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:34078$1163 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:34078$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:34079$1164 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_branch0_br_op__imm_data__data + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:34079$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:34080$1165 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:34080$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:34081$1166 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:34081$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:34082$1167 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:34082$1167_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34154.15-34178.4" + cell \alu_branch0 \alu_branch0 + connect \br_op__cia \alu_branch0_br_op__cia + connect \br_op__fn_unit \alu_branch0_br_op__fn_unit + connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data + connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok + connect \br_op__insn \alu_branch0_br_op__insn + connect \br_op__insn_type \alu_branch0_br_op__insn_type + connect \br_op__is_32bit \alu_branch0_br_op__is_32bit + connect \br_op__lk \alu_branch0_br_op__lk + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_branch0_cr_a + connect \fast1 \alu_branch0_fast1 + connect \fast1$1 \alu_branch0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_branch0_fast2 + connect \fast2$2 \alu_branch0_fast2$2 + connect \fast2_ok \fast2_ok + connect \n_ready_i \alu_branch0_n_ready_i + connect \n_valid_o \alu_branch0_n_valid_o + connect \nia \alu_branch0_nia + connect \nia_ok \nia_ok + connect \p_ready_o \alu_branch0_p_ready_o + connect \p_valid_i \alu_branch0_p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34179.14-34185.4" + cell \alu_l$29 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34186.15-34192.4" + cell \alui_l$28 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34193.14-34199.4" + cell \opc_l$24 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34200.14-34206.4" + cell \req_l$25 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34207.14-34213.4" + cell \rok_l$27 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34214.14-34219.4" + cell \rst_l$26 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:34220.14-34226.4" + cell \src_l$23 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:33481.7-33481.20" + process $proc$libresoc.v:33481$1302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:33599.7-33599.24" + process $proc$libresoc.v:33599$1303 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:33607.14-33607.59" + process $proc$libresoc.v:33607$1304 + assign { } { } + assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:33626.14-33626.51" + process $proc$libresoc.v:33626$1305 + assign { } { } + assign $1\alu_branch0_br_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[13:0] + end + attribute \src "libresoc.v:33630.14-33630.70" + process $proc$libresoc.v:33630$1306 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:33634.7-33634.45" + process $proc$libresoc.v:33634$1307 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:33638.14-33638.45" + process $proc$libresoc.v:33638$1308 + assign { } { } + assign $1\alu_branch0_br_op__insn[31:0] 0 + sync always + sync init + update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:33717.13-33717.49" + process $proc$libresoc.v:33717$1309 + assign { } { } + assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:33721.7-33721.41" + process $proc$libresoc.v:33721$1310 + assign { } { } + assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:33725.7-33725.35" + process $proc$libresoc.v:33725$1311 + assign { } { } + assign $1\alu_branch0_br_op__lk[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:33751.7-33751.26" + process $proc$libresoc.v:33751$1312 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33759.7-33759.25" + process $proc$libresoc.v:33759$1313 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:33771.7-33771.27" + process $proc$libresoc.v:33771$1314 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:33803.14-33803.51" + process $proc$libresoc.v:33803$1315 + assign { } { } + assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__fast1 $1\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:33807.7-33807.31" + process $proc$libresoc.v:33807$1316 + assign { } { } + assign $1\data_r0__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:33811.14-33811.51" + process $proc$libresoc.v:33811$1317 + assign { } { } + assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast2 $1\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:33815.7-33815.31" + process $proc$libresoc.v:33815$1318 + assign { } { } + assign $1\data_r1__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:33819.14-33819.49" + process $proc$libresoc.v:33819$1319 + assign { } { } + assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__nia $1\data_r2__nia[63:0] + end + attribute \src "libresoc.v:33823.7-33823.29" + process $proc$libresoc.v:33823$1320 + assign { } { } + assign $1\data_r2__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:33844.7-33844.25" + process $proc$libresoc.v:33844$1321 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:33848.7-33848.25" + process $proc$libresoc.v:33848$1322 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33958.13-33958.30" + process $proc$libresoc.v:33958$1323 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33966.13-33966.31" + process $proc$libresoc.v:33966$1324 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33970.13-33970.31" + process $proc$libresoc.v:33970$1325 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33982.7-33982.26" + process $proc$libresoc.v:33982$1326 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33986.7-33986.26" + process $proc$libresoc.v:33986$1327 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33990.7-33990.25" + process $proc$libresoc.v:33990$1328 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33994.7-33994.25" + process $proc$libresoc.v:33994$1329 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:34008.13-34008.31" + process $proc$libresoc.v:34008$1330 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:34012.13-34012.31" + process $proc$libresoc.v:34012$1331 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:34018.14-34018.43" + process $proc$libresoc.v:34018$1332 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:34022.14-34022.43" + process $proc$libresoc.v:34022$1333 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:34026.13-34026.26" + process $proc$libresoc.v:34026$1334 + assign { } { } + assign $1\src_r2[3:0] 4'0000 + sync always + sync init + update \src_r2 $1\src_r2[3:0] + end + attribute \src "libresoc.v:34090.3-34091.39" + process $proc$libresoc.v:34090$1175 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:34092.3-34093.43" + process $proc$libresoc.v:34092$1176 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:34094.3-34095.29" + process $proc$libresoc.v:34094$1177 + assign { } { } + assign $0\src_r2[3:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[3:0] + end + attribute \src "libresoc.v:34096.3-34097.29" + process $proc$libresoc.v:34096$1178 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:34098.3-34099.29" + process $proc$libresoc.v:34098$1179 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:34100.3-34101.41" + process $proc$libresoc.v:34100$1180 + assign { } { } + assign $0\data_r2__nia[63:0] \data_r2__nia$next + sync posedge \coresync_clk + update \data_r2__nia $0\data_r2__nia[63:0] + end + attribute \src "libresoc.v:34102.3-34103.47" + process $proc$libresoc.v:34102$1181 + assign { } { } + assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next + sync posedge \coresync_clk + update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:34104.3-34105.45" + process $proc$libresoc.v:34104$1182 + assign { } { } + assign $0\data_r1__fast2[63:0] \data_r1__fast2$next + sync posedge \coresync_clk + update \data_r1__fast2 $0\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:34106.3-34107.51" + process $proc$libresoc.v:34106$1183 + assign { } { } + assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next + sync posedge \coresync_clk + update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:34108.3-34109.45" + process $proc$libresoc.v:34108$1184 + assign { } { } + assign $0\data_r0__fast1[63:0] \data_r0__fast1$next + sync posedge \coresync_clk + update \data_r0__fast1 $0\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:34110.3-34111.51" + process $proc$libresoc.v:34110$1185 + assign { } { } + assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next + sync posedge \coresync_clk + update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:34112.3-34113.61" + process $proc$libresoc.v:34112$1186 + assign { } { } + assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next + sync posedge \coresync_clk + update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:34114.3-34115.73" + process $proc$libresoc.v:34114$1187 + assign { } { } + assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:34116.3-34117.69" + process $proc$libresoc.v:34116$1188 + assign { } { } + assign $0\alu_branch0_br_op__fn_unit[13:0] \alu_branch0_br_op__fn_unit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[13:0] + end + attribute \src "libresoc.v:34118.3-34119.63" + process $proc$libresoc.v:34118$1189 + assign { } { } + assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:34120.3-34121.83" + process $proc$libresoc.v:34120$1190 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:34122.3-34123.79" + process $proc$libresoc.v:34122$1191 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:34124.3-34125.59" + process $proc$libresoc.v:34124$1192 + assign { } { } + assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next + sync posedge \coresync_clk + update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:34126.3-34127.71" + process $proc$libresoc.v:34126$1193 + assign { } { } + assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:34128.3-34129.39" + process $proc$libresoc.v:34128$1194 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:34130.3-34131.39" + process $proc$libresoc.v:34130$1195 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:34132.3-34133.39" + process $proc$libresoc.v:34132$1196 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:34134.3-34135.39" + process $proc$libresoc.v:34134$1197 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:34136.3-34137.39" + process $proc$libresoc.v:34136$1198 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:34138.3-34139.39" + process $proc$libresoc.v:34138$1199 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:34140.3-34141.39" + process $proc$libresoc.v:34140$1200 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:34142.3-34143.39" + process $proc$libresoc.v:34142$1201 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:34144.3-34145.41" + process $proc$libresoc.v:34144$1202 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:34146.3-34147.41" + process $proc$libresoc.v:34146$1203 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:34148.3-34149.37" + process $proc$libresoc.v:34148$1204 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:34150.3-34151.43" + process $proc$libresoc.v:34150$1205 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:34152.3-34153.25" + process $proc$libresoc.v:34152$1206 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:34227.3-34236.6" + process $proc$libresoc.v:34227$1207 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:34228.5-34228.29" + switch \initial + attribute \src "libresoc.v:34228.9-34228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:34237.3-34245.6" + process $proc$libresoc.v:34237$1208 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 + attribute \src "libresoc.v:34238.5-34238.29" + switch \initial + attribute \src "libresoc.v:34238.9-34238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$1210 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$1210 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 + end + attribute \src "libresoc.v:34246.3-34254.6" + process $proc$libresoc.v:34246$1211 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 + attribute \src "libresoc.v:34247.5-34247.29" + switch \initial + attribute \src "libresoc.v:34247.9-34247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$1213 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$1213 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 + end + attribute \src "libresoc.v:34255.3-34263.6" + process $proc$libresoc.v:34255$1214 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 + attribute \src "libresoc.v:34256.5-34256.29" + switch \initial + attribute \src "libresoc.v:34256.9-34256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$1216 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$1216 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 + end + attribute \src "libresoc.v:34264.3-34272.6" + process $proc$libresoc.v:34264$1217 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 + attribute \src "libresoc.v:34265.5-34265.29" + switch \initial + attribute \src "libresoc.v:34265.9-34265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$1219 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$1219 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 + end + attribute \src "libresoc.v:34273.3-34281.6" + process $proc$libresoc.v:34273$1220 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 + attribute \src "libresoc.v:34274.5-34274.29" + switch \initial + attribute \src "libresoc.v:34274.9-34274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$1222 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$1222 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 + end + attribute \src "libresoc.v:34282.3-34290.6" + process $proc$libresoc.v:34282$1223 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 + attribute \src "libresoc.v:34283.5-34283.29" + switch \initial + attribute \src "libresoc.v:34283.9-34283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$1225 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$1225 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 + end + attribute \src "libresoc.v:34291.3-34299.6" + process $proc$libresoc.v:34291$1226 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 + attribute \src "libresoc.v:34292.5-34292.29" + switch \initial + attribute \src "libresoc.v:34292.9-34292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$1228 3'000 + case + assign $1\src_l_s_src$next[2:0]$1228 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 + end + attribute \src "libresoc.v:34300.3-34308.6" + process $proc$libresoc.v:34300$1229 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 + attribute \src "libresoc.v:34301.5-34301.29" + switch \initial + attribute \src "libresoc.v:34301.9-34301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$1231 3'111 + case + assign $1\src_l_r_src$next[2:0]$1231 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 + end + attribute \src "libresoc.v:34309.3-34317.6" + process $proc$libresoc.v:34309$1232 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 + attribute \src "libresoc.v:34310.5-34310.29" + switch \initial + attribute \src "libresoc.v:34310.9-34310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$1234 3'000 + case + assign $1\req_l_s_req$next[2:0]$1234 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 + end + attribute \src "libresoc.v:34318.3-34326.6" + process $proc$libresoc.v:34318$1235 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 + attribute \src "libresoc.v:34319.5-34319.29" + switch \initial + attribute \src "libresoc.v:34319.9-34319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$1237 3'111 + case + assign $1\req_l_r_req$next[2:0]$1237 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 + end + attribute \src "libresoc.v:34327.3-34351.6" + process $proc$libresoc.v:34327$1238 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 + assign $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 + assign $0\alu_branch0_br_op__insn_type$next[6:0]$1244 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 + assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 + assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 + assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 + assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 + attribute \src "libresoc.v:34328.5-34328.29" + switch \initial + attribute \src "libresoc.v:34328.9-34328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + case + assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia + assign $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data + assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok + assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn + assign $1\alu_branch0_br_op__insn_type$next[6:0]$1252 \alu_branch0_br_op__insn_type + assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 \alu_branch0_br_op__is_32bit + assign $1\alu_branch0_br_op__lk$next[0:0]$1254 \alu_branch0_br_op__lk + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 1'0 + case + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + end + sync always + update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 + update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 + update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 + end + attribute \src "libresoc.v:34352.3-34373.6" + process $proc$libresoc.v:34352$1257 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 + assign { } { } + assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 + attribute \src "libresoc.v:34353.5-34353.29" + switch \initial + attribute \src "libresoc.v:34353.9-34353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__fast1_ok$next[0:0]$1261 $1\data_r0__fast1$next[63:0]$1260 } { \fast1_ok \alu_branch0_fast1 } + case + assign $1\data_r0__fast1$next[63:0]$1260 \data_r0__fast1 + assign $1\data_r0__fast1_ok$next[0:0]$1261 \data_r0__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__fast1_ok$next[0:0]$1263 $2\data_r0__fast1$next[63:0]$1262 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__fast1$next[63:0]$1262 $1\data_r0__fast1$next[63:0]$1260 + assign $2\data_r0__fast1_ok$next[0:0]$1263 $1\data_r0__fast1_ok$next[0:0]$1261 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__fast1_ok$next[0:0]$1264 1'0 + case + assign $3\data_r0__fast1_ok$next[0:0]$1264 $2\data_r0__fast1_ok$next[0:0]$1263 + end + sync always + update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 + update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 + end + attribute \src "libresoc.v:34374.3-34395.6" + process $proc$libresoc.v:34374$1265 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 + assign { } { } + assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 + attribute \src "libresoc.v:34375.5-34375.29" + switch \initial + attribute \src "libresoc.v:34375.9-34375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast2_ok$next[0:0]$1269 $1\data_r1__fast2$next[63:0]$1268 } { \fast2_ok \alu_branch0_fast2 } + case + assign $1\data_r1__fast2$next[63:0]$1268 \data_r1__fast2 + assign $1\data_r1__fast2_ok$next[0:0]$1269 \data_r1__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast2_ok$next[0:0]$1271 $2\data_r1__fast2$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast2$next[63:0]$1270 $1\data_r1__fast2$next[63:0]$1268 + assign $2\data_r1__fast2_ok$next[0:0]$1271 $1\data_r1__fast2_ok$next[0:0]$1269 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast2_ok$next[0:0]$1272 1'0 + case + assign $3\data_r1__fast2_ok$next[0:0]$1272 $2\data_r1__fast2_ok$next[0:0]$1271 + end + sync always + update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 + update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 + end + attribute \src "libresoc.v:34396.3-34417.6" + process $proc$libresoc.v:34396$1273 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 + assign { } { } + assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 + attribute \src "libresoc.v:34397.5-34397.29" + switch \initial + attribute \src "libresoc.v:34397.9-34397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__nia_ok$next[0:0]$1277 $1\data_r2__nia$next[63:0]$1276 } { \nia_ok \alu_branch0_nia } + case + assign $1\data_r2__nia$next[63:0]$1276 \data_r2__nia + assign $1\data_r2__nia_ok$next[0:0]$1277 \data_r2__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__nia_ok$next[0:0]$1279 $2\data_r2__nia$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__nia$next[63:0]$1278 $1\data_r2__nia$next[63:0]$1276 + assign $2\data_r2__nia_ok$next[0:0]$1279 $1\data_r2__nia_ok$next[0:0]$1277 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__nia_ok$next[0:0]$1280 1'0 + case + assign $3\data_r2__nia_ok$next[0:0]$1280 $2\data_r2__nia_ok$next[0:0]$1279 + end + sync always + update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 + update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 + end + attribute \src "libresoc.v:34418.3-34427.6" + process $proc$libresoc.v:34418$1281 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 + attribute \src "libresoc.v:34419.5-34419.29" + switch \initial + attribute \src "libresoc.v:34419.9-34419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$1283 \src1_i + case + assign $1\src_r0$next[63:0]$1283 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$1282 + end + attribute \src "libresoc.v:34428.3-34437.6" + process $proc$libresoc.v:34428$1284 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 + attribute \src "libresoc.v:34429.5-34429.29" + switch \initial + attribute \src "libresoc.v:34429.9-34429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$1286 \src_or_imm + case + assign $1\src_r1$next[63:0]$1286 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$1285 + end + attribute \src "libresoc.v:34438.3-34447.6" + process $proc$libresoc.v:34438$1287 + assign { } { } + assign { } { } + assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 + attribute \src "libresoc.v:34439.5-34439.29" + switch \initial + attribute \src "libresoc.v:34439.9-34439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[3:0]$1289 \src3_i + case + assign $1\src_r2$next[3:0]$1289 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[3:0]$1288 + end + attribute \src "libresoc.v:34448.3-34456.6" + process $proc$libresoc.v:34448$1290 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 + attribute \src "libresoc.v:34449.5-34449.29" + switch \initial + attribute \src "libresoc.v:34449.9-34449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$1292 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$1292 \$87 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 + end + attribute \src "libresoc.v:34457.3-34465.6" + process $proc$libresoc.v:34457$1293 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 + attribute \src "libresoc.v:34458.5-34458.29" + switch \initial + attribute \src "libresoc.v:34458.9-34458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$1295 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$1295 \$89 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 + end + attribute \src "libresoc.v:34466.3-34475.6" + process $proc$libresoc.v:34466$1296 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:34467.5-34467.29" + switch \initial + attribute \src "libresoc.v:34467.9-34467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__fast1 + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:34476.3-34485.6" + process $proc$libresoc.v:34476$1297 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:34477.5-34477.29" + switch \initial + attribute \src "libresoc.v:34477.9-34477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast2 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:34486.3-34495.6" + process $proc$libresoc.v:34486$1298 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:34487.5-34487.29" + switch \initial + attribute \src "libresoc.v:34487.9-34487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__nia + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:34496.3-34504.6" + process $proc$libresoc.v:34496$1299 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 + attribute \src "libresoc.v:34497.5-34497.29" + switch \initial + attribute \src "libresoc.v:34497.9-34497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$1301 3'000 + case + assign $1\prev_wr_go$next[2:0]$1301 \$21 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:34580$1340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:34577$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \Y $not$libresoc.v:34577$1337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:34579$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:34579$1339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:34582$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:34582$1342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:34576$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_busy + connect \Y $or$libresoc.v:34576$1336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:34578$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \B \q_int + connect \Y $or$libresoc.v:34578$1338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:34581$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_busy + connect \Y $or$libresoc.v:34581$1341_Y + end + attribute \src "libresoc.v:34540.7-34540.20" + process $proc$libresoc.v:34540$1347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34564.7-34564.19" + process $proc$libresoc.v:34564$1348 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:34583.3-34584.27" + process $proc$libresoc.v:34583$1343 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:34585.3-34593.6" + process $proc$libresoc.v:34585$1344 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34586.5-34586.29" + switch \initial + attribute \src "libresoc.v:34586.9-34586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1346 1'0 + case + assign $1\q_int$next[0:0]$1346 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1345 + end + connect \$9 $and$libresoc.v:34575$1335_Y + connect \$11 $or$libresoc.v:34576$1336_Y + connect \$13 $not$libresoc.v:34577$1337_Y + connect \$15 $or$libresoc.v:34578$1338_Y + connect \$1 $not$libresoc.v:34579$1339_Y + connect \$3 $and$libresoc.v:34580$1340_Y + connect \$5 $or$libresoc.v:34581$1341_Y + connect \$7 $not$libresoc.v:34582$1342_Y + connect \qlq_busy \$15 + connect \qn_busy \$13 + connect \q_busy \$11 +end +attribute \src "libresoc.v:34601.1-36209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +attribute \generator "nMigen" +module \clz + attribute \src "libresoc.v:35076.3-35090.6" + wire width 2 $0\cnt_1_0[1:0] + attribute \src "libresoc.v:35166.3-35180.6" + wire width 2 $0\cnt_1_10[1:0] + attribute \src "libresoc.v:35181.3-35195.6" + wire width 2 $0\cnt_1_11[1:0] + attribute \src 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width 2 \pair48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" + wire width 64 input 2 \sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34983$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_2 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34983$1349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34984$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_0 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34984$1350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34986$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_6 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34986$1352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34987$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_4 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34987$1353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34989$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_10 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34989$1355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34990$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_8 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34990$1356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34992$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_14 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34992$1358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34993$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_12 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34993$1359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34996$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_18 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34996$1362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34997$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_16 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34997$1363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34999$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_22 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34999$1365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35000$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_20 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:35000$1366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35002$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_26 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:35002$1368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35003$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_24 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:35003$1369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35005$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_5 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35005$1371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35006$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_30 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:35006$1372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35007$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_28 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:35007$1373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35009$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_2 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35009$1375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35010$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_0 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35010$1376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35012$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_6 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35012$1378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35013$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_4 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35013$1379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35015$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_10 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35015$1381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35016$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_4 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35016$1382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35017$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_8 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35017$1383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35019$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_14 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35019$1385_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35020$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_12 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:35020$1386_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35022$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_2 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:35022$1388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35023$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_0 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:35023$1389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35025$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_6 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:35025$1391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35026$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_4 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:35026$1392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35029$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_2 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:35029$1395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35030$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_0 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:35030$1396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35032$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_1 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35032$1398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35033$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_7 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35033$1399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35034$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_6 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35034$1400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35036$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_9 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35036$1402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35037$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_8 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35037$1403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35039$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_11 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35039$1405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35040$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_10 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35040$1406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35042$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_13 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35042$1408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35043$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_0 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35043$1409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35044$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_12 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35044$1410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35046$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_15 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35046$1412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35047$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_14 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35047$1413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35049$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_17 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35049$1415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35050$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_16 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35050$1416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35052$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_19 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35052$1418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35053$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_18 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35053$1419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35056$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_21 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35056$1422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35057$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_20 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35057$1423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35059$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_23 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35059$1425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35060$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_22 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35060$1426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35062$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_25 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35062$1428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35063$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_24 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35063$1429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35065$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_3 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35065$1431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35066$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_27 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35066$1432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35067$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_26 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35067$1433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35069$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_29 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35069$1435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35070$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_28 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35070$1436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35072$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_31 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35072$1438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:35073$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_30 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:35073$1439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:35075$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_2 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:35075$1441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34985$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_0 [1:0] } + connect \Y $pos$libresoc.v:34985$1351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34988$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_4 [1:0] } + connect \Y $pos$libresoc.v:34988$1354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34991$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_8 [1:0] } + connect \Y $pos$libresoc.v:34991$1357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34994$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_2 [0] } + connect \Y $pos$libresoc.v:34994$1360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34995$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_12 [1:0] } + connect \Y $pos$libresoc.v:34995$1361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34998$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_16 [1:0] } + connect \Y $pos$libresoc.v:34998$1364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35001$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_20 [1:0] } + connect \Y $pos$libresoc.v:35001$1367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35004$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_24 [1:0] } + connect \Y $pos$libresoc.v:35004$1370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35008$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_28 [1:0] } + connect \Y $pos$libresoc.v:35008$1374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35011$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_0 [2:0] } + connect \Y $pos$libresoc.v:35011$1377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35014$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_4 [2:0] } + connect \Y $pos$libresoc.v:35014$1380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35018$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_8 [2:0] } + connect \Y $pos$libresoc.v:35018$1384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35021$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_12 [2:0] } + connect \Y $pos$libresoc.v:35021$1387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35024$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_0 [3:0] } + connect \Y $pos$libresoc.v:35024$1390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35027$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_4 [0] } + connect \Y $pos$libresoc.v:35027$1393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35028$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_4 [3:0] } + connect \Y $pos$libresoc.v:35028$1394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35031$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'01 \cnt_5_0 [4:0] } + connect \Y $pos$libresoc.v:35031$1397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35035$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_6 [0] } + connect \Y $pos$libresoc.v:35035$1401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35038$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_8 [0] } + connect \Y $pos$libresoc.v:35038$1404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35041$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_10 [0] } + connect \Y $pos$libresoc.v:35041$1407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35045$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_12 [0] } + connect \Y $pos$libresoc.v:35045$1411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35048$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_14 [0] } + connect \Y $pos$libresoc.v:35048$1414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35051$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_16 [0] } + connect \Y $pos$libresoc.v:35051$1417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35054$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_0 [0] } + connect \Y $pos$libresoc.v:35054$1420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35055$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_18 [0] } + connect \Y $pos$libresoc.v:35055$1421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35058$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_20 [0] } + connect \Y $pos$libresoc.v:35058$1424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35061$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_22 [0] } + connect \Y $pos$libresoc.v:35061$1427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35064$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_24 [0] } + connect \Y $pos$libresoc.v:35064$1430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35068$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_26 [0] } + connect \Y $pos$libresoc.v:35068$1434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35071$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_28 [0] } + connect \Y $pos$libresoc.v:35071$1437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:35074$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_30 [0] } + connect \Y $pos$libresoc.v:35074$1440_Y + end + attribute \src "libresoc.v:34602.7-34602.20" + process $proc$libresoc.v:34602$1505 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:35076.3-35090.6" + process $proc$libresoc.v:35076$1442 + assign { } { } + assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] + attribute \src "libresoc.v:35077.5-35077.29" + switch \initial + attribute \src "libresoc.v:35077.9-35077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair0 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_0[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_0[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_0[1:0] 2'00 + end + sync always + update \cnt_1_0 $0\cnt_1_0[1:0] + end + attribute \src "libresoc.v:35091.3-35105.6" + process $proc$libresoc.v:35091$1443 + assign { } { } + assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] + attribute \src "libresoc.v:35092.5-35092.29" + switch \initial + attribute \src "libresoc.v:35092.9-35092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair10 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_5[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_5[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_5[1:0] 2'00 + end + sync always + update \cnt_1_5 $0\cnt_1_5[1:0] + end + attribute \src "libresoc.v:35106.3-35120.6" + process $proc$libresoc.v:35106$1444 + assign { } { } + assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] + attribute \src "libresoc.v:35107.5-35107.29" + switch \initial + attribute \src "libresoc.v:35107.9-35107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair12 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_6[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_6[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_6[1:0] 2'00 + end + sync always + update \cnt_1_6 $0\cnt_1_6[1:0] + end + attribute \src "libresoc.v:35121.3-35135.6" + process $proc$libresoc.v:35121$1445 + assign { } { } + assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] + attribute \src "libresoc.v:35122.5-35122.29" + switch \initial + attribute \src "libresoc.v:35122.9-35122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair14 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_7[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_7[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_7[1:0] 2'00 + end + sync always + update \cnt_1_7 $0\cnt_1_7[1:0] + end + attribute \src "libresoc.v:35136.3-35150.6" + process $proc$libresoc.v:35136$1446 + assign { } { } + assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] + attribute \src "libresoc.v:35137.5-35137.29" + switch \initial + attribute \src "libresoc.v:35137.9-35137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair16 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_8[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_8[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_8[1:0] 2'00 + end + sync always + update \cnt_1_8 $0\cnt_1_8[1:0] + end + attribute \src "libresoc.v:35151.3-35165.6" + process $proc$libresoc.v:35151$1447 + assign { } { } + assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] + attribute \src "libresoc.v:35152.5-35152.29" + switch \initial + attribute \src "libresoc.v:35152.9-35152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair18 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_9[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_9[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_9[1:0] 2'00 + end + sync always + update \cnt_1_9 $0\cnt_1_9[1:0] + end + attribute \src "libresoc.v:35166.3-35180.6" + process $proc$libresoc.v:35166$1448 + assign { } { } + assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] + attribute \src "libresoc.v:35167.5-35167.29" + switch \initial + attribute \src "libresoc.v:35167.9-35167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair20 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_10[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_10[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_10[1:0] 2'00 + end + sync always + update \cnt_1_10 $0\cnt_1_10[1:0] + end + attribute \src "libresoc.v:35181.3-35195.6" + process $proc$libresoc.v:35181$1449 + assign { } { } + assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] + attribute \src "libresoc.v:35182.5-35182.29" + switch \initial + attribute \src "libresoc.v:35182.9-35182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair22 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_11[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_11[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_11[1:0] 2'00 + end + sync always + update \cnt_1_11 $0\cnt_1_11[1:0] + end + attribute \src "libresoc.v:35196.3-35210.6" + process $proc$libresoc.v:35196$1450 + assign { } { } + assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] + attribute \src "libresoc.v:35197.5-35197.29" + switch \initial + attribute \src "libresoc.v:35197.9-35197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair24 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_12[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_12[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_12[1:0] 2'00 + end + sync always + update \cnt_1_12 $0\cnt_1_12[1:0] + end + attribute \src "libresoc.v:35211.3-35225.6" + process $proc$libresoc.v:35211$1451 + assign { } { } + assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] + attribute \src "libresoc.v:35212.5-35212.29" + switch \initial + attribute \src "libresoc.v:35212.9-35212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair26 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_13[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_13[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_13[1:0] 2'00 + end + sync always + update \cnt_1_13 $0\cnt_1_13[1:0] + end + attribute \src "libresoc.v:35226.3-35240.6" + process $proc$libresoc.v:35226$1452 + assign { } { } + assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] + attribute \src "libresoc.v:35227.5-35227.29" + switch \initial + attribute \src "libresoc.v:35227.9-35227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair28 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_14[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_14[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_14[1:0] 2'00 + end + sync always + update \cnt_1_14 $0\cnt_1_14[1:0] + end + attribute \src "libresoc.v:35241.3-35255.6" + process $proc$libresoc.v:35241$1453 + assign { } { } + assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] + attribute \src "libresoc.v:35242.5-35242.29" + switch \initial + attribute \src "libresoc.v:35242.9-35242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair2 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_1[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_1[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_1[1:0] 2'00 + end + sync always + update \cnt_1_1 $0\cnt_1_1[1:0] + end + attribute \src "libresoc.v:35256.3-35270.6" + process $proc$libresoc.v:35256$1454 + assign { } { } + assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] + attribute \src "libresoc.v:35257.5-35257.29" + switch \initial + attribute \src "libresoc.v:35257.9-35257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair30 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_15[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_15[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_15[1:0] 2'00 + end + sync always + update \cnt_1_15 $0\cnt_1_15[1:0] + end + attribute \src "libresoc.v:35271.3-35285.6" + process $proc$libresoc.v:35271$1455 + assign { } { } + assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] + attribute \src "libresoc.v:35272.5-35272.29" + switch \initial + attribute \src "libresoc.v:35272.9-35272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair32 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_16[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_16[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_16[1:0] 2'00 + end + sync always + update \cnt_1_16 $0\cnt_1_16[1:0] + end + attribute \src "libresoc.v:35286.3-35300.6" + process $proc$libresoc.v:35286$1456 + assign { } { } + assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] + attribute \src "libresoc.v:35287.5-35287.29" + switch \initial + attribute \src "libresoc.v:35287.9-35287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair34 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_17[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_17[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_17[1:0] 2'00 + end + sync always + update \cnt_1_17 $0\cnt_1_17[1:0] + end + attribute \src "libresoc.v:35301.3-35315.6" + process $proc$libresoc.v:35301$1457 + assign { } { } + assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] + attribute \src "libresoc.v:35302.5-35302.29" + switch \initial + attribute \src "libresoc.v:35302.9-35302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair36 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_18[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_18[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_18[1:0] 2'00 + end + sync always + update \cnt_1_18 $0\cnt_1_18[1:0] + end + attribute \src "libresoc.v:35316.3-35330.6" + process $proc$libresoc.v:35316$1458 + assign { } { } + assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] + attribute \src "libresoc.v:35317.5-35317.29" + switch \initial + attribute \src "libresoc.v:35317.9-35317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair38 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_19[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_19[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_19[1:0] 2'00 + end + sync always + update \cnt_1_19 $0\cnt_1_19[1:0] + end + attribute \src "libresoc.v:35331.3-35345.6" + process $proc$libresoc.v:35331$1459 + assign { } { } + assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] + attribute \src "libresoc.v:35332.5-35332.29" + switch \initial + attribute \src "libresoc.v:35332.9-35332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair40 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_20[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_20[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_20[1:0] 2'00 + end + sync always + update \cnt_1_20 $0\cnt_1_20[1:0] + end + attribute \src "libresoc.v:35346.3-35360.6" + process $proc$libresoc.v:35346$1460 + assign { } { } + assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] + attribute \src "libresoc.v:35347.5-35347.29" + switch \initial + attribute \src "libresoc.v:35347.9-35347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair42 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_21[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_21[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_21[1:0] 2'00 + end + sync always + update \cnt_1_21 $0\cnt_1_21[1:0] + end + attribute \src "libresoc.v:35361.3-35375.6" + process $proc$libresoc.v:35361$1461 + assign { } { } + assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] + attribute \src "libresoc.v:35362.5-35362.29" + switch \initial + attribute \src "libresoc.v:35362.9-35362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair44 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_22[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_22[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_22[1:0] 2'00 + end + sync always + update \cnt_1_22 $0\cnt_1_22[1:0] + end + attribute \src "libresoc.v:35376.3-35390.6" + process $proc$libresoc.v:35376$1462 + assign { } { } + assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] + attribute \src "libresoc.v:35377.5-35377.29" + switch \initial + attribute \src "libresoc.v:35377.9-35377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair46 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_23[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_23[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_23[1:0] 2'00 + end + sync always + update \cnt_1_23 $0\cnt_1_23[1:0] + end + attribute \src "libresoc.v:35391.3-35405.6" + process $proc$libresoc.v:35391$1463 + assign { } { } + assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] + attribute \src "libresoc.v:35392.5-35392.29" + switch \initial + attribute \src "libresoc.v:35392.9-35392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair48 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_24[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_24[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_24[1:0] 2'00 + end + sync always + update \cnt_1_24 $0\cnt_1_24[1:0] + end + attribute \src "libresoc.v:35406.3-35420.6" + process $proc$libresoc.v:35406$1464 + assign { } { } + assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] + attribute \src "libresoc.v:35407.5-35407.29" + switch \initial + attribute \src "libresoc.v:35407.9-35407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair4 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_2[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_2[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_2[1:0] 2'00 + end + sync always + update \cnt_1_2 $0\cnt_1_2[1:0] + end + attribute \src "libresoc.v:35421.3-35435.6" + process $proc$libresoc.v:35421$1465 + assign { } { } + assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] + attribute \src "libresoc.v:35422.5-35422.29" + switch \initial + attribute \src "libresoc.v:35422.9-35422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair50 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_25[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_25[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_25[1:0] 2'00 + end + sync always + update \cnt_1_25 $0\cnt_1_25[1:0] + end + attribute \src "libresoc.v:35436.3-35450.6" + process $proc$libresoc.v:35436$1466 + assign { } { } + assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] + attribute \src "libresoc.v:35437.5-35437.29" + switch \initial + attribute \src "libresoc.v:35437.9-35437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair52 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_26[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_26[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_26[1:0] 2'00 + end + sync always + update \cnt_1_26 $0\cnt_1_26[1:0] + end + attribute \src "libresoc.v:35451.3-35465.6" + process $proc$libresoc.v:35451$1467 + assign { } { } + assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] + attribute \src "libresoc.v:35452.5-35452.29" + switch \initial + attribute \src "libresoc.v:35452.9-35452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair54 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_27[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_27[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_27[1:0] 2'00 + end + sync always + update \cnt_1_27 $0\cnt_1_27[1:0] + end + attribute \src "libresoc.v:35466.3-35480.6" + process $proc$libresoc.v:35466$1468 + assign { } { } + assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] + attribute \src "libresoc.v:35467.5-35467.29" + switch \initial + attribute \src "libresoc.v:35467.9-35467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair56 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_28[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_28[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_28[1:0] 2'00 + end + sync always + update \cnt_1_28 $0\cnt_1_28[1:0] + end + attribute \src "libresoc.v:35481.3-35495.6" + process $proc$libresoc.v:35481$1469 + assign { } { } + assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] + attribute \src "libresoc.v:35482.5-35482.29" + switch \initial + attribute \src "libresoc.v:35482.9-35482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair58 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_29[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_29[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_29[1:0] 2'00 + end + sync always + update \cnt_1_29 $0\cnt_1_29[1:0] + end + attribute \src "libresoc.v:35496.3-35510.6" + process $proc$libresoc.v:35496$1470 + assign { } { } + assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] + attribute \src "libresoc.v:35497.5-35497.29" + switch \initial + attribute \src "libresoc.v:35497.9-35497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair60 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_30[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_30[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_30[1:0] 2'00 + end + sync always + update \cnt_1_30 $0\cnt_1_30[1:0] + end + attribute \src "libresoc.v:35511.3-35525.6" + process $proc$libresoc.v:35511$1471 + assign { } { } + assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] + attribute \src "libresoc.v:35512.5-35512.29" + switch \initial + attribute \src "libresoc.v:35512.9-35512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair62 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_31[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_31[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_31[1:0] 2'00 + end + sync always + update \cnt_1_31 $0\cnt_1_31[1:0] + end + attribute \src "libresoc.v:35526.3-35545.6" + process $proc$libresoc.v:35526$1472 + assign { } { } + assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] + attribute \src "libresoc.v:35527.5-35527.29" + switch \initial + attribute \src "libresoc.v:35527.9-35527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_0[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_0[2:0] \$5 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } + end + sync always + update \cnt_2_0 $0\cnt_2_0[2:0] + end + attribute \src "libresoc.v:35546.3-35565.6" + process $proc$libresoc.v:35546$1473 + assign { } { } + assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] + attribute \src "libresoc.v:35547.5-35547.29" + switch \initial + attribute \src "libresoc.v:35547.9-35547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_2[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_2[2:0] \$11 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } + end + sync always + update \cnt_2_2 $0\cnt_2_2[2:0] + end + attribute \src "libresoc.v:35566.3-35585.6" + process $proc$libresoc.v:35566$1474 + assign { } { } + assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] + attribute \src "libresoc.v:35567.5-35567.29" + switch \initial + attribute \src "libresoc.v:35567.9-35567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_4[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_4[2:0] \$17 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } + end + sync always + update \cnt_2_4 $0\cnt_2_4[2:0] + end + attribute \src "libresoc.v:35586.3-35605.6" + process $proc$libresoc.v:35586$1475 + assign { } { } + assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] + attribute \src "libresoc.v:35587.5-35587.29" + switch \initial + attribute \src "libresoc.v:35587.9-35587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_6[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_6[2:0] \$23 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } + end + sync always + update \cnt_2_6 $0\cnt_2_6[2:0] + end + attribute \src "libresoc.v:35606.3-35625.6" + process $proc$libresoc.v:35606$1476 + assign { } { } + assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] + attribute \src "libresoc.v:35607.5-35607.29" + switch \initial + attribute \src "libresoc.v:35607.9-35607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_8[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_8[2:0] \$29 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } + end + sync always + update \cnt_2_8 $0\cnt_2_8[2:0] + end + attribute \src "libresoc.v:35626.3-35645.6" + process $proc$libresoc.v:35626$1477 + assign { } { } + assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] + attribute \src "libresoc.v:35627.5-35627.29" + switch \initial + attribute \src "libresoc.v:35627.9-35627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_10[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_10[2:0] \$35 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } + end + sync always + update \cnt_2_10 $0\cnt_2_10[2:0] + end + attribute \src "libresoc.v:35646.3-35660.6" + process $proc$libresoc.v:35646$1478 + assign { } { } + assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] + attribute \src "libresoc.v:35647.5-35647.29" + switch \initial + attribute \src "libresoc.v:35647.9-35647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair6 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_3[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_3[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_3[1:0] 2'00 + end + sync always + update \cnt_1_3 $0\cnt_1_3[1:0] + end + attribute \src "libresoc.v:35661.3-35680.6" + process $proc$libresoc.v:35661$1479 + assign { } { } + assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] + attribute \src "libresoc.v:35662.5-35662.29" + switch \initial + attribute \src "libresoc.v:35662.9-35662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_12[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_12[2:0] \$41 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } + end + sync always + update \cnt_2_12 $0\cnt_2_12[2:0] + end + attribute \src "libresoc.v:35681.3-35700.6" + process $proc$libresoc.v:35681$1480 + assign { } { } + assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] + attribute \src "libresoc.v:35682.5-35682.29" + switch \initial + attribute \src "libresoc.v:35682.9-35682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_14[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_14[2:0] \$47 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } + end + sync always + update \cnt_2_14 $0\cnt_2_14[2:0] + end + attribute \src "libresoc.v:35701.3-35720.6" + process $proc$libresoc.v:35701$1481 + assign { } { } + assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] + attribute \src "libresoc.v:35702.5-35702.29" + switch \initial + attribute \src "libresoc.v:35702.9-35702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_16[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_16[2:0] \$53 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } + end + sync always + update \cnt_2_16 $0\cnt_2_16[2:0] + end + attribute \src "libresoc.v:35721.3-35740.6" + process $proc$libresoc.v:35721$1482 + assign { } { } + assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] + attribute \src "libresoc.v:35722.5-35722.29" + switch \initial + attribute \src "libresoc.v:35722.9-35722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_18[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_18[2:0] \$59 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } + end + sync always + update \cnt_2_18 $0\cnt_2_18[2:0] + end + attribute \src "libresoc.v:35741.3-35760.6" + process $proc$libresoc.v:35741$1483 + assign { } { } + assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] + attribute \src "libresoc.v:35742.5-35742.29" + switch \initial + attribute \src "libresoc.v:35742.9-35742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_20[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_20[2:0] \$65 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } + end + sync always + update \cnt_2_20 $0\cnt_2_20[2:0] + end + attribute \src "libresoc.v:35761.3-35780.6" + process $proc$libresoc.v:35761$1484 + assign { } { } + assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] + attribute \src "libresoc.v:35762.5-35762.29" + switch \initial + attribute \src "libresoc.v:35762.9-35762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_22[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_22[2:0] \$71 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } + end + sync always + update \cnt_2_22 $0\cnt_2_22[2:0] + end + attribute \src "libresoc.v:35781.3-35800.6" + process $proc$libresoc.v:35781$1485 + assign { } { } + assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] + attribute \src "libresoc.v:35782.5-35782.29" + switch \initial + attribute \src "libresoc.v:35782.9-35782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_24[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_24[2:0] \$77 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } + end + sync always + update \cnt_2_24 $0\cnt_2_24[2:0] + end + attribute \src "libresoc.v:35801.3-35820.6" + process $proc$libresoc.v:35801$1486 + assign { } { } + assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] + attribute \src "libresoc.v:35802.5-35802.29" + switch \initial + attribute \src "libresoc.v:35802.9-35802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_26[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_26[2:0] \$83 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } + end + sync always + update \cnt_2_26 $0\cnt_2_26[2:0] + end + attribute \src "libresoc.v:35821.3-35840.6" + process $proc$libresoc.v:35821$1487 + assign { } { } + assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] + attribute \src "libresoc.v:35822.5-35822.29" + switch \initial + attribute \src "libresoc.v:35822.9-35822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_28[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_28[2:0] \$89 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } + end + sync always + update \cnt_2_28 $0\cnt_2_28[2:0] + end + attribute \src "libresoc.v:35841.3-35860.6" + process $proc$libresoc.v:35841$1488 + assign { } { } + assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] + attribute \src "libresoc.v:35842.5-35842.29" + switch \initial + attribute \src "libresoc.v:35842.9-35842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_30[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_30[2:0] \$95 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } + end + sync always + update \cnt_2_30 $0\cnt_2_30[2:0] + end + attribute \src "libresoc.v:35861.3-35880.6" + process $proc$libresoc.v:35861$1489 + assign { } { } + assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] + attribute \src "libresoc.v:35862.5-35862.29" + switch \initial + attribute \src "libresoc.v:35862.9-35862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_0[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_0[3:0] \$101 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } + end + sync always + update \cnt_3_0 $0\cnt_3_0[3:0] + end + attribute \src "libresoc.v:35881.3-35900.6" + process $proc$libresoc.v:35881$1490 + assign { } { } + assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] + attribute \src "libresoc.v:35882.5-35882.29" + switch \initial + attribute \src "libresoc.v:35882.9-35882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_2[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_2[3:0] \$107 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } + end + sync always + update \cnt_3_2 $0\cnt_3_2[3:0] + end + attribute \src "libresoc.v:35901.3-35920.6" + process $proc$libresoc.v:35901$1491 + assign { } { } + assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] + attribute \src "libresoc.v:35902.5-35902.29" + switch \initial + attribute \src "libresoc.v:35902.9-35902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_4[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_4[3:0] \$113 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } + end + sync always + update \cnt_3_4 $0\cnt_3_4[3:0] + end + attribute \src "libresoc.v:35921.3-35940.6" + process $proc$libresoc.v:35921$1492 + assign { } { } + assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] + attribute \src "libresoc.v:35922.5-35922.29" + switch \initial + attribute \src "libresoc.v:35922.9-35922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_6[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_6[3:0] \$119 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } + end + sync always + update \cnt_3_6 $0\cnt_3_6[3:0] + end + attribute \src "libresoc.v:35941.3-35960.6" + process $proc$libresoc.v:35941$1493 + assign { } { } + assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] + attribute \src "libresoc.v:35942.5-35942.29" + switch \initial + attribute \src "libresoc.v:35942.9-35942.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_8[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_8[3:0] \$125 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } + end + sync always + update \cnt_3_8 $0\cnt_3_8[3:0] + end + attribute \src "libresoc.v:35961.3-35980.6" + process $proc$libresoc.v:35961$1494 + assign { } { } + assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] + attribute \src "libresoc.v:35962.5-35962.29" + switch \initial + attribute \src "libresoc.v:35962.9-35962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_10[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_10[3:0] \$131 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } + end + sync always + update \cnt_3_10 $0\cnt_3_10[3:0] + end + attribute \src "libresoc.v:35981.3-36000.6" + process $proc$libresoc.v:35981$1495 + assign { } { } + assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] + attribute \src "libresoc.v:35982.5-35982.29" + switch \initial + attribute \src "libresoc.v:35982.9-35982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_12[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_12[3:0] \$137 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } + end + sync always + update \cnt_3_12 $0\cnt_3_12[3:0] + end + attribute \src "libresoc.v:36001.3-36020.6" + process $proc$libresoc.v:36001$1496 + assign { } { } + assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] + attribute \src "libresoc.v:36002.5-36002.29" + switch \initial + attribute \src "libresoc.v:36002.9-36002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$139 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_14[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_14[3:0] \$143 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } + end + sync always + update \cnt_3_14 $0\cnt_3_14[3:0] + end + attribute \src "libresoc.v:36021.3-36040.6" + process $proc$libresoc.v:36021$1497 + assign { } { } + assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] + attribute \src "libresoc.v:36022.5-36022.29" + switch \initial + attribute \src "libresoc.v:36022.9-36022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$147 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_0[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_0[4:0] \$149 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } + end + sync always + update \cnt_4_0 $0\cnt_4_0[4:0] + end + attribute \src "libresoc.v:36041.3-36060.6" + process $proc$libresoc.v:36041$1498 + assign { } { } + assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] + attribute \src "libresoc.v:36042.5-36042.29" + switch \initial + attribute \src "libresoc.v:36042.9-36042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$151 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_2[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_2[4:0] \$155 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } + end + sync always + update \cnt_4_2 $0\cnt_4_2[4:0] + end + attribute \src "libresoc.v:36061.3-36075.6" + process $proc$libresoc.v:36061$1499 + assign { } { } + assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] + attribute \src "libresoc.v:36062.5-36062.29" + switch \initial + attribute \src "libresoc.v:36062.9-36062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair8 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_4[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_4[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_4[1:0] 2'00 + end + sync always + update \cnt_1_4 $0\cnt_1_4[1:0] + end + attribute \src "libresoc.v:36076.3-36095.6" + process $proc$libresoc.v:36076$1500 + assign { } { } + assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] + attribute \src "libresoc.v:36077.5-36077.29" + switch \initial + attribute \src "libresoc.v:36077.9-36077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$159 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_4[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_4[4:0] \$161 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } + end + sync always + update \cnt_4_4 $0\cnt_4_4[4:0] + end + attribute \src "libresoc.v:36096.3-36115.6" + process $proc$libresoc.v:36096$1501 + assign { } { } + assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] + attribute \src "libresoc.v:36097.5-36097.29" + switch \initial + attribute \src "libresoc.v:36097.9-36097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$163 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_6[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_6[4:0] \$167 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } + end + sync always + update \cnt_4_6 $0\cnt_4_6[4:0] + end + attribute \src "libresoc.v:36116.3-36135.6" + process $proc$libresoc.v:36116$1502 + assign { } { } + assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] + attribute \src "libresoc.v:36117.5-36117.29" + switch \initial + attribute \src "libresoc.v:36117.9-36117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$171 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_0[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_0[5:0] \$173 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } + end + sync always + update \cnt_5_0 $0\cnt_5_0[5:0] + end + attribute \src "libresoc.v:36136.3-36155.6" + process $proc$libresoc.v:36136$1503 + assign { } { } + assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] + attribute \src "libresoc.v:36137.5-36137.29" + switch \initial + attribute \src "libresoc.v:36137.9-36137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$175 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_2[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_2[5:0] \$179 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } + end + sync always + update \cnt_5_2 $0\cnt_5_2[5:0] + end + attribute \src "libresoc.v:36156.3-36175.6" + process $proc$libresoc.v:36156$1504 + assign { } { } + assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] + attribute \src "libresoc.v:36157.5-36157.29" + switch \initial + attribute \src "libresoc.v:36157.9-36157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$183 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_6_0[6:0] 7'1000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_6_0[6:0] \$185 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } + end + sync always + update \cnt_6_0 $0\cnt_6_0[6:0] + end + connect \$9 $eq$libresoc.v:34983$1349_Y + connect \$99 $eq$libresoc.v:34984$1350_Y + connect \$101 $pos$libresoc.v:34985$1351_Y + connect \$103 $eq$libresoc.v:34986$1352_Y + connect \$105 $eq$libresoc.v:34987$1353_Y + connect \$107 $pos$libresoc.v:34988$1354_Y + connect \$109 $eq$libresoc.v:34989$1355_Y + connect \$111 $eq$libresoc.v:34990$1356_Y + connect \$113 $pos$libresoc.v:34991$1357_Y + connect \$115 $eq$libresoc.v:34992$1358_Y + connect \$117 $eq$libresoc.v:34993$1359_Y + connect \$11 $pos$libresoc.v:34994$1360_Y + connect \$119 $pos$libresoc.v:34995$1361_Y + connect \$121 $eq$libresoc.v:34996$1362_Y + connect \$123 $eq$libresoc.v:34997$1363_Y + connect \$125 $pos$libresoc.v:34998$1364_Y + connect \$127 $eq$libresoc.v:34999$1365_Y + connect \$129 $eq$libresoc.v:35000$1366_Y + connect \$131 $pos$libresoc.v:35001$1367_Y + connect \$133 $eq$libresoc.v:35002$1368_Y + connect \$135 $eq$libresoc.v:35003$1369_Y + connect \$137 $pos$libresoc.v:35004$1370_Y + connect \$13 $eq$libresoc.v:35005$1371_Y + connect \$139 $eq$libresoc.v:35006$1372_Y + connect \$141 $eq$libresoc.v:35007$1373_Y + connect \$143 $pos$libresoc.v:35008$1374_Y + connect \$145 $eq$libresoc.v:35009$1375_Y + connect \$147 $eq$libresoc.v:35010$1376_Y + connect \$149 $pos$libresoc.v:35011$1377_Y + connect \$151 $eq$libresoc.v:35012$1378_Y + connect \$153 $eq$libresoc.v:35013$1379_Y + connect \$155 $pos$libresoc.v:35014$1380_Y + connect \$157 $eq$libresoc.v:35015$1381_Y + connect \$15 $eq$libresoc.v:35016$1382_Y + connect \$159 $eq$libresoc.v:35017$1383_Y + connect \$161 $pos$libresoc.v:35018$1384_Y + connect \$163 $eq$libresoc.v:35019$1385_Y + connect \$165 $eq$libresoc.v:35020$1386_Y + connect \$167 $pos$libresoc.v:35021$1387_Y + connect \$169 $eq$libresoc.v:35022$1388_Y + connect \$171 $eq$libresoc.v:35023$1389_Y + connect \$173 $pos$libresoc.v:35024$1390_Y + connect \$175 $eq$libresoc.v:35025$1391_Y + connect \$177 $eq$libresoc.v:35026$1392_Y + connect \$17 $pos$libresoc.v:35027$1393_Y + connect \$179 $pos$libresoc.v:35028$1394_Y + connect \$181 $eq$libresoc.v:35029$1395_Y + connect \$183 $eq$libresoc.v:35030$1396_Y + connect \$185 $pos$libresoc.v:35031$1397_Y + connect \$1 $eq$libresoc.v:35032$1398_Y + connect \$19 $eq$libresoc.v:35033$1399_Y + connect \$21 $eq$libresoc.v:35034$1400_Y + connect \$23 $pos$libresoc.v:35035$1401_Y + connect \$25 $eq$libresoc.v:35036$1402_Y + connect \$27 $eq$libresoc.v:35037$1403_Y + connect \$29 $pos$libresoc.v:35038$1404_Y + connect \$31 $eq$libresoc.v:35039$1405_Y + connect \$33 $eq$libresoc.v:35040$1406_Y + connect \$35 $pos$libresoc.v:35041$1407_Y + connect \$37 $eq$libresoc.v:35042$1408_Y + connect \$3 $eq$libresoc.v:35043$1409_Y + connect \$39 $eq$libresoc.v:35044$1410_Y + connect \$41 $pos$libresoc.v:35045$1411_Y + connect \$43 $eq$libresoc.v:35046$1412_Y + connect \$45 $eq$libresoc.v:35047$1413_Y + connect \$47 $pos$libresoc.v:35048$1414_Y + connect \$49 $eq$libresoc.v:35049$1415_Y + connect \$51 $eq$libresoc.v:35050$1416_Y + connect \$53 $pos$libresoc.v:35051$1417_Y + connect \$55 $eq$libresoc.v:35052$1418_Y + connect \$57 $eq$libresoc.v:35053$1419_Y + connect \$5 $pos$libresoc.v:35054$1420_Y + connect \$59 $pos$libresoc.v:35055$1421_Y + connect \$61 $eq$libresoc.v:35056$1422_Y + connect \$63 $eq$libresoc.v:35057$1423_Y + connect \$65 $pos$libresoc.v:35058$1424_Y + connect \$67 $eq$libresoc.v:35059$1425_Y + connect \$69 $eq$libresoc.v:35060$1426_Y + connect \$71 $pos$libresoc.v:35061$1427_Y + connect \$73 $eq$libresoc.v:35062$1428_Y + connect \$75 $eq$libresoc.v:35063$1429_Y + connect \$77 $pos$libresoc.v:35064$1430_Y + connect \$7 $eq$libresoc.v:35065$1431_Y + connect \$79 $eq$libresoc.v:35066$1432_Y + connect \$81 $eq$libresoc.v:35067$1433_Y + connect \$83 $pos$libresoc.v:35068$1434_Y + connect \$85 $eq$libresoc.v:35069$1435_Y + connect \$87 $eq$libresoc.v:35070$1436_Y + connect \$89 $pos$libresoc.v:35071$1437_Y + connect \$91 $eq$libresoc.v:35072$1438_Y + connect \$93 $eq$libresoc.v:35073$1439_Y + connect \$95 $pos$libresoc.v:35074$1440_Y + connect \$97 $eq$libresoc.v:35075$1441_Y + connect \lz \cnt_6_0 + connect \pair62 \sig_in [63:62] + connect \pair60 \sig_in [61:60] + connect \pair58 \sig_in [59:58] + connect \pair56 \sig_in [57:56] + connect \pair54 \sig_in [55:54] + connect \pair52 \sig_in [53:52] + connect \pair50 \sig_in [51:50] + connect \pair48 \sig_in [49:48] + connect \pair46 \sig_in [47:46] + connect \pair44 \sig_in [45:44] + connect \pair42 \sig_in [43:42] + connect \pair40 \sig_in [41:40] + connect \pair38 \sig_in [39:38] + connect \pair36 \sig_in [37:36] + connect \pair34 \sig_in [35:34] + connect \pair32 \sig_in [33:32] + connect \pair30 \sig_in [31:30] + connect \pair28 \sig_in [29:28] + connect \pair26 \sig_in [27:26] + connect \pair24 \sig_in [25:24] + connect \pair22 \sig_in [23:22] + connect \pair20 \sig_in [21:20] + connect \pair18 \sig_in [19:18] + connect \pair16 \sig_in [17:16] + connect \pair14 \sig_in [15:14] + connect \pair12 \sig_in [13:12] + connect \pair10 \sig_in [11:10] + connect \pair8 \sig_in [9:8] + connect \pair6 \sig_in [7:6] + connect \pair4 \sig_in [5:4] + connect \pair2 \sig_in [3:2] + connect \pair0 \sig_in [1:0] +end +attribute \src "libresoc.v:36213.1-49141.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core" +attribute \generator "nMigen" +module \core + attribute \src "libresoc.v:46587.3-46607.6" + wire $0\core_terminate_o$next[0:0]$2673 + attribute \src "libresoc.v:42982.3-42983.49" + wire $0\core_terminate_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $0\corebusy_o[0:0] + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $0\counter$next[1:0]$2654 + attribute \src "libresoc.v:42984.3-42985.31" + wire width 2 $0\counter[1:0] + attribute \src "libresoc.v:46412.3-46420.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:42918.3-42919.57" + wire $0\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:46393.3-46401.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:42920.3-42921.49" + wire $0\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:46458.3-46466.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:42916.3-42917.49" + wire $0\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:46568.3-46576.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:42914.3-42915.49" + wire $0\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:46374.3-46382.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 + attribute \src "libresoc.v:42922.3-42923.55" + wire $0\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:46608.3-46616.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 + attribute \src "libresoc.v:42912.3-42913.63" + wire $0\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:46675.3-46683.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 + attribute \src "libresoc.v:42908.3-42909.57" + wire $0\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:46627.3-46635.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 + attribute \src "libresoc.v:42910.3-42911.59" + wire $0\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:46723.3-46731.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 + attribute \src "libresoc.v:42906.3-42907.63" + wire $0\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:46742.3-46750.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 + attribute \src "libresoc.v:42904.3-42905.59" + wire $0\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:45823.3-45831.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2474 + attribute \src "libresoc.v:42980.3-42981.49" + wire $0\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:45842.3-45850.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2478 + attribute \src "libresoc.v:42978.3-42979.47" + wire $0\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:45918.3-45926.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2502 + attribute \src "libresoc.v:42970.3-42971.49" + wire $0\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:45975.3-45983.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2520 + attribute \src "libresoc.v:42964.3-42965.51" + wire $0\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:45880.3-45888.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2490 + attribute \src "libresoc.v:42974.3-42975.57" + wire $0\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:45937.3-45945.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2508 + attribute \src "libresoc.v:42968.3-42969.49" + wire $0\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:45956.3-45964.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 + attribute \src "libresoc.v:42966.3-42967.59" + wire $0\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:45899.3-45907.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2496 + attribute \src "libresoc.v:42972.3-42973.49" + wire $0\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:45861.3-45869.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2484 + attribute \src "libresoc.v:42976.3-42977.51" + wire $0\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:45994.3-46002.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2526 + attribute \src "libresoc.v:42962.3-42963.49" + wire $0\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:46013.3-46021.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2530 + attribute \src "libresoc.v:42960.3-42961.47" + wire $0\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:46070.3-46078.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2548 + attribute \src "libresoc.v:42954.3-42955.49" + wire $0\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:46127.3-46135.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2566 + attribute \src "libresoc.v:42948.3-42949.51" + wire $0\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:46051.3-46059.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2542 + attribute \src "libresoc.v:42956.3-42957.57" + wire $0\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:46089.3-46097.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2554 + attribute \src "libresoc.v:42952.3-42953.49" + wire $0\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:46108.3-46116.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 + attribute \src "libresoc.v:42950.3-42951.59" + wire $0\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:46032.3-46040.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2536 + attribute \src "libresoc.v:42958.3-42959.51" + wire $0\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:46165.3-46173.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2576 + attribute \src "libresoc.v:42944.3-42945.51" + wire $0\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:46146.3-46154.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 + attribute \src "libresoc.v:42946.3-42947.59" + wire $0\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:46791.3-46799.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 + attribute \src "libresoc.v:42902.3-42903.53" + wire $0\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:46298.3-46306.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 + attribute \src "libresoc.v:42930.3-42931.57" + wire $0\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:46336.3-46344.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 + attribute \src "libresoc.v:42926.3-42927.67" + wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:46317.3-46325.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 + attribute \src "libresoc.v:42928.3-42929.57" + wire $0\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:46355.3-46363.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 + attribute \src "libresoc.v:42924.3-42925.57" + wire $0\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:46184.3-46192.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 + attribute \src "libresoc.v:42942.3-42943.57" + wire $0\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:46241.3-46249.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 + attribute \src "libresoc.v:42936.3-42937.57" + wire $0\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:46203.3-46211.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 + attribute \src "libresoc.v:42940.3-42941.65" + wire $0\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:46260.3-46268.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 + attribute \src "libresoc.v:42934.3-42935.57" + wire $0\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:46279.3-46287.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 + attribute \src "libresoc.v:42932.3-42933.67" + wire $0\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:46222.3-46230.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 + attribute \src "libresoc.v:42938.3-42939.57" + wire $0\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:47566.3-47594.6" + wire $0\fus_cu_issue_i$13[0:0]$2821 + attribute \src "libresoc.v:47900.3-47928.6" + wire $0\fus_cu_issue_i$16[0:0]$2862 + attribute \src "libresoc.v:48219.3-48247.6" + wire $0\fus_cu_issue_i$19[0:0]$2881 + attribute \src "libresoc.v:43868.3-43896.6" + wire $0\fus_cu_issue_i$22[0:0]$2359 + attribute \src "libresoc.v:44042.3-44070.6" + wire $0\fus_cu_issue_i$25[0:0]$2373 + attribute \src "libresoc.v:44538.3-44566.6" + wire $0\fus_cu_issue_i$28[0:0]$2398 + attribute \src "libresoc.v:44860.3-44888.6" + wire $0\fus_cu_issue_i$31[0:0]$2417 + attribute \src "libresoc.v:45327.3-45355.6" + wire $0\fus_cu_issue_i$34[0:0]$2441 + attribute \src "libresoc.v:45765.3-45793.6" + wire $0\fus_cu_issue_i$37[0:0]$2464 + attribute \src "libresoc.v:47349.3-47377.6" + wire $0\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2829 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 + attribute \src "libresoc.v:47396.3-47424.6" + wire width 4 $0\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:47273.3-47301.6" + wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:47094.3-47122.6" + wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:47311.3-47339.6" + wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:46646.3-46674.6" + wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46933.3-46961.6" + wire $0\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:47018.3-47046.6" + wire $0\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:47188.3-47216.6" + wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:47226.3-47254.6" + wire $0\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:47141.3-47169.6" + wire $0\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:47056.3-47084.6" + wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46980.3-47008.6" + wire $0\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:47651.3-47679.6" + wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47774.3-47802.6" + wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47689.3-47717.6" + wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47871.3-47899.6" + wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47842.3-47870.6" + wire $0\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" + wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:47434.3-47462.6" + wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:44480.3-44508.6" + wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:44306.3-44334.6" + wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:44509.3-44537.6" + wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:44100.3-44128.6" + wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:44248.3-44276.6" + wire $0\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:44335.3-44363.6" + wire $0\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:44422.3-44450.6" + wire $0\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:44451.3-44479.6" + wire $0\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $0\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $0\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:44393.3-44421.6" + wire $0\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $0\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $0\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:44364.3-44392.6" + wire $0\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:44277.3-44305.6" + wire $0\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:43810.3-43838.6" + wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:48483.3-48511.6" + wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:43839.3-43867.6" + wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:48277.3-48305.6" + wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:48425.3-48453.6" + wire $0\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:48512.3-48540.6" + wire $0\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:43752.3-43780.6" + wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43781.3-43809.6" + wire $0\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:43723.3-43751.6" + wire $0\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:48541.3-48569.6" + wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:48454.3-48482.6" + wire $0\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44831.3-44859.6" + wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44596.3-44624.6" + wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44773.3-44801.6" + wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44802.3-44830.6" + wire $0\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44744.3-44772.6" + wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:45124.3-45152.6" + wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:45182.3-45210.6" + wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:45298.3-45326.6" + wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44918.3-44946.6" + wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:45095.3-45123.6" + wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:45240.3-45268.6" + wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:45269.3-45297.6" + wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:45153.3-45181.6" + wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:45211.3-45239.6" + wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:45066.3-45094.6" + wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" + wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43926.3-43954.6" + wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:44013.3-44041.6" + wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:48074.3-48102.6" + wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" + wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47958.3-47986.6" + wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:48103.3-48131.6" + wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:48190.3-48218.6" + wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:48045.3-48073.6" + wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:48161.3-48189.6" + wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:48132.3-48160.6" + wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45649.3-45677.6" + wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45620.3-45648.6" + wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45736.3-45764.6" + wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:45385.3-45413.6" + wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45562.3-45590.6" + wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45591.3-45619.6" + wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45707.3-45735.6" + wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45678.3-45706.6" + wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:45473.3-45501.6" + wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45851.3-45860.6" + wire width 64 $0\fus_src1_i$42[63:0]$2481 + attribute \src "libresoc.v:45870.3-45879.6" + wire width 64 $0\fus_src1_i$45[63:0]$2487 + attribute \src "libresoc.v:45889.3-45898.6" + wire width 64 $0\fus_src1_i$48[63:0]$2493 + attribute \src "libresoc.v:45908.3-45917.6" + wire width 64 $0\fus_src1_i$51[63:0]$2499 + attribute \src "libresoc.v:45927.3-45936.6" + wire width 64 $0\fus_src1_i$54[63:0]$2505 + attribute \src "libresoc.v:45946.3-45955.6" + wire width 64 $0\fus_src1_i$57[63:0]$2511 + attribute \src "libresoc.v:45965.3-45974.6" + wire width 64 $0\fus_src1_i$60[63:0]$2517 + attribute \src "libresoc.v:45984.3-45993.6" + wire width 64 $0\fus_src1_i$63[63:0]$2523 + attribute \src "libresoc.v:46617.3-46626.6" + wire width 64 $0\fus_src1_i$86[63:0]$2681 + attribute \src "libresoc.v:45832.3-45841.6" + wire width 64 $0\fus_src1_i[63:0] + attribute \src "libresoc.v:46022.3-46031.6" + wire width 64 $0\fus_src2_i$64[63:0]$2533 + attribute \src "libresoc.v:46041.3-46050.6" + wire width 64 $0\fus_src2_i$65[63:0]$2539 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $0\fus_src2_i$66[63:0]$2545 + attribute \src "libresoc.v:46079.3-46088.6" + wire width 64 $0\fus_src2_i$67[63:0]$2551 + attribute \src "libresoc.v:46098.3-46107.6" + wire width 64 $0\fus_src2_i$68[63:0]$2557 + attribute \src "libresoc.v:46117.3-46126.6" + wire width 64 $0\fus_src2_i$69[63:0]$2563 + attribute \src "libresoc.v:46136.3-46145.6" + wire width 64 $0\fus_src2_i$70[63:0]$2569 + attribute \src "libresoc.v:46732.3-46741.6" + wire width 64 $0\fus_src2_i$89[63:0]$2701 + attribute \src "libresoc.v:46800.3-46809.6" + wire width 64 $0\fus_src2_i$91[63:0]$2714 + attribute \src "libresoc.v:46003.3-46012.6" + wire width 64 $0\fus_src2_i[63:0] + attribute \src "libresoc.v:46174.3-46183.6" + wire width 64 $0\fus_src3_i$71[63:0]$2579 + attribute \src "libresoc.v:46193.3-46202.6" + wire $0\fus_src3_i$72[0:0]$2585 + attribute \src "libresoc.v:46212.3-46221.6" + wire $0\fus_src3_i$73[0:0]$2591 + attribute \src "libresoc.v:46250.3-46259.6" + wire $0\fus_src3_i$74[0:0]$2601 + attribute \src "libresoc.v:46269.3-46278.6" + wire $0\fus_src3_i$75[0:0]$2607 + attribute \src "libresoc.v:46383.3-46392.6" + wire width 32 $0\fus_src3_i$79[31:0]$2639 + attribute \src "libresoc.v:46421.3-46430.6" + wire width 4 $0\fus_src3_i$83[3:0]$2651 + attribute \src "libresoc.v:46636.3-46645.6" + wire width 64 $0\fus_src3_i$87[63:0]$2687 + attribute \src "libresoc.v:46684.3-46693.6" + wire width 64 $0\fus_src3_i$88[63:0]$2694 + attribute \src "libresoc.v:46155.3-46164.6" + wire width 64 $0\fus_src3_i[63:0] + attribute \src "libresoc.v:46288.3-46297.6" + wire $0\fus_src4_i$76[0:0]$2613 + attribute \src "libresoc.v:46307.3-46316.6" + wire width 2 $0\fus_src4_i$77[1:0]$2619 + attribute \src "libresoc.v:46402.3-46411.6" + wire width 4 $0\fus_src4_i$80[3:0]$2645 + attribute \src "libresoc.v:46751.3-46760.6" + wire width 64 $0\fus_src4_i$90[63:0]$2707 + attribute \src "libresoc.v:46231.3-46240.6" + wire $0\fus_src4_i[0:0] + attribute \src "libresoc.v:46364.3-46373.6" + wire width 2 $0\fus_src5_i$78[1:0]$2633 + attribute \src "libresoc.v:46467.3-46476.6" + wire width 4 $0\fus_src5_i$84[3:0]$2663 + attribute \src "libresoc.v:46345.3-46354.6" + wire width 2 $0\fus_src5_i[1:0] + attribute \src "libresoc.v:46577.3-46586.6" + wire width 4 $0\fus_src6_i$85[3:0]$2670 + attribute \src "libresoc.v:46326.3-46335.6" + wire width 2 $0\fus_src6_i[1:0] + attribute \src "libresoc.v:36214.7-36214.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46858.3-46866.6" + wire $0\wr_pick_dly$1010$next[0:0]$2724 + attribute \src "libresoc.v:42896.3-42897.51" + wire $0\wr_pick_dly$1010[0:0]$2307 + attribute \src "libresoc.v:41726.7-41726.32" + wire $0\wr_pick_dly$1010[0:0]$2945 + attribute \src "libresoc.v:46867.3-46875.6" + wire $0\wr_pick_dly$1031$next[0:0]$2727 + attribute \src "libresoc.v:42894.3-42895.51" + wire $0\wr_pick_dly$1031[0:0]$2305 + attribute \src "libresoc.v:41730.7-41730.32" + wire $0\wr_pick_dly$1031[0:0]$2947 + attribute \src "libresoc.v:46906.3-46914.6" + wire $0\wr_pick_dly$1049$next[0:0]$2731 + attribute \src "libresoc.v:42892.3-42893.51" + wire $0\wr_pick_dly$1049[0:0]$2303 + attribute \src "libresoc.v:41734.7-41734.32" + wire $0\wr_pick_dly$1049[0:0]$2949 + attribute \src "libresoc.v:46915.3-46923.6" + wire $0\wr_pick_dly$1071$next[0:0]$2734 + attribute \src "libresoc.v:42890.3-42891.51" + wire $0\wr_pick_dly$1071[0:0]$2301 + attribute \src "libresoc.v:41738.7-41738.32" + wire $0\wr_pick_dly$1071[0:0]$2951 + attribute \src "libresoc.v:46924.3-46932.6" + wire $0\wr_pick_dly$1091$next[0:0]$2737 + attribute \src "libresoc.v:42888.3-42889.51" + wire $0\wr_pick_dly$1091[0:0]$2299 + attribute \src "libresoc.v:41742.7-41742.32" + wire $0\wr_pick_dly$1091[0:0]$2953 + attribute \src "libresoc.v:46962.3-46970.6" + wire $0\wr_pick_dly$1111$next[0:0]$2741 + attribute \src "libresoc.v:42886.3-42887.51" + wire $0\wr_pick_dly$1111[0:0]$2297 + attribute \src "libresoc.v:41746.7-41746.32" + wire $0\wr_pick_dly$1111[0:0]$2955 + attribute \src "libresoc.v:46971.3-46979.6" + wire $0\wr_pick_dly$1130$next[0:0]$2744 + attribute \src "libresoc.v:42884.3-42885.51" + wire $0\wr_pick_dly$1130[0:0]$2295 + attribute \src "libresoc.v:41750.7-41750.32" + wire $0\wr_pick_dly$1130[0:0]$2957 + attribute \src "libresoc.v:47009.3-47017.6" + wire $0\wr_pick_dly$1148$next[0:0]$2748 + attribute \src "libresoc.v:42882.3-42883.51" + wire $0\wr_pick_dly$1148[0:0]$2293 + attribute \src "libresoc.v:41754.7-41754.32" + wire $0\wr_pick_dly$1148[0:0]$2959 + attribute \src "libresoc.v:47047.3-47055.6" + wire $0\wr_pick_dly$1222$next[0:0]$2752 + attribute \src "libresoc.v:42880.3-42881.51" + wire $0\wr_pick_dly$1222[0:0]$2291 + attribute \src "libresoc.v:41758.7-41758.32" + wire $0\wr_pick_dly$1222[0:0]$2961 + attribute \src "libresoc.v:47085.3-47093.6" + wire $0\wr_pick_dly$1250$next[0:0]$2756 + attribute \src "libresoc.v:42878.3-42879.51" + wire $0\wr_pick_dly$1250[0:0]$2289 + attribute \src "libresoc.v:41762.7-41762.32" + wire $0\wr_pick_dly$1250[0:0]$2963 + attribute \src "libresoc.v:47123.3-47131.6" + wire $0\wr_pick_dly$1270$next[0:0]$2760 + attribute \src "libresoc.v:42876.3-42877.51" + wire $0\wr_pick_dly$1270[0:0]$2287 + attribute \src "libresoc.v:41766.7-41766.32" + wire $0\wr_pick_dly$1270[0:0]$2965 + attribute \src "libresoc.v:47132.3-47140.6" + wire $0\wr_pick_dly$1290$next[0:0]$2763 + attribute \src "libresoc.v:42874.3-42875.51" + wire $0\wr_pick_dly$1290[0:0]$2285 + attribute \src "libresoc.v:41770.7-41770.32" + wire $0\wr_pick_dly$1290[0:0]$2967 + attribute \src "libresoc.v:47170.3-47178.6" + wire $0\wr_pick_dly$1310$next[0:0]$2767 + attribute \src "libresoc.v:42872.3-42873.51" + wire $0\wr_pick_dly$1310[0:0]$2283 + attribute \src "libresoc.v:41774.7-41774.32" + wire $0\wr_pick_dly$1310[0:0]$2969 + attribute \src "libresoc.v:47179.3-47187.6" + wire $0\wr_pick_dly$1330$next[0:0]$2770 + attribute \src "libresoc.v:42870.3-42871.51" + wire $0\wr_pick_dly$1330[0:0]$2281 + attribute \src "libresoc.v:41778.7-41778.32" + wire $0\wr_pick_dly$1330[0:0]$2971 + attribute \src "libresoc.v:47217.3-47225.6" + wire $0\wr_pick_dly$1350$next[0:0]$2774 + attribute \src "libresoc.v:42868.3-42869.51" + wire $0\wr_pick_dly$1350[0:0]$2279 + attribute \src "libresoc.v:41782.7-41782.32" + wire $0\wr_pick_dly$1350[0:0]$2973 + attribute \src "libresoc.v:47255.3-47263.6" + wire $0\wr_pick_dly$1397$next[0:0]$2778 + attribute \src "libresoc.v:42866.3-42867.51" + wire $0\wr_pick_dly$1397[0:0]$2277 + attribute \src "libresoc.v:41786.7-41786.32" + wire $0\wr_pick_dly$1397[0:0]$2975 + attribute \src "libresoc.v:47264.3-47272.6" + wire $0\wr_pick_dly$1413$next[0:0]$2781 + attribute \src "libresoc.v:42864.3-42865.51" + wire $0\wr_pick_dly$1413[0:0]$2275 + attribute \src "libresoc.v:41790.7-41790.32" + wire $0\wr_pick_dly$1413[0:0]$2977 + attribute \src "libresoc.v:47302.3-47310.6" + wire $0\wr_pick_dly$1429$next[0:0]$2785 + attribute \src "libresoc.v:42862.3-42863.51" + wire $0\wr_pick_dly$1429[0:0]$2273 + attribute \src "libresoc.v:41794.7-41794.32" + wire $0\wr_pick_dly$1429[0:0]$2979 + attribute \src "libresoc.v:47340.3-47348.6" + wire $0\wr_pick_dly$1463$next[0:0]$2789 + attribute \src "libresoc.v:42860.3-42861.51" + wire $0\wr_pick_dly$1463[0:0]$2271 + attribute \src "libresoc.v:41798.7-41798.32" + wire $0\wr_pick_dly$1463[0:0]$2981 + attribute \src "libresoc.v:47378.3-47386.6" + wire $0\wr_pick_dly$1479$next[0:0]$2793 + attribute \src "libresoc.v:42858.3-42859.51" + wire $0\wr_pick_dly$1479[0:0]$2269 + attribute \src "libresoc.v:41802.7-41802.32" + wire $0\wr_pick_dly$1479[0:0]$2983 + attribute \src "libresoc.v:47387.3-47395.6" + wire $0\wr_pick_dly$1495$next[0:0]$2796 + attribute \src "libresoc.v:42856.3-42857.51" + wire $0\wr_pick_dly$1495[0:0]$2267 + attribute \src "libresoc.v:41806.7-41806.32" + wire $0\wr_pick_dly$1495[0:0]$2985 + attribute \src "libresoc.v:47425.3-47433.6" + wire $0\wr_pick_dly$1511$next[0:0]$2800 + attribute \src "libresoc.v:42854.3-42855.51" + wire $0\wr_pick_dly$1511[0:0]$2265 + attribute \src "libresoc.v:41810.7-41810.32" + wire $0\wr_pick_dly$1511[0:0]$2987 + attribute \src "libresoc.v:47463.3-47471.6" + wire $0\wr_pick_dly$1547$next[0:0]$2804 + attribute \src "libresoc.v:42852.3-42853.51" + wire $0\wr_pick_dly$1547[0:0]$2263 + attribute \src "libresoc.v:41814.7-41814.32" + wire $0\wr_pick_dly$1547[0:0]$2989 + attribute \src "libresoc.v:47472.3-47480.6" + wire $0\wr_pick_dly$1563$next[0:0]$2807 + attribute \src "libresoc.v:42850.3-42851.51" + wire $0\wr_pick_dly$1563[0:0]$2261 + attribute \src "libresoc.v:41818.7-41818.32" + wire $0\wr_pick_dly$1563[0:0]$2991 + attribute \src "libresoc.v:47510.3-47518.6" + wire $0\wr_pick_dly$1579$next[0:0]$2811 + attribute \src "libresoc.v:42848.3-42849.51" + wire $0\wr_pick_dly$1579[0:0]$2259 + attribute \src "libresoc.v:41822.7-41822.32" + wire $0\wr_pick_dly$1579[0:0]$2993 + attribute \src "libresoc.v:47519.3-47527.6" + wire $0\wr_pick_dly$1595$next[0:0]$2814 + attribute \src "libresoc.v:42846.3-42847.51" + wire $0\wr_pick_dly$1595[0:0]$2257 + attribute \src "libresoc.v:41826.7-41826.32" + wire $0\wr_pick_dly$1595[0:0]$2995 + attribute \src "libresoc.v:47557.3-47565.6" + wire $0\wr_pick_dly$1637$next[0:0]$2818 + attribute \src "libresoc.v:42844.3-42845.51" + wire $0\wr_pick_dly$1637[0:0]$2255 + attribute \src "libresoc.v:41830.7-41830.32" + wire $0\wr_pick_dly$1637[0:0]$2997 + attribute \src "libresoc.v:47595.3-47603.6" + wire $0\wr_pick_dly$1656$next[0:0]$2826 + attribute \src "libresoc.v:42842.3-42843.51" + wire $0\wr_pick_dly$1656[0:0]$2253 + attribute \src "libresoc.v:41834.7-41834.32" + wire $0\wr_pick_dly$1656[0:0]$2999 + attribute \src "libresoc.v:47633.3-47641.6" + wire $0\wr_pick_dly$1672$next[0:0]$2834 + attribute \src "libresoc.v:42840.3-42841.51" + wire $0\wr_pick_dly$1672[0:0]$2251 + attribute \src "libresoc.v:41838.7-41838.32" + wire $0\wr_pick_dly$1672[0:0]$3001 + attribute \src "libresoc.v:47642.3-47650.6" + wire $0\wr_pick_dly$1688$next[0:0]$2837 + attribute \src "libresoc.v:42838.3-42839.51" + wire $0\wr_pick_dly$1688[0:0]$2249 + attribute \src "libresoc.v:41842.7-41842.32" + wire $0\wr_pick_dly$1688[0:0]$3003 + attribute \src "libresoc.v:47680.3-47688.6" + wire $0\wr_pick_dly$1704$next[0:0]$2841 + attribute \src "libresoc.v:42836.3-42837.51" + wire $0\wr_pick_dly$1704[0:0]$2247 + attribute \src "libresoc.v:41846.7-41846.32" + wire $0\wr_pick_dly$1704[0:0]$3005 + attribute \src "libresoc.v:47718.3-47726.6" + wire $0\wr_pick_dly$1748$next[0:0]$2845 + attribute \src "libresoc.v:42834.3-42835.51" + wire $0\wr_pick_dly$1748[0:0]$2245 + attribute \src "libresoc.v:41850.7-41850.32" + wire $0\wr_pick_dly$1748[0:0]$3007 + attribute \src "libresoc.v:47727.3-47735.6" + wire $0\wr_pick_dly$1764$next[0:0]$2848 + attribute \src "libresoc.v:42832.3-42833.51" + wire $0\wr_pick_dly$1764[0:0]$2243 + attribute \src "libresoc.v:41854.7-41854.32" + wire $0\wr_pick_dly$1764[0:0]$3009 + attribute \src "libresoc.v:47765.3-47773.6" + wire $0\wr_pick_dly$1788$next[0:0]$2852 + attribute \src "libresoc.v:42830.3-42831.51" + wire $0\wr_pick_dly$1788[0:0]$2241 + attribute \src "libresoc.v:41858.7-41858.32" + wire $0\wr_pick_dly$1788[0:0]$3011 + attribute \src "libresoc.v:47803.3-47811.6" + wire $0\wr_pick_dly$1808$next[0:0]$2856 + attribute \src "libresoc.v:42828.3-42829.51" + wire $0\wr_pick_dly$1808[0:0]$2239 + attribute \src "libresoc.v:41862.7-41862.32" + wire $0\wr_pick_dly$1808[0:0]$3013 + attribute \src "libresoc.v:46819.3-46827.6" + wire $0\wr_pick_dly$991$next[0:0]$2720 + attribute \src "libresoc.v:42898.3-42899.49" + wire $0\wr_pick_dly$991[0:0]$2309 + attribute \src "libresoc.v:41866.7-41866.31" + wire $0\wr_pick_dly$991[0:0]$3015 + attribute \src "libresoc.v:46810.3-46818.6" + wire $0\wr_pick_dly$next[0:0]$2717 + attribute \src "libresoc.v:42900.3-42901.39" + wire $0\wr_pick_dly[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $10\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $11\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $12\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $13\corebusy_o[0:0] + attribute \src "libresoc.v:46587.3-46607.6" + wire $1\core_terminate_o$next[0:0]$2674 + attribute \src "libresoc.v:38263.7-38263.30" + wire $1\core_terminate_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $1\corebusy_o[0:0] + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $1\counter$next[1:0]$2655 + attribute \src "libresoc.v:38276.13-38276.27" + wire width 2 $1\counter[1:0] + attribute \src "libresoc.v:46412.3-46420.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 + attribute \src "libresoc.v:39443.7-39443.34" + wire $1\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:46393.3-46401.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 + attribute \src "libresoc.v:39447.7-39447.30" + wire $1\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:46458.3-46466.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:39451.7-39451.30" + wire $1\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:46568.3-46576.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 + attribute \src "libresoc.v:39455.7-39455.30" + wire $1\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:46374.3-46382.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 + attribute \src "libresoc.v:39459.7-39459.33" + wire $1\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:46608.3-46616.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 + attribute \src "libresoc.v:39463.7-39463.37" + wire $1\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:46675.3-46683.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 + attribute \src "libresoc.v:39467.7-39467.34" + wire $1\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:46627.3-46635.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:39471.7-39471.35" + wire $1\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:46723.3-46731.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 + attribute \src "libresoc.v:39475.7-39475.37" + wire $1\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:46742.3-46750.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 + attribute \src "libresoc.v:39479.7-39479.35" + wire $1\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:45823.3-45831.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:39483.7-39483.30" + wire $1\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:45842.3-45850.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:39487.7-39487.29" + wire $1\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:45918.3-45926.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2503 + attribute \src "libresoc.v:39491.7-39491.30" + wire $1\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:45975.3-45983.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2521 + attribute \src "libresoc.v:39495.7-39495.31" + wire $1\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:45880.3-45888.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:39499.7-39499.34" + wire $1\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:45937.3-45945.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2509 + attribute \src "libresoc.v:39503.7-39503.30" + wire $1\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:45956.3-45964.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 + attribute \src "libresoc.v:39507.7-39507.35" + wire $1\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:45899.3-45907.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2497 + attribute \src "libresoc.v:39511.7-39511.30" + wire $1\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:45861.3-45869.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:39515.7-39515.31" + wire $1\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:45994.3-46002.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2527 + attribute \src "libresoc.v:39519.7-39519.30" + wire $1\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:46013.3-46021.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2531 + attribute \src "libresoc.v:39523.7-39523.29" + wire $1\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:46070.3-46078.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2549 + attribute \src "libresoc.v:39527.7-39527.30" + wire $1\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:46127.3-46135.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2567 + attribute \src "libresoc.v:39531.7-39531.31" + wire $1\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:46051.3-46059.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2543 + attribute \src "libresoc.v:39535.7-39535.34" + wire $1\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:46089.3-46097.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2555 + attribute \src "libresoc.v:39539.7-39539.30" + wire $1\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:46108.3-46116.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 + attribute \src "libresoc.v:39543.7-39543.35" + wire $1\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:46032.3-46040.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2537 + attribute \src "libresoc.v:39547.7-39547.31" + wire $1\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:46165.3-46173.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2577 + attribute \src "libresoc.v:39551.7-39551.31" + wire $1\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:46146.3-46154.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 + attribute \src "libresoc.v:39555.7-39555.35" + wire $1\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:46791.3-46799.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 + attribute \src "libresoc.v:39559.7-39559.32" + wire $1\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:46298.3-46306.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 + attribute \src "libresoc.v:39563.7-39563.34" + wire $1\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:46336.3-46344.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 + attribute \src "libresoc.v:39567.7-39567.39" + wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:46317.3-46325.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 + attribute \src "libresoc.v:39571.7-39571.34" + wire $1\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:46355.3-46363.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 + attribute \src "libresoc.v:39575.7-39575.34" + wire $1\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:46184.3-46192.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 + attribute \src "libresoc.v:39579.7-39579.34" + wire $1\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:46241.3-46249.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 + attribute \src "libresoc.v:39583.7-39583.34" + wire $1\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:46203.3-46211.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 + attribute \src "libresoc.v:39587.7-39587.38" + wire $1\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:46260.3-46268.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:39591.7-39591.34" + wire $1\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:46279.3-46287.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:39595.7-39595.39" + wire $1\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:46222.3-46230.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 + attribute \src "libresoc.v:39599.7-39599.34" + wire $1\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:47566.3-47594.6" + wire $1\fus_cu_issue_i$13[0:0]$2822 + attribute \src "libresoc.v:47900.3-47928.6" + wire $1\fus_cu_issue_i$16[0:0]$2863 + attribute \src "libresoc.v:48219.3-48247.6" + wire $1\fus_cu_issue_i$19[0:0]$2882 + attribute \src "libresoc.v:43868.3-43896.6" + wire $1\fus_cu_issue_i$22[0:0]$2360 + attribute \src "libresoc.v:44042.3-44070.6" + wire $1\fus_cu_issue_i$25[0:0]$2374 + attribute \src "libresoc.v:44538.3-44566.6" + wire $1\fus_cu_issue_i$28[0:0]$2399 + attribute \src "libresoc.v:44860.3-44888.6" + wire $1\fus_cu_issue_i$31[0:0]$2418 + attribute \src "libresoc.v:45327.3-45355.6" + wire $1\fus_cu_issue_i$34[0:0]$2442 + attribute \src "libresoc.v:45765.3-45793.6" + wire $1\fus_cu_issue_i$37[0:0]$2465 + attribute \src "libresoc.v:47349.3-47377.6" + wire $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2830 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 + attribute \src "libresoc.v:47396.3-47424.6" + wire width 4 $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:47273.3-47301.6" + wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:47094.3-47122.6" + wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:47311.3-47339.6" + wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:46646.3-46674.6" + wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46933.3-46961.6" + wire $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:47018.3-47046.6" + wire $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:47188.3-47216.6" + wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:47226.3-47254.6" + wire $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:47141.3-47169.6" + wire $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:47056.3-47084.6" + wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46980.3-47008.6" + wire $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:47651.3-47679.6" + wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47774.3-47802.6" + wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47689.3-47717.6" + wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47871.3-47899.6" + wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47842.3-47870.6" + wire $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" + wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:47434.3-47462.6" + wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:44480.3-44508.6" + wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:44306.3-44334.6" + wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:44509.3-44537.6" + wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:44100.3-44128.6" + wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:44248.3-44276.6" + wire $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:44335.3-44363.6" + wire $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:44422.3-44450.6" + wire $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:44451.3-44479.6" + wire $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $1\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:44393.3-44421.6" + wire $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $1\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:44364.3-44392.6" + wire $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:44277.3-44305.6" + wire $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:43810.3-43838.6" + wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:48483.3-48511.6" + wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:43839.3-43867.6" + wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:48277.3-48305.6" + wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:48425.3-48453.6" + wire $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:48512.3-48540.6" + wire $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:43752.3-43780.6" + wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43781.3-43809.6" + wire $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:43723.3-43751.6" + wire $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:48541.3-48569.6" + wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:48454.3-48482.6" + wire $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44831.3-44859.6" + wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44596.3-44624.6" + wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44773.3-44801.6" + wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44802.3-44830.6" + wire $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44744.3-44772.6" + wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:45124.3-45152.6" + wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:45182.3-45210.6" + wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:45298.3-45326.6" + wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44918.3-44946.6" + wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:45095.3-45123.6" + wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:45240.3-45268.6" + wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:45269.3-45297.6" + wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:45153.3-45181.6" + wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:45211.3-45239.6" + wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:45066.3-45094.6" + wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" + wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43926.3-43954.6" + wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:44013.3-44041.6" + wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:48074.3-48102.6" + wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" + wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47958.3-47986.6" + wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:48103.3-48131.6" + wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:48190.3-48218.6" + wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:48045.3-48073.6" + wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:48161.3-48189.6" + wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:48132.3-48160.6" + wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45649.3-45677.6" + wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45620.3-45648.6" + wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45736.3-45764.6" + wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:45385.3-45413.6" + wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45562.3-45590.6" + wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45591.3-45619.6" + wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45707.3-45735.6" + wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45678.3-45706.6" + wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:45473.3-45501.6" + wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45851.3-45860.6" + wire width 64 $1\fus_src1_i$42[63:0]$2482 + attribute \src "libresoc.v:45870.3-45879.6" + wire width 64 $1\fus_src1_i$45[63:0]$2488 + attribute \src "libresoc.v:45889.3-45898.6" + wire width 64 $1\fus_src1_i$48[63:0]$2494 + attribute \src "libresoc.v:45908.3-45917.6" + wire width 64 $1\fus_src1_i$51[63:0]$2500 + attribute \src "libresoc.v:45927.3-45936.6" + wire width 64 $1\fus_src1_i$54[63:0]$2506 + attribute \src "libresoc.v:45946.3-45955.6" + wire width 64 $1\fus_src1_i$57[63:0]$2512 + attribute \src "libresoc.v:45965.3-45974.6" + wire width 64 $1\fus_src1_i$60[63:0]$2518 + attribute \src "libresoc.v:45984.3-45993.6" + wire width 64 $1\fus_src1_i$63[63:0]$2524 + attribute \src "libresoc.v:46617.3-46626.6" + wire width 64 $1\fus_src1_i$86[63:0]$2682 + attribute \src "libresoc.v:45832.3-45841.6" + wire width 64 $1\fus_src1_i[63:0] + attribute \src "libresoc.v:46022.3-46031.6" + wire width 64 $1\fus_src2_i$64[63:0]$2534 + attribute \src "libresoc.v:46041.3-46050.6" + wire width 64 $1\fus_src2_i$65[63:0]$2540 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $1\fus_src2_i$66[63:0]$2546 + attribute \src "libresoc.v:46079.3-46088.6" + wire width 64 $1\fus_src2_i$67[63:0]$2552 + attribute \src "libresoc.v:46098.3-46107.6" + wire width 64 $1\fus_src2_i$68[63:0]$2558 + attribute \src "libresoc.v:46117.3-46126.6" + wire width 64 $1\fus_src2_i$69[63:0]$2564 + attribute \src "libresoc.v:46136.3-46145.6" + wire width 64 $1\fus_src2_i$70[63:0]$2570 + attribute \src "libresoc.v:46732.3-46741.6" + wire width 64 $1\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:46800.3-46809.6" + wire width 64 $1\fus_src2_i$91[63:0]$2715 + attribute \src "libresoc.v:46003.3-46012.6" + wire width 64 $1\fus_src2_i[63:0] + attribute \src "libresoc.v:46174.3-46183.6" + wire width 64 $1\fus_src3_i$71[63:0]$2580 + attribute \src "libresoc.v:46193.3-46202.6" + wire $1\fus_src3_i$72[0:0]$2586 + attribute \src "libresoc.v:46212.3-46221.6" + wire $1\fus_src3_i$73[0:0]$2592 + attribute \src "libresoc.v:46250.3-46259.6" + wire $1\fus_src3_i$74[0:0]$2602 + attribute \src "libresoc.v:46269.3-46278.6" + wire $1\fus_src3_i$75[0:0]$2608 + attribute \src "libresoc.v:46383.3-46392.6" + wire width 32 $1\fus_src3_i$79[31:0]$2640 + attribute \src "libresoc.v:46421.3-46430.6" + wire width 4 $1\fus_src3_i$83[3:0]$2652 + attribute \src "libresoc.v:46636.3-46645.6" + wire width 64 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46684.3-46693.6" + wire width 64 $1\fus_src3_i$88[63:0]$2695 + attribute \src "libresoc.v:46155.3-46164.6" + wire width 64 $1\fus_src3_i[63:0] + attribute \src "libresoc.v:46288.3-46297.6" + wire $1\fus_src4_i$76[0:0]$2614 + attribute \src "libresoc.v:46307.3-46316.6" + wire width 2 $1\fus_src4_i$77[1:0]$2620 + attribute \src "libresoc.v:46402.3-46411.6" + wire width 4 $1\fus_src4_i$80[3:0]$2646 + attribute \src "libresoc.v:46751.3-46760.6" + wire width 64 $1\fus_src4_i$90[63:0]$2708 + attribute \src "libresoc.v:46231.3-46240.6" + wire $1\fus_src4_i[0:0] + attribute \src "libresoc.v:46364.3-46373.6" + wire width 2 $1\fus_src5_i$78[1:0]$2634 + attribute \src "libresoc.v:46467.3-46476.6" + wire width 4 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46345.3-46354.6" + wire width 2 $1\fus_src5_i[1:0] + attribute \src "libresoc.v:46577.3-46586.6" + wire width 4 $1\fus_src6_i$85[3:0]$2671 + attribute \src "libresoc.v:46326.3-46335.6" + wire width 2 $1\fus_src6_i[1:0] + attribute \src "libresoc.v:46858.3-46866.6" + wire $1\wr_pick_dly$1010$next[0:0]$2725 + attribute \src "libresoc.v:46867.3-46875.6" + wire $1\wr_pick_dly$1031$next[0:0]$2728 + attribute \src "libresoc.v:46906.3-46914.6" + wire $1\wr_pick_dly$1049$next[0:0]$2732 + attribute \src "libresoc.v:46915.3-46923.6" + wire $1\wr_pick_dly$1071$next[0:0]$2735 + attribute \src "libresoc.v:46924.3-46932.6" + wire $1\wr_pick_dly$1091$next[0:0]$2738 + attribute \src "libresoc.v:46962.3-46970.6" + wire $1\wr_pick_dly$1111$next[0:0]$2742 + attribute \src "libresoc.v:46971.3-46979.6" + wire $1\wr_pick_dly$1130$next[0:0]$2745 + attribute \src "libresoc.v:47009.3-47017.6" + wire $1\wr_pick_dly$1148$next[0:0]$2749 + attribute \src "libresoc.v:47047.3-47055.6" + wire $1\wr_pick_dly$1222$next[0:0]$2753 + attribute \src "libresoc.v:47085.3-47093.6" + wire $1\wr_pick_dly$1250$next[0:0]$2757 + attribute \src "libresoc.v:47123.3-47131.6" + wire $1\wr_pick_dly$1270$next[0:0]$2761 + attribute \src "libresoc.v:47132.3-47140.6" + wire $1\wr_pick_dly$1290$next[0:0]$2764 + attribute \src "libresoc.v:47170.3-47178.6" + wire $1\wr_pick_dly$1310$next[0:0]$2768 + attribute \src "libresoc.v:47179.3-47187.6" + wire $1\wr_pick_dly$1330$next[0:0]$2771 + attribute \src "libresoc.v:47217.3-47225.6" + wire $1\wr_pick_dly$1350$next[0:0]$2775 + attribute \src "libresoc.v:47255.3-47263.6" + wire $1\wr_pick_dly$1397$next[0:0]$2779 + attribute \src "libresoc.v:47264.3-47272.6" + wire $1\wr_pick_dly$1413$next[0:0]$2782 + attribute \src "libresoc.v:47302.3-47310.6" + wire $1\wr_pick_dly$1429$next[0:0]$2786 + attribute \src "libresoc.v:47340.3-47348.6" + wire $1\wr_pick_dly$1463$next[0:0]$2790 + attribute \src "libresoc.v:47378.3-47386.6" + wire $1\wr_pick_dly$1479$next[0:0]$2794 + attribute \src "libresoc.v:47387.3-47395.6" + wire $1\wr_pick_dly$1495$next[0:0]$2797 + attribute \src "libresoc.v:47425.3-47433.6" + wire $1\wr_pick_dly$1511$next[0:0]$2801 + attribute \src "libresoc.v:47463.3-47471.6" + wire $1\wr_pick_dly$1547$next[0:0]$2805 + attribute \src "libresoc.v:47472.3-47480.6" + wire $1\wr_pick_dly$1563$next[0:0]$2808 + attribute \src "libresoc.v:47510.3-47518.6" + wire $1\wr_pick_dly$1579$next[0:0]$2812 + attribute \src "libresoc.v:47519.3-47527.6" + wire $1\wr_pick_dly$1595$next[0:0]$2815 + attribute \src "libresoc.v:47557.3-47565.6" + wire $1\wr_pick_dly$1637$next[0:0]$2819 + attribute \src "libresoc.v:47595.3-47603.6" + wire $1\wr_pick_dly$1656$next[0:0]$2827 + attribute \src "libresoc.v:47633.3-47641.6" + wire $1\wr_pick_dly$1672$next[0:0]$2835 + attribute \src "libresoc.v:47642.3-47650.6" + wire $1\wr_pick_dly$1688$next[0:0]$2838 + attribute \src "libresoc.v:47680.3-47688.6" + wire $1\wr_pick_dly$1704$next[0:0]$2842 + attribute \src "libresoc.v:47718.3-47726.6" + wire $1\wr_pick_dly$1748$next[0:0]$2846 + attribute \src "libresoc.v:47727.3-47735.6" + wire $1\wr_pick_dly$1764$next[0:0]$2849 + attribute \src "libresoc.v:47765.3-47773.6" + wire $1\wr_pick_dly$1788$next[0:0]$2853 + attribute \src "libresoc.v:47803.3-47811.6" + wire $1\wr_pick_dly$1808$next[0:0]$2857 + attribute \src "libresoc.v:46819.3-46827.6" + wire $1\wr_pick_dly$991$next[0:0]$2721 + attribute \src "libresoc.v:46810.3-46818.6" + wire $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:41724.7-41724.25" + wire $1\wr_pick_dly[0:0] + attribute \src "libresoc.v:46587.3-46607.6" + wire $2\core_terminate_o$next[0:0]$2675 + attribute \src "libresoc.v:46477.3-46567.6" + wire $2\corebusy_o[0:0] + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $2\counter$next[1:0]$2656 + attribute \src "libresoc.v:47566.3-47594.6" + wire $2\fus_cu_issue_i$13[0:0]$2823 + attribute \src "libresoc.v:47900.3-47928.6" + wire $2\fus_cu_issue_i$16[0:0]$2864 + attribute \src "libresoc.v:48219.3-48247.6" + wire $2\fus_cu_issue_i$19[0:0]$2883 + attribute \src "libresoc.v:43868.3-43896.6" + wire $2\fus_cu_issue_i$22[0:0]$2361 + attribute \src "libresoc.v:44042.3-44070.6" + wire $2\fus_cu_issue_i$25[0:0]$2375 + attribute \src "libresoc.v:44538.3-44566.6" + wire $2\fus_cu_issue_i$28[0:0]$2400 + attribute \src "libresoc.v:44860.3-44888.6" + wire $2\fus_cu_issue_i$31[0:0]$2419 + attribute \src "libresoc.v:45327.3-45355.6" + wire $2\fus_cu_issue_i$34[0:0]$2443 + attribute \src "libresoc.v:45765.3-45793.6" + wire $2\fus_cu_issue_i$37[0:0]$2466 + attribute \src "libresoc.v:47349.3-47377.6" + wire $2\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2831 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 + attribute \src "libresoc.v:47396.3-47424.6" + wire width 4 $2\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:47273.3-47301.6" + wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:47094.3-47122.6" + wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:47311.3-47339.6" + wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:46646.3-46674.6" + wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46933.3-46961.6" + wire $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:47018.3-47046.6" + wire $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:47188.3-47216.6" + wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:47226.3-47254.6" + wire $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:47141.3-47169.6" + wire $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:47056.3-47084.6" + wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46980.3-47008.6" + wire $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:47651.3-47679.6" + wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47774.3-47802.6" + wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47689.3-47717.6" + wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47871.3-47899.6" + wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47842.3-47870.6" + wire $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" + wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:47434.3-47462.6" + wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:44480.3-44508.6" + wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:44306.3-44334.6" + wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:44509.3-44537.6" + wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:44100.3-44128.6" + wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:44248.3-44276.6" + wire $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:44335.3-44363.6" + wire $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:44422.3-44450.6" + wire $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:44451.3-44479.6" + wire $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $2\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:44393.3-44421.6" + wire $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $2\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:44364.3-44392.6" + wire $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:44277.3-44305.6" + wire $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:43810.3-43838.6" + wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:48483.3-48511.6" + wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:43839.3-43867.6" + wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:48277.3-48305.6" + wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:48425.3-48453.6" + wire $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:48512.3-48540.6" + wire $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:43752.3-43780.6" + wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43781.3-43809.6" + wire $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:43723.3-43751.6" + wire $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:48541.3-48569.6" + wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:48454.3-48482.6" + wire $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44831.3-44859.6" + wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44596.3-44624.6" + wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44773.3-44801.6" + wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44802.3-44830.6" + wire $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44744.3-44772.6" + wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:45124.3-45152.6" + wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:45182.3-45210.6" + wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:45298.3-45326.6" + wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44918.3-44946.6" + wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:45095.3-45123.6" + wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:45240.3-45268.6" + wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:45269.3-45297.6" + wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:45153.3-45181.6" + wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:45211.3-45239.6" + wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:45066.3-45094.6" + wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" + wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43926.3-43954.6" + wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:44013.3-44041.6" + wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:48074.3-48102.6" + wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" + wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47958.3-47986.6" + wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:48103.3-48131.6" + wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:48190.3-48218.6" + wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:48045.3-48073.6" + wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:48161.3-48189.6" + wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:48132.3-48160.6" + wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45649.3-45677.6" + wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45620.3-45648.6" + wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45736.3-45764.6" + wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:45385.3-45413.6" + wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45562.3-45590.6" + wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45591.3-45619.6" + wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45707.3-45735.6" + wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45678.3-45706.6" + wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:45473.3-45501.6" + wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:46587.3-46607.6" + wire $3\core_terminate_o$next[0:0]$2676 + attribute \src "libresoc.v:46477.3-46567.6" + wire $3\corebusy_o[0:0] + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $3\counter$next[1:0]$2657 + attribute \src "libresoc.v:47566.3-47594.6" + wire $3\fus_cu_issue_i$13[0:0]$2824 + attribute \src "libresoc.v:47900.3-47928.6" + wire $3\fus_cu_issue_i$16[0:0]$2865 + attribute \src "libresoc.v:48219.3-48247.6" + wire $3\fus_cu_issue_i$19[0:0]$2884 + attribute \src "libresoc.v:43868.3-43896.6" + wire $3\fus_cu_issue_i$22[0:0]$2362 + attribute \src "libresoc.v:44042.3-44070.6" + wire $3\fus_cu_issue_i$25[0:0]$2376 + attribute \src "libresoc.v:44538.3-44566.6" + wire $3\fus_cu_issue_i$28[0:0]$2401 + attribute \src "libresoc.v:44860.3-44888.6" + wire $3\fus_cu_issue_i$31[0:0]$2420 + attribute \src "libresoc.v:45327.3-45355.6" + wire $3\fus_cu_issue_i$34[0:0]$2444 + attribute \src "libresoc.v:45765.3-45793.6" + wire $3\fus_cu_issue_i$37[0:0]$2467 + attribute \src "libresoc.v:47349.3-47377.6" + wire $3\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2832 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 + attribute \src "libresoc.v:47396.3-47424.6" + wire width 4 $3\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:47273.3-47301.6" + wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:46761.3-46790.6" + wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:47094.3-47122.6" + wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:47311.3-47339.6" + wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:46646.3-46674.6" + wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46933.3-46961.6" + wire $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:47018.3-47046.6" + wire $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:47188.3-47216.6" + wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:47226.3-47254.6" + wire $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46876.3-46905.6" + wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:47141.3-47169.6" + wire $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46828.3-46857.6" + wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:47056.3-47084.6" + wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46980.3-47008.6" + wire $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:47651.3-47679.6" + wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47812.3-47841.6" + wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47774.3-47802.6" + wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47689.3-47717.6" + wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47871.3-47899.6" + wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47842.3-47870.6" + wire $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" + wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:47434.3-47462.6" + wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:44480.3-44508.6" + wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:44158.3-44187.6" + wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:44306.3-44334.6" + wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:44509.3-44537.6" + wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:44100.3-44128.6" + wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:44248.3-44276.6" + wire $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:44335.3-44363.6" + wire $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:44422.3-44450.6" + wire $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:44451.3-44479.6" + wire $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $3\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:44218.3-44247.6" + wire $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:44393.3-44421.6" + wire $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $3\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:44188.3-44217.6" + wire $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:44364.3-44392.6" + wire $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:44277.3-44305.6" + wire $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:43810.3-43838.6" + wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:48335.3-48364.6" + wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:48483.3-48511.6" + wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:43839.3-43867.6" + wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:48277.3-48305.6" + wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:48425.3-48453.6" + wire $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:48512.3-48540.6" + wire $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:43752.3-43780.6" + wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43781.3-43809.6" + wire $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:48395.3-48424.6" + wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:43723.3-43751.6" + wire $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:48365.3-48394.6" + wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:48541.3-48569.6" + wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:48454.3-48482.6" + wire $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44654.3-44683.6" + wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44831.3-44859.6" + wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44596.3-44624.6" + wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44773.3-44801.6" + wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44802.3-44830.6" + wire $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44714.3-44743.6" + wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44684.3-44713.6" + wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44744.3-44772.6" + wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44976.3-45005.6" + wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:45124.3-45152.6" + wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:45182.3-45210.6" + wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:45298.3-45326.6" + wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44918.3-44946.6" + wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:45095.3-45123.6" + wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:45240.3-45268.6" + wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:45269.3-45297.6" + wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:45036.3-45065.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:45153.3-45181.6" + wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:45211.3-45239.6" + wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:45006.3-45035.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:45066.3-45094.6" + wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" + wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43926.3-43954.6" + wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:44013.3-44041.6" + wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:48074.3-48102.6" + wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" + wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47958.3-47986.6" + wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:48103.3-48131.6" + wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:48190.3-48218.6" + wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:48045.3-48073.6" + wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:48161.3-48189.6" + wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:48132.3-48160.6" + wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45649.3-45677.6" + wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45620.3-45648.6" + wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:45443.3-45472.6" + wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45736.3-45764.6" + wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:45385.3-45413.6" + wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45562.3-45590.6" + wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45591.3-45619.6" + wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45707.3-45735.6" + wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:45532.3-45561.6" + wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:45502.3-45531.6" + wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45678.3-45706.6" + wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:45473.3-45501.6" + wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $4\corebusy_o[0:0] + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $4\counter$next[1:0]$2658 + attribute \src "libresoc.v:46477.3-46567.6" + wire $5\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $6\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $7\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $8\corebusy_o[0:0] + attribute \src "libresoc.v:46477.3-46567.6" + wire $9\corebusy_o[0:0] + attribute \src "libresoc.v:42103.20-42103.122" + wire $and$libresoc.v:42103$1506_Y + attribute \src "libresoc.v:42105.20-42105.122" + wire $and$libresoc.v:42105$1508_Y + attribute \src "libresoc.v:42106.20-42106.126" + wire $and$libresoc.v:42106$1509_Y + attribute \src "libresoc.v:42108.20-42108.110" + wire $and$libresoc.v:42108$1511_Y + attribute \src "libresoc.v:42109.20-42109.123" + wire $and$libresoc.v:42109$1512_Y + attribute \src "libresoc.v:42111.20-42111.122" + wire $and$libresoc.v:42111$1514_Y + attribute \src "libresoc.v:42112.20-42112.126" + wire $and$libresoc.v:42112$1515_Y + attribute \src "libresoc.v:42114.20-42114.110" + wire $and$libresoc.v:42114$1517_Y + attribute \src "libresoc.v:42115.20-42115.123" + wire $and$libresoc.v:42115$1518_Y + attribute \src "libresoc.v:42117.20-42117.123" + wire $and$libresoc.v:42117$1520_Y + attribute \src "libresoc.v:42118.20-42118.126" + wire $and$libresoc.v:42118$1521_Y + attribute \src "libresoc.v:42120.20-42120.110" + wire $and$libresoc.v:42120$1523_Y + attribute \src "libresoc.v:42121.20-42121.123" + wire $and$libresoc.v:42121$1524_Y + attribute \src "libresoc.v:42123.20-42123.123" + wire $and$libresoc.v:42123$1526_Y + attribute \src "libresoc.v:42124.20-42124.126" + wire $and$libresoc.v:42124$1527_Y + attribute \src "libresoc.v:42126.20-42126.110" + wire $and$libresoc.v:42126$1529_Y + attribute \src "libresoc.v:42127.20-42127.123" + wire $and$libresoc.v:42127$1530_Y + attribute \src "libresoc.v:42129.20-42129.123" + wire $and$libresoc.v:42129$1532_Y + attribute \src "libresoc.v:42130.20-42130.126" + wire $and$libresoc.v:42130$1533_Y + attribute \src "libresoc.v:42132.20-42132.110" + wire $and$libresoc.v:42132$1535_Y + attribute \src "libresoc.v:42133.20-42133.123" + wire $and$libresoc.v:42133$1536_Y + attribute \src "libresoc.v:42135.20-42135.123" + wire $and$libresoc.v:42135$1538_Y + attribute \src "libresoc.v:42136.20-42136.126" + wire $and$libresoc.v:42136$1539_Y + attribute \src "libresoc.v:42138.20-42138.110" + wire $and$libresoc.v:42138$1541_Y + attribute \src "libresoc.v:42139.20-42139.123" + wire $and$libresoc.v:42139$1542_Y + attribute \src "libresoc.v:42141.20-42141.113" + wire $and$libresoc.v:42141$1544_Y + attribute \src "libresoc.v:42142.20-42142.126" + wire $and$libresoc.v:42142$1545_Y + attribute \src "libresoc.v:42144.20-42144.110" + wire $and$libresoc.v:42144$1547_Y + attribute \src "libresoc.v:42145.20-42145.123" + wire $and$libresoc.v:42145$1548_Y + attribute \src "libresoc.v:42147.20-42147.114" + wire $and$libresoc.v:42147$1550_Y + attribute \src "libresoc.v:42148.20-42148.126" + wire $and$libresoc.v:42148$1551_Y + attribute \src "libresoc.v:42150.20-42150.110" + wire $and$libresoc.v:42150$1553_Y + attribute \src "libresoc.v:42151.20-42151.123" + wire $and$libresoc.v:42151$1554_Y + attribute \src "libresoc.v:42180.20-42180.123" + wire $and$libresoc.v:42180$1583_Y + attribute \src "libresoc.v:42181.20-42181.128" + wire $and$libresoc.v:42181$1584_Y + attribute \src "libresoc.v:42182.20-42182.133" + wire $and$libresoc.v:42182$1585_Y + attribute \src "libresoc.v:42184.20-42184.110" + wire $and$libresoc.v:42184$1587_Y + attribute \src "libresoc.v:42185.20-42185.128" + wire $and$libresoc.v:42185$1588_Y + attribute \src "libresoc.v:42187.20-42187.116" + wire $and$libresoc.v:42187$1590_Y + attribute \src "libresoc.v:42188.20-42188.123" + wire $and$libresoc.v:42188$1591_Y + attribute \src "libresoc.v:42189.20-42189.128" + wire $and$libresoc.v:42189$1592_Y + attribute \src "libresoc.v:42190.20-42190.128" + wire $and$libresoc.v:42190$1593_Y + attribute \src "libresoc.v:42191.20-42191.129" + wire $and$libresoc.v:42191$1594_Y + attribute \src "libresoc.v:42192.20-42192.129" + wire $and$libresoc.v:42192$1595_Y + attribute \src "libresoc.v:42193.20-42193.129" + wire $and$libresoc.v:42193$1596_Y + attribute \src "libresoc.v:42194.20-42194.130" + wire $and$libresoc.v:42194$1597_Y + attribute \src "libresoc.v:42196.20-42196.110" + wire $and$libresoc.v:42196$1599_Y + attribute \src "libresoc.v:42197.20-42197.125" + wire $and$libresoc.v:42197$1600_Y + attribute \src "libresoc.v:42201.20-42201.126" + wire $and$libresoc.v:42201$1604_Y + attribute \src "libresoc.v:42202.20-42202.130" + wire $and$libresoc.v:42202$1605_Y + attribute \src "libresoc.v:42204.20-42204.110" + wire $and$libresoc.v:42204$1607_Y + attribute \src "libresoc.v:42205.20-42205.125" + wire $and$libresoc.v:42205$1608_Y + attribute \src "libresoc.v:42209.20-42209.126" + wire $and$libresoc.v:42209$1612_Y + attribute \src "libresoc.v:42210.20-42210.130" + wire $and$libresoc.v:42210$1613_Y + attribute \src "libresoc.v:42212.20-42212.110" + wire $and$libresoc.v:42212$1615_Y + attribute \src "libresoc.v:42213.20-42213.125" + wire $and$libresoc.v:42213$1616_Y + attribute \src "libresoc.v:42217.20-42217.126" + wire $and$libresoc.v:42217$1620_Y + attribute \src "libresoc.v:42218.20-42218.130" + wire $and$libresoc.v:42218$1621_Y + attribute \src "libresoc.v:42220.20-42220.110" + wire $and$libresoc.v:42220$1623_Y + attribute \src "libresoc.v:42221.20-42221.125" + wire $and$libresoc.v:42221$1624_Y + attribute \src "libresoc.v:42225.20-42225.126" + wire $and$libresoc.v:42225$1628_Y + attribute \src "libresoc.v:42226.20-42226.130" + wire $and$libresoc.v:42226$1629_Y + attribute \src "libresoc.v:42228.20-42228.110" + wire $and$libresoc.v:42228$1631_Y + attribute \src "libresoc.v:42229.20-42229.125" + wire $and$libresoc.v:42229$1632_Y + attribute \src "libresoc.v:42233.20-42233.126" + wire $and$libresoc.v:42233$1636_Y + attribute \src "libresoc.v:42234.20-42234.130" + wire $and$libresoc.v:42234$1637_Y + attribute \src "libresoc.v:42236.20-42236.110" + wire $and$libresoc.v:42236$1639_Y + attribute \src "libresoc.v:42237.20-42237.125" + wire $and$libresoc.v:42237$1640_Y + attribute \src "libresoc.v:42251.20-42251.118" + wire $and$libresoc.v:42251$1654_Y + attribute \src "libresoc.v:42252.20-42252.123" + wire $and$libresoc.v:42252$1655_Y + attribute \src "libresoc.v:42253.20-42253.129" + wire $and$libresoc.v:42253$1656_Y + attribute \src "libresoc.v:42254.20-42254.129" + wire $and$libresoc.v:42254$1657_Y + attribute \src "libresoc.v:42255.20-42255.136" + wire $and$libresoc.v:42255$1658_Y + attribute \src "libresoc.v:42257.20-42257.110" + wire $and$libresoc.v:42257$1660_Y + attribute \src "libresoc.v:42258.20-42258.128" + wire $and$libresoc.v:42258$1661_Y + attribute \src "libresoc.v:42260.20-42260.128" + wire $and$libresoc.v:42260$1663_Y + attribute \src "libresoc.v:42261.20-42261.136" + wire $and$libresoc.v:42261$1664_Y + attribute \src "libresoc.v:42263.20-42263.110" + wire $and$libresoc.v:42263$1666_Y + attribute \src "libresoc.v:42264.20-42264.128" + wire $and$libresoc.v:42264$1667_Y + attribute \src "libresoc.v:42266.20-42266.128" + wire $and$libresoc.v:42266$1669_Y + attribute \src "libresoc.v:42267.20-42267.136" + wire $and$libresoc.v:42267$1670_Y + attribute \src "libresoc.v:42269.20-42269.110" + wire $and$libresoc.v:42269$1672_Y + attribute \src "libresoc.v:42270.20-42270.128" + wire $and$libresoc.v:42270$1673_Y + attribute \src "libresoc.v:42277.20-42277.118" + wire $and$libresoc.v:42277$1681_Y + attribute \src "libresoc.v:42278.20-42278.123" + wire $and$libresoc.v:42278$1682_Y + attribute \src "libresoc.v:42279.20-42279.129" + wire $and$libresoc.v:42279$1683_Y + attribute \src "libresoc.v:42280.20-42280.129" + wire $and$libresoc.v:42280$1684_Y + attribute \src "libresoc.v:42281.20-42281.129" + wire $and$libresoc.v:42281$1685_Y + attribute \src "libresoc.v:42282.20-42282.136" + wire $and$libresoc.v:42282$1686_Y + attribute \src "libresoc.v:42284.20-42284.110" + wire $and$libresoc.v:42284$1688_Y + attribute \src "libresoc.v:42285.20-42285.128" + wire $and$libresoc.v:42285$1689_Y + attribute \src "libresoc.v:42287.20-42287.128" + wire $and$libresoc.v:42287$1691_Y + attribute \src "libresoc.v:42288.20-42288.136" + wire $and$libresoc.v:42288$1692_Y + attribute \src "libresoc.v:42290.20-42290.110" + wire $and$libresoc.v:42290$1694_Y + attribute \src "libresoc.v:42291.20-42291.128" + wire $and$libresoc.v:42291$1695_Y + attribute \src "libresoc.v:42293.20-42293.128" + wire $and$libresoc.v:42293$1697_Y + attribute \src "libresoc.v:42294.20-42294.136" + wire $and$libresoc.v:42294$1698_Y + attribute \src "libresoc.v:42296.20-42296.110" + wire $and$libresoc.v:42296$1700_Y + attribute \src "libresoc.v:42297.20-42297.128" + wire $and$libresoc.v:42297$1701_Y + attribute \src "libresoc.v:42299.20-42299.128" + wire $and$libresoc.v:42299$1703_Y + attribute \src "libresoc.v:42300.20-42300.136" + wire $and$libresoc.v:42300$1704_Y + attribute \src "libresoc.v:42302.20-42302.110" + wire $and$libresoc.v:42302$1706_Y + attribute \src "libresoc.v:42303.20-42303.128" + wire $and$libresoc.v:42303$1707_Y + attribute \src "libresoc.v:42311.20-42311.118" + wire $and$libresoc.v:42311$1715_Y + attribute \src "libresoc.v:42312.20-42312.123" + wire $and$libresoc.v:42312$1716_Y + attribute \src "libresoc.v:42313.20-42313.129" + wire $and$libresoc.v:42313$1717_Y + attribute \src "libresoc.v:42314.20-42314.129" + wire $and$libresoc.v:42314$1718_Y + attribute \src "libresoc.v:42315.20-42315.129" + wire $and$libresoc.v:42315$1719_Y + attribute \src "libresoc.v:42316.20-42316.136" + wire $and$libresoc.v:42316$1720_Y + attribute \src "libresoc.v:42318.20-42318.110" + wire $and$libresoc.v:42318$1722_Y + attribute \src "libresoc.v:42319.20-42319.128" + wire $and$libresoc.v:42319$1723_Y + attribute \src "libresoc.v:42321.20-42321.128" + wire $and$libresoc.v:42321$1725_Y + attribute \src "libresoc.v:42322.20-42322.136" + wire $and$libresoc.v:42322$1726_Y + attribute \src "libresoc.v:42324.20-42324.110" + wire $and$libresoc.v:42324$1728_Y + attribute \src "libresoc.v:42325.20-42325.128" + wire $and$libresoc.v:42325$1729_Y + attribute \src "libresoc.v:42327.20-42327.128" + wire $and$libresoc.v:42327$1731_Y + attribute \src "libresoc.v:42328.20-42328.136" + wire $and$libresoc.v:42328$1732_Y + attribute \src "libresoc.v:42330.20-42330.110" + wire $and$libresoc.v:42330$1734_Y + attribute \src "libresoc.v:42331.20-42331.128" + wire $and$libresoc.v:42331$1735_Y + attribute \src "libresoc.v:42333.20-42333.128" + wire $and$libresoc.v:42333$1737_Y + attribute \src "libresoc.v:42334.20-42334.136" + wire $and$libresoc.v:42334$1738_Y + attribute \src "libresoc.v:42336.20-42336.110" + wire $and$libresoc.v:42336$1740_Y + attribute \src "libresoc.v:42337.20-42337.128" + wire $and$libresoc.v:42337$1741_Y + attribute \src "libresoc.v:42347.20-42347.121" + wire $and$libresoc.v:42347$1753_Y + attribute \src "libresoc.v:42348.20-42348.129" + wire $and$libresoc.v:42348$1754_Y + attribute \src "libresoc.v:42349.20-42349.128" + wire $and$libresoc.v:42349$1755_Y + attribute \src "libresoc.v:42350.20-42350.129" + wire $and$libresoc.v:42350$1756_Y + attribute \src "libresoc.v:42351.20-42351.129" + wire $and$libresoc.v:42351$1757_Y + attribute \src "libresoc.v:42352.20-42352.128" + wire $and$libresoc.v:42352$1758_Y + attribute \src "libresoc.v:42353.20-42353.136" + wire $and$libresoc.v:42353$1759_Y + attribute \src "libresoc.v:42355.20-42355.110" + wire $and$libresoc.v:42355$1761_Y + attribute \src "libresoc.v:42356.20-42356.128" + wire $and$libresoc.v:42356$1762_Y + attribute \src "libresoc.v:42358.20-42358.127" + wire $and$libresoc.v:42358$1764_Y + attribute \src "libresoc.v:42359.20-42359.136" + wire $and$libresoc.v:42359$1765_Y + attribute \src "libresoc.v:42361.20-42361.110" + wire $and$libresoc.v:42361$1767_Y + attribute \src "libresoc.v:42362.20-42362.128" + wire $and$libresoc.v:42362$1768_Y + attribute \src "libresoc.v:42364.20-42364.127" + wire $and$libresoc.v:42364$1770_Y + attribute \src "libresoc.v:42365.20-42365.136" + wire $and$libresoc.v:42365$1771_Y + attribute \src "libresoc.v:42367.20-42367.110" + wire $and$libresoc.v:42367$1773_Y + attribute \src "libresoc.v:42368.20-42368.128" + wire $and$libresoc.v:42368$1774_Y + attribute \src "libresoc.v:42370.20-42370.121" + wire $and$libresoc.v:42370$1776_Y + attribute \src "libresoc.v:42371.20-42371.136" + wire $and$libresoc.v:42371$1777_Y + attribute \src "libresoc.v:42373.20-42373.110" + wire $and$libresoc.v:42373$1779_Y + attribute \src "libresoc.v:42374.20-42374.128" + wire $and$libresoc.v:42374$1780_Y + attribute \src "libresoc.v:42376.20-42376.127" + wire $and$libresoc.v:42376$1782_Y + attribute \src "libresoc.v:42377.20-42377.136" + wire $and$libresoc.v:42377$1783_Y + attribute \src "libresoc.v:42379.20-42379.110" + wire $and$libresoc.v:42379$1785_Y + attribute \src "libresoc.v:42380.20-42380.128" + wire $and$libresoc.v:42380$1786_Y + attribute \src "libresoc.v:42394.20-42394.119" + wire $and$libresoc.v:42394$1800_Y + attribute \src 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$not$libresoc.v:42329$1733_Y + attribute \src "libresoc.v:42335.20-42335.106" + wire $not$libresoc.v:42335$1739_Y + attribute \src "libresoc.v:42354.20-42354.106" + wire $not$libresoc.v:42354$1760_Y + attribute \src "libresoc.v:42360.20-42360.106" + wire $not$libresoc.v:42360$1766_Y + attribute \src "libresoc.v:42366.20-42366.106" + wire $not$libresoc.v:42366$1772_Y + attribute \src "libresoc.v:42372.20-42372.106" + wire $not$libresoc.v:42372$1778_Y + attribute \src "libresoc.v:42378.20-42378.106" + wire $not$libresoc.v:42378$1784_Y + attribute \src "libresoc.v:42398.20-42398.106" + wire $not$libresoc.v:42398$1804_Y + attribute \src "libresoc.v:42404.20-42404.106" + wire $not$libresoc.v:42404$1810_Y + attribute \src "libresoc.v:42414.20-42414.106" + wire $not$libresoc.v:42414$1821_Y + attribute \src "libresoc.v:42422.20-42422.106" + wire $not$libresoc.v:42422$1830_Y + attribute \src "libresoc.v:42459.19-42459.136" + wire width 4 $not$libresoc.v:42459$1867_Y + attribute \src "libresoc.v:42460.19-42460.192" + wire width 6 $not$libresoc.v:42460$1868_Y + attribute \src "libresoc.v:42461.19-42461.138" + wire width 3 $not$libresoc.v:42461$1869_Y + attribute \src "libresoc.v:42462.19-42462.150" + wire width 4 $not$libresoc.v:42462$1870_Y + attribute \src "libresoc.v:42469.19-42469.128" + wire width 3 $not$libresoc.v:42469$1877_Y + attribute \src "libresoc.v:42484.19-42484.159" + wire width 6 $not$libresoc.v:42484$1892_Y + attribute \src "libresoc.v:42491.19-42491.128" + wire width 3 $not$libresoc.v:42491$1899_Y + attribute \src "libresoc.v:42498.19-42498.128" + wire width 3 $not$libresoc.v:42498$1906_Y + attribute \src "libresoc.v:42509.19-42509.150" + wire width 5 $not$libresoc.v:42509$1917_Y + attribute \src "libresoc.v:42510.19-42510.134" + wire width 3 $not$libresoc.v:42510$1918_Y + attribute \src "libresoc.v:42513.19-42513.106" + wire $not$libresoc.v:42513$1921_Y + attribute \src "libresoc.v:42519.19-42519.105" + wire $not$libresoc.v:42519$1927_Y + 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$not$libresoc.v:42600$2008_Y + attribute \src "libresoc.v:42606.19-42606.106" + wire $not$libresoc.v:42606$2014_Y + attribute \src "libresoc.v:42612.19-42612.111" + wire $not$libresoc.v:42612$2020_Y + attribute \src "libresoc.v:42618.19-42618.107" + wire $not$libresoc.v:42618$2026_Y + attribute \src "libresoc.v:42632.19-42632.111" + wire $not$libresoc.v:42632$2040_Y + attribute \src "libresoc.v:42638.19-42638.107" + wire $not$libresoc.v:42638$2046_Y + attribute \src "libresoc.v:42652.19-42652.110" + wire $not$libresoc.v:42652$2060_Y + attribute \src "libresoc.v:42658.19-42658.114" + wire $not$libresoc.v:42658$2066_Y + attribute \src "libresoc.v:42664.19-42664.110" + wire $not$libresoc.v:42664$2072_Y + attribute \src "libresoc.v:42670.19-42670.110" + wire $not$libresoc.v:42670$2078_Y + attribute \src "libresoc.v:42676.19-42676.110" + wire $not$libresoc.v:42676$2084_Y + attribute \src "libresoc.v:42682.19-42682.115" + wire $not$libresoc.v:42682$2090_Y + attribute \src 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26 \core_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 32 \cr_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 32 \cr_full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 5 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 6 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 12 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 70 \data_i$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 89 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 94 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 88 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 93 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 96 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 90 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 92 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 91 \dbus__stb + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire \dec_LDST_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire \dec_LDST_sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LOGICAL_LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_LOGICAL_LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_LOGICAL_LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LOGICAL_LOGICAL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_LOGICAL_LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire \dec_LOGICAL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire \dec_LOGICAL_sv_a_nz + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_MUL_MUL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_MUL_MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire \dec_MUL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 \dec_MUL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire \dec_SHIFT_ROT_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute 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\dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast1_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast1_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast2_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_FAST_fast2_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_div0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_ldst0_8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_mul0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_shiftrot0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_spr0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_ra_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_div0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_ldst0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_mul0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_shiftrot0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rb_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rc_ldst0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_INT_rc_shiftrot0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_SPR_spr1_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ca_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ca_shiftrot0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ca_spr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_ov_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_div0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_logical0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_mul0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_shiftrot0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \dp_XER_xer_so_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_ldst0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_logical0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_shiftrot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire \en_trap0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \fast_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \fast_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \fast_dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \fast_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \fast_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \fast_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \fast_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \fast_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \fast_src2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 10 \fu_enable + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 32 output 78 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 input 77 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 6 output 80 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 79 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute 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"OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \fus_oper_i_alu_trap0__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \fus_oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__rc__rc + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1136 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1638 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1643 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1644 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$978 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$979 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$980 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$981 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$992 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$997 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_alu0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_alu0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_alu0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_alu0_xer_ov_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_alu0_xer_so_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_branch0_fast1_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_branch0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_branch0_nia_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_cr0_cr_a_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_cr0_full_cr_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_cr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_div0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_div0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_div0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_div0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_ldst0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_ldst0_o_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_logical0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_logical0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_mul0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_mul0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_mul0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_mul0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_shiftrot0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_shiftrot0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_shiftrot0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_spr0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_spr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_spr0_spr1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_spr0_xer_ca_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_spr0_xer_ov_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_spr0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_trap0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_trap0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_trap0_msr_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_trap0_nia_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wrflag_trap0_o_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_CR_cr_a_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 6 \wrpick_CR_cr_a_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 6 \wrpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_CR_full_cr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire \wrpick_CR_full_cr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire \wrpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_FAST_fast1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 5 \wrpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 5 \wrpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_INT_o_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 10 \wrpick_INT_o_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 10 \wrpick_INT_o_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_SPR_spr1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire \wrpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire \wrpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_STATE_msr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire \wrpick_STATE_msr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire \wrpick_STATE_msr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_STATE_nia_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 \wrpick_STATE_nia_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 \wrpick_STATE_nia_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_XER_xer_ca_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 3 \wrpick_XER_xer_ca_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 3 \wrpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_XER_xer_ov_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 4 \wrpick_XER_xer_ov_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 4 \wrpick_XER_xer_ov_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \wrpick_XER_xer_so_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 4 \wrpick_XER_xer_so_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 4 \wrpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_data_i$170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_data_i$172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \xer_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_wen$171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 \xer_wen$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42103$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$988 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:42103$1506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42105$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$95 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:42105$1508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42106$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [2] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:42106$1509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42108$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1007 + connect \B \$1012 + connect \Y $and$libresoc.v:42108$1511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42109$1512 + parameter \A_SIGNED 0 + parameter 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parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1327 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:42229$1632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42233$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$126 + connect \B \fus_cu_busy_o$35 + connect \Y $and$libresoc.v:42233$1636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42234$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [5] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:42234$1637_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42236$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1347 + connect \B \$1351 + connect \Y $and$libresoc.v:42236$1639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42237$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1347 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:42237$1640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42251$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:42251$1654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42252$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [2] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:42252$1655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42253$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$102 [5] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:42253$1656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42254$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$111 [2] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:42254$1657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42255$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [0] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:42255$1658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42257$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1394 + connect \B \$1398 + connect \Y $and$libresoc.v:42257$1660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42258$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1394 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:42258$1661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42260$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$132 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42260$1663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42261$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [1] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:42261$1664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42263$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1410 + connect \B \$1414 + connect \Y $and$libresoc.v:42263$1666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42264$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1410 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:42264$1667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42266$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$133 + connect \B \fus_cu_busy_o$35 + connect \Y $and$libresoc.v:42266$1669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42267$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [2] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:42267$1670_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42269$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1426 + connect \B \$1430 + connect \Y $and$libresoc.v:42269$1672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42270$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1426 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:42270$1673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42277$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:42277$1681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42278$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [3] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:42278$1682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42279$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$102 [4] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:42279$1683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42280$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$105 [2] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:42280$1684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42281$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$108 [2] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:42281$1685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42282$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [0] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:42282$1686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42284$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1460 + connect \B \$1464 + connect \Y $and$libresoc.v:42284$1688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42285$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1460 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:42285$1689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42287$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$136 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:42287$1691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42288$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [1] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:42288$1692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42290$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1476 + connect \B \$1480 + connect \Y $and$libresoc.v:42290$1694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42291$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1476 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:42291$1695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42293$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter 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parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1508 + connect \B \$1512 + connect \Y $and$libresoc.v:42302$1706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42303$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1508 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:42303$1707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42311$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:42311$1715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42312$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [4] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:42312$1716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42313$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$102 [3] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:42313$1717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42314$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$105 [3] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:42314$1718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42315$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$108 [3] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:42315$1719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42316$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [0] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:42316$1720_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42318$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1544 + connect \B \$1548 + connect \Y $and$libresoc.v:42318$1722_Y + end + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42401$1807 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1753 + connect \Y $ternary$libresoc.v:42401$1807_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42407$1813 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1769 + connect \Y $ternary$libresoc.v:42407$1813_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42417$1824 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1793 + connect \Y $ternary$libresoc.v:42417$1824_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42425$1833 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spro + connect \S \wp$1813 + connect \Y $ternary$libresoc.v:42425$1833_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42516$1924 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_alu0_0 + connect \Y $ternary$libresoc.v:42516$1924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42522$1930 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_cr0_1 + connect \Y $ternary$libresoc.v:42522$1930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42528$1936 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_trap0_2 + connect \Y $ternary$libresoc.v:42528$1936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42534$1942 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_logical0_3 + connect \Y $ternary$libresoc.v:42534$1942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42540$1948 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_spr0_4 + connect \Y $ternary$libresoc.v:42540$1948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42546$1954 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_div0_5 + connect \Y $ternary$libresoc.v:42546$1954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42552$1960 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_mul0_6 + connect \Y $ternary$libresoc.v:42552$1960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42558$1966 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_shiftrot0_7 + connect \Y $ternary$libresoc.v:42558$1966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42564$1972 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_ldst0_8 + connect \Y $ternary$libresoc.v:42564$1972_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42579$1987 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_alu0_0 + connect \Y $ternary$libresoc.v:42579$1987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42585$1993 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_cr0_1 + connect \Y $ternary$libresoc.v:42585$1993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42591$1999 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_trap0_2 + connect \Y $ternary$libresoc.v:42591$1999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42597$2005 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_logical0_3 + connect \Y $ternary$libresoc.v:42597$2005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42603$2011 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_div0_4 + connect \Y $ternary$libresoc.v:42603$2011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42609$2017 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_mul0_5 + connect \Y $ternary$libresoc.v:42609$2017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42615$2023 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_shiftrot0_6 + connect \Y $ternary$libresoc.v:42615$2023_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42621$2029 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_ldst0_7 + connect \Y $ternary$libresoc.v:42621$2029_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42635$2043 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg3 + connect \S \rp_INT_rc_shiftrot0_0 + connect \Y $ternary$libresoc.v:42635$2043_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42641$2049 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg3 + connect \S \rp_INT_rc_ldst0_1 + connect \Y $ternary$libresoc.v:42641$2049_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42655$2063 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_alu0_0 + connect \Y $ternary$libresoc.v:42655$2063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42661$2069 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_logical0_1 + connect \Y $ternary$libresoc.v:42661$2069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42667$2075 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_spr0_2 + connect \Y $ternary$libresoc.v:42667$2075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42673$2081 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_div0_3 + connect \Y $ternary$libresoc.v:42673$2081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42679$2087 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_mul0_4 + connect \Y $ternary$libresoc.v:42679$2087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42685$2093 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_shiftrot0_5 + connect \Y $ternary$libresoc.v:42685$2093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42701$2110 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_alu0_0 + connect \Y $ternary$libresoc.v:42701$2110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42707$2116 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_spr0_1 + connect \Y $ternary$libresoc.v:42707$2116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42713$2122 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_shiftrot0_2 + connect \Y $ternary$libresoc.v:42713$2122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42726$2136 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \rp_XER_xer_ov_spr0_0 + connect \Y $ternary$libresoc.v:42726$2136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42732$2142 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B \core_core_cr_rd + connect \S \rp_CR_full_cr_cr0_0 + connect \Y $ternary$libresoc.v:42732$2142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42740$2150 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$811 + connect \S \rp_CR_cr_a_cr0_0 + connect \Y $ternary$libresoc.v:42740$2150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42748$2158 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$827 + connect \S \rp_CR_cr_a_branch0_1 + connect \Y $ternary$libresoc.v:42748$2158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42757$2167 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$846 + connect \S \rp_CR_cr_b_cr0_0 + connect \Y $ternary$libresoc.v:42757$2167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42765$2175 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$862 + connect \S \rp_CR_cr_c_cr0_0 + connect \Y $ternary$libresoc.v:42765$2175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42771$2181 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_branch0_0 + connect \Y $ternary$libresoc.v:42771$2181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42777$2187 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_trap0_1 + connect \Y $ternary$libresoc.v:42777$2187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42783$2193 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_spr0_2 + connect \Y $ternary$libresoc.v:42783$2193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42792$2202 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_branch0_0 + connect \Y $ternary$libresoc.v:42792$2202_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42798$2208 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_trap0_1 + connect \Y $ternary$libresoc.v:42798$2208_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42806$2216 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spr1 + connect \S \rp_SPR_spr1_spr0_0 + connect \Y $ternary$libresoc.v:42806$2216_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42823$2233 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_rego + connect \S \wp + connect \Y $ternary$libresoc.v:42823$2233_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42986.6-43003.4" + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \cr_data_i + connect \full_rd2__data_o \full_rd2__data_o + connect \full_rd2__ren \full_rd2__ren + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \wen \cr_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43004.11-43026.4" + cell \dec_ALU \dec_ALU + connect \ALU__data_len \dec_ALU_ALU__data_len + connect \ALU__fn_unit \dec_ALU_ALU__fn_unit + connect \ALU__imm_data__data \dec_ALU_ALU__imm_data__data + connect \ALU__imm_data__ok \dec_ALU_ALU__imm_data__ok + connect \ALU__input_carry \dec_ALU_ALU__input_carry + connect \ALU__insn \dec_ALU_ALU__insn + connect \ALU__insn_type \dec_ALU_ALU__insn_type + connect \ALU__invert_in \dec_ALU_ALU__invert_in + connect \ALU__invert_out \dec_ALU_ALU__invert_out + connect \ALU__is_32bit \dec_ALU_ALU__is_32bit + connect \ALU__is_signed \dec_ALU_ALU__is_signed + connect \ALU__oe__oe \dec_ALU_ALU__oe__oe + connect \ALU__oe__ok \dec_ALU_ALU__oe__ok + connect \ALU__output_carry \dec_ALU_ALU__output_carry + connect \ALU__rc__ok \dec_ALU_ALU__rc__ok + connect \ALU__rc__rc \dec_ALU_ALU__rc__rc + connect \ALU__write_cr0 \dec_ALU_ALU__write_cr0 + connect \ALU__zero_a \dec_ALU_ALU__zero_a + connect \bigendian \dec_ALU_bigendian + connect \raw_opcode_in \dec_ALU_raw_opcode_in + connect \sv_a_nz \dec_ALU_sv_a_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43027.14-43039.4" + cell \dec_BRANCH \dec_BRANCH + connect \BRANCH__cia \dec_BRANCH_BRANCH__cia + connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit + connect \BRANCH__imm_data__data \dec_BRANCH_BRANCH__imm_data__data + connect \BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__ok + connect \BRANCH__insn \dec_BRANCH_BRANCH__insn + connect \BRANCH__insn_type \dec_BRANCH_BRANCH__insn_type + connect \BRANCH__is_32bit \dec_BRANCH_BRANCH__is_32bit + connect \BRANCH__lk \dec_BRANCH_BRANCH__lk + connect \bigendian \dec_BRANCH_bigendian + connect \core_pc \core_pc + connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43040.10-43046.4" + cell \dec_CR \dec_CR + connect \CR__fn_unit \dec_CR_CR__fn_unit + connect \CR__insn \dec_CR_CR__insn + connect \CR__insn_type \dec_CR_CR__insn_type + connect \bigendian \dec_CR_bigendian + connect \raw_opcode_in \dec_CR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43047.11-43069.4" + cell \dec_DIV \dec_DIV + connect \DIV__data_len \dec_DIV_DIV__data_len + connect \DIV__fn_unit \dec_DIV_DIV__fn_unit + connect \DIV__imm_data__data \dec_DIV_DIV__imm_data__data + connect \DIV__imm_data__ok \dec_DIV_DIV__imm_data__ok + connect \DIV__input_carry \dec_DIV_DIV__input_carry + connect \DIV__insn \dec_DIV_DIV__insn + connect \DIV__insn_type \dec_DIV_DIV__insn_type + connect \DIV__invert_in \dec_DIV_DIV__invert_in + connect \DIV__invert_out \dec_DIV_DIV__invert_out + connect \DIV__is_32bit \dec_DIV_DIV__is_32bit + connect \DIV__is_signed \dec_DIV_DIV__is_signed + connect \DIV__oe__oe \dec_DIV_DIV__oe__oe + connect \DIV__oe__ok \dec_DIV_DIV__oe__ok + connect \DIV__output_carry \dec_DIV_DIV__output_carry + connect \DIV__rc__ok \dec_DIV_DIV__rc__ok + connect \DIV__rc__rc \dec_DIV_DIV__rc__rc + connect \DIV__write_cr0 \dec_DIV_DIV__write_cr0 + connect \DIV__zero_a \dec_DIV_DIV__zero_a + connect \bigendian \dec_DIV_bigendian + connect \raw_opcode_in \dec_DIV_raw_opcode_in + connect \sv_a_nz \dec_DIV_sv_a_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43070.12-43090.4" + cell \dec_LDST \dec_LDST + connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse + connect \LDST__data_len \dec_LDST_LDST__data_len + connect \LDST__fn_unit \dec_LDST_LDST__fn_unit + connect \LDST__imm_data__data \dec_LDST_LDST__imm_data__data + connect \LDST__imm_data__ok \dec_LDST_LDST__imm_data__ok + connect \LDST__insn \dec_LDST_LDST__insn + connect \LDST__insn_type \dec_LDST_LDST__insn_type + connect \LDST__is_32bit \dec_LDST_LDST__is_32bit + connect \LDST__is_signed \dec_LDST_LDST__is_signed + connect \LDST__ldst_mode \dec_LDST_LDST__ldst_mode + connect \LDST__oe__oe \dec_LDST_LDST__oe__oe + connect \LDST__oe__ok \dec_LDST_LDST__oe__ok + connect \LDST__rc__ok \dec_LDST_LDST__rc__ok + connect \LDST__rc__rc \dec_LDST_LDST__rc__rc + connect \LDST__sign_extend \dec_LDST_LDST__sign_extend + connect \LDST__zero_a \dec_LDST_LDST__zero_a + connect \bigendian \dec_LDST_bigendian + connect \raw_opcode_in \dec_LDST_raw_opcode_in + connect \sv_a_nz \dec_LDST_sv_a_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43091.15-43113.4" + cell \dec_LOGICAL \dec_LOGICAL + connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len + connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL__input_carry \dec_LOGICAL_LOGICAL__input_carry + connect \LOGICAL__insn \dec_LOGICAL_LOGICAL__insn + connect \LOGICAL__insn_type \dec_LOGICAL_LOGICAL__insn_type + connect \LOGICAL__invert_in \dec_LOGICAL_LOGICAL__invert_in + connect \LOGICAL__invert_out \dec_LOGICAL_LOGICAL__invert_out + connect \LOGICAL__is_32bit \dec_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL__is_signed \dec_LOGICAL_LOGICAL__is_signed + connect \LOGICAL__oe__oe \dec_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL__output_carry \dec_LOGICAL_LOGICAL__output_carry + connect \LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL__rc__rc \dec_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a + connect \bigendian \dec_LOGICAL_bigendian + connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + connect \sv_a_nz \dec_LOGICAL_sv_a_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43114.11-43129.4" + cell \dec_MUL \dec_MUL + connect \MUL__fn_unit \dec_MUL_MUL__fn_unit + connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data + connect \MUL__imm_data__ok \dec_MUL_MUL__imm_data__ok + connect \MUL__insn \dec_MUL_MUL__insn + connect \MUL__insn_type \dec_MUL_MUL__insn_type + connect \MUL__is_32bit \dec_MUL_MUL__is_32bit + connect \MUL__is_signed \dec_MUL_MUL__is_signed + connect \MUL__oe__oe \dec_MUL_MUL__oe__oe + connect \MUL__oe__ok \dec_MUL_MUL__oe__ok + connect \MUL__rc__ok \dec_MUL_MUL__rc__ok + connect \MUL__rc__rc \dec_MUL_MUL__rc__rc + connect \MUL__write_cr0 \dec_MUL_MUL__write_cr0 + connect \bigendian \dec_MUL_bigendian + connect \raw_opcode_in \dec_MUL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43130.17-43150.4" + cell \dec_SHIFT_ROT \dec_SHIFT_ROT + connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT__insn + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_SHIFT_ROT__invert_in + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \bigendian \dec_SHIFT_ROT_bigendian + connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43151.11-43158.4" + cell \dec_SPR \dec_SPR + connect \SPR__fn_unit \dec_SPR_SPR__fn_unit + connect \SPR__insn \dec_SPR_SPR__insn + connect \SPR__insn_type \dec_SPR_SPR__insn_type + connect \SPR__is_32bit \dec_SPR_SPR__is_32bit + connect \bigendian \dec_SPR_bigendian + connect \raw_opcode_in \dec_SPR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43159.8-43177.4" + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \fast_dest1__addr + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__wen \fast_dest1__wen + connect \issue__addr \issue__addr + connect \issue__addr$1 \issue__addr$12 + connect \issue__data_i \issue__data_i + connect \issue__data_o \issue__data_o + connect \issue__ren \issue__ren + connect \issue__wen \issue__wen + connect \src1__addr \fast_src1__addr + connect \src1__data_o \fast_src1__data_o + connect \src1__ren \fast_src1__ren + connect \src2__addr \fast_src2__addr + connect \src2__data_o \fast_src2__data_o + connect \src2__ren \fast_src2__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43178.7-43509.4" + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \fus_cr_a_ok + connect \cr_a_ok$110 \fus_cr_a_ok$122 + connect \cr_a_ok$111 \fus_cr_a_ok$123 + connect \cr_a_ok$112 \fus_cr_a_ok$124 + connect \cr_a_ok$113 \fus_cr_a_ok$125 + connect \cr_a_ok$114 \fus_cr_a_ok$126 + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \fus_cu_busy_o + connect \cu_busy_o$11 \fus_cu_busy_o$23 + connect \cu_busy_o$14 \fus_cu_busy_o$26 + connect \cu_busy_o$17 \fus_cu_busy_o$29 + connect \cu_busy_o$2 \fus_cu_busy_o$14 + connect \cu_busy_o$20 \fus_cu_busy_o$32 + connect \cu_busy_o$23 \fus_cu_busy_o$35 + connect \cu_busy_o$26 \fus_cu_busy_o$38 + connect \cu_busy_o$5 \fus_cu_busy_o$17 + connect \cu_busy_o$8 \fus_cu_busy_o$20 + connect \cu_issue_i \fus_cu_issue_i + connect \cu_issue_i$1 \fus_cu_issue_i$13 + connect \cu_issue_i$10 \fus_cu_issue_i$22 + connect \cu_issue_i$13 \fus_cu_issue_i$25 + connect \cu_issue_i$16 \fus_cu_issue_i$28 + connect \cu_issue_i$19 \fus_cu_issue_i$31 + connect \cu_issue_i$22 \fus_cu_issue_i$34 + connect \cu_issue_i$25 \fus_cu_issue_i$37 + connect \cu_issue_i$4 \fus_cu_issue_i$16 + connect \cu_issue_i$7 \fus_cu_issue_i$19 + connect \cu_rd__go_i \fus_cu_rd__go_i + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$41 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$44 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$47 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$50 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$53 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$56 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$59 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$62 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$82 + connect \cu_rd__rel_o \fus_cu_rd__rel_o + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$40 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$43 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$46 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$49 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$52 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$55 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$58 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$61 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$81 + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$24 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$27 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$30 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$33 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$36 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$39 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$15 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$18 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$21 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \fus_cu_wr__go_i + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$112 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$114 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$149 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$94 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$97 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$100 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$103 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$106 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$109 + connect \cu_wr__rel_o \fus_cu_wr__rel_o + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$113 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$148 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$93 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$96 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$99 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$102 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$105 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$108 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$111 + connect \dest1_o \fus_dest1_o + connect \dest1_o$103 \fus_dest1_o$115 + connect \dest1_o$104 \fus_dest1_o$116 + connect \dest1_o$105 \fus_dest1_o$117 + connect \dest1_o$106 \fus_dest1_o$118 + connect \dest1_o$107 \fus_dest1_o$119 + connect \dest1_o$108 \fus_dest1_o$120 + connect \dest1_o$109 \fus_dest1_o$121 + connect \dest1_o$141 \fus_dest1_o$153 + connect \dest2_o \fus_dest2_o + connect \dest2_o$115 \fus_dest2_o$127 + connect \dest2_o$116 \fus_dest2_o$128 + connect \dest2_o$117 \fus_dest2_o$129 + connect \dest2_o$118 \fus_dest2_o$130 + connect \dest2_o$119 \fus_dest2_o$131 + connect \dest2_o$142 \fus_dest2_o$154 + connect \dest2_o$144 \fus_dest2_o$156 + connect \dest2_o$150 \fus_dest2_o$162 + connect \dest3_o \fus_dest3_o + connect \dest3_o$122 \fus_dest3_o$134 + connect \dest3_o$123 \fus_dest3_o$135 + connect \dest3_o$127 \fus_dest3_o$139 + connect \dest3_o$128 \fus_dest3_o$140 + connect \dest3_o$143 \fus_dest3_o$155 + connect \dest3_o$145 \fus_dest3_o$157 + connect \dest3_o$147 \fus_dest3_o$159 + connect \dest4_o \fus_dest4_o + connect \dest4_o$133 \fus_dest4_o$145 + connect \dest4_o$134 \fus_dest4_o$146 + connect \dest4_o$135 \fus_dest4_o$147 + connect \dest4_o$148 \fus_dest4_o$160 + connect \dest5_o \fus_dest5_o + connect \dest5_o$132 \fus_dest5_o$144 + connect \dest5_o$149 \fus_dest5_o$161 + connect \dest6_o \fus_dest6_o + connect \ea \fus_ea + connect \fast1_ok \fus_fast1_ok + connect \fast1_ok$138 \fus_fast1_ok$150 + connect \fast1_ok$139 \fus_fast1_ok$151 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$140 \fus_fast2_ok$152 + connect \full_cr_ok \fus_full_cr_ok + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$168 + connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$169 + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \msr_ok \fus_msr_ok + connect \nia_ok \fus_nia_ok + connect \nia_ok$146 \fus_nia_ok$158 + connect \o \fus_o + connect \o_ok \fus_o_ok + connect \o_ok$80 \fus_o_ok$92 + connect \o_ok$83 \fus_o_ok$95 + connect \o_ok$86 \fus_o_ok$98 + connect \o_ok$89 \fus_o_ok$101 + connect \o_ok$92 \fus_o_ok$104 + connect \o_ok$95 \fus_o_ok$107 + connect \o_ok$98 \fus_o_ok$110 + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \fus_oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \fus_oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a + connect \spr1_ok \fus_spr1_ok + connect \src1_i \fus_src1_i + connect \src1_i$30 \fus_src1_i$42 + connect \src1_i$33 \fus_src1_i$45 + connect \src1_i$36 \fus_src1_i$48 + connect \src1_i$39 \fus_src1_i$51 + connect \src1_i$42 \fus_src1_i$54 + connect \src1_i$45 \fus_src1_i$57 + connect \src1_i$48 \fus_src1_i$60 + connect \src1_i$51 \fus_src1_i$63 + connect \src1_i$74 \fus_src1_i$86 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$64 + connect \src2_i$53 \fus_src2_i$65 + connect \src2_i$54 \fus_src2_i$66 + connect \src2_i$55 \fus_src2_i$67 + connect \src2_i$56 \fus_src2_i$68 + connect \src2_i$57 \fus_src2_i$69 + connect \src2_i$58 \fus_src2_i$70 + connect \src2_i$77 \fus_src2_i$89 + connect \src2_i$79 \fus_src2_i$91 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$71 + connect \src3_i$60 \fus_src3_i$72 + connect \src3_i$61 \fus_src3_i$73 + connect \src3_i$62 \fus_src3_i$74 + connect \src3_i$63 \fus_src3_i$75 + connect \src3_i$67 \fus_src3_i$79 + connect \src3_i$71 \fus_src3_i$83 + connect \src3_i$75 \fus_src3_i$87 + connect \src3_i$76 \fus_src3_i$88 + connect \src4_i \fus_src4_i + connect \src4_i$64 \fus_src4_i$76 + connect \src4_i$65 \fus_src4_i$77 + connect \src4_i$68 \fus_src4_i$80 + connect \src4_i$78 \fus_src4_i$90 + connect \src5_i \fus_src5_i + connect \src5_i$66 \fus_src5_i$78 + connect \src5_i$72 \fus_src5_i$84 + connect \src6_i \fus_src6_i + connect \src6_i$73 \fus_src6_i$85 + connect \xer_ca_ok \fus_xer_ca_ok + connect \xer_ca_ok$120 \fus_xer_ca_ok$132 + connect \xer_ca_ok$121 \fus_xer_ca_ok$133 + connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$124 \fus_xer_ov_ok$136 + connect \xer_ov_ok$125 \fus_xer_ov_ok$137 + connect \xer_ov_ok$126 \fus_xer_ov_ok$138 + connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$129 \fus_xer_so_ok$141 + connect \xer_so_ok$130 \fus_xer_so_ok$142 + connect \xer_so_ok$131 \fus_xer_so_ok$143 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43510.9-43528.4" + cell \int \int + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \int_dest1__addr + connect \dest1__data_i \int_dest1__data_i + connect \dest1__wen \int_dest1__wen + connect \dmi__addr \dmi__addr + connect \dmi__data_o \dmi__data_o + connect \dmi__ren \dmi__ren + connect \src1__addr \int_src1__addr + connect \src1__data_o \int_src1__data_o + connect \src1__ren \int_src1__ren + connect \src2__addr \int_src2__addr + connect \src2__data_o \int_src2__data_o + connect \src2__ren \int_src2__ren + connect \src3__addr \int_src3__addr + connect \src3__data_o \int_src3__data_o + connect \src3__ren \int_src3__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43529.6-43561.4" + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$168 + connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$169 + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \wb_dcache_en \wb_dcache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43562.18-43566.4" + cell \rdpick_CR_cr_a \rdpick_CR_cr_a + connect \en_o \rdpick_CR_cr_a_en_o + connect \i \rdpick_CR_cr_a_i + connect \o \rdpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43567.18-43571.4" + cell \rdpick_CR_cr_b \rdpick_CR_cr_b + connect \en_o \rdpick_CR_cr_b_en_o + connect \i \rdpick_CR_cr_b_i + connect \o \rdpick_CR_cr_b_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43572.18-43576.4" + cell \rdpick_CR_cr_c \rdpick_CR_cr_c + connect \en_o \rdpick_CR_cr_c_en_o + connect \i \rdpick_CR_cr_c_i + connect \o \rdpick_CR_cr_c_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43577.21-43581.4" + cell \rdpick_CR_full_cr \rdpick_CR_full_cr + connect \en_o \rdpick_CR_full_cr_en_o + connect \i \rdpick_CR_full_cr_i + connect \o \rdpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43582.21-43586.4" + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \en_o \rdpick_FAST_fast1_en_o + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43587.21-43591.4" + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \en_o \rdpick_FAST_fast2_en_o + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43592.17-43596.4" + cell \rdpick_INT_ra \rdpick_INT_ra + connect \en_o \rdpick_INT_ra_en_o + connect \i \rdpick_INT_ra_i + connect \o \rdpick_INT_ra_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43597.17-43601.4" + cell \rdpick_INT_rb \rdpick_INT_rb + connect \en_o \rdpick_INT_rb_en_o + connect \i \rdpick_INT_rb_i + connect \o \rdpick_INT_rb_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43602.17-43606.4" + cell \rdpick_INT_rc \rdpick_INT_rc + connect \en_o \rdpick_INT_rc_en_o + connect \i \rdpick_INT_rc_i + connect \o \rdpick_INT_rc_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43607.19-43611.4" + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \en_o \rdpick_SPR_spr1_en_o + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43612.21-43616.4" + cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca + connect \en_o \rdpick_XER_xer_ca_en_o + connect \i \rdpick_XER_xer_ca_i + connect \o \rdpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43617.21-43621.4" + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \en_o \rdpick_XER_xer_ov_en_o + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43622.21-43626.4" + cell \rdpick_XER_xer_so \rdpick_XER_xer_so + connect \en_o \rdpick_XER_xer_so_en_o + connect \i \rdpick_XER_xer_so_i + connect \o \rdpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43627.7-43636.4" + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \spr1__addr \spr_spr1__addr + connect \spr1__addr$1 \spr_spr1__addr$175 + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__ren \spr_spr1__ren + connect \spr1__wen \spr_spr1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43637.9-43654.4" + cell \state \state + connect \cia__data_o \cia__data_o + connect \cia__ren \cia__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \data_i + connect \data_i$2 \data_i$11 + connect \data_i$3 \state_data_i + connect \data_i$4 \state_data_i$174 + connect \msr__data_o \msr__data_o + connect \msr__ren \msr__ren + connect \state_nia_wen \state_nia_wen + connect \sv__data_o \sv__data_o + connect \sv__ren \sv__ren + connect \wen \wen + connect \wen$1 \wen$10 + connect \wen$5 \state_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43655.18-43659.4" + cell \wrpick_CR_cr_a \wrpick_CR_cr_a + connect \en_o \wrpick_CR_cr_a_en_o + connect \i \wrpick_CR_cr_a_i + connect \o \wrpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43660.21-43664.4" + cell \wrpick_CR_full_cr \wrpick_CR_full_cr + connect \en_o \wrpick_CR_full_cr_en_o + connect \i \wrpick_CR_full_cr_i + connect \o \wrpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43665.21-43669.4" + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \en_o \wrpick_FAST_fast1_en_o + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43670.16-43674.4" + cell \wrpick_INT_o \wrpick_INT_o + connect \en_o \wrpick_INT_o_en_o + connect \i \wrpick_INT_o_i + connect \o \wrpick_INT_o_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43675.19-43679.4" + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \en_o \wrpick_SPR_spr1_en_o + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43680.20-43684.4" + cell \wrpick_STATE_msr \wrpick_STATE_msr + connect \en_o \wrpick_STATE_msr_en_o + connect \i \wrpick_STATE_msr_i + connect \o \wrpick_STATE_msr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43685.20-43689.4" + cell \wrpick_STATE_nia \wrpick_STATE_nia + connect \en_o \wrpick_STATE_nia_en_o + connect \i \wrpick_STATE_nia_i + connect \o \wrpick_STATE_nia_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43690.21-43694.4" + cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca + connect \en_o \wrpick_XER_xer_ca_en_o + connect \i \wrpick_XER_xer_ca_i + connect \o \wrpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43695.21-43699.4" + cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov + connect \en_o \wrpick_XER_xer_ov_en_o + connect \i \wrpick_XER_xer_ov_i + connect \o \wrpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43700.21-43704.4" + cell \wrpick_XER_xer_so \wrpick_XER_xer_so + connect \en_o \wrpick_XER_xer_so_en_o + connect \i \wrpick_XER_xer_so_i + connect \o \wrpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43705.7-43722.4" + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \xer_data_i + connect \data_i$1 \xer_data_i$170 + connect \data_i$3 \xer_data_i$172 + connect \full_rd__data_o \full_rd__data_o + connect \full_rd__ren \full_rd__ren + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \wen \xer_wen + connect \wen$2 \xer_wen$171 + connect \wen$4 \xer_wen$173 + end + attribute \src "libresoc.v:36214.7-36214.20" + process $proc$libresoc.v:36214$2900 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:38263.7-38263.30" + process $proc$libresoc.v:38263$2901 + assign { } { } + assign $1\core_terminate_o[0:0] 1'0 + sync always + sync init + update \core_terminate_o $1\core_terminate_o[0:0] + end + attribute \src "libresoc.v:38276.13-38276.27" + process $proc$libresoc.v:38276$2902 + assign { } { } + assign $1\counter[1:0] 2'00 + sync always + sync init + update \counter $1\counter[1:0] + end + attribute \src "libresoc.v:39443.7-39443.34" + process $proc$libresoc.v:39443$2903 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:39447.7-39447.30" + process $proc$libresoc.v:39447$2904 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:39451.7-39451.30" + process $proc$libresoc.v:39451$2905 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:39455.7-39455.30" + process $proc$libresoc.v:39455$2906 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:39459.7-39459.33" + process $proc$libresoc.v:39459$2907 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:39463.7-39463.37" + process $proc$libresoc.v:39463$2908 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:39467.7-39467.34" + process $proc$libresoc.v:39467$2909 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:39471.7-39471.35" + process $proc$libresoc.v:39471$2910 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:39475.7-39475.37" + process $proc$libresoc.v:39475$2911 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:39479.7-39479.35" + process $proc$libresoc.v:39479$2912 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:39483.7-39483.30" + process $proc$libresoc.v:39483$2913 + assign { } { } + assign $1\dp_INT_ra_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:39487.7-39487.29" + process $proc$libresoc.v:39487$2914 + assign { } { } + assign $1\dp_INT_ra_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:39491.7-39491.30" + process $proc$libresoc.v:39491$2915 + assign { } { } + assign $1\dp_INT_ra_div0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:39495.7-39495.31" + process $proc$libresoc.v:39495$2916 + assign { } { } + assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:39499.7-39499.34" + process $proc$libresoc.v:39499$2917 + assign { } { } + assign $1\dp_INT_ra_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:39503.7-39503.30" + process $proc$libresoc.v:39503$2918 + assign { } { } + assign $1\dp_INT_ra_mul0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:39507.7-39507.35" + process $proc$libresoc.v:39507$2919 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:39511.7-39511.30" + process $proc$libresoc.v:39511$2920 + assign { } { } + assign $1\dp_INT_ra_spr0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:39515.7-39515.31" + process $proc$libresoc.v:39515$2921 + assign { } { } + assign $1\dp_INT_ra_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:39519.7-39519.30" + process $proc$libresoc.v:39519$2922 + assign { } { } + assign $1\dp_INT_rb_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:39523.7-39523.29" + process $proc$libresoc.v:39523$2923 + assign { } { } + assign $1\dp_INT_rb_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:39527.7-39527.30" + process $proc$libresoc.v:39527$2924 + assign { } { } + assign $1\dp_INT_rb_div0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:39531.7-39531.31" + process $proc$libresoc.v:39531$2925 + assign { } { } + assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:39535.7-39535.34" + process $proc$libresoc.v:39535$2926 + assign { } { } + assign $1\dp_INT_rb_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:39539.7-39539.30" + process $proc$libresoc.v:39539$2927 + assign { } { } + assign $1\dp_INT_rb_mul0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:39543.7-39543.35" + process $proc$libresoc.v:39543$2928 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:39547.7-39547.31" + process $proc$libresoc.v:39547$2929 + assign { } { } + assign $1\dp_INT_rb_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:39551.7-39551.31" + process $proc$libresoc.v:39551$2930 + assign { } { } + assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:39555.7-39555.35" + process $proc$libresoc.v:39555$2931 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:39559.7-39559.32" + process $proc$libresoc.v:39559$2932 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:39563.7-39563.34" + process $proc$libresoc.v:39563$2933 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:39567.7-39567.39" + process $proc$libresoc.v:39567$2934 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:39571.7-39571.34" + process $proc$libresoc.v:39571$2935 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:39575.7-39575.34" + process $proc$libresoc.v:39575$2936 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:39579.7-39579.34" + process $proc$libresoc.v:39579$2937 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:39583.7-39583.34" + process $proc$libresoc.v:39583$2938 + assign { } { } + assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:39587.7-39587.38" + process $proc$libresoc.v:39587$2939 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:39591.7-39591.34" + process $proc$libresoc.v:39591$2940 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:39595.7-39595.39" + process $proc$libresoc.v:39595$2941 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:39599.7-39599.34" + process $proc$libresoc.v:39599$2942 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:41724.7-41724.25" + process $proc$libresoc.v:41724$2943 + assign { } { } + assign $1\wr_pick_dly[0:0] 1'0 + sync always + sync init + update \wr_pick_dly $1\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:41726.7-41726.32" + process $proc$libresoc.v:41726$2944 + assign { } { } + assign $0\wr_pick_dly$1010[0:0]$2945 1'0 + sync always + sync init + update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2945 + end + attribute \src "libresoc.v:41730.7-41730.32" + process $proc$libresoc.v:41730$2946 + assign { } { } + assign $0\wr_pick_dly$1031[0:0]$2947 1'0 + sync always + sync init + update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2947 + end + attribute \src "libresoc.v:41734.7-41734.32" + process $proc$libresoc.v:41734$2948 + assign { } { } + assign $0\wr_pick_dly$1049[0:0]$2949 1'0 + sync always + sync init + update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2949 + end + attribute \src "libresoc.v:41738.7-41738.32" + process $proc$libresoc.v:41738$2950 + assign { } { } + assign $0\wr_pick_dly$1071[0:0]$2951 1'0 + sync always + sync init + update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2951 + end + attribute \src "libresoc.v:41742.7-41742.32" + process $proc$libresoc.v:41742$2952 + assign { } { } + assign $0\wr_pick_dly$1091[0:0]$2953 1'0 + sync always + sync init + update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2953 + end + attribute \src "libresoc.v:41746.7-41746.32" + process $proc$libresoc.v:41746$2954 + assign { } { } + assign $0\wr_pick_dly$1111[0:0]$2955 1'0 + sync always + sync init + update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2955 + end + attribute \src "libresoc.v:41750.7-41750.32" + process $proc$libresoc.v:41750$2956 + assign { } { } + assign $0\wr_pick_dly$1130[0:0]$2957 1'0 + sync always + sync init + update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2957 + end + attribute \src "libresoc.v:41754.7-41754.32" + process $proc$libresoc.v:41754$2958 + assign { } { } + assign $0\wr_pick_dly$1148[0:0]$2959 1'0 + sync always + sync init + update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2959 + end + attribute \src "libresoc.v:41758.7-41758.32" + process $proc$libresoc.v:41758$2960 + assign { } { } + assign $0\wr_pick_dly$1222[0:0]$2961 1'0 + sync always + sync init + update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2961 + end + attribute \src "libresoc.v:41762.7-41762.32" + process $proc$libresoc.v:41762$2962 + assign { } { } + assign $0\wr_pick_dly$1250[0:0]$2963 1'0 + sync always + sync init + update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2963 + end + attribute \src "libresoc.v:41766.7-41766.32" + process $proc$libresoc.v:41766$2964 + assign { } { } + assign $0\wr_pick_dly$1270[0:0]$2965 1'0 + sync always + sync init + update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2965 + end + attribute \src "libresoc.v:41770.7-41770.32" + process $proc$libresoc.v:41770$2966 + assign { } { } + assign $0\wr_pick_dly$1290[0:0]$2967 1'0 + sync always + sync init + update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2967 + end + attribute \src "libresoc.v:41774.7-41774.32" + process $proc$libresoc.v:41774$2968 + assign { } { } + assign $0\wr_pick_dly$1310[0:0]$2969 1'0 + sync always + sync init + update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2969 + end + attribute \src "libresoc.v:41778.7-41778.32" + process $proc$libresoc.v:41778$2970 + assign { } { } + assign $0\wr_pick_dly$1330[0:0]$2971 1'0 + sync always + sync init + update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2971 + end + attribute \src "libresoc.v:41782.7-41782.32" + process $proc$libresoc.v:41782$2972 + assign { } { } + assign $0\wr_pick_dly$1350[0:0]$2973 1'0 + sync always + sync init + update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2973 + end + attribute \src "libresoc.v:41786.7-41786.32" + process $proc$libresoc.v:41786$2974 + assign { } { } + assign $0\wr_pick_dly$1397[0:0]$2975 1'0 + sync always + sync init + update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2975 + end + attribute \src "libresoc.v:41790.7-41790.32" + process $proc$libresoc.v:41790$2976 + assign { } { } + assign $0\wr_pick_dly$1413[0:0]$2977 1'0 + sync always + sync init + update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2977 + end + attribute \src "libresoc.v:41794.7-41794.32" + process $proc$libresoc.v:41794$2978 + assign { } { } + assign $0\wr_pick_dly$1429[0:0]$2979 1'0 + sync always + sync init + update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2979 + end + attribute \src "libresoc.v:41798.7-41798.32" + process $proc$libresoc.v:41798$2980 + assign { } { } + assign $0\wr_pick_dly$1463[0:0]$2981 1'0 + sync always + sync init + update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2981 + end + attribute \src "libresoc.v:41802.7-41802.32" + process $proc$libresoc.v:41802$2982 + assign { } { } + assign $0\wr_pick_dly$1479[0:0]$2983 1'0 + sync always + sync init + update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2983 + end + attribute \src "libresoc.v:41806.7-41806.32" + process $proc$libresoc.v:41806$2984 + assign { } { } + assign $0\wr_pick_dly$1495[0:0]$2985 1'0 + sync always + sync init + update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2985 + end + attribute \src "libresoc.v:41810.7-41810.32" + process $proc$libresoc.v:41810$2986 + assign { } { } + assign $0\wr_pick_dly$1511[0:0]$2987 1'0 + sync always + sync init + update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2987 + end + attribute \src "libresoc.v:41814.7-41814.32" + process $proc$libresoc.v:41814$2988 + assign { } { } + assign $0\wr_pick_dly$1547[0:0]$2989 1'0 + sync always + sync init + update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2989 + end + attribute \src "libresoc.v:41818.7-41818.32" + process $proc$libresoc.v:41818$2990 + assign { } { } + assign $0\wr_pick_dly$1563[0:0]$2991 1'0 + sync always + sync init + update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2991 + end + attribute \src "libresoc.v:41822.7-41822.32" + process $proc$libresoc.v:41822$2992 + assign { } { } + assign $0\wr_pick_dly$1579[0:0]$2993 1'0 + sync always + sync init + update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2993 + end + attribute \src "libresoc.v:41826.7-41826.32" + process $proc$libresoc.v:41826$2994 + assign { } { } + assign $0\wr_pick_dly$1595[0:0]$2995 1'0 + sync always + sync init + update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2995 + end + attribute \src "libresoc.v:41830.7-41830.32" + process $proc$libresoc.v:41830$2996 + assign { } { } + assign $0\wr_pick_dly$1637[0:0]$2997 1'0 + sync always + sync init + update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2997 + end + attribute \src "libresoc.v:41834.7-41834.32" + process $proc$libresoc.v:41834$2998 + assign { } { } + assign $0\wr_pick_dly$1656[0:0]$2999 1'0 + sync always + sync init + update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2999 + end + attribute \src "libresoc.v:41838.7-41838.32" + process $proc$libresoc.v:41838$3000 + assign { } { } + assign $0\wr_pick_dly$1672[0:0]$3001 1'0 + sync always + sync init + update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$3001 + end + attribute \src "libresoc.v:41842.7-41842.32" + process $proc$libresoc.v:41842$3002 + assign { } { } + assign $0\wr_pick_dly$1688[0:0]$3003 1'0 + sync always + sync init + update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$3003 + end + attribute \src "libresoc.v:41846.7-41846.32" + process $proc$libresoc.v:41846$3004 + assign { } { } + assign $0\wr_pick_dly$1704[0:0]$3005 1'0 + sync always + sync init + update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$3005 + end + attribute \src "libresoc.v:41850.7-41850.32" + process $proc$libresoc.v:41850$3006 + assign { } { } + assign $0\wr_pick_dly$1748[0:0]$3007 1'0 + sync always + sync init + update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$3007 + end + attribute \src "libresoc.v:41854.7-41854.32" + process $proc$libresoc.v:41854$3008 + assign { } { } + assign $0\wr_pick_dly$1764[0:0]$3009 1'0 + sync always + sync init + update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$3009 + end + attribute \src "libresoc.v:41858.7-41858.32" + process $proc$libresoc.v:41858$3010 + assign { } { } + assign $0\wr_pick_dly$1788[0:0]$3011 1'0 + sync always + sync init + update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$3011 + end + attribute \src "libresoc.v:41862.7-41862.32" + process $proc$libresoc.v:41862$3012 + assign { } { } + assign $0\wr_pick_dly$1808[0:0]$3013 1'0 + sync always + sync init + update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$3013 + end + attribute \src "libresoc.v:41866.7-41866.31" + process $proc$libresoc.v:41866$3014 + assign { } { } + assign $0\wr_pick_dly$991[0:0]$3015 1'0 + sync always + sync init + update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$3015 + end + attribute \src "libresoc.v:42828.3-42829.51" + process $proc$libresoc.v:42828$2238 + assign { } { } + assign $0\wr_pick_dly$1808[0:0]$2239 \wr_pick_dly$1808$next + sync posedge \coresync_clk + update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$2239 + end + attribute \src "libresoc.v:42830.3-42831.51" + process $proc$libresoc.v:42830$2240 + assign { } { } + assign $0\wr_pick_dly$1788[0:0]$2241 \wr_pick_dly$1788$next + sync posedge \coresync_clk + update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$2241 + end + attribute \src "libresoc.v:42832.3-42833.51" + process $proc$libresoc.v:42832$2242 + assign { } { } + assign $0\wr_pick_dly$1764[0:0]$2243 \wr_pick_dly$1764$next + sync posedge \coresync_clk + update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$2243 + end + attribute \src "libresoc.v:42834.3-42835.51" + process $proc$libresoc.v:42834$2244 + assign { } { } + assign $0\wr_pick_dly$1748[0:0]$2245 \wr_pick_dly$1748$next + sync posedge \coresync_clk + update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$2245 + end + attribute \src "libresoc.v:42836.3-42837.51" + process $proc$libresoc.v:42836$2246 + assign { } { } + assign $0\wr_pick_dly$1704[0:0]$2247 \wr_pick_dly$1704$next + sync posedge \coresync_clk + update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$2247 + end + attribute \src "libresoc.v:42838.3-42839.51" + process $proc$libresoc.v:42838$2248 + assign { } { } + assign $0\wr_pick_dly$1688[0:0]$2249 \wr_pick_dly$1688$next + sync posedge \coresync_clk + update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$2249 + end + attribute \src "libresoc.v:42840.3-42841.51" + process $proc$libresoc.v:42840$2250 + assign { } { } + assign $0\wr_pick_dly$1672[0:0]$2251 \wr_pick_dly$1672$next + sync posedge \coresync_clk + update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$2251 + end + attribute \src "libresoc.v:42842.3-42843.51" + process $proc$libresoc.v:42842$2252 + assign { } { } + assign $0\wr_pick_dly$1656[0:0]$2253 \wr_pick_dly$1656$next + sync posedge \coresync_clk + update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2253 + end + attribute \src "libresoc.v:42844.3-42845.51" + process $proc$libresoc.v:42844$2254 + assign { } { } + assign $0\wr_pick_dly$1637[0:0]$2255 \wr_pick_dly$1637$next + sync posedge \coresync_clk + update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2255 + end + attribute \src "libresoc.v:42846.3-42847.51" + process $proc$libresoc.v:42846$2256 + assign { } { } + assign $0\wr_pick_dly$1595[0:0]$2257 \wr_pick_dly$1595$next + sync posedge \coresync_clk + update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2257 + end + attribute \src "libresoc.v:42848.3-42849.51" + process $proc$libresoc.v:42848$2258 + assign { } { } + assign $0\wr_pick_dly$1579[0:0]$2259 \wr_pick_dly$1579$next + sync posedge \coresync_clk + update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2259 + end + attribute \src "libresoc.v:42850.3-42851.51" + process $proc$libresoc.v:42850$2260 + assign { } { } + assign $0\wr_pick_dly$1563[0:0]$2261 \wr_pick_dly$1563$next + sync posedge \coresync_clk + update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2261 + end + attribute \src "libresoc.v:42852.3-42853.51" + process $proc$libresoc.v:42852$2262 + assign { } { } + assign $0\wr_pick_dly$1547[0:0]$2263 \wr_pick_dly$1547$next + sync posedge \coresync_clk + update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2263 + end + attribute \src "libresoc.v:42854.3-42855.51" + process $proc$libresoc.v:42854$2264 + assign { } { } + assign $0\wr_pick_dly$1511[0:0]$2265 \wr_pick_dly$1511$next + sync posedge \coresync_clk + update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2265 + end + attribute \src "libresoc.v:42856.3-42857.51" + process $proc$libresoc.v:42856$2266 + assign { } { } + assign $0\wr_pick_dly$1495[0:0]$2267 \wr_pick_dly$1495$next + sync posedge \coresync_clk + update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2267 + end + attribute \src "libresoc.v:42858.3-42859.51" + process $proc$libresoc.v:42858$2268 + assign { } { } + assign $0\wr_pick_dly$1479[0:0]$2269 \wr_pick_dly$1479$next + sync posedge \coresync_clk + update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2269 + end + attribute \src "libresoc.v:42860.3-42861.51" + process $proc$libresoc.v:42860$2270 + assign { } { } + assign $0\wr_pick_dly$1463[0:0]$2271 \wr_pick_dly$1463$next + sync posedge \coresync_clk + update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2271 + end + attribute \src "libresoc.v:42862.3-42863.51" + process $proc$libresoc.v:42862$2272 + assign { } { } + assign $0\wr_pick_dly$1429[0:0]$2273 \wr_pick_dly$1429$next + sync posedge \coresync_clk + update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2273 + end + attribute \src "libresoc.v:42864.3-42865.51" + process $proc$libresoc.v:42864$2274 + assign { } { } + assign $0\wr_pick_dly$1413[0:0]$2275 \wr_pick_dly$1413$next + sync posedge \coresync_clk + update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2275 + end + attribute \src "libresoc.v:42866.3-42867.51" + process $proc$libresoc.v:42866$2276 + assign { } { } + assign $0\wr_pick_dly$1397[0:0]$2277 \wr_pick_dly$1397$next + sync posedge \coresync_clk + update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2277 + end + attribute \src "libresoc.v:42868.3-42869.51" + process $proc$libresoc.v:42868$2278 + assign { } { } + assign $0\wr_pick_dly$1350[0:0]$2279 \wr_pick_dly$1350$next + sync posedge \coresync_clk + update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2279 + end + attribute \src "libresoc.v:42870.3-42871.51" + process $proc$libresoc.v:42870$2280 + assign { } { } + assign $0\wr_pick_dly$1330[0:0]$2281 \wr_pick_dly$1330$next + sync posedge \coresync_clk + update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2281 + end + attribute \src "libresoc.v:42872.3-42873.51" + process $proc$libresoc.v:42872$2282 + assign { } { } + assign $0\wr_pick_dly$1310[0:0]$2283 \wr_pick_dly$1310$next + sync posedge \coresync_clk + update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2283 + end + attribute \src "libresoc.v:42874.3-42875.51" + process $proc$libresoc.v:42874$2284 + assign { } { } + assign $0\wr_pick_dly$1290[0:0]$2285 \wr_pick_dly$1290$next + sync posedge \coresync_clk + update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2285 + end + attribute \src "libresoc.v:42876.3-42877.51" + process $proc$libresoc.v:42876$2286 + assign { } { } + assign $0\wr_pick_dly$1270[0:0]$2287 \wr_pick_dly$1270$next + sync posedge \coresync_clk + update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2287 + end + attribute \src "libresoc.v:42878.3-42879.51" + process $proc$libresoc.v:42878$2288 + assign { } { } + assign $0\wr_pick_dly$1250[0:0]$2289 \wr_pick_dly$1250$next + sync posedge \coresync_clk + update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2289 + end + attribute \src "libresoc.v:42880.3-42881.51" + process $proc$libresoc.v:42880$2290 + assign { } { } + assign $0\wr_pick_dly$1222[0:0]$2291 \wr_pick_dly$1222$next + sync posedge \coresync_clk + update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2291 + end + attribute \src "libresoc.v:42882.3-42883.51" + process $proc$libresoc.v:42882$2292 + assign { } { } + assign $0\wr_pick_dly$1148[0:0]$2293 \wr_pick_dly$1148$next + sync posedge \coresync_clk + update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2293 + end + attribute \src "libresoc.v:42884.3-42885.51" + process $proc$libresoc.v:42884$2294 + assign { } { } + assign $0\wr_pick_dly$1130[0:0]$2295 \wr_pick_dly$1130$next + sync posedge \coresync_clk + update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2295 + end + attribute \src "libresoc.v:42886.3-42887.51" + process $proc$libresoc.v:42886$2296 + assign { } { } + assign $0\wr_pick_dly$1111[0:0]$2297 \wr_pick_dly$1111$next + sync posedge \coresync_clk + update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2297 + end + attribute \src "libresoc.v:42888.3-42889.51" + process $proc$libresoc.v:42888$2298 + assign { } { } + assign $0\wr_pick_dly$1091[0:0]$2299 \wr_pick_dly$1091$next + sync posedge \coresync_clk + update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2299 + end + attribute \src "libresoc.v:42890.3-42891.51" + process $proc$libresoc.v:42890$2300 + assign { } { } + assign $0\wr_pick_dly$1071[0:0]$2301 \wr_pick_dly$1071$next + sync posedge \coresync_clk + update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2301 + end + attribute \src "libresoc.v:42892.3-42893.51" + process $proc$libresoc.v:42892$2302 + assign { } { } + assign $0\wr_pick_dly$1049[0:0]$2303 \wr_pick_dly$1049$next + sync posedge \coresync_clk + update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2303 + end + attribute \src "libresoc.v:42894.3-42895.51" + process $proc$libresoc.v:42894$2304 + assign { } { } + assign $0\wr_pick_dly$1031[0:0]$2305 \wr_pick_dly$1031$next + sync posedge \coresync_clk + update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2305 + end + attribute \src "libresoc.v:42896.3-42897.51" + process $proc$libresoc.v:42896$2306 + assign { } { } + assign $0\wr_pick_dly$1010[0:0]$2307 \wr_pick_dly$1010$next + sync posedge \coresync_clk + update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2307 + end + attribute \src "libresoc.v:42898.3-42899.49" + process $proc$libresoc.v:42898$2308 + assign { } { } + assign $0\wr_pick_dly$991[0:0]$2309 \wr_pick_dly$991$next + sync posedge \coresync_clk + update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$2309 + end + attribute \src "libresoc.v:42900.3-42901.39" + process $proc$libresoc.v:42900$2310 + assign { } { } + assign $0\wr_pick_dly[0:0] \wr_pick_dly$next + sync posedge \coresync_clk + update \wr_pick_dly $0\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:42902.3-42903.53" + process $proc$libresoc.v:42902$2311 + assign { } { } + assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next + sync posedge \coresync_clk + update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:42904.3-42905.59" + process $proc$libresoc.v:42904$2312 + assign { } { } + assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:42906.3-42907.63" + process $proc$libresoc.v:42906$2313 + assign { } { } + assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:42908.3-42909.57" + process $proc$libresoc.v:42908$2314 + assign { } { } + assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next + sync posedge \coresync_clk + update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:42910.3-42911.59" + process $proc$libresoc.v:42910$2315 + assign { } { } + assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:42912.3-42913.63" + process $proc$libresoc.v:42912$2316 + assign { } { } + assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:42914.3-42915.49" + process $proc$libresoc.v:42914$2317 + assign { } { } + assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:42916.3-42917.49" + process $proc$libresoc.v:42916$2318 + assign { } { } + assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:42918.3-42919.57" + process $proc$libresoc.v:42918$2319 + assign { } { } + assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next + sync posedge \coresync_clk + update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:42920.3-42921.49" + process $proc$libresoc.v:42920$2320 + assign { } { } + assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:42922.3-42923.55" + process $proc$libresoc.v:42922$2321 + assign { } { } + assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:42924.3-42925.57" + process $proc$libresoc.v:42924$2322 + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:42926.3-42927.67" + process $proc$libresoc.v:42926$2323 + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:42928.3-42929.57" + process $proc$libresoc.v:42928$2324 + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:42930.3-42931.57" + process $proc$libresoc.v:42930$2325 + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:42932.3-42933.67" + process $proc$libresoc.v:42932$2326 + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next + sync posedge \coresync_clk + update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:42934.3-42935.57" + process $proc$libresoc.v:42934$2327 + assign { } { } + assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next + sync posedge \coresync_clk + update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:42936.3-42937.57" + process $proc$libresoc.v:42936$2328 + assign { } { } + assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next + sync posedge \coresync_clk + update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:42938.3-42939.57" + process $proc$libresoc.v:42938$2329 + assign { } { } + assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:42940.3-42941.65" + process $proc$libresoc.v:42940$2330 + assign { } { } + assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:42942.3-42943.57" + process $proc$libresoc.v:42942$2331 + assign { } { } + assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:42944.3-42945.51" + process $proc$libresoc.v:42944$2332 + assign { } { } + assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next + sync posedge \coresync_clk + update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:42946.3-42947.59" + process $proc$libresoc.v:42946$2333 + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next + sync posedge \coresync_clk + update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:42948.3-42949.51" + process $proc$libresoc.v:42948$2334 + assign { } { } + assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next + sync posedge \coresync_clk + update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:42950.3-42951.59" + process $proc$libresoc.v:42950$2335 + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next + sync posedge \coresync_clk + update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:42952.3-42953.49" + process $proc$libresoc.v:42952$2336 + assign { } { } + assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next + sync posedge \coresync_clk + update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:42954.3-42955.49" + process $proc$libresoc.v:42954$2337 + assign { } { } + assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next + sync posedge \coresync_clk + update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:42956.3-42957.57" + process $proc$libresoc.v:42956$2338 + assign { } { } + assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:42958.3-42959.51" + process $proc$libresoc.v:42958$2339 + assign { } { } + assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:42960.3-42961.47" + process $proc$libresoc.v:42960$2340 + assign { } { } + assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:42962.3-42963.49" + process $proc$libresoc.v:42962$2341 + assign { } { } + assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:42964.3-42965.51" + process $proc$libresoc.v:42964$2342 + assign { } { } + assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next + sync posedge \coresync_clk + update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:42966.3-42967.59" + process $proc$libresoc.v:42966$2343 + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next + sync posedge \coresync_clk + update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:42968.3-42969.49" + process $proc$libresoc.v:42968$2344 + assign { } { } + assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next + sync posedge \coresync_clk + update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:42970.3-42971.49" + process $proc$libresoc.v:42970$2345 + assign { } { } + assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next + sync posedge \coresync_clk + update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:42972.3-42973.49" + process $proc$libresoc.v:42972$2346 + assign { } { } + assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next + sync posedge \coresync_clk + update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:42974.3-42975.57" + process $proc$libresoc.v:42974$2347 + assign { } { } + assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:42976.3-42977.51" + process $proc$libresoc.v:42976$2348 + assign { } { } + assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:42978.3-42979.47" + process $proc$libresoc.v:42978$2349 + assign { } { } + assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:42980.3-42981.49" + process $proc$libresoc.v:42980$2350 + assign { } { } + assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:42982.3-42983.49" + process $proc$libresoc.v:42982$2351 + assign { } { } + assign $0\core_terminate_o[0:0] \core_terminate_o$next + sync posedge \coresync_clk + update \core_terminate_o $0\core_terminate_o[0:0] + end + attribute \src "libresoc.v:42984.3-42985.31" + process $proc$libresoc.v:42984$2352 + assign { } { } + assign $0\counter[1:0] \counter$next + sync posedge \coresync_clk + update \counter $0\counter[1:0] + end + attribute \src "libresoc.v:43723.3-43751.6" + process $proc$libresoc.v:43723$2353 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:43724.5-43724.29" + switch \initial + attribute \src "libresoc.v:43724.9-43724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry + case + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] + end + attribute \src "libresoc.v:43752.3-43780.6" + process $proc$libresoc.v:43752$2354 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43753.5-43753.29" + switch \initial + attribute \src "libresoc.v:43753.9-43753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit + case + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "libresoc.v:43781.3-43809.6" + process $proc$libresoc.v:43781$2355 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:43782.5-43782.29" + switch \initial + attribute \src "libresoc.v:43782.9-43782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] + end + attribute \src "libresoc.v:43810.3-43838.6" + process $proc$libresoc.v:43810$2356 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:43811.5-43811.29" + switch \initial + attribute \src "libresoc.v:43811.9-43811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "libresoc.v:43839.3-43867.6" + process $proc$libresoc.v:43839$2357 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:43840.5-43840.29" + switch \initial + attribute \src "libresoc.v:43840.9-43840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] + end + attribute \src "libresoc.v:43868.3-43896.6" + process $proc$libresoc.v:43868$2358 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 + attribute \src "libresoc.v:43869.5-43869.29" + switch \initial + attribute \src "libresoc.v:43869.9-43869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$22[0:0]$2362 \issue_i + case + assign $3\fus_cu_issue_i$22[0:0]$2362 1'0 + end + end + case + assign $1\fus_cu_issue_i$22[0:0]$2360 1'0 + end + sync always + update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 + end + attribute \src "libresoc.v:43897.3-43925.6" + process $proc$libresoc.v:43897$2363 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 + attribute \src "libresoc.v:43898.5-43898.29" + switch \initial + attribute \src "libresoc.v:43898.9-43898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 \$256 + case + assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 3'000 + end + sync always + update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 + end + attribute \src "libresoc.v:43926.3-43954.6" + process $proc$libresoc.v:43926$2368 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43927.5-43927.29" + switch \initial + attribute \src "libresoc.v:43927.9-43927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type + case + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] + end + attribute \src "libresoc.v:43955.3-43983.6" + process $proc$libresoc.v:43955$2369 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43956.5-43956.29" + switch \initial + attribute \src "libresoc.v:43956.9-43956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] \dec_SPR_SPR__fn_unit + case + assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] + end + attribute \src "libresoc.v:43984.3-44012.6" + process $proc$libresoc.v:43984$2370 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43985.5-43985.29" + switch \initial + attribute \src "libresoc.v:43985.9-43985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + attribute \src "libresoc.v:44013.3-44041.6" + process $proc$libresoc.v:44013$2371 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:44014.5-44014.29" + switch \initial + attribute \src "libresoc.v:44014.9-44014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "libresoc.v:44042.3-44070.6" + process $proc$libresoc.v:44042$2372 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 + attribute \src "libresoc.v:44043.5-44043.29" + switch \initial + attribute \src "libresoc.v:44043.9-44043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$25[0:0]$2376 \issue_i + case + assign $3\fus_cu_issue_i$25[0:0]$2376 1'0 + end + end + case + assign $1\fus_cu_issue_i$25[0:0]$2374 1'0 + end + sync always + update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 + end + attribute \src "libresoc.v:44071.3-44099.6" + process $proc$libresoc.v:44071$2377 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 + attribute \src "libresoc.v:44072.5-44072.29" + switch \initial + attribute \src "libresoc.v:44072.9-44072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 \$270 + case + assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 + end + attribute \src "libresoc.v:44100.3-44128.6" + process $proc$libresoc.v:44100$2382 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:44101.5-44101.29" + switch \initial + attribute \src "libresoc.v:44101.9-44101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV__insn_type + case + assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] + end + attribute \src "libresoc.v:44129.3-44157.6" + process $proc$libresoc.v:44129$2383 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44130.5-44130.29" + switch \initial + attribute \src "libresoc.v:44130.9-44130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__fn_unit[13:0] \dec_DIV_DIV__fn_unit + case + assign $3\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] + end + attribute \src "libresoc.v:44158.3-44187.6" + process $proc$libresoc.v:44158$2384 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:44159.5-44159.29" + switch \initial + attribute \src "libresoc.v:44159.9-44159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV__imm_data__ok \dec_DIV_DIV__imm_data__data } + case + assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] + update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44188.3-44217.6" + process $proc$libresoc.v:44188$2385 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] + assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:44189.5-44189.29" + switch \initial + attribute \src "libresoc.v:44189.9-44189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV__rc__ok \dec_DIV_DIV__rc__rc } + case + assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] + update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] + end + attribute \src "libresoc.v:44218.3-44247.6" + process $proc$libresoc.v:44218$2386 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] + assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:44219.5-44219.29" + switch \initial + attribute \src "libresoc.v:44219.9-44219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV__oe__ok \dec_DIV_DIV__oe__oe } + case + assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] + update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] + end + attribute \src "libresoc.v:44248.3-44276.6" + process $proc$libresoc.v:44248$2387 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:44249.5-44249.29" + switch \initial + attribute \src "libresoc.v:44249.9-44249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV__invert_in + case + assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] + end + attribute \src "libresoc.v:44277.3-44305.6" + process $proc$libresoc.v:44277$2388 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:44278.5-44278.29" + switch \initial + attribute \src "libresoc.v:44278.9-44278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV__zero_a + case + assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] + end + attribute \src "libresoc.v:44306.3-44334.6" + process $proc$libresoc.v:44306$2389 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:44307.5-44307.29" + switch \initial + attribute \src "libresoc.v:44307.9-44307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV__input_carry + case + assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] + end + attribute \src "libresoc.v:44335.3-44363.6" + process $proc$libresoc.v:44335$2390 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:44336.5-44336.29" + switch \initial + attribute \src "libresoc.v:44336.9-44336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV__invert_out + case + assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] + end + attribute \src "libresoc.v:44364.3-44392.6" + process $proc$libresoc.v:44364$2391 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:44365.5-44365.29" + switch \initial + attribute \src "libresoc.v:44365.9-44365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV__write_cr0 + case + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] + end + attribute \src "libresoc.v:44393.3-44421.6" + process $proc$libresoc.v:44393$2392 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:44394.5-44394.29" + switch \initial + attribute \src "libresoc.v:44394.9-44394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV__output_carry + case + assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] + end + attribute \src "libresoc.v:44422.3-44450.6" + process $proc$libresoc.v:44422$2393 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:44423.5-44423.29" + switch \initial + attribute \src "libresoc.v:44423.9-44423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV__is_32bit + case + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] + end + attribute \src "libresoc.v:44451.3-44479.6" + process $proc$libresoc.v:44451$2394 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:44452.5-44452.29" + switch \initial + attribute \src "libresoc.v:44452.9-44452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV__is_signed + case + assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] + end + attribute \src "libresoc.v:44480.3-44508.6" + process $proc$libresoc.v:44480$2395 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:44481.5-44481.29" + switch \initial + attribute \src "libresoc.v:44481.9-44481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV__data_len + case + assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] + end + attribute \src "libresoc.v:44509.3-44537.6" + process $proc$libresoc.v:44509$2396 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:44510.5-44510.29" + switch \initial + attribute \src "libresoc.v:44510.9-44510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV__insn + case + assign $3\fus_oper_i_alu_div0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_div0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] + end + attribute \src "libresoc.v:44538.3-44566.6" + process $proc$libresoc.v:44538$2397 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 + attribute \src "libresoc.v:44539.5-44539.29" + switch \initial + attribute \src "libresoc.v:44539.9-44539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$28[0:0]$2401 \issue_i + case + assign $3\fus_cu_issue_i$28[0:0]$2401 1'0 + end + end + case + assign $1\fus_cu_issue_i$28[0:0]$2399 1'0 + end + sync always + update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 + end + attribute \src "libresoc.v:44567.3-44595.6" + process $proc$libresoc.v:44567$2402 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 + attribute \src "libresoc.v:44568.5-44568.29" + switch \initial + attribute \src "libresoc.v:44568.9-44568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 \$300 + case + assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 3'000 + end + sync always + update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 + end + attribute \src "libresoc.v:44596.3-44624.6" + process $proc$libresoc.v:44596$2407 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44597.5-44597.29" + switch \initial + attribute \src "libresoc.v:44597.9-44597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL__insn_type + case + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] + end + attribute \src "libresoc.v:44625.3-44653.6" + process $proc$libresoc.v:44625$2408 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44626.5-44626.29" + switch \initial + attribute \src "libresoc.v:44626.9-44626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] \dec_MUL_MUL__fn_unit + case + assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] + end + attribute \src "libresoc.v:44654.3-44683.6" + process $proc$libresoc.v:44654$2409 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44655.5-44655.29" + switch \initial + attribute \src "libresoc.v:44655.9-44655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL__imm_data__ok \dec_MUL_MUL__imm_data__data } + case + assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44684.3-44713.6" + process $proc$libresoc.v:44684$2410 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44685.5-44685.29" + switch \initial + attribute \src "libresoc.v:44685.9-44685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL__rc__ok \dec_MUL_MUL__rc__rc } + case + assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] + update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] + end + attribute \src "libresoc.v:44714.3-44743.6" + process $proc$libresoc.v:44714$2411 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44715.5-44715.29" + switch \initial + attribute \src "libresoc.v:44715.9-44715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL__oe__ok \dec_MUL_MUL__oe__oe } + case + assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] + update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] + end + attribute \src "libresoc.v:44744.3-44772.6" + process $proc$libresoc.v:44744$2412 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44745.5-44745.29" + switch \initial + attribute \src "libresoc.v:44745.9-44745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL__write_cr0 + case + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] + end + attribute \src "libresoc.v:44773.3-44801.6" + process $proc$libresoc.v:44773$2413 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44774.5-44774.29" + switch \initial + attribute \src "libresoc.v:44774.9-44774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL__is_32bit + case + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] + end + attribute \src "libresoc.v:44802.3-44830.6" + process $proc$libresoc.v:44802$2414 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44803.5-44803.29" + switch \initial + attribute \src "libresoc.v:44803.9-44803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL__is_signed + case + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] + end + attribute \src "libresoc.v:44831.3-44859.6" + process $proc$libresoc.v:44831$2415 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44832.5-44832.29" + switch \initial + attribute \src "libresoc.v:44832.9-44832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL__insn + case + assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] + end + attribute \src "libresoc.v:44860.3-44888.6" + process $proc$libresoc.v:44860$2416 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 + attribute \src "libresoc.v:44861.5-44861.29" + switch \initial + attribute \src "libresoc.v:44861.9-44861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$31[0:0]$2420 \issue_i + case + assign $3\fus_cu_issue_i$31[0:0]$2420 1'0 + end + end + case + assign $1\fus_cu_issue_i$31[0:0]$2418 1'0 + end + sync always + update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 + end + attribute \src "libresoc.v:44889.3-44917.6" + process $proc$libresoc.v:44889$2421 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 + attribute \src "libresoc.v:44890.5-44890.29" + switch \initial + attribute \src "libresoc.v:44890.9-44890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 \$314 + case + assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 3'000 + end + sync always + update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 + end + attribute \src "libresoc.v:44918.3-44946.6" + process $proc$libresoc.v:44918$2426 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44919.5-44919.29" + switch \initial + attribute \src "libresoc.v:44919.9-44919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT__insn_type + case + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + end + attribute \src "libresoc.v:44947.3-44975.6" + process $proc$libresoc.v:44947$2427 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44948.5-44948.29" + switch \initial + attribute \src "libresoc.v:44948.9-44948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + case + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + end + attribute \src "libresoc.v:44976.3-45005.6" + process $proc$libresoc.v:44976$2428 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44977.5-44977.29" + switch \initial + attribute \src "libresoc.v:44977.9-44977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data } + case + assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:45006.3-45035.6" + process $proc$libresoc.v:45006$2429 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:45007.5-45007.29" + switch \initial + attribute \src "libresoc.v:45007.9-45007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__rc } + case + assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + end + attribute \src "libresoc.v:45036.3-45065.6" + process $proc$libresoc.v:45036$2430 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:45037.5-45037.29" + switch \initial + attribute \src "libresoc.v:45037.9-45037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__oe } + case + assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + end + attribute \src "libresoc.v:45066.3-45094.6" + process $proc$libresoc.v:45066$2431 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:45067.5-45067.29" + switch \initial + attribute \src "libresoc.v:45067.9-45067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + case + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + end + attribute \src "libresoc.v:45095.3-45123.6" + process $proc$libresoc.v:45095$2432 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:45096.5-45096.29" + switch \initial + attribute \src "libresoc.v:45096.9-45096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] \dec_SHIFT_ROT_SHIFT_ROT__invert_in + case + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + end + attribute \src "libresoc.v:45124.3-45152.6" + process $proc$libresoc.v:45124$2433 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:45125.5-45125.29" + switch \initial + attribute \src "libresoc.v:45125.9-45125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT__input_carry + case + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + end + attribute \src "libresoc.v:45153.3-45181.6" + process $proc$libresoc.v:45153$2434 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:45154.5-45154.29" + switch \initial + attribute \src "libresoc.v:45154.9-45154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_carry + case + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + end + attribute \src "libresoc.v:45182.3-45210.6" + process $proc$libresoc.v:45182$2435 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:45183.5-45183.29" + switch \initial + attribute \src "libresoc.v:45183.9-45183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__input_cr + case + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + end + attribute \src "libresoc.v:45211.3-45239.6" + process $proc$libresoc.v:45211$2436 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:45212.5-45212.29" + switch \initial + attribute \src "libresoc.v:45212.9-45212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_cr + case + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + end + attribute \src "libresoc.v:45240.3-45268.6" + process $proc$libresoc.v:45240$2437 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:45241.5-45241.29" + switch \initial + attribute \src "libresoc.v:45241.9-45241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + case + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + end + attribute \src "libresoc.v:45269.3-45297.6" + process $proc$libresoc.v:45269$2438 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:45270.5-45270.29" + switch \initial + attribute \src "libresoc.v:45270.9-45270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_signed + case + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + end + attribute \src "libresoc.v:45298.3-45326.6" + process $proc$libresoc.v:45298$2439 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:45299.5-45299.29" + switch \initial + attribute \src "libresoc.v:45299.9-45299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT__insn + case + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] + end + attribute \src "libresoc.v:45327.3-45355.6" + process $proc$libresoc.v:45327$2440 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 + attribute \src "libresoc.v:45328.5-45328.29" + switch \initial + attribute \src "libresoc.v:45328.9-45328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$34[0:0]$2444 \issue_i + case + assign $3\fus_cu_issue_i$34[0:0]$2444 1'0 + end + end + case + assign $1\fus_cu_issue_i$34[0:0]$2442 1'0 + end + sync always + update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 + end + attribute \src "libresoc.v:45356.3-45384.6" + process $proc$libresoc.v:45356$2445 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 + attribute \src "libresoc.v:45357.5-45357.29" + switch \initial + attribute \src "libresoc.v:45357.9-45357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 \$328 + case + assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 5'00000 + end + end + case + assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 5'00000 + end + sync always + update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 + end + attribute \src "libresoc.v:45385.3-45413.6" + process $proc$libresoc.v:45385$2450 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45386.5-45386.29" + switch \initial + attribute \src "libresoc.v:45386.9-45386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST__insn_type + case + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + end + attribute \src "libresoc.v:45414.3-45442.6" + process $proc$libresoc.v:45414$2451 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45415.5-45415.29" + switch \initial + attribute \src "libresoc.v:45415.9-45415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] \dec_LDST_LDST__fn_unit + case + assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] + end + attribute \src "libresoc.v:45443.3-45472.6" + process $proc$libresoc.v:45443$2452 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45444.5-45444.29" + switch \initial + attribute \src "libresoc.v:45444.9-45444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST__imm_data__ok \dec_LDST_LDST__imm_data__data } + case + assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:45473.3-45501.6" + process $proc$libresoc.v:45473$2453 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45474.5-45474.29" + switch \initial + attribute \src "libresoc.v:45474.9-45474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST__zero_a + case + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + end + attribute \src "libresoc.v:45502.3-45531.6" + process $proc$libresoc.v:45502$2454 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45503.5-45503.29" + switch \initial + attribute \src "libresoc.v:45503.9-45503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST__rc__ok \dec_LDST_LDST__rc__rc } + case + assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + end + attribute \src "libresoc.v:45532.3-45561.6" + process $proc$libresoc.v:45532$2455 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:45533.5-45533.29" + switch \initial + attribute \src "libresoc.v:45533.9-45533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST__oe__ok \dec_LDST_LDST__oe__oe } + case + assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + end + attribute \src "libresoc.v:45562.3-45590.6" + process $proc$libresoc.v:45562$2456 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45563.5-45563.29" + switch \initial + attribute \src "libresoc.v:45563.9-45563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST__is_32bit + case + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + end + attribute \src "libresoc.v:45591.3-45619.6" + process $proc$libresoc.v:45591$2457 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45592.5-45592.29" + switch \initial + attribute \src "libresoc.v:45592.9-45592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST__is_signed + case + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + end + attribute \src "libresoc.v:45620.3-45648.6" + process $proc$libresoc.v:45620$2458 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:45621.5-45621.29" + switch \initial + attribute \src "libresoc.v:45621.9-45621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST__data_len + case + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] + end + attribute \src "libresoc.v:45649.3-45677.6" + process $proc$libresoc.v:45649$2459 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45650.5-45650.29" + switch \initial + attribute \src "libresoc.v:45650.9-45650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST__byte_reverse + case + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + end + attribute \src "libresoc.v:45678.3-45706.6" + process $proc$libresoc.v:45678$2460 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:45679.5-45679.29" + switch \initial + attribute \src "libresoc.v:45679.9-45679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST__sign_extend + case + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + end + attribute \src "libresoc.v:45707.3-45735.6" + process $proc$libresoc.v:45707$2461 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:45708.5-45708.29" + switch \initial + attribute \src "libresoc.v:45708.9-45708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST__ldst_mode + case + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + sync always + update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + end + attribute \src "libresoc.v:45736.3-45764.6" + process $proc$libresoc.v:45736$2462 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:45737.5-45737.29" + switch \initial + attribute \src "libresoc.v:45737.9-45737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST__insn + case + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + sync always + update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] + end + attribute \src "libresoc.v:45765.3-45793.6" + process $proc$libresoc.v:45765$2463 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 + attribute \src "libresoc.v:45766.5-45766.29" + switch \initial + attribute \src "libresoc.v:45766.9-45766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$37[0:0]$2467 \issue_i + case + assign $3\fus_cu_issue_i$37[0:0]$2467 1'0 + end + end + case + assign $1\fus_cu_issue_i$37[0:0]$2465 1'0 + end + sync always + update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 + end + attribute \src "libresoc.v:45794.3-45822.6" + process $proc$libresoc.v:45794$2468 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 + attribute \src "libresoc.v:45795.5-45795.29" + switch \initial + attribute \src "libresoc.v:45795.9-45795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 \$350 + case + assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 3'000 + end + sync always + update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 + end + attribute \src "libresoc.v:45823.3-45831.6" + process $proc$libresoc.v:45823$2473 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_alu0_0$next[0:0]$2474 $1\dp_INT_ra_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:45824.5-45824.29" + switch \initial + attribute \src "libresoc.v:45824.9-45824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 1'0 + case + assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 \rp_INT_ra_alu0_0 + end + sync always + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2474 + end + attribute \src "libresoc.v:45832.3-45841.6" + process $proc$libresoc.v:45832$2476 + assign { } { } + assign { } { } + assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] + attribute \src "libresoc.v:45833.5-45833.29" + switch \initial + attribute \src "libresoc.v:45833.9-45833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i[63:0] \int_src1__data_o + case + assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i $0\fus_src1_i[63:0] + end + attribute \src "libresoc.v:45842.3-45850.6" + process $proc$libresoc.v:45842$2477 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_cr0_1$next[0:0]$2478 $1\dp_INT_ra_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:45843.5-45843.29" + switch \initial + attribute \src "libresoc.v:45843.9-45843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 1'0 + case + assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 \rp_INT_ra_cr0_1 + end + sync always + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2478 + end + attribute \src "libresoc.v:45851.3-45860.6" + process $proc$libresoc.v:45851$2480 + assign { } { } + assign { } { } + assign $0\fus_src1_i$42[63:0]$2481 $1\fus_src1_i$42[63:0]$2482 + attribute \src "libresoc.v:45852.5-45852.29" + switch \initial + attribute \src "libresoc.v:45852.9-45852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$42[63:0]$2482 \int_src1__data_o + case + assign $1\fus_src1_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2481 + end + attribute \src "libresoc.v:45861.3-45869.6" + process $proc$libresoc.v:45861$2483 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_trap0_2$next[0:0]$2484 $1\dp_INT_ra_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:45862.5-45862.29" + switch \initial + attribute \src "libresoc.v:45862.9-45862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 1'0 + case + assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 \rp_INT_ra_trap0_2 + end + sync always + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2484 + end + attribute \src "libresoc.v:45870.3-45879.6" + process $proc$libresoc.v:45870$2486 + assign { } { } + assign { } { } + assign $0\fus_src1_i$45[63:0]$2487 $1\fus_src1_i$45[63:0]$2488 + attribute \src "libresoc.v:45871.5-45871.29" + switch \initial + attribute \src "libresoc.v:45871.9-45871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$45[63:0]$2488 \int_src1__data_o + case + assign $1\fus_src1_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2487 + end + attribute \src "libresoc.v:45880.3-45888.6" + process $proc$libresoc.v:45880$2489 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_logical0_3$next[0:0]$2490 $1\dp_INT_ra_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:45881.5-45881.29" + switch \initial + attribute \src "libresoc.v:45881.9-45881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 1'0 + case + assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 \rp_INT_ra_logical0_3 + end + sync always + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2490 + end + attribute \src "libresoc.v:45889.3-45898.6" + process $proc$libresoc.v:45889$2492 + assign { } { } + assign { } { } + assign $0\fus_src1_i$48[63:0]$2493 $1\fus_src1_i$48[63:0]$2494 + attribute \src "libresoc.v:45890.5-45890.29" + switch \initial + attribute \src "libresoc.v:45890.9-45890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$48[63:0]$2494 \int_src1__data_o + case + assign $1\fus_src1_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2493 + end + attribute \src "libresoc.v:45899.3-45907.6" + process $proc$libresoc.v:45899$2495 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_spr0_4$next[0:0]$2496 $1\dp_INT_ra_spr0_4$next[0:0]$2497 + attribute \src "libresoc.v:45900.5-45900.29" + switch \initial + attribute \src "libresoc.v:45900.9-45900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 1'0 + case + assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 \rp_INT_ra_spr0_4 + end + sync always + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2496 + end + attribute \src "libresoc.v:45908.3-45917.6" + process $proc$libresoc.v:45908$2498 + assign { } { } + assign { } { } + assign $0\fus_src1_i$51[63:0]$2499 $1\fus_src1_i$51[63:0]$2500 + attribute \src "libresoc.v:45909.5-45909.29" + switch \initial + attribute \src "libresoc.v:45909.9-45909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_spr0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$51[63:0]$2500 \int_src1__data_o + case + assign $1\fus_src1_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2499 + end + attribute \src "libresoc.v:45918.3-45926.6" + process $proc$libresoc.v:45918$2501 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_div0_5$next[0:0]$2502 $1\dp_INT_ra_div0_5$next[0:0]$2503 + attribute \src "libresoc.v:45919.5-45919.29" + switch \initial + attribute \src "libresoc.v:45919.9-45919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_div0_5$next[0:0]$2503 1'0 + case + assign $1\dp_INT_ra_div0_5$next[0:0]$2503 \rp_INT_ra_div0_5 + end + sync always + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2502 + end + attribute \src "libresoc.v:45927.3-45936.6" + process $proc$libresoc.v:45927$2504 + assign { } { } + assign { } { } + assign $0\fus_src1_i$54[63:0]$2505 $1\fus_src1_i$54[63:0]$2506 + attribute \src "libresoc.v:45928.5-45928.29" + switch \initial + attribute \src "libresoc.v:45928.9-45928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_div0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$54[63:0]$2506 \int_src1__data_o + case + assign $1\fus_src1_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2505 + end + attribute \src "libresoc.v:45937.3-45945.6" + process $proc$libresoc.v:45937$2507 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_mul0_6$next[0:0]$2508 $1\dp_INT_ra_mul0_6$next[0:0]$2509 + attribute \src "libresoc.v:45938.5-45938.29" + switch \initial + attribute \src "libresoc.v:45938.9-45938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 1'0 + case + assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 \rp_INT_ra_mul0_6 + end + sync always + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2508 + end + attribute \src "libresoc.v:45946.3-45955.6" + process $proc$libresoc.v:45946$2510 + assign { } { } + assign { } { } + assign $0\fus_src1_i$57[63:0]$2511 $1\fus_src1_i$57[63:0]$2512 + attribute \src "libresoc.v:45947.5-45947.29" + switch \initial + attribute \src "libresoc.v:45947.9-45947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_mul0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$57[63:0]$2512 \int_src1__data_o + case + assign $1\fus_src1_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2511 + end + attribute \src "libresoc.v:45956.3-45964.6" + process $proc$libresoc.v:45956$2513 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 + attribute \src "libresoc.v:45957.5-45957.29" + switch \initial + attribute \src "libresoc.v:45957.9-45957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 1'0 + case + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 \rp_INT_ra_shiftrot0_7 + end + sync always + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 + end + attribute \src "libresoc.v:45965.3-45974.6" + process $proc$libresoc.v:45965$2516 + assign { } { } + assign { } { } + assign $0\fus_src1_i$60[63:0]$2517 $1\fus_src1_i$60[63:0]$2518 + attribute \src "libresoc.v:45966.5-45966.29" + switch \initial + attribute \src "libresoc.v:45966.9-45966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_shiftrot0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$60[63:0]$2518 \int_src1__data_o + case + assign $1\fus_src1_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2517 + end + attribute \src "libresoc.v:45975.3-45983.6" + process $proc$libresoc.v:45975$2519 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2520 $1\dp_INT_ra_ldst0_8$next[0:0]$2521 + attribute \src "libresoc.v:45976.5-45976.29" + switch \initial + attribute \src "libresoc.v:45976.9-45976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 1'0 + case + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 \rp_INT_ra_ldst0_8 + end + sync always + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2520 + end + attribute \src "libresoc.v:45984.3-45993.6" + process $proc$libresoc.v:45984$2522 + assign { } { } + assign { } { } + assign $0\fus_src1_i$63[63:0]$2523 $1\fus_src1_i$63[63:0]$2524 + attribute \src "libresoc.v:45985.5-45985.29" + switch \initial + attribute \src "libresoc.v:45985.9-45985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_ra_ldst0_8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$63[63:0]$2524 \int_src1__data_o + case + assign $1\fus_src1_i$63[63:0]$2524 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2523 + end + attribute \src "libresoc.v:45994.3-46002.6" + process $proc$libresoc.v:45994$2525 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_alu0_0$next[0:0]$2526 $1\dp_INT_rb_alu0_0$next[0:0]$2527 + attribute \src "libresoc.v:45995.5-45995.29" + switch \initial + attribute \src "libresoc.v:45995.9-45995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 1'0 + case + assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 \rp_INT_rb_alu0_0 + end + sync always + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2526 + end + attribute \src "libresoc.v:46003.3-46012.6" + process $proc$libresoc.v:46003$2528 + assign { } { } + assign { } { } + assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] + attribute \src "libresoc.v:46004.5-46004.29" + switch \initial + attribute \src "libresoc.v:46004.9-46004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i[63:0] \int_src2__data_o + case + assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i $0\fus_src2_i[63:0] + end + attribute \src "libresoc.v:46013.3-46021.6" + process $proc$libresoc.v:46013$2529 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_cr0_1$next[0:0]$2530 $1\dp_INT_rb_cr0_1$next[0:0]$2531 + attribute \src "libresoc.v:46014.5-46014.29" + switch \initial + attribute \src "libresoc.v:46014.9-46014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 1'0 + case + assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 \rp_INT_rb_cr0_1 + end + sync always + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2530 + end + attribute \src "libresoc.v:46022.3-46031.6" + process $proc$libresoc.v:46022$2532 + assign { } { } + assign { } { } + assign $0\fus_src2_i$64[63:0]$2533 $1\fus_src2_i$64[63:0]$2534 + attribute \src "libresoc.v:46023.5-46023.29" + switch \initial + attribute \src "libresoc.v:46023.9-46023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$64[63:0]$2534 \int_src2__data_o + case + assign $1\fus_src2_i$64[63:0]$2534 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2533 + end + attribute \src "libresoc.v:46032.3-46040.6" + process $proc$libresoc.v:46032$2535 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_trap0_2$next[0:0]$2536 $1\dp_INT_rb_trap0_2$next[0:0]$2537 + attribute \src "libresoc.v:46033.5-46033.29" + switch \initial + attribute \src "libresoc.v:46033.9-46033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 1'0 + case + assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 \rp_INT_rb_trap0_2 + end + sync always + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2536 + end + attribute \src "libresoc.v:46041.3-46050.6" + process $proc$libresoc.v:46041$2538 + assign { } { } + assign { } { } + assign $0\fus_src2_i$65[63:0]$2539 $1\fus_src2_i$65[63:0]$2540 + attribute \src "libresoc.v:46042.5-46042.29" + switch \initial + attribute \src "libresoc.v:46042.9-46042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$65[63:0]$2540 \int_src2__data_o + case + assign $1\fus_src2_i$65[63:0]$2540 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2539 + end + attribute \src "libresoc.v:46051.3-46059.6" + process $proc$libresoc.v:46051$2541 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_logical0_3$next[0:0]$2542 $1\dp_INT_rb_logical0_3$next[0:0]$2543 + attribute \src "libresoc.v:46052.5-46052.29" + switch \initial + attribute \src "libresoc.v:46052.9-46052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 1'0 + case + assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 \rp_INT_rb_logical0_3 + end + sync always + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2542 + end + attribute \src "libresoc.v:46060.3-46069.6" + process $proc$libresoc.v:46060$2544 + assign { } { } + assign { } { } + assign $0\fus_src2_i$66[63:0]$2545 $1\fus_src2_i$66[63:0]$2546 + attribute \src "libresoc.v:46061.5-46061.29" + switch \initial + attribute \src "libresoc.v:46061.9-46061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$66[63:0]$2546 \int_src2__data_o + case + assign $1\fus_src2_i$66[63:0]$2546 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2545 + end + attribute \src "libresoc.v:46070.3-46078.6" + process $proc$libresoc.v:46070$2547 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_div0_4$next[0:0]$2548 $1\dp_INT_rb_div0_4$next[0:0]$2549 + attribute \src "libresoc.v:46071.5-46071.29" + switch \initial + attribute \src "libresoc.v:46071.9-46071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_div0_4$next[0:0]$2549 1'0 + case + assign $1\dp_INT_rb_div0_4$next[0:0]$2549 \rp_INT_rb_div0_4 + end + sync always + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2548 + end + attribute \src "libresoc.v:46079.3-46088.6" + process $proc$libresoc.v:46079$2550 + assign { } { } + assign { } { } + assign $0\fus_src2_i$67[63:0]$2551 $1\fus_src2_i$67[63:0]$2552 + attribute \src "libresoc.v:46080.5-46080.29" + switch \initial + attribute \src "libresoc.v:46080.9-46080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_div0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$67[63:0]$2552 \int_src2__data_o + case + assign $1\fus_src2_i$67[63:0]$2552 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2551 + end + attribute \src "libresoc.v:46089.3-46097.6" + process $proc$libresoc.v:46089$2553 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_mul0_5$next[0:0]$2554 $1\dp_INT_rb_mul0_5$next[0:0]$2555 + attribute \src "libresoc.v:46090.5-46090.29" + switch \initial + attribute \src "libresoc.v:46090.9-46090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 1'0 + case + assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 \rp_INT_rb_mul0_5 + end + sync always + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2554 + end + attribute \src "libresoc.v:46098.3-46107.6" + process $proc$libresoc.v:46098$2556 + assign { } { } + assign { } { } + assign $0\fus_src2_i$68[63:0]$2557 $1\fus_src2_i$68[63:0]$2558 + attribute \src "libresoc.v:46099.5-46099.29" + switch \initial + attribute \src "libresoc.v:46099.9-46099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_mul0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$68[63:0]$2558 \int_src2__data_o + case + assign $1\fus_src2_i$68[63:0]$2558 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2557 + end + attribute \src "libresoc.v:46108.3-46116.6" + process $proc$libresoc.v:46108$2559 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 + attribute \src "libresoc.v:46109.5-46109.29" + switch \initial + attribute \src "libresoc.v:46109.9-46109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 1'0 + case + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 \rp_INT_rb_shiftrot0_6 + end + sync always + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 + end + attribute \src "libresoc.v:46117.3-46126.6" + process $proc$libresoc.v:46117$2562 + assign { } { } + assign { } { } + assign $0\fus_src2_i$69[63:0]$2563 $1\fus_src2_i$69[63:0]$2564 + attribute \src "libresoc.v:46118.5-46118.29" + switch \initial + attribute \src "libresoc.v:46118.9-46118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_shiftrot0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$69[63:0]$2564 \int_src2__data_o + case + assign $1\fus_src2_i$69[63:0]$2564 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2563 + end + attribute \src "libresoc.v:46127.3-46135.6" + process $proc$libresoc.v:46127$2565 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2566 $1\dp_INT_rb_ldst0_7$next[0:0]$2567 + attribute \src "libresoc.v:46128.5-46128.29" + switch \initial + attribute \src "libresoc.v:46128.9-46128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 1'0 + case + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 \rp_INT_rb_ldst0_7 + end + sync always + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2566 + end + attribute \src "libresoc.v:46136.3-46145.6" + process $proc$libresoc.v:46136$2568 + assign { } { } + assign { } { } + assign $0\fus_src2_i$70[63:0]$2569 $1\fus_src2_i$70[63:0]$2570 + attribute \src "libresoc.v:46137.5-46137.29" + switch \initial + attribute \src "libresoc.v:46137.9-46137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rb_ldst0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$70[63:0]$2570 \int_src2__data_o + case + assign $1\fus_src2_i$70[63:0]$2570 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2569 + end + attribute \src "libresoc.v:46146.3-46154.6" + process $proc$libresoc.v:46146$2571 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 + attribute \src "libresoc.v:46147.5-46147.29" + switch \initial + attribute \src "libresoc.v:46147.9-46147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 1'0 + case + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 \rp_INT_rc_shiftrot0_0 + end + sync always + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 + end + attribute \src "libresoc.v:46155.3-46164.6" + process $proc$libresoc.v:46155$2574 + assign { } { } + assign { } { } + assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] + attribute \src "libresoc.v:46156.5-46156.29" + switch \initial + attribute \src "libresoc.v:46156.9-46156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rc_shiftrot0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i[63:0] \int_src3__data_o + case + assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i $0\fus_src3_i[63:0] + end + attribute \src "libresoc.v:46165.3-46173.6" + process $proc$libresoc.v:46165$2575 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2576 $1\dp_INT_rc_ldst0_1$next[0:0]$2577 + attribute \src "libresoc.v:46166.5-46166.29" + switch \initial + attribute \src "libresoc.v:46166.9-46166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 1'0 + case + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 \rp_INT_rc_ldst0_1 + end + sync always + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2576 + end + attribute \src "libresoc.v:46174.3-46183.6" + process $proc$libresoc.v:46174$2578 + assign { } { } + assign { } { } + assign $0\fus_src3_i$71[63:0]$2579 $1\fus_src3_i$71[63:0]$2580 + attribute \src "libresoc.v:46175.5-46175.29" + switch \initial + attribute \src "libresoc.v:46175.9-46175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_INT_rc_ldst0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$71[63:0]$2580 \int_src3__data_o + case + assign $1\fus_src3_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2579 + end + attribute \src "libresoc.v:46184.3-46192.6" + process $proc$libresoc.v:46184$2581 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 + attribute \src "libresoc.v:46185.5-46185.29" + switch \initial + attribute \src "libresoc.v:46185.9-46185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 1'0 + case + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 \rp_XER_xer_so_alu0_0 + end + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 + end + attribute \src "libresoc.v:46193.3-46202.6" + process $proc$libresoc.v:46193$2584 + assign { } { } + assign { } { } + assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 + attribute \src "libresoc.v:46194.5-46194.29" + switch \initial + attribute \src "libresoc.v:46194.9-46194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$72[0:0]$2586 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$72[0:0]$2586 1'0 + end + sync always + update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 + end + attribute \src "libresoc.v:46203.3-46211.6" + process $proc$libresoc.v:46203$2587 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 + attribute \src "libresoc.v:46204.5-46204.29" + switch \initial + attribute \src "libresoc.v:46204.9-46204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 1'0 + case + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 \rp_XER_xer_so_logical0_1 + end + sync always + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 + end + attribute \src "libresoc.v:46212.3-46221.6" + process $proc$libresoc.v:46212$2590 + assign { } { } + assign { } { } + assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 + attribute \src "libresoc.v:46213.5-46213.29" + switch \initial + attribute \src "libresoc.v:46213.9-46213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_logical0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$73[0:0]$2592 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$73[0:0]$2592 1'0 + end + sync always + update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 + end + attribute \src "libresoc.v:46222.3-46230.6" + process $proc$libresoc.v:46222$2593 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 + attribute \src "libresoc.v:46223.5-46223.29" + switch \initial + attribute \src "libresoc.v:46223.9-46223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 1'0 + case + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 \rp_XER_xer_so_spr0_2 + end + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 + end + attribute \src "libresoc.v:46231.3-46240.6" + process $proc$libresoc.v:46231$2596 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:46232.5-46232.29" + switch \initial + attribute \src "libresoc.v:46232.9-46232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + case + assign $1\fus_src4_i[0:0] 1'0 + end + sync always + update \fus_src4_i $0\fus_src4_i[0:0] + end + attribute \src "libresoc.v:46241.3-46249.6" + process $proc$libresoc.v:46241$2597 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 + attribute \src "libresoc.v:46242.5-46242.29" + switch \initial + attribute \src "libresoc.v:46242.9-46242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 1'0 + case + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 \rp_XER_xer_so_div0_3 + end + sync always + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 + end + attribute \src "libresoc.v:46250.3-46259.6" + process $proc$libresoc.v:46250$2600 + assign { } { } + assign { } { } + assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 + attribute \src "libresoc.v:46251.5-46251.29" + switch \initial + attribute \src "libresoc.v:46251.9-46251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_div0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$74[0:0]$2602 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$74[0:0]$2602 1'0 + end + sync always + update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 + end + attribute \src "libresoc.v:46260.3-46268.6" + process $proc$libresoc.v:46260$2603 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:46261.5-46261.29" + switch \initial + attribute \src "libresoc.v:46261.9-46261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 1'0 + case + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 \rp_XER_xer_so_mul0_4 + end + sync always + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 + end + attribute \src "libresoc.v:46269.3-46278.6" + process $proc$libresoc.v:46269$2606 + assign { } { } + assign { } { } + assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 + attribute \src "libresoc.v:46270.5-46270.29" + switch \initial + attribute \src "libresoc.v:46270.9-46270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_mul0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$75[0:0]$2608 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$75[0:0]$2608 1'0 + end + sync always + update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 + end + attribute \src "libresoc.v:46279.3-46287.6" + process $proc$libresoc.v:46279$2609 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:46280.5-46280.29" + switch \initial + attribute \src "libresoc.v:46280.9-46280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 + end + attribute \src "libresoc.v:46288.3-46297.6" + process $proc$libresoc.v:46288$2612 + assign { } { } + assign { } { } + assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 + attribute \src "libresoc.v:46289.5-46289.29" + switch \initial + attribute \src "libresoc.v:46289.9-46289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$76[0:0]$2614 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$76[0:0]$2614 1'0 + end + sync always + update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 + end + attribute \src "libresoc.v:46298.3-46306.6" + process $proc$libresoc.v:46298$2615 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 + attribute \src "libresoc.v:46299.5-46299.29" + switch \initial + attribute \src "libresoc.v:46299.9-46299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 1'0 + case + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 \rp_XER_xer_ca_alu0_0 + end + sync always + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 + end + attribute \src "libresoc.v:46307.3-46316.6" + process $proc$libresoc.v:46307$2618 + assign { } { } + assign { } { } + assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 + attribute \src "libresoc.v:46308.5-46308.29" + switch \initial + attribute \src "libresoc.v:46308.9-46308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$77[1:0]$2620 \xer_src2__data_o + case + assign $1\fus_src4_i$77[1:0]$2620 2'00 + end + sync always + update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 + end + attribute \src "libresoc.v:46317.3-46325.6" + process $proc$libresoc.v:46317$2621 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 + attribute \src "libresoc.v:46318.5-46318.29" + switch \initial + attribute \src "libresoc.v:46318.9-46318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 1'0 + case + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 \rp_XER_xer_ca_spr0_1 + end + sync always + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 + end + attribute \src "libresoc.v:46326.3-46335.6" + process $proc$libresoc.v:46326$2624 + assign { } { } + assign { } { } + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:46327.5-46327.29" + switch \initial + attribute \src "libresoc.v:46327.9-46327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_spr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i[1:0] \xer_src2__data_o + case + assign $1\fus_src6_i[1:0] 2'00 + end + sync always + update \fus_src6_i $0\fus_src6_i[1:0] + end + attribute \src "libresoc.v:46336.3-46344.6" + process $proc$libresoc.v:46336$2625 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 + attribute \src "libresoc.v:46337.5-46337.29" + switch \initial + attribute \src "libresoc.v:46337.9-46337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 1'0 + case + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 \rp_XER_xer_ca_shiftrot0_2 + end + sync always + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 + end + attribute \src "libresoc.v:46345.3-46354.6" + process $proc$libresoc.v:46345$2628 + assign { } { } + assign { } { } + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:46346.5-46346.29" + switch \initial + attribute \src "libresoc.v:46346.9-46346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i[1:0] \xer_src2__data_o + case + assign $1\fus_src5_i[1:0] 2'00 + end + sync always + update \fus_src5_i $0\fus_src5_i[1:0] + end + attribute \src "libresoc.v:46355.3-46363.6" + process $proc$libresoc.v:46355$2629 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 + attribute \src "libresoc.v:46356.5-46356.29" + switch \initial + attribute \src "libresoc.v:46356.9-46356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 1'0 + case + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 \rp_XER_xer_ov_spr0_0 + end + sync always + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 + end + attribute \src "libresoc.v:46364.3-46373.6" + process $proc$libresoc.v:46364$2632 + assign { } { } + assign { } { } + assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 + attribute \src "libresoc.v:46365.5-46365.29" + switch \initial + attribute \src "libresoc.v:46365.9-46365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$78[1:0]$2634 \xer_src3__data_o + case + assign $1\fus_src5_i$78[1:0]$2634 2'00 + end + sync always + update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 + end + attribute \src "libresoc.v:46374.3-46382.6" + process $proc$libresoc.v:46374$2635 + assign { } { } + assign { } { } + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 + attribute \src "libresoc.v:46375.5-46375.29" + switch \initial + attribute \src "libresoc.v:46375.9-46375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 1'0 + case + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 \rp_CR_full_cr_cr0_0 + end + sync always + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 + end + attribute \src "libresoc.v:46383.3-46392.6" + process $proc$libresoc.v:46383$2638 + assign { } { } + assign { } { } + assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 + attribute \src "libresoc.v:46384.5-46384.29" + switch \initial + attribute \src "libresoc.v:46384.9-46384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_full_cr_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$79[31:0]$2640 \cr_full_rd__data_o + case + assign $1\fus_src3_i$79[31:0]$2640 0 + end + sync always + update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 + end + attribute \src "libresoc.v:46393.3-46401.6" + process $proc$libresoc.v:46393$2641 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 + attribute \src "libresoc.v:46394.5-46394.29" + switch \initial + attribute \src "libresoc.v:46394.9-46394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 1'0 + case + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 \rp_CR_cr_a_cr0_0 + end + sync always + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 + end + attribute \src "libresoc.v:46402.3-46411.6" + process $proc$libresoc.v:46402$2644 + assign { } { } + assign { } { } + assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 + attribute \src "libresoc.v:46403.5-46403.29" + switch \initial + attribute \src "libresoc.v:46403.9-46403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_a_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$80[3:0]$2646 \cr_src1__data_o + case + assign $1\fus_src4_i$80[3:0]$2646 4'0000 + end + sync always + update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 + end + attribute \src "libresoc.v:46412.3-46420.6" + process $proc$libresoc.v:46412$2647 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 + attribute \src "libresoc.v:46413.5-46413.29" + switch \initial + attribute \src "libresoc.v:46413.9-46413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 1'0 + case + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 \rp_CR_cr_a_branch0_1 + end + sync always + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 + end + attribute \src "libresoc.v:46421.3-46430.6" + process $proc$libresoc.v:46421$2650 + assign { } { } + assign { } { } + assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 + attribute \src "libresoc.v:46422.5-46422.29" + switch \initial + attribute \src "libresoc.v:46422.9-46422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_a_branch0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$83[3:0]$2652 \cr_src1__data_o + case + assign $1\fus_src3_i$83[3:0]$2652 4'0000 + end + sync always + update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 + end + attribute \src "libresoc.v:46431.3-46457.6" + process $proc$libresoc.v:46431$2653 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2654 $4\counter$next[1:0]$2658 + attribute \src "libresoc.v:46432.5-46432.29" + switch \initial + attribute \src "libresoc.v:46432.9-46432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \$221 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter$next[1:0]$2655 \$223 [1:0] + case + assign $1\counter$next[1:0]$2655 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2656 $3\counter$next[1:0]$2657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2657 2'10 + case + assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655 + end + case + assign $2\counter$next[1:0]$2656 $1\counter$next[1:0]$2655 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2658 2'00 + case + assign $4\counter$next[1:0]$2658 $2\counter$next[1:0]$2656 + end + sync always + update \counter$next $0\counter$next[1:0]$2654 + end + attribute \src "libresoc.v:46458.3-46466.6" + process $proc$libresoc.v:46458$2659 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:46459.5-46459.29" + switch \initial + attribute \src "libresoc.v:46459.9-46459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 1'0 + case + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 \rp_CR_cr_b_cr0_0 + end + sync always + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 + end + attribute \src "libresoc.v:46467.3-46476.6" + process $proc$libresoc.v:46467$2662 + assign { } { } + assign { } { } + assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46468.5-46468.29" + switch \initial + attribute \src "libresoc.v:46468.9-46468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o + case + assign $1\fus_src5_i$84[3:0]$2664 4'0000 + end + sync always + update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 + end + attribute \src "libresoc.v:46477.3-46567.6" + process $proc$libresoc.v:46477$2665 + assign { } { } + assign { } { } + assign { } { } + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "libresoc.v:46478.5-46478.29" + switch \initial + attribute \src "libresoc.v:46478.9-46478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \$226 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$14 + case + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$17 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$20 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$23 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$26 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$29 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$32 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$35 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$38 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] + end + end + case + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + end + sync always + update \corebusy_o $0\corebusy_o[0:0] + end + attribute \src "libresoc.v:46568.3-46576.6" + process $proc$libresoc.v:46568$2666 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 + attribute \src "libresoc.v:46569.5-46569.29" + switch \initial + attribute \src "libresoc.v:46569.9-46569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 1'0 + case + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 \rp_CR_cr_c_cr0_0 + end + sync always + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 + end + attribute \src "libresoc.v:46577.3-46586.6" + process $proc$libresoc.v:46577$2669 + assign { } { } + assign { } { } + assign $0\fus_src6_i$85[3:0]$2670 $1\fus_src6_i$85[3:0]$2671 + attribute \src "libresoc.v:46578.5-46578.29" + switch \initial + attribute \src "libresoc.v:46578.9-46578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_c_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i$85[3:0]$2671 \cr_src3__data_o + case + assign $1\fus_src6_i$85[3:0]$2671 4'0000 + end + sync always + update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2670 + end + attribute \src "libresoc.v:46587.3-46607.6" + process $proc$libresoc.v:46587$2672 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_terminate_o$next[0:0]$2673 $3\core_terminate_o$next[0:0]$2676 + attribute \src "libresoc.v:46588.5-46588.29" + switch \initial + attribute \src "libresoc.v:46588.9-46588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_terminate_o$next[0:0]$2674 $2\core_terminate_o$next[0:0]$2675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2675 1'1 + case + assign $2\core_terminate_o$next[0:0]$2675 \core_terminate_o + end + case + assign $1\core_terminate_o$next[0:0]$2674 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_terminate_o$next[0:0]$2676 1'0 + case + assign $3\core_terminate_o$next[0:0]$2676 $1\core_terminate_o$next[0:0]$2674 + end + sync always + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2673 + end + attribute \src "libresoc.v:46608.3-46616.6" + process $proc$libresoc.v:46608$2677 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 + attribute \src "libresoc.v:46609.5-46609.29" + switch \initial + attribute \src "libresoc.v:46609.9-46609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 1'0 + case + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 \rp_FAST_fast1_branch0_0 + end + sync always + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 + end + attribute \src "libresoc.v:46617.3-46626.6" + process $proc$libresoc.v:46617$2680 + assign { } { } + assign { } { } + assign $0\fus_src1_i$86[63:0]$2681 $1\fus_src1_i$86[63:0]$2682 + attribute \src "libresoc.v:46618.5-46618.29" + switch \initial + attribute \src "libresoc.v:46618.9-46618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$86[63:0]$2682 \fast_src1__data_o + case + assign $1\fus_src1_i$86[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2681 + end + attribute \src "libresoc.v:46627.3-46635.6" + process $proc$libresoc.v:46627$2683 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:46628.5-46628.29" + switch \initial + attribute \src "libresoc.v:46628.9-46628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0 + case + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1 + end + sync always + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 + end + attribute \src "libresoc.v:46636.3-46645.6" + process $proc$libresoc.v:46636$2686 + assign { } { } + assign { } { } + assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46637.5-46637.29" + switch \initial + attribute \src "libresoc.v:46637.9-46637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o + case + assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 + end + attribute \src "libresoc.v:46646.3-46674.6" + process $proc$libresoc.v:46646$2689 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46647.5-46647.29" + switch \initial + attribute \src "libresoc.v:46647.9-46647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type + case + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + end + attribute \src "libresoc.v:46675.3-46683.6" + process $proc$libresoc.v:46675$2690 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 + attribute \src "libresoc.v:46676.5-46676.29" + switch \initial + attribute \src "libresoc.v:46676.9-46676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 1'0 + case + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 \rp_FAST_fast1_spr0_2 + end + sync always + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 + end + attribute \src "libresoc.v:46684.3-46693.6" + process $proc$libresoc.v:46684$2693 + assign { } { } + assign { } { } + assign $0\fus_src3_i$88[63:0]$2694 $1\fus_src3_i$88[63:0]$2695 + attribute \src "libresoc.v:46685.5-46685.29" + switch \initial + attribute \src "libresoc.v:46685.9-46685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$88[63:0]$2695 \fast_src1__data_o + case + assign $1\fus_src3_i$88[63:0]$2695 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2694 + end + attribute \src "libresoc.v:46694.3-46722.6" + process $proc$libresoc.v:46694$2696 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46695.5-46695.29" + switch \initial + attribute \src "libresoc.v:46695.9-46695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] + end + attribute \src "libresoc.v:46723.3-46731.6" + process $proc$libresoc.v:46723$2697 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 + attribute \src "libresoc.v:46724.5-46724.29" + switch \initial + attribute \src "libresoc.v:46724.9-46724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 1'0 + case + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 \rp_FAST_fast2_branch0_0 + end + sync always + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 + end + attribute \src "libresoc.v:46732.3-46741.6" + process $proc$libresoc.v:46732$2700 + assign { } { } + assign { } { } + assign $0\fus_src2_i$89[63:0]$2701 $1\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:46733.5-46733.29" + switch \initial + attribute \src "libresoc.v:46733.9-46733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast2_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$89[63:0]$2702 \fast_src2__data_o + case + assign $1\fus_src2_i$89[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2701 + end + attribute \src "libresoc.v:46742.3-46750.6" + process $proc$libresoc.v:46742$2703 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 + attribute \src "libresoc.v:46743.5-46743.29" + switch \initial + attribute \src "libresoc.v:46743.9-46743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 1'0 + case + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 \rp_FAST_fast2_trap0_1 + end + sync always + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 + end + attribute \src "libresoc.v:46751.3-46760.6" + process $proc$libresoc.v:46751$2706 + assign { } { } + assign { } { } + assign $0\fus_src4_i$90[63:0]$2707 $1\fus_src4_i$90[63:0]$2708 + attribute \src "libresoc.v:46752.5-46752.29" + switch \initial + attribute \src "libresoc.v:46752.9-46752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast2_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$90[63:0]$2708 \fast_src2__data_o + case + assign $1\fus_src4_i$90[63:0]$2708 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2707 + end + attribute \src "libresoc.v:46761.3-46790.6" + process $proc$libresoc.v:46761$2709 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46762.5-46762.29" + switch \initial + attribute \src "libresoc.v:46762.9-46762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } + case + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:46791.3-46799.6" + process $proc$libresoc.v:46791$2710 + assign { } { } + assign { } { } + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 + attribute \src "libresoc.v:46792.5-46792.29" + switch \initial + attribute \src "libresoc.v:46792.9-46792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 1'0 + case + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 \rp_SPR_spr1_spr0_0 + end + sync always + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 + end + attribute \src "libresoc.v:46800.3-46809.6" + process $proc$libresoc.v:46800$2713 + assign { } { } + assign { } { } + assign $0\fus_src2_i$91[63:0]$2714 $1\fus_src2_i$91[63:0]$2715 + attribute \src "libresoc.v:46801.5-46801.29" + switch \initial + attribute \src "libresoc.v:46801.9-46801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_SPR_spr1_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$91[63:0]$2715 \spr_spr1__data_o + case + assign $1\fus_src2_i$91[63:0]$2715 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2714 + end + attribute \src "libresoc.v:46810.3-46818.6" + process $proc$libresoc.v:46810$2716 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:46811.5-46811.29" + switch \initial + attribute \src "libresoc.v:46811.9-46811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$next[0:0]$2718 1'0 + case + assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick + end + sync always + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 + end + attribute \src "libresoc.v:46819.3-46827.6" + process $proc$libresoc.v:46819$2719 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$991$next[0:0]$2720 $1\wr_pick_dly$991$next[0:0]$2721 + attribute \src "libresoc.v:46820.5-46820.29" + switch \initial + attribute \src "libresoc.v:46820.9-46820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$991$next[0:0]$2721 1'0 + case + assign $1\wr_pick_dly$991$next[0:0]$2721 \wr_pick$988 + end + sync always + update \wr_pick_dly$991$next $0\wr_pick_dly$991$next[0:0]$2720 + end + attribute \src "libresoc.v:46828.3-46857.6" + process $proc$libresoc.v:46828$2722 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46829.5-46829.29" + switch \initial + attribute \src "libresoc.v:46829.9-46829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + end + attribute \src "libresoc.v:46858.3-46866.6" + process $proc$libresoc.v:46858$2723 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1010$next[0:0]$2724 $1\wr_pick_dly$1010$next[0:0]$2725 + attribute \src "libresoc.v:46859.5-46859.29" + switch \initial + attribute \src "libresoc.v:46859.9-46859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1010$next[0:0]$2725 1'0 + case + assign $1\wr_pick_dly$1010$next[0:0]$2725 \wr_pick$1007 + end + sync always + update \wr_pick_dly$1010$next $0\wr_pick_dly$1010$next[0:0]$2724 + end + attribute \src "libresoc.v:46867.3-46875.6" + process $proc$libresoc.v:46867$2726 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1031$next[0:0]$2727 $1\wr_pick_dly$1031$next[0:0]$2728 + attribute \src "libresoc.v:46868.5-46868.29" + switch \initial + attribute \src "libresoc.v:46868.9-46868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1031$next[0:0]$2728 1'0 + case + assign $1\wr_pick_dly$1031$next[0:0]$2728 \wr_pick$1028 + end + sync always + update \wr_pick_dly$1031$next $0\wr_pick_dly$1031$next[0:0]$2727 + end + attribute \src "libresoc.v:46876.3-46905.6" + process $proc$libresoc.v:46876$2729 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46877.5-46877.29" + switch \initial + attribute \src "libresoc.v:46877.9-46877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } + case + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + end + attribute \src "libresoc.v:46906.3-46914.6" + process $proc$libresoc.v:46906$2730 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1049$next[0:0]$2731 $1\wr_pick_dly$1049$next[0:0]$2732 + attribute \src "libresoc.v:46907.5-46907.29" + switch \initial + attribute \src "libresoc.v:46907.9-46907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1049$next[0:0]$2732 1'0 + case + assign $1\wr_pick_dly$1049$next[0:0]$2732 \wr_pick$1046 + end + sync always + update \wr_pick_dly$1049$next $0\wr_pick_dly$1049$next[0:0]$2731 + end + attribute \src "libresoc.v:46915.3-46923.6" + process $proc$libresoc.v:46915$2733 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1071$next[0:0]$2734 $1\wr_pick_dly$1071$next[0:0]$2735 + attribute \src "libresoc.v:46916.5-46916.29" + switch \initial + attribute \src "libresoc.v:46916.9-46916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1071$next[0:0]$2735 1'0 + case + assign $1\wr_pick_dly$1071$next[0:0]$2735 \wr_pick$1068 + end + sync always + update \wr_pick_dly$1071$next $0\wr_pick_dly$1071$next[0:0]$2734 + end + attribute \src "libresoc.v:46924.3-46932.6" + process $proc$libresoc.v:46924$2736 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1091$next[0:0]$2737 $1\wr_pick_dly$1091$next[0:0]$2738 + attribute \src "libresoc.v:46925.5-46925.29" + switch \initial + attribute \src "libresoc.v:46925.9-46925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1091$next[0:0]$2738 1'0 + case + assign $1\wr_pick_dly$1091$next[0:0]$2738 \wr_pick$1088 + end + sync always + update \wr_pick_dly$1091$next $0\wr_pick_dly$1091$next[0:0]$2737 + end + attribute \src "libresoc.v:46933.3-46961.6" + process $proc$libresoc.v:46933$2739 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46934.5-46934.29" + switch \initial + attribute \src "libresoc.v:46934.9-46934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in + case + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + end + attribute \src "libresoc.v:46962.3-46970.6" + process $proc$libresoc.v:46962$2740 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1111$next[0:0]$2741 $1\wr_pick_dly$1111$next[0:0]$2742 + attribute \src "libresoc.v:46963.5-46963.29" + switch \initial + attribute \src "libresoc.v:46963.9-46963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1111$next[0:0]$2742 1'0 + case + assign $1\wr_pick_dly$1111$next[0:0]$2742 \wr_pick$1108 + end + sync always + update \wr_pick_dly$1111$next $0\wr_pick_dly$1111$next[0:0]$2741 + end + attribute \src "libresoc.v:46971.3-46979.6" + process $proc$libresoc.v:46971$2743 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1130$next[0:0]$2744 $1\wr_pick_dly$1130$next[0:0]$2745 + attribute \src "libresoc.v:46972.5-46972.29" + switch \initial + attribute \src "libresoc.v:46972.9-46972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1130$next[0:0]$2745 1'0 + case + assign $1\wr_pick_dly$1130$next[0:0]$2745 \wr_pick$1127 + end + sync always + update \wr_pick_dly$1130$next $0\wr_pick_dly$1130$next[0:0]$2744 + end + attribute \src "libresoc.v:46980.3-47008.6" + process $proc$libresoc.v:46980$2746 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46981.5-46981.29" + switch \initial + attribute \src "libresoc.v:46981.9-46981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + end + attribute \src "libresoc.v:47009.3-47017.6" + process $proc$libresoc.v:47009$2747 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1148$next[0:0]$2748 $1\wr_pick_dly$1148$next[0:0]$2749 + attribute \src "libresoc.v:47010.5-47010.29" + switch \initial + attribute \src "libresoc.v:47010.9-47010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1148$next[0:0]$2749 1'0 + case + assign $1\wr_pick_dly$1148$next[0:0]$2749 \wr_pick$1145 + end + sync always + update \wr_pick_dly$1148$next $0\wr_pick_dly$1148$next[0:0]$2748 + end + attribute \src "libresoc.v:47018.3-47046.6" + process $proc$libresoc.v:47018$2750 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:47019.5-47019.29" + switch \initial + attribute \src "libresoc.v:47019.9-47019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU__invert_out + case + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] + end + attribute \src "libresoc.v:47047.3-47055.6" + process $proc$libresoc.v:47047$2751 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1222$next[0:0]$2752 $1\wr_pick_dly$1222$next[0:0]$2753 + attribute \src "libresoc.v:47048.5-47048.29" + switch \initial + attribute \src "libresoc.v:47048.9-47048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1222$next[0:0]$2753 1'0 + case + assign $1\wr_pick_dly$1222$next[0:0]$2753 \wr_pick$1219 + end + sync always + update \wr_pick_dly$1222$next $0\wr_pick_dly$1222$next[0:0]$2752 + end + attribute \src "libresoc.v:47056.3-47084.6" + process $proc$libresoc.v:47056$2754 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:47057.5-47057.29" + switch \initial + attribute \src "libresoc.v:47057.9-47057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU__write_cr0 + case + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] + end + attribute \src "libresoc.v:47085.3-47093.6" + process $proc$libresoc.v:47085$2755 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1250$next[0:0]$2756 $1\wr_pick_dly$1250$next[0:0]$2757 + attribute \src "libresoc.v:47086.5-47086.29" + switch \initial + attribute \src "libresoc.v:47086.9-47086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1250$next[0:0]$2757 1'0 + case + assign $1\wr_pick_dly$1250$next[0:0]$2757 \wr_pick$1247 + end + sync always + update \wr_pick_dly$1250$next $0\wr_pick_dly$1250$next[0:0]$2756 + end + attribute \src "libresoc.v:47094.3-47122.6" + process $proc$libresoc.v:47094$2758 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:47095.5-47095.29" + switch \initial + attribute \src "libresoc.v:47095.9-47095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU__input_carry + case + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] + end + attribute \src "libresoc.v:47123.3-47131.6" + process $proc$libresoc.v:47123$2759 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1270$next[0:0]$2760 $1\wr_pick_dly$1270$next[0:0]$2761 + attribute \src "libresoc.v:47124.5-47124.29" + switch \initial + attribute \src "libresoc.v:47124.9-47124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1270$next[0:0]$2761 1'0 + case + assign $1\wr_pick_dly$1270$next[0:0]$2761 \wr_pick$1267 + end + sync always + update \wr_pick_dly$1270$next $0\wr_pick_dly$1270$next[0:0]$2760 + end + attribute \src "libresoc.v:47132.3-47140.6" + process $proc$libresoc.v:47132$2762 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1290$next[0:0]$2763 $1\wr_pick_dly$1290$next[0:0]$2764 + attribute \src "libresoc.v:47133.5-47133.29" + switch \initial + attribute \src "libresoc.v:47133.9-47133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1290$next[0:0]$2764 1'0 + case + assign $1\wr_pick_dly$1290$next[0:0]$2764 \wr_pick$1287 + end + sync always + update \wr_pick_dly$1290$next $0\wr_pick_dly$1290$next[0:0]$2763 + end + attribute \src "libresoc.v:47141.3-47169.6" + process $proc$libresoc.v:47141$2765 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:47142.5-47142.29" + switch \initial + attribute \src "libresoc.v:47142.9-47142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU__output_carry + case + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] + end + attribute \src "libresoc.v:47170.3-47178.6" + process $proc$libresoc.v:47170$2766 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1310$next[0:0]$2767 $1\wr_pick_dly$1310$next[0:0]$2768 + attribute \src "libresoc.v:47171.5-47171.29" + switch \initial + attribute \src "libresoc.v:47171.9-47171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1310$next[0:0]$2768 1'0 + case + assign $1\wr_pick_dly$1310$next[0:0]$2768 \wr_pick$1307 + end + sync always + update \wr_pick_dly$1310$next $0\wr_pick_dly$1310$next[0:0]$2767 + end + attribute \src "libresoc.v:47179.3-47187.6" + process $proc$libresoc.v:47179$2769 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1330$next[0:0]$2770 $1\wr_pick_dly$1330$next[0:0]$2771 + attribute \src "libresoc.v:47180.5-47180.29" + switch \initial + attribute \src "libresoc.v:47180.9-47180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1330$next[0:0]$2771 1'0 + case + assign $1\wr_pick_dly$1330$next[0:0]$2771 \wr_pick$1327 + end + sync always + update \wr_pick_dly$1330$next $0\wr_pick_dly$1330$next[0:0]$2770 + end + attribute \src "libresoc.v:47188.3-47216.6" + process $proc$libresoc.v:47188$2772 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:47189.5-47189.29" + switch \initial + attribute \src "libresoc.v:47189.9-47189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU__is_32bit + case + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] + end + attribute \src "libresoc.v:47217.3-47225.6" + process $proc$libresoc.v:47217$2773 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1350$next[0:0]$2774 $1\wr_pick_dly$1350$next[0:0]$2775 + attribute \src "libresoc.v:47218.5-47218.29" + switch \initial + attribute \src "libresoc.v:47218.9-47218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1350$next[0:0]$2775 1'0 + case + assign $1\wr_pick_dly$1350$next[0:0]$2775 \wr_pick$1347 + end + sync always + update \wr_pick_dly$1350$next $0\wr_pick_dly$1350$next[0:0]$2774 + end + attribute \src "libresoc.v:47226.3-47254.6" + process $proc$libresoc.v:47226$2776 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:47227.5-47227.29" + switch \initial + attribute \src "libresoc.v:47227.9-47227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU__is_signed + case + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] + end + attribute \src "libresoc.v:47255.3-47263.6" + process $proc$libresoc.v:47255$2777 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1397$next[0:0]$2778 $1\wr_pick_dly$1397$next[0:0]$2779 + attribute \src "libresoc.v:47256.5-47256.29" + switch \initial + attribute \src "libresoc.v:47256.9-47256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1397$next[0:0]$2779 1'0 + case + assign $1\wr_pick_dly$1397$next[0:0]$2779 \wr_pick$1394 + end + sync always + update \wr_pick_dly$1397$next $0\wr_pick_dly$1397$next[0:0]$2778 + end + attribute \src "libresoc.v:47264.3-47272.6" + process $proc$libresoc.v:47264$2780 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1413$next[0:0]$2781 $1\wr_pick_dly$1413$next[0:0]$2782 + attribute \src "libresoc.v:47265.5-47265.29" + switch \initial + attribute \src "libresoc.v:47265.9-47265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1413$next[0:0]$2782 1'0 + case + assign $1\wr_pick_dly$1413$next[0:0]$2782 \wr_pick$1410 + end + sync always + update \wr_pick_dly$1413$next $0\wr_pick_dly$1413$next[0:0]$2781 + end + attribute \src "libresoc.v:47273.3-47301.6" + process $proc$libresoc.v:47273$2783 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:47274.5-47274.29" + switch \initial + attribute \src "libresoc.v:47274.9-47274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU__data_len + case + assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] + end + attribute \src "libresoc.v:47302.3-47310.6" + process $proc$libresoc.v:47302$2784 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1429$next[0:0]$2785 $1\wr_pick_dly$1429$next[0:0]$2786 + attribute \src "libresoc.v:47303.5-47303.29" + switch \initial + attribute \src "libresoc.v:47303.9-47303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1429$next[0:0]$2786 1'0 + case + assign $1\wr_pick_dly$1429$next[0:0]$2786 \wr_pick$1426 + end + sync always + update \wr_pick_dly$1429$next $0\wr_pick_dly$1429$next[0:0]$2785 + end + attribute \src "libresoc.v:47311.3-47339.6" + process $proc$libresoc.v:47311$2787 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:47312.5-47312.29" + switch \initial + attribute \src "libresoc.v:47312.9-47312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU__insn + case + assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] + end + attribute \src "libresoc.v:47340.3-47348.6" + process $proc$libresoc.v:47340$2788 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1463$next[0:0]$2789 $1\wr_pick_dly$1463$next[0:0]$2790 + attribute \src "libresoc.v:47341.5-47341.29" + switch \initial + attribute \src "libresoc.v:47341.9-47341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1463$next[0:0]$2790 1'0 + case + assign $1\wr_pick_dly$1463$next[0:0]$2790 \wr_pick$1460 + end + sync always + update \wr_pick_dly$1463$next $0\wr_pick_dly$1463$next[0:0]$2789 + end + attribute \src "libresoc.v:47349.3-47377.6" + process $proc$libresoc.v:47349$2791 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:47350.5-47350.29" + switch \initial + attribute \src "libresoc.v:47350.9-47350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i[0:0] \issue_i + case + assign $3\fus_cu_issue_i[0:0] 1'0 + end + end + case + assign $1\fus_cu_issue_i[0:0] 1'0 + end + sync always + update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] + end + attribute \src "libresoc.v:47378.3-47386.6" + process $proc$libresoc.v:47378$2792 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1479$next[0:0]$2793 $1\wr_pick_dly$1479$next[0:0]$2794 + attribute \src "libresoc.v:47379.5-47379.29" + switch \initial + attribute \src "libresoc.v:47379.9-47379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1479$next[0:0]$2794 1'0 + case + assign $1\wr_pick_dly$1479$next[0:0]$2794 \wr_pick$1476 + end + sync always + update \wr_pick_dly$1479$next $0\wr_pick_dly$1479$next[0:0]$2793 + end + attribute \src "libresoc.v:47387.3-47395.6" + process $proc$libresoc.v:47387$2795 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1495$next[0:0]$2796 $1\wr_pick_dly$1495$next[0:0]$2797 + attribute \src "libresoc.v:47388.5-47388.29" + switch \initial + attribute \src "libresoc.v:47388.9-47388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1495$next[0:0]$2797 1'0 + case + assign $1\wr_pick_dly$1495$next[0:0]$2797 \wr_pick$1492 + end + sync always + update \wr_pick_dly$1495$next $0\wr_pick_dly$1495$next[0:0]$2796 + end + attribute \src "libresoc.v:47396.3-47424.6" + process $proc$libresoc.v:47396$2798 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:47397.5-47397.29" + switch \initial + attribute \src "libresoc.v:47397.9-47397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i[3:0] \$228 + case + assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 + end + sync always + update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] + end + attribute \src "libresoc.v:47425.3-47433.6" + process $proc$libresoc.v:47425$2799 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1511$next[0:0]$2800 $1\wr_pick_dly$1511$next[0:0]$2801 + attribute \src "libresoc.v:47426.5-47426.29" + switch \initial + attribute \src "libresoc.v:47426.9-47426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1511$next[0:0]$2801 1'0 + case + assign $1\wr_pick_dly$1511$next[0:0]$2801 \wr_pick$1508 + end + sync always + update \wr_pick_dly$1511$next $0\wr_pick_dly$1511$next[0:0]$2800 + end + attribute \src "libresoc.v:47434.3-47462.6" + process $proc$libresoc.v:47434$2802 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:47435.5-47435.29" + switch \initial + attribute \src "libresoc.v:47435.9-47435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR__insn_type + case + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] + end + attribute \src "libresoc.v:47463.3-47471.6" + process $proc$libresoc.v:47463$2803 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1547$next[0:0]$2804 $1\wr_pick_dly$1547$next[0:0]$2805 + attribute \src "libresoc.v:47464.5-47464.29" + switch \initial + attribute \src "libresoc.v:47464.9-47464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1547$next[0:0]$2805 1'0 + case + assign $1\wr_pick_dly$1547$next[0:0]$2805 \wr_pick$1544 + end + sync always + update \wr_pick_dly$1547$next $0\wr_pick_dly$1547$next[0:0]$2804 + end + attribute \src "libresoc.v:47472.3-47480.6" + process $proc$libresoc.v:47472$2806 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1563$next[0:0]$2807 $1\wr_pick_dly$1563$next[0:0]$2808 + attribute \src "libresoc.v:47473.5-47473.29" + switch \initial + attribute \src "libresoc.v:47473.9-47473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1563$next[0:0]$2808 1'0 + case + assign $1\wr_pick_dly$1563$next[0:0]$2808 \wr_pick$1560 + end + sync always + update \wr_pick_dly$1563$next $0\wr_pick_dly$1563$next[0:0]$2807 + end + attribute \src "libresoc.v:47481.3-47509.6" + process $proc$libresoc.v:47481$2809 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47482.5-47482.29" + switch \initial + attribute \src "libresoc.v:47482.9-47482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] \dec_CR_CR__fn_unit + case + assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] + end + attribute \src "libresoc.v:47510.3-47518.6" + process $proc$libresoc.v:47510$2810 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1579$next[0:0]$2811 $1\wr_pick_dly$1579$next[0:0]$2812 + attribute \src "libresoc.v:47511.5-47511.29" + switch \initial + attribute \src "libresoc.v:47511.9-47511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1579$next[0:0]$2812 1'0 + case + assign $1\wr_pick_dly$1579$next[0:0]$2812 \wr_pick$1576 + end + sync always + update \wr_pick_dly$1579$next $0\wr_pick_dly$1579$next[0:0]$2811 + end + attribute \src "libresoc.v:47519.3-47527.6" + process $proc$libresoc.v:47519$2813 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1595$next[0:0]$2814 $1\wr_pick_dly$1595$next[0:0]$2815 + attribute \src "libresoc.v:47520.5-47520.29" + switch \initial + attribute \src "libresoc.v:47520.9-47520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1595$next[0:0]$2815 1'0 + case + assign $1\wr_pick_dly$1595$next[0:0]$2815 \wr_pick$1592 + end + sync always + update \wr_pick_dly$1595$next $0\wr_pick_dly$1595$next[0:0]$2814 + end + attribute \src "libresoc.v:47528.3-47556.6" + process $proc$libresoc.v:47528$2816 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:47529.5-47529.29" + switch \initial + attribute \src "libresoc.v:47529.9-47529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR__insn + case + assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] + end + attribute \src "libresoc.v:47557.3-47565.6" + process $proc$libresoc.v:47557$2817 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1637$next[0:0]$2818 $1\wr_pick_dly$1637$next[0:0]$2819 + attribute \src "libresoc.v:47558.5-47558.29" + switch \initial + attribute \src "libresoc.v:47558.9-47558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1637$next[0:0]$2819 1'0 + case + assign $1\wr_pick_dly$1637$next[0:0]$2819 \wr_pick$1634 + end + sync always + update \wr_pick_dly$1637$next $0\wr_pick_dly$1637$next[0:0]$2818 + end + attribute \src "libresoc.v:47566.3-47594.6" + process $proc$libresoc.v:47566$2820 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$13[0:0]$2821 $1\fus_cu_issue_i$13[0:0]$2822 + attribute \src "libresoc.v:47567.5-47567.29" + switch \initial + attribute \src "libresoc.v:47567.9-47567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$13[0:0]$2822 $2\fus_cu_issue_i$13[0:0]$2823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$13[0:0]$2823 $3\fus_cu_issue_i$13[0:0]$2824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$13[0:0]$2824 \issue_i + case + assign $3\fus_cu_issue_i$13[0:0]$2824 1'0 + end + end + case + assign $1\fus_cu_issue_i$13[0:0]$2822 1'0 + end + sync always + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2821 + end + attribute \src "libresoc.v:47595.3-47603.6" + process $proc$libresoc.v:47595$2825 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1656$next[0:0]$2826 $1\wr_pick_dly$1656$next[0:0]$2827 + attribute \src "libresoc.v:47596.5-47596.29" + switch \initial + attribute \src "libresoc.v:47596.9-47596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1656$next[0:0]$2827 1'0 + case + assign $1\wr_pick_dly$1656$next[0:0]$2827 \wr_pick$1653 + end + sync always + update \wr_pick_dly$1656$next $0\wr_pick_dly$1656$next[0:0]$2826 + end + attribute \src "libresoc.v:47604.3-47632.6" + process $proc$libresoc.v:47604$2828 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$15[5:0]$2829 $1\fus_cu_rdmaskn_i$15[5:0]$2830 + attribute \src "libresoc.v:47605.5-47605.29" + switch \initial + attribute \src "libresoc.v:47605.9-47605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 $2\fus_cu_rdmaskn_i$15[5:0]$2831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 $3\fus_cu_rdmaskn_i$15[5:0]$2832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 \$250 + case + assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2829 + end + attribute \src "libresoc.v:47633.3-47641.6" + process $proc$libresoc.v:47633$2833 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1672$next[0:0]$2834 $1\wr_pick_dly$1672$next[0:0]$2835 + attribute \src "libresoc.v:47634.5-47634.29" + switch \initial + attribute \src "libresoc.v:47634.9-47634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1672$next[0:0]$2835 1'0 + case + assign $1\wr_pick_dly$1672$next[0:0]$2835 \wr_pick$1669 + end + sync always + update \wr_pick_dly$1672$next $0\wr_pick_dly$1672$next[0:0]$2834 + end + attribute \src "libresoc.v:47642.3-47650.6" + process $proc$libresoc.v:47642$2836 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1688$next[0:0]$2837 $1\wr_pick_dly$1688$next[0:0]$2838 + attribute \src "libresoc.v:47643.5-47643.29" + switch \initial + attribute \src "libresoc.v:47643.9-47643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1688$next[0:0]$2838 1'0 + case + assign $1\wr_pick_dly$1688$next[0:0]$2838 \wr_pick$1685 + end + sync always + update \wr_pick_dly$1688$next $0\wr_pick_dly$1688$next[0:0]$2837 + end + attribute \src "libresoc.v:47651.3-47679.6" + process $proc$libresoc.v:47651$2839 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47652.5-47652.29" + switch \initial + attribute \src "libresoc.v:47652.9-47652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH__cia + case + assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] + end + attribute \src "libresoc.v:47680.3-47688.6" + process $proc$libresoc.v:47680$2840 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1704$next[0:0]$2841 $1\wr_pick_dly$1704$next[0:0]$2842 + attribute \src "libresoc.v:47681.5-47681.29" + switch \initial + attribute \src "libresoc.v:47681.9-47681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1704$next[0:0]$2842 1'0 + case + assign $1\wr_pick_dly$1704$next[0:0]$2842 \wr_pick$1701 + end + sync always + update \wr_pick_dly$1704$next $0\wr_pick_dly$1704$next[0:0]$2841 + end + attribute \src "libresoc.v:47689.3-47717.6" + process $proc$libresoc.v:47689$2843 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47690.5-47690.29" + switch \initial + attribute \src "libresoc.v:47690.9-47690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH__insn_type + case + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] + end + attribute \src "libresoc.v:47718.3-47726.6" + process $proc$libresoc.v:47718$2844 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1748$next[0:0]$2845 $1\wr_pick_dly$1748$next[0:0]$2846 + attribute \src "libresoc.v:47719.5-47719.29" + switch \initial + attribute \src "libresoc.v:47719.9-47719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1748$next[0:0]$2846 1'0 + case + assign $1\wr_pick_dly$1748$next[0:0]$2846 \wr_pick$1745 + end + sync always + update \wr_pick_dly$1748$next $0\wr_pick_dly$1748$next[0:0]$2845 + end + attribute \src "libresoc.v:47727.3-47735.6" + process $proc$libresoc.v:47727$2847 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1764$next[0:0]$2848 $1\wr_pick_dly$1764$next[0:0]$2849 + attribute \src "libresoc.v:47728.5-47728.29" + switch \initial + attribute \src "libresoc.v:47728.9-47728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1764$next[0:0]$2849 1'0 + case + assign $1\wr_pick_dly$1764$next[0:0]$2849 \wr_pick$1761 + end + sync always + update \wr_pick_dly$1764$next $0\wr_pick_dly$1764$next[0:0]$2848 + end + attribute \src "libresoc.v:47736.3-47764.6" + process $proc$libresoc.v:47736$2850 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47737.5-47737.29" + switch \initial + attribute \src "libresoc.v:47737.9-47737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] \dec_BRANCH_BRANCH__fn_unit + case + assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] + end + attribute \src "libresoc.v:47765.3-47773.6" + process $proc$libresoc.v:47765$2851 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1788$next[0:0]$2852 $1\wr_pick_dly$1788$next[0:0]$2853 + attribute \src "libresoc.v:47766.5-47766.29" + switch \initial + attribute \src "libresoc.v:47766.9-47766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1788$next[0:0]$2853 1'0 + case + assign $1\wr_pick_dly$1788$next[0:0]$2853 \wr_pick$1785 + end + sync always + update \wr_pick_dly$1788$next $0\wr_pick_dly$1788$next[0:0]$2852 + end + attribute \src "libresoc.v:47774.3-47802.6" + process $proc$libresoc.v:47774$2854 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47775.5-47775.29" + switch \initial + attribute \src "libresoc.v:47775.9-47775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH__insn + case + assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] + end + attribute \src "libresoc.v:47803.3-47811.6" + process $proc$libresoc.v:47803$2855 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1808$next[0:0]$2856 $1\wr_pick_dly$1808$next[0:0]$2857 + attribute \src "libresoc.v:47804.5-47804.29" + switch \initial + attribute \src "libresoc.v:47804.9-47804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1808$next[0:0]$2857 1'0 + case + assign $1\wr_pick_dly$1808$next[0:0]$2857 \wr_pick$1805 + end + sync always + update \wr_pick_dly$1808$next $0\wr_pick_dly$1808$next[0:0]$2856 + end + attribute \src "libresoc.v:47812.3-47841.6" + process $proc$libresoc.v:47812$2858 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47813.5-47813.29" + switch \initial + attribute \src "libresoc.v:47813.9-47813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__data } + case + assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:47842.3-47870.6" + process $proc$libresoc.v:47842$2859 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47843.5-47843.29" + switch \initial + attribute \src "libresoc.v:47843.9-47843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk + case + assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] + end + attribute \src "libresoc.v:47871.3-47899.6" + process $proc$libresoc.v:47871$2860 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47872.5-47872.29" + switch \initial + attribute \src "libresoc.v:47872.9-47872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit + case + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] + end + attribute \src "libresoc.v:47900.3-47928.6" + process $proc$libresoc.v:47900$2861 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 + attribute \src "libresoc.v:47901.5-47901.29" + switch \initial + attribute \src "libresoc.v:47901.9-47901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$16[0:0]$2865 \issue_i + case + assign $3\fus_cu_issue_i$16[0:0]$2865 1'0 + end + end + case + assign $1\fus_cu_issue_i$16[0:0]$2863 1'0 + end + sync always + update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 + end + attribute \src "libresoc.v:47929.3-47957.6" + process $proc$libresoc.v:47929$2866 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 + attribute \src "libresoc.v:47930.5-47930.29" + switch \initial + attribute \src "libresoc.v:47930.9-47930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 \$252 + case + assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 3'000 + end + sync always + update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 + end + attribute \src "libresoc.v:47958.3-47986.6" + process $proc$libresoc.v:47958$2871 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47959.5-47959.29" + switch \initial + attribute \src "libresoc.v:47959.9-47959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + case + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] + end + attribute \src "libresoc.v:47987.3-48015.6" + process $proc$libresoc.v:47987$2872 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:47988.5-47988.29" + switch \initial + attribute \src "libresoc.v:47988.9-47988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] \core_core_fn_unit + case + assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] + end + attribute \src "libresoc.v:48016.3-48044.6" + process $proc$libresoc.v:48016$2873 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:48017.5-48017.29" + switch \initial + attribute \src "libresoc.v:48017.9-48017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn + case + assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] + end + attribute \src "libresoc.v:48045.3-48073.6" + process $proc$libresoc.v:48045$2874 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:48046.5-48046.29" + switch \initial + attribute \src "libresoc.v:48046.9-48046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr + case + assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] + end + attribute \src "libresoc.v:48074.3-48102.6" + process $proc$libresoc.v:48074$2875 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:48075.5-48075.29" + switch \initial + attribute \src "libresoc.v:48075.9-48075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia + case + assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] + end + attribute \src "libresoc.v:48103.3-48131.6" + process $proc$libresoc.v:48103$2876 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:48104.5-48104.29" + switch \initial + attribute \src "libresoc.v:48104.9-48104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit + case + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] + end + attribute \src "libresoc.v:48132.3-48160.6" + process $proc$libresoc.v:48132$2877 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:48133.5-48133.29" + switch \initial + attribute \src "libresoc.v:48133.9-48133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype + case + assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + end + sync always + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] + end + attribute \src "libresoc.v:48161.3-48189.6" + process $proc$libresoc.v:48161$2878 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:48162.5-48162.29" + switch \initial + attribute \src "libresoc.v:48162.9-48162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr + case + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] + end + attribute \src "libresoc.v:48190.3-48218.6" + process $proc$libresoc.v:48190$2879 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:48191.5-48191.29" + switch \initial + attribute \src "libresoc.v:48191.9-48191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } + case + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + sync always + update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + end + attribute \src "libresoc.v:48219.3-48247.6" + process $proc$libresoc.v:48219$2880 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 + attribute \src "libresoc.v:48220.5-48220.29" + switch \initial + attribute \src "libresoc.v:48220.9-48220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$19[0:0]$2884 \issue_i + case + assign $3\fus_cu_issue_i$19[0:0]$2884 1'0 + end + end + case + assign $1\fus_cu_issue_i$19[0:0]$2882 1'0 + end + sync always + update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 + end + attribute \src "libresoc.v:48248.3-48276.6" + process $proc$libresoc.v:48248$2885 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 + attribute \src "libresoc.v:48249.5-48249.29" + switch \initial + attribute \src "libresoc.v:48249.9-48249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 \$254 + case + assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 4'0000 + end + sync always + update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 + end + attribute \src "libresoc.v:48277.3-48305.6" + process $proc$libresoc.v:48277$2890 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:48278.5-48278.29" + switch \initial + attribute \src "libresoc.v:48278.9-48278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL__insn_type + case + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] + end + attribute \src "libresoc.v:48306.3-48334.6" + process $proc$libresoc.v:48306$2891 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48307.5-48307.29" + switch \initial + attribute \src "libresoc.v:48307.9-48307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] \dec_LOGICAL_LOGICAL__fn_unit + case + assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] + end + attribute \src "libresoc.v:48335.3-48364.6" + process $proc$libresoc.v:48335$2892 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:48336.5-48336.29" + switch \initial + attribute \src "libresoc.v:48336.9-48336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__data } + case + assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:48365.3-48394.6" + process $proc$libresoc.v:48365$2893 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:48366.5-48366.29" + switch \initial + attribute \src "libresoc.v:48366.9-48366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__rc } + case + assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] + update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] + end + attribute \src "libresoc.v:48395.3-48424.6" + process $proc$libresoc.v:48395$2894 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:48396.5-48396.29" + switch \initial + attribute \src "libresoc.v:48396.9-48396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__oe } + case + assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] + update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] + end + attribute \src "libresoc.v:48425.3-48453.6" + process $proc$libresoc.v:48425$2895 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:48426.5-48426.29" + switch \initial + attribute \src "libresoc.v:48426.9-48426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL__invert_in + case + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] + end + attribute \src "libresoc.v:48454.3-48482.6" + process $proc$libresoc.v:48454$2896 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:48455.5-48455.29" + switch \initial + attribute \src "libresoc.v:48455.9-48455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL__zero_a + case + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] + end + attribute \src "libresoc.v:48483.3-48511.6" + process $proc$libresoc.v:48483$2897 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:48484.5-48484.29" + switch \initial + attribute \src "libresoc.v:48484.9-48484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL__input_carry + case + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] + end + attribute \src "libresoc.v:48512.3-48540.6" + process $proc$libresoc.v:48512$2898 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:48513.5-48513.29" + switch \initial + attribute \src "libresoc.v:48513.9-48513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL__invert_out + case + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] + end + attribute \src "libresoc.v:48541.3-48569.6" + process $proc$libresoc.v:48541$2899 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:48542.5-48542.29" + switch \initial + attribute \src "libresoc.v:48542.9-48542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL__write_cr0 + case + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] + end + connect \$1000 $and$libresoc.v:42103$1506_Y + connect \$1003 $ternary$libresoc.v:42104$1507_Y + connect \$1005 $and$libresoc.v:42105$1508_Y + connect \$1008 $and$libresoc.v:42106$1509_Y + connect \$1012 $not$libresoc.v:42107$1510_Y + connect \$1014 $and$libresoc.v:42108$1511_Y + connect \$1021 $and$libresoc.v:42109$1512_Y + connect \$1024 $ternary$libresoc.v:42110$1513_Y + connect \$1026 $and$libresoc.v:42111$1514_Y + connect \$1029 $and$libresoc.v:42112$1515_Y + connect \$1033 $not$libresoc.v:42113$1516_Y + connect \$1035 $and$libresoc.v:42114$1517_Y + connect \$1039 $and$libresoc.v:42115$1518_Y + connect \$1042 $ternary$libresoc.v:42116$1519_Y + connect \$1044 $and$libresoc.v:42117$1520_Y + connect \$1047 $and$libresoc.v:42118$1521_Y + connect \$1051 $not$libresoc.v:42119$1522_Y + connect \$1053 $and$libresoc.v:42120$1523_Y + connect \$1061 $and$libresoc.v:42121$1524_Y + connect \$1064 $ternary$libresoc.v:42122$1525_Y + connect \$1066 $and$libresoc.v:42123$1526_Y + connect \$1069 $and$libresoc.v:42124$1527_Y + connect \$1073 $not$libresoc.v:42125$1528_Y + connect \$1075 $and$libresoc.v:42126$1529_Y + connect \$1081 $and$libresoc.v:42127$1530_Y + connect \$1084 $ternary$libresoc.v:42128$1531_Y + connect \$1086 $and$libresoc.v:42129$1532_Y + connect \$1089 $and$libresoc.v:42130$1533_Y + connect \$1093 $not$libresoc.v:42131$1534_Y + connect \$1095 $and$libresoc.v:42132$1535_Y + connect \$1101 $and$libresoc.v:42133$1536_Y + connect \$1104 $ternary$libresoc.v:42134$1537_Y + connect \$1106 $and$libresoc.v:42135$1538_Y + connect \$1109 $and$libresoc.v:42136$1539_Y + connect \$1113 $not$libresoc.v:42137$1540_Y + connect \$1115 $and$libresoc.v:42138$1541_Y + connect \$1120 $and$libresoc.v:42139$1542_Y + connect \$1123 $ternary$libresoc.v:42140$1543_Y + connect \$1125 $and$libresoc.v:42141$1544_Y + connect \$1128 $and$libresoc.v:42142$1545_Y + connect \$1132 $not$libresoc.v:42143$1546_Y + connect \$1134 $and$libresoc.v:42144$1547_Y + connect \$1138 $and$libresoc.v:42145$1548_Y + connect \$1141 $ternary$libresoc.v:42146$1549_Y + connect \$1143 $and$libresoc.v:42147$1550_Y + connect \$1146 $and$libresoc.v:42148$1551_Y + connect \$1149 $not$libresoc.v:42149$1552_Y + connect \$1151 $and$libresoc.v:42150$1553_Y + connect \$1154 $and$libresoc.v:42151$1554_Y + connect \$1157 $ternary$libresoc.v:42152$1555_Y + connect \$1160 $or$libresoc.v:42153$1556_Y + connect \$1162 $or$libresoc.v:42154$1557_Y + connect \$1164 $or$libresoc.v:42155$1558_Y + connect \$1166 $or$libresoc.v:42156$1559_Y + connect \$1168 $or$libresoc.v:42157$1560_Y + connect \$1170 $or$libresoc.v:42158$1561_Y + connect \$1172 $or$libresoc.v:42159$1562_Y + connect \$1174 $or$libresoc.v:42160$1563_Y + connect \$1176 $or$libresoc.v:42161$1564_Y + connect \$1179 $or$libresoc.v:42162$1565_Y + connect \$1181 $or$libresoc.v:42163$1566_Y + connect \$1183 $or$libresoc.v:42164$1567_Y + connect \$1185 $or$libresoc.v:42165$1568_Y + connect \$1187 $or$libresoc.v:42166$1569_Y + connect \$1189 $or$libresoc.v:42167$1570_Y + connect \$1191 $or$libresoc.v:42168$1571_Y + connect \$1193 $or$libresoc.v:42169$1572_Y + connect \$1195 $or$libresoc.v:42170$1573_Y + connect \$1197 $or$libresoc.v:42171$1574_Y + connect \$1199 $or$libresoc.v:42172$1575_Y + connect \$1201 $or$libresoc.v:42173$1576_Y + connect \$1203 $or$libresoc.v:42174$1577_Y + connect \$1205 $or$libresoc.v:42175$1578_Y + connect \$1207 $or$libresoc.v:42176$1579_Y + connect \$1209 $or$libresoc.v:42177$1580_Y + connect \$1211 $or$libresoc.v:42178$1581_Y + connect \$1213 $or$libresoc.v:42179$1582_Y + connect \$1215 $and$libresoc.v:42180$1583_Y + connect \$1217 $and$libresoc.v:42181$1584_Y + connect \$1220 $and$libresoc.v:42182$1585_Y + connect \$1223 $not$libresoc.v:42183$1586_Y + connect \$1225 $and$libresoc.v:42184$1587_Y + connect \$1228 $and$libresoc.v:42185$1588_Y + connect \$1231 $ternary$libresoc.v:42186$1589_Y + connect \$1233 $and$libresoc.v:42187$1590_Y + connect \$1235 $and$libresoc.v:42188$1591_Y + connect \$1237 $and$libresoc.v:42189$1592_Y + connect \$1239 $and$libresoc.v:42190$1593_Y + connect \$1241 $and$libresoc.v:42191$1594_Y + connect \$1243 $and$libresoc.v:42192$1595_Y + connect \$1245 $and$libresoc.v:42193$1596_Y + connect \$1248 $and$libresoc.v:42194$1597_Y + connect \$1251 $not$libresoc.v:42195$1598_Y + connect \$1253 $and$libresoc.v:42196$1599_Y + connect \$1256 $and$libresoc.v:42197$1600_Y + connect \$1259 $sub$libresoc.v:42198$1601_Y + connect \$1261 $sshl$libresoc.v:42199$1602_Y + connect \$1263 $ternary$libresoc.v:42200$1603_Y + connect \$1265 $and$libresoc.v:42201$1604_Y + connect \$1268 $and$libresoc.v:42202$1605_Y + connect \$1271 $not$libresoc.v:42203$1606_Y + connect \$1273 $and$libresoc.v:42204$1607_Y + connect \$1276 $and$libresoc.v:42205$1608_Y + connect \$1279 $sub$libresoc.v:42206$1609_Y + connect \$1281 $sshl$libresoc.v:42207$1610_Y + connect \$1283 $ternary$libresoc.v:42208$1611_Y + connect \$1285 $and$libresoc.v:42209$1612_Y + connect \$1288 $and$libresoc.v:42210$1613_Y + connect \$1291 $not$libresoc.v:42211$1614_Y + connect \$1293 $and$libresoc.v:42212$1615_Y + connect \$1296 $and$libresoc.v:42213$1616_Y + connect \$1299 $sub$libresoc.v:42214$1617_Y + connect \$1301 $sshl$libresoc.v:42215$1618_Y + connect \$1303 $ternary$libresoc.v:42216$1619_Y + connect \$1305 $and$libresoc.v:42217$1620_Y + connect \$1308 $and$libresoc.v:42218$1621_Y + connect \$1311 $not$libresoc.v:42219$1622_Y + connect \$1313 $and$libresoc.v:42220$1623_Y + connect \$1316 $and$libresoc.v:42221$1624_Y + connect \$1319 $sub$libresoc.v:42222$1625_Y + connect \$1321 $sshl$libresoc.v:42223$1626_Y + connect \$1323 $ternary$libresoc.v:42224$1627_Y + connect \$1325 $and$libresoc.v:42225$1628_Y + connect \$1328 $and$libresoc.v:42226$1629_Y + connect \$1331 $not$libresoc.v:42227$1630_Y + connect \$1333 $and$libresoc.v:42228$1631_Y + connect \$1336 $and$libresoc.v:42229$1632_Y + connect \$1339 $sub$libresoc.v:42230$1633_Y + connect \$1341 $sshl$libresoc.v:42231$1634_Y + connect \$1343 $ternary$libresoc.v:42232$1635_Y + connect \$1345 $and$libresoc.v:42233$1636_Y + connect \$1348 $and$libresoc.v:42234$1637_Y + connect \$1351 $not$libresoc.v:42235$1638_Y + connect \$1353 $and$libresoc.v:42236$1639_Y + connect \$1356 $and$libresoc.v:42237$1640_Y + connect \$1359 $sub$libresoc.v:42238$1641_Y + connect \$1361 $sshl$libresoc.v:42239$1642_Y + connect \$1363 $ternary$libresoc.v:42240$1643_Y + connect \$1365 $or$libresoc.v:42241$1644_Y + connect \$1367 $or$libresoc.v:42242$1645_Y + connect \$1369 $or$libresoc.v:42243$1646_Y + connect \$1371 $or$libresoc.v:42244$1647_Y + connect \$1373 $or$libresoc.v:42245$1648_Y + connect \$1376 $or$libresoc.v:42246$1649_Y + connect \$1378 $or$libresoc.v:42247$1650_Y + connect \$1380 $or$libresoc.v:42248$1651_Y + connect \$1382 $or$libresoc.v:42249$1652_Y + connect \$1384 $or$libresoc.v:42250$1653_Y + connect \$1386 $and$libresoc.v:42251$1654_Y + connect \$1388 $and$libresoc.v:42252$1655_Y + connect \$1390 $and$libresoc.v:42253$1656_Y + connect \$1392 $and$libresoc.v:42254$1657_Y + connect \$1395 $and$libresoc.v:42255$1658_Y + connect \$1398 $not$libresoc.v:42256$1659_Y + connect \$1400 $and$libresoc.v:42257$1660_Y + connect \$1403 $and$libresoc.v:42258$1661_Y + connect \$1406 $ternary$libresoc.v:42259$1662_Y + connect \$1408 $and$libresoc.v:42260$1663_Y + connect \$1411 $and$libresoc.v:42261$1664_Y + connect \$1414 $not$libresoc.v:42262$1665_Y + connect \$1416 $and$libresoc.v:42263$1666_Y + connect \$1419 $and$libresoc.v:42264$1667_Y + connect \$1422 $ternary$libresoc.v:42265$1668_Y + connect \$1424 $and$libresoc.v:42266$1669_Y + connect \$1427 $and$libresoc.v:42267$1670_Y + connect \$1430 $not$libresoc.v:42268$1671_Y + connect \$1432 $and$libresoc.v:42269$1672_Y + connect \$1435 $and$libresoc.v:42270$1673_Y + connect \$1438 $ternary$libresoc.v:42271$1674_Y + connect \$1440 $or$libresoc.v:42272$1675_Y + connect \$1442 $or$libresoc.v:42273$1676_Y + connect \$1445 $or$libresoc.v:42274$1677_Y + connect \$1447 $or$libresoc.v:42275$1678_Y + connect \$1444 $pos$libresoc.v:42276$1680_Y + connect \$1450 $and$libresoc.v:42277$1681_Y + connect \$1452 $and$libresoc.v:42278$1682_Y + connect \$1454 $and$libresoc.v:42279$1683_Y + connect \$1456 $and$libresoc.v:42280$1684_Y + connect \$1458 $and$libresoc.v:42281$1685_Y + connect \$1461 $and$libresoc.v:42282$1686_Y + connect \$1464 $not$libresoc.v:42283$1687_Y + connect \$1466 $and$libresoc.v:42284$1688_Y + connect \$1469 $and$libresoc.v:42285$1689_Y + connect \$1472 $ternary$libresoc.v:42286$1690_Y + connect \$1474 $and$libresoc.v:42287$1691_Y + connect \$1477 $and$libresoc.v:42288$1692_Y + connect \$1480 $not$libresoc.v:42289$1693_Y + connect \$1482 $and$libresoc.v:42290$1694_Y + connect \$1485 $and$libresoc.v:42291$1695_Y + connect \$1488 $ternary$libresoc.v:42292$1696_Y + connect \$1490 $and$libresoc.v:42293$1697_Y + connect \$1493 $and$libresoc.v:42294$1698_Y + connect \$1496 $not$libresoc.v:42295$1699_Y + connect \$1498 $and$libresoc.v:42296$1700_Y + connect \$1501 $and$libresoc.v:42297$1701_Y + connect \$1504 $ternary$libresoc.v:42298$1702_Y + connect \$1506 $and$libresoc.v:42299$1703_Y + connect \$1509 $and$libresoc.v:42300$1704_Y + connect \$1512 $not$libresoc.v:42301$1705_Y + connect \$1514 $and$libresoc.v:42302$1706_Y + connect \$1517 $and$libresoc.v:42303$1707_Y + connect \$1520 $ternary$libresoc.v:42304$1708_Y + connect \$1522 $or$libresoc.v:42305$1709_Y + connect \$1524 $or$libresoc.v:42306$1710_Y + connect \$1526 $or$libresoc.v:42307$1711_Y + connect \$1528 $or$libresoc.v:42308$1712_Y + connect \$1530 $or$libresoc.v:42309$1713_Y + connect \$1532 $or$libresoc.v:42310$1714_Y + connect \$1534 $and$libresoc.v:42311$1715_Y + connect \$1536 $and$libresoc.v:42312$1716_Y + connect \$1538 $and$libresoc.v:42313$1717_Y + connect \$1540 $and$libresoc.v:42314$1718_Y + connect \$1542 $and$libresoc.v:42315$1719_Y + connect \$1545 $and$libresoc.v:42316$1720_Y + connect \$1548 $not$libresoc.v:42317$1721_Y + connect \$1550 $and$libresoc.v:42318$1722_Y + connect \$1553 $and$libresoc.v:42319$1723_Y + connect \$1556 $ternary$libresoc.v:42320$1724_Y + connect \$1558 $and$libresoc.v:42321$1725_Y + connect \$1561 $and$libresoc.v:42322$1726_Y + connect \$1564 $not$libresoc.v:42323$1727_Y + connect \$1566 $and$libresoc.v:42324$1728_Y + connect \$1569 $and$libresoc.v:42325$1729_Y + connect \$1572 $ternary$libresoc.v:42326$1730_Y + connect \$1574 $and$libresoc.v:42327$1731_Y + connect \$1577 $and$libresoc.v:42328$1732_Y + connect \$1580 $not$libresoc.v:42329$1733_Y + connect \$1582 $and$libresoc.v:42330$1734_Y + connect \$1585 $and$libresoc.v:42331$1735_Y + connect \$1588 $ternary$libresoc.v:42332$1736_Y + connect \$1590 $and$libresoc.v:42333$1737_Y + connect \$1593 $and$libresoc.v:42334$1738_Y + connect \$1596 $not$libresoc.v:42335$1739_Y + connect \$1598 $and$libresoc.v:42336$1740_Y + connect \$1601 $and$libresoc.v:42337$1741_Y + connect \$1604 $ternary$libresoc.v:42338$1742_Y + connect \$1607 $or$libresoc.v:42339$1743_Y + connect \$1609 $or$libresoc.v:42340$1744_Y + connect \$1611 $or$libresoc.v:42341$1745_Y + connect \$1606 $pos$libresoc.v:42342$1747_Y + connect \$1615 $or$libresoc.v:42343$1748_Y + connect \$1617 $or$libresoc.v:42344$1749_Y + connect \$1619 $or$libresoc.v:42345$1750_Y + connect \$1614 $pos$libresoc.v:42346$1752_Y + connect \$1622 $and$libresoc.v:42347$1753_Y + connect \$1624 $and$libresoc.v:42348$1754_Y + connect \$1626 $and$libresoc.v:42349$1755_Y + connect \$1628 $and$libresoc.v:42350$1756_Y + connect \$1630 $and$libresoc.v:42351$1757_Y + connect \$1632 $and$libresoc.v:42352$1758_Y + connect \$1635 $and$libresoc.v:42353$1759_Y + connect \$1639 $not$libresoc.v:42354$1760_Y + connect \$1641 $and$libresoc.v:42355$1761_Y + connect \$1646 $and$libresoc.v:42356$1762_Y + connect \$1649 $ternary$libresoc.v:42357$1763_Y + connect \$1651 $and$libresoc.v:42358$1764_Y + connect \$1654 $and$libresoc.v:42359$1765_Y + connect \$1657 $not$libresoc.v:42360$1766_Y + connect \$1659 $and$libresoc.v:42361$1767_Y + connect \$1662 $and$libresoc.v:42362$1768_Y + connect \$1665 $ternary$libresoc.v:42363$1769_Y + connect \$1667 $and$libresoc.v:42364$1770_Y + connect \$1670 $and$libresoc.v:42365$1771_Y + connect \$1673 $not$libresoc.v:42366$1772_Y + connect \$1675 $and$libresoc.v:42367$1773_Y + connect \$1678 $and$libresoc.v:42368$1774_Y + connect \$1681 $ternary$libresoc.v:42369$1775_Y + connect \$1683 $and$libresoc.v:42370$1776_Y + connect \$1686 $and$libresoc.v:42371$1777_Y + connect \$1689 $not$libresoc.v:42372$1778_Y + connect \$1691 $and$libresoc.v:42373$1779_Y + connect \$1694 $and$libresoc.v:42374$1780_Y + connect \$1697 $ternary$libresoc.v:42375$1781_Y + connect \$1699 $and$libresoc.v:42376$1782_Y + connect \$1702 $and$libresoc.v:42377$1783_Y + connect \$1705 $not$libresoc.v:42378$1784_Y + connect \$1707 $and$libresoc.v:42379$1785_Y + connect \$1710 $and$libresoc.v:42380$1786_Y + connect \$1713 $ternary$libresoc.v:42381$1787_Y + connect \$1715 $or$libresoc.v:42382$1788_Y + connect \$1717 $or$libresoc.v:42383$1789_Y + connect \$1719 $or$libresoc.v:42384$1790_Y + connect \$1721 $or$libresoc.v:42385$1791_Y + connect \$1723 $or$libresoc.v:42386$1792_Y + connect \$1725 $or$libresoc.v:42387$1793_Y + connect \$1727 $or$libresoc.v:42388$1794_Y + connect \$1729 $or$libresoc.v:42389$1795_Y + connect \$1731 $or$libresoc.v:42390$1796_Y + connect \$1733 $or$libresoc.v:42391$1797_Y + connect \$1735 $or$libresoc.v:42392$1798_Y + connect \$1737 $or$libresoc.v:42393$1799_Y + connect \$1739 $and$libresoc.v:42394$1800_Y + connect \$1741 $and$libresoc.v:42395$1801_Y + connect \$1743 $and$libresoc.v:42396$1802_Y + connect \$1746 $and$libresoc.v:42397$1803_Y + connect \$1749 $not$libresoc.v:42398$1804_Y + connect \$1751 $and$libresoc.v:42399$1805_Y + connect \$1754 $and$libresoc.v:42400$1806_Y + connect \$1757 $ternary$libresoc.v:42401$1807_Y + connect \$1759 $and$libresoc.v:42402$1808_Y + connect \$1762 $and$libresoc.v:42403$1809_Y + connect \$1765 $not$libresoc.v:42404$1810_Y + connect \$1767 $and$libresoc.v:42405$1811_Y + connect \$1770 $and$libresoc.v:42406$1812_Y + connect \$1773 $ternary$libresoc.v:42407$1813_Y + connect \$1775 $or$libresoc.v:42408$1814_Y + connect \$1778 $or$libresoc.v:42409$1815_Y + connect \$1777 $pos$libresoc.v:42410$1817_Y + connect \$1781 $and$libresoc.v:42411$1818_Y + connect \$1783 $and$libresoc.v:42412$1819_Y + connect \$1786 $and$libresoc.v:42413$1820_Y + connect \$1789 $not$libresoc.v:42414$1821_Y + connect \$1791 $and$libresoc.v:42415$1822_Y + connect \$1794 $and$libresoc.v:42416$1823_Y + connect \$1797 $ternary$libresoc.v:42417$1824_Y + connect \$1799 $pos$libresoc.v:42418$1826_Y + connect \$1801 $and$libresoc.v:42419$1827_Y + connect \$1803 $and$libresoc.v:42420$1828_Y + connect \$1806 $and$libresoc.v:42421$1829_Y + connect \$1809 $not$libresoc.v:42422$1830_Y + connect \$1811 $and$libresoc.v:42423$1831_Y + connect \$1814 $and$libresoc.v:42424$1832_Y + connect \$1817 $ternary$libresoc.v:42425$1833_Y + connect \$182 $and$libresoc.v:42426$1834_Y + connect \$181 $reduce_or$libresoc.v:42427$1835_Y + connect \$186 $and$libresoc.v:42428$1836_Y + connect \$185 $reduce_or$libresoc.v:42429$1837_Y + connect \$190 $and$libresoc.v:42430$1838_Y + connect \$189 $reduce_or$libresoc.v:42431$1839_Y + connect \$194 $and$libresoc.v:42432$1840_Y + connect \$193 $reduce_or$libresoc.v:42433$1841_Y + connect \$198 $and$libresoc.v:42434$1842_Y + connect \$197 $reduce_or$libresoc.v:42435$1843_Y + connect \$202 $and$libresoc.v:42436$1844_Y + connect \$201 $reduce_or$libresoc.v:42437$1845_Y + connect \$206 $and$libresoc.v:42438$1846_Y + connect \$205 $reduce_or$libresoc.v:42439$1847_Y + connect \$210 $and$libresoc.v:42440$1848_Y + connect \$209 $reduce_or$libresoc.v:42441$1849_Y + connect \$214 $and$libresoc.v:42442$1850_Y + connect \$213 $reduce_or$libresoc.v:42443$1851_Y + connect \$218 $and$libresoc.v:42444$1852_Y + connect \$217 $reduce_or$libresoc.v:42445$1853_Y + connect \$221 $ne$libresoc.v:42446$1854_Y + connect \$224 $sub$libresoc.v:42447$1855_Y + connect \$226 $ne$libresoc.v:42448$1856_Y + connect \$229 $and$libresoc.v:42449$1857_Y + connect \$231 $and$libresoc.v:42450$1858_Y + connect \$233 $eq$libresoc.v:42451$1859_Y + connect \$235 $or$libresoc.v:42452$1860_Y + connect \$237 $and$libresoc.v:42453$1861_Y + connect \$239 $or$libresoc.v:42454$1862_Y + connect \$241 $eq$libresoc.v:42455$1863_Y + connect \$243 $and$libresoc.v:42456$1864_Y + connect \$245 $eq$libresoc.v:42457$1865_Y + connect \$247 $or$libresoc.v:42458$1866_Y + connect \$228 $not$libresoc.v:42459$1867_Y + connect \$250 $not$libresoc.v:42460$1868_Y + connect \$252 $not$libresoc.v:42461$1869_Y + connect \$254 $not$libresoc.v:42462$1870_Y + connect \$257 $and$libresoc.v:42463$1871_Y + connect \$259 $and$libresoc.v:42464$1872_Y + connect \$261 $eq$libresoc.v:42465$1873_Y + connect \$263 $or$libresoc.v:42466$1874_Y + connect \$265 $and$libresoc.v:42467$1875_Y + connect \$267 $or$libresoc.v:42468$1876_Y + connect \$256 $not$libresoc.v:42469$1877_Y + connect \$271 $and$libresoc.v:42470$1878_Y + connect \$273 $and$libresoc.v:42471$1879_Y + connect \$275 $eq$libresoc.v:42472$1880_Y + connect \$277 $or$libresoc.v:42473$1881_Y + connect \$279 $and$libresoc.v:42474$1882_Y + connect \$281 $or$libresoc.v:42475$1883_Y + connect \$283 $and$libresoc.v:42476$1884_Y + connect \$285 $and$libresoc.v:42477$1885_Y + connect \$287 $eq$libresoc.v:42478$1886_Y + connect \$289 $or$libresoc.v:42479$1887_Y + connect \$291 $eq$libresoc.v:42480$1888_Y + connect \$293 $and$libresoc.v:42481$1889_Y + connect \$295 $eq$libresoc.v:42482$1890_Y + connect \$297 $or$libresoc.v:42483$1891_Y + connect \$270 $not$libresoc.v:42484$1892_Y + connect \$301 $and$libresoc.v:42485$1893_Y + connect \$303 $and$libresoc.v:42486$1894_Y + connect \$305 $eq$libresoc.v:42487$1895_Y + connect \$307 $or$libresoc.v:42488$1896_Y + connect \$309 $and$libresoc.v:42489$1897_Y + connect \$311 $or$libresoc.v:42490$1898_Y + connect \$300 $not$libresoc.v:42491$1899_Y + connect \$315 $and$libresoc.v:42492$1900_Y + connect \$317 $and$libresoc.v:42493$1901_Y + connect \$319 $eq$libresoc.v:42494$1902_Y + connect \$321 $or$libresoc.v:42495$1903_Y + connect \$323 $and$libresoc.v:42496$1904_Y + connect \$325 $or$libresoc.v:42497$1905_Y + connect \$314 $not$libresoc.v:42498$1906_Y + connect \$329 $and$libresoc.v:42499$1907_Y + connect \$331 $and$libresoc.v:42500$1908_Y + connect \$333 $eq$libresoc.v:42501$1909_Y + connect \$335 $or$libresoc.v:42502$1910_Y + connect \$337 $and$libresoc.v:42503$1911_Y + connect \$339 $or$libresoc.v:42504$1912_Y + connect \$341 $eq$libresoc.v:42505$1913_Y + connect \$343 $and$libresoc.v:42506$1914_Y + connect \$345 $eq$libresoc.v:42507$1915_Y + connect \$347 $or$libresoc.v:42508$1916_Y + connect \$328 $not$libresoc.v:42509$1917_Y + connect \$350 $not$libresoc.v:42510$1918_Y + connect \$352 $and$libresoc.v:42511$1919_Y + connect \$354 $and$libresoc.v:42512$1920_Y + connect \$356 $not$libresoc.v:42513$1921_Y + connect \$358 $and$libresoc.v:42514$1922_Y + connect \$360 $and$libresoc.v:42515$1923_Y + connect \$362 $ternary$libresoc.v:42516$1924_Y + connect \$364 $and$libresoc.v:42517$1925_Y + connect \$366 $and$libresoc.v:42518$1926_Y + connect \$368 $not$libresoc.v:42519$1927_Y + connect \$370 $and$libresoc.v:42520$1928_Y + connect \$372 $and$libresoc.v:42521$1929_Y + connect \$374 $ternary$libresoc.v:42522$1930_Y + connect \$376 $and$libresoc.v:42523$1931_Y + connect \$378 $and$libresoc.v:42524$1932_Y + connect \$380 $not$libresoc.v:42525$1933_Y + connect \$382 $and$libresoc.v:42526$1934_Y + connect \$384 $and$libresoc.v:42527$1935_Y + connect \$386 $ternary$libresoc.v:42528$1936_Y + connect \$388 $and$libresoc.v:42529$1937_Y + connect \$390 $and$libresoc.v:42530$1938_Y + connect \$392 $not$libresoc.v:42531$1939_Y + connect \$394 $and$libresoc.v:42532$1940_Y + connect \$396 $and$libresoc.v:42533$1941_Y + connect \$398 $ternary$libresoc.v:42534$1942_Y + connect \$400 $and$libresoc.v:42535$1943_Y + connect \$402 $and$libresoc.v:42536$1944_Y + connect \$404 $not$libresoc.v:42537$1945_Y + connect \$406 $and$libresoc.v:42538$1946_Y + connect \$408 $and$libresoc.v:42539$1947_Y + connect \$410 $ternary$libresoc.v:42540$1948_Y + connect \$412 $and$libresoc.v:42541$1949_Y + connect \$414 $and$libresoc.v:42542$1950_Y + connect \$416 $not$libresoc.v:42543$1951_Y + connect \$418 $and$libresoc.v:42544$1952_Y + connect \$420 $and$libresoc.v:42545$1953_Y + connect \$422 $ternary$libresoc.v:42546$1954_Y + connect \$424 $and$libresoc.v:42547$1955_Y + connect \$426 $and$libresoc.v:42548$1956_Y + connect \$428 $not$libresoc.v:42549$1957_Y + connect \$430 $and$libresoc.v:42550$1958_Y + connect \$432 $and$libresoc.v:42551$1959_Y + connect \$434 $ternary$libresoc.v:42552$1960_Y + connect \$436 $and$libresoc.v:42553$1961_Y + connect \$438 $and$libresoc.v:42554$1962_Y + connect \$440 $not$libresoc.v:42555$1963_Y + connect \$442 $and$libresoc.v:42556$1964_Y + connect \$444 $and$libresoc.v:42557$1965_Y + connect \$446 $ternary$libresoc.v:42558$1966_Y + connect \$448 $and$libresoc.v:42559$1967_Y + connect \$450 $and$libresoc.v:42560$1968_Y + connect \$452 $not$libresoc.v:42561$1969_Y + connect \$454 $and$libresoc.v:42562$1970_Y + connect \$456 $and$libresoc.v:42563$1971_Y + connect \$458 $ternary$libresoc.v:42564$1972_Y + connect \$461 $or$libresoc.v:42565$1973_Y + connect \$463 $or$libresoc.v:42566$1974_Y + connect \$465 $or$libresoc.v:42567$1975_Y + connect \$467 $or$libresoc.v:42568$1976_Y + connect \$469 $or$libresoc.v:42569$1977_Y + connect \$471 $or$libresoc.v:42570$1978_Y + connect \$473 $or$libresoc.v:42571$1979_Y + connect \$475 $or$libresoc.v:42572$1980_Y + connect \$477 $reduce_or$libresoc.v:42573$1981_Y + connect \$479 $and$libresoc.v:42574$1982_Y + connect \$481 $and$libresoc.v:42575$1983_Y + connect \$483 $not$libresoc.v:42576$1984_Y + connect \$485 $and$libresoc.v:42577$1985_Y + connect \$487 $and$libresoc.v:42578$1986_Y + connect \$489 $ternary$libresoc.v:42579$1987_Y + connect \$491 $and$libresoc.v:42580$1988_Y + connect \$493 $and$libresoc.v:42581$1989_Y + connect \$495 $not$libresoc.v:42582$1990_Y + connect \$497 $and$libresoc.v:42583$1991_Y + connect \$499 $and$libresoc.v:42584$1992_Y + connect \$501 $ternary$libresoc.v:42585$1993_Y + connect \$503 $and$libresoc.v:42586$1994_Y + connect \$505 $and$libresoc.v:42587$1995_Y + connect \$507 $not$libresoc.v:42588$1996_Y + connect \$509 $and$libresoc.v:42589$1997_Y + connect \$511 $and$libresoc.v:42590$1998_Y + connect \$513 $ternary$libresoc.v:42591$1999_Y + connect \$515 $and$libresoc.v:42592$2000_Y + connect \$517 $and$libresoc.v:42593$2001_Y + connect \$519 $not$libresoc.v:42594$2002_Y + connect \$521 $and$libresoc.v:42595$2003_Y + connect \$523 $and$libresoc.v:42596$2004_Y + connect \$525 $ternary$libresoc.v:42597$2005_Y + connect \$527 $and$libresoc.v:42598$2006_Y + connect \$529 $and$libresoc.v:42599$2007_Y + connect \$531 $not$libresoc.v:42600$2008_Y + connect \$533 $and$libresoc.v:42601$2009_Y + connect \$535 $and$libresoc.v:42602$2010_Y + connect \$537 $ternary$libresoc.v:42603$2011_Y + connect \$539 $and$libresoc.v:42604$2012_Y + connect \$541 $and$libresoc.v:42605$2013_Y + connect \$543 $not$libresoc.v:42606$2014_Y + connect \$545 $and$libresoc.v:42607$2015_Y + connect \$547 $and$libresoc.v:42608$2016_Y + connect \$549 $ternary$libresoc.v:42609$2017_Y + connect \$551 $and$libresoc.v:42610$2018_Y + connect \$553 $and$libresoc.v:42611$2019_Y + connect \$555 $not$libresoc.v:42612$2020_Y + connect \$557 $and$libresoc.v:42613$2021_Y + connect \$559 $and$libresoc.v:42614$2022_Y + connect \$561 $ternary$libresoc.v:42615$2023_Y + connect \$563 $and$libresoc.v:42616$2024_Y + connect \$565 $and$libresoc.v:42617$2025_Y + connect \$567 $not$libresoc.v:42618$2026_Y + connect \$569 $and$libresoc.v:42619$2027_Y + connect \$571 $and$libresoc.v:42620$2028_Y + connect \$573 $ternary$libresoc.v:42621$2029_Y + connect \$576 $or$libresoc.v:42622$2030_Y + connect \$578 $or$libresoc.v:42623$2031_Y + connect \$580 $or$libresoc.v:42624$2032_Y + connect \$582 $or$libresoc.v:42625$2033_Y + connect \$584 $or$libresoc.v:42626$2034_Y + connect \$586 $or$libresoc.v:42627$2035_Y + connect \$588 $or$libresoc.v:42628$2036_Y + connect \$590 $reduce_or$libresoc.v:42629$2037_Y + connect \$592 $and$libresoc.v:42630$2038_Y + connect \$594 $and$libresoc.v:42631$2039_Y + connect \$596 $not$libresoc.v:42632$2040_Y + connect \$598 $and$libresoc.v:42633$2041_Y + connect \$600 $and$libresoc.v:42634$2042_Y + connect \$602 $ternary$libresoc.v:42635$2043_Y + connect \$604 $and$libresoc.v:42636$2044_Y + connect \$606 $and$libresoc.v:42637$2045_Y + connect \$608 $not$libresoc.v:42638$2046_Y + connect \$610 $and$libresoc.v:42639$2047_Y + connect \$612 $and$libresoc.v:42640$2048_Y + connect \$614 $ternary$libresoc.v:42641$2049_Y + connect \$617 $or$libresoc.v:42642$2050_Y + connect \$619 $reduce_or$libresoc.v:42643$2051_Y + connect \$621 $and$libresoc.v:42644$2052_Y + connect \$623 $and$libresoc.v:42645$2053_Y + connect \$625 $eq$libresoc.v:42646$2054_Y + connect \$627 $or$libresoc.v:42647$2055_Y + connect \$629 $and$libresoc.v:42648$2056_Y + connect \$631 $or$libresoc.v:42649$2057_Y + connect \$633 $and$libresoc.v:42650$2058_Y + connect \$635 $and$libresoc.v:42651$2059_Y + connect \$637 $not$libresoc.v:42652$2060_Y + connect \$639 $and$libresoc.v:42653$2061_Y + connect \$641 $and$libresoc.v:42654$2062_Y + connect \$643 $ternary$libresoc.v:42655$2063_Y + connect \$645 $and$libresoc.v:42656$2064_Y + connect \$647 $and$libresoc.v:42657$2065_Y + connect \$649 $not$libresoc.v:42658$2066_Y + connect \$651 $and$libresoc.v:42659$2067_Y + connect \$653 $and$libresoc.v:42660$2068_Y + connect \$655 $ternary$libresoc.v:42661$2069_Y + connect \$657 $and$libresoc.v:42662$2070_Y + connect \$659 $and$libresoc.v:42663$2071_Y + connect \$661 $not$libresoc.v:42664$2072_Y + connect \$663 $and$libresoc.v:42665$2073_Y + connect \$665 $and$libresoc.v:42666$2074_Y + connect \$667 $ternary$libresoc.v:42667$2075_Y + connect \$669 $and$libresoc.v:42668$2076_Y + connect \$671 $and$libresoc.v:42669$2077_Y + connect \$673 $not$libresoc.v:42670$2078_Y + connect \$675 $and$libresoc.v:42671$2079_Y + connect \$677 $and$libresoc.v:42672$2080_Y + connect \$679 $ternary$libresoc.v:42673$2081_Y + connect \$681 $and$libresoc.v:42674$2082_Y + connect \$683 $and$libresoc.v:42675$2083_Y + connect \$685 $not$libresoc.v:42676$2084_Y + connect \$687 $and$libresoc.v:42677$2085_Y + connect \$689 $and$libresoc.v:42678$2086_Y + connect \$691 $ternary$libresoc.v:42679$2087_Y + connect \$693 $and$libresoc.v:42680$2088_Y + connect \$695 $and$libresoc.v:42681$2089_Y + connect \$697 $not$libresoc.v:42682$2090_Y + connect \$699 $and$libresoc.v:42683$2091_Y + connect \$701 $and$libresoc.v:42684$2092_Y + connect \$703 $ternary$libresoc.v:42685$2093_Y + connect \$706 $or$libresoc.v:42686$2094_Y + connect \$708 $or$libresoc.v:42687$2095_Y + connect \$710 $or$libresoc.v:42688$2096_Y + connect \$712 $or$libresoc.v:42689$2097_Y + connect \$714 $or$libresoc.v:42690$2098_Y + connect \$705 $pos$libresoc.v:42691$2100_Y + connect \$717 $eq$libresoc.v:42692$2101_Y + connect \$719 $and$libresoc.v:42693$2102_Y + connect \$721 $eq$libresoc.v:42694$2103_Y + connect \$723 $or$libresoc.v:42695$2104_Y + connect \$725 $and$libresoc.v:42696$2105_Y + connect \$727 $and$libresoc.v:42697$2106_Y + connect \$729 $not$libresoc.v:42698$2107_Y + connect \$731 $and$libresoc.v:42699$2108_Y + connect \$733 $and$libresoc.v:42700$2109_Y + connect \$735 $ternary$libresoc.v:42701$2110_Y + connect \$737 $and$libresoc.v:42702$2111_Y + connect \$739 $and$libresoc.v:42703$2112_Y + connect \$741 $not$libresoc.v:42704$2113_Y + connect \$743 $and$libresoc.v:42705$2114_Y + connect \$745 $and$libresoc.v:42706$2115_Y + connect \$747 $ternary$libresoc.v:42707$2116_Y + connect \$749 $and$libresoc.v:42708$2117_Y + connect \$751 $and$libresoc.v:42709$2118_Y + connect \$753 $not$libresoc.v:42710$2119_Y + connect \$755 $and$libresoc.v:42711$2120_Y + connect \$757 $and$libresoc.v:42712$2121_Y + connect \$759 $ternary$libresoc.v:42713$2122_Y + connect \$762 $or$libresoc.v:42714$2123_Y + connect \$764 $or$libresoc.v:42715$2124_Y + connect \$761 $pos$libresoc.v:42716$2126_Y + connect \$767 $and$libresoc.v:42717$2127_Y + connect \$769 $and$libresoc.v:42718$2128_Y + connect \$771 $eq$libresoc.v:42719$2129_Y + connect \$773 $or$libresoc.v:42720$2130_Y + connect \$775 $and$libresoc.v:42721$2131_Y + connect \$777 $and$libresoc.v:42722$2132_Y + connect \$779 $not$libresoc.v:42723$2133_Y + connect \$781 $and$libresoc.v:42724$2134_Y + connect \$783 $and$libresoc.v:42725$2135_Y + connect \$785 $ternary$libresoc.v:42726$2136_Y + connect \$787 $and$libresoc.v:42727$2137_Y + connect \$789 $and$libresoc.v:42728$2138_Y + connect \$791 $not$libresoc.v:42729$2139_Y + connect \$793 $and$libresoc.v:42730$2140_Y + connect \$795 $and$libresoc.v:42731$2141_Y + connect \$797 $ternary$libresoc.v:42732$2142_Y + connect \$799 $and$libresoc.v:42733$2143_Y + connect \$801 $and$libresoc.v:42734$2144_Y + connect \$803 $not$libresoc.v:42735$2145_Y + connect \$805 $and$libresoc.v:42736$2146_Y + connect \$807 $and$libresoc.v:42737$2147_Y + connect \$809 $sub$libresoc.v:42738$2148_Y + connect \$811 $sshl$libresoc.v:42739$2149_Y + connect \$813 $ternary$libresoc.v:42740$2150_Y + connect \$815 $and$libresoc.v:42741$2151_Y + connect \$817 $and$libresoc.v:42742$2152_Y + connect \$819 $not$libresoc.v:42743$2153_Y + connect \$821 $and$libresoc.v:42744$2154_Y + connect \$823 $and$libresoc.v:42745$2155_Y + connect \$825 $sub$libresoc.v:42746$2156_Y + connect \$827 $sshl$libresoc.v:42747$2157_Y + connect \$829 $ternary$libresoc.v:42748$2158_Y + connect \$832 $or$libresoc.v:42749$2159_Y + connect \$834 $and$libresoc.v:42750$2160_Y + connect \$836 $and$libresoc.v:42751$2161_Y + connect \$838 $not$libresoc.v:42752$2162_Y + connect \$840 $and$libresoc.v:42753$2163_Y + connect \$842 $and$libresoc.v:42754$2164_Y + connect \$844 $sub$libresoc.v:42755$2165_Y + connect \$846 $sshl$libresoc.v:42756$2166_Y + connect \$848 $ternary$libresoc.v:42757$2167_Y + connect \$850 $and$libresoc.v:42758$2168_Y + connect \$852 $and$libresoc.v:42759$2169_Y + connect \$854 $not$libresoc.v:42760$2170_Y + connect \$856 $and$libresoc.v:42761$2171_Y + connect \$858 $and$libresoc.v:42762$2172_Y + connect \$860 $sub$libresoc.v:42763$2173_Y + connect \$862 $sshl$libresoc.v:42764$2174_Y + connect \$864 $ternary$libresoc.v:42765$2175_Y + connect \$866 $and$libresoc.v:42766$2176_Y + connect \$868 $and$libresoc.v:42767$2177_Y + connect \$870 $not$libresoc.v:42768$2178_Y + connect \$872 $and$libresoc.v:42769$2179_Y + connect \$874 $and$libresoc.v:42770$2180_Y + connect \$876 $ternary$libresoc.v:42771$2181_Y + connect \$878 $and$libresoc.v:42772$2182_Y + connect \$880 $and$libresoc.v:42773$2183_Y + connect \$882 $not$libresoc.v:42774$2184_Y + connect \$884 $and$libresoc.v:42775$2185_Y + connect \$886 $and$libresoc.v:42776$2186_Y + connect \$888 $ternary$libresoc.v:42777$2187_Y + connect \$890 $and$libresoc.v:42778$2188_Y + connect \$892 $and$libresoc.v:42779$2189_Y + connect \$894 $not$libresoc.v:42780$2190_Y + connect \$896 $and$libresoc.v:42781$2191_Y + connect \$898 $and$libresoc.v:42782$2192_Y + connect \$900 $ternary$libresoc.v:42783$2193_Y + connect \$902 $or$libresoc.v:42784$2194_Y + connect \$904 $or$libresoc.v:42785$2195_Y + connect \$906 $reduce_or$libresoc.v:42786$2196_Y + connect \$908 $and$libresoc.v:42787$2197_Y + connect \$910 $and$libresoc.v:42788$2198_Y + connect \$912 $not$libresoc.v:42789$2199_Y + connect \$914 $and$libresoc.v:42790$2200_Y + connect \$916 $and$libresoc.v:42791$2201_Y + connect \$918 $ternary$libresoc.v:42792$2202_Y + connect \$920 $and$libresoc.v:42793$2203_Y + connect \$922 $and$libresoc.v:42794$2204_Y + connect \$924 $not$libresoc.v:42795$2205_Y + connect \$926 $and$libresoc.v:42796$2206_Y + connect \$928 $and$libresoc.v:42797$2207_Y + connect \$930 $ternary$libresoc.v:42798$2208_Y + connect \$932 $or$libresoc.v:42799$2209_Y + connect \$934 $reduce_or$libresoc.v:42800$2210_Y + connect \$936 $and$libresoc.v:42801$2211_Y + connect \$938 $and$libresoc.v:42802$2212_Y + connect \$940 $not$libresoc.v:42803$2213_Y + connect \$942 $and$libresoc.v:42804$2214_Y + connect \$944 $and$libresoc.v:42805$2215_Y + connect \$946 $ternary$libresoc.v:42806$2216_Y + connect \$948 $reduce_or$libresoc.v:42807$2217_Y + connect \$950 $and$libresoc.v:42808$2218_Y + connect \$952 $and$libresoc.v:42809$2219_Y + connect \$954 $and$libresoc.v:42810$2220_Y + connect \$956 $and$libresoc.v:42811$2221_Y + connect \$958 $and$libresoc.v:42812$2222_Y + connect \$960 $and$libresoc.v:42813$2223_Y + connect \$962 $and$libresoc.v:42814$2224_Y + connect \$964 $and$libresoc.v:42815$2225_Y + connect \$966 $and$libresoc.v:42816$2226_Y + connect \$968 $and$libresoc.v:42817$2227_Y + connect \$970 $and$libresoc.v:42818$2228_Y + connect \$972 $and$libresoc.v:42819$2229_Y + connect \$974 $not$libresoc.v:42820$2230_Y + connect \$976 $and$libresoc.v:42821$2231_Y + connect \$982 $and$libresoc.v:42822$2232_Y + connect \$984 $ternary$libresoc.v:42823$2233_Y + connect \$986 $and$libresoc.v:42824$2234_Y + connect \$989 $and$libresoc.v:42825$2235_Y + connect \$993 $not$libresoc.v:42826$2236_Y + connect \$995 $and$libresoc.v:42827$2237_Y + connect \$223 \$224 + connect \$460 \$475 + connect \$575 \$588 + connect \$616 \$617 + connect \$831 \$832 + connect \$1159 \$1176 + connect \$1178 \$1195 + connect \$1375 \$1384 + connect \o_ok 1'0 + connect \ea_ok 1'0 + connect \spr_spr1__wen \wp$1813 + connect \spr_spr1__addr$175 \addr_en$1816 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$162 + connect \addr_en$1816 \$1817 + connect \wp$1813 \$1814 + connect \wr_pick_rise$1059 \$1811 + connect \wr_pick$1805 \$1806 + connect \wrpick_SPR_spr1_i \$1803 + connect \wrflag_spr0_spr1_1 \$1801 + connect \state_wen \$1799 + connect \state_data_i$174 \fus_dest5_o$161 + connect \addr_en$1796 \$1797 + connect \wp$1793 \$1794 + connect \wr_pick_rise$1019 \$1791 + connect \wr_pick$1785 \$1786 + connect \wrpick_STATE_msr_i \$1783 + connect \wrflag_trap0_msr_4 \$1781 + connect \state_nia_wen \$1777 + connect \state_data_i \$1775 + connect \addr_en$1772 \$1773 + connect \wp$1769 \$1770 + connect \wr_pick_rise$1018 \$1767 + connect \wr_pick$1761 \$1762 + connect \wrflag_trap0_nia_3 \$1759 + connect \addr_en$1756 \$1757 + connect \wp$1753 \$1754 + connect \wr_pick_rise$1644 \$1751 + connect \wr_pick$1745 \$1746 + connect \wrpick_STATE_nia_i [1] \$1743 + connect \wrpick_STATE_nia_i [0] \$1741 + connect \wrflag_branch0_nia_2 \$1739 + connect \fast_dest1__wen \$1737 + connect \fast_dest1__addr \$1729 + connect \fast_dest1__data_i \$1721 + connect \addr_en$1712 \$1713 + connect \wp$1709 \$1710 + connect \wr_pick_rise$1017 \$1707 + connect \wr_pick$1701 \$1702 + connect \wrflag_trap0_fast1_2 \$1699 + connect \addr_en$1696 \$1697 + connect \wp$1693 \$1694 + connect \wr_pick_rise$1643 \$1691 + connect \wr_pick$1685 \$1686 + connect \wrflag_branch0_fast1_1 \$1683 + connect \addr_en$1680 \$1681 + connect \wp$1677 \$1678 + connect \wr_pick_rise$1058 \$1675 + connect \wr_pick$1669 \$1670 + connect \wrflag_spr0_fast1_2 \$1667 + connect \addr_en$1664 \$1665 + connect \wp$1661 \$1662 + connect \wr_pick_rise$1016 \$1659 + connect \wr_pick$1653 \$1654 + connect \wrflag_trap0_fast1_1 \$1651 + connect \addr_en$1648 \$1649 + connect \wp$1645 \$1646 + connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1644 + connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1643 + connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1638 + connect \wr_pick_rise$1638 \$1641 + connect \wr_pick$1634 \$1635 + connect \wrpick_FAST_fast1_i [4] \$1632 + connect \wrpick_FAST_fast1_i [3] \$1630 + connect \wrpick_FAST_fast1_i [2] \$1628 + connect \wrpick_FAST_fast1_i [1] \$1626 + connect \wrpick_FAST_fast1_i [0] \$1624 + connect \wrflag_branch0_fast1_0 \$1622 + connect \xer_wen$173 \$1614 + connect \xer_data_i$172 \$1606 + connect \addr_en$1603 \$1604 + connect \wp$1600 \$1601 + connect \wr_pick_rise$1099 \$1598 + connect \wr_pick$1592 \$1593 + connect \wrflag_mul0_xer_so_3 \$1590 + connect \addr_en$1587 \$1588 + connect \wp$1584 \$1585 + connect \wr_pick_rise$1079 \$1582 + connect \wr_pick$1576 \$1577 + connect \wrflag_div0_xer_so_3 \$1574 + connect \addr_en$1571 \$1572 + connect \wp$1568 \$1569 + connect \wr_pick_rise$1057 \$1566 + connect \wr_pick$1560 \$1561 + connect \wrflag_spr0_xer_so_3 \$1558 + connect \addr_en$1555 \$1556 + connect \wp$1552 \$1553 + connect \wr_pick_rise$981 \$1550 + connect \wr_pick$1544 \$1545 + connect \wrpick_XER_xer_so_i [3] \$1542 + connect \wrpick_XER_xer_so_i [2] \$1540 + connect \wrpick_XER_xer_so_i [1] \$1538 + connect \wrpick_XER_xer_so_i [0] \$1536 + connect \wrflag_alu0_xer_so_4 \$1534 + connect \xer_wen$171 \$1532 + connect \xer_data_i$170 \$1526 + connect \addr_en$1519 \$1520 + connect \wp$1516 \$1517 + connect \wr_pick_rise$1098 \$1514 + connect \wr_pick$1508 \$1509 + connect \wrflag_mul0_xer_ov_2 \$1506 + connect \addr_en$1503 \$1504 + connect \wp$1500 \$1501 + connect \wr_pick_rise$1078 \$1498 + connect \wr_pick$1492 \$1493 + connect \wrflag_div0_xer_ov_2 \$1490 + connect \addr_en$1487 \$1488 + connect \wp$1484 \$1485 + connect \wr_pick_rise$1056 \$1482 + connect \wr_pick$1476 \$1477 + connect \wrflag_spr0_xer_ov_4 \$1474 + connect \addr_en$1471 \$1472 + connect \wp$1468 \$1469 + connect \wr_pick_rise$980 \$1466 + connect \wr_pick$1460 \$1461 + connect \wrpick_XER_xer_ov_i [3] \$1458 + connect \wrpick_XER_xer_ov_i [2] \$1456 + connect \wrpick_XER_xer_ov_i [1] \$1454 + connect \wrpick_XER_xer_ov_i [0] \$1452 + connect \wrflag_alu0_xer_ov_3 \$1450 + connect \xer_wen \$1444 + connect \xer_data_i \$1442 + connect \addr_en$1437 \$1438 + connect \wp$1434 \$1435 + connect \wr_pick_rise$1118 \$1432 + connect \wr_pick$1426 \$1427 + connect \wrflag_shiftrot0_xer_ca_2 \$1424 + connect \addr_en$1421 \$1422 + connect \wp$1418 \$1419 + connect \wr_pick_rise$1055 \$1416 + connect \wr_pick$1410 \$1411 + connect \wrflag_spr0_xer_ca_5 \$1408 + connect \addr_en$1405 \$1406 + connect \wp$1402 \$1403 + connect \wr_pick_rise$979 \$1400 + connect \wr_pick$1394 \$1395 + connect \wrpick_XER_xer_ca_i [2] \$1392 + connect \wrpick_XER_xer_ca_i [1] \$1390 + connect \wrpick_XER_xer_ca_i [0] \$1388 + connect \wrflag_alu0_xer_ca_2 \$1386 + connect \cr_wen \$1384 [7:0] + connect \cr_data_i \$1373 + connect \addr_en$1358 \$1363 + connect \wp$1355 \$1356 + connect \wr_pick_rise$1117 \$1353 + connect \wr_pick$1347 \$1348 + connect \wrflag_shiftrot0_cr_a_1 \$1345 + connect \addr_en$1338 \$1343 + connect \wp$1335 \$1336 + connect \wr_pick_rise$1097 \$1333 + connect \wr_pick$1327 \$1328 + connect \wrflag_mul0_cr_a_1 \$1325 + connect \addr_en$1318 \$1323 + connect \wp$1315 \$1316 + connect \wr_pick_rise$1077 \$1313 + connect \wr_pick$1307 \$1308 + connect \wrflag_div0_cr_a_1 \$1305 + connect \addr_en$1298 \$1303 + connect \wp$1295 \$1296 + connect \wr_pick_rise$1037 \$1293 + connect \wr_pick$1287 \$1288 + connect \wrflag_logical0_cr_a_1 \$1285 + connect \addr_en$1278 \$1283 + connect \wp$1275 \$1276 + connect \wr_pick_rise$998 \$1273 + connect \wr_pick$1267 \$1268 + connect \wrflag_cr0_cr_a_2 \$1265 + connect \addr_en$1258 \$1263 + connect \wp$1255 \$1256 + connect \wr_pick_rise$978 \$1253 + connect \wr_pick$1247 \$1248 + connect \wrpick_CR_cr_a_i [5] \$1245 + connect \wrpick_CR_cr_a_i [4] \$1243 + connect \wrpick_CR_cr_a_i [3] \$1241 + connect \wrpick_CR_cr_a_i [2] \$1239 + connect \wrpick_CR_cr_a_i [1] \$1237 + connect \wrpick_CR_cr_a_i [0] \$1235 + connect \wrflag_alu0_cr_a_1 \$1233 + connect \cr_full_wr__wen \addr_en$1230 + connect \cr_full_wr__data_i \fus_dest2_o + connect \addr_en$1230 \$1231 + connect \wp$1227 \$1228 + connect \wr_pick_rise$997 \$1225 + connect \wr_pick$1219 \$1220 + connect \wrpick_CR_full_cr_i \$1217 + connect \wrflag_cr0_full_cr_1 \$1215 + connect \int_dest1__wen \$1213 + connect \int_dest1__addr \$1195 [4:0] + connect \int_dest1__data_i \$1176 [63:0] + connect \addr_en$1156 \$1157 + connect \wp$1153 \$1154 + connect \wr_pick_rise$1136 \$1151 + connect \wr_pick$1145 \$1146 + connect \wrflag_ldst0_o_1 \$1143 + connect \addr_en$1140 \$1141 + connect \wp$1137 \$1138 + connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1136 + connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1131 + connect \wr_pick_rise$1131 \$1134 + connect \wr_pick$1127 \$1128 + connect \wrflag_ldst0_o_0 \$1125 + connect \addr_en$1122 \$1123 + connect \wp$1119 \$1120 + connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1118 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1117 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1112 + connect \wr_pick_rise$1112 \$1115 + connect \wr_pick$1108 \$1109 + connect \wrflag_shiftrot0_o_0 \$1106 + connect \addr_en$1103 \$1104 + connect \wp$1100 \$1101 + connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1099 + connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1098 + connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1097 + connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1092 + connect \wr_pick_rise$1092 \$1095 + connect \wr_pick$1088 \$1089 + connect \wrflag_mul0_o_0 \$1086 + connect \addr_en$1083 \$1084 + connect \wp$1080 \$1081 + connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1079 + connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1078 + connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1077 + connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1072 + connect \wr_pick_rise$1072 \$1075 + connect \wr_pick$1068 \$1069 + connect \wrflag_div0_o_0 \$1066 + connect \addr_en$1063 \$1064 + connect \wp$1060 \$1061 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1059 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1058 + connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1057 + connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1056 + connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1055 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1050 + connect \wr_pick_rise$1050 \$1053 + connect \wr_pick$1046 \$1047 + connect \wrflag_spr0_o_0 \$1044 + connect \addr_en$1041 \$1042 + connect \wp$1038 \$1039 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1037 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1032 + connect \wr_pick_rise$1032 \$1035 + connect \wr_pick$1028 \$1029 + connect \wrflag_logical0_o_0 \$1026 + connect \addr_en$1023 \$1024 + connect \wp$1020 \$1021 + connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1019 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1018 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1017 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1016 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1011 + connect \wr_pick_rise$1011 \$1014 + connect \wr_pick$1007 \$1008 + connect \wrflag_trap0_o_0 \$1005 + connect \addr_en$1002 \$1003 + connect \wp$999 \$1000 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$998 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$997 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$992 + connect \wr_pick_rise$992 \$995 + connect \wr_pick$988 \$989 + connect \wrflag_cr0_o_0 \$986 + connect \addr_en \$984 + connect \wp \$982 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$981 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$980 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$979 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$978 + connect \fus_cu_wr__go_i [0] \wr_pick_rise + connect \wr_pick_rise \$976 + connect \wr_pick \$972 + connect \wrpick_INT_o_i [9] \$970 + connect \wrpick_INT_o_i [8] \$968 + connect \wrpick_INT_o_i [7] \$966 + connect \wrpick_INT_o_i [6] \$964 + connect \wrpick_INT_o_i [5] \$962 + connect \wrpick_INT_o_i [4] \$960 + connect \wrpick_INT_o_i [3] \$958 + connect \wrpick_INT_o_i [2] \$956 + connect \wrpick_INT_o_i [1] \$954 + connect \wrpick_INT_o_i [0] \$952 + connect \wrflag_alu0_o_0 \$950 + connect \spr_spr1__ren \$948 + connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + connect \addr_en_SPR_spr1_spr0_0 \$946 + connect \rp_SPR_spr1_spr0_0 \$944 + connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 + connect \pick_SPR_spr1_spr0_0 \$942 + connect \rdflag_SPR_spr1_0 \core_spr1_ok + connect \fast_src2__ren \$934 + connect \fast_src2__addr \$932 + connect \addr_en_FAST_fast2_trap0_1 \$930 + connect \rp_FAST_fast2_trap0_1 \$928 + connect \pick_FAST_fast2_trap0_1 \$926 + connect \addr_en_FAST_fast2_branch0_0 \$918 + connect \rp_FAST_fast2_branch0_0 \$916 + connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 + connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 + connect \pick_FAST_fast2_branch0_0 \$914 + connect \rdflag_FAST_fast2_0 \core_fast2_ok + connect \fast_src1__ren \$906 + connect \fast_src1__addr \$904 + connect \addr_en_FAST_fast1_spr0_2 \$900 + connect \rp_FAST_fast1_spr0_2 \$898 + connect \pick_FAST_fast1_spr0_2 \$896 + connect \addr_en_FAST_fast1_trap0_1 \$888 + connect \rp_FAST_fast1_trap0_1 \$886 + connect \pick_FAST_fast1_trap0_1 \$884 + connect \addr_en_FAST_fast1_branch0_0 \$876 + connect \rp_FAST_fast1_branch0_0 \$874 + connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 + connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 + connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 + connect \pick_FAST_fast1_branch0_0 \$872 + connect \rdflag_FAST_fast1_0 \core_fast1_ok + connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] + connect \addr_en_CR_cr_c_cr0_0 \$864 + connect \rp_CR_cr_c_cr0_0 \$858 + connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 + connect \pick_CR_cr_c_cr0_0 \$856 + connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 + connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] + connect \addr_en_CR_cr_b_cr0_0 \$848 + connect \rp_CR_cr_b_cr0_0 \$842 + connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 + connect \pick_CR_cr_b_cr0_0 \$840 + connect \rdflag_CR_cr_b_0 \core_cr_in2_ok + connect \cr_src1__ren \$832 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$829 + connect \rp_CR_cr_a_branch0_1 \$823 + connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$821 + connect \addr_en_CR_cr_a_cr0_0 \$813 + connect \rp_CR_cr_a_cr0_0 \$807 + connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 + connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 + connect \pick_CR_cr_a_cr0_0 \$805 + connect \rdflag_CR_cr_a_0 \core_cr_in1_ok + connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + connect \addr_en_CR_full_cr_cr0_0 \$797 + connect \rp_CR_full_cr_cr0_0 \$795 + connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 + connect \pick_CR_full_cr_cr0_0 \$793 + connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok + connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + connect \addr_en_XER_xer_ov_spr0_0 \$785 + connect \rp_XER_xer_ov_spr0_0 \$783 + connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 + connect \pick_XER_xer_ov_spr0_0 \$781 + connect \rdflag_XER_xer_ov_0 \$773 + connect \xer_src2__ren \$761 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$759 + connect \rp_XER_xer_ca_shiftrot0_2 \$757 + connect \pick_XER_xer_ca_shiftrot0_2 \$755 + connect \addr_en_XER_xer_ca_spr0_1 \$747 + connect \rp_XER_xer_ca_spr0_1 \$745 + connect \pick_XER_xer_ca_spr0_1 \$743 + connect \addr_en_XER_xer_ca_alu0_0 \$735 + connect \rp_XER_xer_ca_alu0_0 \$733 + connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 + connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 + connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 + connect \pick_XER_xer_ca_alu0_0 \$731 + connect \rdflag_XER_xer_ca_0 \$723 + connect \xer_src1__ren \$705 + connect \addr_en_XER_xer_so_shiftrot0_5 \$703 + connect \rp_XER_xer_so_shiftrot0_5 \$701 + connect \pick_XER_xer_so_shiftrot0_5 \$699 + connect \addr_en_XER_xer_so_mul0_4 \$691 + connect \rp_XER_xer_so_mul0_4 \$689 + connect \pick_XER_xer_so_mul0_4 \$687 + connect \addr_en_XER_xer_so_div0_3 \$679 + connect \rp_XER_xer_so_div0_3 \$677 + connect \pick_XER_xer_so_div0_3 \$675 + connect \addr_en_XER_xer_so_spr0_2 \$667 + connect \rp_XER_xer_so_spr0_2 \$665 + connect \pick_XER_xer_so_spr0_2 \$663 + connect \addr_en_XER_xer_so_logical0_1 \$655 + connect \rp_XER_xer_so_logical0_1 \$653 + connect \pick_XER_xer_so_logical0_1 \$651 + connect \addr_en_XER_xer_so_alu0_0 \$643 + connect \rp_XER_xer_so_alu0_0 \$641 + connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 + connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 + connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 + connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 + connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 + connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 + connect \pick_XER_xer_so_alu0_0 \$639 + connect \rdflag_XER_xer_so_0 \$631 + connect \int_src3__ren \$619 + connect \int_src3__addr \$617 [4:0] + connect \addr_en_INT_rc_ldst0_1 \$614 + connect \rp_INT_rc_ldst0_1 \$612 + connect \pick_INT_rc_ldst0_1 \$610 + connect \addr_en_INT_rc_shiftrot0_0 \$602 + connect \rp_INT_rc_shiftrot0_0 \$600 + connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 + connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 + connect \pick_INT_rc_shiftrot0_0 \$598 + connect \rdflag_INT_rc_0 \core_reg3_ok + connect \int_src2__ren \$590 + connect \int_src2__addr \$588 [4:0] + connect \addr_en_INT_rb_ldst0_7 \$573 + connect \rp_INT_rb_ldst0_7 \$571 + connect \pick_INT_rb_ldst0_7 \$569 + connect \addr_en_INT_rb_shiftrot0_6 \$561 + connect \rp_INT_rb_shiftrot0_6 \$559 + connect \pick_INT_rb_shiftrot0_6 \$557 + connect \addr_en_INT_rb_mul0_5 \$549 + connect \rp_INT_rb_mul0_5 \$547 + connect \pick_INT_rb_mul0_5 \$545 + connect \addr_en_INT_rb_div0_4 \$537 + connect \rp_INT_rb_div0_4 \$535 + connect \pick_INT_rb_div0_4 \$533 + connect \addr_en_INT_rb_logical0_3 \$525 + connect \rp_INT_rb_logical0_3 \$523 + connect \pick_INT_rb_logical0_3 \$521 + connect \addr_en_INT_rb_trap0_2 \$513 + connect \rp_INT_rb_trap0_2 \$511 + connect \pick_INT_rb_trap0_2 \$509 + connect \addr_en_INT_rb_cr0_1 \$501 + connect \rp_INT_rb_cr0_1 \$499 + connect \pick_INT_rb_cr0_1 \$497 + connect \addr_en_INT_rb_alu0_0 \$489 + connect \rp_INT_rb_alu0_0 \$487 + connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 + connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 + connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 + connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 + connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 + connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 + connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 + connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 + connect \pick_INT_rb_alu0_0 \$485 + connect \rdflag_INT_rb_0 \core_reg2_ok + connect \int_src1__ren \$477 + connect \int_src1__addr \$475 [4:0] + connect \addr_en_INT_ra_ldst0_8 \$458 + connect \rp_INT_ra_ldst0_8 \$456 + connect \fus_cu_rd__go_i$62 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$62 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$62 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$454 + connect \addr_en_INT_ra_shiftrot0_7 \$446 + connect \rp_INT_ra_shiftrot0_7 \$444 + connect \fus_cu_rd__go_i$59 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$59 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$59 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$59 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$59 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$442 + connect \addr_en_INT_ra_mul0_6 \$434 + connect \rp_INT_ra_mul0_6 \$432 + connect \fus_cu_rd__go_i$56 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$56 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$56 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$430 + connect \addr_en_INT_ra_div0_5 \$422 + connect \rp_INT_ra_div0_5 \$420 + connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$418 + connect \addr_en_INT_ra_spr0_4 \$410 + connect \rp_INT_ra_spr0_4 \$408 + connect \fus_cu_rd__go_i$50 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$50 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$50 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$406 + connect \addr_en_INT_ra_logical0_3 \$398 + connect \rp_INT_ra_logical0_3 \$396 + connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$394 + connect \addr_en_INT_ra_trap0_2 \$386 + connect \rp_INT_ra_trap0_2 \$384 + connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$382 + connect \addr_en_INT_ra_cr0_1 \$374 + connect \rp_INT_ra_cr0_1 \$372 + connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$41 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$370 + connect \addr_en_INT_ra_alu0_0 \$362 + connect \rp_INT_ra_alu0_0 \$360 + connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 + connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 + connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 + connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 + connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 + connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 + connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 + connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 + connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 + connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 + connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 + connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 + connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 + connect \pick_INT_ra_alu0_0 \$358 + connect \rdflag_INT_ra_0 \core_reg1_ok + connect \en_ldst0 \$217 + connect \en_shiftrot0 \$213 + connect \en_mul0 \$209 + connect \en_div0 \$205 + connect \en_spr0 \$201 + connect \en_logical0 \$197 + connect \en_trap0 \$193 + connect \en_branch0 \$189 + connect \en_cr0 \$185 + connect \fu_enable [9] \en_ldst0 + connect \fu_enable [8] \en_shiftrot0 + connect \fu_enable [7] \en_mul0 + connect \fu_enable [6] \en_div0 + connect \fu_enable [5] \en_spr0 + connect \fu_enable [4] \en_logical0 + connect \fu_enable [3] \en_trap0 + connect \fu_enable [2] \en_branch0 + connect \fu_enable [1] \en_cr0 + connect \fu_enable [0] \en_alu0 + connect \en_alu0 \$181 + connect \dec_LDST_sv_a_nz \sv_a_nz + connect \dec_LDST_bigendian \bigendian_i + connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \sv_a_nz$180 \sv_a_nz + connect \dec_SHIFT_ROT_bigendian \bigendian_i + connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \sv_a_nz$179 \sv_a_nz + connect \dec_MUL_bigendian \bigendian_i + connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_sv_a_nz \sv_a_nz + connect \dec_DIV_bigendian \bigendian_i + connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \sv_a_nz$178 \sv_a_nz + connect \dec_SPR_bigendian \bigendian_i + connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_sv_a_nz \sv_a_nz + connect \dec_LOGICAL_bigendian \bigendian_i + connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \sv_a_nz$177 \sv_a_nz + connect \dec_BRANCH_bigendian \bigendian_i + connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \sv_a_nz$176 \sv_a_nz + connect \dec_CR_bigendian \bigendian_i + connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_sv_a_nz \sv_a_nz + connect \dec_ALU_bigendian \bigendian_i + connect \dec_ALU_raw_opcode_in \raw_insn_i +end +attribute \src "libresoc.v:49145.1-49881.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr" +attribute 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49582$3040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$libresoc.v:49582$3040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49583$3041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$54 + connect \B \$56 + connect \Y $or$libresoc.v:49583$3041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49584$3042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_cr_pred2__data_o + connect \B \reg_3_cr_pred3__data_o + connect \Y $or$libresoc.v:49584$3042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49585$3043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:49585$3043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49586$3044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:49586$3044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49587$3045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$60 + connect \B \$62 + connect \Y $or$libresoc.v:49587$3045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49588$3046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$58 + connect \B \$64 + connect \Y $or$libresoc.v:49588$3046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49589$3047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \$5 + connect \Y $or$libresoc.v:49589$3047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49562$3020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$17 + connect \Y $reduce_or$libresoc.v:49562$3020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49563$3021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:49563$3021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49571$3029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$34 + connect \Y $reduce_or$libresoc.v:49571$3029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49580$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$51 + connect \Y $reduce_or$libresoc.v:49580$3038_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49598.9-49619.4" + cell \reg_0 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred0__data_o \reg_0_cr_pred0__data_o + connect \cr_pred0__ren \reg_0_cr_pred0__ren + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \r20__data_o \reg_0_r20__data_o + connect \r20__ren \reg_0_r20__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49620.9-49641.4" + cell \reg_1 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred1__data_o \reg_1_cr_pred1__data_o + connect \cr_pred1__ren \reg_1_cr_pred1__ren + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \r21__data_o \reg_1_r21__data_o + connect \r21__ren \reg_1_r21__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49642.9-49663.4" + cell \reg_2 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred2__data_o \reg_2_cr_pred2__data_o + connect \cr_pred2__ren \reg_2_cr_pred2__ren + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \r22__data_o \reg_2_r22__data_o + connect \r22__ren \reg_2_r22__ren + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49664.9-49685.4" + cell \reg_3 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred3__data_o \reg_3_cr_pred3__data_o + connect \cr_pred3__ren \reg_3_cr_pred3__ren + connect \dest13__data_i \reg_3_dest13__data_i + connect \dest13__wen \reg_3_dest13__wen + connect \dest23__data_i \reg_3_dest23__data_i + connect \dest23__wen \reg_3_dest23__wen + connect \r23__data_o \reg_3_r23__data_o + connect \r23__ren \reg_3_r23__ren + connect \r3__data_o \reg_3_r3__data_o + connect \r3__ren \reg_3_r3__ren + connect \src13__data_o \reg_3_src13__data_o + connect \src13__ren \reg_3_src13__ren + connect \src23__data_o \reg_3_src23__data_o + connect \src23__ren \reg_3_src23__ren + connect \src33__data_o \reg_3_src33__data_o + connect \src33__ren \reg_3_src33__ren + connect \w3__data_i \reg_3_w3__data_i + connect \w3__wen \reg_3_w3__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49686.9-49707.4" + cell \reg_4 \reg_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred4__data_o \reg_4_cr_pred4__data_o + connect \cr_pred4__ren \reg_4_cr_pred4__ren + connect \dest14__data_i \reg_4_dest14__data_i + connect \dest14__wen \reg_4_dest14__wen + connect \dest24__data_i \reg_4_dest24__data_i + connect \dest24__wen \reg_4_dest24__wen + connect \r24__data_o \reg_4_r24__data_o + connect \r24__ren \reg_4_r24__ren + connect \r4__data_o \reg_4_r4__data_o + connect \r4__ren \reg_4_r4__ren + connect \src14__data_o \reg_4_src14__data_o + connect \src14__ren \reg_4_src14__ren + connect \src24__data_o \reg_4_src24__data_o + connect \src24__ren \reg_4_src24__ren + connect \src34__data_o \reg_4_src34__data_o + connect \src34__ren \reg_4_src34__ren + connect \w4__data_i \reg_4_w4__data_i + connect \w4__wen \reg_4_w4__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49708.9-49729.4" + cell \reg_5 \reg_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred5__data_o \reg_5_cr_pred5__data_o + connect \cr_pred5__ren \reg_5_cr_pred5__ren + connect \dest15__data_i \reg_5_dest15__data_i + connect \dest15__wen \reg_5_dest15__wen + connect \dest25__data_i \reg_5_dest25__data_i + connect \dest25__wen \reg_5_dest25__wen + connect \r25__data_o \reg_5_r25__data_o + connect \r25__ren \reg_5_r25__ren + connect \r5__data_o \reg_5_r5__data_o + connect \r5__ren \reg_5_r5__ren + connect \src15__data_o \reg_5_src15__data_o + connect \src15__ren \reg_5_src15__ren + connect \src25__data_o \reg_5_src25__data_o + connect \src25__ren \reg_5_src25__ren + connect \src35__data_o \reg_5_src35__data_o + connect \src35__ren \reg_5_src35__ren + connect \w5__data_i \reg_5_w5__data_i + connect \w5__wen \reg_5_w5__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49730.9-49751.4" + cell \reg_6 \reg_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred6__data_o \reg_6_cr_pred6__data_o + connect \cr_pred6__ren \reg_6_cr_pred6__ren + connect \dest16__data_i \reg_6_dest16__data_i + connect \dest16__wen \reg_6_dest16__wen + connect \dest26__data_i \reg_6_dest26__data_i + connect \dest26__wen \reg_6_dest26__wen + connect \r26__data_o \reg_6_r26__data_o + connect \r26__ren \reg_6_r26__ren + connect \r6__data_o \reg_6_r6__data_o + connect \r6__ren \reg_6_r6__ren + connect \src16__data_o \reg_6_src16__data_o + connect \src16__ren \reg_6_src16__ren + connect \src26__data_o \reg_6_src26__data_o + connect \src26__ren \reg_6_src26__ren + connect \src36__data_o \reg_6_src36__data_o + connect \src36__ren \reg_6_src36__ren + connect \w6__data_i \reg_6_w6__data_i + connect \w6__wen \reg_6_w6__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49752.9-49773.4" + cell \reg_7 \reg_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_pred7__data_o \reg_7_cr_pred7__data_o + connect \cr_pred7__ren \reg_7_cr_pred7__ren + connect \dest17__data_i \reg_7_dest17__data_i + connect \dest17__wen \reg_7_dest17__wen + connect \dest27__data_i \reg_7_dest27__data_i + connect \dest27__wen \reg_7_dest27__wen + connect \r27__data_o \reg_7_r27__data_o + connect \r27__ren \reg_7_r27__ren + connect \r7__data_o \reg_7_r7__data_o + connect \r7__ren \reg_7_r7__ren + connect \src17__data_o \reg_7_src17__data_o + connect \src17__ren \reg_7_src17__ren + connect \src27__data_o \reg_7_src27__data_o + connect \src27__ren \reg_7_src27__ren + connect \src37__data_o \reg_7_src37__data_o + connect \src37__ren \reg_7_src37__ren + connect \w7__data_i \reg_7_w7__data_i + connect \w7__wen \reg_7_w7__wen + end + attribute \src "libresoc.v:49146.7-49146.20" + process $proc$libresoc.v:49146$3071 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:49524.13-49524.30" + process $proc$libresoc.v:49524$3072 + assign { } { } + assign $1\ren_delay[7:0] 8'00000000 + sync always + sync init + update \ren_delay $1\ren_delay[7:0] + end + attribute \src "libresoc.v:49526.13-49526.35" + process $proc$libresoc.v:49526$3073 + assign { } { } + assign $0\ren_delay$17[7:0]$3074 8'00000000 + sync always + sync init + update \ren_delay$17 $0\ren_delay$17[7:0]$3074 + end + attribute \src "libresoc.v:49530.13-49530.35" + process $proc$libresoc.v:49530$3075 + assign { } { } + assign $0\ren_delay$34[7:0]$3076 8'00000000 + sync always + sync init + update \ren_delay$34 $0\ren_delay$34[7:0]$3076 + end + attribute \src "libresoc.v:49534.13-49534.35" + process $proc$libresoc.v:49534$3077 + assign { } { } + assign $0\ren_delay$51[7:0]$3078 8'00000000 + sync always + sync init + update \ren_delay$51 $0\ren_delay$51[7:0]$3078 + end + attribute \src "libresoc.v:49590.3-49591.43" + process $proc$libresoc.v:49590$3048 + assign { } { } + assign $0\ren_delay$51[7:0]$3049 \ren_delay$51$next + sync posedge \coresync_clk + update \ren_delay$51 $0\ren_delay$51[7:0]$3049 + end + attribute \src "libresoc.v:49592.3-49593.43" + process $proc$libresoc.v:49592$3050 + assign { } { } + assign $0\ren_delay$34[7:0]$3051 \ren_delay$34$next + sync posedge \coresync_clk + update \ren_delay$34 $0\ren_delay$34[7:0]$3051 + end + attribute \src "libresoc.v:49594.3-49595.43" + process $proc$libresoc.v:49594$3052 + assign { } { } + assign $0\ren_delay$17[7:0]$3053 \ren_delay$17$next + sync posedge \coresync_clk + update \ren_delay$17 $0\ren_delay$17[7:0]$3053 + end + attribute \src "libresoc.v:49596.3-49597.35" + process $proc$libresoc.v:49596$3054 + assign { } { } + assign $0\ren_delay[7:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[7:0] + end + attribute \src "libresoc.v:49774.3-49782.6" + process $proc$libresoc.v:49774$3055 + assign { } { } + assign { } { } + assign $0\ren_delay$17$next[7:0]$3056 $1\ren_delay$17$next[7:0]$3057 + attribute \src "libresoc.v:49775.5-49775.29" + switch \initial + attribute \src "libresoc.v:49775.9-49775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$17$next[7:0]$3057 8'00000000 + case + assign $1\ren_delay$17$next[7:0]$3057 \src1__ren + end + sync always + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3056 + end + attribute \src "libresoc.v:49783.3-49792.6" + process $proc$libresoc.v:49783$3058 + assign { } { } + assign { } { } + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:49784.5-49784.29" + switch \initial + attribute \src "libresoc.v:49784.9-49784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$18 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[3:0] \$32 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + attribute \src "libresoc.v:49793.3-49801.6" + process $proc$libresoc.v:49793$3059 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$3060 $1\ren_delay$34$next[7:0]$3061 + attribute \src "libresoc.v:49794.5-49794.29" + switch \initial + attribute \src "libresoc.v:49794.9-49794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$3061 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$3061 \src2__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3060 + end + attribute \src "libresoc.v:49802.3-49811.6" + process $proc$libresoc.v:49802$3062 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "libresoc.v:49803.5-49803.29" + switch \initial + attribute \src "libresoc.v:49803.9-49803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$49 + case + assign $1\src2__data_o[3:0] 4'0000 + end + sync always + update \src2__data_o $0\src2__data_o[3:0] + end + attribute \src "libresoc.v:49812.3-49820.6" + process $proc$libresoc.v:49812$3063 + assign { } { } + assign { } { } + assign $0\ren_delay$51$next[7:0]$3064 $1\ren_delay$51$next[7:0]$3065 + attribute \src "libresoc.v:49813.5-49813.29" + switch \initial + attribute \src "libresoc.v:49813.9-49813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$51$next[7:0]$3065 8'00000000 + case + assign $1\ren_delay$51$next[7:0]$3065 \src3__ren + end + sync always + update \ren_delay$51$next $0\ren_delay$51$next[7:0]$3064 + end + attribute \src "libresoc.v:49821.3-49830.6" + process $proc$libresoc.v:49821$3066 + assign { } { } + assign { } { } + assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] + attribute \src "libresoc.v:49822.5-49822.29" + switch \initial + attribute \src "libresoc.v:49822.9-49822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[3:0] \$66 + case + assign $1\src3__data_o[3:0] 4'0000 + end + sync always + update \src3__data_o $0\src3__data_o[3:0] + end + attribute \src "libresoc.v:49831.3-49839.6" + process $proc$libresoc.v:49831$3067 + assign { } { } + assign { } { } + assign $0\ren_delay$next[7:0]$3068 $1\ren_delay$next[7:0]$3069 + attribute \src "libresoc.v:49832.5-49832.29" + switch \initial + attribute \src "libresoc.v:49832.9-49832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[7:0]$3069 8'00000000 + case + assign $1\ren_delay$next[7:0]$3069 \cr_pred__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[7:0]$3068 + end + attribute \src "libresoc.v:49840.3-49849.6" + process $proc$libresoc.v:49840$3070 + assign { } { } + assign { } { } + assign $0\cr_pred__data_o[3:0] $1\cr_pred__data_o[3:0] + attribute \src "libresoc.v:49841.5-49841.29" + switch \initial + attribute \src "libresoc.v:49841.9-49841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_pred__data_o[3:0] \$15 + case + assign $1\cr_pred__data_o[3:0] 4'0000 + end + sync always + update \cr_pred__data_o $0\cr_pred__data_o[3:0] + end + connect \$9 $or$libresoc.v:49558$3016_Y + connect \$11 $or$libresoc.v:49559$3017_Y + connect \$13 $or$libresoc.v:49560$3018_Y + connect \$15 $or$libresoc.v:49561$3019_Y + connect \$18 $reduce_or$libresoc.v:49562$3020_Y + connect \$1 $reduce_or$libresoc.v:49563$3021_Y + connect \$20 $or$libresoc.v:49564$3022_Y + connect \$22 $or$libresoc.v:49565$3023_Y + connect \$24 $or$libresoc.v:49566$3024_Y + connect \$26 $or$libresoc.v:49567$3025_Y + connect \$28 $or$libresoc.v:49568$3026_Y + connect \$30 $or$libresoc.v:49569$3027_Y + connect \$32 $or$libresoc.v:49570$3028_Y + connect \$35 $reduce_or$libresoc.v:49571$3029_Y + connect \$37 $or$libresoc.v:49572$3030_Y + connect \$3 $or$libresoc.v:49573$3031_Y + connect \$39 $or$libresoc.v:49574$3032_Y + connect \$41 $or$libresoc.v:49575$3033_Y + connect \$43 $or$libresoc.v:49576$3034_Y + connect \$45 $or$libresoc.v:49577$3035_Y + connect \$47 $or$libresoc.v:49578$3036_Y + connect \$49 $or$libresoc.v:49579$3037_Y + connect \$52 $reduce_or$libresoc.v:49580$3038_Y + connect \$54 $or$libresoc.v:49581$3039_Y + connect \$56 $or$libresoc.v:49582$3040_Y + connect \$58 $or$libresoc.v:49583$3041_Y + connect \$5 $or$libresoc.v:49584$3042_Y + connect \$60 $or$libresoc.v:49585$3043_Y + connect \$62 $or$libresoc.v:49586$3044_Y + connect \$64 $or$libresoc.v:49587$3045_Y + connect \$66 $or$libresoc.v:49588$3046_Y + connect \$7 $or$libresoc.v:49589$3047_Y + connect \cr_pred__ren 8'00000000 + connect \wen$68 8'00000000 + connect \data_i$69 4'0000 + connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren + connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } + connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_7_dest27__data_i 4'0000 + connect \reg_6_dest26__data_i 4'0000 + connect \reg_5_dest25__data_i 4'0000 + connect \reg_4_dest24__data_i 4'0000 + connect \reg_3_dest23__data_i 4'0000 + connect \reg_2_dest22__data_i 4'0000 + connect \reg_1_dest21__data_i 4'0000 + connect \reg_0_dest20__data_i 4'0000 + connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 + connect \reg_7_dest17__data_i \data_i + connect \reg_6_dest16__data_i \data_i + connect \reg_5_dest15__data_i \data_i + connect \reg_4_dest14__data_i \data_i + connect \reg_3_dest13__data_i \data_i + connect \reg_2_dest12__data_i \data_i + connect \reg_1_dest11__data_i \data_i + connect \reg_0_dest10__data_i \data_i + connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen + connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + connect { \reg_7_cr_pred7__ren \reg_6_cr_pred6__ren \reg_5_cr_pred5__ren \reg_4_cr_pred4__ren \reg_3_cr_pred3__ren \reg_2_cr_pred2__ren \reg_1_cr_pred1__ren \reg_0_cr_pred0__ren } 8'00000000 +end +attribute \src "libresoc.v:49885.1-50942.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" +attribute \generator "nMigen" +module \cr0 + attribute \src "libresoc.v:50543.3-50544.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:50716.3-50727.6" + wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 + attribute \src "libresoc.v:50515.3-50516.61" + wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] + attribute \src "libresoc.v:50716.3-50727.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3199 + attribute \src "libresoc.v:50517.3-50518.55" + wire width 32 $0\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:50716.3-50727.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 + attribute \src "libresoc.v:50513.3-50514.65" + wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:50541.3-50542.39" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:50863.3-50871.6" + wire $0\alu_l_r_alu$next[0:0]$3250 + attribute \src "libresoc.v:50485.3-50486.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:50854.3-50862.6" + wire $0\alui_l_r_alui$next[0:0]$3247 + attribute \src "libresoc.v:50487.3-50488.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $0\data_r0__o$next[63:0]$3205 + attribute \src "libresoc.v:50509.3-50510.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:50728.3-50749.6" + wire $0\data_r0__o_ok$next[0:0]$3206 + attribute \src "libresoc.v:50511.3-50512.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3213 + attribute \src "libresoc.v:50505.3-50506.49" + wire width 32 $0\data_r1__full_cr[31:0] + attribute \src "libresoc.v:50750.3-50771.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3214 + attribute \src "libresoc.v:50507.3-50508.55" + wire $0\data_r1__full_cr_ok[0:0] + attribute \src "libresoc.v:50772.3-50793.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3221 + attribute \src "libresoc.v:50501.3-50502.43" + wire width 4 $0\data_r2__cr_a[3:0] + attribute \src "libresoc.v:50772.3-50793.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3222 + attribute \src "libresoc.v:50503.3-50504.49" + wire $0\data_r2__cr_a_ok[0:0] + attribute \src "libresoc.v:50872.3-50881.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:50882.3-50891.6" + wire width 32 $0\dest2_o[31:0] + attribute \src "libresoc.v:50892.3-50901.6" + wire width 4 $0\dest3_o[3:0] + attribute \src "libresoc.v:49886.7-49886.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50671.3-50679.6" + wire $0\opc_l_r_opc$next[0:0]$3183 + attribute \src "libresoc.v:50527.3-50528.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:50662.3-50670.6" + wire $0\opc_l_s_opc$next[0:0]$3180 + attribute \src "libresoc.v:50529.3-50530.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:50902.3-50910.6" + wire width 3 $0\prev_wr_go$next[2:0]$3256 + attribute \src "libresoc.v:50539.3-50540.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:50616.3-50625.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:50707.3-50715.6" + wire width 3 $0\req_l_r_req$next[2:0]$3195 + attribute \src "libresoc.v:50519.3-50520.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:50698.3-50706.6" + wire width 3 $0\req_l_s_req$next[2:0]$3192 + attribute \src "libresoc.v:50521.3-50522.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:50635.3-50643.6" + wire $0\rok_l_r_rdok$next[0:0]$3171 + attribute \src "libresoc.v:50535.3-50536.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:50626.3-50634.6" + wire $0\rok_l_s_rdok$next[0:0]$3168 + attribute \src "libresoc.v:50537.3-50538.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:50653.3-50661.6" + wire $0\rst_l_r_rst$next[0:0]$3177 + attribute \src "libresoc.v:50531.3-50532.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:50644.3-50652.6" + wire $0\rst_l_s_rst$next[0:0]$3174 + attribute \src "libresoc.v:50533.3-50534.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:50689.3-50697.6" + wire width 6 $0\src_l_r_src$next[5:0]$3189 + attribute \src "libresoc.v:50523.3-50524.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:50680.3-50688.6" + wire width 6 $0\src_l_s_src$next[5:0]$3186 + attribute \src "libresoc.v:50525.3-50526.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:50794.3-50803.6" + wire width 64 $0\src_r0$next[63:0]$3229 + attribute \src "libresoc.v:50499.3-50500.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:50804.3-50813.6" + wire width 64 $0\src_r1$next[63:0]$3232 + attribute \src "libresoc.v:50497.3-50498.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:50814.3-50823.6" + wire width 32 $0\src_r2$next[31:0]$3235 + attribute \src "libresoc.v:50495.3-50496.29" + wire width 32 $0\src_r2[31:0] + attribute \src "libresoc.v:50824.3-50833.6" + wire width 4 $0\src_r3$next[3:0]$3238 + attribute \src "libresoc.v:50493.3-50494.29" + wire width 4 $0\src_r3[3:0] + attribute \src "libresoc.v:50834.3-50843.6" + wire width 4 $0\src_r4$next[3:0]$3241 + attribute \src "libresoc.v:50491.3-50492.29" + wire width 4 $0\src_r4[3:0] + attribute \src "libresoc.v:50844.3-50853.6" + wire width 4 $0\src_r5$next[3:0]$3244 + attribute \src "libresoc.v:50489.3-50490.29" + wire width 4 $0\src_r5[3:0] + attribute \src "libresoc.v:50004.7-50004.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:50716.3-50727.6" + wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 + attribute \src "libresoc.v:50035.14-50035.47" + wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] + attribute \src "libresoc.v:50716.3-50727.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3202 + attribute \src "libresoc.v:50039.14-50039.41" + wire width 32 $1\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:50716.3-50727.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 + attribute \src "libresoc.v:50118.13-50118.45" + wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:50142.7-50142.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:50863.3-50871.6" + wire $1\alu_l_r_alu$next[0:0]$3251 + attribute \src "libresoc.v:50150.7-50150.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:50854.3-50862.6" + wire $1\alui_l_r_alui$next[0:0]$3248 + attribute \src "libresoc.v:50162.7-50162.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $1\data_r0__o$next[63:0]$3207 + attribute \src "libresoc.v:50196.14-50196.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:50728.3-50749.6" + wire $1\data_r0__o_ok$next[0:0]$3208 + attribute \src "libresoc.v:50200.7-50200.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3215 + attribute \src "libresoc.v:50204.14-50204.38" + wire width 32 $1\data_r1__full_cr[31:0] + attribute \src "libresoc.v:50750.3-50771.6" + wire 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$reduce_or$libresoc.v:50449$3100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:50449$3100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:50450$3101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:50450$3101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50473$3124 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:50473$3124_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50474$3125 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:50474$3125_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50475$3126 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:50475$3126_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50476$3127 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:50476$3127_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50477$3128 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:50477$3128_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50478$3129 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:50478$3129_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50545.11-50567.4" + cell \alu_cr0 \alu_cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_cr0_cr_a + connect \cr_a$2 \alu_cr0_cr_a$2 + connect \cr_a_ok \cr_a_ok + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit + connect \cr_op__insn \alu_cr0_cr_op__insn + connect \cr_op__insn_type \alu_cr0_cr_op__insn_type + connect \full_cr \alu_cr0_full_cr + connect \full_cr$1 \alu_cr0_full_cr$1 + connect \full_cr_ok \full_cr_ok + connect \n_ready_i \alu_cr0_n_ready_i + connect \n_valid_o \alu_cr0_n_valid_o + connect \o \alu_cr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_cr0_p_ready_o + connect \p_valid_i \alu_cr0_p_valid_i + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50568.14-50574.4" + cell \alu_l$16 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50575.15-50581.4" + cell \alui_l$15 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50582.14-50588.4" + cell \opc_l$11 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50589.14-50595.4" + cell \req_l$12 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50596.14-50602.4" + cell \rok_l$14 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50603.14-50608.4" + cell \rst_l$13 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50609.14-50615.4" + cell \src_l$10 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:49886.7-49886.20" + process $proc$libresoc.v:49886$3258 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50004.7-50004.24" + process $proc$libresoc.v:50004$3259 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:50035.14-50035.47" + process $proc$libresoc.v:50035$3260 + assign { } { } + assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:50039.14-50039.41" + process $proc$libresoc.v:50039$3261 + assign { } { } + assign $1\alu_cr0_cr_op__insn[31:0] 0 + sync always + sync init + update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:50118.13-50118.45" + process $proc$libresoc.v:50118$3262 + assign { } { } + assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:50142.7-50142.26" + process $proc$libresoc.v:50142$3263 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:50150.7-50150.25" + process $proc$libresoc.v:50150$3264 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:50162.7-50162.27" + process $proc$libresoc.v:50162$3265 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:50196.14-50196.47" + process $proc$libresoc.v:50196$3266 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:50200.7-50200.27" + process $proc$libresoc.v:50200$3267 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:50204.14-50204.38" + process $proc$libresoc.v:50204$3268 + assign { } { } + assign $1\data_r1__full_cr[31:0] 0 + sync always + sync init + update \data_r1__full_cr $1\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:50208.7-50208.33" + process $proc$libresoc.v:50208$3269 + assign { } { } + assign $1\data_r1__full_cr_ok[0:0] 1'0 + sync always + sync init + update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:50212.13-50212.33" + process $proc$libresoc.v:50212$3270 + assign { } { } + assign $1\data_r2__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r2__cr_a $1\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:50216.7-50216.30" + process $proc$libresoc.v:50216$3271 + assign { } { } + assign $1\data_r2__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:50235.7-50235.25" + process $proc$libresoc.v:50235$3272 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:50239.7-50239.25" + process $proc$libresoc.v:50239$3273 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:50339.13-50339.30" + process $proc$libresoc.v:50339$3274 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:50347.13-50347.31" + process $proc$libresoc.v:50347$3275 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:50351.13-50351.31" + process $proc$libresoc.v:50351$3276 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:50363.7-50363.26" + process $proc$libresoc.v:50363$3277 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:50367.7-50367.26" + process $proc$libresoc.v:50367$3278 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:50371.7-50371.25" + process $proc$libresoc.v:50371$3279 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:50375.7-50375.25" + process $proc$libresoc.v:50375$3280 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:50395.13-50395.32" + process $proc$libresoc.v:50395$3281 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:50399.13-50399.32" + process $proc$libresoc.v:50399$3282 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:50403.14-50403.43" + process $proc$libresoc.v:50403$3283 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:50407.14-50407.43" + process $proc$libresoc.v:50407$3284 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:50411.14-50411.28" + process $proc$libresoc.v:50411$3285 + assign { } { } + assign $1\src_r2[31:0] 0 + sync always + sync init + update \src_r2 $1\src_r2[31:0] + end + attribute \src "libresoc.v:50415.13-50415.26" + process $proc$libresoc.v:50415$3286 + assign { } { } + assign $1\src_r3[3:0] 4'0000 + sync always + sync init + update \src_r3 $1\src_r3[3:0] + end + attribute \src "libresoc.v:50419.13-50419.26" + process $proc$libresoc.v:50419$3287 + assign { } { } + assign $1\src_r4[3:0] 4'0000 + sync always + sync init + update \src_r4 $1\src_r4[3:0] + end + attribute \src "libresoc.v:50423.13-50423.26" + process $proc$libresoc.v:50423$3288 + assign { } { } + assign $1\src_r5[3:0] 4'0000 + sync always + sync init + update \src_r5 $1\src_r5[3:0] + end + attribute \src "libresoc.v:50485.3-50486.39" + process $proc$libresoc.v:50485$3136 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:50487.3-50488.43" + process $proc$libresoc.v:50487$3137 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:50489.3-50490.29" + process $proc$libresoc.v:50489$3138 + assign { } { } + assign $0\src_r5[3:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[3:0] + end + attribute \src "libresoc.v:50491.3-50492.29" + process $proc$libresoc.v:50491$3139 + assign { } { } + assign $0\src_r4[3:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[3:0] + end + attribute \src "libresoc.v:50493.3-50494.29" + process $proc$libresoc.v:50493$3140 + assign { } { } + assign $0\src_r3[3:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[3:0] + end + attribute \src "libresoc.v:50495.3-50496.29" + process $proc$libresoc.v:50495$3141 + assign { } { } + assign $0\src_r2[31:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[31:0] + end + attribute \src "libresoc.v:50497.3-50498.29" + process $proc$libresoc.v:50497$3142 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:50499.3-50500.29" + process $proc$libresoc.v:50499$3143 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:50501.3-50502.43" + process $proc$libresoc.v:50501$3144 + assign { } { } + assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next + sync posedge \coresync_clk + update \data_r2__cr_a $0\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:50503.3-50504.49" + process $proc$libresoc.v:50503$3145 + assign { } { } + assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next + sync posedge \coresync_clk + update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:50505.3-50506.49" + process $proc$libresoc.v:50505$3146 + assign { } { } + assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next + sync posedge \coresync_clk + update \data_r1__full_cr $0\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:50507.3-50508.55" + process $proc$libresoc.v:50507$3147 + assign { } { } + assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next + sync posedge \coresync_clk + update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:50509.3-50510.37" + process $proc$libresoc.v:50509$3148 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:50511.3-50512.43" + process $proc$libresoc.v:50511$3149 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:50513.3-50514.65" + process $proc$libresoc.v:50513$3150 + assign { } { } + assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:50515.3-50516.61" + process $proc$libresoc.v:50515$3151 + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:50517.3-50518.55" + process $proc$libresoc.v:50517$3152 + assign { } { } + assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:50519.3-50520.39" + process $proc$libresoc.v:50519$3153 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:50521.3-50522.39" + process $proc$libresoc.v:50521$3154 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:50523.3-50524.39" + process $proc$libresoc.v:50523$3155 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:50525.3-50526.39" + process $proc$libresoc.v:50525$3156 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:50527.3-50528.39" + process $proc$libresoc.v:50527$3157 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:50529.3-50530.39" + process $proc$libresoc.v:50529$3158 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:50531.3-50532.39" + process $proc$libresoc.v:50531$3159 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:50533.3-50534.39" + process $proc$libresoc.v:50533$3160 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:50535.3-50536.41" + process $proc$libresoc.v:50535$3161 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:50537.3-50538.41" + process $proc$libresoc.v:50537$3162 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:50539.3-50540.37" + process $proc$libresoc.v:50539$3163 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:50541.3-50542.39" + process $proc$libresoc.v:50541$3164 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:50543.3-50544.25" + process $proc$libresoc.v:50543$3165 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:50616.3-50625.6" + process $proc$libresoc.v:50616$3166 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:50617.5-50617.29" + switch \initial + attribute \src "libresoc.v:50617.9-50617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:50626.3-50634.6" + process $proc$libresoc.v:50626$3167 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$3168 $1\rok_l_s_rdok$next[0:0]$3169 + attribute \src "libresoc.v:50627.5-50627.29" + switch \initial + attribute \src "libresoc.v:50627.9-50627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$3169 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$3169 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3168 + end + attribute \src "libresoc.v:50635.3-50643.6" + process $proc$libresoc.v:50635$3170 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$3171 $1\rok_l_r_rdok$next[0:0]$3172 + attribute \src "libresoc.v:50636.5-50636.29" + switch \initial + attribute \src "libresoc.v:50636.9-50636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$3172 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$3172 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3171 + end + attribute \src "libresoc.v:50644.3-50652.6" + process $proc$libresoc.v:50644$3173 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$3174 $1\rst_l_s_rst$next[0:0]$3175 + attribute \src "libresoc.v:50645.5-50645.29" + switch \initial + attribute \src "libresoc.v:50645.9-50645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$3175 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$3175 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3174 + end + attribute \src "libresoc.v:50653.3-50661.6" + process $proc$libresoc.v:50653$3176 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$3177 $1\rst_l_r_rst$next[0:0]$3178 + attribute \src "libresoc.v:50654.5-50654.29" + switch \initial + attribute \src "libresoc.v:50654.9-50654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$3178 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$3178 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3177 + end + attribute \src "libresoc.v:50662.3-50670.6" + process $proc$libresoc.v:50662$3179 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$3180 $1\opc_l_s_opc$next[0:0]$3181 + attribute \src "libresoc.v:50663.5-50663.29" + switch \initial + attribute \src "libresoc.v:50663.9-50663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$3181 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$3181 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3180 + end + attribute \src "libresoc.v:50671.3-50679.6" + process $proc$libresoc.v:50671$3182 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$3183 $1\opc_l_r_opc$next[0:0]$3184 + attribute \src "libresoc.v:50672.5-50672.29" + switch \initial + attribute \src "libresoc.v:50672.9-50672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$3184 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$3184 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3183 + end + attribute \src "libresoc.v:50680.3-50688.6" + process $proc$libresoc.v:50680$3185 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$3186 $1\src_l_s_src$next[5:0]$3187 + attribute \src "libresoc.v:50681.5-50681.29" + switch \initial + attribute \src "libresoc.v:50681.9-50681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$3187 6'000000 + case + assign $1\src_l_s_src$next[5:0]$3187 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3186 + end + attribute \src "libresoc.v:50689.3-50697.6" + process $proc$libresoc.v:50689$3188 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$3189 $1\src_l_r_src$next[5:0]$3190 + attribute \src "libresoc.v:50690.5-50690.29" + switch \initial + attribute \src "libresoc.v:50690.9-50690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$3190 6'111111 + case + assign $1\src_l_r_src$next[5:0]$3190 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3189 + end + attribute \src "libresoc.v:50698.3-50706.6" + process $proc$libresoc.v:50698$3191 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$3192 $1\req_l_s_req$next[2:0]$3193 + attribute \src "libresoc.v:50699.5-50699.29" + switch \initial + attribute \src "libresoc.v:50699.9-50699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$3193 3'000 + case + assign $1\req_l_s_req$next[2:0]$3193 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3192 + end + attribute \src "libresoc.v:50707.3-50715.6" + process $proc$libresoc.v:50707$3194 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$3195 $1\req_l_r_req$next[2:0]$3196 + attribute \src "libresoc.v:50708.5-50708.29" + switch \initial + attribute \src "libresoc.v:50708.9-50708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$3196 3'111 + case + assign $1\req_l_r_req$next[2:0]$3196 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3195 + end + attribute \src "libresoc.v:50716.3-50727.6" + process $proc$libresoc.v:50716$3197 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3199 $1\alu_cr0_cr_op__insn$next[31:0]$3202 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 + attribute \src "libresoc.v:50717.5-50717.29" + switch \initial + attribute \src "libresoc.v:50717.9-50717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3202 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + case + assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3202 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 \alu_cr0_cr_op__insn_type + end + sync always + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3199 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 + end + attribute \src "libresoc.v:50728.3-50749.6" + process $proc$libresoc.v:50728$3204 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$3205 $2\data_r0__o$next[63:0]$3209 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$3206 $3\data_r0__o_ok$next[0:0]$3211 + attribute \src "libresoc.v:50729.5-50729.29" + switch \initial + attribute \src "libresoc.v:50729.9-50729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$3208 $1\data_r0__o$next[63:0]$3207 } { \o_ok \alu_cr0_o } + case + assign $1\data_r0__o$next[63:0]$3207 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3208 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$3210 $2\data_r0__o$next[63:0]$3209 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$3209 $1\data_r0__o$next[63:0]$3207 + assign $2\data_r0__o_ok$next[0:0]$3210 $1\data_r0__o_ok$next[0:0]$3208 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$3211 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$3211 $2\data_r0__o_ok$next[0:0]$3210 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$3205 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3206 + end + attribute \src "libresoc.v:50750.3-50771.6" + process $proc$libresoc.v:50750$3212 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__full_cr$next[31:0]$3213 $2\data_r1__full_cr$next[31:0]$3217 + assign { } { } + assign $0\data_r1__full_cr_ok$next[0:0]$3214 $3\data_r1__full_cr_ok$next[0:0]$3219 + attribute \src "libresoc.v:50751.5-50751.29" + switch \initial + attribute \src "libresoc.v:50751.9-50751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__full_cr_ok$next[0:0]$3216 $1\data_r1__full_cr$next[31:0]$3215 } { \full_cr_ok \alu_cr0_full_cr } + case + assign $1\data_r1__full_cr$next[31:0]$3215 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3216 \data_r1__full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__full_cr_ok$next[0:0]$3218 $2\data_r1__full_cr$next[31:0]$3217 } 33'000000000000000000000000000000000 + case + assign $2\data_r1__full_cr$next[31:0]$3217 $1\data_r1__full_cr$next[31:0]$3215 + assign $2\data_r1__full_cr_ok$next[0:0]$3218 $1\data_r1__full_cr_ok$next[0:0]$3216 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__full_cr_ok$next[0:0]$3219 1'0 + case + assign $3\data_r1__full_cr_ok$next[0:0]$3219 $2\data_r1__full_cr_ok$next[0:0]$3218 + end + sync always + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3213 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3214 + end + attribute \src "libresoc.v:50772.3-50793.6" + process $proc$libresoc.v:50772$3220 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__cr_a$next[3:0]$3221 $2\data_r2__cr_a$next[3:0]$3225 + assign { } { } + assign $0\data_r2__cr_a_ok$next[0:0]$3222 $3\data_r2__cr_a_ok$next[0:0]$3227 + attribute \src "libresoc.v:50773.5-50773.29" + switch \initial + attribute \src "libresoc.v:50773.9-50773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__cr_a_ok$next[0:0]$3224 $1\data_r2__cr_a$next[3:0]$3223 } { \cr_a_ok \alu_cr0_cr_a } + case + assign $1\data_r2__cr_a$next[3:0]$3223 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3224 \data_r2__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__cr_a_ok$next[0:0]$3226 $2\data_r2__cr_a$next[3:0]$3225 } 5'00000 + case + assign $2\data_r2__cr_a$next[3:0]$3225 $1\data_r2__cr_a$next[3:0]$3223 + assign $2\data_r2__cr_a_ok$next[0:0]$3226 $1\data_r2__cr_a_ok$next[0:0]$3224 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__cr_a_ok$next[0:0]$3227 1'0 + case + assign $3\data_r2__cr_a_ok$next[0:0]$3227 $2\data_r2__cr_a_ok$next[0:0]$3226 + end + sync always + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3221 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3222 + end + attribute \src "libresoc.v:50794.3-50803.6" + process $proc$libresoc.v:50794$3228 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$3229 $1\src_r0$next[63:0]$3230 + attribute \src "libresoc.v:50795.5-50795.29" + switch \initial + attribute \src "libresoc.v:50795.9-50795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$3230 \src1_i + case + assign $1\src_r0$next[63:0]$3230 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$3229 + end + attribute \src "libresoc.v:50804.3-50813.6" + process $proc$libresoc.v:50804$3231 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$3232 $1\src_r1$next[63:0]$3233 + attribute \src "libresoc.v:50805.5-50805.29" + switch \initial + attribute \src "libresoc.v:50805.9-50805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$3233 \src2_i + case + assign $1\src_r1$next[63:0]$3233 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$3232 + end + attribute \src "libresoc.v:50814.3-50823.6" + process $proc$libresoc.v:50814$3234 + assign { } { } + assign { } { } + assign $0\src_r2$next[31:0]$3235 $1\src_r2$next[31:0]$3236 + attribute \src "libresoc.v:50815.5-50815.29" + switch \initial + attribute \src "libresoc.v:50815.9-50815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[31:0]$3236 \src3_i + case + assign $1\src_r2$next[31:0]$3236 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[31:0]$3235 + end + attribute \src "libresoc.v:50824.3-50833.6" + process $proc$libresoc.v:50824$3237 + assign { } { } + assign { } { } + assign $0\src_r3$next[3:0]$3238 $1\src_r3$next[3:0]$3239 + attribute \src "libresoc.v:50825.5-50825.29" + switch \initial + attribute \src "libresoc.v:50825.9-50825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[3:0]$3239 \src4_i + case + assign $1\src_r3$next[3:0]$3239 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[3:0]$3238 + end + attribute \src "libresoc.v:50834.3-50843.6" + process $proc$libresoc.v:50834$3240 + assign { } { } + assign { } { } + assign $0\src_r4$next[3:0]$3241 $1\src_r4$next[3:0]$3242 + attribute \src "libresoc.v:50835.5-50835.29" + switch \initial + attribute \src "libresoc.v:50835.9-50835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[3:0]$3242 \src5_i + case + assign $1\src_r4$next[3:0]$3242 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[3:0]$3241 + end + attribute \src "libresoc.v:50844.3-50853.6" + process $proc$libresoc.v:50844$3243 + assign { } { } + assign { } { } + assign $0\src_r5$next[3:0]$3244 $1\src_r5$next[3:0]$3245 + attribute \src "libresoc.v:50845.5-50845.29" + switch \initial + attribute \src "libresoc.v:50845.9-50845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[3:0]$3245 \src6_i + case + assign $1\src_r5$next[3:0]$3245 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[3:0]$3244 + end + attribute \src "libresoc.v:50854.3-50862.6" + process $proc$libresoc.v:50854$3246 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$3247 $1\alui_l_r_alui$next[0:0]$3248 + attribute \src "libresoc.v:50855.5-50855.29" + switch \initial + attribute \src "libresoc.v:50855.9-50855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$3248 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$3248 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3247 + end + attribute \src "libresoc.v:50863.3-50871.6" + process $proc$libresoc.v:50863$3249 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$3250 $1\alu_l_r_alu$next[0:0]$3251 + attribute \src "libresoc.v:50864.5-50864.29" + switch \initial + attribute \src "libresoc.v:50864.9-50864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$3251 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$3251 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3250 + end + attribute \src "libresoc.v:50872.3-50881.6" + process $proc$libresoc.v:50872$3252 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:50873.5-50873.29" + switch \initial + attribute \src "libresoc.v:50873.9-50873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:50882.3-50891.6" + process $proc$libresoc.v:50882$3253 + assign { } { } + assign { } { } + assign $0\dest2_o[31:0] $1\dest2_o[31:0] + attribute \src "libresoc.v:50883.5-50883.29" + switch \initial + attribute \src "libresoc.v:50883.9-50883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[31:0] \data_r1__full_cr + case + assign $1\dest2_o[31:0] 0 + end + sync always + update \dest2_o $0\dest2_o[31:0] + end + attribute \src "libresoc.v:50892.3-50901.6" + process $proc$libresoc.v:50892$3254 + assign { } { } + assign { } { } + assign $0\dest3_o[3:0] $1\dest3_o[3:0] + attribute \src "libresoc.v:50893.5-50893.29" + switch \initial + attribute \src "libresoc.v:50893.9-50893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[3:0] \data_r2__cr_a + case + assign $1\dest3_o[3:0] 4'0000 + end + sync always + update \dest3_o $0\dest3_o[3:0] + end + attribute \src "libresoc.v:50902.3-50910.6" + process $proc$libresoc.v:50902$3255 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$3256 $1\prev_wr_go$next[2:0]$3257 + attribute \src "libresoc.v:50903.5-50903.29" + switch \initial + attribute \src "libresoc.v:50903.9-50903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$3257 3'000 + case + assign $1\prev_wr_go$next[2:0]$3257 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3256 + end + connect \$5 $reduce_and$libresoc.v:50428$3079_Y + connect \$99 $and$libresoc.v:50429$3080_Y + connect \$101 $and$libresoc.v:50430$3081_Y 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\$39 $not$libresoc.v:50453$3104_Y + connect \$41 $and$libresoc.v:50454$3105_Y + connect \$43 $and$libresoc.v:50455$3106_Y + connect \$45 $eq$libresoc.v:50456$3107_Y + connect \$47 $and$libresoc.v:50457$3108_Y + connect \$49 $eq$libresoc.v:50458$3109_Y + connect \$51 $and$libresoc.v:50459$3110_Y + connect \$53 $and$libresoc.v:50460$3111_Y + connect \$55 $and$libresoc.v:50461$3112_Y + connect \$57 $or$libresoc.v:50462$3113_Y + connect \$59 $or$libresoc.v:50463$3114_Y + connect \$61 $or$libresoc.v:50464$3115_Y + connect \$63 $or$libresoc.v:50465$3116_Y + connect \$65 $and$libresoc.v:50466$3117_Y + connect \$67 $and$libresoc.v:50467$3118_Y + connect \$6 $not$libresoc.v:50468$3119_Y + connect \$69 $or$libresoc.v:50469$3120_Y + connect \$71 $and$libresoc.v:50470$3121_Y + connect \$73 $and$libresoc.v:50471$3122_Y + connect \$75 $and$libresoc.v:50472$3123_Y + connect \$77 $ternary$libresoc.v:50473$3124_Y + connect \$79 $ternary$libresoc.v:50474$3125_Y + connect \$81 $ternary$libresoc.v:50475$3126_Y + connect \$83 $ternary$libresoc.v:50476$3127_Y + connect \$85 $ternary$libresoc.v:50477$3128_Y + connect \$87 $ternary$libresoc.v:50478$3129_Y + connect \$8 $or$libresoc.v:50479$3130_Y + connect \$89 $and$libresoc.v:50480$3131_Y + connect \$91 $and$libresoc.v:50481$3132_Y + connect \$93 $and$libresoc.v:50482$3133_Y + connect \$95 $and$libresoc.v:50483$3134_Y + connect \$97 $not$libresoc.v:50484$3135_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_cr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_cr0_p_valid_i \alui_l_q_alui + connect \alu_cr0_cr_c \$87 + connect \alu_cr0_cr_b \$85 + connect \alu_cr0_cr_a$2 \$83 + connect \alu_cr0_full_cr$1 \$81 + connect \alu_cr0_rb \$79 + connect \alu_cr0_ra \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_cr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:50946.1-50995.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" +attribute \generator "nMigen" +module \cyc_l + attribute \src "libresoc.v:50947.7-50947.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50983.3-50991.6" + wire $0\q_int$next[0:0]$3296 + attribute \src "libresoc.v:50981.3-50982.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:50983.3-50991.6" + wire $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50965.7-50965.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:50978.17-50978.96" + wire $and$libresoc.v:50978$3291_Y + attribute \src "libresoc.v:50977.17-50977.92" + wire $not$libresoc.v:50977$3290_Y + attribute \src "libresoc.v:50980.17-50980.92" + wire $not$libresoc.v:50980$3293_Y + attribute \src "libresoc.v:50976.17-50976.98" + wire $or$libresoc.v:50976$3289_Y + attribute \src "libresoc.v:50979.17-50979.97" + wire $or$libresoc.v:50979$3292_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:50947.7-50947.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:50978$3291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:50978$3291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:50977$3290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_cyc + connect \Y $not$libresoc.v:50977$3290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:50980$3293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \Y $not$libresoc.v:50980$3293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:50976$3289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \B \q_int + connect \Y $or$libresoc.v:50976$3289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:50979$3292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_cyc + connect \Y $or$libresoc.v:50979$3292_Y + end + attribute \src "libresoc.v:50947.7-50947.20" + process $proc$libresoc.v:50947$3298 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50965.7-50965.19" + process $proc$libresoc.v:50965$3299 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:50981.3-50982.27" + process $proc$libresoc.v:50981$3294 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:50983.3-50991.6" + process $proc$libresoc.v:50983$3295 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50984.5-50984.29" + switch \initial + attribute \src "libresoc.v:50984.9-50984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$3297 1'0 + case + assign $1\q_int$next[0:0]$3297 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$3296 + end + connect \$9 $or$libresoc.v:50976$3289_Y + connect \$1 $not$libresoc.v:50977$3290_Y + connect \$3 $and$libresoc.v:50978$3291_Y + connect \$5 $or$libresoc.v:50979$3292_Y + connect \$7 $not$libresoc.v:50980$3293_Y + connect \qlq_cyc \$9 + connect \qn_cyc \$7 + connect \q_cyc \q_int +end +attribute \src "libresoc.v:50999.1-51731.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "libresoc.v:51544.3-51553.6" + wire $0\d_cr_req[0:0] + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 30 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 input 13 \core_dbg_core_dbg_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 input 16 \core_dbg_core_dbg_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 input 14 \core_dbg_core_dbg_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 input 12 \core_dbg_core_dbg_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 input 11 \core_dbg_core_dbg_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 input 15 \core_dbg_core_dbg_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" + wire width 64 input 17 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" + wire width 64 input 10 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" + wire output 8 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire output 18 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" + wire input 19 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire input 26 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 64 input 25 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire output 24 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire input 23 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 7 output 21 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 64 input 22 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire output 20 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire input 29 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 64 input 28 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire output 27 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" + wire output 6 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 4 input 2 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 input 5 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire width 64 output 7 \dmi_dout + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire width 64 \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire input 9 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" + wire \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" + wire \terminated$next + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51255$3307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51255$3307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51256$3308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51256$3308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51257$3309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51257$3309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" + cell $eq $eq$libresoc.v:51260$3312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $eq$libresoc.v:51260$3312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51264$3316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51264$3316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51265$3317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51265$3317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51266$3318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51266$3318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51272$3324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51272$3324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51273$3325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51273$3325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51274$3326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51274$3326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51280$3332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51280$3332_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51281$3333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51281$3333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51282$3334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51282$3334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51287$3339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51287$3339_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51288$3340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51288$3340_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51290$3342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51290$3342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51295$3347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51295$3347_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51296$3348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51296$3348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51297$3349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51297$3349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51303$3355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51303$3355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $eq $eq$libresoc.v:51304$3356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51304$3356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" + cell $eq $eq$libresoc.v:51305$3357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51305$3357_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + cell $eq $eq$libresoc.v:51310$3362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51310$3362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51248$3300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51248$3300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51251$3303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51251$3303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51253$3305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51253$3305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" + cell $not $not$libresoc.v:51262$3314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$libresoc.v:51262$3314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51268$3320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51268$3320_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51270$3322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51270$3322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51275$3327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51275$3327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51277$3329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51277$3329_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51283$3335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51283$3335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51285$3337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51285$3337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51289$3341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51289$3341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51291$3343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51291$3343_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51293$3345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51293$3345_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51298$3350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51298$3350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51301$3353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51301$3353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + cell $not $not$libresoc.v:51306$3358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51306$3358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $not $not$libresoc.v:51308$3360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51308$3360_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $pos $pos$libresoc.v:51267$3319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:51267$3319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:51278$3330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } + connect \Y $pos$libresoc.v:51278$3330_Y + end + attribute \src "libresoc.v:51000.7-51000.20" + process $proc$libresoc.v:51000$3446 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:51187.7-51187.31" + process $proc$libresoc.v:51187$3447 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:51191.7-51191.33" + process $proc$libresoc.v:51191$3448 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:51197.7-51197.25" + process $proc$libresoc.v:51197$3449 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:51203.7-51203.27" + process $proc$libresoc.v:51203$3450 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:51207.7-51207.24" + process $proc$libresoc.v:51207$3451 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:51211.7-51211.22" + process $proc$libresoc.v:51211$3452 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:51215.7-51215.21" + process $proc$libresoc.v:51215$3453 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:51219.13-51219.31" + process $proc$libresoc.v:51219$3454 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:51225.14-51225.34" + process $proc$libresoc.v:51225$3455 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:51237.7-51237.22" + process $proc$libresoc.v:51237$3456 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:51243.7-51243.24" + process $proc$libresoc.v:51243$3457 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:51311.3-51312.51" + process $proc$libresoc.v:51311$3363 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:51313.3-51314.55" + process $proc$libresoc.v:51313$3364 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:51315.3-51316.41" + process $proc$libresoc.v:51315$3365 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:51317.3-51318.37" + process $proc$libresoc.v:51317$3366 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:51319.3-51320.33" + process $proc$libresoc.v:51319$3367 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:51321.3-51322.37" + process $proc$libresoc.v:51321$3368 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:51323.3-51324.39" + process $proc$libresoc.v:51323$3369 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:51325.3-51326.43" + process $proc$libresoc.v:51325$3370 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:51327.3-51328.37" + process $proc$libresoc.v:51327$3371 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:51329.3-51330.33" + process $proc$libresoc.v:51329$3372 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "libresoc.v:51331.3-51332.31" + process $proc$libresoc.v:51331$3373 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:51333.3-51350.6" + process $proc$libresoc.v:51333$3374 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:51334.5-51334.29" + switch \initial + attribute \src "libresoc.v:51334.9-51334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + attribute \src "libresoc.v:51351.3-51360.6" + process $proc$libresoc.v:51351$3375 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:51352.5-51352.29" + switch \initial + attribute \src "libresoc.v:51352.9-51352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "libresoc.v:51361.3-51369.6" + process $proc$libresoc.v:51361$3376 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$3377 $1\dmi_req_i_1$next[0:0]$3378 + attribute \src "libresoc.v:51362.5-51362.29" + switch \initial + attribute \src "libresoc.v:51362.9-51362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$3378 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$3378 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3377 + end + attribute \src "libresoc.v:51370.3-51419.6" + process $proc$libresoc.v:51370$3379 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$3380 $8\terminated$next[0:0]$3388 + attribute \src "libresoc.v:51371.5-51371.29" + switch \initial + attribute \src "libresoc.v:51371.9-51371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$67 \$63 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$3381 $2\terminated$next[0:0]$3382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$3382 $3\terminated$next[0:0]$3383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$73 \$71 \$69 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$3383 $6\terminated$next[0:0]$3386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$3384 1'0 + case + assign $4\terminated$next[0:0]$3384 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$3385 1'0 + case + assign $5\terminated$next[0:0]$3385 $4\terminated$next[0:0]$3384 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$3386 1'0 + case + assign $6\terminated$next[0:0]$3386 $5\terminated$next[0:0]$3385 + end + case + assign $3\terminated$next[0:0]$3383 \terminated + end + case + assign $2\terminated$next[0:0]$3382 \terminated + end + case + assign $1\terminated$next[0:0]$3381 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$3387 1'1 + case + assign $7\terminated$next[0:0]$3387 $1\terminated$next[0:0]$3381 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$3388 1'0 + case + assign $8\terminated$next[0:0]$3388 $7\terminated$next[0:0]$3387 + end + sync always + update \terminated$next $0\terminated$next[0:0]$3380 + end + attribute \src "libresoc.v:51420.3-51463.6" + process $proc$libresoc.v:51420$3389 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$3390 $7\stopping$next[0:0]$3397 + attribute \src "libresoc.v:51421.5-51421.29" + switch \initial + attribute \src "libresoc.v:51421.9-51421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$81 \$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$3391 $2\stopping$next[0:0]$3392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$3392 $3\stopping$next[0:0]$3393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$87 \$85 \$83 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$3393 $5\stopping$next[0:0]$3395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$3394 1'1 + case + assign $4\stopping$next[0:0]$3394 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$3395 1'0 + case + assign $5\stopping$next[0:0]$3395 $4\stopping$next[0:0]$3394 + end + case + assign $3\stopping$next[0:0]$3393 \stopping + end + case + assign $2\stopping$next[0:0]$3392 \stopping + end + case + assign $1\stopping$next[0:0]$3391 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$3396 1'1 + case + assign $6\stopping$next[0:0]$3396 $1\stopping$next[0:0]$3391 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$3397 1'0 + case + assign $7\stopping$next[0:0]$3397 $6\stopping$next[0:0]$3396 + end + sync always + update \stopping$next $0\stopping$next[0:0]$3390 + end + attribute \src "libresoc.v:51464.3-51491.6" + process $proc$libresoc.v:51464$3398 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$3399 $4\gspr_index$next[6:0]$3403 + attribute \src "libresoc.v:51465.5-51465.29" + switch \initial + attribute \src "libresoc.v:51465.9-51465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$95 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$3400 $2\gspr_index$next[6:0]$3401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$3401 $3\gspr_index$next[6:0]$3402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$101 \$99 \$97 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$3402 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$3402 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$3402 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$3401 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$3400 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$3403 7'0000000 + case + assign $4\gspr_index$next[6:0]$3403 $1\gspr_index$next[6:0]$3400 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$3399 + end + attribute \src "libresoc.v:51492.3-51525.6" + process $proc$libresoc.v:51492$3404 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$3405 $4\log_dmi_addr$next[31:0]$3409 + attribute \src "libresoc.v:51493.5-51493.29" + switch \initial + attribute \src "libresoc.v:51493.9-51493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$109 \$105 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$3406 $2\log_dmi_addr$next[31:0]$3407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$3407 $3\log_dmi_addr$next[31:0]$3408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$115 \$113 \$111 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$3408 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$3406 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3406 [1:0] \$117 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$3406 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$3409 0 + case + assign $4\log_dmi_addr$next[31:0]$3409 $1\log_dmi_addr$next[31:0]$3406 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3405 + end + attribute \src "libresoc.v:51526.3-51534.6" + process $proc$libresoc.v:51526$3410 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$3411 $1\dmi_read_log_data_1$next[0:0]$3412 + attribute \src "libresoc.v:51527.5-51527.29" + switch \initial + attribute \src "libresoc.v:51527.9-51527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$3412 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$3412 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3411 + end + attribute \src "libresoc.v:51535.3-51543.6" + process $proc$libresoc.v:51535$3413 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$3414 $1\dmi_read_log_data$next[0:0]$3415 + attribute \src "libresoc.v:51536.5-51536.29" + switch \initial + attribute \src "libresoc.v:51536.9-51536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$3415 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$3415 \$122 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3414 + end + attribute \src "libresoc.v:51544.3-51553.6" + process $proc$libresoc.v:51544$3416 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:51545.5-51545.29" + switch \initial + attribute \src "libresoc.v:51545.9-51545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "libresoc.v:51554.3-51563.6" + process $proc$libresoc.v:51554$3417 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:51555.5-51555.29" + switch \initial + attribute \src "libresoc.v:51555.9-51555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "libresoc.v:51564.3-51597.6" + process $proc$libresoc.v:51564$3418 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:51565.5-51565.29" + switch \initial + attribute \src "libresoc.v:51565.9-51565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\dmi_dout[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "libresoc.v:51598.3-51627.6" + process $proc$libresoc.v:51598$3419 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$3420 $5\do_step$next[0:0]$3425 + attribute \src "libresoc.v:51599.5-51599.29" + switch \initial + attribute \src "libresoc.v:51599.9-51599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$11 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$3421 $2\do_step$next[0:0]$3422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$3422 $3\do_step$next[0:0]$3423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$17 \$15 \$13 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$3423 $4\do_step$next[0:0]$3424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$3424 1'1 + case + assign $4\do_step$next[0:0]$3424 1'0 + end + case + assign $3\do_step$next[0:0]$3423 1'0 + end + case + assign $2\do_step$next[0:0]$3422 1'0 + end + case + assign $1\do_step$next[0:0]$3421 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$3425 1'0 + case + assign $5\do_step$next[0:0]$3425 $1\do_step$next[0:0]$3421 + end + sync always + update \do_step$next $0\do_step$next[0:0]$3420 + end + attribute \src "libresoc.v:51628.3-51657.6" + process $proc$libresoc.v:51628$3426 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$3427 $5\do_reset$next[0:0]$3432 + attribute \src "libresoc.v:51629.5-51629.29" + switch \initial + attribute \src "libresoc.v:51629.9-51629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch { \$25 \$21 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$3428 $2\do_reset$next[0:0]$3429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$3429 $3\do_reset$next[0:0]$3430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch { \$31 \$29 \$27 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$3430 $4\do_reset$next[0:0]$3431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \ALU_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 25 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \ALU_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 2 \ALU_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \ALU_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \ALU_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 26 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \ALU_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 output 22 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \ALU_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 24 \ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \ALU_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 17 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 23 \ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 20 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 18 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ALU_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 19 \ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 9 \ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 13 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \ALU_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec19_ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec19_ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec19_ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec19_ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \ALU_dec19_ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec19_ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec19_ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \ALU_dec19_ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec19_ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec19_ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec19_ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec19_ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec19_ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec19_ALU_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \ALU_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_ALU_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \ALU_dec31_ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \ALU_dec31_ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \ALU_dec31_ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \ALU_dec31_ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \ALU_dec31_ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \ALU_dec31_ALU_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \ALU_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 15 \ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 10 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 16 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 output 21 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:51736.7-51736.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 27 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:52937$3458 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:52937$3458_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:52938.13-52954.4" + cell \ALU_dec19 \ALU_dec19 + connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in + connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out + connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in + connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out + connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit + connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel + connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel + connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op + connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a + connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out + connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b + connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len + connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel + connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn + connect \opcode_in \ALU_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:52955.13-52971.4" + cell \ALU_dec31 \ALU_dec31 + connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in + connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out + connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in + connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out + connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit + connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel + connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel + connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op + connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a + connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out + connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b + connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len + connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel + connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn + connect \opcode_in \ALU_dec31_opcode_in + end + attribute \src "libresoc.v:51736.7-51736.20" + process $proc$libresoc.v:51736$3473 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:52972.3-53005.6" + process $proc$libresoc.v:52972$3459 + assign { } { } + assign { } { } + assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] + attribute \src "libresoc.v:52973.5-52973.29" + switch \initial + attribute \src "libresoc.v:52973.9-52973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + case + assign $1\ALU_rc_sel[1:0] 2'00 + end + sync always + update \ALU_rc_sel $0\ALU_rc_sel[1:0] + end + attribute \src "libresoc.v:53006.3-53039.6" + process $proc$libresoc.v:53006$3460 + assign { } { } + assign { } { } + assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] + attribute \src "libresoc.v:53007.5-53007.29" + switch \initial + attribute \src "libresoc.v:53007.9-53007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + case + assign $1\ALU_cry_in[1:0] 2'00 + end + sync always + update \ALU_cry_in $0\ALU_cry_in[1:0] + end + attribute \src "libresoc.v:53040.3-53073.6" + process $proc$libresoc.v:53040$3461 + assign { } { } + assign { } { } + assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] + attribute \src "libresoc.v:53041.5-53041.29" + switch \initial + attribute \src "libresoc.v:53041.9-53041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + case + assign $1\ALU_inv_a[0:0] 1'0 + end + sync always + update \ALU_inv_a $0\ALU_inv_a[0:0] + end + attribute \src "libresoc.v:53074.3-53107.6" + process $proc$libresoc.v:53074$3462 + assign { } { } + assign { } { } + assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] + attribute \src "libresoc.v:53075.5-53075.29" + switch \initial + attribute \src "libresoc.v:53075.9-53075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + case + assign $1\ALU_inv_out[0:0] 1'0 + end + sync always + update \ALU_inv_out $0\ALU_inv_out[0:0] + end + attribute \src "libresoc.v:53108.3-53141.6" + process $proc$libresoc.v:53108$3463 + assign { } { } + assign { } { } + assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] + attribute \src "libresoc.v:53109.5-53109.29" + switch \initial + attribute \src "libresoc.v:53109.9-53109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + case + assign $1\ALU_cry_out[0:0] 1'0 + end + sync always + update \ALU_cry_out $0\ALU_cry_out[0:0] + end + attribute \src "libresoc.v:53142.3-53175.6" + process $proc$libresoc.v:53142$3464 + assign { } { } + assign { } { } + assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] + attribute \src "libresoc.v:53143.5-53143.29" + switch \initial + attribute \src "libresoc.v:53143.9-53143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + case + assign $1\ALU_is_32b[0:0] 1'0 + end + sync always + update \ALU_is_32b $0\ALU_is_32b[0:0] + end + attribute \src "libresoc.v:53176.3-53209.6" + process $proc$libresoc.v:53176$3465 + assign { } { } + assign { } { } + assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] + attribute \src "libresoc.v:53177.5-53177.29" + switch \initial + attribute \src "libresoc.v:53177.9-53177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + case + assign $1\ALU_sgn[0:0] 1'0 + end + sync always + update \ALU_sgn $0\ALU_sgn[0:0] + end + attribute \src "libresoc.v:53210.3-53243.6" + process $proc$libresoc.v:53210$3466 + assign { } { } + assign { } { } + assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] + attribute \src "libresoc.v:53211.5-53211.29" + switch \initial + attribute \src "libresoc.v:53211.9-53211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_function_unit[13:0] \ALU_dec19_ALU_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_function_unit[13:0] \ALU_dec31_ALU_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_function_unit[13:0] 14'00000000000010 + case + assign $1\ALU_function_unit[13:0] 14'00000000000000 + end + sync always + update \ALU_function_unit $0\ALU_function_unit[13:0] + end + attribute \src "libresoc.v:53244.3-53277.6" + process $proc$libresoc.v:53244$3467 + assign { } { } + assign { } { } + assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] + attribute \src "libresoc.v:53245.5-53245.29" + switch \initial + attribute \src "libresoc.v:53245.9-53245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + case + assign $1\ALU_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_internal_op $0\ALU_internal_op[6:0] + end + attribute \src "libresoc.v:53278.3-53311.6" + process $proc$libresoc.v:53278$3468 + assign { } { } + assign { } { } + assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] + attribute \src "libresoc.v:53279.5-53279.29" + switch \initial + attribute \src "libresoc.v:53279.9-53279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + case + assign $1\ALU_in1_sel[2:0] 3'000 + end + sync always + update \ALU_in1_sel $0\ALU_in1_sel[2:0] + end + attribute \src "libresoc.v:53312.3-53345.6" + process $proc$libresoc.v:53312$3469 + assign { } { } + assign { } { } + assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] + attribute \src "libresoc.v:53313.5-53313.29" + switch \initial + attribute \src "libresoc.v:53313.9-53313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + case + assign $1\ALU_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_in2_sel $0\ALU_in2_sel[3:0] + end + attribute \src "libresoc.v:53346.3-53379.6" + process $proc$libresoc.v:53346$3470 + assign { } { } + assign { } { } + assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] + attribute \src "libresoc.v:53347.5-53347.29" + switch \initial + attribute \src "libresoc.v:53347.9-53347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + case + assign $1\ALU_cr_in[2:0] 3'000 + end + sync always + update \ALU_cr_in $0\ALU_cr_in[2:0] + end + attribute \src "libresoc.v:53380.3-53413.6" + process $proc$libresoc.v:53380$3471 + assign { } { } + assign { } { } + assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] + attribute \src "libresoc.v:53381.5-53381.29" + switch \initial + attribute \src "libresoc.v:53381.9-53381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + case + assign $1\ALU_cr_out[2:0] 3'000 + end + sync always + update \ALU_cr_out $0\ALU_cr_out[2:0] + end + attribute \src "libresoc.v:53414.3-53447.6" + process $proc$libresoc.v:53414$3472 + assign { } { } + assign { } { } + assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] + attribute \src "libresoc.v:53415.5-53415.29" + switch \initial + attribute \src "libresoc.v:53415.9-53415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + case + assign $1\ALU_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_ldst_len $0\ALU_ldst_len[3:0] + end + connect \$1 $ternary$libresoc.v:52937$3458_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \ALU_SPR \opcode_in [20:11] + connect \ALU_MB \opcode_in [10:6] + connect \ALU_ME \opcode_in [5:1] + connect \ALU_SH \opcode_in [15:11] + connect \ALU_BC \opcode_in [10:6] + connect \ALU_TO \opcode_in [25:21] + connect \ALU_DS \opcode_in [15:2] + connect \ALU_D \opcode_in [15:0] + connect \ALU_BH \opcode_in [12:11] + connect \ALU_BI \opcode_in [20:16] + connect \ALU_BO \opcode_in [25:21] + connect \ALU_FXM \opcode_in [19:12] + connect \ALU_BT \opcode_in [25:21] + connect \ALU_BA \opcode_in [20:16] + connect \ALU_BB \opcode_in [15:11] + connect \ALU_CR \opcode_in [10:1] + connect \ALU_BF \opcode_in [25:23] + connect \ALU_BD \opcode_in [15:2] + connect \ALU_OE \opcode_in [10] + connect \ALU_Rc \opcode_in [0] + connect \ALU_AA \opcode_in [1] + connect \ALU_LK \opcode_in [0] + connect \ALU_LI \opcode_in [25:2] + connect \ALU_ME32 \opcode_in [5:1] + connect \ALU_MB32 \opcode_in [10:6] + connect \ALU_sh { \opcode_in [1] \opcode_in [15:11] } + connect \ALU_SH32 \opcode_in [15:11] + connect \ALU_L \opcode_in [21] + connect \ALU_UI \opcode_in [15:0] + connect \ALU_SI \opcode_in [15:0] + connect \ALU_RB \opcode_in [15:11] + connect \ALU_RA \opcode_in [20:16] + connect \ALU_RT \opcode_in [25:21] + connect \ALU_RS \opcode_in [25:21] + connect \ALU_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \ALU_dec31_opcode_in \opcode_in + connect \ALU_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:53789.1-55254.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" +attribute \generator "nMigen" +module \dec$138 + attribute \src "libresoc.v:54878.3-54890.6" + wire width 3 $0\CR_cr_in[2:0] + attribute \src "libresoc.v:54891.3-54903.6" + wire width 3 $0\CR_cr_out[2:0] + attribute \src "libresoc.v:54852.3-54864.6" + wire width 14 $0\CR_function_unit[13:0] + attribute \src "libresoc.v:54865.3-54877.6" + wire width 7 $0\CR_internal_op[6:0] + attribute \src "libresoc.v:54904.3-54916.6" + wire width 2 $0\CR_rc_sel[1:0] + attribute \src "libresoc.v:53790.7-53790.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:54878.3-54890.6" + wire width 3 $1\CR_cr_in[2:0] + attribute \src "libresoc.v:54891.3-54903.6" + wire width 3 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 9 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \CR_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 8 \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \CR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \CR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \CR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \CR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \CR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec19_CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \CR_dec19_CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \CR_dec19_CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 10 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:54835$3474 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:54835$3474_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54836.12-54843.4" + cell \CR_dec19 \CR_dec19 + connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in + connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out + connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit + connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op + connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel + connect \opcode_in \CR_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54844.12-54851.4" + cell \CR_dec31 \CR_dec31 + connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in + connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out + connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit + connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op + connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel + connect \opcode_in \CR_dec31_opcode_in + end + attribute \src "libresoc.v:53790.7-53790.20" + process $proc$libresoc.v:53790$3480 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:54852.3-54864.6" + process $proc$libresoc.v:54852$3475 + assign { } { } + assign { } { } + assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] + attribute \src "libresoc.v:54853.5-54853.29" + switch \initial + attribute \src "libresoc.v:54853.9-54853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_function_unit[13:0] \CR_dec19_CR_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_function_unit[13:0] \CR_dec31_CR_dec31_function_unit + case + assign $1\CR_function_unit[13:0] 14'00000000000000 + end + sync always + update \CR_function_unit $0\CR_function_unit[13:0] + end + attribute \src "libresoc.v:54865.3-54877.6" + process $proc$libresoc.v:54865$3476 + assign { } { } + assign { } { } + assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] + attribute \src "libresoc.v:54866.5-54866.29" + switch \initial + attribute \src "libresoc.v:54866.9-54866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op + case + assign $1\CR_internal_op[6:0] 7'0000000 + end + sync always + update \CR_internal_op $0\CR_internal_op[6:0] + end + attribute \src "libresoc.v:54878.3-54890.6" + process $proc$libresoc.v:54878$3477 + assign { } { } + assign { } { } + assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] + attribute \src "libresoc.v:54879.5-54879.29" + switch \initial + attribute \src "libresoc.v:54879.9-54879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in + case + assign $1\CR_cr_in[2:0] 3'000 + end + sync always + update \CR_cr_in $0\CR_cr_in[2:0] + end + attribute \src "libresoc.v:54891.3-54903.6" + process $proc$libresoc.v:54891$3478 + assign { } { } + assign { } { } + assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] + attribute \src "libresoc.v:54892.5-54892.29" + switch \initial + attribute \src "libresoc.v:54892.9-54892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out + case + assign $1\CR_cr_out[2:0] 3'000 + end + sync always + update \CR_cr_out $0\CR_cr_out[2:0] + end + attribute \src "libresoc.v:54904.3-54916.6" + process $proc$libresoc.v:54904$3479 + assign { } { } + assign { } { } + assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] + attribute \src "libresoc.v:54905.5-54905.29" + switch \initial + attribute \src "libresoc.v:54905.9-54905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel + case + assign $1\CR_rc_sel[1:0] 2'00 + end + sync always + update \CR_rc_sel $0\CR_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:54835$3474_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \CR_SPR \opcode_in [20:11] + connect \CR_MB \opcode_in [10:6] + connect \CR_ME \opcode_in [5:1] + connect \CR_SH \opcode_in [15:11] + connect \CR_BC \opcode_in [10:6] + connect \CR_TO \opcode_in [25:21] + connect \CR_DS \opcode_in [15:2] + connect \CR_D \opcode_in [15:0] + connect \CR_BH \opcode_in [12:11] + connect \CR_BI \opcode_in [20:16] + connect \CR_BO \opcode_in [25:21] + connect \CR_FXM \opcode_in [19:12] + connect \CR_BT \opcode_in [25:21] + connect \CR_BA \opcode_in [20:16] + connect \CR_BB \opcode_in [15:11] + connect \CR_CR \opcode_in [10:1] + connect \CR_BF \opcode_in [25:23] + connect \CR_BD \opcode_in [15:2] + connect \CR_OE \opcode_in [10] + connect \CR_Rc \opcode_in [0] + connect \CR_AA \opcode_in [1] + connect \CR_LK \opcode_in [0] + connect \CR_LI \opcode_in [25:2] + connect \CR_ME32 \opcode_in [5:1] + connect \CR_MB32 \opcode_in [10:6] + connect \CR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \CR_SH32 \opcode_in [15:11] + connect \CR_L \opcode_in [21] + connect \CR_UI \opcode_in [15:0] + connect \CR_SI \opcode_in [15:0] + connect \CR_RB \opcode_in [15:11] + connect \CR_RA \opcode_in [20:16] + connect \CR_RT \opcode_in [25:21] + connect \CR_RS \opcode_in [25:21] + connect \CR_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \CR_dec31_opcode_in \opcode_in + connect \CR_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:55258.1-56703.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" +attribute \generator "nMigen" +module \dec$141 + attribute \src "libresoc.v:56287.3-56302.6" + wire width 3 $0\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:56303.3-56318.6" + wire width 3 $0\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:56239.3-56254.6" + wire width 14 $0\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56271.3-56286.6" + wire width 4 $0\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:56255.3-56270.6" + wire width 7 $0\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:56335.3-56350.6" + wire $0\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:56351.3-56366.6" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \BRANCH_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 19 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \BRANCH_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 2 \BRANCH_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \BRANCH_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \BRANCH_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 20 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \BRANCH_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 output 16 \BRANCH_LI + attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 17 \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 14 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 12 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \BRANCH_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 13 \BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 8 \BRANCH_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute 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"CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute 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attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:55259.7-55259.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:56227$3481 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:56227$3481_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:56228.16-56238.4" + cell \BRANCH_dec19 \BRANCH_dec19 + connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in + connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out + connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit + connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel + connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op + connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b + connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk + connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel + connect \opcode_in \BRANCH_dec19_opcode_in + end + attribute \src "libresoc.v:55259.7-55259.20" + process $proc$libresoc.v:55259$3490 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:56239.3-56254.6" + process $proc$libresoc.v:56239$3482 + assign { } { } + assign { } { } + assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56240.5-56240.29" + switch \initial + attribute \src "libresoc.v:56240.9-56240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_function_unit[13:0] \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_function_unit[13:0] 14'00000000100000 + case + assign $1\BRANCH_function_unit[13:0] 14'00000000000000 + end + sync always + update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] + end + attribute \src "libresoc.v:56255.3-56270.6" + process $proc$libresoc.v:56255$3483 + assign { } { } + assign { } { } + assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:56256.5-56256.29" + switch \initial + attribute \src "libresoc.v:56256.9-56256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000111 + case + assign $1\BRANCH_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] + end + attribute \src "libresoc.v:56271.3-56286.6" + process $proc$libresoc.v:56271$3484 + assign { } { } + assign { } { } + assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:56272.5-56272.29" + switch \initial + attribute \src "libresoc.v:56272.9-56272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0111 + case + assign $1\BRANCH_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] + end + attribute \src "libresoc.v:56287.3-56302.6" + process $proc$libresoc.v:56287$3485 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:56288.5-56288.29" + switch \initial + attribute \src "libresoc.v:56288.9-56288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'010 + case + assign $1\BRANCH_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] + end + attribute \src "libresoc.v:56303.3-56318.6" + process $proc$libresoc.v:56303$3486 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:56304.5-56304.29" + switch \initial + attribute \src "libresoc.v:56304.9-56304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + case + assign $1\BRANCH_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] + end + attribute \src "libresoc.v:56319.3-56334.6" + process $proc$libresoc.v:56319$3487 + assign { } { } + assign { } { } + assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:56320.5-56320.29" + switch \initial + attribute \src "libresoc.v:56320.9-56320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] + end + attribute \src "libresoc.v:56335.3-56350.6" + process $proc$libresoc.v:56335$3488 + assign { } { } + assign { } { } + assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:56336.5-56336.29" + switch \initial + attribute \src "libresoc.v:56336.9-56336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + case + assign $1\BRANCH_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] + end + attribute \src "libresoc.v:56351.3-56366.6" + process $proc$libresoc.v:56351$3489 + assign { } { } + assign { } { } + assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:56352.5-56352.29" + switch \initial + attribute \src "libresoc.v:56352.9-56352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + case + assign $1\BRANCH_lk[0:0] 1'0 + end + sync always + update \BRANCH_lk $0\BRANCH_lk[0:0] + end + connect \$1 $ternary$libresoc.v:56227$3481_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \BRANCH_SPR \opcode_in [20:11] + connect \BRANCH_MB \opcode_in [10:6] + connect \BRANCH_ME \opcode_in [5:1] + connect \BRANCH_SH \opcode_in [15:11] + connect \BRANCH_BC \opcode_in [10:6] + connect \BRANCH_TO \opcode_in [25:21] + connect \BRANCH_DS \opcode_in [15:2] + connect \BRANCH_D \opcode_in [15:0] + connect \BRANCH_BH \opcode_in [12:11] + connect \BRANCH_BI \opcode_in [20:16] + connect \BRANCH_BO \opcode_in [25:21] + connect \BRANCH_FXM \opcode_in [19:12] + connect \BRANCH_BT \opcode_in [25:21] + connect \BRANCH_BA \opcode_in [20:16] + connect \BRANCH_BB \opcode_in [15:11] + connect \BRANCH_CR \opcode_in [10:1] + connect \BRANCH_BF \opcode_in [25:23] + connect \BRANCH_BD \opcode_in [15:2] + connect \BRANCH_OE \opcode_in [10] + connect \BRANCH_Rc \opcode_in [0] + connect \BRANCH_AA \opcode_in [1] + connect \BRANCH_LK \opcode_in [0] + connect \BRANCH_LI \opcode_in [25:2] + connect \BRANCH_ME32 \opcode_in [5:1] + connect \BRANCH_MB32 \opcode_in [10:6] + connect \BRANCH_sh { \opcode_in [1] \opcode_in [15:11] } + connect \BRANCH_SH32 \opcode_in [15:11] + connect \BRANCH_L \opcode_in [21] + connect \BRANCH_UI \opcode_in [15:0] + connect \BRANCH_SI \opcode_in [15:0] + connect \BRANCH_RB \opcode_in [15:11] + connect \BRANCH_RA \opcode_in [20:16] + connect \BRANCH_RT \opcode_in [25:21] + connect \BRANCH_RS \opcode_in [25:21] + connect \BRANCH_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \BRANCH_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:56707.1-58484.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \LOGICAL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 25 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \LOGICAL_BF + attribute \src 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9 \LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 13 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \LOGICAL_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \LOGICAL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 15 \LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 10 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 16 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 output 21 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src 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\opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 27 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:57738$3491 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:57738$3491_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:57739.17-57755.4" + cell \LOGICAL_dec31 \LOGICAL_dec31 + connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in + connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out + connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in + connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out + connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit + connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel + connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel + connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op + connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a + connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out + connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b + connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len + connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel + connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn + connect \opcode_in \LOGICAL_dec31_opcode_in + end + attribute \src "libresoc.v:56708.7-56708.20" + process $proc$libresoc.v:56708$3506 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:57756.3-57783.6" + process $proc$libresoc.v:57756$3492 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:57757.5-57757.29" + switch \initial + attribute \src "libresoc.v:57757.9-57757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] + end + attribute \src "libresoc.v:57784.3-57811.6" + process $proc$libresoc.v:57784$3493 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:57785.5-57785.29" + switch \initial + attribute \src "libresoc.v:57785.9-57785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] + end + attribute \src "libresoc.v:57812.3-57839.6" + process $proc$libresoc.v:57812$3494 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:57813.5-57813.29" + switch \initial + attribute \src "libresoc.v:57813.9-57813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] + end + attribute \src "libresoc.v:57840.3-57867.6" + process $proc$libresoc.v:57840$3495 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57841.5-57841.29" + switch \initial + attribute \src "libresoc.v:57841.9-57841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] + end + attribute \src "libresoc.v:57868.3-57895.6" + process $proc$libresoc.v:57868$3496 + assign { } { } + assign { } { } + assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:57869.5-57869.29" + switch \initial + attribute \src "libresoc.v:57869.9-57869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] + end + attribute \src "libresoc.v:57896.3-57923.6" + process $proc$libresoc.v:57896$3497 + assign { } { } + assign { } { } + assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:57897.5-57897.29" + switch \initial + attribute \src "libresoc.v:57897.9-57897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + case + assign $1\LOGICAL_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] + end + attribute \src "libresoc.v:57924.3-57951.6" + process $proc$libresoc.v:57924$3498 + assign { } { } + assign { } { } + assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57925.5-57925.29" + switch \initial + attribute \src "libresoc.v:57925.9-57925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 + case + assign $1\LOGICAL_function_unit[13:0] 14'00000000000000 + end + sync always + update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] + end + attribute \src "libresoc.v:57952.3-57979.6" + process $proc$libresoc.v:57952$3499 + assign { } { } + assign { } { } + assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:57953.5-57953.29" + switch \initial + attribute \src "libresoc.v:57953.9-57953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] + end + attribute \src "libresoc.v:57980.3-58007.6" + process $proc$libresoc.v:57980$3500 + assign { } { } + assign { } { } + assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57981.5-57981.29" + switch \initial + attribute \src "libresoc.v:57981.9-57981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] + end + attribute \src "libresoc.v:58008.3-58035.6" + process $proc$libresoc.v:58008$3501 + assign { } { } + assign { } { } + assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:58009.5-58009.29" + switch \initial + attribute \src "libresoc.v:58009.9-58009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + case + assign $1\LOGICAL_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] + end + attribute \src "libresoc.v:58036.3-58063.6" + process $proc$libresoc.v:58036$3502 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:58037.5-58037.29" + switch \initial + attribute \src "libresoc.v:58037.9-58037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] + end + attribute \src "libresoc.v:58064.3-58091.6" + process $proc$libresoc.v:58064$3503 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:58065.5-58065.29" + switch \initial + attribute \src "libresoc.v:58065.9-58065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] + end + attribute \src "libresoc.v:58092.3-58119.6" + process $proc$libresoc.v:58092$3504 + assign { } { } + assign { } { } + assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:58093.5-58093.29" + switch \initial + attribute \src "libresoc.v:58093.9-58093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] + end + attribute \src "libresoc.v:58120.3-58147.6" + process $proc$libresoc.v:58120$3505 + assign { } { } + assign { } { } + assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:58121.5-58121.29" + switch \initial + attribute \src "libresoc.v:58121.9-58121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:57738$3491_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LOGICAL_SPR \opcode_in [20:11] + connect \LOGICAL_MB \opcode_in [10:6] + connect \LOGICAL_ME \opcode_in [5:1] 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\enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SPR_dec31_SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SPR_dec31_SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SPR_dec31_SPR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SPR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 8 \SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \SPR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:58489.7-58489.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 11 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:59417$3507 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:59417$3507_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:59418.13-59426.4" + cell \SPR_dec31 \SPR_dec31 + connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in + connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out + connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit + connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op + connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b + connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel + connect \opcode_in \SPR_dec31_opcode_in + end + attribute \src "libresoc.v:58489.7-58489.20" + process $proc$libresoc.v:58489$3514 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:59427.3-59436.6" + process $proc$libresoc.v:59427$3508 + assign { } { } + assign { } { } + assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] + attribute \src "libresoc.v:59428.5-59428.29" + switch \initial + attribute \src "libresoc.v:59428.9-59428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_function_unit[13:0] \SPR_dec31_SPR_dec31_function_unit + case + assign $1\SPR_function_unit[13:0] 14'00000000000000 + end + sync always + update \SPR_function_unit $0\SPR_function_unit[13:0] + end + attribute \src "libresoc.v:59437.3-59446.6" + process $proc$libresoc.v:59437$3509 + assign { } { } + assign { } { } + assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:59438.5-59438.29" + switch \initial + attribute \src "libresoc.v:59438.9-59438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op + case + assign $1\SPR_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_internal_op $0\SPR_internal_op[6:0] + end + attribute \src "libresoc.v:59447.3-59456.6" + process $proc$libresoc.v:59447$3510 + assign { } { } + assign { } { } + assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:59448.5-59448.29" + switch \initial + attribute \src "libresoc.v:59448.9-59448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in + case + assign $1\SPR_cr_in[2:0] 3'000 + end + sync always + update \SPR_cr_in $0\SPR_cr_in[2:0] + end + attribute \src "libresoc.v:59457.3-59466.6" + process $proc$libresoc.v:59457$3511 + assign { } { } + assign { } { } + assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:59458.5-59458.29" + switch \initial + attribute \src "libresoc.v:59458.9-59458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out + case + assign $1\SPR_cr_out[2:0] 3'000 + end + sync always + update \SPR_cr_out $0\SPR_cr_out[2:0] + end + attribute \src "libresoc.v:59467.3-59476.6" + process $proc$libresoc.v:59467$3512 + assign { } { } + assign { } { } + assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:59468.5-59468.29" + switch \initial + attribute \src "libresoc.v:59468.9-59468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel + case + assign $1\SPR_rc_sel[1:0] 2'00 + end + sync always + update \SPR_rc_sel $0\SPR_rc_sel[1:0] + end + attribute \src "libresoc.v:59477.3-59486.6" + process $proc$libresoc.v:59477$3513 + assign { } { } + assign { } { } + assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:59478.5-59478.29" + switch \initial + attribute \src "libresoc.v:59478.9-59478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b + case + assign $1\SPR_is_32b[0:0] 1'0 + end + sync always + update \SPR_is_32b $0\SPR_is_32b[0:0] + end + connect \$1 $ternary$libresoc.v:59417$3507_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR_SPR \opcode_in [20:11] + connect \SPR_MB \opcode_in [10:6] + connect \SPR_ME \opcode_in [5:1] + connect \SPR_SH \opcode_in [15:11] + connect \SPR_BC \opcode_in [10:6] + connect \SPR_TO \opcode_in [25:21] + connect \SPR_DS \opcode_in [15:2] + connect \SPR_D \opcode_in [15:0] + connect \SPR_BH \opcode_in [12:11] + connect \SPR_BI \opcode_in [20:16] + connect \SPR_BO \opcode_in [25:21] + connect \SPR_FXM \opcode_in [19:12] + connect \SPR_BT \opcode_in [25:21] + connect \SPR_BA \opcode_in [20:16] + connect \SPR_BB \opcode_in [15:11] + connect \SPR_CR \opcode_in [10:1] + connect \SPR_BF \opcode_in [25:23] + connect \SPR_BD \opcode_in [15:2] + connect \SPR_OE \opcode_in [10] + connect \SPR_Rc \opcode_in [0] + connect \SPR_AA \opcode_in [1] + connect \SPR_LK \opcode_in [0] + connect \SPR_LI \opcode_in [25:2] + connect \SPR_ME32 \opcode_in [5:1] + connect \SPR_MB32 \opcode_in [10:6] + connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SPR_SH32 \opcode_in [15:11] + connect \SPR_L \opcode_in [21] + connect \SPR_UI \opcode_in [15:0] + connect \SPR_SI \opcode_in [15:0] + connect \SPR_RB \opcode_in [15:11] + connect \SPR_RA \opcode_in [20:16] + connect \SPR_RT \opcode_in [25:21] + connect \SPR_RS \opcode_in [25:21] + connect \SPR_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \SPR_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:59827.1-61352.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" +attribute \generator "nMigen" +module \dec$153 + attribute \src "libresoc.v:60976.3-60985.6" + wire width 3 $0\DIV_cr_in[2:0] + attribute \src "libresoc.v:60986.3-60995.6" + wire width 3 $0\DIV_cr_out[2:0] + attribute \src "libresoc.v:60876.3-60885.6" + wire width 2 $0\DIV_cry_in[1:0] + attribute \src "libresoc.v:60906.3-60915.6" + wire $0\DIV_cry_out[0:0] + attribute \src "libresoc.v:60936.3-60945.6" + wire width 14 $0\DIV_function_unit[13:0] + attribute \src "libresoc.v:60956.3-60965.6" + wire width 3 $0\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60966.3-60975.6" + wire width 4 $0\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60946.3-60955.6" + wire width 7 $0\DIV_internal_op[6:0] + attribute \src "libresoc.v:60886.3-60895.6" + wire $0\DIV_inv_a[0:0] + attribute \src "libresoc.v:60896.3-60905.6" + wire $0\DIV_inv_out[0:0] + attribute \src "libresoc.v:60916.3-60925.6" + wire $0\DIV_is_32b[0:0] + attribute \src "libresoc.v:60996.3-61005.6" + wire width 4 $0\DIV_ldst_len[3:0] + attribute \src "libresoc.v:61006.3-61015.6" + wire width 2 $0\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60926.3-60935.6" + wire $0\DIV_sgn[0:0] + attribute \src "libresoc.v:59828.7-59828.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:60976.3-60985.6" + wire width 3 $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:60986.3-60995.6" + wire width 3 $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:60876.3-60885.6" + wire width 2 $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:60906.3-60915.6" + wire $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:60936.3-60945.6" + wire width 14 $1\DIV_function_unit[13:0] + attribute \src "libresoc.v:60956.3-60965.6" + wire width 3 $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60966.3-60975.6" + wire width 4 $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60946.3-60955.6" + wire width 7 $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:60886.3-60895.6" + wire $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:60896.3-60905.6" + wire $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:60916.3-60925.6" + wire $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:60996.3-61005.6" + wire width 4 $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:61006.3-61015.6" + wire width 2 $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60926.3-60935.6" + wire $1\DIV_sgn[0:0] + attribute \src "libresoc.v:60858.17-60858.211" + wire width 32 $ternary$libresoc.v:60858$3515_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \DIV_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 25 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \DIV_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 2 \DIV_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \DIV_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \DIV_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 26 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \DIV_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 output 22 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \DIV_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 24 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \DIV_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 17 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 23 \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 20 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 18 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \DIV_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 19 \DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 9 \DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 13 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \DIV_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \DIV_dec31_DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_DIV_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \DIV_dec31_DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \DIV_dec31_DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \DIV_dec31_DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \DIV_dec31_DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \DIV_dec31_DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \DIV_dec31_DIV_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \DIV_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 15 \DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 10 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 16 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 output 21 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BFA + attribute \src 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wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_T + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:59828.7-59828.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 27 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:60858$3515 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:60858$3515_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:60859.13-60875.4" + cell \DIV_dec31 \DIV_dec31 + connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in + connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out + connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in + connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out + connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit + connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel + connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel + connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op + connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a + connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out + connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b + connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len + connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel + connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn + connect \opcode_in \DIV_dec31_opcode_in + end + attribute \src "libresoc.v:59828.7-59828.20" + process $proc$libresoc.v:59828$3530 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:60876.3-60885.6" + process $proc$libresoc.v:60876$3516 + assign { } { } + assign { } { } + assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:60877.5-60877.29" + switch \initial + attribute \src "libresoc.v:60877.9-60877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in + case + assign $1\DIV_cry_in[1:0] 2'00 + end + sync always + update \DIV_cry_in $0\DIV_cry_in[1:0] + end + attribute \src "libresoc.v:60886.3-60895.6" + process $proc$libresoc.v:60886$3517 + assign { } { } + assign { } { } + assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:60887.5-60887.29" + switch \initial + attribute \src "libresoc.v:60887.9-60887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a + case + assign $1\DIV_inv_a[0:0] 1'0 + end + sync always + update \DIV_inv_a $0\DIV_inv_a[0:0] + end + attribute \src "libresoc.v:60896.3-60905.6" + process $proc$libresoc.v:60896$3518 + assign { } { } + assign { } { } + assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:60897.5-60897.29" + switch \initial + attribute \src "libresoc.v:60897.9-60897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out + case + assign $1\DIV_inv_out[0:0] 1'0 + end + sync always + update \DIV_inv_out $0\DIV_inv_out[0:0] + end + attribute \src "libresoc.v:60906.3-60915.6" + process $proc$libresoc.v:60906$3519 + assign { } { } + assign { } { } + assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:60907.5-60907.29" + switch \initial + attribute \src "libresoc.v:60907.9-60907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out + case + assign $1\DIV_cry_out[0:0] 1'0 + end + sync always + update \DIV_cry_out $0\DIV_cry_out[0:0] + end + attribute \src "libresoc.v:60916.3-60925.6" + process $proc$libresoc.v:60916$3520 + assign { } { } + assign { } { } + assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:60917.5-60917.29" + switch \initial + attribute \src "libresoc.v:60917.9-60917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b + case + assign $1\DIV_is_32b[0:0] 1'0 + end + sync always + update \DIV_is_32b $0\DIV_is_32b[0:0] + end + attribute \src "libresoc.v:60926.3-60935.6" + process $proc$libresoc.v:60926$3521 + assign { } { } + assign { } { } + assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] + attribute \src "libresoc.v:60927.5-60927.29" + switch \initial + attribute \src "libresoc.v:60927.9-60927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn + case + assign $1\DIV_sgn[0:0] 1'0 + end + sync always + update \DIV_sgn $0\DIV_sgn[0:0] + end + attribute \src "libresoc.v:60936.3-60945.6" + process $proc$libresoc.v:60936$3522 + assign { } { } + assign { } { } + assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] + attribute \src "libresoc.v:60937.5-60937.29" + switch \initial + attribute \src "libresoc.v:60937.9-60937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_function_unit[13:0] \DIV_dec31_DIV_dec31_function_unit + case + assign $1\DIV_function_unit[13:0] 14'00000000000000 + end + sync always + update \DIV_function_unit $0\DIV_function_unit[13:0] + end + attribute \src "libresoc.v:60946.3-60955.6" + process $proc$libresoc.v:60946$3523 + assign { } { } + assign { } { } + assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:60947.5-60947.29" + switch \initial + attribute \src "libresoc.v:60947.9-60947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op + case + assign $1\DIV_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_internal_op $0\DIV_internal_op[6:0] + end + attribute \src "libresoc.v:60956.3-60965.6" + process $proc$libresoc.v:60956$3524 + assign { } { } + assign { } { } + assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60957.5-60957.29" + switch \initial + attribute \src "libresoc.v:60957.9-60957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel + case + assign $1\DIV_in1_sel[2:0] 3'000 + end + sync always + update \DIV_in1_sel $0\DIV_in1_sel[2:0] + end + attribute \src "libresoc.v:60966.3-60975.6" + process $proc$libresoc.v:60966$3525 + assign { } { } + assign { } { } + assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60967.5-60967.29" + switch \initial + attribute \src "libresoc.v:60967.9-60967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel + case + assign $1\DIV_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_in2_sel $0\DIV_in2_sel[3:0] + end + attribute \src "libresoc.v:60976.3-60985.6" + process $proc$libresoc.v:60976$3526 + assign { } { } + assign { } { } + assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:60977.5-60977.29" + switch \initial + attribute \src "libresoc.v:60977.9-60977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in + case + assign $1\DIV_cr_in[2:0] 3'000 + end + sync always + update \DIV_cr_in $0\DIV_cr_in[2:0] + end + attribute \src "libresoc.v:60986.3-60995.6" + process $proc$libresoc.v:60986$3527 + assign { } { } + assign { } { } + assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:60987.5-60987.29" + switch \initial + attribute \src "libresoc.v:60987.9-60987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out + case + assign $1\DIV_cr_out[2:0] 3'000 + end + sync always + update \DIV_cr_out $0\DIV_cr_out[2:0] + end + attribute \src "libresoc.v:60996.3-61005.6" + process $proc$libresoc.v:60996$3528 + assign { } { } + assign { } { } + assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60997.5-60997.29" + switch \initial + attribute \src "libresoc.v:60997.9-60997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len + case + assign $1\DIV_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_ldst_len $0\DIV_ldst_len[3:0] + end + attribute \src "libresoc.v:61006.3-61015.6" + process $proc$libresoc.v:61006$3529 + assign { } { } + assign { } { } + assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:61007.5-61007.29" + switch \initial + attribute \src "libresoc.v:61007.9-61007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel + case + assign $1\DIV_rc_sel[1:0] 2'00 + end + sync always + update \DIV_rc_sel $0\DIV_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:60858$3515_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \DIV_SPR \opcode_in [20:11] + connect \DIV_MB \opcode_in [10:6] + connect \DIV_ME \opcode_in [5:1] + connect \DIV_SH \opcode_in [15:11] + connect \DIV_BC \opcode_in [10:6] + connect \DIV_TO \opcode_in [25:21] + connect \DIV_DS \opcode_in [15:2] + connect \DIV_D \opcode_in [15:0] + connect \DIV_BH \opcode_in [12:11] + connect \DIV_BI \opcode_in [20:16] + connect \DIV_BO \opcode_in [25:21] + connect \DIV_FXM \opcode_in [19:12] + connect \DIV_BT \opcode_in [25:21] + connect \DIV_BA \opcode_in [20:16] + connect \DIV_BB \opcode_in [15:11] + connect \DIV_CR \opcode_in [10:1] + connect \DIV_BF \opcode_in [25:23] + connect \DIV_BD \opcode_in [15:2] + connect \DIV_OE \opcode_in [10] + connect \DIV_Rc \opcode_in [0] + connect \DIV_AA \opcode_in [1] + connect \DIV_LK \opcode_in [0] + connect \DIV_LI \opcode_in [25:2] + connect \DIV_ME32 \opcode_in [5:1] + connect \DIV_MB32 \opcode_in [10:6] + connect \DIV_sh { \opcode_in [1] \opcode_in [15:11] } + connect \DIV_SH32 \opcode_in [15:11] + connect \DIV_L \opcode_in [21] + connect \DIV_UI \opcode_in [15:0] + connect \DIV_SI \opcode_in [15:0] + connect \DIV_RB \opcode_in [15:11] + connect \DIV_RA \opcode_in [20:16] + connect \DIV_RT \opcode_in [25:21] + connect \DIV_RS \opcode_in [25:21] + connect \DIV_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \DIV_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:61356.1-62777.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" +attribute \generator "nMigen" +module \dec$158 + attribute \src "libresoc.v:62376.3-62388.6" + wire width 3 $0\MUL_cr_in[2:0] + attribute \src "libresoc.v:62389.3-62401.6" + wire width 3 $0\MUL_cr_out[2:0] + attribute \src "libresoc.v:62337.3-62349.6" + wire width 14 $0\MUL_function_unit[13:0] + attribute \src "libresoc.v:62363.3-62375.6" + wire width 4 $0\MUL_in2_sel[3:0] + attribute \src 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attribute \src "libresoc.v:62325.17-62325.211" + wire width 32 $ternary$libresoc.v:62325$3531_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RB + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \MUL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 18 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \MUL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 2 \MUL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \MUL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \MUL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 19 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \MUL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 output 15 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \MUL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 17 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \MUL_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 16 \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 13 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 11 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \MUL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 12 \MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 8 \MUL_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_dec31_MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \MUL_dec31_MUL_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \MUL_dec31_MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \MUL_dec31_MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \MUL_dec31_MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \MUL_dec31_MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \MUL_dec31_MUL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \MUL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 9 \MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 output 14 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO_1 + attribute \src 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wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_BX + attribute \src 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wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_UIM + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:61357.7-61357.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:62325$3531 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:62325$3531_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:62326.13-62336.4" + cell \MUL_dec31 \MUL_dec31 + connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in + connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out + connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit + connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel + connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op + connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b + connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel + connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn + connect \opcode_in \MUL_dec31_opcode_in + end + attribute \src "libresoc.v:61357.7-61357.20" + process $proc$libresoc.v:61357$3540 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:62337.3-62349.6" + process $proc$libresoc.v:62337$3532 + assign { } { } + assign { } { } + assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] + attribute \src "libresoc.v:62338.5-62338.29" + switch \initial + attribute \src "libresoc.v:62338.9-62338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_function_unit[13:0] \MUL_dec31_MUL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_function_unit[13:0] 14'00000100000000 + case + assign $1\MUL_function_unit[13:0] 14'00000000000000 + end + sync always + update \MUL_function_unit $0\MUL_function_unit[13:0] + end + attribute \src "libresoc.v:62350.3-62362.6" + process $proc$libresoc.v:62350$3533 + assign { } { } + assign { } { } + assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:62351.5-62351.29" + switch \initial + attribute \src "libresoc.v:62351.9-62351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_internal_op[6:0] 7'0110010 + case + assign $1\MUL_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_internal_op $0\MUL_internal_op[6:0] + end + attribute \src "libresoc.v:62363.3-62375.6" + process $proc$libresoc.v:62363$3534 + assign { } { } + assign { } { } + assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:62364.5-62364.29" + switch \initial + attribute \src "libresoc.v:62364.9-62364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_in2_sel[3:0] 4'0011 + case + assign $1\MUL_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_in2_sel $0\MUL_in2_sel[3:0] + end + attribute \src "libresoc.v:62376.3-62388.6" + process $proc$libresoc.v:62376$3535 + assign { } { } + assign { } { } + assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:62377.5-62377.29" + switch \initial + attribute \src "libresoc.v:62377.9-62377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_in[2:0] 3'000 + case + assign $1\MUL_cr_in[2:0] 3'000 + end + sync always + update \MUL_cr_in $0\MUL_cr_in[2:0] + end + attribute \src "libresoc.v:62389.3-62401.6" + process $proc$libresoc.v:62389$3536 + assign { } { } + assign { } { } + assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:62390.5-62390.29" + switch \initial + attribute \src "libresoc.v:62390.9-62390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_out[2:0] 3'001 + case + assign $1\MUL_cr_out[2:0] 3'000 + end + sync always + update \MUL_cr_out $0\MUL_cr_out[2:0] + end + attribute \src "libresoc.v:62402.3-62414.6" + process $proc$libresoc.v:62402$3537 + assign { } { } + assign { } { } + assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:62403.5-62403.29" + switch \initial + attribute \src "libresoc.v:62403.9-62403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_rc_sel[1:0] 2'00 + case + assign $1\MUL_rc_sel[1:0] 2'00 + end + sync always + update \MUL_rc_sel $0\MUL_rc_sel[1:0] + end + attribute \src "libresoc.v:62415.3-62427.6" + process $proc$libresoc.v:62415$3538 + assign { } { } + assign { } { } + assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:62416.5-62416.29" + switch \initial + attribute \src "libresoc.v:62416.9-62416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_is_32b[0:0] 1'0 + case + assign $1\MUL_is_32b[0:0] 1'0 + end + sync always + update \MUL_is_32b $0\MUL_is_32b[0:0] + end + attribute \src "libresoc.v:62428.3-62440.6" + process $proc$libresoc.v:62428$3539 + assign { } { } + assign { } { } + assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] + attribute \src "libresoc.v:62429.5-62429.29" + switch \initial + attribute \src "libresoc.v:62429.9-62429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_sgn[0:0] 1'1 + case + assign $1\MUL_sgn[0:0] 1'0 + end + sync always + update \MUL_sgn $0\MUL_sgn[0:0] + end + connect \$1 $ternary$libresoc.v:62325$3531_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \MUL_SPR \opcode_in [20:11] + connect \MUL_MB \opcode_in [10:6] + connect \MUL_ME \opcode_in [5:1] + connect \MUL_SH \opcode_in [15:11] + connect \MUL_BC \opcode_in [10:6] + connect \MUL_TO \opcode_in [25:21] + connect \MUL_DS \opcode_in [15:2] + connect \MUL_D \opcode_in [15:0] + connect \MUL_BH \opcode_in [12:11] + connect \MUL_BI \opcode_in [20:16] + connect \MUL_BO \opcode_in [25:21] + connect \MUL_FXM \opcode_in [19:12] + connect \MUL_BT \opcode_in [25:21] + connect \MUL_BA \opcode_in [20:16] + connect \MUL_BB \opcode_in [15:11] + connect \MUL_CR \opcode_in [10:1] + connect \MUL_BF \opcode_in [25:23] + connect \MUL_BD \opcode_in [15:2] + connect \MUL_OE \opcode_in [10] + connect \MUL_Rc \opcode_in [0] + connect \MUL_AA \opcode_in [1] + connect \MUL_LK \opcode_in [0] + connect \MUL_LI \opcode_in [25:2] + connect \MUL_ME32 \opcode_in [5:1] + connect \MUL_MB32 \opcode_in [10:6] + connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MUL_SH32 \opcode_in [15:11] + connect \MUL_L \opcode_in [21] + connect \MUL_UI \opcode_in [15:0] + connect \MUL_SI \opcode_in [15:0] + connect \MUL_RB \opcode_in [15:11] + connect \MUL_RA \opcode_in [20:16] + connect \MUL_RT \opcode_in [25:21] + connect \MUL_RS \opcode_in [25:21] + connect \MUL_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \MUL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:62781.1-64535.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" +attribute \generator "nMigen" +module \dec$162 + attribute \src "libresoc.v:64110.3-64131.6" + wire width 3 $0\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:64132.3-64153.6" + wire width 3 $0\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:64176.3-64197.6" + wire width 2 $0\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63978.3-63999.6" + wire $0\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:64044.3-64065.6" + wire width 14 $0\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:64088.3-64109.6" + wire width 4 $0\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:64066.3-64087.6" + wire width 7 $0\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:63956.3-63977.6" + wire $0\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:64000.3-64021.6" + wire $0\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:64154.3-64175.6" + wire width 2 $0\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:64022.3-64043.6" + wire $0\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:62782.7-62782.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:64110.3-64131.6" + wire width 3 $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:64132.3-64153.6" + wire width 3 $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:64176.3-64197.6" + wire width 2 $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63978.3-63999.6" + wire $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:64044.3-64065.6" + wire width 14 $1\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:64088.3-64109.6" + wire width 4 $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:64066.3-64087.6" + wire width 7 $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:63956.3-63977.6" + wire $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:64000.3-64021.6" + wire $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:64154.3-64175.6" + wire width 2 $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:64022.3-64043.6" + wire $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:63927.17-63927.211" + wire width 32 $ternary$libresoc.v:63927$3541_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \SHIFT_ROT_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 22 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \SHIFT_ROT_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 2 \SHIFT_ROT_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \SHIFT_ROT_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \SHIFT_ROT_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 23 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \SHIFT_ROT_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 output 19 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \SHIFT_ROT_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 21 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \SHIFT_ROT_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 20 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 17 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 15 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SHIFT_ROT_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 16 \SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 9 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 8 \SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 11 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \SHIFT_ROT_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SHIFT_ROT_dec30_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \SHIFT_ROT_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 7 \SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 10 \SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 output 18 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_A + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:62782.7-62782.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 24 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:63927$3541 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:63927$3541_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:63928.19-63941.4" + cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 + connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + connect \SHIFT_ROT_dec30_inv_a \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + connect \opcode_in \SHIFT_ROT_dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:63942.19-63955.4" + cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 + connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + connect \SHIFT_ROT_dec31_inv_a \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + connect \opcode_in \SHIFT_ROT_dec31_opcode_in + end + attribute \src "libresoc.v:62782.7-62782.20" + process $proc$libresoc.v:62782$3553 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:63956.3-63977.6" + process $proc$libresoc.v:63956$3542 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63957.5-63957.29" + switch \initial + attribute \src "libresoc.v:63957.9-63957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] + end + attribute \src "libresoc.v:63978.3-63999.6" + process $proc$libresoc.v:63978$3543 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:63979.5-63979.29" + switch \initial + attribute \src "libresoc.v:63979.9-63979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] + end + attribute \src "libresoc.v:64000.3-64021.6" + process $proc$libresoc.v:64000$3544 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:64001.5-64001.29" + switch \initial + attribute \src "libresoc.v:64001.9-64001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] + end + attribute \src "libresoc.v:64022.3-64043.6" + process $proc$libresoc.v:64022$3545 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:64023.5-64023.29" + switch \initial + attribute \src "libresoc.v:64023.9-64023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] + end + attribute \src "libresoc.v:64044.3-64065.6" + process $proc$libresoc.v:64044$3546 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:64045.5-64045.29" + switch \initial + attribute \src "libresoc.v:64045.9-64045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 + case + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000000000 + end + sync always + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] + end + attribute \src "libresoc.v:64066.3-64087.6" + process $proc$libresoc.v:64066$3547 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:64067.5-64067.29" + switch \initial + attribute \src "libresoc.v:64067.9-64067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + case + assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] + end + attribute \src "libresoc.v:64088.3-64109.6" + process $proc$libresoc.v:64088$3548 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:64089.5-64089.29" + switch \initial + attribute \src "libresoc.v:64089.9-64089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] + end + attribute \src "libresoc.v:64110.3-64131.6" + process $proc$libresoc.v:64110$3549 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:64111.5-64111.29" + switch \initial + attribute \src "libresoc.v:64111.9-64111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] + end + attribute \src "libresoc.v:64132.3-64153.6" + process $proc$libresoc.v:64132$3550 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:64133.5-64133.29" + switch \initial + attribute \src "libresoc.v:64133.9-64133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] + end + attribute \src "libresoc.v:64154.3-64175.6" + process $proc$libresoc.v:64154$3551 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:64155.5-64155.29" + switch \initial + attribute \src "libresoc.v:64155.9-64155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] + end + attribute \src "libresoc.v:64176.3-64197.6" + process $proc$libresoc.v:64176$3552 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:64177.5-64177.29" + switch \initial + attribute \src "libresoc.v:64177.9-64177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] + end + connect \$1 $ternary$libresoc.v:63927$3541_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SHIFT_ROT_SPR \opcode_in [20:11] + connect \SHIFT_ROT_MB \opcode_in [10:6] + connect \SHIFT_ROT_ME \opcode_in [5:1] + connect \SHIFT_ROT_SH \opcode_in [15:11] + connect \SHIFT_ROT_BC \opcode_in [10:6] + connect \SHIFT_ROT_TO \opcode_in [25:21] + connect \SHIFT_ROT_DS \opcode_in [15:2] + connect \SHIFT_ROT_D \opcode_in [15:0] + connect \SHIFT_ROT_BH \opcode_in [12:11] + connect \SHIFT_ROT_BI \opcode_in [20:16] + connect \SHIFT_ROT_BO \opcode_in [25:21] + connect \SHIFT_ROT_FXM \opcode_in [19:12] + connect \SHIFT_ROT_BT \opcode_in [25:21] + connect \SHIFT_ROT_BA \opcode_in [20:16] + connect \SHIFT_ROT_BB \opcode_in [15:11] + connect \SHIFT_ROT_CR \opcode_in [10:1] + connect \SHIFT_ROT_BF \opcode_in [25:23] + connect \SHIFT_ROT_BD \opcode_in [15:2] + connect \SHIFT_ROT_OE \opcode_in [10] + connect \SHIFT_ROT_Rc \opcode_in [0] + connect \SHIFT_ROT_AA \opcode_in [1] + connect \SHIFT_ROT_LK \opcode_in [0] + connect \SHIFT_ROT_LI \opcode_in [25:2] + connect \SHIFT_ROT_ME32 \opcode_in [5:1] + connect \SHIFT_ROT_MB32 \opcode_in [10:6] + connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SHIFT_ROT_SH32 \opcode_in [15:11] + connect \SHIFT_ROT_L \opcode_in [21] + connect \SHIFT_ROT_UI \opcode_in [15:0] + connect \SHIFT_ROT_SI \opcode_in [15:0] + connect \SHIFT_ROT_RB \opcode_in [15:11] + connect \SHIFT_ROT_RA \opcode_in [20:16] + connect \SHIFT_ROT_RT \opcode_in [25:21] + connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \SHIFT_ROT_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \SHIFT_ROT_dec31_opcode_in \opcode_in + connect \SHIFT_ROT_dec30_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:64539.1-67048.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" +attribute \generator "nMigen" +module \dec$166 + attribute \src "libresoc.v:66130.3-66187.6" + wire $0\LDST_br[0:0] + attribute \src "libresoc.v:66594.3-66651.6" + wire width 3 $0\LDST_cr_in[2:0] + attribute \src "libresoc.v:66652.3-66709.6" + wire width 3 $0\LDST_cr_out[2:0] + attribute \src "libresoc.v:66362.3-66419.6" + wire width 14 $0\LDST_function_unit[13:0] + attribute \src "libresoc.v:66478.3-66535.6" + wire width 3 $0\LDST_in1_sel[2:0] + attribute \src "libresoc.v:66536.3-66593.6" + wire width 4 $0\LDST_in2_sel[3:0] + attribute \src "libresoc.v:66420.3-66477.6" + wire width 7 $0\LDST_internal_op[6:0] + attribute \src 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attribute \src "libresoc.v:66420.3-66477.6" + wire width 7 $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:66246.3-66303.6" + wire $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:65956.3-66013.6" + wire width 4 $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:66072.3-66129.6" + wire width 2 $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:66304.3-66361.6" + wire $1\LDST_sgn[0:0] + attribute \src "libresoc.v:66188.3-66245.6" + wire $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:66014.3-66071.6" + wire width 2 $1\LDST_upd[1:0] + attribute \src "libresoc.v:65907.17-65907.211" + wire width 32 $ternary$libresoc.v:65907$3554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \LDST_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 24 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 3 \LDST_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 2 \LDST_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \LDST_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \LDST_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 output 25 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \LDST_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 output 21 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \LDST_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 23 \LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \LDST_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 16 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 22 \LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 19 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 17 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \LDST_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 output 18 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 13 \LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 9 \LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec31_LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LDST_dec31_LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \LDST_dec31_LDST_dec31_cr_out + attribute \enum_base_type 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attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LDST_dec62_LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec62_LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \LDST_dec62_LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \LDST_dec62_LDST_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \LDST_dec62_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 6 \LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 4 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 11 \LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 10 \LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 3 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 12 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 14 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 output 20 \LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 15 \LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dm + attribute \src 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wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "libresoc.v:64540.7-64540.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 26 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:65907$3554 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:65907$3554_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:65908.14-65923.4" + cell \LDST_dec31 \LDST_dec31 + connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br + connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in + connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out + connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit + connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel + connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel + connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op + connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b + connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len + connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel + connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn + connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext + connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd + connect \opcode_in \LDST_dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:65924.14-65939.4" + cell \LDST_dec58 \LDST_dec58 + connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br + connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in + connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out + connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit + connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel + connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel + connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op + connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b + connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len + connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel + connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn + connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext + connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd + connect \opcode_in \LDST_dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:65940.14-65955.4" + cell \LDST_dec62 \LDST_dec62 + connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br + connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in + connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out + connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit + connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel + connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel + connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op + connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b + connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len + connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel + connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn + connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext + connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd + connect \opcode_in \LDST_dec62_opcode_in + end + attribute \src "libresoc.v:64540.7-64540.20" + process $proc$libresoc.v:64540$3568 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:65956.3-66013.6" + process $proc$libresoc.v:65956$3555 + assign { } { } + assign { } { } + assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:65957.5-65957.29" + switch \initial + attribute \src "libresoc.v:65957.9-65957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + case + assign $1\LDST_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_ldst_len $0\LDST_ldst_len[3:0] + end + attribute \src "libresoc.v:66014.3-66071.6" + process $proc$libresoc.v:66014$3556 + assign { } { } + assign { } { } + assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] + attribute \src "libresoc.v:66015.5-66015.29" + switch \initial + attribute \src "libresoc.v:66015.9-66015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + case + assign $1\LDST_upd[1:0] 2'00 + end + sync always + update \LDST_upd $0\LDST_upd[1:0] + end + attribute \src "libresoc.v:66072.3-66129.6" + process $proc$libresoc.v:66072$3557 + assign { } { } + assign { } { } + assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:66073.5-66073.29" + switch \initial + attribute \src "libresoc.v:66073.9-66073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + case + assign $1\LDST_rc_sel[1:0] 2'00 + end + sync always + update \LDST_rc_sel $0\LDST_rc_sel[1:0] + end + attribute \src "libresoc.v:66130.3-66187.6" + process $proc$libresoc.v:66130$3558 + assign { } { } + assign { } { } + assign $0\LDST_br[0:0] $1\LDST_br[0:0] + attribute \src "libresoc.v:66131.5-66131.29" + switch \initial + attribute \src "libresoc.v:66131.9-66131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + case + assign $1\LDST_br[0:0] 1'0 + end + sync always + update \LDST_br $0\LDST_br[0:0] + end + attribute \src "libresoc.v:66188.3-66245.6" + process $proc$libresoc.v:66188$3559 + assign { } { } + assign { } { } + assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:66189.5-66189.29" + switch \initial + attribute \src "libresoc.v:66189.9-66189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + case + assign $1\LDST_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] + end + attribute \src "libresoc.v:66246.3-66303.6" + process $proc$libresoc.v:66246$3560 + assign { } { } + assign { } { } + assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:66247.5-66247.29" + switch \initial + attribute \src "libresoc.v:66247.9-66247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + case + assign $1\LDST_is_32b[0:0] 1'0 + end + sync always + update \LDST_is_32b $0\LDST_is_32b[0:0] + end + attribute \src "libresoc.v:66304.3-66361.6" + process $proc$libresoc.v:66304$3561 + assign { } { } + assign { } { } + assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] + attribute \src "libresoc.v:66305.5-66305.29" + switch \initial + attribute \src "libresoc.v:66305.9-66305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + case + assign $1\LDST_sgn[0:0] 1'0 + end + sync always + update \LDST_sgn $0\LDST_sgn[0:0] + end + attribute \src "libresoc.v:66362.3-66419.6" + process $proc$libresoc.v:66362$3562 + assign { } { } + assign { } { } + assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] + attribute \src "libresoc.v:66363.5-66363.29" + switch \initial + attribute \src "libresoc.v:66363.9-66363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_function_unit[13:0] \LDST_dec31_LDST_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_function_unit[13:0] \LDST_dec58_LDST_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_function_unit[13:0] \LDST_dec62_LDST_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_function_unit[13:0] 14'00000000000100 + case + assign $1\LDST_function_unit[13:0] 14'00000000000000 + end + sync always + update \LDST_function_unit $0\LDST_function_unit[13:0] + end + attribute \src "libresoc.v:66420.3-66477.6" + process $proc$libresoc.v:66420$3563 + assign { } { } + assign { } { } + assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:66421.5-66421.29" + switch \initial + attribute \src "libresoc.v:66421.9-66421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + case + assign $1\LDST_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_internal_op $0\LDST_internal_op[6:0] + end + attribute \src "libresoc.v:66478.3-66535.6" + process $proc$libresoc.v:66478$3564 + assign { } { } + assign { } { } + assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:66479.5-66479.29" + switch \initial + attribute \src "libresoc.v:66479.9-66479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + case + assign $1\LDST_in1_sel[2:0] 3'000 + end + sync always + update \LDST_in1_sel $0\LDST_in1_sel[2:0] + end + attribute \src "libresoc.v:66536.3-66593.6" + process $proc$libresoc.v:66536$3565 + assign { } { } + assign { } { } + assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:66537.5-66537.29" + switch \initial + attribute \src "libresoc.v:66537.9-66537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + case + assign $1\LDST_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_in2_sel $0\LDST_in2_sel[3:0] + end + attribute \src "libresoc.v:66594.3-66651.6" + process $proc$libresoc.v:66594$3566 + assign { } { } + assign { } { } + assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:66595.5-66595.29" + switch \initial + attribute \src "libresoc.v:66595.9-66595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + case + assign $1\LDST_cr_in[2:0] 3'000 + end + sync always + update \LDST_cr_in $0\LDST_cr_in[2:0] + end + attribute \src "libresoc.v:66652.3-66709.6" + process $proc$libresoc.v:66652$3567 + assign { } { } + assign { } { } + assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:66653.5-66653.29" + switch \initial + attribute \src "libresoc.v:66653.9-66653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + case + assign $1\LDST_cr_out[2:0] 3'000 + end + sync always + update \LDST_cr_out $0\LDST_cr_out[2:0] + end + connect \$1 $ternary$libresoc.v:65907$3554_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LDST_SPR \opcode_in [20:11] + connect \LDST_MB \opcode_in [10:6] + connect \LDST_ME \opcode_in [5:1] + connect \LDST_SH \opcode_in [15:11] + connect \LDST_BC \opcode_in [10:6] + connect \LDST_TO \opcode_in [25:21] + connect \LDST_DS \opcode_in [15:2] + connect \LDST_D \opcode_in [15:0] + connect \LDST_BH \opcode_in [12:11] + connect \LDST_BI \opcode_in [20:16] + connect \LDST_BO \opcode_in [25:21] + connect \LDST_FXM \opcode_in [19:12] + connect \LDST_BT \opcode_in [25:21] + connect \LDST_BA \opcode_in [20:16] + connect \LDST_BB \opcode_in [15:11] + connect \LDST_CR \opcode_in [10:1] + connect \LDST_BF \opcode_in [25:23] + connect \LDST_BD \opcode_in [15:2] + connect \LDST_OE \opcode_in [10] + connect \LDST_Rc \opcode_in [0] + connect \LDST_AA \opcode_in [1] + connect \LDST_LK \opcode_in [0] + connect \LDST_LI \opcode_in [25:2] + connect \LDST_ME32 \opcode_in [5:1] + connect \LDST_MB32 \opcode_in [10:6] + connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LDST_SH32 \opcode_in [15:11] + connect \LDST_L \opcode_in [21] + connect \LDST_UI \opcode_in [15:0] + connect \LDST_SI \opcode_in [15:0] + connect \LDST_RB \opcode_in [15:11] + connect \LDST_RA \opcode_in [20:16] + connect \LDST_RT \opcode_in [25:21] + connect \LDST_RS \opcode_in [25:21] + connect \LDST_PO \opcode_in [31:26] + connect \opcode_in \$1 + connect \LDST_dec62_opcode_in \opcode_in + connect \LDST_dec58_opcode_in \opcode_in + connect \LDST_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:67052.1-75269.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" +attribute \generator "nMigen" +module \dec$171 + attribute \src "libresoc.v:70432.3-70576.6" + wire width 2 $0\SV_Etype[1:0] + attribute \src "libresoc.v:70577.3-70721.6" + wire width 2 $0\SV_Ptype[1:0] + attribute \src "libresoc.v:70290.3-70431.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:73622.3-73766.6" + wire $0\br[0:0] + attribute \src "libresoc.v:71302.3-71446.6" + wire width 3 $0\cr_in[2:0] + attribute \src "libresoc.v:71447.3-71591.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:73042.3-73186.6" + wire width 2 $0\cry_in[1:0] + attribute \src "libresoc.v:73477.3-73621.6" + wire $0\cry_out[0:0] + attribute \src "libresoc.v:70145.3-70289.6" + wire width 5 $0\form[4:0] + attribute \src "libresoc.v:74637.3-74781.6" + wire width 14 $0\function_unit[13:0] + attribute \src "libresoc.v:70722.3-70866.6" + wire width 3 $0\in1_sel[2:0] + attribute \src "libresoc.v:70867.3-71011.6" + wire width 4 $0\in2_sel[3:0] + attribute \src "libresoc.v:71012.3-71156.6" + wire width 2 $0\in3_sel[1:0] + attribute \src "libresoc.v:67053.7-67053.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:74782.3-74926.6" + wire width 7 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 24 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 21 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 22 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 19 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 output 20 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire output 23 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 output 5 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \SVL_vs + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \X_TH + attribute \src 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wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 17 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \cry_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec19_dec19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec19_dec19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec19_dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec19_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec19_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute 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\enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 18 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:69928$3569 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:69928$3569_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69929.9-69964.4" + cell \dec19 \dec19 + connect \dec19_SV_Etype \dec19_dec19_SV_Etype + connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_sv_cr_in \dec19_dec19_sv_cr_in + connect \dec19_sv_cr_out \dec19_dec19_sv_cr_out + connect \dec19_sv_in1 \dec19_dec19_sv_in1 + connect \dec19_sv_in2 \dec19_dec19_sv_in2 + connect \dec19_sv_in3 \dec19_dec19_sv_in3 + connect \dec19_sv_out \dec19_dec19_sv_out + connect \dec19_sv_out2 \dec19_dec19_sv_out2 + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69965.9-70000.4" + cell \dec22 \dec22 + connect \dec22_SV_Etype \dec22_dec22_SV_Etype + connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype + connect \dec22_asmcode \dec22_dec22_asmcode + connect \dec22_br \dec22_dec22_br + connect \dec22_cr_in \dec22_dec22_cr_in + connect \dec22_cr_out \dec22_dec22_cr_out + connect \dec22_cry_in \dec22_dec22_cry_in + connect \dec22_cry_out \dec22_dec22_cry_out + connect \dec22_form \dec22_dec22_form + connect \dec22_function_unit \dec22_dec22_function_unit + connect \dec22_in1_sel \dec22_dec22_in1_sel + connect \dec22_in2_sel \dec22_dec22_in2_sel + connect \dec22_in3_sel \dec22_dec22_in3_sel + connect \dec22_internal_op \dec22_dec22_internal_op + connect \dec22_inv_a \dec22_dec22_inv_a + connect \dec22_inv_out \dec22_dec22_inv_out + connect \dec22_is_32b \dec22_dec22_is_32b + connect \dec22_ldst_len \dec22_dec22_ldst_len + connect \dec22_lk \dec22_dec22_lk + connect \dec22_out_sel \dec22_dec22_out_sel + connect \dec22_rc_sel \dec22_dec22_rc_sel + connect \dec22_rsrv \dec22_dec22_rsrv + connect \dec22_sgl_pipe \dec22_dec22_sgl_pipe + connect \dec22_sgn \dec22_dec22_sgn + connect \dec22_sgn_ext \dec22_dec22_sgn_ext + connect \dec22_sv_cr_in \dec22_dec22_sv_cr_in + connect \dec22_sv_cr_out \dec22_dec22_sv_cr_out + connect \dec22_sv_in1 \dec22_dec22_sv_in1 + connect \dec22_sv_in2 \dec22_dec22_sv_in2 + connect \dec22_sv_in3 \dec22_dec22_sv_in3 + connect \dec22_sv_out \dec22_dec22_sv_out + connect \dec22_sv_out2 \dec22_dec22_sv_out2 + connect \dec22_upd \dec22_dec22_upd + connect \opcode_in \dec22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:70001.9-70036.4" + cell \dec30 \dec30 + connect \dec30_SV_Etype \dec30_dec30_SV_Etype + connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_sv_cr_in \dec30_dec30_sv_cr_in + connect \dec30_sv_cr_out \dec30_dec30_sv_cr_out + connect \dec30_sv_in1 \dec30_dec30_sv_in1 + connect \dec30_sv_in2 \dec30_dec30_sv_in2 + connect \dec30_sv_in3 \dec30_dec30_sv_in3 + connect \dec30_sv_out \dec30_dec30_sv_out + connect \dec30_sv_out2 \dec30_dec30_sv_out2 + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:70037.9-70072.4" + cell \dec31 \dec31 + connect \dec31_SV_Etype \dec31_dec31_SV_Etype + connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_sv_cr_in \dec31_dec31_sv_cr_in + connect \dec31_sv_cr_out \dec31_dec31_sv_cr_out + connect \dec31_sv_in1 \dec31_dec31_sv_in1 + connect \dec31_sv_in2 \dec31_dec31_sv_in2 + connect \dec31_sv_in3 \dec31_dec31_sv_in3 + connect \dec31_sv_out \dec31_dec31_sv_out + connect \dec31_sv_out2 \dec31_dec31_sv_out2 + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:70073.9-70108.4" + cell \dec58 \dec58 + connect \dec58_SV_Etype \dec58_dec58_SV_Etype + connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_sv_cr_in \dec58_dec58_sv_cr_in + connect \dec58_sv_cr_out \dec58_dec58_sv_cr_out + connect \dec58_sv_in1 \dec58_dec58_sv_in1 + connect \dec58_sv_in2 \dec58_dec58_sv_in2 + connect \dec58_sv_in3 \dec58_dec58_sv_in3 + connect \dec58_sv_out \dec58_dec58_sv_out + connect \dec58_sv_out2 \dec58_dec58_sv_out2 + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:70109.9-70144.4" + cell \dec62 \dec62 + connect \dec62_SV_Etype \dec62_dec62_SV_Etype + connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_sv_cr_in \dec62_dec62_sv_cr_in + connect \dec62_sv_cr_out \dec62_dec62_sv_cr_out + connect \dec62_sv_in1 \dec62_dec62_sv_in1 + connect \dec62_sv_in2 \dec62_dec62_sv_in2 + connect \dec62_sv_in3 \dec62_dec62_sv_in3 + connect \dec62_sv_out \dec62_dec62_sv_out + connect \dec62_sv_out2 \dec62_dec62_sv_out2 + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:67053.7-67053.20" + process $proc$libresoc.v:67053$3603 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:70145.3-70289.6" + process $proc$libresoc.v:70145$3570 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:70146.5-70146.29" + switch \initial + attribute \src "libresoc.v:70146.9-70146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\form[4:0] \dec22_dec22_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + attribute \src "libresoc.v:70290.3-70431.6" + process $proc$libresoc.v:70290$3571 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:70291.5-70291.29" + switch \initial + attribute \src "libresoc.v:70291.9-70291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\asmcode[7:0] \dec22_dec22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010011 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011101 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "libresoc.v:70432.3-70576.6" + process $proc$libresoc.v:70432$3572 + assign { } { } + assign { } { } + assign { } { } + assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] + attribute \src "libresoc.v:70433.5-70433.29" + switch \initial + attribute \src "libresoc.v:70433.9-70433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\SV_Etype[1:0] \dec19_dec19_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SV_Etype[1:0] \dec30_dec30_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SV_Etype[1:0] \dec31_dec31_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\SV_Etype[1:0] \dec58_dec58_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\SV_Etype[1:0] \dec62_dec62_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\SV_Etype[1:0] \dec22_dec22_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + case + assign $1\SV_Etype[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + case + assign $2\SV_Etype[1:0] $1\SV_Etype[1:0] + end + sync always + update \SV_Etype $0\SV_Etype[1:0] + end + attribute \src "libresoc.v:70577.3-70721.6" + process $proc$libresoc.v:70577$3573 + assign { } { } + assign { } { } + assign { } { } + assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] + attribute \src "libresoc.v:70578.5-70578.29" + switch \initial + attribute \src "libresoc.v:70578.9-70578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\SV_Ptype[1:0] \dec19_dec19_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec30_dec30_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SV_Ptype[1:0] \dec31_dec31_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\SV_Ptype[1:0] \dec58_dec58_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec62_dec62_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec22_dec22_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + case + assign $1\SV_Ptype[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + case + assign $2\SV_Ptype[1:0] $1\SV_Ptype[1:0] + end + sync always + update \SV_Ptype $0\SV_Ptype[1:0] + end + attribute \src "libresoc.v:70722.3-70866.6" + process $proc$libresoc.v:70722$3574 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:70723.5-70723.29" + switch \initial + attribute \src "libresoc.v:70723.9-70723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in1_sel[2:0] \dec22_dec22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "libresoc.v:70867.3-71011.6" + process $proc$libresoc.v:70867$3575 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:70868.5-70868.29" + switch \initial + attribute \src "libresoc.v:70868.9-70868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in2_sel[3:0] \dec22_dec22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "libresoc.v:71012.3-71156.6" + process $proc$libresoc.v:71012$3576 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:71013.5-71013.29" + switch \initial + attribute \src "libresoc.v:71013.9-71013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in3_sel[1:0] \dec22_dec22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "libresoc.v:71157.3-71301.6" + process $proc$libresoc.v:71157$3577 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[2:0] $2\out_sel[2:0] + attribute \src "libresoc.v:71158.5-71158.29" + switch \initial + attribute \src "libresoc.v:71158.9-71158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[2:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[2:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[2:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[2:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[2:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\out_sel[2:0] \dec22_dec22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[2:0] 3'010 + case + assign $1\out_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[2:0] 3'001 + case + assign $2\out_sel[2:0] $1\out_sel[2:0] + end + sync always + update \out_sel $0\out_sel[2:0] + end + attribute \src "libresoc.v:71302.3-71446.6" + process $proc$libresoc.v:71302$3578 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:71303.5-71303.29" + switch \initial + attribute \src "libresoc.v:71303.9-71303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cr_in[2:0] \dec22_dec22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "libresoc.v:71447.3-71591.6" + process $proc$libresoc.v:71447$3579 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:71448.5-71448.29" + switch \initial + attribute \src "libresoc.v:71448.9-71448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cr_out[2:0] \dec22_dec22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "libresoc.v:71592.3-71736.6" + process $proc$libresoc.v:71592$3580 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in1[2:0] $2\sv_in1[2:0] + attribute \src "libresoc.v:71593.5-71593.29" + switch \initial + attribute \src "libresoc.v:71593.9-71593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in1[2:0] \dec19_dec19_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in1[2:0] \dec30_dec30_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in1[2:0] \dec31_dec31_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in1[2:0] \dec58_dec58_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in1[2:0] \dec62_dec62_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in1[2:0] \dec22_dec22_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + case + assign $1\sv_in1[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in1[2:0] 3'000 + case + assign $2\sv_in1[2:0] $1\sv_in1[2:0] + end + sync always + update \sv_in1 $0\sv_in1[2:0] + end + attribute \src "libresoc.v:71737.3-71881.6" + process $proc$libresoc.v:71737$3581 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in2[2:0] $2\sv_in2[2:0] + attribute \src "libresoc.v:71738.5-71738.29" + switch \initial + attribute \src "libresoc.v:71738.9-71738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in2[2:0] \dec19_dec19_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in2[2:0] \dec30_dec30_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in2[2:0] \dec31_dec31_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in2[2:0] \dec58_dec58_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in2[2:0] \dec62_dec62_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in2[2:0] \dec22_dec22_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + case + assign $1\sv_in2[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in2[2:0] 3'000 + case + assign $2\sv_in2[2:0] $1\sv_in2[2:0] + end + sync always + update \sv_in2 $0\sv_in2[2:0] + end + attribute \src "libresoc.v:71882.3-72026.6" + process $proc$libresoc.v:71882$3582 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in3[2:0] $2\sv_in3[2:0] + attribute \src "libresoc.v:71883.5-71883.29" + switch \initial + attribute \src "libresoc.v:71883.9-71883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in3[2:0] \dec19_dec19_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in3[2:0] \dec30_dec30_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in3[2:0] \dec31_dec31_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in3[2:0] \dec58_dec58_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in3[2:0] \dec62_dec62_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in3[2:0] \dec22_dec22_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + case + assign $1\sv_in3[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in3[2:0] 3'000 + case + assign $2\sv_in3[2:0] $1\sv_in3[2:0] + end + sync always + update \sv_in3 $0\sv_in3[2:0] + end + attribute \src "libresoc.v:72027.3-72171.6" + process $proc$libresoc.v:72027$3583 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_out[2:0] $2\sv_out[2:0] + attribute \src "libresoc.v:72028.5-72028.29" + switch \initial + attribute \src "libresoc.v:72028.9-72028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_out[2:0] \dec19_dec19_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_out[2:0] \dec30_dec30_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_out[2:0] \dec31_dec31_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_out[2:0] \dec58_dec58_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_out[2:0] \dec62_dec62_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_out[2:0] \dec22_dec22_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + case + assign $1\sv_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_out[2:0] 3'000 + case + assign $2\sv_out[2:0] $1\sv_out[2:0] + end + sync always + update \sv_out $0\sv_out[2:0] + end + attribute \src "libresoc.v:72172.3-72316.6" + process $proc$libresoc.v:72172$3584 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_out2[2:0] $2\sv_out2[2:0] + attribute \src "libresoc.v:72173.5-72173.29" + switch \initial + attribute \src "libresoc.v:72173.9-72173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_out2[2:0] \dec19_dec19_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_out2[2:0] \dec30_dec30_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_out2[2:0] \dec31_dec31_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_out2[2:0] \dec58_dec58_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_out2[2:0] \dec62_dec62_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_out2[2:0] \dec22_dec22_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + case + assign $1\sv_out2[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_out2[2:0] 3'000 + case + assign $2\sv_out2[2:0] $1\sv_out2[2:0] + end + sync always + update \sv_out2 $0\sv_out2[2:0] + end + attribute \src "libresoc.v:72317.3-72461.6" + process $proc$libresoc.v:72317$3585 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] + attribute \src "libresoc.v:72318.5-72318.29" + switch \initial + attribute \src "libresoc.v:72318.9-72318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_cr_in[2:0] \dec19_dec19_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec30_dec30_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_cr_in[2:0] \dec31_dec31_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_cr_in[2:0] \dec58_dec58_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec62_dec62_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec22_dec22_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + case + assign $1\sv_cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + case + assign $2\sv_cr_in[2:0] $1\sv_cr_in[2:0] + end + sync always + update \sv_cr_in $0\sv_cr_in[2:0] + end + attribute \src "libresoc.v:72462.3-72606.6" + process $proc$libresoc.v:72462$3586 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] + attribute \src "libresoc.v:72463.5-72463.29" + switch \initial + attribute \src "libresoc.v:72463.9-72463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_cr_out[2:0] \dec19_dec19_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec30_dec30_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_cr_out[2:0] \dec31_dec31_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_cr_out[2:0] \dec58_dec58_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec62_dec62_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec22_dec22_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + case + assign $1\sv_cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + case + assign $2\sv_cr_out[2:0] $1\sv_cr_out[2:0] + end + sync always + update \sv_cr_out $0\sv_cr_out[2:0] + end + attribute \src "libresoc.v:72607.3-72751.6" + process $proc$libresoc.v:72607$3587 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:72608.5-72608.29" + switch \initial + attribute \src "libresoc.v:72608.9-72608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\ldst_len[3:0] \dec22_dec22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:72752.3-72896.6" + process $proc$libresoc.v:72752$3588 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:72753.5-72753.29" + switch \initial + attribute \src "libresoc.v:72753.9-72753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\upd[1:0] \dec22_dec22_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "libresoc.v:72897.3-73041.6" + process $proc$libresoc.v:72897$3589 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:72898.5-72898.29" + switch \initial + attribute \src "libresoc.v:72898.9-72898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\rc_sel[1:0] \dec22_dec22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "libresoc.v:73042.3-73186.6" + process $proc$libresoc.v:73042$3590 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:73043.5-73043.29" + switch \initial + attribute \src "libresoc.v:73043.9-73043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cry_in[1:0] \dec22_dec22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "libresoc.v:73187.3-73331.6" + process $proc$libresoc.v:73187$3591 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:73188.5-73188.29" + switch \initial + attribute \src "libresoc.v:73188.9-73188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\inv_a[0:0] \dec22_dec22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "libresoc.v:73332.3-73476.6" + process $proc$libresoc.v:73332$3592 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:73333.5-73333.29" + switch \initial + attribute \src "libresoc.v:73333.9-73333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\inv_out[0:0] \dec22_dec22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "libresoc.v:73477.3-73621.6" + process $proc$libresoc.v:73477$3593 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:73478.5-73478.29" + switch \initial + attribute \src "libresoc.v:73478.9-73478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cry_out[0:0] \dec22_dec22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "libresoc.v:73622.3-73766.6" + process $proc$libresoc.v:73622$3594 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:73623.5-73623.29" + switch \initial + attribute \src "libresoc.v:73623.9-73623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\br[0:0] \dec22_dec22_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "libresoc.v:73767.3-73911.6" + process $proc$libresoc.v:73767$3595 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:73768.5-73768.29" + switch \initial + attribute \src "libresoc.v:73768.9-73768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgn_ext[0:0] \dec22_dec22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "libresoc.v:73912.3-74056.6" + process $proc$libresoc.v:73912$3596 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:73913.5-73913.29" + switch \initial + attribute \src "libresoc.v:73913.9-73913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\rsrv[0:0] \dec22_dec22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "libresoc.v:74057.3-74201.6" + process $proc$libresoc.v:74057$3597 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:74058.5-74058.29" + switch \initial + attribute \src "libresoc.v:74058.9-74058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\is_32b[0:0] \dec22_dec22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "libresoc.v:74202.3-74346.6" + process $proc$libresoc.v:74202$3598 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:74203.5-74203.29" + switch \initial + attribute \src "libresoc.v:74203.9-74203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgn[0:0] \dec22_dec22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "libresoc.v:74347.3-74491.6" + process $proc$libresoc.v:74347$3599 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:74348.5-74348.29" + switch \initial + attribute \src "libresoc.v:74348.9-74348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\lk[0:0] \dec22_dec22_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "libresoc.v:74492.3-74636.6" + process $proc$libresoc.v:74492$3600 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:74493.5-74493.29" + switch \initial + attribute \src "libresoc.v:74493.9-74493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec22_dec22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "libresoc.v:74637.3-74781.6" + process $proc$libresoc.v:74637$3601 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[13:0] $2\function_unit[13:0] + attribute \src "libresoc.v:74638.5-74638.29" + switch \initial + attribute \src "libresoc.v:74638.9-74638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[13:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[13:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[13:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[13:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[13:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\function_unit[13:0] \dec22_dec22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[13:0] 14'00000000010000 + case + assign $1\function_unit[13:0] 14'00000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[13:0] 14'00000000000000 + case + assign $2\function_unit[13:0] $1\function_unit[13:0] + end + sync always + update \function_unit $0\function_unit[13:0] + end + attribute \src "libresoc.v:74782.3-74926.6" + process $proc$libresoc.v:74782$3602 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:74783.5-74783.29" + switch \initial + attribute \src "libresoc.v:74783.9-74783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\internal_op[6:0] \dec22_dec22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + connect \$2 $ternary$libresoc.v:69928$3569_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:8] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \PO \opcode_in [31:26] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec22_opcode_in \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:75273.1-77339.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "libresoc.v:77026.3-77077.6" + wire width 2 $0\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:77078.3-77129.6" + wire width 2 $0\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:76402.3-76453.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src 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wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:76818.3-76869.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:76142.3-76193.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:76922.3-76973.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:77286.3-77337.6" + wire width 3 $0\dec19_out_sel[2:0] + attribute \src "libresoc.v:76298.3-76349.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:76714.3-76765.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:76974.3-77025.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76870.3-76921.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:76662.3-76713.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:76038.3-76089.6" + wire width 3 $0\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:76090.3-76141.6" + wire width 3 $0\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75778.3-75829.6" + wire width 3 $0\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75830.3-75881.6" + wire width 3 $0\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75882.3-75933.6" + wire width 3 $0\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75986.3-76037.6" + wire width 3 $0\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75934.3-75985.6" + wire width 3 $0\dec19_sv_out[2:0] + attribute \src "libresoc.v:76246.3-76297.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:75274.7-75274.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:77026.3-77077.6" + wire width 2 $1\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:77078.3-77129.6" + wire width 2 $1\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:76402.3-76453.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:76610.3-76661.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:75674.3-75725.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:75726.3-75777.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:76350.3-76401.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:76558.3-76609.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:76766.3-76817.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:75622.3-75673.6" + wire width 14 $1\dec19_function_unit[13:0] + attribute \src "libresoc.v:77130.3-77181.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:77182.3-77233.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:77234.3-77285.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:76194.3-76245.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:76454.3-76505.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:76506.3-76557.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:76818.3-76869.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:76142.3-76193.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:76922.3-76973.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:77286.3-77337.6" + wire width 3 $1\dec19_out_sel[2:0] + attribute \src "libresoc.v:76298.3-76349.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:76714.3-76765.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:76974.3-77025.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76870.3-76921.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:76662.3-76713.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:76038.3-76089.6" + wire width 3 $1\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:76090.3-76141.6" + wire width 3 $1\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75778.3-75829.6" + wire width 3 $1\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75830.3-75881.6" + wire width 3 $1\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75882.3-75933.6" + wire width 3 $1\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75986.3-76037.6" + wire width 3 $1\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75934.3-75985.6" + wire width 3 $1\dec19_sv_out[2:0] + attribute \src "libresoc.v:76246.3-76297.6" + wire width 2 $1\dec19_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec19_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec19_upd + attribute \src "libresoc.v:75274.7-75274.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \src "libresoc.v:75274.7-75274.20" + process $proc$libresoc.v:75274$3637 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:75622.3-75673.6" + process $proc$libresoc.v:75622$3604 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] + attribute \src "libresoc.v:75623.5-75623.29" + switch \initial + attribute \src "libresoc.v:75623.9-75623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[13:0] 14'00000010000000 + case + assign $1\dec19_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[13:0] + end + attribute \src "libresoc.v:75674.3-75725.6" + process $proc$libresoc.v:75674$3605 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:75675.5-75675.29" + switch \initial + attribute \src "libresoc.v:75675.9-75675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "libresoc.v:75726.3-75777.6" + process $proc$libresoc.v:75726$3606 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:75727.5-75727.29" + switch \initial + attribute \src "libresoc.v:75727.9-75727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + attribute \src "libresoc.v:75778.3-75829.6" + process $proc$libresoc.v:75778$3607 + assign { } { } + assign { } { } + assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75779.5-75779.29" + switch \initial + attribute \src "libresoc.v:75779.9-75779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + case + assign $1\dec19_sv_in1[2:0] 3'000 + end + sync always + update \dec19_sv_in1 $0\dec19_sv_in1[2:0] + end + attribute \src "libresoc.v:75830.3-75881.6" + process $proc$libresoc.v:75830$3608 + assign { } { } + assign { } { } + assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75831.5-75831.29" + switch \initial + attribute \src "libresoc.v:75831.9-75831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + case + assign $1\dec19_sv_in2[2:0] 3'000 + end + sync always + update \dec19_sv_in2 $0\dec19_sv_in2[2:0] + end + attribute \src "libresoc.v:75882.3-75933.6" + process $proc$libresoc.v:75882$3609 + assign { } { } + assign { } { } + assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75883.5-75883.29" + switch \initial + attribute \src "libresoc.v:75883.9-75883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + case + assign $1\dec19_sv_in3[2:0] 3'000 + end + sync always + update \dec19_sv_in3 $0\dec19_sv_in3[2:0] + end + attribute \src "libresoc.v:75934.3-75985.6" + process $proc$libresoc.v:75934$3610 + assign { } { } + assign { } { } + assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] + attribute \src "libresoc.v:75935.5-75935.29" + switch \initial + attribute \src "libresoc.v:75935.9-75935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + case + assign $1\dec19_sv_out[2:0] 3'000 + end + sync always + update \dec19_sv_out $0\dec19_sv_out[2:0] + end + attribute \src "libresoc.v:75986.3-76037.6" + process $proc$libresoc.v:75986$3611 + assign { } { } + assign { } { } + assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75987.5-75987.29" + switch \initial + attribute \src "libresoc.v:75987.9-75987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + case + assign $1\dec19_sv_out2[2:0] 3'000 + end + sync always + update \dec19_sv_out2 $0\dec19_sv_out2[2:0] + end + attribute \src "libresoc.v:76038.3-76089.6" + process $proc$libresoc.v:76038$3612 + assign { } { } + assign { } { } + assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:76039.5-76039.29" + switch \initial + attribute \src "libresoc.v:76039.9-76039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + case + assign $1\dec19_sv_cr_in[2:0] 3'000 + end + sync always + update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] + end + attribute \src "libresoc.v:76090.3-76141.6" + process $proc$libresoc.v:76090$3613 + assign { } { } + assign { } { } + assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:76091.5-76091.29" + switch \initial + attribute \src "libresoc.v:76091.9-76091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + case + assign $1\dec19_sv_cr_out[2:0] 3'000 + end + sync always + update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] + end + attribute \src "libresoc.v:76142.3-76193.6" + process $proc$libresoc.v:76142$3614 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:76143.5-76143.29" + switch \initial + attribute \src "libresoc.v:76143.9-76143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:76194.3-76245.6" + process $proc$libresoc.v:76194$3615 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:76195.5-76195.29" + switch \initial + attribute \src "libresoc.v:76195.9-76195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:76246.3-76297.6" + process $proc$libresoc.v:76246$3616 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:76247.5-76247.29" + switch \initial + attribute \src "libresoc.v:76247.9-76247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "libresoc.v:76298.3-76349.6" + process $proc$libresoc.v:76298$3617 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:76299.5-76299.29" + switch \initial + attribute \src "libresoc.v:76299.9-76299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:76350.3-76401.6" + process $proc$libresoc.v:76350$3618 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:76351.5-76351.29" + switch \initial + attribute \src "libresoc.v:76351.9-76351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:76402.3-76453.6" + process $proc$libresoc.v:76402$3619 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:76403.5-76403.29" + switch \initial + attribute \src "libresoc.v:76403.9-76403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:76454.3-76505.6" + process $proc$libresoc.v:76454$3620 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:76455.5-76455.29" + switch \initial + attribute \src "libresoc.v:76455.9-76455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:76506.3-76557.6" + process $proc$libresoc.v:76506$3621 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:76507.5-76507.29" + switch \initial + attribute \src "libresoc.v:76507.9-76507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:76558.3-76609.6" + process $proc$libresoc.v:76558$3622 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:76559.5-76559.29" + switch \initial + attribute \src "libresoc.v:76559.9-76559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:76610.3-76661.6" + process $proc$libresoc.v:76610$3623 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:76611.5-76611.29" + switch \initial + attribute \src "libresoc.v:76611.9-76611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:76662.3-76713.6" + process $proc$libresoc.v:76662$3624 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:76663.5-76663.29" + switch \initial + attribute \src "libresoc.v:76663.9-76663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:76714.3-76765.6" + process $proc$libresoc.v:76714$3625 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:76715.5-76715.29" + switch \initial + attribute \src "libresoc.v:76715.9-76715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "libresoc.v:76766.3-76817.6" + process $proc$libresoc.v:76766$3626 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:76767.5-76767.29" + switch \initial + attribute \src "libresoc.v:76767.9-76767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:76818.3-76869.6" + process $proc$libresoc.v:76818$3627 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:76819.5-76819.29" + switch \initial + attribute \src "libresoc.v:76819.9-76819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "libresoc.v:76870.3-76921.6" + process $proc$libresoc.v:76870$3628 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:76871.5-76871.29" + switch \initial + attribute \src "libresoc.v:76871.9-76871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "libresoc.v:76922.3-76973.6" + process $proc$libresoc.v:76922$3629 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:76923.5-76923.29" + switch \initial + attribute \src "libresoc.v:76923.9-76923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "libresoc.v:76974.3-77025.6" + process $proc$libresoc.v:76974$3630 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76975.5-76975.29" + switch \initial + attribute \src "libresoc.v:76975.9-76975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:77026.3-77077.6" + process $proc$libresoc.v:77026$3631 + assign { } { } + assign { } { } + assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:77027.5-77027.29" + switch \initial + attribute \src "libresoc.v:77027.9-77027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + case + assign $1\dec19_SV_Etype[1:0] 2'00 + end + sync always + update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] + end + attribute \src "libresoc.v:77078.3-77129.6" + process $proc$libresoc.v:77078$3632 + assign { } { } + assign { } { } + assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:77079.5-77079.29" + switch \initial + attribute \src "libresoc.v:77079.9-77079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + case + assign $1\dec19_SV_Ptype[1:0] 2'00 + end + sync always + update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] + end + attribute \src "libresoc.v:77130.3-77181.6" + process $proc$libresoc.v:77130$3633 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:77131.5-77131.29" + switch \initial + attribute \src "libresoc.v:77131.9-77131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:77182.3-77233.6" + process $proc$libresoc.v:77182$3634 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:77183.5-77183.29" + switch \initial + attribute \src "libresoc.v:77183.9-77183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:77234.3-77285.6" + process $proc$libresoc.v:77234$3635 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:77235.5-77235.29" + switch \initial + attribute \src "libresoc.v:77235.9-77235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "libresoc.v:77286.3-77337.6" + process $proc$libresoc.v:77286$3636 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] + attribute \src "libresoc.v:77287.5-77287.29" + switch \initial + attribute \src "libresoc.v:77287.9-77287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[2:0] 3'000 + case + assign $1\dec19_out_sel[2:0] 3'000 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:77343.1-79564.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\cr_in1[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\cr_in2$1[6:0]$3698 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\cr_in2[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_in2_ok$2[0:0]$3699 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\ea[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$3[0:0]$3701 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$4[0:0]$3702 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$5[0:0]$3703 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$6[0:0]$3704 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$7[0:0]$3705 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$8[0:0]$3706 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$9[0:0]$3707 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal[0:0]$3700 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 14 $0\fn_unit[13:0] + attribute \src "libresoc.v:77344.7-77344.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:79303.3-79326.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\reg1[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\reg2[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\reg3[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\rego[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:79229.3-79243.6" + wire width 14 $0\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:79254.3-79266.6" + wire width 7 $0\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:79244.3-79253.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:79293.3-79302.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:79267.3-79282.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:79283.3-79292.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $0\traptype[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\cr_in1[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\cr_in2$1[6:0]$3708 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\cr_in2[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_in2_ok$2[0:0]$3709 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\cr_out[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\ea[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$3[0:0]$3711 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$4[0:0]$3712 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$5[0:0]$3713 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$6[0:0]$3714 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$7[0:0]$3715 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$8[0:0]$3716 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$9[0:0]$3717 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal[0:0]$3710 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 14 $1\fn_unit[13:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:79303.3-79326.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\reg1[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\reg2[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\reg3[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\rego[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:79229.3-79243.6" + wire width 14 $1\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:79254.3-79266.6" + wire width 7 $1\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:79244.3-79253.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:79293.3-79302.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:79267.3-79282.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:79283.3-79292.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $1\traptype[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 64 $2\cia[63:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\cr_in1[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_in1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\cr_in2$1[6:0]$3718 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\cr_in2[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_in2_ok$2[0:0]$3719 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_in2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\cr_out[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_out_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $2\cr_rd[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_rd_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 8 $2\cr_wr[7:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_wr_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\ea[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\ea_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$3[0:0]$3721 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$4[0:0]$3722 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$5[0:0]$3723 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$6[0:0]$3724 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$7[0:0]$3725 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$8[0:0]$3726 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$9[0:0]$3727 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal[0:0]$3720 + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 14 $2\fn_unit[13:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 2 $2\input_carry[1:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 32 $2\insn[31:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\insn_type[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\is_32bit[0:0] + attribute \src "libresoc.v:79303.3-79326.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\oe_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\rc[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\rc_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\reg1[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\reg1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\reg2[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\reg2_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\reg3[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\reg3_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\rego[6:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\rego_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 10 $2\spr1[9:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\spr1_ok[0:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire width 10 $2\spro[9:0] + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\spro_ok[0:0] + attribute \src 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attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec_a_spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_a_spr_a_ok + attribute \src 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"CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215" + wire \dec_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec_o2_fast_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o2_fast_o2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + wire \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec_o2_reg_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o2_reg_o2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + wire width 3 \dec_o_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 50 \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 51 \exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 52 \exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 53 \exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 54 \exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 55 \exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 56 \exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 57 \exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1214" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 14 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217" + wire \illeg_ok + attribute \src "libresoc.v:77344.7-77344.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + wire width 32 \insn_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" + wire width 32 \insn_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194" + wire width 32 \insn_in$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + wire width 32 \insn_in$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" + wire width 32 \insn_in$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396" + wire width 32 \insn_in$89 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire output 63 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire input 65 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_in2$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute 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"MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \tmp_tmp_traptype + attribute \src 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$and$libresoc.v:79050$3648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" + cell $and $and$libresoc.v:79051$3649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:79051$3649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" + cell $and $and$libresoc.v:79052$3650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:79052$3650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79059$3657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$37 + connect \Y $and$libresoc.v:79059$3657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79060$3658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$39 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:79060$3658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79062$3660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$43 + connect \Y $and$libresoc.v:79062$3660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79064$3662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \B \$47 + connect \Y $and$libresoc.v:79064$3662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79076$3674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$71 + connect \Y $and$libresoc.v:79076$3674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79077$3675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:79077$3675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79079$3677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$77 + connect \Y $and$libresoc.v:79079$3677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79081$3679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:79081$3679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" + cell $eq $eq$libresoc.v:79046$3644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:79046$3644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" + cell $eq $eq$libresoc.v:79047$3645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:79047$3645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" + cell $eq $eq$libresoc.v:79048$3646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:79048$3646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + cell $eq $eq$libresoc.v:79049$3647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:79049$3647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" + cell $eq $eq$libresoc.v:79053$3651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:79053$3651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" + cell $eq $eq$libresoc.v:79054$3652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:79054$3652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + cell $eq $eq$libresoc.v:79055$3653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:79055$3653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" + cell $eq $eq$libresoc.v:79057$3655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:79057$3655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:79058$3656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:79058$3656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:79061$3659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:79061$3659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:79065$3663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:79065$3663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:79066$3664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:79066$3664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79068$3666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:79068$3666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79069$3667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:79069$3667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79071$3669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:79071$3669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:79073$3671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:79073$3671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:79075$3673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:79075$3673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:79078$3676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:79078$3676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79043$3638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_in_cr_bitfield_b + connect \Y $extend$libresoc.v:79043$3638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79044$3640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_in_cr_bitfield_o + connect \Y $extend$libresoc.v:79044$3640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79045$3642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_out_cr_bitfield + connect \Y $extend$libresoc.v:79045$3642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79082$3680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_a_reg_a + connect \Y $extend$libresoc.v:79082$3680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79083$3682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_c_reg_c + connect \Y $extend$libresoc.v:79083$3682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79084$3684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_o_reg_o + connect \Y $extend$libresoc.v:79084$3684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79085$3686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \dec_o2_reg_o2 + connect \Y $extend$libresoc.v:79085$3686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:79086$3688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 7 + connect \A \dec_cr_in_cr_bitfield + connect \Y $extend$libresoc.v:79086$3688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:79063$3661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:79063$3661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:79080$3678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:79080$3678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + cell $or $or$libresoc.v:79056$3654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \B \$30 + connect \Y $or$libresoc.v:79056$3654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:79067$3665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:79067$3665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:79070$3668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \B \$59 + connect \Y $or$libresoc.v:79070$3668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:79072$3670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \$63 + connect \Y $or$libresoc.v:79072$3670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:79074$3672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \B \$67 + connect \Y $or$libresoc.v:79074$3672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79043$3639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79043$3638_Y + connect \Y $pos$libresoc.v:79043$3639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79044$3641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79044$3640_Y + connect \Y $pos$libresoc.v:79044$3641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79045$3643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79045$3642_Y + connect \Y $pos$libresoc.v:79045$3643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79082$3681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79082$3680_Y + connect \Y $pos$libresoc.v:79082$3681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79083$3683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79083$3682_Y + connect \Y $pos$libresoc.v:79083$3683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79084$3685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79084$3684_Y + connect \Y $pos$libresoc.v:79084$3685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79085$3687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79085$3686_Y + connect \Y $pos$libresoc.v:79085$3687_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:79086$3689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:79086$3688_Y + connect \Y $pos$libresoc.v:79086$3689_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79087.13-79124.4" + cell \dec$171 \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79125.9-79140.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + connect \sv_nz \dec_a_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79141.9-79151.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79152.9-79158.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79159.13-79178.4" + cell \dec_cr_in \dec_cr_in$10 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79179.14-79191.4" + cell \dec_cr_out \dec_cr_out$11 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79192.9-79205.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79206.10-79215.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o2 \dec_o2_fast_o2 + connect \fast_o2_ok \dec_o2_fast_o2_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o2 \dec_o2_reg_o2 + connect \reg_o2_ok \dec_o2_reg_o2_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79216.16-79222.4" + cell \dec_oe$173 \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:79223.16-79228.4" + cell \dec_rc$172 \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:77344.7-77344.20" + process $proc$libresoc.v:77344$3748 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:79229.3-79243.6" + process $proc$libresoc.v:79229$3690 + assign { } { } + assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:79230.5-79230.29" + switch \initial + attribute \src "libresoc.v:79230.9-79230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$83 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_tmp_fn_unit[13:0] \dec_function_unit + end + sync always + update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] + end + attribute \src "libresoc.v:79244.3-79253.6" + process $proc$libresoc.v:79244$3691 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:79245.5-79245.29" + switch \initial + attribute \src "libresoc.v:79245.9-79245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "libresoc.v:79254.3-79266.6" + process $proc$libresoc.v:79254$3692 + assign { } { } + assign { } { } + assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:79255.5-79255.29" + switch \initial + attribute \src "libresoc.v:79255.9-79255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$49 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\tmp_tmp_insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\tmp_tmp_insn_type[6:0] 7'0000000 + case + assign $1\tmp_tmp_insn_type[6:0] \dec_internal_op + end + sync always + update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] + end + attribute \src "libresoc.v:79267.3-79282.6" + process $proc$libresoc.v:79267$3693 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:79268.5-79268.29" + switch \initial + attribute \src "libresoc.v:79268.9-79268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" + switch \$106 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" + switch \$108 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "libresoc.v:79283.3-79292.6" + process $proc$libresoc.v:79283$3694 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:79284.5-79284.29" + switch \initial + attribute \src "libresoc.v:79284.9-79284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" + switch \$110 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:79293.3-79302.6" + process $proc$libresoc.v:79293$3695 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:79294.5-79294.29" + switch \initial + attribute \src "libresoc.v:79294.9-79294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + switch \$112 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:79303.3-79326.6" + process $proc$libresoc.v:79303$3696 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:79304.5-79304.29" + switch \initial + attribute \src "libresoc.v:79304.9-79304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001011 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:79327.3-79484.6" + process $proc$libresoc.v:79327$3697 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\ea[6:0] $1\ea[6:0] + assign { } { } + assign $0\cr_out[6:0] $1\cr_out[6:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[6:0] $1\cr_in1[6:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[6:0] $1\cr_in2[6:0] + assign $0\cr_in2$1[6:0]$3698 $1\cr_in2$1[6:0]$3708 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$3699 $1\cr_in2_ok$2[0:0]$3709 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\exc_$signal[0:0]$3700 $1\exc_$signal[0:0]$3710 + assign $0\exc_$signal$3[0:0]$3701 $1\exc_$signal$3[0:0]$3711 + assign $0\exc_$signal$4[0:0]$3702 $1\exc_$signal$4[0:0]$3712 + assign $0\exc_$signal$5[0:0]$3703 $1\exc_$signal$5[0:0]$3713 + assign $0\exc_$signal$6[0:0]$3704 $1\exc_$signal$6[0:0]$3714 + assign $0\exc_$signal$7[0:0]$3705 $1\exc_$signal$7[0:0]$3715 + assign $0\exc_$signal$8[0:0]$3706 $1\exc_$signal$8[0:0]$3716 + assign $0\exc_$signal$9[0:0]$3707 $1\exc_$signal$9[0:0]$3717 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[13:0] $1\fn_unit[13:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[6:0] $1\reg1[6:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[6:0] $1\reg2[6:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[6:0] $1\reg3[6:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[6:0] $1\rego[6:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[7:0] $1\traptype[7:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $5\fasto1[2:0] + assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] + assign $0\fasto2[2:0] $5\fasto2[2:0] + assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] + assign $0\fast1[2:0] $5\fast1[2:0] + assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] + assign $0\fast2[2:0] $5\fast2[2:0] + assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:79328.5-79328.29" + switch \initial + attribute \src "libresoc.v:79328.9-79328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1227" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\fast1[2:0] $2\fast1[2:0] + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $1\fast2[2:0] $2\fast2[2:0] + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $1\rc[0:0] $2\rc[0:0] + assign $1\spr1[9:0] $2\spr1[9:0] + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + assign $1\msr[63:0] $2\msr[63:0] + assign $1\ea_ok[0:0] $2\ea_ok[0:0] + assign $1\ea[6:0] $2\ea[6:0] + assign $1\asmcode[7:0] $2\asmcode[7:0] + assign $1\cr_out[6:0] $2\cr_out[6:0] + assign $1\lk[0:0] $2\lk[0:0] + assign $1\cia[63:0] $2\cia[63:0] + assign $1\cr_in1[6:0] $2\cr_in1[6:0] + assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] + assign $1\cr_in2[6:0] $2\cr_in2[6:0] + assign $1\cr_in2$1[6:0]$3708 $2\cr_in2$1[6:0]$3718 + assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] + assign $1\cr_in2_ok$2[0:0]$3709 $2\cr_in2_ok$2[0:0]$3719 + assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] + assign $1\cr_rd[7:0] $2\cr_rd[7:0] + assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] + assign $1\cr_wr[7:0] $2\cr_wr[7:0] + assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] + assign $1\exc_$signal[0:0]$3710 $2\exc_$signal[0:0]$3720 + assign $1\exc_$signal$3[0:0]$3711 $2\exc_$signal$3[0:0]$3721 + assign $1\exc_$signal$4[0:0]$3712 $2\exc_$signal$4[0:0]$3722 + assign $1\exc_$signal$5[0:0]$3713 $2\exc_$signal$5[0:0]$3723 + assign $1\exc_$signal$6[0:0]$3714 $2\exc_$signal$6[0:0]$3724 + assign $1\exc_$signal$7[0:0]$3715 $2\exc_$signal$7[0:0]$3725 + assign $1\exc_$signal$8[0:0]$3716 $2\exc_$signal$8[0:0]$3726 + assign $1\exc_$signal$9[0:0]$3717 $2\exc_$signal$9[0:0]$3727 + assign $1\fasto1[2:0] $2\fasto1[2:0] + assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $1\fasto2[2:0] $2\fasto2[2:0] + assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $1\fn_unit[13:0] $2\fn_unit[13:0] + assign $1\input_carry[1:0] $2\input_carry[1:0] + assign $1\insn[31:0] $2\insn[31:0] + assign $1\insn_type[6:0] $2\insn_type[6:0] + assign $1\is_32bit[0:0] $2\is_32bit[0:0] + assign $1\oe[0:0] $2\oe[0:0] + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + assign $1\rc_ok[0:0] $2\rc_ok[0:0] + assign $1\reg1[6:0] $2\reg1[6:0] + assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] + assign $1\reg2[6:0] $2\reg2[6:0] + assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] + assign $1\reg3[6:0] $2\reg3[6:0] + assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] + assign $1\rego[6:0] $2\rego[6:0] + assign $1\rego_ok[0:0] $2\rego_ok[0:0] + assign $1\spro[9:0] $2\spro[9:0] + assign $1\spro_ok[0:0] $2\spro_ok[0:0] + assign $1\trapaddr[12:0] $2\trapaddr[12:0] + assign $1\traptype[7:0] $2\traptype[7:0] + assign $1\xer_in[2:0] $2\xer_in[2:0] + assign $1\xer_out[0:0] $2\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228" + switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3727 $2\exc_$signal$8[0:0]$3726 $2\exc_$signal$7[0:0]$3725 $2\exc_$signal$6[0:0]$3724 $2\exc_$signal$5[0:0]$3723 $2\exc_$signal$4[0:0]$3722 $2\exc_$signal$3[0:0]$3721 $2\exc_$signal[0:0]$3720 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3719 $2\cr_in2$1[6:0]$3718 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\insn[31:0] \dec_opcode_in + assign $2\insn_type[6:0] 7'0111111 + assign $2\fn_unit[13:0] 14'00000010000000 + assign $2\trapaddr[12:0] 13'0000001100000 + assign $2\traptype[7:0] 8'00000010 + assign $2\msr[63:0] \cur_msr + assign $2\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $3\fast1[2:0] + assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] + assign $2\fast2[2:0] $3\fast2[2:0] + assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] + assign $2\rc[0:0] $3\rc[0:0] + assign $2\spr1[9:0] $3\spr1[9:0] + assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] + assign $2\msr[63:0] $3\msr[63:0] + assign $2\ea_ok[0:0] $3\ea_ok[0:0] + assign $2\ea[6:0] $3\ea[6:0] + assign $2\asmcode[7:0] $3\asmcode[7:0] + assign $2\cr_out[6:0] $3\cr_out[6:0] + assign $2\lk[0:0] $3\lk[0:0] + assign $2\cia[63:0] $3\cia[63:0] + assign $2\cr_in1[6:0] $3\cr_in1[6:0] + assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] + assign $2\cr_in2[6:0] $3\cr_in2[6:0] + assign $2\cr_in2$1[6:0]$3718 $3\cr_in2$1[6:0]$3728 + assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3719 $3\cr_in2_ok$2[0:0]$3729 + assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $3\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $3\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3720 $3\exc_$signal[0:0]$3730 + assign $2\exc_$signal$3[0:0]$3721 $3\exc_$signal$3[0:0]$3731 + assign $2\exc_$signal$4[0:0]$3722 $3\exc_$signal$4[0:0]$3732 + assign $2\exc_$signal$5[0:0]$3723 $3\exc_$signal$5[0:0]$3733 + assign $2\exc_$signal$6[0:0]$3724 $3\exc_$signal$6[0:0]$3734 + assign $2\exc_$signal$7[0:0]$3725 $3\exc_$signal$7[0:0]$3735 + assign $2\exc_$signal$8[0:0]$3726 $3\exc_$signal$8[0:0]$3736 + assign $2\exc_$signal$9[0:0]$3727 $3\exc_$signal$9[0:0]$3737 + assign $2\fasto1[2:0] $3\fasto1[2:0] + assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] + assign $2\fasto2[2:0] $3\fasto2[2:0] + assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] + assign $2\fn_unit[13:0] $3\fn_unit[13:0] + assign $2\input_carry[1:0] $3\input_carry[1:0] + assign $2\insn[31:0] $3\insn[31:0] + assign $2\insn_type[6:0] $3\insn_type[6:0] + assign $2\is_32bit[0:0] $3\is_32bit[0:0] + assign $2\oe[0:0] $3\oe[0:0] + assign $2\oe_ok[0:0] $3\oe_ok[0:0] + assign $2\rc_ok[0:0] $3\rc_ok[0:0] + assign $2\reg1[6:0] $3\reg1[6:0] + assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] + assign $2\reg2[6:0] $3\reg2[6:0] + assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] + assign $2\reg3[6:0] $3\reg3[6:0] + assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] + assign $2\rego[6:0] $3\rego[6:0] + assign $2\rego_ok[0:0] $3\rego_ok[0:0] + assign $2\spro[9:0] $3\spro[9:0] + assign $2\spro_ok[0:0] $3\spro_ok[0:0] + assign $2\trapaddr[12:0] $3\trapaddr[12:0] + assign $2\traptype[7:0] $3\traptype[7:0] + assign $2\xer_in[2:0] $3\xer_in[2:0] + assign $2\xer_out[0:0] $3\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1231" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[13:0] 14'00000010000000 + assign $3\trapaddr[12:0] 13'0000001001000 + assign $3\traptype[7:0] 8'00000010 + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[13:0] 14'00000010000000 + assign $3\trapaddr[12:0] 13'0000001000000 + assign $3\traptype[7:0] 8'01000000 + assign { $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $4\fast1[2:0] + assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] + assign $2\fast2[2:0] $4\fast2[2:0] + assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] + assign $2\rc[0:0] $4\rc[0:0] + assign $2\spr1[9:0] $4\spr1[9:0] + assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] + assign $2\msr[63:0] $4\msr[63:0] + assign $2\ea_ok[0:0] $4\ea_ok[0:0] + assign $2\ea[6:0] $4\ea[6:0] + assign $2\asmcode[7:0] $4\asmcode[7:0] + assign $2\cr_out[6:0] $4\cr_out[6:0] + assign $2\lk[0:0] $4\lk[0:0] + assign $2\cia[63:0] $4\cia[63:0] + assign $2\cr_in1[6:0] $4\cr_in1[6:0] + assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] + assign $2\cr_in2[6:0] $4\cr_in2[6:0] + assign $2\cr_in2$1[6:0]$3718 $4\cr_in2$1[6:0]$3738 + assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3719 $4\cr_in2_ok$2[0:0]$3739 + assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $4\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $4\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3720 $4\exc_$signal[0:0]$3740 + assign $2\exc_$signal$3[0:0]$3721 $4\exc_$signal$3[0:0]$3741 + assign $2\exc_$signal$4[0:0]$3722 $4\exc_$signal$4[0:0]$3742 + assign $2\exc_$signal$5[0:0]$3723 $4\exc_$signal$5[0:0]$3743 + assign $2\exc_$signal$6[0:0]$3724 $4\exc_$signal$6[0:0]$3744 + assign $2\exc_$signal$7[0:0]$3725 $4\exc_$signal$7[0:0]$3745 + assign $2\exc_$signal$8[0:0]$3726 $4\exc_$signal$8[0:0]$3746 + assign $2\exc_$signal$9[0:0]$3727 $4\exc_$signal$9[0:0]$3747 + assign $2\fasto1[2:0] $4\fasto1[2:0] + assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] + assign $2\fasto2[2:0] $4\fasto2[2:0] + assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] + assign $2\fn_unit[13:0] $4\fn_unit[13:0] + assign $2\input_carry[1:0] $4\input_carry[1:0] + assign $2\insn[31:0] $4\insn[31:0] + assign $2\insn_type[6:0] $4\insn_type[6:0] + assign $2\is_32bit[0:0] $4\is_32bit[0:0] + assign $2\oe[0:0] $4\oe[0:0] + assign $2\oe_ok[0:0] $4\oe_ok[0:0] + assign $2\rc_ok[0:0] $4\rc_ok[0:0] + assign $2\reg1[6:0] $4\reg1[6:0] + assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] + assign $2\reg2[6:0] $4\reg2[6:0] + assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] + assign $2\reg3[6:0] $4\reg3[6:0] + assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] + assign $2\rego[6:0] $4\rego[6:0] + assign $2\rego_ok[0:0] $4\rego_ok[0:0] + assign $2\spro[9:0] $4\spro[9:0] + assign $2\spro_ok[0:0] $4\spro_ok[0:0] + assign $2\trapaddr[12:0] $4\trapaddr[12:0] + assign $2\traptype[7:0] $4\traptype[7:0] + assign $2\xer_in[2:0] $4\xer_in[2:0] + assign $2\xer_out[0:0] $4\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1237" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[13:0] 14'00000010000000 + assign $4\trapaddr[12:0] 13'0000000111000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[13:0] 14'00000010000000 + assign $4\trapaddr[12:0] 13'0000000110000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + end + end + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[13:0] 14'00000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[7:0] 8'00100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[13:0] 14'00000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[7:0] 8'00010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[13:0] 14'00000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'00000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[13:0] 14'00000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'10000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + switch \$32 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fasto1[2:0] 3'011 + assign $5\fasto1_ok[0:0] 1'1 + assign $5\fasto2[2:0] 3'100 + assign $5\fasto2_ok[0:0] 1'1 + case + assign $5\fasto1[2:0] $1\fasto1[2:0] + assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $5\fasto2[2:0] $1\fasto2[2:0] + assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fast1[2:0] 3'011 + assign $5\fast1_ok[0:0] 1'1 + assign $5\fast2[2:0] 3'100 + assign $5\fast2_ok[0:0] 1'1 + case + assign $5\fast1[2:0] $1\fast1[2:0] + assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $5\fast2[2:0] $1\fast2[2:0] + assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \rc $0\rc[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \msr $0\msr[63:0] + update \ea_ok $0\ea_ok[0:0] + update \ea $0\ea[6:0] + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[6:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[6:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[6:0] + update \cr_in2$1 $0\cr_in2$1[6:0]$3698 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3699 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \exc_$signal $0\exc_$signal[0:0]$3700 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3701 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3702 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3703 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3704 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3705 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3706 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3707 + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[13:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[6:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[6:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[6:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[6:0] + update \rego_ok $0\rego_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[7:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + connect \$100 $pos$libresoc.v:79043$3639_Y + connect \$102 $pos$libresoc.v:79044$3641_Y + connect \$104 $pos$libresoc.v:79045$3643_Y + connect \$106 $eq$libresoc.v:79046$3644_Y + connect \$108 $eq$libresoc.v:79047$3645_Y + connect \$110 $eq$libresoc.v:79048$3646_Y + connect \$112 $eq$libresoc.v:79049$3647_Y + connect \$114 $and$libresoc.v:79050$3648_Y + connect \$116 $and$libresoc.v:79051$3649_Y + connect \$118 $and$libresoc.v:79052$3650_Y + connect \$120 $eq$libresoc.v:79053$3651_Y + connect \$28 $eq$libresoc.v:79054$3652_Y + connect \$30 $eq$libresoc.v:79055$3653_Y + connect \$32 $or$libresoc.v:79056$3654_Y + connect \$34 $eq$libresoc.v:79057$3655_Y + connect \$37 $eq$libresoc.v:79058$3656_Y + connect \$39 $and$libresoc.v:79059$3657_Y + connect \$41 $and$libresoc.v:79060$3658_Y + connect \$43 $eq$libresoc.v:79061$3659_Y + connect \$45 $and$libresoc.v:79062$3660_Y + connect \$47 $not$libresoc.v:79063$3661_Y + connect \$49 $and$libresoc.v:79064$3662_Y + connect \$51 $eq$libresoc.v:79065$3663_Y + connect \$53 $eq$libresoc.v:79066$3664_Y + connect \$55 $or$libresoc.v:79067$3665_Y + connect \$57 $eq$libresoc.v:79068$3666_Y + connect \$59 $eq$libresoc.v:79069$3667_Y + connect \$61 $or$libresoc.v:79070$3668_Y + connect \$63 $eq$libresoc.v:79071$3669_Y + connect \$65 $or$libresoc.v:79072$3670_Y + connect \$67 $eq$libresoc.v:79073$3671_Y + connect \$69 $or$libresoc.v:79074$3672_Y + connect \$71 $eq$libresoc.v:79075$3673_Y + connect \$73 $and$libresoc.v:79076$3674_Y + connect \$75 $and$libresoc.v:79077$3675_Y + connect \$77 $eq$libresoc.v:79078$3676_Y + connect \$79 $and$libresoc.v:79079$3677_Y + connect \$81 $not$libresoc.v:79080$3678_Y + connect \$83 $and$libresoc.v:79081$3679_Y + connect \$90 $pos$libresoc.v:79082$3681_Y + connect \$92 $pos$libresoc.v:79083$3683_Y + connect \$94 $pos$libresoc.v:79084$3685_Y + connect \$96 $pos$libresoc.v:79085$3687_Y + connect \$98 $pos$libresoc.v:79086$3689_Y + connect \dec2_exc_$signal 1'0 + connect \dec2_exc_$signal$12 1'0 + connect \dec2_exc_$signal$13 1'0 + connect \dec2_exc_$signal$14 1'0 + connect \dec2_exc_$signal$15 1'0 + connect \dec2_exc_$signal$16 1'0 + connect \dec2_exc_$signal$17 1'0 + connect \dec2_exc_$signal$18 1'0 + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 8'00000000 + connect \tmp_tmp_exc_$signal 1'0 + connect \tmp_tmp_exc_$signal$21 1'0 + connect \tmp_tmp_exc_$signal$22 1'0 + connect \tmp_tmp_exc_$signal$23 1'0 + connect \tmp_tmp_exc_$signal$24 1'0 + connect \tmp_tmp_exc_$signal$25 1'0 + connect \tmp_tmp_exc_$signal$26 1'0 + connect \tmp_tmp_exc_$signal$27 1'0 + connect \illeg_ok \$120 + connect \priv_ok \$118 + connect \dec_irq_ok \$116 + connect \ext_irq_ok \$114 + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o2_ok \dec_o2_fast_o2 } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok + connect \tmp_cr_out \$104 + connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok + connect \tmp_cr_in2$19 \$102 + connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok + connect \tmp_cr_in2 \$100 + connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok + connect \tmp_cr_in1 \$98 + connect \tmp_ea_ok \dec_o2_reg_o2_ok + connect \tmp_ea \$96 + connect \tmp_rego_ok \dec_o_reg_o_ok + connect \tmp_rego \$94 + connect \tmp_reg3_ok \dec_c_reg_c_ok + connect \tmp_reg3 \$92 + connect \tmp_reg2_ok \dec_b_reg_b_ok + connect \tmp_reg2 \dec_b_reg_b + connect \tmp_reg1_ok \dec_a_reg_a_ok + connect \tmp_reg1 \$90 + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \insn_in$89 \dec_opcode_in + connect \insn_in$88 \dec_opcode_in + connect \insn_in$87 \dec_opcode_in + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$86 \dec_opcode_in + connect \insn_in$85 \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in + connect \dec_a_sv_nz \sv_a_nz + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \is_mmu_spr \$69 + connect \is_spr_mv \$55 + connect \spr { \dec_SPR [4:0] \dec_SPR [9:5] } + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \insn_in$36 \dec_opcode_in + connect \insn_in \dec_opcode_in +end +attribute \src "libresoc.v:79568.1-80248.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" +attribute \generator "nMigen" +module \dec22 + attribute \src "libresoc.v:80187.3-80196.6" + wire width 2 $0\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:80197.3-80206.6" + wire width 2 $0\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:80067.3-80076.6" + wire width 8 $0\dec22_asmcode[7:0] + attribute \src "libresoc.v:80107.3-80116.6" + wire $0\dec22_br[0:0] + attribute \src "libresoc.v:79927.3-79936.6" + wire width 3 $0\dec22_cr_in[2:0] + attribute \src "libresoc.v:79937.3-79946.6" + wire width 3 $0\dec22_cr_out[2:0] + attribute \src "libresoc.v:80057.3-80066.6" + wire width 2 $0\dec22_cry_in[1:0] + attribute \src "libresoc.v:80097.3-80106.6" + wire $0\dec22_cry_out[0:0] + attribute \src "libresoc.v:80137.3-80146.6" + wire width 5 $0\dec22_form[4:0] + attribute \src "libresoc.v:79917.3-79926.6" + wire width 14 $0\dec22_function_unit[13:0] + attribute \src "libresoc.v:80207.3-80216.6" + wire width 3 $0\dec22_in1_sel[2:0] + attribute \src "libresoc.v:80217.3-80226.6" + wire width 4 $0\dec22_in2_sel[3:0] + attribute \src "libresoc.v:80227.3-80236.6" + wire width 2 $0\dec22_in3_sel[1:0] + attribute \src "libresoc.v:80027.3-80036.6" + wire width 7 $0\dec22_internal_op[6:0] + attribute \src "libresoc.v:80077.3-80086.6" + wire $0\dec22_inv_a[0:0] + attribute \src "libresoc.v:80087.3-80096.6" + wire $0\dec22_inv_out[0:0] + attribute \src "libresoc.v:80147.3-80156.6" + wire $0\dec22_is_32b[0:0] + attribute \src "libresoc.v:80017.3-80026.6" + wire width 4 $0\dec22_ldst_len[3:0] + attribute \src "libresoc.v:80167.3-80176.6" + wire $0\dec22_lk[0:0] + attribute \src "libresoc.v:80237.3-80246.6" + wire width 3 $0\dec22_out_sel[2:0] + attribute \src "libresoc.v:80047.3-80056.6" + wire width 2 $0\dec22_rc_sel[1:0] + attribute \src "libresoc.v:80127.3-80136.6" + wire $0\dec22_rsrv[0:0] + attribute \src "libresoc.v:80177.3-80186.6" + wire $0\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:80157.3-80166.6" + wire $0\dec22_sgn[0:0] + attribute \src "libresoc.v:80117.3-80126.6" + wire $0\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79997.3-80006.6" + wire width 3 $0\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:80007.3-80016.6" + wire width 3 $0\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79947.3-79956.6" + wire width 3 $0\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79957.3-79966.6" + wire width 3 $0\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79967.3-79976.6" + wire width 3 $0\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79987.3-79996.6" + wire width 3 $0\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79977.3-79986.6" + wire width 3 $0\dec22_sv_out[2:0] + attribute \src "libresoc.v:80037.3-80046.6" + wire width 2 $0\dec22_upd[1:0] + attribute \src "libresoc.v:79569.7-79569.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:80187.3-80196.6" + wire width 2 $1\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:80197.3-80206.6" + wire width 2 $1\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:80067.3-80076.6" + wire width 8 $1\dec22_asmcode[7:0] + attribute \src "libresoc.v:80107.3-80116.6" + wire $1\dec22_br[0:0] + attribute \src "libresoc.v:79927.3-79936.6" + wire width 3 $1\dec22_cr_in[2:0] + attribute \src "libresoc.v:79937.3-79946.6" + wire width 3 $1\dec22_cr_out[2:0] + attribute \src "libresoc.v:80057.3-80066.6" + wire width 2 $1\dec22_cry_in[1:0] + attribute \src "libresoc.v:80097.3-80106.6" + wire $1\dec22_cry_out[0:0] + attribute \src "libresoc.v:80137.3-80146.6" + wire width 5 $1\dec22_form[4:0] + attribute \src "libresoc.v:79917.3-79926.6" + wire width 14 $1\dec22_function_unit[13:0] + attribute \src "libresoc.v:80207.3-80216.6" + wire width 3 $1\dec22_in1_sel[2:0] + attribute \src "libresoc.v:80217.3-80226.6" + wire width 4 $1\dec22_in2_sel[3:0] + attribute \src "libresoc.v:80227.3-80236.6" + wire width 2 $1\dec22_in3_sel[1:0] + attribute \src "libresoc.v:80027.3-80036.6" + wire width 7 $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:80077.3-80086.6" + wire $1\dec22_inv_a[0:0] + attribute \src "libresoc.v:80087.3-80096.6" + wire $1\dec22_inv_out[0:0] + attribute \src "libresoc.v:80147.3-80156.6" + wire $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:80017.3-80026.6" + wire width 4 $1\dec22_ldst_len[3:0] + attribute \src "libresoc.v:80167.3-80176.6" + wire $1\dec22_lk[0:0] + attribute \src "libresoc.v:80237.3-80246.6" + wire width 3 $1\dec22_out_sel[2:0] + attribute \src "libresoc.v:80047.3-80056.6" + wire width 2 $1\dec22_rc_sel[1:0] + attribute \src "libresoc.v:80127.3-80136.6" + wire $1\dec22_rsrv[0:0] + attribute \src "libresoc.v:80177.3-80186.6" + wire $1\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:80157.3-80166.6" + wire $1\dec22_sgn[0:0] + attribute \src "libresoc.v:80117.3-80126.6" + wire $1\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79997.3-80006.6" + wire width 3 $1\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:80007.3-80016.6" + wire width 3 $1\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79947.3-79956.6" + wire width 3 $1\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79957.3-79966.6" + wire width 3 $1\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79967.3-79976.6" + wire width 3 $1\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79987.3-79996.6" + wire width 3 $1\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79977.3-79986.6" + wire width 3 $1\dec22_sv_out[2:0] + attribute \src "libresoc.v:80037.3-80046.6" + wire width 2 $1\dec22_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec22_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec22_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec22_upd + attribute \src "libresoc.v:79569.7-79569.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 4 \opcode_switch + attribute \src "libresoc.v:79569.7-79569.20" + process $proc$libresoc.v:79569$3782 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:79917.3-79926.6" + process $proc$libresoc.v:79917$3749 + assign { } { } + assign { } { } + assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] + attribute \src "libresoc.v:79918.5-79918.29" + switch \initial + attribute \src "libresoc.v:79918.9-79918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_function_unit[13:0] 14'10000000000000 + case + assign $1\dec22_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec22_function_unit $0\dec22_function_unit[13:0] + end + attribute \src "libresoc.v:79927.3-79936.6" + process $proc$libresoc.v:79927$3750 + assign { } { } + assign { } { } + assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] + attribute \src "libresoc.v:79928.5-79928.29" + switch \initial + attribute \src "libresoc.v:79928.9-79928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cr_in[2:0] 3'000 + case + assign $1\dec22_cr_in[2:0] 3'000 + end + sync always + update \dec22_cr_in $0\dec22_cr_in[2:0] + end + attribute \src "libresoc.v:79937.3-79946.6" + process $proc$libresoc.v:79937$3751 + assign { } { } + assign { } { } + assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] + attribute \src "libresoc.v:79938.5-79938.29" + switch \initial + attribute \src "libresoc.v:79938.9-79938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cr_out[2:0] 3'001 + case + assign $1\dec22_cr_out[2:0] 3'000 + end + sync always + update \dec22_cr_out $0\dec22_cr_out[2:0] + end + attribute \src "libresoc.v:79947.3-79956.6" + process $proc$libresoc.v:79947$3752 + assign { } { } + assign { } { } + assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79948.5-79948.29" + switch \initial + attribute \src "libresoc.v:79948.9-79948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in1[2:0] 3'000 + case + assign $1\dec22_sv_in1[2:0] 3'000 + end + sync always + update \dec22_sv_in1 $0\dec22_sv_in1[2:0] + end + attribute \src "libresoc.v:79957.3-79966.6" + process $proc$libresoc.v:79957$3753 + assign { } { } + assign { } { } + assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79958.5-79958.29" + switch \initial + attribute \src "libresoc.v:79958.9-79958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in2[2:0] 3'000 + case + assign $1\dec22_sv_in2[2:0] 3'000 + end + sync always + update \dec22_sv_in2 $0\dec22_sv_in2[2:0] + end + attribute \src "libresoc.v:79967.3-79976.6" + process $proc$libresoc.v:79967$3754 + assign { } { } + assign { } { } + assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79968.5-79968.29" + switch \initial + attribute \src "libresoc.v:79968.9-79968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in3[2:0] 3'000 + case + assign $1\dec22_sv_in3[2:0] 3'000 + end + sync always + update \dec22_sv_in3 $0\dec22_sv_in3[2:0] + end + attribute \src "libresoc.v:79977.3-79986.6" + process $proc$libresoc.v:79977$3755 + assign { } { } + assign { } { } + assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] + attribute \src "libresoc.v:79978.5-79978.29" + switch \initial + attribute \src "libresoc.v:79978.9-79978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_out[2:0] 3'000 + case + assign $1\dec22_sv_out[2:0] 3'000 + end + sync always + update \dec22_sv_out $0\dec22_sv_out[2:0] + end + attribute \src "libresoc.v:79987.3-79996.6" + process $proc$libresoc.v:79987$3756 + assign { } { } + assign { } { } + assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79988.5-79988.29" + switch \initial + attribute \src "libresoc.v:79988.9-79988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_out2[2:0] 3'000 + case + assign $1\dec22_sv_out2[2:0] 3'000 + end + sync always + update \dec22_sv_out2 $0\dec22_sv_out2[2:0] + end + attribute \src "libresoc.v:79997.3-80006.6" + process $proc$libresoc.v:79997$3757 + assign { } { } + assign { } { } + assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79998.5-79998.29" + switch \initial + attribute \src "libresoc.v:79998.9-79998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_cr_in[2:0] 3'000 + case + assign $1\dec22_sv_cr_in[2:0] 3'000 + end + sync always + update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] + end + attribute \src "libresoc.v:80007.3-80016.6" + process $proc$libresoc.v:80007$3758 + assign { } { } + assign { } { } + assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:80008.5-80008.29" + switch \initial + attribute \src "libresoc.v:80008.9-80008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_cr_out[2:0] 3'000 + case + assign $1\dec22_sv_cr_out[2:0] 3'000 + end + sync always + update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] + end + attribute \src "libresoc.v:80017.3-80026.6" + process $proc$libresoc.v:80017$3759 + assign { } { } + assign { } { } + assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] + attribute \src "libresoc.v:80018.5-80018.29" + switch \initial + attribute \src "libresoc.v:80018.9-80018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_ldst_len[3:0] 4'0000 + case + assign $1\dec22_ldst_len[3:0] 4'0000 + end + sync always + update \dec22_ldst_len $0\dec22_ldst_len[3:0] + end + attribute \src "libresoc.v:80027.3-80036.6" + process $proc$libresoc.v:80027$3760 + assign { } { } + assign { } { } + assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:80028.5-80028.29" + switch \initial + attribute \src "libresoc.v:80028.9-80028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_internal_op[6:0] 7'1001100 + case + assign $1\dec22_internal_op[6:0] 7'0000000 + end + sync always + update \dec22_internal_op $0\dec22_internal_op[6:0] + end + attribute \src "libresoc.v:80037.3-80046.6" + process $proc$libresoc.v:80037$3761 + assign { } { } + assign { } { } + assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] + attribute \src "libresoc.v:80038.5-80038.29" + switch \initial + attribute \src "libresoc.v:80038.9-80038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_upd[1:0] 2'00 + case + assign $1\dec22_upd[1:0] 2'00 + end + sync always + update \dec22_upd $0\dec22_upd[1:0] + end + attribute \src "libresoc.v:80047.3-80056.6" + process $proc$libresoc.v:80047$3762 + assign { } { } + assign { } { } + assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] + attribute \src "libresoc.v:80048.5-80048.29" + switch \initial + attribute \src "libresoc.v:80048.9-80048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_rc_sel[1:0] 2'10 + case + assign $1\dec22_rc_sel[1:0] 2'00 + end + sync always + update \dec22_rc_sel $0\dec22_rc_sel[1:0] + end + attribute \src "libresoc.v:80057.3-80066.6" + process $proc$libresoc.v:80057$3763 + assign { } { } + assign { } { } + assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] + attribute \src "libresoc.v:80058.5-80058.29" + switch \initial + attribute \src "libresoc.v:80058.9-80058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cry_in[1:0] 2'00 + case + assign $1\dec22_cry_in[1:0] 2'00 + end + sync always + update \dec22_cry_in $0\dec22_cry_in[1:0] + end + attribute \src "libresoc.v:80067.3-80076.6" + process $proc$libresoc.v:80067$3764 + assign { } { } + assign { } { } + assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] + attribute \src "libresoc.v:80068.5-80068.29" + switch \initial + attribute \src "libresoc.v:80068.9-80068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_asmcode[7:0] 8'10011100 + case + assign $1\dec22_asmcode[7:0] 8'00000000 + end + sync always + update \dec22_asmcode $0\dec22_asmcode[7:0] + end + attribute \src "libresoc.v:80077.3-80086.6" + process $proc$libresoc.v:80077$3765 + assign { } { } + assign { } { } + assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] + attribute \src "libresoc.v:80078.5-80078.29" + switch \initial + attribute \src "libresoc.v:80078.9-80078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_inv_a[0:0] 1'0 + case + assign $1\dec22_inv_a[0:0] 1'0 + end + sync always + update \dec22_inv_a $0\dec22_inv_a[0:0] + end + attribute \src "libresoc.v:80087.3-80096.6" + process $proc$libresoc.v:80087$3766 + assign { } { } + assign { } { } + assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] + attribute \src "libresoc.v:80088.5-80088.29" + switch \initial + attribute \src "libresoc.v:80088.9-80088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_inv_out[0:0] 1'0 + case + assign $1\dec22_inv_out[0:0] 1'0 + end + sync always + update \dec22_inv_out $0\dec22_inv_out[0:0] + end + attribute \src "libresoc.v:80097.3-80106.6" + process $proc$libresoc.v:80097$3767 + assign { } { } + assign { } { } + assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] + attribute \src "libresoc.v:80098.5-80098.29" + switch \initial + attribute \src "libresoc.v:80098.9-80098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cry_out[0:0] 1'0 + case + assign $1\dec22_cry_out[0:0] 1'0 + end + sync always + update \dec22_cry_out $0\dec22_cry_out[0:0] + end + attribute \src "libresoc.v:80107.3-80116.6" + process $proc$libresoc.v:80107$3768 + assign { } { } + assign { } { } + assign $0\dec22_br[0:0] $1\dec22_br[0:0] + attribute \src "libresoc.v:80108.5-80108.29" + switch \initial + attribute \src "libresoc.v:80108.9-80108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_br[0:0] 1'0 + case + assign $1\dec22_br[0:0] 1'0 + end + sync always + update \dec22_br $0\dec22_br[0:0] + end + attribute \src "libresoc.v:80117.3-80126.6" + process $proc$libresoc.v:80117$3769 + assign { } { } + assign { } { } + assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:80118.5-80118.29" + switch \initial + attribute \src "libresoc.v:80118.9-80118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgn_ext[0:0] 1'0 + case + assign $1\dec22_sgn_ext[0:0] 1'0 + end + sync always + update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] + end + attribute \src "libresoc.v:80127.3-80136.6" + process $proc$libresoc.v:80127$3770 + assign { } { } + assign { } { } + assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] + attribute \src "libresoc.v:80128.5-80128.29" + switch \initial + attribute \src "libresoc.v:80128.9-80128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_rsrv[0:0] 1'0 + case + assign $1\dec22_rsrv[0:0] 1'0 + end + sync always + update \dec22_rsrv $0\dec22_rsrv[0:0] + end + attribute \src "libresoc.v:80137.3-80146.6" + process $proc$libresoc.v:80137$3771 + assign { } { } + assign { } { } + assign $0\dec22_form[4:0] $1\dec22_form[4:0] + attribute \src "libresoc.v:80138.5-80138.29" + switch \initial + attribute \src "libresoc.v:80138.9-80138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_form[4:0] 5'11101 + case + assign $1\dec22_form[4:0] 5'00000 + end + sync always + update \dec22_form $0\dec22_form[4:0] + end + attribute \src "libresoc.v:80147.3-80156.6" + process $proc$libresoc.v:80147$3772 + assign { } { } + assign { } { } + assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:80148.5-80148.29" + switch \initial + attribute \src "libresoc.v:80148.9-80148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_is_32b[0:0] 1'0 + case + assign $1\dec22_is_32b[0:0] 1'0 + end + sync always + update \dec22_is_32b $0\dec22_is_32b[0:0] + end + attribute \src "libresoc.v:80157.3-80166.6" + process $proc$libresoc.v:80157$3773 + assign { } { } + assign { } { } + assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] + attribute \src "libresoc.v:80158.5-80158.29" + switch \initial + attribute \src "libresoc.v:80158.9-80158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgn[0:0] 1'0 + case + assign $1\dec22_sgn[0:0] 1'0 + end + sync always + update \dec22_sgn $0\dec22_sgn[0:0] + end + attribute \src "libresoc.v:80167.3-80176.6" + process $proc$libresoc.v:80167$3774 + assign { } { } + assign { } { } + assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] + attribute \src "libresoc.v:80168.5-80168.29" + switch \initial + attribute \src "libresoc.v:80168.9-80168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_lk[0:0] 1'0 + case + assign $1\dec22_lk[0:0] 1'0 + end + sync always + update \dec22_lk $0\dec22_lk[0:0] + end + attribute \src "libresoc.v:80177.3-80186.6" + process $proc$libresoc.v:80177$3775 + assign { } { } + assign { } { } + assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:80178.5-80178.29" + switch \initial + attribute \src "libresoc.v:80178.9-80178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgl_pipe[0:0] 1'0 + case + assign $1\dec22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:80187.3-80196.6" + process $proc$libresoc.v:80187$3776 + assign { } { } + assign { } { } + assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:80188.5-80188.29" + switch \initial + attribute \src "libresoc.v:80188.9-80188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_SV_Etype[1:0] 2'00 + case + assign $1\dec22_SV_Etype[1:0] 2'00 + end + sync always + update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] + end + attribute \src "libresoc.v:80197.3-80206.6" + process $proc$libresoc.v:80197$3777 + assign { } { } + assign { } { } + assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:80198.5-80198.29" + switch \initial + attribute \src "libresoc.v:80198.9-80198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_SV_Ptype[1:0] 2'00 + case + assign $1\dec22_SV_Ptype[1:0] 2'00 + end + sync always + update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] + end + attribute \src "libresoc.v:80207.3-80216.6" + process $proc$libresoc.v:80207$3778 + assign { } { } + assign { } { } + assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] + attribute \src "libresoc.v:80208.5-80208.29" + switch \initial + attribute \src "libresoc.v:80208.9-80208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in1_sel[2:0] 3'010 + case + assign $1\dec22_in1_sel[2:0] 3'000 + end + sync always + update \dec22_in1_sel $0\dec22_in1_sel[2:0] + end + attribute \src "libresoc.v:80217.3-80226.6" + process $proc$libresoc.v:80217$3779 + assign { } { } + assign { } { } + assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] + attribute \src "libresoc.v:80218.5-80218.29" + switch \initial + attribute \src "libresoc.v:80218.9-80218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in2_sel[3:0] 4'0000 + case + assign $1\dec22_in2_sel[3:0] 4'0000 + end + sync always + update \dec22_in2_sel $0\dec22_in2_sel[3:0] + end + attribute \src "libresoc.v:80227.3-80236.6" + process $proc$libresoc.v:80227$3780 + assign { } { } + assign { } { } + assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] + attribute \src "libresoc.v:80228.5-80228.29" + switch \initial + attribute \src "libresoc.v:80228.9-80228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in3_sel[1:0] 2'00 + case + assign $1\dec22_in3_sel[1:0] 2'00 + end + sync always + update \dec22_in3_sel $0\dec22_in3_sel[1:0] + end + attribute \src "libresoc.v:80237.3-80246.6" + process $proc$libresoc.v:80237$3781 + assign { } { } + assign { } { } + assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] + attribute \src "libresoc.v:80238.5-80238.29" + switch \initial + attribute \src "libresoc.v:80238.9-80238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_out_sel[2:0] 3'100 + case + assign $1\dec22_out_sel[2:0] 3'000 + end + sync always + update \dec22_out_sel $0\dec22_out_sel[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:80252.1-81823.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "libresoc.v:81600.3-81636.6" + wire width 2 $0\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:81637.3-81673.6" + wire width 2 $0\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:81156.3-81192.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:81304.3-81340.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:80638.3-80674.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:80675.3-80711.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:81119.3-81155.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:81267.3-81303.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:81415.3-81451.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:80601.3-80637.6" + wire width 14 $0\dec30_function_unit[13:0] + attribute \src "libresoc.v:81674.3-81710.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:81711.3-81747.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:81748.3-81784.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:81008.3-81044.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:81193.3-81229.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:81230.3-81266.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:81452.3-81488.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:80971.3-81007.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:81526.3-81562.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:81785.3-81821.6" + wire width 3 $0\dec30_out_sel[2:0] + attribute \src "libresoc.v:81082.3-81118.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:81378.3-81414.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:81563.3-81599.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:81489.3-81525.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:81341.3-81377.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:80897.3-80933.6" + wire width 3 $0\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:80934.3-80970.6" + wire width 3 $0\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:80712.3-80748.6" + wire width 3 $0\dec30_sv_in1[2:0] + attribute \src "libresoc.v:80749.3-80785.6" + wire width 3 $0\dec30_sv_in2[2:0] + attribute \src "libresoc.v:80786.3-80822.6" + wire width 3 $0\dec30_sv_in3[2:0] + attribute \src "libresoc.v:80860.3-80896.6" + wire width 3 $0\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80823.3-80859.6" + wire width 3 $0\dec30_sv_out[2:0] + attribute \src "libresoc.v:81045.3-81081.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:80253.7-80253.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:81600.3-81636.6" + wire width 2 $1\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:81637.3-81673.6" + wire width 2 $1\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:81156.3-81192.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:81304.3-81340.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:80638.3-80674.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:80675.3-80711.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:81119.3-81155.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:81267.3-81303.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:81415.3-81451.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:80601.3-80637.6" + wire width 14 $1\dec30_function_unit[13:0] + attribute \src "libresoc.v:81674.3-81710.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:81711.3-81747.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:81748.3-81784.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:81008.3-81044.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:81193.3-81229.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:81230.3-81266.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:81452.3-81488.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:80971.3-81007.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:81526.3-81562.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:81785.3-81821.6" + wire width 3 $1\dec30_out_sel[2:0] + attribute \src "libresoc.v:81082.3-81118.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:81378.3-81414.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:81563.3-81599.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:81489.3-81525.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:81341.3-81377.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:80897.3-80933.6" + wire width 3 $1\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:80934.3-80970.6" + wire width 3 $1\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:80712.3-80748.6" + wire width 3 $1\dec30_sv_in1[2:0] + attribute \src "libresoc.v:80749.3-80785.6" + wire width 3 $1\dec30_sv_in2[2:0] + attribute \src "libresoc.v:80786.3-80822.6" + wire width 3 $1\dec30_sv_in3[2:0] + attribute \src "libresoc.v:80860.3-80896.6" + wire width 3 $1\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80823.3-80859.6" + wire width 3 $1\dec30_sv_out[2:0] + attribute \src "libresoc.v:81045.3-81081.6" + wire width 2 $1\dec30_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec30_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec30_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec30_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec30_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec30_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec30_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec30_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec30_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec30_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec30_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec30_upd + attribute \src "libresoc.v:80253.7-80253.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 4 \opcode_switch + attribute \src "libresoc.v:80253.7-80253.20" + process $proc$libresoc.v:80253$3816 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:80601.3-80637.6" + process $proc$libresoc.v:80601$3783 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] + attribute \src "libresoc.v:80602.5-80602.29" + switch \initial + attribute \src "libresoc.v:80602.9-80602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[13:0] 14'00000000001000 + case + assign $1\dec30_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[13:0] + end + attribute \src "libresoc.v:80638.3-80674.6" + process $proc$libresoc.v:80638$3784 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:80639.5-80639.29" + switch \initial + attribute \src "libresoc.v:80639.9-80639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "libresoc.v:80675.3-80711.6" + process $proc$libresoc.v:80675$3785 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:80676.5-80676.29" + switch \initial + attribute \src "libresoc.v:80676.9-80676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + attribute \src "libresoc.v:80712.3-80748.6" + process $proc$libresoc.v:80712$3786 + assign { } { } + assign { } { } + assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] + attribute \src "libresoc.v:80713.5-80713.29" + switch \initial + attribute \src "libresoc.v:80713.9-80713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + case + assign $1\dec30_sv_in1[2:0] 3'000 + end + sync always + update \dec30_sv_in1 $0\dec30_sv_in1[2:0] + end + attribute \src "libresoc.v:80749.3-80785.6" + process $proc$libresoc.v:80749$3787 + assign { } { } + assign { } { } + assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] + attribute \src "libresoc.v:80750.5-80750.29" + switch \initial + attribute \src "libresoc.v:80750.9-80750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'010 + case + assign $1\dec30_sv_in2[2:0] 3'000 + end + sync always + update \dec30_sv_in2 $0\dec30_sv_in2[2:0] + end + attribute \src "libresoc.v:80786.3-80822.6" + process $proc$libresoc.v:80786$3788 + assign { } { } + assign { } { } + assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] + attribute \src "libresoc.v:80787.5-80787.29" + switch \initial + attribute \src "libresoc.v:80787.9-80787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + case + assign $1\dec30_sv_in3[2:0] 3'000 + end + sync always + update \dec30_sv_in3 $0\dec30_sv_in3[2:0] + end + attribute \src "libresoc.v:80823.3-80859.6" + process $proc$libresoc.v:80823$3789 + assign { } { } + assign { } { } + assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] + attribute \src "libresoc.v:80824.5-80824.29" + switch \initial + attribute \src "libresoc.v:80824.9-80824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + case + assign $1\dec30_sv_out[2:0] 3'000 + end + sync always + update \dec30_sv_out $0\dec30_sv_out[2:0] + end + attribute \src "libresoc.v:80860.3-80896.6" + process $proc$libresoc.v:80860$3790 + assign { } { } + assign { } { } + assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80861.5-80861.29" + switch \initial + attribute \src "libresoc.v:80861.9-80861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + case + assign $1\dec30_sv_out2[2:0] 3'000 + end + sync always + update \dec30_sv_out2 $0\dec30_sv_out2[2:0] + end + attribute \src "libresoc.v:80897.3-80933.6" + process $proc$libresoc.v:80897$3791 + assign { } { } + assign { } { } + assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:80898.5-80898.29" + switch \initial + attribute \src "libresoc.v:80898.9-80898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + case + assign $1\dec30_sv_cr_in[2:0] 3'000 + end + sync always + update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] + end + attribute \src "libresoc.v:80934.3-80970.6" + process $proc$libresoc.v:80934$3792 + assign { } { } + assign { } { } + assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:80935.5-80935.29" + switch \initial + attribute \src "libresoc.v:80935.9-80935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + case + assign $1\dec30_sv_cr_out[2:0] 3'000 + end + sync always + update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] + end + attribute \src "libresoc.v:80971.3-81007.6" + process $proc$libresoc.v:80971$3793 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:80972.5-80972.29" + switch \initial + attribute \src "libresoc.v:80972.9-80972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "libresoc.v:81008.3-81044.6" + process $proc$libresoc.v:81008$3794 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:81009.5-81009.29" + switch \initial + attribute \src "libresoc.v:81009.9-81009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "libresoc.v:81045.3-81081.6" + process $proc$libresoc.v:81045$3795 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:81046.5-81046.29" + switch \initial + attribute \src "libresoc.v:81046.9-81046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "libresoc.v:81082.3-81118.6" + process $proc$libresoc.v:81082$3796 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:81083.5-81083.29" + switch \initial + attribute \src "libresoc.v:81083.9-81083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:81119.3-81155.6" + process $proc$libresoc.v:81119$3797 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:81120.5-81120.29" + switch \initial + attribute \src "libresoc.v:81120.9-81120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:81156.3-81192.6" + process $proc$libresoc.v:81156$3798 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:81157.5-81157.29" + switch \initial + attribute \src "libresoc.v:81157.9-81157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:81193.3-81229.6" + process $proc$libresoc.v:81193$3799 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:81194.5-81194.29" + switch \initial + attribute \src "libresoc.v:81194.9-81194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "libresoc.v:81230.3-81266.6" + process $proc$libresoc.v:81230$3800 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:81231.5-81231.29" + switch \initial + attribute \src "libresoc.v:81231.9-81231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "libresoc.v:81267.3-81303.6" + process $proc$libresoc.v:81267$3801 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:81268.5-81268.29" + switch \initial + attribute \src "libresoc.v:81268.9-81268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "libresoc.v:81304.3-81340.6" + process $proc$libresoc.v:81304$3802 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:81305.5-81305.29" + switch \initial + attribute \src "libresoc.v:81305.9-81305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "libresoc.v:81341.3-81377.6" + process $proc$libresoc.v:81341$3803 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:81342.5-81342.29" + switch \initial + attribute \src "libresoc.v:81342.9-81342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "libresoc.v:81378.3-81414.6" + process $proc$libresoc.v:81378$3804 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:81379.5-81379.29" + switch \initial + attribute \src "libresoc.v:81379.9-81379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "libresoc.v:81415.3-81451.6" + process $proc$libresoc.v:81415$3805 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:81416.5-81416.29" + switch \initial + attribute \src "libresoc.v:81416.9-81416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "libresoc.v:81452.3-81488.6" + process $proc$libresoc.v:81452$3806 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:81453.5-81453.29" + switch \initial + attribute \src "libresoc.v:81453.9-81453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "libresoc.v:81489.3-81525.6" + process $proc$libresoc.v:81489$3807 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:81490.5-81490.29" + switch \initial + attribute \src "libresoc.v:81490.9-81490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:81526.3-81562.6" + process $proc$libresoc.v:81526$3808 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:81527.5-81527.29" + switch \initial + attribute \src "libresoc.v:81527.9-81527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:81563.3-81599.6" + process $proc$libresoc.v:81563$3809 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:81564.5-81564.29" + switch \initial + attribute \src "libresoc.v:81564.9-81564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:81600.3-81636.6" + process $proc$libresoc.v:81600$3810 + assign { } { } + assign { } { } + assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:81601.5-81601.29" + switch \initial + attribute \src "libresoc.v:81601.9-81601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + case + assign $1\dec30_SV_Etype[1:0] 2'00 + end + sync always + update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] + end + attribute \src "libresoc.v:81637.3-81673.6" + process $proc$libresoc.v:81637$3811 + assign { } { } + assign { } { } + assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:81638.5-81638.29" + switch \initial + attribute \src "libresoc.v:81638.9-81638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + case + assign $1\dec30_SV_Ptype[1:0] 2'00 + end + sync always + update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] + end + attribute \src "libresoc.v:81674.3-81710.6" + process $proc$libresoc.v:81674$3812 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:81675.5-81675.29" + switch \initial + attribute \src "libresoc.v:81675.9-81675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:81711.3-81747.6" + process $proc$libresoc.v:81711$3813 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:81712.5-81712.29" + switch \initial + attribute \src "libresoc.v:81712.9-81712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:81748.3-81784.6" + process $proc$libresoc.v:81748$3814 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:81749.5-81749.29" + switch \initial + attribute \src "libresoc.v:81749.9-81749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:81785.3-81821.6" + process $proc$libresoc.v:81785$3815 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] + attribute \src "libresoc.v:81786.5-81786.29" + switch \initial + attribute \src "libresoc.v:81786.9-81786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[2:0] 3'010 + case + assign $1\dec30_out_sel[2:0] 3'000 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:81827.1-90475.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "libresoc.v:88686.3-88746.6" + wire width 2 $0\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:88747.3-88807.6" + wire width 2 $0\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:88625.3-88685.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:90028.3-90088.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:89052.3-89112.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:89113.3-89173.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:89784.3-89844.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:89967.3-90027.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:88564.3-88624.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:88442.3-88502.6" + wire width 14 $0\dec31_function_unit[13:0] + attribute \src "libresoc.v:88808.3-88868.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:88869.3-88929.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:88930.3-88990.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:88503.3-88563.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:89845.3-89905.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:89906.3-89966.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:90211.3-90271.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:89601.3-89661.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:90333.3-90393.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:88991.3-89051.6" + wire width 3 $0\dec31_out_sel[2:0] + attribute \src "libresoc.v:89723.3-89783.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:90150.3-90210.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:90394.3-90454.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:90272.3-90332.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:90089.3-90149.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:89479.3-89539.6" + wire width 3 $0\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:89540.3-89600.6" + wire width 3 $0\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:89174.3-89234.6" + wire width 3 $0\dec31_sv_in1[2:0] + attribute \src "libresoc.v:89235.3-89295.6" + wire width 3 $0\dec31_sv_in2[2:0] + attribute \src "libresoc.v:89296.3-89356.6" + wire width 3 $0\dec31_sv_in3[2:0] + attribute \src "libresoc.v:89418.3-89478.6" + wire width 3 $0\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89357.3-89417.6" + wire width 3 $0\dec31_sv_out[2:0] + attribute \src "libresoc.v:89662.3-89722.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:81828.7-81828.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:88686.3-88746.6" + wire width 2 $1\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:88747.3-88807.6" + wire width 2 $1\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:88625.3-88685.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:90028.3-90088.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:89052.3-89112.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:89113.3-89173.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:89784.3-89844.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:89967.3-90027.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:88564.3-88624.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:88442.3-88502.6" + wire width 14 $1\dec31_function_unit[13:0] + attribute \src "libresoc.v:88808.3-88868.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:88869.3-88929.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:88930.3-88990.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:88503.3-88563.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:89845.3-89905.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:89906.3-89966.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:90211.3-90271.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:89601.3-89661.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:90333.3-90393.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:88991.3-89051.6" + wire width 3 $1\dec31_out_sel[2:0] + attribute \src "libresoc.v:89723.3-89783.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:90150.3-90210.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:90394.3-90454.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:90272.3-90332.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:90089.3-90149.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:89479.3-89539.6" + wire width 3 $1\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:89540.3-89600.6" + wire width 3 $1\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:89174.3-89234.6" + wire width 3 $1\dec31_sv_in1[2:0] + attribute \src "libresoc.v:89235.3-89295.6" + wire width 3 $1\dec31_sv_in2[2:0] + attribute \src "libresoc.v:89296.3-89356.6" + wire width 3 $1\dec31_sv_in3[2:0] + attribute \src "libresoc.v:89418.3-89478.6" + wire width 3 $1\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89357.3-89417.6" + wire width 3 $1\dec31_sv_out[2:0] + attribute \src "libresoc.v:89662.3-89722.6" + wire width 2 $1\dec31_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_cry_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec31_dec_sub0_opcode_in + attribute \enum_base_type "SVEtype" + attribute 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\dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src 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attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_upd + attribute \src "libresoc.v:81828.7-81828.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:87794.18-87829.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_sv_cr_in \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + connect \dec31_dec_sub0_sv_cr_out \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + connect \dec31_dec_sub0_sv_in1 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + connect \dec31_dec_sub0_sv_in2 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + connect \dec31_dec_sub0_sv_in3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + connect \dec31_dec_sub0_sv_out \dec31_dec_sub0_dec31_dec_sub0_sv_out + connect \dec31_dec_sub0_sv_out2 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87830.19-87865.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_sv_cr_in \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + connect \dec31_dec_sub10_sv_cr_out \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + connect \dec31_dec_sub10_sv_in1 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + connect \dec31_dec_sub10_sv_in2 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + connect \dec31_dec_sub10_sv_in3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + connect \dec31_dec_sub10_sv_out \dec31_dec_sub10_dec31_dec_sub10_sv_out + connect \dec31_dec_sub10_sv_out2 \dec31_dec_sub10_dec31_dec_sub10_sv_out2 + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87866.19-87901.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_sv_cr_in \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + connect \dec31_dec_sub11_sv_cr_out \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + connect \dec31_dec_sub11_sv_in1 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + connect \dec31_dec_sub11_sv_in2 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + connect \dec31_dec_sub11_sv_in3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + connect \dec31_dec_sub11_sv_out \dec31_dec_sub11_dec31_dec_sub11_sv_out + connect \dec31_dec_sub11_sv_out2 \dec31_dec_sub11_dec31_dec_sub11_sv_out2 + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87902.19-87937.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_sv_cr_in \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + connect \dec31_dec_sub15_sv_cr_out \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + connect \dec31_dec_sub15_sv_in1 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + connect \dec31_dec_sub15_sv_in2 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + connect \dec31_dec_sub15_sv_in3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + connect \dec31_dec_sub15_sv_out \dec31_dec_sub15_dec31_dec_sub15_sv_out + connect \dec31_dec_sub15_sv_out2 \dec31_dec_sub15_dec31_dec_sub15_sv_out2 + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87938.19-87973.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_sv_cr_in \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + connect \dec31_dec_sub16_sv_cr_out \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + connect \dec31_dec_sub16_sv_in1 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + connect \dec31_dec_sub16_sv_in2 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + connect \dec31_dec_sub16_sv_in3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + connect \dec31_dec_sub16_sv_out \dec31_dec_sub16_dec31_dec_sub16_sv_out + connect \dec31_dec_sub16_sv_out2 \dec31_dec_sub16_dec31_dec_sub16_sv_out2 + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87974.19-88009.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_sv_cr_in \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + connect \dec31_dec_sub18_sv_cr_out \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + connect \dec31_dec_sub18_sv_in1 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + connect \dec31_dec_sub18_sv_in2 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + connect \dec31_dec_sub18_sv_in3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + connect \dec31_dec_sub18_sv_out \dec31_dec_sub18_dec31_dec_sub18_sv_out + connect \dec31_dec_sub18_sv_out2 \dec31_dec_sub18_dec31_dec_sub18_sv_out2 + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88010.19-88045.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_sv_cr_in \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + connect \dec31_dec_sub19_sv_cr_out \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + connect \dec31_dec_sub19_sv_in1 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + connect \dec31_dec_sub19_sv_in2 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + connect \dec31_dec_sub19_sv_in3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + connect \dec31_dec_sub19_sv_out \dec31_dec_sub19_dec31_dec_sub19_sv_out + connect \dec31_dec_sub19_sv_out2 \dec31_dec_sub19_dec31_dec_sub19_sv_out2 + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88046.19-88081.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_sv_cr_in \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + connect \dec31_dec_sub20_sv_cr_out \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + connect \dec31_dec_sub20_sv_in1 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + connect \dec31_dec_sub20_sv_in2 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + connect \dec31_dec_sub20_sv_in3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + connect \dec31_dec_sub20_sv_out \dec31_dec_sub20_dec31_dec_sub20_sv_out + connect \dec31_dec_sub20_sv_out2 \dec31_dec_sub20_dec31_dec_sub20_sv_out2 + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88082.19-88117.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_sv_cr_in \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + connect \dec31_dec_sub21_sv_cr_out \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + connect \dec31_dec_sub21_sv_in1 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + connect \dec31_dec_sub21_sv_in2 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + connect \dec31_dec_sub21_sv_in3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + connect \dec31_dec_sub21_sv_out \dec31_dec_sub21_dec31_dec_sub21_sv_out + connect \dec31_dec_sub21_sv_out2 \dec31_dec_sub21_dec31_dec_sub21_sv_out2 + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88118.19-88153.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_sv_cr_in \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + connect \dec31_dec_sub22_sv_cr_out \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + connect \dec31_dec_sub22_sv_in1 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + connect \dec31_dec_sub22_sv_in2 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + connect \dec31_dec_sub22_sv_in3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + connect \dec31_dec_sub22_sv_out \dec31_dec_sub22_dec31_dec_sub22_sv_out + connect \dec31_dec_sub22_sv_out2 \dec31_dec_sub22_dec31_dec_sub22_sv_out2 + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88154.19-88189.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_sv_cr_in \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + connect \dec31_dec_sub23_sv_cr_out \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + connect \dec31_dec_sub23_sv_in1 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + connect \dec31_dec_sub23_sv_in2 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + connect \dec31_dec_sub23_sv_in3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + connect \dec31_dec_sub23_sv_out \dec31_dec_sub23_dec31_dec_sub23_sv_out + connect \dec31_dec_sub23_sv_out2 \dec31_dec_sub23_dec31_dec_sub23_sv_out2 + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88190.19-88225.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_sv_cr_in \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + connect \dec31_dec_sub24_sv_cr_out \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + connect \dec31_dec_sub24_sv_in1 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + connect \dec31_dec_sub24_sv_in2 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + connect \dec31_dec_sub24_sv_in3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + connect \dec31_dec_sub24_sv_out \dec31_dec_sub24_dec31_dec_sub24_sv_out + connect \dec31_dec_sub24_sv_out2 \dec31_dec_sub24_dec31_dec_sub24_sv_out2 + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88226.19-88261.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_sv_cr_in \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + connect \dec31_dec_sub26_sv_cr_out \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + connect \dec31_dec_sub26_sv_in1 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + connect \dec31_dec_sub26_sv_in2 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + connect \dec31_dec_sub26_sv_in3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + connect \dec31_dec_sub26_sv_out \dec31_dec_sub26_dec31_dec_sub26_sv_out + connect \dec31_dec_sub26_sv_out2 \dec31_dec_sub26_dec31_dec_sub26_sv_out2 + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88262.19-88297.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_sv_cr_in \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + connect \dec31_dec_sub27_sv_cr_out \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + connect \dec31_dec_sub27_sv_in1 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + connect \dec31_dec_sub27_sv_in2 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + connect \dec31_dec_sub27_sv_in3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + connect \dec31_dec_sub27_sv_out \dec31_dec_sub27_dec31_dec_sub27_sv_out + connect \dec31_dec_sub27_sv_out2 \dec31_dec_sub27_dec31_dec_sub27_sv_out2 + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88298.19-88333.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_sv_cr_in \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + connect \dec31_dec_sub28_sv_cr_out \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + connect \dec31_dec_sub28_sv_in1 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + connect \dec31_dec_sub28_sv_in2 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + connect \dec31_dec_sub28_sv_in3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + connect \dec31_dec_sub28_sv_out \dec31_dec_sub28_dec31_dec_sub28_sv_out + connect \dec31_dec_sub28_sv_out2 \dec31_dec_sub28_dec31_dec_sub28_sv_out2 + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88334.18-88369.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_sv_cr_in \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + connect \dec31_dec_sub4_sv_cr_out \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + connect \dec31_dec_sub4_sv_in1 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + connect \dec31_dec_sub4_sv_in2 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + connect \dec31_dec_sub4_sv_in3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + connect \dec31_dec_sub4_sv_out \dec31_dec_sub4_dec31_dec_sub4_sv_out + connect \dec31_dec_sub4_sv_out2 \dec31_dec_sub4_dec31_dec_sub4_sv_out2 + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88370.18-88405.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_sv_cr_in \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + connect \dec31_dec_sub8_sv_cr_out \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + connect \dec31_dec_sub8_sv_in1 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + connect \dec31_dec_sub8_sv_in2 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + connect \dec31_dec_sub8_sv_in3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + connect \dec31_dec_sub8_sv_out \dec31_dec_sub8_dec31_dec_sub8_sv_out + connect \dec31_dec_sub8_sv_out2 \dec31_dec_sub8_dec31_dec_sub8_sv_out2 + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:88406.18-88441.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_sv_cr_in \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + connect \dec31_dec_sub9_sv_cr_out \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + connect \dec31_dec_sub9_sv_in1 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + connect \dec31_dec_sub9_sv_in2 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + connect \dec31_dec_sub9_sv_in3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + connect \dec31_dec_sub9_sv_out \dec31_dec_sub9_dec31_dec_sub9_sv_out + connect \dec31_dec_sub9_sv_out2 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:81828.7-81828.20" + process $proc$libresoc.v:81828$3850 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:88442.3-88502.6" + process $proc$libresoc.v:88442$3817 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] + attribute \src "libresoc.v:88443.5-88443.29" + switch \initial + attribute \src "libresoc.v:88443.9-88443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[13:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[13:0] + end + attribute \src "libresoc.v:88503.3-88563.6" + process $proc$libresoc.v:88503$3818 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:88504.5-88504.29" + switch \initial + attribute \src "libresoc.v:88504.9-88504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "libresoc.v:88564.3-88624.6" + process $proc$libresoc.v:88564$3819 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:88565.5-88565.29" + switch \initial + attribute \src "libresoc.v:88565.9-88565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "libresoc.v:88625.3-88685.6" + process $proc$libresoc.v:88625$3820 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:88626.5-88626.29" + switch \initial + attribute \src "libresoc.v:88626.9-88626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "libresoc.v:88686.3-88746.6" + process $proc$libresoc.v:88686$3821 + assign { } { } + assign { } { } + assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:88687.5-88687.29" + switch \initial + attribute \src "libresoc.v:88687.9-88687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + case + assign $1\dec31_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] + end + attribute \src "libresoc.v:88747.3-88807.6" + process $proc$libresoc.v:88747$3822 + assign { } { } + assign { } { } + assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:88748.5-88748.29" + switch \initial + attribute \src "libresoc.v:88748.9-88748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype + case + assign $1\dec31_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] + end + attribute \src "libresoc.v:88808.3-88868.6" + process $proc$libresoc.v:88808$3823 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:88809.5-88809.29" + switch \initial + attribute \src "libresoc.v:88809.9-88809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:88869.3-88929.6" + process $proc$libresoc.v:88869$3824 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:88870.5-88870.29" + switch \initial + attribute \src "libresoc.v:88870.9-88870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:88930.3-88990.6" + process $proc$libresoc.v:88930$3825 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:88931.5-88931.29" + switch \initial + attribute \src "libresoc.v:88931.9-88931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "libresoc.v:88991.3-89051.6" + process $proc$libresoc.v:88991$3826 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] + attribute \src "libresoc.v:88992.5-88992.29" + switch \initial + attribute \src "libresoc.v:88992.9-88992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[2:0] 3'000 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[2:0] + end + attribute \src "libresoc.v:89052.3-89112.6" + process $proc$libresoc.v:89052$3827 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:89053.5-89053.29" + switch \initial + attribute \src "libresoc.v:89053.9-89053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "libresoc.v:89113.3-89173.6" + process $proc$libresoc.v:89113$3828 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:89114.5-89114.29" + switch \initial + attribute \src "libresoc.v:89114.9-89114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "libresoc.v:89174.3-89234.6" + process $proc$libresoc.v:89174$3829 + assign { } { } + assign { } { } + assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] + attribute \src "libresoc.v:89175.5-89175.29" + switch \initial + attribute \src "libresoc.v:89175.9-89175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + case + assign $1\dec31_sv_in1[2:0] 3'000 + end + sync always + update \dec31_sv_in1 $0\dec31_sv_in1[2:0] + end + attribute \src "libresoc.v:89235.3-89295.6" + process $proc$libresoc.v:89235$3830 + assign { } { } + assign { } { } + assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] + attribute \src "libresoc.v:89236.5-89236.29" + switch \initial + attribute \src "libresoc.v:89236.9-89236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + case + assign $1\dec31_sv_in2[2:0] 3'000 + end + sync always + update \dec31_sv_in2 $0\dec31_sv_in2[2:0] + end + attribute \src "libresoc.v:89296.3-89356.6" + process $proc$libresoc.v:89296$3831 + assign { } { } + assign { } { } + assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] + attribute \src "libresoc.v:89297.5-89297.29" + switch \initial + attribute \src "libresoc.v:89297.9-89297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + case + assign $1\dec31_sv_in3[2:0] 3'000 + end + sync always + update \dec31_sv_in3 $0\dec31_sv_in3[2:0] + end + attribute \src "libresoc.v:89357.3-89417.6" + process $proc$libresoc.v:89357$3832 + assign { } { } + assign { } { } + assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] + attribute \src "libresoc.v:89358.5-89358.29" + switch \initial + attribute \src "libresoc.v:89358.9-89358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out + case + assign $1\dec31_sv_out[2:0] 3'000 + end + sync always + update \dec31_sv_out $0\dec31_sv_out[2:0] + end + attribute \src "libresoc.v:89418.3-89478.6" + process $proc$libresoc.v:89418$3833 + assign { } { } + assign { } { } + assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89419.5-89419.29" + switch \initial + attribute \src "libresoc.v:89419.9-89419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out2 + case + assign $1\dec31_sv_out2[2:0] 3'000 + end + sync always + update \dec31_sv_out2 $0\dec31_sv_out2[2:0] + end + attribute \src "libresoc.v:89479.3-89539.6" + process $proc$libresoc.v:89479$3834 + assign { } { } + assign { } { } + assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:89480.5-89480.29" + switch \initial + attribute \src "libresoc.v:89480.9-89480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + case + assign $1\dec31_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] + end + attribute \src "libresoc.v:89540.3-89600.6" + process $proc$libresoc.v:89540$3835 + assign { } { } + assign { } { } + assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:89541.5-89541.29" + switch \initial + attribute \src "libresoc.v:89541.9-89541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + case + assign $1\dec31_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] + end + attribute \src "libresoc.v:89601.3-89661.6" + process $proc$libresoc.v:89601$3836 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:89602.5-89602.29" + switch \initial + attribute \src "libresoc.v:89602.9-89602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:89662.3-89722.6" + process $proc$libresoc.v:89662$3837 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:89663.5-89663.29" + switch \initial + attribute \src "libresoc.v:89663.9-89663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "libresoc.v:89723.3-89783.6" + process $proc$libresoc.v:89723$3838 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:89724.5-89724.29" + switch \initial + attribute \src "libresoc.v:89724.9-89724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:89784.3-89844.6" + process $proc$libresoc.v:89784$3839 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:89785.5-89785.29" + switch \initial + attribute \src "libresoc.v:89785.9-89785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "libresoc.v:89845.3-89905.6" + process $proc$libresoc.v:89845$3840 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:89846.5-89846.29" + switch \initial + attribute \src "libresoc.v:89846.9-89846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "libresoc.v:89906.3-89966.6" + process $proc$libresoc.v:89906$3841 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:89907.5-89907.29" + switch \initial + attribute \src "libresoc.v:89907.9-89907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "libresoc.v:89967.3-90027.6" + process $proc$libresoc.v:89967$3842 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:89968.5-89968.29" + switch \initial + attribute \src "libresoc.v:89968.9-89968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "libresoc.v:90028.3-90088.6" + process $proc$libresoc.v:90028$3843 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:90029.5-90029.29" + switch \initial + attribute \src "libresoc.v:90029.9-90029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "libresoc.v:90089.3-90149.6" + process $proc$libresoc.v:90089$3844 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:90090.5-90090.29" + switch \initial + attribute \src "libresoc.v:90090.9-90090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:90150.3-90210.6" + process $proc$libresoc.v:90150$3845 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:90151.5-90151.29" + switch \initial + attribute \src "libresoc.v:90151.9-90151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "libresoc.v:90211.3-90271.6" + process $proc$libresoc.v:90211$3846 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:90212.5-90212.29" + switch \initial + attribute \src "libresoc.v:90212.9-90212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "libresoc.v:90272.3-90332.6" + process $proc$libresoc.v:90272$3847 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:90273.5-90273.29" + switch \initial + attribute \src "libresoc.v:90273.9-90273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "libresoc.v:90333.3-90393.6" + process $proc$libresoc.v:90333$3848 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:90334.5-90334.29" + switch \initial + attribute \src "libresoc.v:90334.9-90334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "libresoc.v:90394.3-90454.6" + process $proc$libresoc.v:90394$3849 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:90395.5-90395.29" + switch \initial + attribute \src "libresoc.v:90395.9-90395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:90479.1-91456.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:91341.3-91359.6" + wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:91360.3-91378.6" + wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:91113.3-91131.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:91189.3-91207.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:90847.3-90865.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:90866.3-90884.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:91094.3-91112.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:91170.3-91188.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:91246.3-91264.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:90828.3-90846.6" + wire width 14 $0\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:91379.3-91397.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:91398.3-91416.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:91417.3-91435.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:91037.3-91055.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:91132.3-91150.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:91151.3-91169.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:91265.3-91283.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:91018.3-91036.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:91303.3-91321.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:91436.3-91454.6" + wire width 3 $0\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:91075.3-91093.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:91227.3-91245.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:91322.3-91340.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:91284.3-91302.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:91208.3-91226.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:90980.3-90998.6" + wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:90999.3-91017.6" + wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:90885.3-90903.6" + wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:90904.3-90922.6" + wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:90923.3-90941.6" + wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:90961.3-90979.6" + wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90942.3-90960.6" + wire width 3 $0\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:91056.3-91074.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:90480.7-90480.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:91341.3-91359.6" + wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:91360.3-91378.6" + wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:91113.3-91131.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:91189.3-91207.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:90847.3-90865.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:90866.3-90884.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:91094.3-91112.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:91170.3-91188.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:91246.3-91264.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:90828.3-90846.6" + wire width 14 $1\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:91379.3-91397.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:91398.3-91416.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:91417.3-91435.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:91037.3-91055.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:91132.3-91150.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:91151.3-91169.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:91265.3-91283.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:91018.3-91036.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:91303.3-91321.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:91436.3-91454.6" + wire width 3 $1\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:91075.3-91093.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:91227.3-91245.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:91322.3-91340.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:91284.3-91302.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:91208.3-91226.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:90980.3-90998.6" + wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:90999.3-91017.6" + wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:90885.3-90903.6" + wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:90904.3-90922.6" + wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:90923.3-90941.6" + wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:90961.3-90979.6" + wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90942.3-90960.6" + wire width 3 $1\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:91056.3-91074.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub0_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub0_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub0_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub0_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub0_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub0_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub0_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub0_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub0_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub0_upd + attribute \src "libresoc.v:90480.7-90480.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:90480.7-90480.20" + process $proc$libresoc.v:90480$3884 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:90828.3-90846.6" + process $proc$libresoc.v:90828$3851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90829.5-90829.29" + switch \initial + attribute \src "libresoc.v:90829.9-90829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000001000000 + case + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] + end + attribute \src "libresoc.v:90847.3-90865.6" + process $proc$libresoc.v:90847$3852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:90848.5-90848.29" + switch \initial + attribute \src "libresoc.v:90848.9-90848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:90866.3-90884.6" + process $proc$libresoc.v:90866$3853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:90867.5-90867.29" + switch \initial + attribute \src "libresoc.v:90867.9-90867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:90885.3-90903.6" + process $proc$libresoc.v:90885$3854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:90886.5-90886.29" + switch \initial + attribute \src "libresoc.v:90886.9-90886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] + end + attribute \src "libresoc.v:90904.3-90922.6" + process $proc$libresoc.v:90904$3855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:90905.5-90905.29" + switch \initial + attribute \src "libresoc.v:90905.9-90905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] + end + attribute \src "libresoc.v:90923.3-90941.6" + process $proc$libresoc.v:90923$3856 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:90924.5-90924.29" + switch \initial + attribute \src "libresoc.v:90924.9-90924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] + end + attribute \src "libresoc.v:90942.3-90960.6" + process $proc$libresoc.v:90942$3857 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:90943.5-90943.29" + switch \initial + attribute \src "libresoc.v:90943.9-90943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] + end + attribute \src "libresoc.v:90961.3-90979.6" + process $proc$libresoc.v:90961$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90962.5-90962.29" + switch \initial + attribute \src "libresoc.v:90962.9-90962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] + end + attribute \src "libresoc.v:90980.3-90998.6" + process $proc$libresoc.v:90980$3859 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:90981.5-90981.29" + switch \initial + attribute \src "libresoc.v:90981.9-90981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'010 + case + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] + end + attribute \src "libresoc.v:90999.3-91017.6" + process $proc$libresoc.v:90999$3860 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:91000.5-91000.29" + switch \initial + attribute \src "libresoc.v:91000.9-91000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] + end + attribute \src "libresoc.v:91018.3-91036.6" + process $proc$libresoc.v:91018$3861 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:91019.5-91019.29" + switch \initial + attribute \src "libresoc.v:91019.9-91019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:91037.3-91055.6" + process $proc$libresoc.v:91037$3862 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:91038.5-91038.29" + switch \initial + attribute \src "libresoc.v:91038.9-91038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:91056.3-91074.6" + process $proc$libresoc.v:91056$3863 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:91057.5-91057.29" + switch \initial + attribute \src "libresoc.v:91057.9-91057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "libresoc.v:91075.3-91093.6" + process $proc$libresoc.v:91075$3864 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:91076.5-91076.29" + switch \initial + attribute \src "libresoc.v:91076.9-91076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:91094.3-91112.6" + process $proc$libresoc.v:91094$3865 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:91095.5-91095.29" + switch \initial + attribute \src "libresoc.v:91095.9-91095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:91113.3-91131.6" + process $proc$libresoc.v:91113$3866 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:91114.5-91114.29" + switch \initial + attribute \src "libresoc.v:91114.9-91114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:91132.3-91150.6" + process $proc$libresoc.v:91132$3867 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:91133.5-91133.29" + switch \initial + attribute \src "libresoc.v:91133.9-91133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:91151.3-91169.6" + process $proc$libresoc.v:91151$3868 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:91152.5-91152.29" + switch \initial + attribute \src "libresoc.v:91152.9-91152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:91170.3-91188.6" + process $proc$libresoc.v:91170$3869 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:91171.5-91171.29" + switch \initial + attribute \src "libresoc.v:91171.9-91171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:91189.3-91207.6" + process $proc$libresoc.v:91189$3870 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:91190.5-91190.29" + switch \initial + attribute \src "libresoc.v:91190.9-91190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:91208.3-91226.6" + process $proc$libresoc.v:91208$3871 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:91209.5-91209.29" + switch \initial + attribute \src "libresoc.v:91209.9-91209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:91227.3-91245.6" + process $proc$libresoc.v:91227$3872 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:91228.5-91228.29" + switch \initial + attribute \src "libresoc.v:91228.9-91228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:91246.3-91264.6" + process $proc$libresoc.v:91246$3873 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:91247.5-91247.29" + switch \initial + attribute \src "libresoc.v:91247.9-91247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:91265.3-91283.6" + process $proc$libresoc.v:91265$3874 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:91266.5-91266.29" + switch \initial + attribute \src "libresoc.v:91266.9-91266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:91284.3-91302.6" + process $proc$libresoc.v:91284$3875 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:91285.5-91285.29" + switch \initial + attribute \src "libresoc.v:91285.9-91285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:91303.3-91321.6" + process $proc$libresoc.v:91303$3876 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:91304.5-91304.29" + switch \initial + attribute \src "libresoc.v:91304.9-91304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:91322.3-91340.6" + process $proc$libresoc.v:91322$3877 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:91323.5-91323.29" + switch \initial + attribute \src "libresoc.v:91323.9-91323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:91341.3-91359.6" + process $proc$libresoc.v:91341$3878 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:91342.5-91342.29" + switch \initial + attribute \src "libresoc.v:91342.9-91342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] + end + attribute \src "libresoc.v:91360.3-91378.6" + process $proc$libresoc.v:91360$3879 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:91361.5-91361.29" + switch \initial + attribute \src "libresoc.v:91361.9-91361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] + end + attribute \src "libresoc.v:91379.3-91397.6" + process $proc$libresoc.v:91379$3880 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:91380.5-91380.29" + switch \initial + attribute \src "libresoc.v:91380.9-91380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:91398.3-91416.6" + process $proc$libresoc.v:91398$3881 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:91399.5-91399.29" + switch \initial + attribute \src "libresoc.v:91399.9-91399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:91417.3-91435.6" + process $proc$libresoc.v:91417$3882 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:91418.5-91418.29" + switch \initial + attribute \src "libresoc.v:91418.9-91418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:91436.3-91454.6" + process $proc$libresoc.v:91436$3883 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:91437.5-91437.29" + switch \initial + attribute \src "libresoc.v:91437.9-91437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:91460.1-93031.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "libresoc.v:92808.3-92844.6" + wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:92845.3-92881.6" + wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:92364.3-92400.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:92512.3-92548.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:91846.3-91882.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:91883.3-91919.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:92327.3-92363.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:92475.3-92511.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:92623.3-92659.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:91809.3-91845.6" + wire width 14 $0\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:92882.3-92918.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:92919.3-92955.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:92956.3-92992.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:92216.3-92252.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:92401.3-92437.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:92438.3-92474.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:92660.3-92696.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:92179.3-92215.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:92734.3-92770.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:92993.3-93029.6" + wire width 3 $0\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:92290.3-92326.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:92586.3-92622.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:92771.3-92807.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:92697.3-92733.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:92549.3-92585.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:92105.3-92141.6" + wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:92142.3-92178.6" + wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:91920.3-91956.6" + wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:91957.3-91993.6" + wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:91994.3-92030.6" + wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:92068.3-92104.6" + wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92031.3-92067.6" + wire width 3 $0\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:92253.3-92289.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:91461.7-91461.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:92808.3-92844.6" + wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:92845.3-92881.6" + wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:92364.3-92400.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:92512.3-92548.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:91846.3-91882.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:91883.3-91919.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:92327.3-92363.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:92475.3-92511.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:92623.3-92659.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:91809.3-91845.6" + wire width 14 $1\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:92882.3-92918.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:92919.3-92955.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:92956.3-92992.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:92216.3-92252.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:92401.3-92437.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:92438.3-92474.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:92660.3-92696.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:92179.3-92215.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:92734.3-92770.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:92993.3-93029.6" + wire width 3 $1\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:92290.3-92326.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:92586.3-92622.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:92771.3-92807.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:92697.3-92733.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:92549.3-92585.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:92105.3-92141.6" + wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:92142.3-92178.6" + wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:91920.3-91956.6" + wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:91957.3-91993.6" + wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:91994.3-92030.6" + wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:92068.3-92104.6" + wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92031.3-92067.6" + wire width 3 $1\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:92253.3-92289.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub10_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub10_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub10_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub10_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub10_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub10_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub10_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub10_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub10_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub10_upd + attribute \src "libresoc.v:91461.7-91461.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:91461.7-91461.20" + process $proc$libresoc.v:91461$3918 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:91809.3-91845.6" + process $proc$libresoc.v:91809$3885 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:91810.5-91810.29" + switch \initial + attribute \src "libresoc.v:91810.9-91810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 + case + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] + end + attribute \src "libresoc.v:91846.3-91882.6" + process $proc$libresoc.v:91846$3886 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:91847.5-91847.29" + switch \initial + attribute \src "libresoc.v:91847.9-91847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:91883.3-91919.6" + process $proc$libresoc.v:91883$3887 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:91884.5-91884.29" + switch \initial + attribute \src "libresoc.v:91884.9-91884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + attribute \src "libresoc.v:91920.3-91956.6" + process $proc$libresoc.v:91920$3888 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:91921.5-91921.29" + switch \initial + attribute \src "libresoc.v:91921.9-91921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] + end + attribute \src "libresoc.v:91957.3-91993.6" + process $proc$libresoc.v:91957$3889 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:91958.5-91958.29" + switch \initial + attribute \src "libresoc.v:91958.9-91958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] + end + attribute \src "libresoc.v:91994.3-92030.6" + process $proc$libresoc.v:91994$3890 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:91995.5-91995.29" + switch \initial + attribute \src "libresoc.v:91995.9-91995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] + end + attribute \src "libresoc.v:92031.3-92067.6" + process $proc$libresoc.v:92031$3891 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:92032.5-92032.29" + switch \initial + attribute \src "libresoc.v:92032.9-92032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] + end + attribute \src "libresoc.v:92068.3-92104.6" + process $proc$libresoc.v:92068$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92069.5-92069.29" + switch \initial + attribute \src "libresoc.v:92069.9-92069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] + end + attribute \src "libresoc.v:92105.3-92141.6" + process $proc$libresoc.v:92105$3893 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:92106.5-92106.29" + switch \initial + attribute \src "libresoc.v:92106.9-92106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] + end + attribute \src "libresoc.v:92142.3-92178.6" + process $proc$libresoc.v:92142$3894 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:92143.5-92143.29" + switch \initial + attribute \src "libresoc.v:92143.9-92143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] + end + attribute \src "libresoc.v:92179.3-92215.6" + process $proc$libresoc.v:92179$3895 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:92180.5-92180.29" + switch \initial + attribute \src "libresoc.v:92180.9-92180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:92216.3-92252.6" + process $proc$libresoc.v:92216$3896 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:92217.5-92217.29" + switch \initial + attribute \src "libresoc.v:92217.9-92217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:92253.3-92289.6" + process $proc$libresoc.v:92253$3897 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:92254.5-92254.29" + switch \initial + attribute \src "libresoc.v:92254.9-92254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + end + attribute \src "libresoc.v:92290.3-92326.6" + process $proc$libresoc.v:92290$3898 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:92291.5-92291.29" + switch \initial + attribute \src "libresoc.v:92291.9-92291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:92327.3-92363.6" + process $proc$libresoc.v:92327$3899 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:92328.5-92328.29" + switch \initial + attribute \src "libresoc.v:92328.9-92328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "libresoc.v:92364.3-92400.6" + process $proc$libresoc.v:92364$3900 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:92365.5-92365.29" + switch \initial + attribute \src "libresoc.v:92365.9-92365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "libresoc.v:92401.3-92437.6" + process $proc$libresoc.v:92401$3901 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:92402.5-92402.29" + switch \initial + attribute \src "libresoc.v:92402.9-92402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:92438.3-92474.6" + process $proc$libresoc.v:92438$3902 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:92439.5-92439.29" + switch \initial + attribute \src "libresoc.v:92439.9-92439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:92475.3-92511.6" + process $proc$libresoc.v:92475$3903 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:92476.5-92476.29" + switch \initial + attribute \src "libresoc.v:92476.9-92476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:92512.3-92548.6" + process $proc$libresoc.v:92512$3904 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:92513.5-92513.29" + switch \initial + attribute \src "libresoc.v:92513.9-92513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:92549.3-92585.6" + process $proc$libresoc.v:92549$3905 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:92550.5-92550.29" + switch \initial + attribute \src "libresoc.v:92550.9-92550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:92586.3-92622.6" + process $proc$libresoc.v:92586$3906 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:92587.5-92587.29" + switch \initial + attribute \src "libresoc.v:92587.9-92587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "libresoc.v:92623.3-92659.6" + process $proc$libresoc.v:92623$3907 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:92624.5-92624.29" + switch \initial + attribute \src "libresoc.v:92624.9-92624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + end + attribute \src "libresoc.v:92660.3-92696.6" + process $proc$libresoc.v:92660$3908 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:92661.5-92661.29" + switch \initial + attribute \src "libresoc.v:92661.9-92661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:92697.3-92733.6" + process $proc$libresoc.v:92697$3909 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:92698.5-92698.29" + switch \initial + attribute \src "libresoc.v:92698.9-92698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:92734.3-92770.6" + process $proc$libresoc.v:92734$3910 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:92735.5-92735.29" + switch \initial + attribute \src "libresoc.v:92735.9-92735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + end + attribute \src "libresoc.v:92771.3-92807.6" + process $proc$libresoc.v:92771$3911 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:92772.5-92772.29" + switch \initial + attribute \src "libresoc.v:92772.9-92772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + end + attribute \src "libresoc.v:92808.3-92844.6" + process $proc$libresoc.v:92808$3912 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:92809.5-92809.29" + switch \initial + attribute \src "libresoc.v:92809.9-92809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] + end + attribute \src "libresoc.v:92845.3-92881.6" + process $proc$libresoc.v:92845$3913 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:92846.5-92846.29" + switch \initial + attribute \src "libresoc.v:92846.9-92846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] + end + attribute \src "libresoc.v:92882.3-92918.6" + process $proc$libresoc.v:92882$3914 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:92883.5-92883.29" + switch \initial + attribute \src "libresoc.v:92883.9-92883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:92919.3-92955.6" + process $proc$libresoc.v:92919$3915 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:92920.5-92920.29" + switch \initial + attribute \src "libresoc.v:92920.9-92920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:92956.3-92992.6" + process $proc$libresoc.v:92956$3916 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:92957.5-92957.29" + switch \initial + attribute \src "libresoc.v:92957.9-92957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + end + attribute \src "libresoc.v:92993.3-93029.6" + process $proc$libresoc.v:92993$3917 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:92994.5-92994.29" + switch \initial + attribute \src "libresoc.v:92994.9-92994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:93035.1-95200.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "libresoc.v:94869.3-94923.6" + wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:94924.3-94978.6" + wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:94209.3-94263.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:94429.3-94483.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:93439.3-93493.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:93494.3-93548.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:94154.3-94208.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:94374.3-94428.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:94594.3-94648.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:93384.3-93438.6" + wire width 14 $0\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:94979.3-95033.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:95034.3-95088.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:95089.3-95143.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:93989.3-94043.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:94264.3-94318.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:94319.3-94373.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:94649.3-94703.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:93934.3-93988.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:94759.3-94813.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:95144.3-95198.6" + wire width 3 $0\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:94099.3-94153.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:94539.3-94593.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:94814.3-94868.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:94704.3-94758.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:94484.3-94538.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:93824.3-93878.6" + wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:93879.3-93933.6" + wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:93549.3-93603.6" + wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:93604.3-93658.6" + wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:93659.3-93713.6" + wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:93769.3-93823.6" + wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93714.3-93768.6" + wire width 3 $0\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:94044.3-94098.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:93036.7-93036.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:94869.3-94923.6" + wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:94924.3-94978.6" + wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:94209.3-94263.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:94429.3-94483.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:93439.3-93493.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:93494.3-93548.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:94154.3-94208.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:94374.3-94428.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:94594.3-94648.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:93384.3-93438.6" + wire width 14 $1\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:94979.3-95033.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:95034.3-95088.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:95089.3-95143.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:93989.3-94043.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:94264.3-94318.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:94319.3-94373.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:94649.3-94703.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:93934.3-93988.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:94759.3-94813.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:95144.3-95198.6" + wire width 3 $1\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:94099.3-94153.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:94539.3-94593.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:94814.3-94868.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:94704.3-94758.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:94484.3-94538.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:93824.3-93878.6" + wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:93879.3-93933.6" + wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:93549.3-93603.6" + wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:93604.3-93658.6" + wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:93659.3-93713.6" + wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:93769.3-93823.6" + wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93714.3-93768.6" + wire width 3 $1\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:94044.3-94098.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub11_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub11_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub11_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub11_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub11_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub11_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub11_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub11_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub11_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub11_upd + attribute \src "libresoc.v:93036.7-93036.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:93036.7-93036.20" + process $proc$libresoc.v:93036$3952 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:93384.3-93438.6" + process $proc$libresoc.v:93384$3919 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:93385.5-93385.29" + switch \initial + attribute \src "libresoc.v:93385.9-93385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 + case + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] + end + attribute \src "libresoc.v:93439.3-93493.6" + process $proc$libresoc.v:93439$3920 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:93440.5-93440.29" + switch \initial + attribute \src "libresoc.v:93440.9-93440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:93494.3-93548.6" + process $proc$libresoc.v:93494$3921 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:93495.5-93495.29" + switch \initial + attribute \src "libresoc.v:93495.9-93495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:93549.3-93603.6" + process $proc$libresoc.v:93549$3922 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:93550.5-93550.29" + switch \initial + attribute \src "libresoc.v:93550.9-93550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] + end + attribute \src "libresoc.v:93604.3-93658.6" + process $proc$libresoc.v:93604$3923 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:93605.5-93605.29" + switch \initial + attribute \src "libresoc.v:93605.9-93605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] + end + attribute \src "libresoc.v:93659.3-93713.6" + process $proc$libresoc.v:93659$3924 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:93660.5-93660.29" + switch \initial + attribute \src "libresoc.v:93660.9-93660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] + end + attribute \src "libresoc.v:93714.3-93768.6" + process $proc$libresoc.v:93714$3925 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:93715.5-93715.29" + switch \initial + attribute \src "libresoc.v:93715.9-93715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] + end + attribute \src "libresoc.v:93769.3-93823.6" + process $proc$libresoc.v:93769$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93770.5-93770.29" + switch \initial + attribute \src "libresoc.v:93770.9-93770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] + end + attribute \src "libresoc.v:93824.3-93878.6" + process $proc$libresoc.v:93824$3927 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:93825.5-93825.29" + switch \initial + attribute \src "libresoc.v:93825.9-93825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] + end + attribute \src "libresoc.v:93879.3-93933.6" + process $proc$libresoc.v:93879$3928 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:93880.5-93880.29" + switch \initial + attribute \src "libresoc.v:93880.9-93880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] + end + attribute \src "libresoc.v:93934.3-93988.6" + process $proc$libresoc.v:93934$3929 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:93935.5-93935.29" + switch \initial + attribute \src "libresoc.v:93935.9-93935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:93989.3-94043.6" + process $proc$libresoc.v:93989$3930 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:93990.5-93990.29" + switch \initial + attribute \src "libresoc.v:93990.9-93990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:94044.3-94098.6" + process $proc$libresoc.v:94044$3931 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:94045.5-94045.29" + switch \initial + attribute \src "libresoc.v:94045.9-94045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + end + attribute \src "libresoc.v:94099.3-94153.6" + process $proc$libresoc.v:94099$3932 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:94100.5-94100.29" + switch \initial + attribute \src "libresoc.v:94100.9-94100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:94154.3-94208.6" + process $proc$libresoc.v:94154$3933 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:94155.5-94155.29" + switch \initial + attribute \src "libresoc.v:94155.9-94155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + end + attribute \src "libresoc.v:94209.3-94263.6" + process $proc$libresoc.v:94209$3934 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:94210.5-94210.29" + switch \initial + attribute \src "libresoc.v:94210.9-94210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + end + attribute \src "libresoc.v:94264.3-94318.6" + process $proc$libresoc.v:94264$3935 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:94265.5-94265.29" + switch \initial + attribute \src "libresoc.v:94265.9-94265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:94319.3-94373.6" + process $proc$libresoc.v:94319$3936 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:94320.5-94320.29" + switch \initial + attribute \src "libresoc.v:94320.9-94320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:94374.3-94428.6" + process $proc$libresoc.v:94374$3937 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:94375.5-94375.29" + switch \initial + attribute \src "libresoc.v:94375.9-94375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:94429.3-94483.6" + process $proc$libresoc.v:94429$3938 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:94430.5-94430.29" + switch \initial + attribute \src "libresoc.v:94430.9-94430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "libresoc.v:94484.3-94538.6" + process $proc$libresoc.v:94484$3939 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:94485.5-94485.29" + switch \initial + attribute \src "libresoc.v:94485.9-94485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "libresoc.v:94539.3-94593.6" + process $proc$libresoc.v:94539$3940 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:94540.5-94540.29" + switch \initial + attribute \src "libresoc.v:94540.9-94540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "libresoc.v:94594.3-94648.6" + process $proc$libresoc.v:94594$3941 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:94595.5-94595.29" + switch \initial + attribute \src "libresoc.v:94595.9-94595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + end + attribute \src "libresoc.v:94649.3-94703.6" + process $proc$libresoc.v:94649$3942 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:94650.5-94650.29" + switch \initial + attribute \src "libresoc.v:94650.9-94650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:94704.3-94758.6" + process $proc$libresoc.v:94704$3943 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:94705.5-94705.29" + switch \initial + attribute \src "libresoc.v:94705.9-94705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:94759.3-94813.6" + process $proc$libresoc.v:94759$3944 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:94760.5-94760.29" + switch \initial + attribute \src "libresoc.v:94760.9-94760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + end + attribute \src "libresoc.v:94814.3-94868.6" + process $proc$libresoc.v:94814$3945 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:94815.5-94815.29" + switch \initial + attribute \src "libresoc.v:94815.9-94815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + end + attribute \src "libresoc.v:94869.3-94923.6" + process $proc$libresoc.v:94869$3946 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:94870.5-94870.29" + switch \initial + attribute \src "libresoc.v:94870.9-94870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] + end + attribute \src "libresoc.v:94924.3-94978.6" + process $proc$libresoc.v:94924$3947 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:94925.5-94925.29" + switch \initial + attribute \src "libresoc.v:94925.9-94925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] + end + attribute \src "libresoc.v:94979.3-95033.6" + process $proc$libresoc.v:94979$3948 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:94980.5-94980.29" + switch \initial + attribute \src "libresoc.v:94980.9-94980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:95034.3-95088.6" + process $proc$libresoc.v:95034$3949 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:95035.5-95035.29" + switch \initial + attribute \src "libresoc.v:95035.9-95035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:95089.3-95143.6" + process $proc$libresoc.v:95089$3950 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:95090.5-95090.29" + switch \initial + attribute \src "libresoc.v:95090.9-95090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "libresoc.v:95144.3-95198.6" + process $proc$libresoc.v:95144$3951 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:95145.5-95145.29" + switch \initial + attribute \src "libresoc.v:95145.9-95145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:95204.1-98953.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "libresoc.v:98334.3-98436.6" + wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:98437.3-98539.6" + wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:97098.3-97200.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:97510.3-97612.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:95656.3-95758.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:95759.3-95861.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:96995.3-97097.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:97407.3-97509.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:97819.3-97921.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:95553.3-95655.6" + wire width 14 $0\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:98540.3-98642.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:98643.3-98745.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:98746.3-98848.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:96686.3-96788.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:97201.3-97303.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:97304.3-97406.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:97922.3-98024.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:96583.3-96685.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:98128.3-98230.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:98849.3-98951.6" + wire width 3 $0\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:96892.3-96994.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:97716.3-97818.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:98231.3-98333.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:98025.3-98127.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:97613.3-97715.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:96377.3-96479.6" + wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:96480.3-96582.6" + wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:95862.3-95964.6" + wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:95965.3-96067.6" + wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:96068.3-96170.6" + wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:96274.3-96376.6" + wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96171.3-96273.6" + wire width 3 $0\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:96789.3-96891.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:95205.7-95205.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:98334.3-98436.6" + wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:98437.3-98539.6" + wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:97098.3-97200.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:97510.3-97612.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:95656.3-95758.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:95759.3-95861.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:96995.3-97097.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:97407.3-97509.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:97819.3-97921.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:95553.3-95655.6" + wire width 14 $1\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:98540.3-98642.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:98643.3-98745.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:98746.3-98848.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:96686.3-96788.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:97201.3-97303.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:97304.3-97406.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:97922.3-98024.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:96583.3-96685.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:98128.3-98230.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:98849.3-98951.6" + wire width 3 $1\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:96892.3-96994.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:97716.3-97818.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:98231.3-98333.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:98025.3-98127.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:97613.3-97715.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:96377.3-96479.6" + wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:96480.3-96582.6" + wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:95862.3-95964.6" + wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:95965.3-96067.6" + wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:96068.3-96170.6" + wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:96274.3-96376.6" + wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96171.3-96273.6" + wire width 3 $1\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:96789.3-96891.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub15_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub15_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub15_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub15_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub15_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub15_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub15_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub15_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub15_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub15_upd + attribute \src "libresoc.v:95205.7-95205.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:95205.7-95205.20" + process $proc$libresoc.v:95205$3986 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:95553.3-95655.6" + process $proc$libresoc.v:95553$3953 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:95554.5-95554.29" + switch \initial + attribute \src "libresoc.v:95554.9-95554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 + case + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] + end + attribute \src "libresoc.v:95656.3-95758.6" + process $proc$libresoc.v:95656$3954 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:95657.5-95657.29" + switch \initial + attribute \src "libresoc.v:95657.9-95657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:95759.3-95861.6" + process $proc$libresoc.v:95759$3955 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:95760.5-95760.29" + switch \initial + attribute \src "libresoc.v:95760.9-95760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + attribute \src "libresoc.v:95862.3-95964.6" + process $proc$libresoc.v:95862$3956 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:95863.5-95863.29" + switch \initial + attribute \src "libresoc.v:95863.9-95863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] + end + attribute \src "libresoc.v:95965.3-96067.6" + process $proc$libresoc.v:95965$3957 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:95966.5-95966.29" + switch \initial + attribute \src "libresoc.v:95966.9-95966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] + end + attribute \src "libresoc.v:96068.3-96170.6" + process $proc$libresoc.v:96068$3958 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:96069.5-96069.29" + switch \initial + attribute \src "libresoc.v:96069.9-96069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] + end + attribute \src "libresoc.v:96171.3-96273.6" + process $proc$libresoc.v:96171$3959 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:96172.5-96172.29" + switch \initial + attribute \src "libresoc.v:96172.9-96172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub15_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] + end + attribute \src "libresoc.v:96274.3-96376.6" + process $proc$libresoc.v:96274$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96275.5-96275.29" + switch \initial + attribute \src "libresoc.v:96275.9-96275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] + end + attribute \src "libresoc.v:96377.3-96479.6" + process $proc$libresoc.v:96377$3961 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:96378.5-96378.29" + switch \initial + attribute \src "libresoc.v:96378.9-96378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + case + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] + end + attribute \src "libresoc.v:96480.3-96582.6" + process $proc$libresoc.v:96480$3962 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:96481.5-96481.29" + switch \initial + attribute \src "libresoc.v:96481.9-96481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] + end + attribute \src "libresoc.v:96583.3-96685.6" + process $proc$libresoc.v:96583$3963 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:96584.5-96584.29" + switch \initial + attribute \src "libresoc.v:96584.9-96584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + end + attribute \src "libresoc.v:96686.3-96788.6" + process $proc$libresoc.v:96686$3964 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:96687.5-96687.29" + switch \initial + attribute \src "libresoc.v:96687.9-96687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:96789.3-96891.6" + process $proc$libresoc.v:96789$3965 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:96790.5-96790.29" + switch \initial + attribute \src "libresoc.v:96790.9-96790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + end + attribute \src "libresoc.v:96892.3-96994.6" + process $proc$libresoc.v:96892$3966 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:96893.5-96893.29" + switch \initial + attribute \src "libresoc.v:96893.9-96893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "libresoc.v:96995.3-97097.6" + process $proc$libresoc.v:96995$3967 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:96996.5-96996.29" + switch \initial + attribute \src "libresoc.v:96996.9-96996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + end + attribute \src "libresoc.v:97098.3-97200.6" + process $proc$libresoc.v:97098$3968 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:97099.5-97099.29" + switch \initial + attribute \src "libresoc.v:97099.9-97099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + end + attribute \src "libresoc.v:97201.3-97303.6" + process $proc$libresoc.v:97201$3969 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:97202.5-97202.29" + switch \initial + attribute \src "libresoc.v:97202.9-97202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + end + attribute \src "libresoc.v:97304.3-97406.6" + process $proc$libresoc.v:97304$3970 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:97305.5-97305.29" + switch \initial + attribute \src "libresoc.v:97305.9-97305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + end + attribute \src "libresoc.v:97407.3-97509.6" + process $proc$libresoc.v:97407$3971 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:97408.5-97408.29" + switch \initial + attribute \src "libresoc.v:97408.9-97408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + end + attribute \src "libresoc.v:97510.3-97612.6" + process $proc$libresoc.v:97510$3972 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:97511.5-97511.29" + switch \initial + attribute \src "libresoc.v:97511.9-97511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + end + attribute \src "libresoc.v:97613.3-97715.6" + process $proc$libresoc.v:97613$3973 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:97614.5-97614.29" + switch \initial + attribute \src "libresoc.v:97614.9-97614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + end + attribute \src "libresoc.v:97716.3-97818.6" + process $proc$libresoc.v:97716$3974 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:97717.5-97717.29" + switch \initial + attribute \src "libresoc.v:97717.9-97717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + end + attribute \src "libresoc.v:97819.3-97921.6" + process $proc$libresoc.v:97819$3975 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:97820.5-97820.29" + switch \initial + attribute \src "libresoc.v:97820.9-97820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + end + attribute \src "libresoc.v:97922.3-98024.6" + process $proc$libresoc.v:97922$3976 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:97923.5-97923.29" + switch \initial + attribute \src "libresoc.v:97923.9-97923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + end + attribute \src "libresoc.v:98025.3-98127.6" + process $proc$libresoc.v:98025$3977 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:98026.5-98026.29" + switch \initial + attribute \src "libresoc.v:98026.9-98026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + end + attribute \src "libresoc.v:98128.3-98230.6" + process $proc$libresoc.v:98128$3978 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:98129.5-98129.29" + switch \initial + attribute \src "libresoc.v:98129.9-98129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + end + attribute \src "libresoc.v:98231.3-98333.6" + process $proc$libresoc.v:98231$3979 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:98232.5-98232.29" + switch \initial + attribute \src "libresoc.v:98232.9-98232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + end + attribute \src "libresoc.v:98334.3-98436.6" + process $proc$libresoc.v:98334$3980 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:98335.5-98335.29" + switch \initial + attribute \src "libresoc.v:98335.9-98335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] + end + attribute \src "libresoc.v:98437.3-98539.6" + process $proc$libresoc.v:98437$3981 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:98438.5-98438.29" + switch \initial + attribute \src "libresoc.v:98438.9-98438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] + end + attribute \src "libresoc.v:98540.3-98642.6" + process $proc$libresoc.v:98540$3982 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:98541.5-98541.29" + switch \initial + attribute \src "libresoc.v:98541.9-98541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + end + attribute \src "libresoc.v:98643.3-98745.6" + process $proc$libresoc.v:98643$3983 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:98644.5-98644.29" + switch \initial + attribute \src "libresoc.v:98644.9-98644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + end + attribute \src "libresoc.v:98746.3-98848.6" + process $proc$libresoc.v:98746$3984 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:98747.5-98747.29" + switch \initial + attribute \src "libresoc.v:98747.9-98747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "libresoc.v:98849.3-98951.6" + process $proc$libresoc.v:98849$3985 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:98850.5-98850.29" + switch \initial + attribute \src "libresoc.v:98850.9-98850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub15_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:98957.1-99637.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "libresoc.v:99576.3-99585.6" + wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:99586.3-99595.6" + wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:99456.3-99465.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:99496.3-99505.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:99316.3-99325.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:99326.3-99335.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:99446.3-99455.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:99486.3-99495.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:99526.3-99535.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:99306.3-99315.6" + wire width 14 $0\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:99596.3-99605.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:99606.3-99615.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:99616.3-99625.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:99416.3-99425.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:99466.3-99475.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:99476.3-99485.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:99536.3-99545.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:99406.3-99415.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:99556.3-99565.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:99626.3-99635.6" + wire width 3 $0\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:99436.3-99445.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:99516.3-99525.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:99566.3-99575.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:99546.3-99555.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:99506.3-99515.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:99386.3-99395.6" + wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:99396.3-99405.6" + wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:99336.3-99345.6" + wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:99346.3-99355.6" + wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:99356.3-99365.6" + wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:99376.3-99385.6" + wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99366.3-99375.6" + wire width 3 $0\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:99426.3-99435.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:98958.7-98958.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:99576.3-99585.6" + wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:99586.3-99595.6" + wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:99456.3-99465.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:99496.3-99505.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:99316.3-99325.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:99326.3-99335.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:99446.3-99455.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:99486.3-99495.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:99526.3-99535.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:99306.3-99315.6" + wire width 14 $1\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:99596.3-99605.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:99606.3-99615.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:99616.3-99625.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:99416.3-99425.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:99466.3-99475.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:99476.3-99485.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:99536.3-99545.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:99406.3-99415.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:99556.3-99565.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:99626.3-99635.6" + wire width 3 $1\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:99436.3-99445.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:99516.3-99525.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:99566.3-99575.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:99546.3-99555.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:99506.3-99515.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:99386.3-99395.6" + wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:99396.3-99405.6" + wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:99336.3-99345.6" + wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:99346.3-99355.6" + wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:99356.3-99365.6" + wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:99376.3-99385.6" + wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99366.3-99375.6" + wire width 3 $1\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:99426.3-99435.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub16_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub16_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub16_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub16_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub16_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub16_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub16_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub16_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub16_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub16_upd + attribute \src "libresoc.v:98958.7-98958.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:98958.7-98958.20" + process $proc$libresoc.v:98958$4020 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99306.3-99315.6" + process $proc$libresoc.v:99306$3987 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:99307.5-99307.29" + switch \initial + attribute \src "libresoc.v:99307.9-99307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000001000000 + case + assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] + end + attribute \src "libresoc.v:99316.3-99325.6" + process $proc$libresoc.v:99316$3988 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:99317.5-99317.29" + switch \initial + attribute \src "libresoc.v:99317.9-99317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:99326.3-99335.6" + process $proc$libresoc.v:99326$3989 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:99327.5-99327.29" + switch \initial + attribute \src "libresoc.v:99327.9-99327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + attribute \src "libresoc.v:99336.3-99345.6" + process $proc$libresoc.v:99336$3990 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:99337.5-99337.29" + switch \initial + attribute \src "libresoc.v:99337.9-99337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub16_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] + end + attribute \src "libresoc.v:99346.3-99355.6" + process $proc$libresoc.v:99346$3991 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:99347.5-99347.29" + switch \initial + attribute \src "libresoc.v:99347.9-99347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] + end + attribute \src "libresoc.v:99356.3-99365.6" + process $proc$libresoc.v:99356$3992 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:99357.5-99357.29" + switch \initial + attribute \src "libresoc.v:99357.9-99357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] + end + attribute \src "libresoc.v:99366.3-99375.6" + process $proc$libresoc.v:99366$3993 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:99367.5-99367.29" + switch \initial + attribute \src "libresoc.v:99367.9-99367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] + end + attribute \src "libresoc.v:99376.3-99385.6" + process $proc$libresoc.v:99376$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99377.5-99377.29" + switch \initial + attribute \src "libresoc.v:99377.9-99377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] + end + attribute \src "libresoc.v:99386.3-99395.6" + process $proc$libresoc.v:99386$3995 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:99387.5-99387.29" + switch \initial + attribute \src "libresoc.v:99387.9-99387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] + end + attribute \src "libresoc.v:99396.3-99405.6" + process $proc$libresoc.v:99396$3996 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:99397.5-99397.29" + switch \initial + attribute \src "libresoc.v:99397.9-99397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] + end + attribute \src "libresoc.v:99406.3-99415.6" + process $proc$libresoc.v:99406$3997 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:99407.5-99407.29" + switch \initial + attribute \src "libresoc.v:99407.9-99407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:99416.3-99425.6" + process $proc$libresoc.v:99416$3998 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:99417.5-99417.29" + switch \initial + attribute \src "libresoc.v:99417.9-99417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:99426.3-99435.6" + process $proc$libresoc.v:99426$3999 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:99427.5-99427.29" + switch \initial + attribute \src "libresoc.v:99427.9-99427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:99436.3-99445.6" + process $proc$libresoc.v:99436$4000 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:99437.5-99437.29" + switch \initial + attribute \src "libresoc.v:99437.9-99437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:99446.3-99455.6" + process $proc$libresoc.v:99446$4001 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:99447.5-99447.29" + switch \initial + attribute \src "libresoc.v:99447.9-99447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:99456.3-99465.6" + process $proc$libresoc.v:99456$4002 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:99457.5-99457.29" + switch \initial + attribute \src "libresoc.v:99457.9-99457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:99466.3-99475.6" + process $proc$libresoc.v:99466$4003 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:99467.5-99467.29" + switch \initial + attribute \src "libresoc.v:99467.9-99467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:99476.3-99485.6" + process $proc$libresoc.v:99476$4004 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:99477.5-99477.29" + switch \initial + attribute \src "libresoc.v:99477.9-99477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:99486.3-99495.6" + process $proc$libresoc.v:99486$4005 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:99487.5-99487.29" + switch \initial + attribute \src "libresoc.v:99487.9-99487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:99496.3-99505.6" + process $proc$libresoc.v:99496$4006 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:99497.5-99497.29" + switch \initial + attribute \src "libresoc.v:99497.9-99497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:99506.3-99515.6" + process $proc$libresoc.v:99506$4007 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:99507.5-99507.29" + switch \initial + attribute \src "libresoc.v:99507.9-99507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:99516.3-99525.6" + process $proc$libresoc.v:99516$4008 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:99517.5-99517.29" + switch \initial + attribute \src "libresoc.v:99517.9-99517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:99526.3-99535.6" + process $proc$libresoc.v:99526$4009 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:99527.5-99527.29" + switch \initial + attribute \src "libresoc.v:99527.9-99527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:99536.3-99545.6" + process $proc$libresoc.v:99536$4010 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:99537.5-99537.29" + switch \initial + attribute \src "libresoc.v:99537.9-99537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:99546.3-99555.6" + process $proc$libresoc.v:99546$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:99547.5-99547.29" + switch \initial + attribute \src "libresoc.v:99547.9-99547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:99556.3-99565.6" + process $proc$libresoc.v:99556$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:99557.5-99557.29" + switch \initial + attribute \src "libresoc.v:99557.9-99557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:99566.3-99575.6" + process $proc$libresoc.v:99566$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:99567.5-99567.29" + switch \initial + attribute \src "libresoc.v:99567.9-99567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:99576.3-99585.6" + process $proc$libresoc.v:99576$4014 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:99577.5-99577.29" + switch \initial + attribute \src "libresoc.v:99577.9-99577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] + end + attribute \src "libresoc.v:99586.3-99595.6" + process $proc$libresoc.v:99586$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:99587.5-99587.29" + switch \initial + attribute \src "libresoc.v:99587.9-99587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] + end + attribute \src "libresoc.v:99596.3-99605.6" + process $proc$libresoc.v:99596$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:99597.5-99597.29" + switch \initial + attribute \src "libresoc.v:99597.9-99597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:99606.3-99615.6" + process $proc$libresoc.v:99606$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:99607.5-99607.29" + switch \initial + attribute \src "libresoc.v:99607.9-99607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:99616.3-99625.6" + process $proc$libresoc.v:99616$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:99617.5-99617.29" + switch \initial + attribute \src "libresoc.v:99617.9-99617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:99626.3-99635.6" + process $proc$libresoc.v:99626$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:99627.5-99627.29" + switch \initial + attribute \src "libresoc.v:99627.9-99627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:99641.1-100717.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:100584.3-100605.6" + wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:100606.3-100627.6" + wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:100320.3-100341.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:100408.3-100429.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:100012.3-100033.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:100034.3-100055.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:100298.3-100319.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:100386.3-100407.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:100474.3-100495.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:99990.3-100011.6" + wire width 14 $0\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:100628.3-100649.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:100650.3-100671.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:100672.3-100693.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:100232.3-100253.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:100342.3-100363.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:100364.3-100385.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:100496.3-100517.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:100210.3-100231.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:100540.3-100561.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:100694.3-100715.6" + wire width 3 $0\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:100276.3-100297.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:100452.3-100473.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:100562.3-100583.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:100518.3-100539.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:100430.3-100451.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:100166.3-100187.6" + wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:100188.3-100209.6" + wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:100056.3-100077.6" + wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:100078.3-100099.6" + wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:100100.3-100121.6" + wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:100144.3-100165.6" + wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100122.3-100143.6" + wire width 3 $0\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:100254.3-100275.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:99642.7-99642.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:100584.3-100605.6" + wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:100606.3-100627.6" + wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:100320.3-100341.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:100408.3-100429.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:100012.3-100033.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:100034.3-100055.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:100298.3-100319.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:100386.3-100407.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:100474.3-100495.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:99990.3-100011.6" + wire width 14 $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:100628.3-100649.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:100650.3-100671.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:100672.3-100693.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:100232.3-100253.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:100342.3-100363.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:100364.3-100385.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:100496.3-100517.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:100210.3-100231.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:100540.3-100561.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:100694.3-100715.6" + wire width 3 $1\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:100276.3-100297.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:100452.3-100473.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:100562.3-100583.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:100518.3-100539.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:100430.3-100451.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:100166.3-100187.6" + wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:100188.3-100209.6" + wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:100056.3-100077.6" + wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:100078.3-100099.6" + wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:100100.3-100121.6" + wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:100144.3-100165.6" + wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100122.3-100143.6" + wire width 3 $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:100254.3-100275.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub18_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub18_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub18_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub18_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub18_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub18_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub18_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub18_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub18_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub18_upd + attribute \src "libresoc.v:99642.7-99642.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100012.3-100033.6" + process $proc$libresoc.v:100012$4022 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:100013.5-100013.29" + switch \initial + attribute \src "libresoc.v:100013.9-100013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:100034.3-100055.6" + process $proc$libresoc.v:100034$4023 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:100035.5-100035.29" + switch \initial + attribute \src "libresoc.v:100035.9-100035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + attribute \src "libresoc.v:100056.3-100077.6" + process $proc$libresoc.v:100056$4024 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:100057.5-100057.29" + switch \initial + attribute \src "libresoc.v:100057.9-100057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] + end + attribute \src "libresoc.v:100078.3-100099.6" + process $proc$libresoc.v:100078$4025 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:100079.5-100079.29" + switch \initial + attribute \src "libresoc.v:100079.9-100079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] + end + attribute \src "libresoc.v:100100.3-100121.6" + process $proc$libresoc.v:100100$4026 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:100101.5-100101.29" + switch \initial + attribute \src "libresoc.v:100101.9-100101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] + end + attribute \src "libresoc.v:100122.3-100143.6" + process $proc$libresoc.v:100122$4027 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:100123.5-100123.29" + switch \initial + attribute \src "libresoc.v:100123.9-100123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] + end + attribute \src "libresoc.v:100144.3-100165.6" + process $proc$libresoc.v:100144$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100145.5-100145.29" + switch \initial + attribute \src "libresoc.v:100145.9-100145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] + end + attribute \src "libresoc.v:100166.3-100187.6" + process $proc$libresoc.v:100166$4029 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:100167.5-100167.29" + switch \initial + attribute \src "libresoc.v:100167.9-100167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] + end + attribute \src "libresoc.v:100188.3-100209.6" + process $proc$libresoc.v:100188$4030 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:100189.5-100189.29" + switch \initial + attribute \src "libresoc.v:100189.9-100189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] + end + attribute \src "libresoc.v:100210.3-100231.6" + process $proc$libresoc.v:100210$4031 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:100211.5-100211.29" + switch \initial + attribute \src "libresoc.v:100211.9-100211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:100232.3-100253.6" + process $proc$libresoc.v:100232$4032 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:100233.5-100233.29" + switch \initial + attribute \src "libresoc.v:100233.9-100233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:100254.3-100275.6" + process $proc$libresoc.v:100254$4033 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:100255.5-100255.29" + switch \initial + attribute \src "libresoc.v:100255.9-100255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:100276.3-100297.6" + process $proc$libresoc.v:100276$4034 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:100277.5-100277.29" + switch \initial + attribute \src "libresoc.v:100277.9-100277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:100298.3-100319.6" + process $proc$libresoc.v:100298$4035 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:100299.5-100299.29" + switch \initial + attribute \src "libresoc.v:100299.9-100299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:100320.3-100341.6" + process $proc$libresoc.v:100320$4036 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:100321.5-100321.29" + switch \initial + attribute \src "libresoc.v:100321.9-100321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:100342.3-100363.6" + process $proc$libresoc.v:100342$4037 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:100343.5-100343.29" + switch \initial + attribute \src "libresoc.v:100343.9-100343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:100364.3-100385.6" + process $proc$libresoc.v:100364$4038 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:100365.5-100365.29" + switch \initial + attribute \src "libresoc.v:100365.9-100365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:100386.3-100407.6" + process $proc$libresoc.v:100386$4039 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:100387.5-100387.29" + switch \initial + attribute \src "libresoc.v:100387.9-100387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:100408.3-100429.6" + process $proc$libresoc.v:100408$4040 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:100409.5-100409.29" + switch \initial + attribute \src "libresoc.v:100409.9-100409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:100430.3-100451.6" + process $proc$libresoc.v:100430$4041 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:100431.5-100431.29" + switch \initial + attribute \src "libresoc.v:100431.9-100431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:100452.3-100473.6" + process $proc$libresoc.v:100452$4042 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:100453.5-100453.29" + switch \initial + attribute \src "libresoc.v:100453.9-100453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:100474.3-100495.6" + process $proc$libresoc.v:100474$4043 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:100475.5-100475.29" + switch \initial + attribute \src "libresoc.v:100475.9-100475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:100496.3-100517.6" + process $proc$libresoc.v:100496$4044 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:100497.5-100497.29" + switch \initial + attribute \src "libresoc.v:100497.9-100497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:100518.3-100539.6" + process $proc$libresoc.v:100518$4045 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:100519.5-100519.29" + switch \initial + attribute \src "libresoc.v:100519.9-100519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:100540.3-100561.6" + process $proc$libresoc.v:100540$4046 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:100541.5-100541.29" + switch \initial + attribute \src "libresoc.v:100541.9-100541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:100562.3-100583.6" + process $proc$libresoc.v:100562$4047 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:100563.5-100563.29" + switch \initial + attribute \src "libresoc.v:100563.9-100563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:100584.3-100605.6" + process $proc$libresoc.v:100584$4048 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:100585.5-100585.29" + switch \initial + attribute \src "libresoc.v:100585.9-100585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] + end + attribute \src "libresoc.v:100606.3-100627.6" + process $proc$libresoc.v:100606$4049 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:100607.5-100607.29" + switch \initial + attribute \src "libresoc.v:100607.9-100607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] + end + attribute \src "libresoc.v:100628.3-100649.6" + process $proc$libresoc.v:100628$4050 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:100629.5-100629.29" + switch \initial + attribute \src "libresoc.v:100629.9-100629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:100650.3-100671.6" + process $proc$libresoc.v:100650$4051 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:100651.5-100651.29" + switch \initial + attribute \src "libresoc.v:100651.9-100651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:100672.3-100693.6" + process $proc$libresoc.v:100672$4052 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:100673.5-100673.29" + switch \initial + attribute \src "libresoc.v:100673.9-100673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:100694.3-100715.6" + process $proc$libresoc.v:100694$4053 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:100695.5-100695.29" + switch \initial + attribute \src "libresoc.v:100695.9-100695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] + end + attribute \src "libresoc.v:99642.7-99642.20" + process $proc$libresoc.v:99642$4054 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99990.3-100011.6" + process $proc$libresoc.v:99990$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99991.5-99991.29" + switch \initial + attribute \src "libresoc.v:99991.9-99991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + case + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:100721.1-101698.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:101583.3-101601.6" + wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:101602.3-101620.6" + wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:101355.3-101373.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:101431.3-101449.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:101089.3-101107.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:101108.3-101126.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:101336.3-101354.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:101412.3-101430.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:101488.3-101506.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:101070.3-101088.6" + wire width 14 $0\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:101621.3-101639.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:101640.3-101658.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:101659.3-101677.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:101279.3-101297.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:101374.3-101392.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:101393.3-101411.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:101507.3-101525.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:101260.3-101278.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:101545.3-101563.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:101678.3-101696.6" + wire width 3 $0\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:101317.3-101335.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:101469.3-101487.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:101564.3-101582.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:101526.3-101544.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:101450.3-101468.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:101222.3-101240.6" + wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:101241.3-101259.6" + wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:101127.3-101145.6" + wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:101146.3-101164.6" + wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:101165.3-101183.6" + wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:101203.3-101221.6" + wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101184.3-101202.6" + wire width 3 $0\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:101298.3-101316.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:100722.7-100722.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:101583.3-101601.6" + wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:101602.3-101620.6" + wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:101355.3-101373.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:101431.3-101449.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:101089.3-101107.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:101108.3-101126.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:101336.3-101354.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:101412.3-101430.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:101488.3-101506.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:101070.3-101088.6" + wire width 14 $1\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:101621.3-101639.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:101640.3-101658.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:101659.3-101677.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:101279.3-101297.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:101374.3-101392.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:101393.3-101411.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:101507.3-101525.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:101260.3-101278.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:101545.3-101563.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:101678.3-101696.6" + wire width 3 $1\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:101317.3-101335.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:101469.3-101487.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:101564.3-101582.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:101526.3-101544.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:101450.3-101468.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:101222.3-101240.6" + wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:101241.3-101259.6" + wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:101127.3-101145.6" + wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:101146.3-101164.6" + wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:101165.3-101183.6" + wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:101203.3-101221.6" + wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101184.3-101202.6" + wire width 3 $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:101298.3-101316.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub19_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub19_upd + attribute \src "libresoc.v:100722.7-100722.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100722.7-100722.20" + process $proc$libresoc.v:100722$4088 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:101070.3-101088.6" + process $proc$libresoc.v:101070$4055 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:101071.5-101071.29" + switch \initial + attribute \src "libresoc.v:101071.9-101071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 + case + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] + end + attribute \src "libresoc.v:101089.3-101107.6" + process $proc$libresoc.v:101089$4056 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:101090.5-101090.29" + switch \initial + attribute \src "libresoc.v:101090.9-101090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:101108.3-101126.6" + process $proc$libresoc.v:101108$4057 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:101109.5-101109.29" + switch \initial + attribute \src "libresoc.v:101109.9-101109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:101127.3-101145.6" + process $proc$libresoc.v:101127$4058 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:101128.5-101128.29" + switch \initial + attribute \src "libresoc.v:101128.9-101128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] + end + attribute \src "libresoc.v:101146.3-101164.6" + process $proc$libresoc.v:101146$4059 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:101147.5-101147.29" + switch \initial + attribute \src "libresoc.v:101147.9-101147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] + end + attribute \src "libresoc.v:101165.3-101183.6" + process $proc$libresoc.v:101165$4060 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:101166.5-101166.29" + switch \initial + attribute \src "libresoc.v:101166.9-101166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] + end + attribute \src "libresoc.v:101184.3-101202.6" + process $proc$libresoc.v:101184$4061 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:101185.5-101185.29" + switch \initial + attribute \src "libresoc.v:101185.9-101185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] + end + attribute \src "libresoc.v:101203.3-101221.6" + process $proc$libresoc.v:101203$4062 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101204.5-101204.29" + switch \initial + attribute \src "libresoc.v:101204.9-101204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] + end + attribute \src "libresoc.v:101222.3-101240.6" + process $proc$libresoc.v:101222$4063 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:101223.5-101223.29" + switch \initial + attribute \src "libresoc.v:101223.9-101223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] + end + attribute \src "libresoc.v:101241.3-101259.6" + process $proc$libresoc.v:101241$4064 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:101242.5-101242.29" + switch \initial + attribute \src "libresoc.v:101242.9-101242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] + end + attribute \src "libresoc.v:101260.3-101278.6" + process $proc$libresoc.v:101260$4065 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:101261.5-101261.29" + switch \initial + attribute \src "libresoc.v:101261.9-101261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:101279.3-101297.6" + process $proc$libresoc.v:101279$4066 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:101280.5-101280.29" + switch \initial + attribute \src "libresoc.v:101280.9-101280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:101298.3-101316.6" + process $proc$libresoc.v:101298$4067 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:101299.5-101299.29" + switch \initial + attribute \src "libresoc.v:101299.9-101299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:101317.3-101335.6" + process $proc$libresoc.v:101317$4068 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:101318.5-101318.29" + switch \initial + attribute \src "libresoc.v:101318.9-101318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:101336.3-101354.6" + process $proc$libresoc.v:101336$4069 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:101337.5-101337.29" + switch \initial + attribute \src "libresoc.v:101337.9-101337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:101355.3-101373.6" + process $proc$libresoc.v:101355$4070 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:101356.5-101356.29" + switch \initial + attribute \src "libresoc.v:101356.9-101356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:101374.3-101392.6" + process $proc$libresoc.v:101374$4071 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:101375.5-101375.29" + switch \initial + attribute \src "libresoc.v:101375.9-101375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:101393.3-101411.6" + process $proc$libresoc.v:101393$4072 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:101394.5-101394.29" + switch \initial + attribute \src "libresoc.v:101394.9-101394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:101412.3-101430.6" + process $proc$libresoc.v:101412$4073 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:101413.5-101413.29" + switch \initial + attribute \src "libresoc.v:101413.9-101413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:101431.3-101449.6" + process $proc$libresoc.v:101431$4074 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:101432.5-101432.29" + switch \initial + attribute \src "libresoc.v:101432.9-101432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:101450.3-101468.6" + process $proc$libresoc.v:101450$4075 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:101451.5-101451.29" + switch \initial + attribute \src "libresoc.v:101451.9-101451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:101469.3-101487.6" + process $proc$libresoc.v:101469$4076 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:101470.5-101470.29" + switch \initial + attribute \src "libresoc.v:101470.9-101470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:101488.3-101506.6" + process $proc$libresoc.v:101488$4077 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:101489.5-101489.29" + switch \initial + attribute \src "libresoc.v:101489.9-101489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:101507.3-101525.6" + process $proc$libresoc.v:101507$4078 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:101508.5-101508.29" + switch \initial + attribute \src "libresoc.v:101508.9-101508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:101526.3-101544.6" + process $proc$libresoc.v:101526$4079 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:101527.5-101527.29" + switch \initial + attribute \src "libresoc.v:101527.9-101527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:101545.3-101563.6" + process $proc$libresoc.v:101545$4080 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:101546.5-101546.29" + switch \initial + attribute \src "libresoc.v:101546.9-101546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:101564.3-101582.6" + process $proc$libresoc.v:101564$4081 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:101565.5-101565.29" + switch \initial + attribute \src "libresoc.v:101565.9-101565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:101583.3-101601.6" + process $proc$libresoc.v:101583$4082 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:101584.5-101584.29" + switch \initial + attribute \src "libresoc.v:101584.9-101584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] + end + attribute \src "libresoc.v:101602.3-101620.6" + process $proc$libresoc.v:101602$4083 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:101603.5-101603.29" + switch \initial + attribute \src "libresoc.v:101603.9-101603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] + end + attribute \src "libresoc.v:101621.3-101639.6" + process $proc$libresoc.v:101621$4084 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:101622.5-101622.29" + switch \initial + attribute \src "libresoc.v:101622.9-101622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:101640.3-101658.6" + process $proc$libresoc.v:101640$4085 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:101641.5-101641.29" + switch \initial + attribute \src "libresoc.v:101641.9-101641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:101659.3-101677.6" + process $proc$libresoc.v:101659$4086 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:101660.5-101660.29" + switch \initial + attribute \src "libresoc.v:101660.9-101660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:101678.3-101696.6" + process $proc$libresoc.v:101678$4087 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:101679.5-101679.29" + switch \initial + attribute \src "libresoc.v:101679.9-101679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[2:0] 3'011 + case + assign $1\dec31_dec_sub19_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:101702.1-102877.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:102726.3-102750.6" + wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:102751.3-102775.6" + wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:102426.3-102450.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:102526.3-102550.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:102076.3-102100.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:102101.3-102125.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:102401.3-102425.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:102501.3-102525.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:102601.3-102625.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:102051.3-102075.6" + wire width 14 $0\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:102776.3-102800.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:102801.3-102825.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:102826.3-102850.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:102326.3-102350.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:102451.3-102475.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:102476.3-102500.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:102626.3-102650.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:102301.3-102325.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:102676.3-102700.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:102851.3-102875.6" + wire width 3 $0\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:102376.3-102400.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:102576.3-102600.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:102701.3-102725.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:102651.3-102675.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:102551.3-102575.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:102251.3-102275.6" + wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:102276.3-102300.6" + wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:102126.3-102150.6" + wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:102151.3-102175.6" + wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:102176.3-102200.6" + wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:102226.3-102250.6" + wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102201.3-102225.6" + wire width 3 $0\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:102351.3-102375.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:101703.7-101703.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:102726.3-102750.6" + wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:102751.3-102775.6" + wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:102426.3-102450.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:102526.3-102550.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:102076.3-102100.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:102101.3-102125.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:102401.3-102425.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:102501.3-102525.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:102601.3-102625.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:102051.3-102075.6" + wire width 14 $1\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:102776.3-102800.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:102801.3-102825.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:102826.3-102850.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:102326.3-102350.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:102451.3-102475.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:102476.3-102500.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:102626.3-102650.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:102301.3-102325.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:102676.3-102700.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:102851.3-102875.6" + wire width 3 $1\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:102376.3-102400.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:102576.3-102600.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:102701.3-102725.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:102651.3-102675.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:102551.3-102575.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:102251.3-102275.6" + wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:102276.3-102300.6" + wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:102126.3-102150.6" + wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:102151.3-102175.6" + wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:102176.3-102200.6" + wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:102226.3-102250.6" + wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102201.3-102225.6" + wire width 3 $1\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:102351.3-102375.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub20_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub20_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub20_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub20_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub20_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub20_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub20_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub20_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub20_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub20_upd + attribute \src "libresoc.v:101703.7-101703.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:101703.7-101703.20" + process $proc$libresoc.v:101703$4122 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:102051.3-102075.6" + process $proc$libresoc.v:102051$4089 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:102052.5-102052.29" + switch \initial + attribute \src "libresoc.v:102052.9-102052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 + case + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] + end + attribute \src "libresoc.v:102076.3-102100.6" + process $proc$libresoc.v:102076$4090 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:102077.5-102077.29" + switch \initial + attribute \src "libresoc.v:102077.9-102077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:102101.3-102125.6" + process $proc$libresoc.v:102101$4091 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:102102.5-102102.29" + switch \initial + attribute \src "libresoc.v:102102.9-102102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + attribute \src "libresoc.v:102126.3-102150.6" + process $proc$libresoc.v:102126$4092 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:102127.5-102127.29" + switch \initial + attribute \src "libresoc.v:102127.9-102127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] + end + attribute \src "libresoc.v:102151.3-102175.6" + process $proc$libresoc.v:102151$4093 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:102152.5-102152.29" + switch \initial + attribute \src "libresoc.v:102152.9-102152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] + end + attribute \src "libresoc.v:102176.3-102200.6" + process $proc$libresoc.v:102176$4094 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:102177.5-102177.29" + switch \initial + attribute \src "libresoc.v:102177.9-102177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] + end + attribute \src "libresoc.v:102201.3-102225.6" + process $proc$libresoc.v:102201$4095 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:102202.5-102202.29" + switch \initial + attribute \src "libresoc.v:102202.9-102202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] + end + attribute \src "libresoc.v:102226.3-102250.6" + process $proc$libresoc.v:102226$4096 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102227.5-102227.29" + switch \initial + attribute \src "libresoc.v:102227.9-102227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] + end + attribute \src "libresoc.v:102251.3-102275.6" + process $proc$libresoc.v:102251$4097 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:102252.5-102252.29" + switch \initial + attribute \src "libresoc.v:102252.9-102252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] + end + attribute \src "libresoc.v:102276.3-102300.6" + process $proc$libresoc.v:102276$4098 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:102277.5-102277.29" + switch \initial + attribute \src "libresoc.v:102277.9-102277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] + end + attribute \src "libresoc.v:102301.3-102325.6" + process $proc$libresoc.v:102301$4099 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:102302.5-102302.29" + switch \initial + attribute \src "libresoc.v:102302.9-102302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:102326.3-102350.6" + process $proc$libresoc.v:102326$4100 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:102327.5-102327.29" + switch \initial + attribute \src "libresoc.v:102327.9-102327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:102351.3-102375.6" + process $proc$libresoc.v:102351$4101 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:102352.5-102352.29" + switch \initial + attribute \src "libresoc.v:102352.9-102352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:102376.3-102400.6" + process $proc$libresoc.v:102376$4102 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:102377.5-102377.29" + switch \initial + attribute \src "libresoc.v:102377.9-102377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:102401.3-102425.6" + process $proc$libresoc.v:102401$4103 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:102402.5-102402.29" + switch \initial + attribute \src "libresoc.v:102402.9-102402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:102426.3-102450.6" + process $proc$libresoc.v:102426$4104 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:102427.5-102427.29" + switch \initial + attribute \src "libresoc.v:102427.9-102427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101110 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:102451.3-102475.6" + process $proc$libresoc.v:102451$4105 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:102452.5-102452.29" + switch \initial + attribute \src "libresoc.v:102452.9-102452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:102476.3-102500.6" + process $proc$libresoc.v:102476$4106 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:102477.5-102477.29" + switch \initial + attribute \src "libresoc.v:102477.9-102477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:102501.3-102525.6" + process $proc$libresoc.v:102501$4107 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:102502.5-102502.29" + switch \initial + attribute \src "libresoc.v:102502.9-102502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:102526.3-102550.6" + process $proc$libresoc.v:102526$4108 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:102527.5-102527.29" + switch \initial + attribute \src "libresoc.v:102527.9-102527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:102551.3-102575.6" + process $proc$libresoc.v:102551$4109 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:102552.5-102552.29" + switch \initial + attribute \src "libresoc.v:102552.9-102552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:102576.3-102600.6" + process $proc$libresoc.v:102576$4110 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:102577.5-102577.29" + switch \initial + attribute \src "libresoc.v:102577.9-102577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:102601.3-102625.6" + process $proc$libresoc.v:102601$4111 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:102602.5-102602.29" + switch \initial + attribute \src "libresoc.v:102602.9-102602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:102626.3-102650.6" + process $proc$libresoc.v:102626$4112 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:102627.5-102627.29" + switch \initial + attribute \src "libresoc.v:102627.9-102627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:102651.3-102675.6" + process $proc$libresoc.v:102651$4113 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:102652.5-102652.29" + switch \initial + attribute \src "libresoc.v:102652.9-102652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:102676.3-102700.6" + process $proc$libresoc.v:102676$4114 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:102677.5-102677.29" + switch \initial + attribute \src "libresoc.v:102677.9-102677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:102701.3-102725.6" + process $proc$libresoc.v:102701$4115 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:102702.5-102702.29" + switch \initial + attribute \src "libresoc.v:102702.9-102702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:102726.3-102750.6" + process $proc$libresoc.v:102726$4116 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:102727.5-102727.29" + switch \initial + attribute \src "libresoc.v:102727.9-102727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] + end + attribute \src "libresoc.v:102751.3-102775.6" + process $proc$libresoc.v:102751$4117 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:102752.5-102752.29" + switch \initial + attribute \src "libresoc.v:102752.9-102752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] + end + attribute \src "libresoc.v:102776.3-102800.6" + process $proc$libresoc.v:102776$4118 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:102777.5-102777.29" + switch \initial + attribute \src "libresoc.v:102777.9-102777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:102801.3-102825.6" + process $proc$libresoc.v:102801$4119 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:102802.5-102802.29" + switch \initial + attribute \src "libresoc.v:102802.9-102802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:102826.3-102850.6" + process $proc$libresoc.v:102826$4120 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:102827.5-102827.29" + switch \initial + attribute \src "libresoc.v:102827.9-102827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:102851.3-102875.6" + process $proc$libresoc.v:102851$4121 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:102852.5-102852.29" + switch \initial + attribute \src "libresoc.v:102852.9-102852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute 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width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:103230.3-103278.6" + wire width 14 $0\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:104633.3-104681.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:104682.3-104730.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:104731.3-104779.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:103769.3-103817.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:103965.3-104013.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:104014.3-104062.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:104259.3-104307.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:103720.3-103768.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:104406.3-104454.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:104780.3-104828.6" + wire width 3 $0\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:103867.3-103915.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:104210.3-104258.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:104455.3-104503.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:104357.3-104405.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:104161.3-104209.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:103622.3-103670.6" + wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:103671.3-103719.6" + wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:103377.3-103425.6" + wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:103426.3-103474.6" + wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:103475.3-103523.6" + wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:103573.3-103621.6" + wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103524.3-103572.6" + wire width 3 $0\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:103818.3-103866.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:102882.7-102882.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:104535.3-104583.6" + wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:104584.3-104632.6" + wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:104504.3-104534.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:104112.3-104160.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:103279.3-103327.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:103328.3-103376.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:103916.3-103964.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:104063.3-104111.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:104308.3-104356.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:103230.3-103278.6" + wire width 14 $1\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:104633.3-104681.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:104682.3-104730.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:104731.3-104779.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:103769.3-103817.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:103965.3-104013.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:104014.3-104062.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:104259.3-104307.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:103720.3-103768.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:104406.3-104454.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:104780.3-104828.6" + wire width 3 $1\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:103867.3-103915.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:104210.3-104258.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:104455.3-104503.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:104357.3-104405.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:104161.3-104209.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:103622.3-103670.6" + wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:103671.3-103719.6" + wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:103377.3-103425.6" + wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:103426.3-103474.6" + wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:103475.3-103523.6" + wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:103573.3-103621.6" + wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103524.3-103572.6" + wire width 3 $1\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:103818.3-103866.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub21_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub21_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub21_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub21_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub21_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub21_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub21_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub21_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub21_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub21_upd + attribute \src "libresoc.v:102882.7-102882.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:102882.7-102882.20" + process $proc$libresoc.v:102882$4156 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:103230.3-103278.6" + process $proc$libresoc.v:103230$4123 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:103231.5-103231.29" + switch \initial + attribute \src "libresoc.v:103231.9-103231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 + case + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] + end + attribute \src "libresoc.v:103279.3-103327.6" + process $proc$libresoc.v:103279$4124 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:103280.5-103280.29" + switch \initial + attribute \src "libresoc.v:103280.9-103280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:103328.3-103376.6" + process $proc$libresoc.v:103328$4125 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:103329.5-103329.29" + switch \initial + attribute \src "libresoc.v:103329.9-103329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + attribute \src "libresoc.v:103377.3-103425.6" + process $proc$libresoc.v:103377$4126 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:103378.5-103378.29" + switch \initial + attribute \src "libresoc.v:103378.9-103378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] + end + attribute \src "libresoc.v:103426.3-103474.6" + process $proc$libresoc.v:103426$4127 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:103427.5-103427.29" + switch \initial + attribute \src "libresoc.v:103427.9-103427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] + end + attribute \src "libresoc.v:103475.3-103523.6" + process $proc$libresoc.v:103475$4128 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:103476.5-103476.29" + switch \initial + attribute \src "libresoc.v:103476.9-103476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] + end + attribute \src "libresoc.v:103524.3-103572.6" + process $proc$libresoc.v:103524$4129 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:103525.5-103525.29" + switch \initial + attribute \src "libresoc.v:103525.9-103525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] + end + attribute \src "libresoc.v:103573.3-103621.6" + process $proc$libresoc.v:103573$4130 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103574.5-103574.29" + switch \initial + attribute \src "libresoc.v:103574.9-103574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] + end + attribute \src "libresoc.v:103622.3-103670.6" + process $proc$libresoc.v:103622$4131 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:103623.5-103623.29" + switch \initial + attribute \src "libresoc.v:103623.9-103623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] + end + attribute \src "libresoc.v:103671.3-103719.6" + process $proc$libresoc.v:103671$4132 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:103672.5-103672.29" + switch \initial + attribute \src "libresoc.v:103672.9-103672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] + end + attribute \src "libresoc.v:103720.3-103768.6" + process $proc$libresoc.v:103720$4133 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:103721.5-103721.29" + switch \initial + attribute \src "libresoc.v:103721.9-103721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:103769.3-103817.6" + process $proc$libresoc.v:103769$4134 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:103770.5-103770.29" + switch \initial + attribute \src "libresoc.v:103770.9-103770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:103818.3-103866.6" + process $proc$libresoc.v:103818$4135 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:103819.5-103819.29" + switch \initial + attribute \src "libresoc.v:103819.9-103819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:103867.3-103915.6" + process $proc$libresoc.v:103867$4136 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:103868.5-103868.29" + switch \initial + attribute \src "libresoc.v:103868.9-103868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "libresoc.v:103916.3-103964.6" + process $proc$libresoc.v:103916$4137 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:103917.5-103917.29" + switch \initial + attribute \src "libresoc.v:103917.9-103917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "libresoc.v:103965.3-104013.6" + process $proc$libresoc.v:103965$4138 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:103966.5-103966.29" + switch \initial + attribute \src "libresoc.v:103966.9-103966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "libresoc.v:104014.3-104062.6" + process $proc$libresoc.v:104014$4139 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:104015.5-104015.29" + switch \initial + attribute \src "libresoc.v:104015.9-104015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "libresoc.v:104063.3-104111.6" + process $proc$libresoc.v:104063$4140 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:104064.5-104064.29" + switch \initial + attribute \src "libresoc.v:104064.9-104064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "libresoc.v:104112.3-104160.6" + process $proc$libresoc.v:104112$4141 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:104113.5-104113.29" + switch \initial + attribute \src "libresoc.v:104113.9-104113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:104161.3-104209.6" + process $proc$libresoc.v:104161$4142 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:104162.5-104162.29" + switch \initial + attribute \src "libresoc.v:104162.9-104162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:104210.3-104258.6" + process $proc$libresoc.v:104210$4143 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:104211.5-104211.29" + switch \initial + attribute \src "libresoc.v:104211.9-104211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "libresoc.v:104259.3-104307.6" + process $proc$libresoc.v:104259$4144 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:104260.5-104260.29" + switch \initial + attribute \src "libresoc.v:104260.9-104260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:104308.3-104356.6" + process $proc$libresoc.v:104308$4145 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:104309.5-104309.29" + switch \initial + attribute \src "libresoc.v:104309.9-104309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "libresoc.v:104357.3-104405.6" + process $proc$libresoc.v:104357$4146 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:104358.5-104358.29" + switch \initial + attribute \src "libresoc.v:104358.9-104358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:104406.3-104454.6" + process $proc$libresoc.v:104406$4147 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:104407.5-104407.29" + switch \initial + attribute \src "libresoc.v:104407.9-104407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:104455.3-104503.6" + process $proc$libresoc.v:104455$4148 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:104456.5-104456.29" + switch \initial + attribute \src "libresoc.v:104456.9-104456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:104504.3-104534.6" + process $proc$libresoc.v:104504$4149 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:104505.5-104505.29" + switch \initial + attribute \src "libresoc.v:104505.9-104505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110010 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:104535.3-104583.6" + process $proc$libresoc.v:104535$4150 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:104536.5-104536.29" + switch \initial + attribute \src "libresoc.v:104536.9-104536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] + end + attribute \src "libresoc.v:104584.3-104632.6" + process $proc$libresoc.v:104584$4151 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:104585.5-104585.29" + switch \initial + attribute \src "libresoc.v:104585.9-104585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] + end + attribute \src "libresoc.v:104633.3-104681.6" + process $proc$libresoc.v:104633$4152 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:104634.5-104634.29" + switch \initial + attribute \src "libresoc.v:104634.9-104634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:104682.3-104730.6" + process $proc$libresoc.v:104682$4153 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:104683.5-104683.29" + switch \initial + attribute \src "libresoc.v:104683.9-104683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:104731.3-104779.6" + process $proc$libresoc.v:104731$4154 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:104732.5-104732.29" + switch \initial + attribute \src "libresoc.v:104732.9-104732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:104780.3-104828.6" + process $proc$libresoc.v:104780$4155 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:104781.5-104781.29" + switch \initial + attribute \src "libresoc.v:104781.9-104781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:104834.1-106999.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:106668.3-106722.6" + wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:106723.3-106777.6" + wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:106008.3-106062.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:106228.3-106282.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:105238.3-105292.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:105293.3-105347.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:105953.3-106007.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:106173.3-106227.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:106393.3-106447.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:105183.3-105237.6" + wire width 14 $0\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:106778.3-106832.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:106833.3-106887.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:106888.3-106942.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:105788.3-105842.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:106063.3-106117.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:106118.3-106172.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:106448.3-106502.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:105733.3-105787.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:106558.3-106612.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:106943.3-106997.6" + wire width 3 $0\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:105898.3-105952.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:106338.3-106392.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:106613.3-106667.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:106503.3-106557.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:106283.3-106337.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:105623.3-105677.6" + wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:105678.3-105732.6" + wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:105348.3-105402.6" + wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:105403.3-105457.6" + wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:105458.3-105512.6" + wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:105568.3-105622.6" + wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105513.3-105567.6" + wire width 3 $0\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:105843.3-105897.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:104835.7-104835.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:106668.3-106722.6" + wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:106723.3-106777.6" + wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:106008.3-106062.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:106228.3-106282.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:105238.3-105292.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:105293.3-105347.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:105953.3-106007.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:106173.3-106227.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:106393.3-106447.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:105183.3-105237.6" + wire width 14 $1\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:106778.3-106832.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:106833.3-106887.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:106888.3-106942.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:105788.3-105842.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:106063.3-106117.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:106118.3-106172.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:106448.3-106502.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:105733.3-105787.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:106558.3-106612.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:106943.3-106997.6" + wire width 3 $1\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:105898.3-105952.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:106338.3-106392.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:106613.3-106667.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:106503.3-106557.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:106283.3-106337.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:105623.3-105677.6" + wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:105678.3-105732.6" + wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:105348.3-105402.6" + wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:105403.3-105457.6" + wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:105458.3-105512.6" + wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:105568.3-105622.6" + wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105513.3-105567.6" + wire width 3 $1\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:105843.3-105897.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub22_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub22_upd + attribute \src "libresoc.v:104835.7-104835.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:104835.7-104835.20" + process $proc$libresoc.v:104835$4190 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:105183.3-105237.6" + process $proc$libresoc.v:105183$4157 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:105184.5-105184.29" + switch \initial + attribute \src "libresoc.v:105184.9-105184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 + case + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] + end + attribute \src "libresoc.v:105238.3-105292.6" + process $proc$libresoc.v:105238$4158 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:105239.5-105239.29" + switch \initial + attribute \src "libresoc.v:105239.9-105239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:105293.3-105347.6" + process $proc$libresoc.v:105293$4159 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:105294.5-105294.29" + switch \initial + attribute \src "libresoc.v:105294.9-105294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:105348.3-105402.6" + process $proc$libresoc.v:105348$4160 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:105349.5-105349.29" + switch \initial + attribute \src "libresoc.v:105349.9-105349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] + end + attribute \src "libresoc.v:105403.3-105457.6" + process $proc$libresoc.v:105403$4161 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:105404.5-105404.29" + switch \initial + attribute \src "libresoc.v:105404.9-105404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] + end + attribute \src "libresoc.v:105458.3-105512.6" + process $proc$libresoc.v:105458$4162 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:105459.5-105459.29" + switch \initial + attribute \src "libresoc.v:105459.9-105459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] + end + attribute \src "libresoc.v:105513.3-105567.6" + process $proc$libresoc.v:105513$4163 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:105514.5-105514.29" + switch \initial + attribute \src "libresoc.v:105514.9-105514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] + end + attribute \src "libresoc.v:105568.3-105622.6" + process $proc$libresoc.v:105568$4164 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105569.5-105569.29" + switch \initial + attribute \src "libresoc.v:105569.9-105569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] + end + attribute \src "libresoc.v:105623.3-105677.6" + process $proc$libresoc.v:105623$4165 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:105624.5-105624.29" + switch \initial + attribute \src "libresoc.v:105624.9-105624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] + end + attribute \src "libresoc.v:105678.3-105732.6" + process $proc$libresoc.v:105678$4166 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:105679.5-105679.29" + switch \initial + attribute \src "libresoc.v:105679.9-105679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] + end + attribute \src "libresoc.v:105733.3-105787.6" + process $proc$libresoc.v:105733$4167 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:105734.5-105734.29" + switch \initial + attribute \src "libresoc.v:105734.9-105734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:105788.3-105842.6" + process $proc$libresoc.v:105788$4168 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:105789.5-105789.29" + switch \initial + attribute \src "libresoc.v:105789.9-105789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:105843.3-105897.6" + process $proc$libresoc.v:105843$4169 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:105844.5-105844.29" + switch \initial + attribute \src "libresoc.v:105844.9-105844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:105898.3-105952.6" + process $proc$libresoc.v:105898$4170 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:105899.5-105899.29" + switch \initial + attribute \src "libresoc.v:105899.9-105899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:105953.3-106007.6" + process $proc$libresoc.v:105953$4171 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:105954.5-105954.29" + switch \initial + attribute \src "libresoc.v:105954.9-105954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "libresoc.v:106008.3-106062.6" + process $proc$libresoc.v:106008$4172 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:106009.5-106009.29" + switch \initial + attribute \src "libresoc.v:106009.9-106009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001010 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "libresoc.v:106063.3-106117.6" + process $proc$libresoc.v:106063$4173 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:106064.5-106064.29" + switch \initial + attribute \src "libresoc.v:106064.9-106064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:106118.3-106172.6" + process $proc$libresoc.v:106118$4174 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:106119.5-106119.29" + switch \initial + attribute \src "libresoc.v:106119.9-106119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:106173.3-106227.6" + process $proc$libresoc.v:106173$4175 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:106174.5-106174.29" + switch \initial + attribute \src "libresoc.v:106174.9-106174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:106228.3-106282.6" + process $proc$libresoc.v:106228$4176 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:106229.5-106229.29" + switch \initial + attribute \src "libresoc.v:106229.9-106229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:106283.3-106337.6" + process $proc$libresoc.v:106283$4177 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:106284.5-106284.29" + switch \initial + attribute \src "libresoc.v:106284.9-106284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:106338.3-106392.6" + process $proc$libresoc.v:106338$4178 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:106339.5-106339.29" + switch \initial + attribute \src "libresoc.v:106339.9-106339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "libresoc.v:106393.3-106447.6" + process $proc$libresoc.v:106393$4179 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:106394.5-106394.29" + switch \initial + attribute \src "libresoc.v:106394.9-106394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "libresoc.v:106448.3-106502.6" + process $proc$libresoc.v:106448$4180 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:106449.5-106449.29" + switch \initial + attribute \src "libresoc.v:106449.9-106449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:106503.3-106557.6" + process $proc$libresoc.v:106503$4181 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:106504.5-106504.29" + switch \initial + attribute \src "libresoc.v:106504.9-106504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:106558.3-106612.6" + process $proc$libresoc.v:106558$4182 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:106559.5-106559.29" + switch \initial + attribute \src "libresoc.v:106559.9-106559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "libresoc.v:106613.3-106667.6" + process $proc$libresoc.v:106613$4183 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:106614.5-106614.29" + switch \initial + attribute \src "libresoc.v:106614.9-106614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:106668.3-106722.6" + process $proc$libresoc.v:106668$4184 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:106669.5-106669.29" + switch \initial + attribute \src "libresoc.v:106669.9-106669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] + end + attribute \src "libresoc.v:106723.3-106777.6" + process $proc$libresoc.v:106723$4185 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:106724.5-106724.29" + switch \initial + attribute \src "libresoc.v:106724.9-106724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] + end + attribute \src "libresoc.v:106778.3-106832.6" + process $proc$libresoc.v:106778$4186 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:106779.5-106779.29" + switch \initial + attribute \src "libresoc.v:106779.9-106779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:106833.3-106887.6" + process $proc$libresoc.v:106833$4187 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:106834.5-106834.29" + switch \initial + attribute \src "libresoc.v:106834.9-106834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:106888.3-106942.6" + process $proc$libresoc.v:106888$4188 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:106889.5-106889.29" + switch \initial + attribute \src "libresoc.v:106889.9-106889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "libresoc.v:106943.3-106997.6" + process $proc$libresoc.v:106943$4189 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:106944.5-106944.29" + switch \initial + attribute \src "libresoc.v:106944.9-106944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:107003.1-108970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:108675.3-108723.6" + wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:108724.3-108772.6" + wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:108087.3-108135.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:108283.3-108331.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:107401.3-107449.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:107450.3-107498.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:108038.3-108086.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:108234.3-108282.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:108430.3-108478.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:107352.3-107400.6" + wire width 14 $0\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:108773.3-108821.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:108822.3-108870.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:108871.3-108919.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:107891.3-107939.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:108136.3-108184.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:108185.3-108233.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:108479.3-108527.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:107842.3-107890.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:108577.3-108625.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:108920.3-108968.6" + wire width 3 $0\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:107989.3-108037.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:108381.3-108429.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:108626.3-108674.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:108528.3-108576.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:108332.3-108380.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:107744.3-107792.6" + wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:107793.3-107841.6" + wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:107499.3-107547.6" + wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:107548.3-107596.6" + wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:107597.3-107645.6" + wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:107695.3-107743.6" + wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107646.3-107694.6" + wire width 3 $0\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:107940.3-107988.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:107004.7-107004.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:108675.3-108723.6" + wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:108724.3-108772.6" + wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:108087.3-108135.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:108283.3-108331.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:107401.3-107449.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:107450.3-107498.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:108038.3-108086.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:108234.3-108282.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:108430.3-108478.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:107352.3-107400.6" + wire width 14 $1\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:108773.3-108821.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:108822.3-108870.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:108871.3-108919.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:107891.3-107939.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:108136.3-108184.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:108185.3-108233.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:108479.3-108527.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:107842.3-107890.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:108577.3-108625.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:108920.3-108968.6" + wire width 3 $1\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:107989.3-108037.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:108381.3-108429.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:108626.3-108674.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:108528.3-108576.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:108332.3-108380.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:107744.3-107792.6" + wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:107793.3-107841.6" + wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:107499.3-107547.6" + wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:107548.3-107596.6" + wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:107597.3-107645.6" + wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:107695.3-107743.6" + wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107646.3-107694.6" + wire width 3 $1\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:107940.3-107988.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub23_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub23_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub23_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub23_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub23_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub23_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub23_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub23_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub23_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub23_upd + attribute \src "libresoc.v:107004.7-107004.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:107004.7-107004.20" + process $proc$libresoc.v:107004$4224 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:107352.3-107400.6" + process $proc$libresoc.v:107352$4191 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:107353.5-107353.29" + switch \initial + attribute \src "libresoc.v:107353.9-107353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 + case + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] + end + attribute \src "libresoc.v:107401.3-107449.6" + process $proc$libresoc.v:107401$4192 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:107402.5-107402.29" + switch \initial + attribute \src "libresoc.v:107402.9-107402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:107450.3-107498.6" + process $proc$libresoc.v:107450$4193 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:107451.5-107451.29" + switch \initial + attribute \src "libresoc.v:107451.9-107451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + attribute \src "libresoc.v:107499.3-107547.6" + process $proc$libresoc.v:107499$4194 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:107500.5-107500.29" + switch \initial + attribute \src "libresoc.v:107500.9-107500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] + end + attribute \src "libresoc.v:107548.3-107596.6" + process $proc$libresoc.v:107548$4195 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:107549.5-107549.29" + switch \initial + attribute \src "libresoc.v:107549.9-107549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] + end + attribute \src "libresoc.v:107597.3-107645.6" + process $proc$libresoc.v:107597$4196 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:107598.5-107598.29" + switch \initial + attribute \src "libresoc.v:107598.9-107598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] + end + attribute \src "libresoc.v:107646.3-107694.6" + process $proc$libresoc.v:107646$4197 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:107647.5-107647.29" + switch \initial + attribute \src "libresoc.v:107647.9-107647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] + end + attribute \src "libresoc.v:107695.3-107743.6" + process $proc$libresoc.v:107695$4198 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107696.5-107696.29" + switch \initial + attribute \src "libresoc.v:107696.9-107696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] + end + attribute \src "libresoc.v:107744.3-107792.6" + process $proc$libresoc.v:107744$4199 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:107745.5-107745.29" + switch \initial + attribute \src "libresoc.v:107745.9-107745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] + end + attribute \src "libresoc.v:107793.3-107841.6" + process $proc$libresoc.v:107793$4200 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:107794.5-107794.29" + switch \initial + attribute \src "libresoc.v:107794.9-107794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] + end + attribute \src "libresoc.v:107842.3-107890.6" + process $proc$libresoc.v:107842$4201 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:107843.5-107843.29" + switch \initial + attribute \src "libresoc.v:107843.9-107843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:107891.3-107939.6" + process $proc$libresoc.v:107891$4202 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:107892.5-107892.29" + switch \initial + attribute \src "libresoc.v:107892.9-107892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:107940.3-107988.6" + process $proc$libresoc.v:107940$4203 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:107941.5-107941.29" + switch \initial + attribute \src "libresoc.v:107941.9-107941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:107989.3-108037.6" + process $proc$libresoc.v:107989$4204 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:107990.5-107990.29" + switch \initial + attribute \src "libresoc.v:107990.9-107990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "libresoc.v:108038.3-108086.6" + process $proc$libresoc.v:108038$4205 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:108039.5-108039.29" + switch \initial + attribute \src "libresoc.v:108039.9-108039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + end + attribute \src "libresoc.v:108087.3-108135.6" + process $proc$libresoc.v:108087$4206 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:108088.5-108088.29" + switch \initial + attribute \src "libresoc.v:108088.9-108088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111110 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "libresoc.v:108136.3-108184.6" + process $proc$libresoc.v:108136$4207 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:108137.5-108137.29" + switch \initial + attribute \src "libresoc.v:108137.9-108137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "libresoc.v:108185.3-108233.6" + process $proc$libresoc.v:108185$4208 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:108186.5-108186.29" + switch \initial + attribute \src "libresoc.v:108186.9-108186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + end + attribute \src "libresoc.v:108234.3-108282.6" + process $proc$libresoc.v:108234$4209 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:108235.5-108235.29" + switch \initial + attribute \src "libresoc.v:108235.9-108235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "libresoc.v:108283.3-108331.6" + process $proc$libresoc.v:108283$4210 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:108284.5-108284.29" + switch \initial + attribute \src "libresoc.v:108284.9-108284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:108332.3-108380.6" + process $proc$libresoc.v:108332$4211 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:108333.5-108333.29" + switch \initial + attribute \src "libresoc.v:108333.9-108333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:108381.3-108429.6" + process $proc$libresoc.v:108381$4212 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:108382.5-108382.29" + switch \initial + attribute \src "libresoc.v:108382.9-108382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:108430.3-108478.6" + process $proc$libresoc.v:108430$4213 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:108431.5-108431.29" + switch \initial + attribute \src "libresoc.v:108431.9-108431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:108479.3-108527.6" + process $proc$libresoc.v:108479$4214 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:108480.5-108480.29" + switch \initial + attribute \src "libresoc.v:108480.9-108480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:108528.3-108576.6" + process $proc$libresoc.v:108528$4215 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:108529.5-108529.29" + switch \initial + attribute \src "libresoc.v:108529.9-108529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:108577.3-108625.6" + process $proc$libresoc.v:108577$4216 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:108578.5-108578.29" + switch \initial + attribute \src "libresoc.v:108578.9-108578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:108626.3-108674.6" + process $proc$libresoc.v:108626$4217 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:108627.5-108627.29" + switch \initial + attribute \src "libresoc.v:108627.9-108627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + end + attribute \src "libresoc.v:108675.3-108723.6" + process $proc$libresoc.v:108675$4218 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:108676.5-108676.29" + switch \initial + attribute \src "libresoc.v:108676.9-108676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] + end + attribute \src "libresoc.v:108724.3-108772.6" + process $proc$libresoc.v:108724$4219 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:108725.5-108725.29" + switch \initial + attribute \src "libresoc.v:108725.9-108725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] + end + attribute \src "libresoc.v:108773.3-108821.6" + process $proc$libresoc.v:108773$4220 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:108774.5-108774.29" + switch \initial + attribute \src "libresoc.v:108774.9-108774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:108822.3-108870.6" + process $proc$libresoc.v:108822$4221 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:108823.5-108823.29" + switch \initial + attribute \src "libresoc.v:108823.9-108823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:108871.3-108919.6" + process $proc$libresoc.v:108871$4222 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:108872.5-108872.29" + switch \initial + attribute \src "libresoc.v:108872.9-108872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:108920.3-108968.6" + process $proc$libresoc.v:108920$4223 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:108921.5-108921.29" + switch \initial + attribute \src "libresoc.v:108921.9-108921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:108974.1-109951.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:109836.3-109854.6" + wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:109855.3-109873.6" + wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:109608.3-109626.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:109684.3-109702.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:109342.3-109360.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:109361.3-109379.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:109589.3-109607.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:109665.3-109683.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:109741.3-109759.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:109323.3-109341.6" + wire width 14 $0\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:109874.3-109892.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:109893.3-109911.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:109912.3-109930.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:109532.3-109550.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:109627.3-109645.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:109646.3-109664.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:109760.3-109778.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:109513.3-109531.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:109798.3-109816.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:109931.3-109949.6" + wire width 3 $0\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:109570.3-109588.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:109722.3-109740.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:109817.3-109835.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:109779.3-109797.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:109703.3-109721.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:109475.3-109493.6" + wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:109494.3-109512.6" + wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:109380.3-109398.6" + wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:109399.3-109417.6" + wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:109418.3-109436.6" + wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:109456.3-109474.6" + wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109437.3-109455.6" + wire width 3 $0\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:109551.3-109569.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:108975.7-108975.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109836.3-109854.6" + wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:109855.3-109873.6" + wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:109608.3-109626.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:109684.3-109702.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:109342.3-109360.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:109361.3-109379.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:109589.3-109607.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:109665.3-109683.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:109741.3-109759.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:109323.3-109341.6" + wire width 14 $1\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:109874.3-109892.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:109893.3-109911.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:109912.3-109930.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:109532.3-109550.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:109627.3-109645.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:109646.3-109664.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:109760.3-109778.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:109513.3-109531.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:109798.3-109816.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:109931.3-109949.6" + wire width 3 $1\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:109570.3-109588.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:109722.3-109740.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:109817.3-109835.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:109779.3-109797.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:109703.3-109721.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:109475.3-109493.6" + wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:109494.3-109512.6" + wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:109380.3-109398.6" + wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:109399.3-109417.6" + wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:109418.3-109436.6" + wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:109456.3-109474.6" + wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109437.3-109455.6" + wire width 3 $1\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:109551.3-109569.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub24_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub24_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub24_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub24_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub24_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub24_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub24_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub24_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub24_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub24_upd + attribute \src "libresoc.v:108975.7-108975.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:108975.7-108975.20" + process $proc$libresoc.v:108975$4258 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109323.3-109341.6" + process $proc$libresoc.v:109323$4225 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:109324.5-109324.29" + switch \initial + attribute \src "libresoc.v:109324.9-109324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 + case + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] + end + attribute \src "libresoc.v:109342.3-109360.6" + process $proc$libresoc.v:109342$4226 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:109343.5-109343.29" + switch \initial + attribute \src "libresoc.v:109343.9-109343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:109361.3-109379.6" + process $proc$libresoc.v:109361$4227 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:109362.5-109362.29" + switch \initial + attribute \src "libresoc.v:109362.9-109362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + attribute \src "libresoc.v:109380.3-109398.6" + process $proc$libresoc.v:109380$4228 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:109381.5-109381.29" + switch \initial + attribute \src "libresoc.v:109381.9-109381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] + end + attribute \src "libresoc.v:109399.3-109417.6" + process $proc$libresoc.v:109399$4229 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:109400.5-109400.29" + switch \initial + attribute \src "libresoc.v:109400.9-109400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 + case + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] + end + attribute \src "libresoc.v:109418.3-109436.6" + process $proc$libresoc.v:109418$4230 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:109419.5-109419.29" + switch \initial + attribute \src "libresoc.v:109419.9-109419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 + case + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] + end + attribute \src "libresoc.v:109437.3-109455.6" + process $proc$libresoc.v:109437$4231 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:109438.5-109438.29" + switch \initial + attribute \src "libresoc.v:109438.9-109438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] + end + attribute \src "libresoc.v:109456.3-109474.6" + process $proc$libresoc.v:109456$4232 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109457.5-109457.29" + switch \initial + attribute \src "libresoc.v:109457.9-109457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] + end + attribute \src "libresoc.v:109475.3-109493.6" + process $proc$libresoc.v:109475$4233 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:109476.5-109476.29" + switch \initial + attribute \src "libresoc.v:109476.9-109476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] + end + attribute \src "libresoc.v:109494.3-109512.6" + process $proc$libresoc.v:109494$4234 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:109495.5-109495.29" + switch \initial + attribute \src "libresoc.v:109495.9-109495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] + end + attribute \src "libresoc.v:109513.3-109531.6" + process $proc$libresoc.v:109513$4235 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:109514.5-109514.29" + switch \initial + attribute \src "libresoc.v:109514.9-109514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "libresoc.v:109532.3-109550.6" + process $proc$libresoc.v:109532$4236 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:109533.5-109533.29" + switch \initial + attribute \src "libresoc.v:109533.9-109533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:109551.3-109569.6" + process $proc$libresoc.v:109551$4237 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:109552.5-109552.29" + switch \initial + attribute \src "libresoc.v:109552.9-109552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "libresoc.v:109570.3-109588.6" + process $proc$libresoc.v:109570$4238 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:109571.5-109571.29" + switch \initial + attribute \src "libresoc.v:109571.9-109571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:109589.3-109607.6" + process $proc$libresoc.v:109589$4239 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:109590.5-109590.29" + switch \initial + attribute \src "libresoc.v:109590.9-109590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:109608.3-109626.6" + process $proc$libresoc.v:109608$4240 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:109609.5-109609.29" + switch \initial + attribute \src "libresoc.v:109609.9-109609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100110 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + end + attribute \src "libresoc.v:109627.3-109645.6" + process $proc$libresoc.v:109627$4241 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:109628.5-109628.29" + switch \initial + attribute \src "libresoc.v:109628.9-109628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:109646.3-109664.6" + process $proc$libresoc.v:109646$4242 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:109647.5-109647.29" + switch \initial + attribute \src "libresoc.v:109647.9-109647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:109665.3-109683.6" + process $proc$libresoc.v:109665$4243 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:109666.5-109666.29" + switch \initial + attribute \src "libresoc.v:109666.9-109666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:109684.3-109702.6" + process $proc$libresoc.v:109684$4244 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:109685.5-109685.29" + switch \initial + attribute \src "libresoc.v:109685.9-109685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:109703.3-109721.6" + process $proc$libresoc.v:109703$4245 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:109704.5-109704.29" + switch \initial + attribute \src "libresoc.v:109704.9-109704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "libresoc.v:109722.3-109740.6" + process $proc$libresoc.v:109722$4246 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:109723.5-109723.29" + switch \initial + attribute \src "libresoc.v:109723.9-109723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:109741.3-109759.6" + process $proc$libresoc.v:109741$4247 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:109742.5-109742.29" + switch \initial + attribute \src "libresoc.v:109742.9-109742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:109760.3-109778.6" + process $proc$libresoc.v:109760$4248 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:109761.5-109761.29" + switch \initial + attribute \src "libresoc.v:109761.9-109761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:109779.3-109797.6" + process $proc$libresoc.v:109779$4249 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:109780.5-109780.29" + switch \initial + attribute \src "libresoc.v:109780.9-109780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:109798.3-109816.6" + process $proc$libresoc.v:109798$4250 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:109799.5-109799.29" + switch \initial + attribute \src "libresoc.v:109799.9-109799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:109817.3-109835.6" + process $proc$libresoc.v:109817$4251 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:109818.5-109818.29" + switch \initial + attribute \src "libresoc.v:109818.9-109818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + end + attribute \src "libresoc.v:109836.3-109854.6" + process $proc$libresoc.v:109836$4252 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:109837.5-109837.29" + switch \initial + attribute \src "libresoc.v:109837.9-109837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] + end + attribute \src "libresoc.v:109855.3-109873.6" + process $proc$libresoc.v:109855$4253 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:109856.5-109856.29" + switch \initial + attribute \src "libresoc.v:109856.9-109856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] + end + attribute \src "libresoc.v:109874.3-109892.6" + process $proc$libresoc.v:109874$4254 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:109875.5-109875.29" + switch \initial + attribute \src "libresoc.v:109875.9-109875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:109893.3-109911.6" + process $proc$libresoc.v:109893$4255 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:109894.5-109894.29" + switch \initial + attribute \src "libresoc.v:109894.9-109894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:109912.3-109930.6" + process $proc$libresoc.v:109912$4256 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:109913.5-109913.29" + switch \initial + attribute \src "libresoc.v:109913.9-109913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:109931.3-109949.6" + process $proc$libresoc.v:109931$4257 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:109932.5-109932.29" + switch \initial + attribute \src "libresoc.v:109932.9-109932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub24_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:109955.1-112021.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:111708.3-111759.6" + wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:111760.3-111811.6" + wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:111084.3-111135.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:111292.3-111343.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:110356.3-110407.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:110408.3-110459.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:111032.3-111083.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:111240.3-111291.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:111448.3-111499.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:110304.3-110355.6" + wire width 14 $0\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:111812.3-111863.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:111864.3-111915.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:111916.3-111967.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:110876.3-110927.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:111136.3-111187.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:111188.3-111239.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:111500.3-111551.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:110824.3-110875.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:111604.3-111655.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:111968.3-112019.6" + wire width 3 $0\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:110980.3-111031.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:111396.3-111447.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:111656.3-111707.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:111552.3-111603.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:111344.3-111395.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:110720.3-110771.6" + wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:110772.3-110823.6" + wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:110460.3-110511.6" + wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:110512.3-110563.6" + wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:110564.3-110615.6" + wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:110668.3-110719.6" + wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110616.3-110667.6" + wire width 3 $0\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:110928.3-110979.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:109956.7-109956.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111708.3-111759.6" + wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:111760.3-111811.6" + wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:111084.3-111135.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:111292.3-111343.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:110356.3-110407.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:110408.3-110459.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:111032.3-111083.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:111240.3-111291.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:111448.3-111499.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:110304.3-110355.6" + wire width 14 $1\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:111812.3-111863.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:111864.3-111915.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:111916.3-111967.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:110876.3-110927.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:111136.3-111187.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:111188.3-111239.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:111500.3-111551.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:110824.3-110875.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:111604.3-111655.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:111968.3-112019.6" + wire width 3 $1\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:110980.3-111031.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:111396.3-111447.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:111656.3-111707.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:111552.3-111603.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:111344.3-111395.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:110720.3-110771.6" + wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:110772.3-110823.6" + wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:110460.3-110511.6" + wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:110512.3-110563.6" + wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:110564.3-110615.6" + wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:110668.3-110719.6" + wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110616.3-110667.6" + wire width 3 $1\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:110928.3-110979.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub26_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub26_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub26_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub26_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub26_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub26_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub26_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub26_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub26_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub26_upd + attribute \src "libresoc.v:109956.7-109956.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:109956.7-109956.20" + process $proc$libresoc.v:109956$4292 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110304.3-110355.6" + process $proc$libresoc.v:110304$4259 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:110305.5-110305.29" + switch \initial + attribute \src "libresoc.v:110305.9-110305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 + case + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] + end + attribute \src "libresoc.v:110356.3-110407.6" + process $proc$libresoc.v:110356$4260 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:110357.5-110357.29" + switch \initial + attribute \src "libresoc.v:110357.9-110357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:110408.3-110459.6" + process $proc$libresoc.v:110408$4261 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:110409.5-110409.29" + switch \initial + attribute \src "libresoc.v:110409.9-110409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:110460.3-110511.6" + process $proc$libresoc.v:110460$4262 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:110461.5-110461.29" + switch \initial + attribute \src "libresoc.v:110461.9-110461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] + end + attribute \src "libresoc.v:110512.3-110563.6" + process $proc$libresoc.v:110512$4263 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:110513.5-110513.29" + switch \initial + attribute \src "libresoc.v:110513.9-110513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] + end + attribute \src "libresoc.v:110564.3-110615.6" + process $proc$libresoc.v:110564$4264 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:110565.5-110565.29" + switch \initial + attribute \src "libresoc.v:110565.9-110565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 + case + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] + end + attribute \src "libresoc.v:110616.3-110667.6" + process $proc$libresoc.v:110616$4265 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:110617.5-110617.29" + switch \initial + attribute \src "libresoc.v:110617.9-110617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] + end + attribute \src "libresoc.v:110668.3-110719.6" + process $proc$libresoc.v:110668$4266 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110669.5-110669.29" + switch \initial + attribute \src "libresoc.v:110669.9-110669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] + end + attribute \src "libresoc.v:110720.3-110771.6" + process $proc$libresoc.v:110720$4267 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:110721.5-110721.29" + switch \initial + attribute \src "libresoc.v:110721.9-110721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] + end + attribute \src "libresoc.v:110772.3-110823.6" + process $proc$libresoc.v:110772$4268 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:110773.5-110773.29" + switch \initial + attribute \src "libresoc.v:110773.9-110773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] + end + attribute \src "libresoc.v:110824.3-110875.6" + process $proc$libresoc.v:110824$4269 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:110825.5-110825.29" + switch \initial + attribute \src "libresoc.v:110825.9-110825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:110876.3-110927.6" + process $proc$libresoc.v:110876$4270 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:110877.5-110877.29" + switch \initial + attribute \src "libresoc.v:110877.9-110877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:110928.3-110979.6" + process $proc$libresoc.v:110928$4271 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:110929.5-110929.29" + switch \initial + attribute \src "libresoc.v:110929.9-110929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "libresoc.v:110980.3-111031.6" + process $proc$libresoc.v:110980$4272 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:110981.5-110981.29" + switch \initial + attribute \src "libresoc.v:110981.9-110981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:111032.3-111083.6" + process $proc$libresoc.v:111032$4273 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:111033.5-111033.29" + switch \initial + attribute \src "libresoc.v:111033.9-111033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:111084.3-111135.6" + process $proc$libresoc.v:111084$4274 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:111085.5-111085.29" + switch \initial + attribute \src "libresoc.v:111085.9-111085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100010 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "libresoc.v:111136.3-111187.6" + process $proc$libresoc.v:111136$4275 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:111137.5-111137.29" + switch \initial + attribute \src "libresoc.v:111137.9-111137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:111188.3-111239.6" + process $proc$libresoc.v:111188$4276 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:111189.5-111189.29" + switch \initial + attribute \src "libresoc.v:111189.9-111189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:111240.3-111291.6" + process $proc$libresoc.v:111240$4277 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:111241.5-111241.29" + switch \initial + attribute \src "libresoc.v:111241.9-111241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:111292.3-111343.6" + process $proc$libresoc.v:111292$4278 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:111293.5-111293.29" + switch \initial + attribute \src "libresoc.v:111293.9-111293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + end + attribute \src "libresoc.v:111344.3-111395.6" + process $proc$libresoc.v:111344$4279 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:111345.5-111345.29" + switch \initial + attribute \src "libresoc.v:111345.9-111345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "libresoc.v:111396.3-111447.6" + process $proc$libresoc.v:111396$4280 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:111397.5-111397.29" + switch \initial + attribute \src "libresoc.v:111397.9-111397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + end + attribute \src "libresoc.v:111448.3-111499.6" + process $proc$libresoc.v:111448$4281 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:111449.5-111449.29" + switch \initial + attribute \src "libresoc.v:111449.9-111449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "libresoc.v:111500.3-111551.6" + process $proc$libresoc.v:111500$4282 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:111501.5-111501.29" + switch \initial + attribute \src "libresoc.v:111501.9-111501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:111552.3-111603.6" + process $proc$libresoc.v:111552$4283 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:111553.5-111553.29" + switch \initial + attribute \src "libresoc.v:111553.9-111553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:111604.3-111655.6" + process $proc$libresoc.v:111604$4284 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:111605.5-111605.29" + switch \initial + attribute \src "libresoc.v:111605.9-111605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + end + attribute \src "libresoc.v:111656.3-111707.6" + process $proc$libresoc.v:111656$4285 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:111657.5-111657.29" + switch \initial + attribute \src "libresoc.v:111657.9-111657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:111708.3-111759.6" + process $proc$libresoc.v:111708$4286 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:111709.5-111709.29" + switch \initial + attribute \src "libresoc.v:111709.9-111709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] + end + attribute \src "libresoc.v:111760.3-111811.6" + process $proc$libresoc.v:111760$4287 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:111761.5-111761.29" + switch \initial + attribute \src "libresoc.v:111761.9-111761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] + end + attribute \src "libresoc.v:111812.3-111863.6" + process $proc$libresoc.v:111812$4288 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:111813.5-111813.29" + switch \initial + attribute \src "libresoc.v:111813.9-111813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:111864.3-111915.6" + process $proc$libresoc.v:111864$4289 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:111865.5-111865.29" + switch \initial + attribute \src "libresoc.v:111865.9-111865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:111916.3-111967.6" + process $proc$libresoc.v:111916$4290 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:111917.5-111917.29" + switch \initial + attribute \src "libresoc.v:111917.9-111917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:111968.3-112019.6" + process $proc$libresoc.v:111968$4291 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:111969.5-111969.29" + switch \initial + attribute \src "libresoc.v:111969.9-111969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub26_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:112025.1-113002.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:112887.3-112905.6" + wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:112906.3-112924.6" + wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:112659.3-112677.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:112735.3-112753.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:112393.3-112411.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:112412.3-112430.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:112640.3-112658.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:112716.3-112734.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:112792.3-112810.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:112374.3-112392.6" + wire width 14 $0\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:112925.3-112943.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:112944.3-112962.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:112963.3-112981.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:112583.3-112601.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:112678.3-112696.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:112697.3-112715.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:112811.3-112829.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:112564.3-112582.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:112849.3-112867.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:112982.3-113000.6" + wire width 3 $0\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:112621.3-112639.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:112773.3-112791.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:112868.3-112886.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:112830.3-112848.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:112754.3-112772.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:112526.3-112544.6" + wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:112545.3-112563.6" + wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:112431.3-112449.6" + wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:112450.3-112468.6" + wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:112469.3-112487.6" + wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:112507.3-112525.6" + wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112488.3-112506.6" + wire width 3 $0\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:112602.3-112620.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:112026.7-112026.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112887.3-112905.6" + wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:112906.3-112924.6" + wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:112659.3-112677.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:112735.3-112753.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:112393.3-112411.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:112412.3-112430.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:112640.3-112658.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:112716.3-112734.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:112792.3-112810.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:112374.3-112392.6" + wire width 14 $1\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:112925.3-112943.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:112944.3-112962.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:112963.3-112981.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:112583.3-112601.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:112678.3-112696.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:112697.3-112715.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:112811.3-112829.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:112564.3-112582.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:112849.3-112867.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:112982.3-113000.6" + wire width 3 $1\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:112621.3-112639.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:112773.3-112791.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:112868.3-112886.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:112830.3-112848.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:112754.3-112772.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:112526.3-112544.6" + wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:112545.3-112563.6" + wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:112431.3-112449.6" + wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:112450.3-112468.6" + wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:112469.3-112487.6" + wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:112507.3-112525.6" + wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112488.3-112506.6" + wire width 3 $1\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:112602.3-112620.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub27_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub27_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub27_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub27_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub27_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub27_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub27_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub27_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub27_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub27_upd + attribute \src "libresoc.v:112026.7-112026.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:112026.7-112026.20" + process $proc$libresoc.v:112026$4326 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:112374.3-112392.6" + process $proc$libresoc.v:112374$4293 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:112375.5-112375.29" + switch \initial + attribute \src "libresoc.v:112375.9-112375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 + case + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] + end + attribute \src "libresoc.v:112393.3-112411.6" + process $proc$libresoc.v:112393$4294 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:112394.5-112394.29" + switch \initial + attribute \src "libresoc.v:112394.9-112394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:112412.3-112430.6" + process $proc$libresoc.v:112412$4295 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:112413.5-112413.29" + switch \initial + attribute \src "libresoc.v:112413.9-112413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + attribute \src "libresoc.v:112431.3-112449.6" + process $proc$libresoc.v:112431$4296 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:112432.5-112432.29" + switch \initial + attribute \src "libresoc.v:112432.9-112432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] + end + attribute \src "libresoc.v:112450.3-112468.6" + process $proc$libresoc.v:112450$4297 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:112451.5-112451.29" + switch \initial + attribute \src "libresoc.v:112451.9-112451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 + case + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] + end + attribute \src "libresoc.v:112469.3-112487.6" + process $proc$libresoc.v:112469$4298 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:112470.5-112470.29" + switch \initial + attribute \src "libresoc.v:112470.9-112470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 + case + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] + end + attribute \src "libresoc.v:112488.3-112506.6" + process $proc$libresoc.v:112488$4299 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:112489.5-112489.29" + switch \initial + attribute \src "libresoc.v:112489.9-112489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] + end + attribute \src "libresoc.v:112507.3-112525.6" + process $proc$libresoc.v:112507$4300 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112508.5-112508.29" + switch \initial + attribute \src "libresoc.v:112508.9-112508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] + end + attribute \src "libresoc.v:112526.3-112544.6" + process $proc$libresoc.v:112526$4301 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:112527.5-112527.29" + switch \initial + attribute \src "libresoc.v:112527.9-112527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] + end + attribute \src "libresoc.v:112545.3-112563.6" + process $proc$libresoc.v:112545$4302 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:112546.5-112546.29" + switch \initial + attribute \src "libresoc.v:112546.9-112546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] + end + attribute \src "libresoc.v:112564.3-112582.6" + process $proc$libresoc.v:112564$4303 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:112565.5-112565.29" + switch \initial + attribute \src "libresoc.v:112565.9-112565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + end + attribute \src "libresoc.v:112583.3-112601.6" + process $proc$libresoc.v:112583$4304 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:112584.5-112584.29" + switch \initial + attribute \src "libresoc.v:112584.9-112584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:112602.3-112620.6" + process $proc$libresoc.v:112602$4305 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:112603.5-112603.29" + switch \initial + attribute \src "libresoc.v:112603.9-112603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "libresoc.v:112621.3-112639.6" + process $proc$libresoc.v:112621$4306 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:112622.5-112622.29" + switch \initial + attribute \src "libresoc.v:112622.9-112622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:112640.3-112658.6" + process $proc$libresoc.v:112640$4307 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:112641.5-112641.29" + switch \initial + attribute \src "libresoc.v:112641.9-112641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:112659.3-112677.6" + process $proc$libresoc.v:112659$4308 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:112660.5-112660.29" + switch \initial + attribute \src "libresoc.v:112660.9-112660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "libresoc.v:112678.3-112696.6" + process $proc$libresoc.v:112678$4309 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:112679.5-112679.29" + switch \initial + attribute \src "libresoc.v:112679.9-112679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:112697.3-112715.6" + process $proc$libresoc.v:112697$4310 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:112698.5-112698.29" + switch \initial + attribute \src "libresoc.v:112698.9-112698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "libresoc.v:112716.3-112734.6" + process $proc$libresoc.v:112716$4311 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:112717.5-112717.29" + switch \initial + attribute \src "libresoc.v:112717.9-112717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:112735.3-112753.6" + process $proc$libresoc.v:112735$4312 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:112736.5-112736.29" + switch \initial + attribute \src "libresoc.v:112736.9-112736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "libresoc.v:112754.3-112772.6" + process $proc$libresoc.v:112754$4313 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:112755.5-112755.29" + switch \initial + attribute \src "libresoc.v:112755.9-112755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "libresoc.v:112773.3-112791.6" + process $proc$libresoc.v:112773$4314 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:112774.5-112774.29" + switch \initial + attribute \src "libresoc.v:112774.9-112774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + end + attribute \src "libresoc.v:112792.3-112810.6" + process $proc$libresoc.v:112792$4315 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:112793.5-112793.29" + switch \initial + attribute \src "libresoc.v:112793.9-112793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "libresoc.v:112811.3-112829.6" + process $proc$libresoc.v:112811$4316 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:112812.5-112812.29" + switch \initial + attribute \src "libresoc.v:112812.9-112812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:112830.3-112848.6" + process $proc$libresoc.v:112830$4317 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:112831.5-112831.29" + switch \initial + attribute \src "libresoc.v:112831.9-112831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:112849.3-112867.6" + process $proc$libresoc.v:112849$4318 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:112850.5-112850.29" + switch \initial + attribute \src "libresoc.v:112850.9-112850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:112868.3-112886.6" + process $proc$libresoc.v:112868$4319 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:112869.5-112869.29" + switch \initial + attribute \src "libresoc.v:112869.9-112869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:112887.3-112905.6" + process $proc$libresoc.v:112887$4320 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:112888.5-112888.29" + switch \initial + attribute \src "libresoc.v:112888.9-112888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] + end + attribute \src "libresoc.v:112906.3-112924.6" + process $proc$libresoc.v:112906$4321 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:112907.5-112907.29" + switch \initial + attribute \src "libresoc.v:112907.9-112907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] + end + attribute \src "libresoc.v:112925.3-112943.6" + process $proc$libresoc.v:112925$4322 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:112926.5-112926.29" + switch \initial + attribute \src "libresoc.v:112926.9-112926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:112944.3-112962.6" + process $proc$libresoc.v:112944$4323 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:112945.5-112945.29" + switch \initial + attribute \src "libresoc.v:112945.9-112945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:112963.3-112981.6" + process $proc$libresoc.v:112963$4324 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:112964.5-112964.29" + switch \initial + attribute \src "libresoc.v:112964.9-112964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:112982.3-113000.6" + process $proc$libresoc.v:112982$4325 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:112983.5-112983.29" + switch \initial + attribute \src "libresoc.v:112983.9-112983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub27_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:113006.1-114577.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:114354.3-114390.6" + wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:114391.3-114427.6" + wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:113910.3-113946.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:114058.3-114094.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:113392.3-113428.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:113429.3-113465.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:113873.3-113909.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:114021.3-114057.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:114169.3-114205.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:113355.3-113391.6" + wire width 14 $0\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:114428.3-114464.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:114465.3-114501.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:114502.3-114538.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:113762.3-113798.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:113947.3-113983.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:113984.3-114020.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:114206.3-114242.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:113725.3-113761.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:114280.3-114316.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:114539.3-114575.6" + wire width 3 $0\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:113836.3-113872.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:114132.3-114168.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:114317.3-114353.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:114243.3-114279.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:114095.3-114131.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:113651.3-113687.6" + wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:113688.3-113724.6" + wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:113466.3-113502.6" + wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:113503.3-113539.6" + wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:113540.3-113576.6" + wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:113614.3-113650.6" + wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113577.3-113613.6" + wire width 3 $0\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:113799.3-113835.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:113007.7-113007.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114354.3-114390.6" + wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:114391.3-114427.6" + wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:113910.3-113946.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:114058.3-114094.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:113392.3-113428.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:113429.3-113465.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:113873.3-113909.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:114021.3-114057.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:114169.3-114205.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:113355.3-113391.6" + wire width 14 $1\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:114428.3-114464.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:114465.3-114501.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:114502.3-114538.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:113762.3-113798.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:113947.3-113983.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:113984.3-114020.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:114206.3-114242.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:113725.3-113761.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:114280.3-114316.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:114539.3-114575.6" + wire width 3 $1\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:113836.3-113872.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:114132.3-114168.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:114317.3-114353.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:114243.3-114279.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:114095.3-114131.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:113651.3-113687.6" + wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:113688.3-113724.6" + wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:113466.3-113502.6" + wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:113503.3-113539.6" + wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:113540.3-113576.6" + wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:113614.3-113650.6" + wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113577.3-113613.6" + wire width 3 $1\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:113799.3-113835.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub28_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub28_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub28_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub28_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub28_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub28_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub28_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub28_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub28_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub28_upd + attribute \src "libresoc.v:113007.7-113007.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:113007.7-113007.20" + process $proc$libresoc.v:113007$4360 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:113355.3-113391.6" + process $proc$libresoc.v:113355$4327 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:113356.5-113356.29" + switch \initial + attribute \src "libresoc.v:113356.9-113356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 + case + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] + end + attribute \src "libresoc.v:113392.3-113428.6" + process $proc$libresoc.v:113392$4328 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:113393.5-113393.29" + switch \initial + attribute \src "libresoc.v:113393.9-113393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:113429.3-113465.6" + process $proc$libresoc.v:113429$4329 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:113430.5-113430.29" + switch \initial + attribute \src "libresoc.v:113430.9-113430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:113466.3-113502.6" + process $proc$libresoc.v:113466$4330 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:113467.5-113467.29" + switch \initial + attribute \src "libresoc.v:113467.9-113467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + case + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] + end + attribute \src "libresoc.v:113503.3-113539.6" + process $proc$libresoc.v:113503$4331 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:113504.5-113504.29" + switch \initial + attribute \src "libresoc.v:113504.9-113504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + case + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] + end + attribute \src "libresoc.v:113540.3-113576.6" + process $proc$libresoc.v:113540$4332 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:113541.5-113541.29" + switch \initial + attribute \src "libresoc.v:113541.9-113541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] + end + attribute \src "libresoc.v:113577.3-113613.6" + process $proc$libresoc.v:113577$4333 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:113578.5-113578.29" + switch \initial + attribute \src "libresoc.v:113578.9-113578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] + end + attribute \src "libresoc.v:113614.3-113650.6" + process $proc$libresoc.v:113614$4334 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113615.5-113615.29" + switch \initial + attribute \src "libresoc.v:113615.9-113615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] + end + attribute \src "libresoc.v:113651.3-113687.6" + process $proc$libresoc.v:113651$4335 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:113652.5-113652.29" + switch \initial + attribute \src "libresoc.v:113652.9-113652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] + end + attribute \src "libresoc.v:113688.3-113724.6" + process $proc$libresoc.v:113688$4336 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:113689.5-113689.29" + switch \initial + attribute \src "libresoc.v:113689.9-113689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] + end + attribute \src "libresoc.v:113725.3-113761.6" + process $proc$libresoc.v:113725$4337 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:113726.5-113726.29" + switch \initial + attribute \src "libresoc.v:113726.9-113726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:113762.3-113798.6" + process $proc$libresoc.v:113762$4338 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:113763.5-113763.29" + switch \initial + attribute \src "libresoc.v:113763.9-113763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:113799.3-113835.6" + process $proc$libresoc.v:113799$4339 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:113800.5-113800.29" + switch \initial + attribute \src "libresoc.v:113800.9-113800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "libresoc.v:113836.3-113872.6" + process $proc$libresoc.v:113836$4340 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:113837.5-113837.29" + switch \initial + attribute \src "libresoc.v:113837.9-113837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:113873.3-113909.6" + process $proc$libresoc.v:113873$4341 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:113874.5-113874.29" + switch \initial + attribute \src "libresoc.v:113874.9-113874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + end + attribute \src "libresoc.v:113910.3-113946.6" + process $proc$libresoc.v:113910$4342 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:113911.5-113911.29" + switch \initial + attribute \src "libresoc.v:113911.9-113911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010001 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + end + attribute \src "libresoc.v:113947.3-113983.6" + process $proc$libresoc.v:113947$4343 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:113948.5-113948.29" + switch \initial + attribute \src "libresoc.v:113948.9-113948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:113984.3-114020.6" + process $proc$libresoc.v:113984$4344 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:113985.5-113985.29" + switch \initial + attribute \src "libresoc.v:113985.9-113985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:114021.3-114057.6" + process $proc$libresoc.v:114021$4345 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:114022.5-114022.29" + switch \initial + attribute \src "libresoc.v:114022.9-114022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:114058.3-114094.6" + process $proc$libresoc.v:114058$4346 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:114059.5-114059.29" + switch \initial + attribute \src "libresoc.v:114059.9-114059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "libresoc.v:114095.3-114131.6" + process $proc$libresoc.v:114095$4347 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:114096.5-114096.29" + switch \initial + attribute \src "libresoc.v:114096.9-114096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + end + attribute \src "libresoc.v:114132.3-114168.6" + process $proc$libresoc.v:114132$4348 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:114133.5-114133.29" + switch \initial + attribute \src "libresoc.v:114133.9-114133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "libresoc.v:114169.3-114205.6" + process $proc$libresoc.v:114169$4349 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:114170.5-114170.29" + switch \initial + attribute \src "libresoc.v:114170.9-114170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "libresoc.v:114206.3-114242.6" + process $proc$libresoc.v:114206$4350 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:114207.5-114207.29" + switch \initial + attribute \src "libresoc.v:114207.9-114207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:114243.3-114279.6" + process $proc$libresoc.v:114243$4351 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:114244.5-114244.29" + switch \initial + attribute \src "libresoc.v:114244.9-114244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:114280.3-114316.6" + process $proc$libresoc.v:114280$4352 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:114281.5-114281.29" + switch \initial + attribute \src "libresoc.v:114281.9-114281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "libresoc.v:114317.3-114353.6" + process $proc$libresoc.v:114317$4353 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:114318.5-114318.29" + switch \initial + attribute \src "libresoc.v:114318.9-114318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + end + attribute \src "libresoc.v:114354.3-114390.6" + process $proc$libresoc.v:114354$4354 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:114355.5-114355.29" + switch \initial + attribute \src "libresoc.v:114355.9-114355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] + end + attribute \src "libresoc.v:114391.3-114427.6" + process $proc$libresoc.v:114391$4355 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:114392.5-114392.29" + switch \initial + attribute \src "libresoc.v:114392.9-114392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] + end + attribute \src "libresoc.v:114428.3-114464.6" + process $proc$libresoc.v:114428$4356 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:114429.5-114429.29" + switch \initial + attribute \src "libresoc.v:114429.9-114429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:114465.3-114501.6" + process $proc$libresoc.v:114465$4357 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:114466.5-114466.29" + switch \initial + attribute \src "libresoc.v:114466.9-114466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:114502.3-114538.6" + process $proc$libresoc.v:114502$4358 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:114503.5-114503.29" + switch \initial + attribute \src "libresoc.v:114503.9-114503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "libresoc.v:114539.3-114575.6" + process $proc$libresoc.v:114539$4359 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:114540.5-114540.29" + switch \initial + attribute \src "libresoc.v:114540.9-114540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub28_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:114581.1-115360.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "libresoc.v:115281.3-115293.6" + wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:115294.3-115306.6" + wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:115125.3-115137.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:115177.3-115189.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:114943.3-114955.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:114956.3-114968.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:115112.3-115124.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:115164.3-115176.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:115216.3-115228.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:114930.3-114942.6" + wire width 14 $0\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:115307.3-115319.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:115320.3-115332.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:115333.3-115345.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:115073.3-115085.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:115138.3-115150.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:115151.3-115163.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:115229.3-115241.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:115060.3-115072.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:115255.3-115267.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:115346.3-115358.6" + wire width 3 $0\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:115099.3-115111.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:115203.3-115215.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:115268.3-115280.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:115242.3-115254.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:115190.3-115202.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:115034.3-115046.6" + wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:115047.3-115059.6" + wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:114969.3-114981.6" + wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:114982.3-114994.6" + wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:114995.3-115007.6" + wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:115021.3-115033.6" + wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115008.3-115020.6" + wire width 3 $0\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:115086.3-115098.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:114582.7-114582.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115281.3-115293.6" + wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:115294.3-115306.6" + wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:115125.3-115137.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:115177.3-115189.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:114943.3-114955.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:114956.3-114968.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:115112.3-115124.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:115164.3-115176.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:115216.3-115228.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:114930.3-114942.6" + wire width 14 $1\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:115307.3-115319.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:115320.3-115332.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:115333.3-115345.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:115073.3-115085.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:115138.3-115150.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:115151.3-115163.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:115229.3-115241.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:115060.3-115072.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:115255.3-115267.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:115346.3-115358.6" + wire width 3 $1\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:115099.3-115111.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:115203.3-115215.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:115268.3-115280.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:115242.3-115254.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:115190.3-115202.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:115034.3-115046.6" + wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:115047.3-115059.6" + wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:114969.3-114981.6" + wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:114982.3-114994.6" + wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:114995.3-115007.6" + wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:115021.3-115033.6" + wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115008.3-115020.6" + wire width 3 $1\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:115086.3-115098.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub4_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub4_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub4_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub4_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub4_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub4_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub4_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub4_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub4_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub4_upd + attribute \src "libresoc.v:114582.7-114582.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:114582.7-114582.20" + process $proc$libresoc.v:114582$4394 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114930.3-114942.6" + process $proc$libresoc.v:114930$4361 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:114931.5-114931.29" + switch \initial + attribute \src "libresoc.v:114931.9-114931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 + case + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] + end + attribute \src "libresoc.v:114943.3-114955.6" + process $proc$libresoc.v:114943$4362 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:114944.5-114944.29" + switch \initial + attribute \src "libresoc.v:114944.9-114944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "libresoc.v:114956.3-114968.6" + process $proc$libresoc.v:114956$4363 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:114957.5-114957.29" + switch \initial + attribute \src "libresoc.v:114957.9-114957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + attribute \src "libresoc.v:114969.3-114981.6" + process $proc$libresoc.v:114969$4364 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:114970.5-114970.29" + switch \initial + attribute \src "libresoc.v:114970.9-114970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] + end + attribute \src "libresoc.v:114982.3-114994.6" + process $proc$libresoc.v:114982$4365 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:114983.5-114983.29" + switch \initial + attribute \src "libresoc.v:114983.9-114983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] + end + attribute \src "libresoc.v:114995.3-115007.6" + process $proc$libresoc.v:114995$4366 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:114996.5-114996.29" + switch \initial + attribute \src "libresoc.v:114996.9-114996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] + end + attribute \src "libresoc.v:115008.3-115020.6" + process $proc$libresoc.v:115008$4367 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:115009.5-115009.29" + switch \initial + attribute \src "libresoc.v:115009.9-115009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] + end + attribute \src "libresoc.v:115021.3-115033.6" + process $proc$libresoc.v:115021$4368 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115022.5-115022.29" + switch \initial + attribute \src "libresoc.v:115022.9-115022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] + end + attribute \src "libresoc.v:115034.3-115046.6" + process $proc$libresoc.v:115034$4369 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:115035.5-115035.29" + switch \initial + attribute \src "libresoc.v:115035.9-115035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] + end + attribute \src "libresoc.v:115047.3-115059.6" + process $proc$libresoc.v:115047$4370 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:115048.5-115048.29" + switch \initial + attribute \src "libresoc.v:115048.9-115048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] + end + attribute \src "libresoc.v:115060.3-115072.6" + process $proc$libresoc.v:115060$4371 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:115061.5-115061.29" + switch \initial + attribute \src "libresoc.v:115061.9-115061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "libresoc.v:115073.3-115085.6" + process $proc$libresoc.v:115073$4372 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:115074.5-115074.29" + switch \initial + attribute \src "libresoc.v:115074.9-115074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:115086.3-115098.6" + process $proc$libresoc.v:115086$4373 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:115087.5-115087.29" + switch \initial + attribute \src "libresoc.v:115087.9-115087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:115099.3-115111.6" + process $proc$libresoc.v:115099$4374 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:115100.5-115100.29" + switch \initial + attribute \src "libresoc.v:115100.9-115100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:115112.3-115124.6" + process $proc$libresoc.v:115112$4375 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:115113.5-115113.29" + switch \initial + attribute \src "libresoc.v:115113.9-115113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "libresoc.v:115125.3-115137.6" + process $proc$libresoc.v:115125$4376 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:115126.5-115126.29" + switch \initial + attribute \src "libresoc.v:115126.9-115126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001111 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:115138.3-115150.6" + process $proc$libresoc.v:115138$4377 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:115139.5-115139.29" + switch \initial + attribute \src "libresoc.v:115139.9-115139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:115151.3-115163.6" + process $proc$libresoc.v:115151$4378 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:115152.5-115152.29" + switch \initial + attribute \src "libresoc.v:115152.9-115152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:115164.3-115176.6" + process $proc$libresoc.v:115164$4379 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:115165.5-115165.29" + switch \initial + attribute \src "libresoc.v:115165.9-115165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:115177.3-115189.6" + process $proc$libresoc.v:115177$4380 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:115178.5-115178.29" + switch \initial + attribute \src "libresoc.v:115178.9-115178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:115190.3-115202.6" + process $proc$libresoc.v:115190$4381 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:115191.5-115191.29" + switch \initial + attribute \src "libresoc.v:115191.9-115191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:115203.3-115215.6" + process $proc$libresoc.v:115203$4382 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:115204.5-115204.29" + switch \initial + attribute \src "libresoc.v:115204.9-115204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:115216.3-115228.6" + process $proc$libresoc.v:115216$4383 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:115217.5-115217.29" + switch \initial + attribute \src "libresoc.v:115217.9-115217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:115229.3-115241.6" + process $proc$libresoc.v:115229$4384 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:115230.5-115230.29" + switch \initial + attribute \src "libresoc.v:115230.9-115230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "libresoc.v:115242.3-115254.6" + process $proc$libresoc.v:115242$4385 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:115243.5-115243.29" + switch \initial + attribute \src "libresoc.v:115243.9-115243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:115255.3-115267.6" + process $proc$libresoc.v:115255$4386 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:115256.5-115256.29" + switch \initial + attribute \src "libresoc.v:115256.9-115256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:115268.3-115280.6" + process $proc$libresoc.v:115268$4387 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:115269.5-115269.29" + switch \initial + attribute \src "libresoc.v:115269.9-115269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:115281.3-115293.6" + process $proc$libresoc.v:115281$4388 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:115282.5-115282.29" + switch \initial + attribute \src "libresoc.v:115282.9-115282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] + end + attribute \src "libresoc.v:115294.3-115306.6" + process $proc$libresoc.v:115294$4389 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:115295.5-115295.29" + switch \initial + attribute \src "libresoc.v:115295.9-115295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] + end + attribute \src "libresoc.v:115307.3-115319.6" + process $proc$libresoc.v:115307$4390 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:115308.5-115308.29" + switch \initial + attribute \src "libresoc.v:115308.9-115308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:115320.3-115332.6" + process $proc$libresoc.v:115320$4391 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:115321.5-115321.29" + switch \initial + attribute \src "libresoc.v:115321.9-115321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "libresoc.v:115333.3-115345.6" + process $proc$libresoc.v:115333$4392 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:115334.5-115334.29" + switch \initial + attribute \src "libresoc.v:115334.9-115334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:115346.3-115358.6" + process $proc$libresoc.v:115346$4393 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:115347.5-115347.29" + switch \initial + attribute \src "libresoc.v:115347.9-115347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:115364.1-117133.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:116874.3-116916.6" + wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:116917.3-116959.6" + wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:116358.3-116400.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:116530.3-116572.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:115756.3-115798.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:115799.3-115841.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:116315.3-116357.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:116487.3-116529.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:116659.3-116701.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:115713.3-115755.6" + wire width 14 $0\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:116960.3-117002.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:117003.3-117045.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:117046.3-117088.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:116186.3-116228.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:116401.3-116443.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:116444.3-116486.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:116702.3-116744.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:116143.3-116185.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:116788.3-116830.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:117089.3-117131.6" + wire width 3 $0\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:116272.3-116314.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:116616.3-116658.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:116831.3-116873.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:116745.3-116787.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:116573.3-116615.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:116057.3-116099.6" + wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:116100.3-116142.6" + wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:115842.3-115884.6" + wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:115885.3-115927.6" + wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:115928.3-115970.6" + wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:116014.3-116056.6" + wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:115971.3-116013.6" + wire width 3 $0\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:116229.3-116271.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:115365.7-115365.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116874.3-116916.6" + wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:116917.3-116959.6" + wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:116358.3-116400.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:116530.3-116572.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:115756.3-115798.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:115799.3-115841.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:116315.3-116357.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:116487.3-116529.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:116659.3-116701.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:115713.3-115755.6" + wire width 14 $1\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:116960.3-117002.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:117003.3-117045.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:117046.3-117088.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:116186.3-116228.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:116401.3-116443.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:116444.3-116486.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:116702.3-116744.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:116143.3-116185.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:116788.3-116830.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:117089.3-117131.6" + wire width 3 $1\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:116272.3-116314.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:116616.3-116658.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:116831.3-116873.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:116745.3-116787.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:116573.3-116615.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:116057.3-116099.6" + wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:116100.3-116142.6" + wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:115842.3-115884.6" + wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:115885.3-115927.6" + wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:115928.3-115970.6" + wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:116014.3-116056.6" + wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:115971.3-116013.6" + wire width 3 $1\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:116229.3-116271.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub8_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub8_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub8_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub8_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub8_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub8_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub8_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub8_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub8_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub8_upd + attribute \src "libresoc.v:115365.7-115365.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:115365.7-115365.20" + process $proc$libresoc.v:115365$4428 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115713.3-115755.6" + process $proc$libresoc.v:115713$4395 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:115714.5-115714.29" + switch \initial + attribute \src "libresoc.v:115714.9-115714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 + case + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] + end + attribute \src "libresoc.v:115756.3-115798.6" + process $proc$libresoc.v:115756$4396 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:115757.5-115757.29" + switch \initial + attribute \src "libresoc.v:115757.9-115757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:115799.3-115841.6" + process $proc$libresoc.v:115799$4397 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:115800.5-115800.29" + switch \initial + attribute \src "libresoc.v:115800.9-115800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + end + attribute \src "libresoc.v:115842.3-115884.6" + process $proc$libresoc.v:115842$4398 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:115843.5-115843.29" + switch \initial + attribute \src "libresoc.v:115843.9-115843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] + end + attribute \src "libresoc.v:115885.3-115927.6" + process $proc$libresoc.v:115885$4399 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:115886.5-115886.29" + switch \initial + attribute \src "libresoc.v:115886.9-115886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] + end + attribute \src "libresoc.v:115928.3-115970.6" + process $proc$libresoc.v:115928$4400 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:115929.5-115929.29" + switch \initial + attribute \src "libresoc.v:115929.9-115929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] + end + attribute \src "libresoc.v:115971.3-116013.6" + process $proc$libresoc.v:115971$4401 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:115972.5-115972.29" + switch \initial + attribute \src "libresoc.v:115972.9-115972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] + end + attribute \src "libresoc.v:116014.3-116056.6" + process $proc$libresoc.v:116014$4402 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:116015.5-116015.29" + switch \initial + attribute \src "libresoc.v:116015.9-116015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] + end + attribute \src "libresoc.v:116057.3-116099.6" + process $proc$libresoc.v:116057$4403 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:116058.5-116058.29" + switch \initial + attribute \src "libresoc.v:116058.9-116058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] + end + attribute \src "libresoc.v:116100.3-116142.6" + process $proc$libresoc.v:116100$4404 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:116101.5-116101.29" + switch \initial + attribute \src "libresoc.v:116101.9-116101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] + end + attribute \src "libresoc.v:116143.3-116185.6" + process $proc$libresoc.v:116143$4405 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:116144.5-116144.29" + switch \initial + attribute \src "libresoc.v:116144.9-116144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:116186.3-116228.6" + process $proc$libresoc.v:116186$4406 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:116187.5-116187.29" + switch \initial + attribute \src "libresoc.v:116187.9-116187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:116229.3-116271.6" + process $proc$libresoc.v:116229$4407 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:116230.5-116230.29" + switch \initial + attribute \src "libresoc.v:116230.9-116230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "libresoc.v:116272.3-116314.6" + process $proc$libresoc.v:116272$4408 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:116273.5-116273.29" + switch \initial + attribute \src "libresoc.v:116273.9-116273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:116315.3-116357.6" + process $proc$libresoc.v:116315$4409 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:116316.5-116316.29" + switch \initial + attribute \src "libresoc.v:116316.9-116316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "libresoc.v:116358.3-116400.6" + process $proc$libresoc.v:116358$4410 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:116359.5-116359.29" + switch \initial + attribute \src "libresoc.v:116359.9-116359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "libresoc.v:116401.3-116443.6" + process $proc$libresoc.v:116401$4411 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:116402.5-116402.29" + switch \initial + attribute \src "libresoc.v:116402.9-116402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:116444.3-116486.6" + process $proc$libresoc.v:116444$4412 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:116445.5-116445.29" + switch \initial + attribute \src "libresoc.v:116445.9-116445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:116487.3-116529.6" + process $proc$libresoc.v:116487$4413 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:116488.5-116488.29" + switch \initial + attribute \src "libresoc.v:116488.9-116488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:116530.3-116572.6" + process $proc$libresoc.v:116530$4414 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:116531.5-116531.29" + switch \initial + attribute \src "libresoc.v:116531.9-116531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "libresoc.v:116573.3-116615.6" + process $proc$libresoc.v:116573$4415 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:116574.5-116574.29" + switch \initial + attribute \src "libresoc.v:116574.9-116574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:116616.3-116658.6" + process $proc$libresoc.v:116616$4416 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:116617.5-116617.29" + switch \initial + attribute \src "libresoc.v:116617.9-116617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "libresoc.v:116659.3-116701.6" + process $proc$libresoc.v:116659$4417 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:116660.5-116660.29" + switch \initial + attribute \src "libresoc.v:116660.9-116660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "libresoc.v:116702.3-116744.6" + process $proc$libresoc.v:116702$4418 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:116703.5-116703.29" + switch \initial + attribute \src "libresoc.v:116703.9-116703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:116745.3-116787.6" + process $proc$libresoc.v:116745$4419 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:116746.5-116746.29" + switch \initial + attribute \src "libresoc.v:116746.9-116746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:116788.3-116830.6" + process $proc$libresoc.v:116788$4420 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:116789.5-116789.29" + switch \initial + attribute \src "libresoc.v:116789.9-116789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:116831.3-116873.6" + process $proc$libresoc.v:116831$4421 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:116832.5-116832.29" + switch \initial + attribute \src "libresoc.v:116832.9-116832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "libresoc.v:116874.3-116916.6" + process $proc$libresoc.v:116874$4422 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:116875.5-116875.29" + switch \initial + attribute \src "libresoc.v:116875.9-116875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] + end + attribute \src "libresoc.v:116917.3-116959.6" + process $proc$libresoc.v:116917$4423 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:116918.5-116918.29" + switch \initial + attribute \src "libresoc.v:116918.9-116918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] + end + attribute \src "libresoc.v:116960.3-117002.6" + process $proc$libresoc.v:116960$4424 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:116961.5-116961.29" + switch \initial + attribute \src "libresoc.v:116961.9-116961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:117003.3-117045.6" + process $proc$libresoc.v:117003$4425 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:117004.5-117004.29" + switch \initial + attribute \src "libresoc.v:117004.9-117004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:117046.3-117088.6" + process $proc$libresoc.v:117046$4426 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:117047.5-117047.29" + switch \initial + attribute \src "libresoc.v:117047.9-117047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "libresoc.v:117089.3-117131.6" + process $proc$libresoc.v:117089$4427 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:117090.5-117090.29" + switch \initial + attribute \src "libresoc.v:117090.9-117090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:117137.1-119302.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:118971.3-119025.6" + wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:119026.3-119080.6" + wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:118311.3-118365.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:118531.3-118585.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:117541.3-117595.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:117596.3-117650.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:118256.3-118310.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:118476.3-118530.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:118696.3-118750.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:117486.3-117540.6" + wire width 14 $0\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:119081.3-119135.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:119136.3-119190.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:119191.3-119245.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:118091.3-118145.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:118366.3-118420.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:118421.3-118475.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:118751.3-118805.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:118036.3-118090.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:118861.3-118915.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:119246.3-119300.6" + wire width 3 $0\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:118201.3-118255.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:118641.3-118695.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:118916.3-118970.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:118806.3-118860.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:118586.3-118640.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:117926.3-117980.6" + wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:117981.3-118035.6" + wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:117651.3-117705.6" + wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:117706.3-117760.6" + wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:117761.3-117815.6" + wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:117871.3-117925.6" + wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117816.3-117870.6" + wire width 3 $0\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:118146.3-118200.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:117138.7-117138.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118971.3-119025.6" + wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:119026.3-119080.6" + wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:118311.3-118365.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:118531.3-118585.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:117541.3-117595.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:117596.3-117650.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:118256.3-118310.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:118476.3-118530.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:118696.3-118750.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:117486.3-117540.6" + wire width 14 $1\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:119081.3-119135.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:119136.3-119190.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:119191.3-119245.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:118091.3-118145.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:118366.3-118420.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:118421.3-118475.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:118751.3-118805.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:118036.3-118090.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:118861.3-118915.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:119246.3-119300.6" + wire width 3 $1\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:118201.3-118255.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:118641.3-118695.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:118916.3-118970.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:118806.3-118860.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:118586.3-118640.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:117926.3-117980.6" + wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:117981.3-118035.6" + wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:117651.3-117705.6" + wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:117706.3-117760.6" + wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:117761.3-117815.6" + wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:117871.3-117925.6" + wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117816.3-117870.6" + wire width 3 $1\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:118146.3-118200.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec31_dec_sub9_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec31_dec_sub9_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub9_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub9_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec31_dec_sub9_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec31_dec_sub9_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec31_dec_sub9_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec31_dec_sub9_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub9_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub9_upd + attribute \src "libresoc.v:117138.7-117138.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 5 \opcode_switch + attribute \src "libresoc.v:117138.7-117138.20" + process $proc$libresoc.v:117138$4462 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:117486.3-117540.6" + process $proc$libresoc.v:117486$4429 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:117487.5-117487.29" + switch \initial + attribute \src "libresoc.v:117487.9-117487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 + case + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] + end + attribute \src "libresoc.v:117541.3-117595.6" + process $proc$libresoc.v:117541$4430 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:117542.5-117542.29" + switch \initial + attribute \src "libresoc.v:117542.9-117542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:117596.3-117650.6" + process $proc$libresoc.v:117596$4431 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:117597.5-117597.29" + switch \initial + attribute \src "libresoc.v:117597.9-117597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:117651.3-117705.6" + process $proc$libresoc.v:117651$4432 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:117652.5-117652.29" + switch \initial + attribute \src "libresoc.v:117652.9-117652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] + end + attribute \src "libresoc.v:117706.3-117760.6" + process $proc$libresoc.v:117706$4433 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:117707.5-117707.29" + switch \initial + attribute \src "libresoc.v:117707.9-117707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] + end + attribute \src "libresoc.v:117761.3-117815.6" + process $proc$libresoc.v:117761$4434 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:117762.5-117762.29" + switch \initial + attribute \src "libresoc.v:117762.9-117762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] + end + attribute \src "libresoc.v:117816.3-117870.6" + process $proc$libresoc.v:117816$4435 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:117817.5-117817.29" + switch \initial + attribute \src "libresoc.v:117817.9-117817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] + end + attribute \src "libresoc.v:117871.3-117925.6" + process $proc$libresoc.v:117871$4436 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117872.5-117872.29" + switch \initial + attribute \src "libresoc.v:117872.9-117872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] + end + attribute \src "libresoc.v:117926.3-117980.6" + process $proc$libresoc.v:117926$4437 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:117927.5-117927.29" + switch \initial + attribute \src "libresoc.v:117927.9-117927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] + end + attribute \src "libresoc.v:117981.3-118035.6" + process $proc$libresoc.v:117981$4438 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:117982.5-117982.29" + switch \initial + attribute \src "libresoc.v:117982.9-117982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] + end + attribute \src "libresoc.v:118036.3-118090.6" + process $proc$libresoc.v:118036$4439 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:118037.5-118037.29" + switch \initial + attribute \src "libresoc.v:118037.9-118037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:118091.3-118145.6" + process $proc$libresoc.v:118091$4440 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:118092.5-118092.29" + switch \initial + attribute \src "libresoc.v:118092.9-118092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:118146.3-118200.6" + process $proc$libresoc.v:118146$4441 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:118147.5-118147.29" + switch \initial + attribute \src "libresoc.v:118147.9-118147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + end + attribute \src "libresoc.v:118201.3-118255.6" + process $proc$libresoc.v:118201$4442 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:118202.5-118202.29" + switch \initial + attribute \src "libresoc.v:118202.9-118202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:118256.3-118310.6" + process $proc$libresoc.v:118256$4443 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:118257.5-118257.29" + switch \initial + attribute \src "libresoc.v:118257.9-118257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + end + attribute \src "libresoc.v:118311.3-118365.6" + process $proc$libresoc.v:118311$4444 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:118312.5-118312.29" + switch \initial + attribute \src "libresoc.v:118312.9-118312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + end + attribute \src "libresoc.v:118366.3-118420.6" + process $proc$libresoc.v:118366$4445 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:118367.5-118367.29" + switch \initial + attribute \src "libresoc.v:118367.9-118367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:118421.3-118475.6" + process $proc$libresoc.v:118421$4446 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:118422.5-118422.29" + switch \initial + attribute \src "libresoc.v:118422.9-118422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:118476.3-118530.6" + process $proc$libresoc.v:118476$4447 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:118477.5-118477.29" + switch \initial + attribute \src "libresoc.v:118477.9-118477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:118531.3-118585.6" + process $proc$libresoc.v:118531$4448 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:118532.5-118532.29" + switch \initial + attribute \src "libresoc.v:118532.9-118532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + end + attribute \src "libresoc.v:118586.3-118640.6" + process $proc$libresoc.v:118586$4449 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:118587.5-118587.29" + switch \initial + attribute \src "libresoc.v:118587.9-118587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + end + attribute \src "libresoc.v:118641.3-118695.6" + process $proc$libresoc.v:118641$4450 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:118642.5-118642.29" + switch \initial + attribute \src "libresoc.v:118642.9-118642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + end + attribute \src "libresoc.v:118696.3-118750.6" + process $proc$libresoc.v:118696$4451 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:118697.5-118697.29" + switch \initial + attribute \src "libresoc.v:118697.9-118697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + end + attribute \src "libresoc.v:118751.3-118805.6" + process $proc$libresoc.v:118751$4452 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:118752.5-118752.29" + switch \initial + attribute \src "libresoc.v:118752.9-118752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:118806.3-118860.6" + process $proc$libresoc.v:118806$4453 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:118807.5-118807.29" + switch \initial + attribute \src "libresoc.v:118807.9-118807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:118861.3-118915.6" + process $proc$libresoc.v:118861$4454 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:118862.5-118862.29" + switch \initial + attribute \src "libresoc.v:118862.9-118862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + end + attribute \src "libresoc.v:118916.3-118970.6" + process $proc$libresoc.v:118916$4455 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:118917.5-118917.29" + switch \initial + attribute \src "libresoc.v:118917.9-118917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + end + attribute \src "libresoc.v:118971.3-119025.6" + process $proc$libresoc.v:118971$4456 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:118972.5-118972.29" + switch \initial + attribute \src "libresoc.v:118972.9-118972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] + end + attribute \src "libresoc.v:119026.3-119080.6" + process $proc$libresoc.v:119026$4457 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:119027.5-119027.29" + switch \initial + attribute \src "libresoc.v:119027.9-119027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] + end + attribute \src "libresoc.v:119081.3-119135.6" + process $proc$libresoc.v:119081$4458 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:119082.5-119082.29" + switch \initial + attribute \src "libresoc.v:119082.9-119082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:119136.3-119190.6" + process $proc$libresoc.v:119136$4459 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:119137.5-119137.29" + switch \initial + attribute \src "libresoc.v:119137.9-119137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:119191.3-119245.6" + process $proc$libresoc.v:119191$4460 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:119192.5-119192.29" + switch \initial + attribute \src "libresoc.v:119192.9-119192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "libresoc.v:119246.3-119300.6" + process $proc$libresoc.v:119246$4461 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:119247.5-119247.29" + switch \initial + attribute \src "libresoc.v:119247.9-119247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:119306.1-120184.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:120087.3-120102.6" + wire width 2 $0\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:120103.3-120118.6" + wire width 2 $0\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:119895.3-119910.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:119959.3-119974.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:119671.3-119686.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:119687.3-119702.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:119879.3-119894.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:119943.3-119958.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:120007.3-120022.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:119655.3-119670.6" + wire width 14 $0\dec58_function_unit[13:0] + attribute \src "libresoc.v:120119.3-120134.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:120135.3-120150.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:120151.3-120166.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:119831.3-119846.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:119911.3-119926.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:119927.3-119942.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:120023.3-120038.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:119815.3-119830.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:120055.3-120070.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:120167.3-120182.6" + wire width 3 $0\dec58_out_sel[2:0] + attribute \src "libresoc.v:119863.3-119878.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:119991.3-120006.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:120071.3-120086.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:120039.3-120054.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:119975.3-119990.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:119783.3-119798.6" + wire width 3 $0\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:119799.3-119814.6" + wire width 3 $0\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:119703.3-119718.6" + wire width 3 $0\dec58_sv_in1[2:0] + attribute \src "libresoc.v:119719.3-119734.6" + wire width 3 $0\dec58_sv_in2[2:0] + attribute \src "libresoc.v:119735.3-119750.6" + wire width 3 $0\dec58_sv_in3[2:0] + attribute \src "libresoc.v:119767.3-119782.6" + wire width 3 $0\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119751.3-119766.6" + wire width 3 $0\dec58_sv_out[2:0] + attribute \src "libresoc.v:119847.3-119862.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:119307.7-119307.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120087.3-120102.6" + wire width 2 $1\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:120103.3-120118.6" + wire width 2 $1\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:119895.3-119910.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:119959.3-119974.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:119671.3-119686.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:119687.3-119702.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:119879.3-119894.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:119943.3-119958.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:120007.3-120022.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:119655.3-119670.6" + wire width 14 $1\dec58_function_unit[13:0] + attribute \src "libresoc.v:120119.3-120134.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:120135.3-120150.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:120151.3-120166.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:119831.3-119846.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:119911.3-119926.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:119927.3-119942.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:120023.3-120038.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:119815.3-119830.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:120055.3-120070.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:120167.3-120182.6" + wire width 3 $1\dec58_out_sel[2:0] + attribute \src "libresoc.v:119863.3-119878.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:119991.3-120006.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:120071.3-120086.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:120039.3-120054.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:119975.3-119990.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:119783.3-119798.6" + wire width 3 $1\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:119799.3-119814.6" + wire width 3 $1\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:119703.3-119718.6" + wire width 3 $1\dec58_sv_in1[2:0] + attribute \src "libresoc.v:119719.3-119734.6" + wire width 3 $1\dec58_sv_in2[2:0] + attribute \src "libresoc.v:119735.3-119750.6" + wire width 3 $1\dec58_sv_in3[2:0] + attribute \src "libresoc.v:119767.3-119782.6" + wire width 3 $1\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119751.3-119766.6" + wire width 3 $1\dec58_sv_out[2:0] + attribute \src "libresoc.v:119847.3-119862.6" + wire width 2 $1\dec58_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec58_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec58_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec58_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec58_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec58_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec58_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec58_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec58_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec58_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec58_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec58_upd + attribute \src "libresoc.v:119307.7-119307.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 2 \opcode_switch + attribute \src "libresoc.v:119307.7-119307.20" + process $proc$libresoc.v:119307$4496 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119655.3-119670.6" + process $proc$libresoc.v:119655$4463 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] + attribute \src "libresoc.v:119656.5-119656.29" + switch \initial + attribute \src "libresoc.v:119656.9-119656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[13:0] 14'00000000000100 + case + assign $1\dec58_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[13:0] + end + attribute \src "libresoc.v:119671.3-119686.6" + process $proc$libresoc.v:119671$4464 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:119672.5-119672.29" + switch \initial + attribute \src "libresoc.v:119672.9-119672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:119687.3-119702.6" + process $proc$libresoc.v:119687$4465 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:119688.5-119688.29" + switch \initial + attribute \src "libresoc.v:119688.9-119688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + attribute \src "libresoc.v:119703.3-119718.6" + process $proc$libresoc.v:119703$4466 + assign { } { } + assign { } { } + assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] + attribute \src "libresoc.v:119704.5-119704.29" + switch \initial + attribute \src "libresoc.v:119704.9-119704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'010 + case + assign $1\dec58_sv_in1[2:0] 3'000 + end + sync always + update \dec58_sv_in1 $0\dec58_sv_in1[2:0] + end + attribute \src "libresoc.v:119719.3-119734.6" + process $proc$libresoc.v:119719$4467 + assign { } { } + assign { } { } + assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] + attribute \src "libresoc.v:119720.5-119720.29" + switch \initial + attribute \src "libresoc.v:119720.9-119720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + case + assign $1\dec58_sv_in2[2:0] 3'000 + end + sync always + update \dec58_sv_in2 $0\dec58_sv_in2[2:0] + end + attribute \src "libresoc.v:119735.3-119750.6" + process $proc$libresoc.v:119735$4468 + assign { } { } + assign { } { } + assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] + attribute \src "libresoc.v:119736.5-119736.29" + switch \initial + attribute \src "libresoc.v:119736.9-119736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + case + assign $1\dec58_sv_in3[2:0] 3'000 + end + sync always + update \dec58_sv_in3 $0\dec58_sv_in3[2:0] + end + attribute \src "libresoc.v:119751.3-119766.6" + process $proc$libresoc.v:119751$4469 + assign { } { } + assign { } { } + assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] + attribute \src "libresoc.v:119752.5-119752.29" + switch \initial + attribute \src "libresoc.v:119752.9-119752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + case + assign $1\dec58_sv_out[2:0] 3'000 + end + sync always + update \dec58_sv_out $0\dec58_sv_out[2:0] + end + attribute \src "libresoc.v:119767.3-119782.6" + process $proc$libresoc.v:119767$4470 + assign { } { } + assign { } { } + assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119768.5-119768.29" + switch \initial + attribute \src "libresoc.v:119768.9-119768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'000 + case + assign $1\dec58_sv_out2[2:0] 3'000 + end + sync always + update \dec58_sv_out2 $0\dec58_sv_out2[2:0] + end + attribute \src "libresoc.v:119783.3-119798.6" + process $proc$libresoc.v:119783$4471 + assign { } { } + assign { } { } + assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:119784.5-119784.29" + switch \initial + attribute \src "libresoc.v:119784.9-119784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + case + assign $1\dec58_sv_cr_in[2:0] 3'000 + end + sync always + update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] + end + attribute \src "libresoc.v:119799.3-119814.6" + process $proc$libresoc.v:119799$4472 + assign { } { } + assign { } { } + assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:119800.5-119800.29" + switch \initial + attribute \src "libresoc.v:119800.9-119800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + case + assign $1\dec58_sv_cr_out[2:0] 3'000 + end + sync always + update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] + end + attribute \src "libresoc.v:119815.3-119830.6" + process $proc$libresoc.v:119815$4473 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:119816.5-119816.29" + switch \initial + attribute \src "libresoc.v:119816.9-119816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:119831.3-119846.6" + process $proc$libresoc.v:119831$4474 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:119832.5-119832.29" + switch \initial + attribute \src "libresoc.v:119832.9-119832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:119847.3-119862.6" + process $proc$libresoc.v:119847$4475 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:119848.5-119848.29" + switch \initial + attribute \src "libresoc.v:119848.9-119848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:119863.3-119878.6" + process $proc$libresoc.v:119863$4476 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:119864.5-119864.29" + switch \initial + attribute \src "libresoc.v:119864.9-119864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:119879.3-119894.6" + process $proc$libresoc.v:119879$4477 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:119880.5-119880.29" + switch \initial + attribute \src "libresoc.v:119880.9-119880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:119895.3-119910.6" + process $proc$libresoc.v:119895$4478 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:119896.5-119896.29" + switch \initial + attribute \src "libresoc.v:119896.9-119896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "libresoc.v:119911.3-119926.6" + process $proc$libresoc.v:119911$4479 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:119912.5-119912.29" + switch \initial + attribute \src "libresoc.v:119912.9-119912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:119927.3-119942.6" + process $proc$libresoc.v:119927$4480 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:119928.5-119928.29" + switch \initial + attribute \src "libresoc.v:119928.9-119928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:119943.3-119958.6" + process $proc$libresoc.v:119943$4481 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:119944.5-119944.29" + switch \initial + attribute \src "libresoc.v:119944.9-119944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:119959.3-119974.6" + process $proc$libresoc.v:119959$4482 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:119960.5-119960.29" + switch \initial + attribute \src "libresoc.v:119960.9-119960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:119975.3-119990.6" + process $proc$libresoc.v:119975$4483 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:119976.5-119976.29" + switch \initial + attribute \src "libresoc.v:119976.9-119976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:119991.3-120006.6" + process $proc$libresoc.v:119991$4484 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:119992.5-119992.29" + switch \initial + attribute \src "libresoc.v:119992.9-119992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:120007.3-120022.6" + process $proc$libresoc.v:120007$4485 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:120008.5-120008.29" + switch \initial + attribute \src "libresoc.v:120008.9-120008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:120023.3-120038.6" + process $proc$libresoc.v:120023$4486 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:120024.5-120024.29" + switch \initial + attribute \src "libresoc.v:120024.9-120024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:120039.3-120054.6" + process $proc$libresoc.v:120039$4487 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:120040.5-120040.29" + switch \initial + attribute \src "libresoc.v:120040.9-120040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:120055.3-120070.6" + process $proc$libresoc.v:120055$4488 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:120056.5-120056.29" + switch \initial + attribute \src "libresoc.v:120056.9-120056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:120071.3-120086.6" + process $proc$libresoc.v:120071$4489 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:120072.5-120072.29" + switch \initial + attribute \src "libresoc.v:120072.9-120072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:120087.3-120102.6" + process $proc$libresoc.v:120087$4490 + assign { } { } + assign { } { } + assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:120088.5-120088.29" + switch \initial + attribute \src "libresoc.v:120088.9-120088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'10 + case + assign $1\dec58_SV_Etype[1:0] 2'00 + end + sync always + update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] + end + attribute \src "libresoc.v:120103.3-120118.6" + process $proc$libresoc.v:120103$4491 + assign { } { } + assign { } { } + assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:120104.5-120104.29" + switch \initial + attribute \src "libresoc.v:120104.9-120104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + case + assign $1\dec58_SV_Ptype[1:0] 2'00 + end + sync always + update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] + end + attribute \src "libresoc.v:120119.3-120134.6" + process $proc$libresoc.v:120119$4492 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:120120.5-120120.29" + switch \initial + attribute \src "libresoc.v:120120.9-120120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:120135.3-120150.6" + process $proc$libresoc.v:120135$4493 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:120136.5-120136.29" + switch \initial + attribute \src "libresoc.v:120136.9-120136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:120151.3-120166.6" + process $proc$libresoc.v:120151$4494 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:120152.5-120152.29" + switch \initial + attribute \src "libresoc.v:120152.9-120152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:120167.3-120182.6" + process $proc$libresoc.v:120167$4495 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] + attribute \src "libresoc.v:120168.5-120168.29" + switch \initial + attribute \src "libresoc.v:120168.9-120168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[2:0] 3'001 + case + assign $1\dec58_out_sel[2:0] 3'000 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:120188.1-120967.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:120888.3-120900.6" + wire width 2 $0\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:120901.3-120913.6" + wire width 2 $0\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:120732.3-120744.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:120784.3-120796.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:120550.3-120562.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:120563.3-120575.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:120719.3-120731.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:120771.3-120783.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:120823.3-120835.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:120537.3-120549.6" + wire width 14 $0\dec62_function_unit[13:0] + attribute \src "libresoc.v:120914.3-120926.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:120927.3-120939.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:120940.3-120952.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:120680.3-120692.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:120745.3-120757.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:120758.3-120770.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:120836.3-120848.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:120667.3-120679.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:120862.3-120874.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:120953.3-120965.6" + wire width 3 $0\dec62_out_sel[2:0] + attribute \src "libresoc.v:120706.3-120718.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:120810.3-120822.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:120875.3-120887.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:120849.3-120861.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:120797.3-120809.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:120641.3-120653.6" + wire width 3 $0\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:120654.3-120666.6" + wire width 3 $0\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:120576.3-120588.6" + wire width 3 $0\dec62_sv_in1[2:0] + attribute \src "libresoc.v:120589.3-120601.6" + wire width 3 $0\dec62_sv_in2[2:0] + attribute \src "libresoc.v:120602.3-120614.6" + wire width 3 $0\dec62_sv_in3[2:0] + attribute \src "libresoc.v:120628.3-120640.6" + wire width 3 $0\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120615.3-120627.6" + wire width 3 $0\dec62_sv_out[2:0] + attribute \src "libresoc.v:120693.3-120705.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:120189.7-120189.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120888.3-120900.6" + wire width 2 $1\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:120901.3-120913.6" + wire width 2 $1\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:120732.3-120744.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:120784.3-120796.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:120550.3-120562.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:120563.3-120575.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:120719.3-120731.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:120771.3-120783.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:120823.3-120835.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:120537.3-120549.6" + wire width 14 $1\dec62_function_unit[13:0] + attribute \src "libresoc.v:120914.3-120926.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:120927.3-120939.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:120940.3-120952.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:120680.3-120692.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:120745.3-120757.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:120758.3-120770.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:120836.3-120848.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:120667.3-120679.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:120862.3-120874.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:120953.3-120965.6" + wire width 3 $1\dec62_out_sel[2:0] + attribute \src "libresoc.v:120706.3-120718.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:120810.3-120822.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:120875.3-120887.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:120849.3-120861.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:120797.3-120809.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:120641.3-120653.6" + wire width 3 $1\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:120654.3-120666.6" + wire width 3 $1\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:120576.3-120588.6" + wire width 3 $1\dec62_sv_in1[2:0] + attribute \src "libresoc.v:120589.3-120601.6" + wire width 3 $1\dec62_sv_in2[2:0] + attribute \src "libresoc.v:120602.3-120614.6" + wire width 3 $1\dec62_sv_in3[2:0] + attribute \src "libresoc.v:120628.3-120640.6" + wire width 3 $1\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120615.3-120627.6" + wire width 3 $1\dec62_sv_out[2:0] + attribute \src "libresoc.v:120693.3-120705.6" + wire width 2 $1\dec62_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 5 \dec62_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 6 \dec62_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 11 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 12 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 7 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 8 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 9 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 10 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec62_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec62_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec62_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 13 \dec62_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 14 \dec62_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 15 \dec62_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 16 \dec62_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec62_sv_out2 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec62_upd + attribute \src "libresoc.v:120189.7-120189.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" + wire width 2 \opcode_switch + attribute \src "libresoc.v:120189.7-120189.20" + process $proc$libresoc.v:120189$4530 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:120537.3-120549.6" + process $proc$libresoc.v:120537$4497 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] + attribute \src "libresoc.v:120538.5-120538.29" + switch \initial + attribute \src "libresoc.v:120538.9-120538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[13:0] 14'00000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[13:0] 14'00000000000100 + case + assign $1\dec62_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[13:0] + end + attribute \src "libresoc.v:120550.3-120562.6" + process $proc$libresoc.v:120550$4498 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:120551.5-120551.29" + switch \initial + attribute \src "libresoc.v:120551.9-120551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:120563.3-120575.6" + process $proc$libresoc.v:120563$4499 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:120564.5-120564.29" + switch \initial + attribute \src "libresoc.v:120564.9-120564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + attribute \src "libresoc.v:120576.3-120588.6" + process $proc$libresoc.v:120576$4500 + assign { } { } + assign { } { } + assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] + attribute \src "libresoc.v:120577.5-120577.29" + switch \initial + attribute \src "libresoc.v:120577.9-120577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_in1[2:0] 3'011 + case + assign $1\dec62_sv_in1[2:0] 3'000 + end + sync always + update \dec62_sv_in1 $0\dec62_sv_in1[2:0] + end + attribute \src "libresoc.v:120589.3-120601.6" + process $proc$libresoc.v:120589$4501 + assign { } { } + assign { } { } + assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] + attribute \src "libresoc.v:120590.5-120590.29" + switch \initial + attribute \src "libresoc.v:120590.9-120590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_in2[2:0] 3'000 + case + assign $1\dec62_sv_in2[2:0] 3'000 + end + sync always + update \dec62_sv_in2 $0\dec62_sv_in2[2:0] + end + attribute \src "libresoc.v:120602.3-120614.6" + process $proc$libresoc.v:120602$4502 + assign { } { } + assign { } { } + assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] + attribute \src "libresoc.v:120603.5-120603.29" + switch \initial + attribute \src "libresoc.v:120603.9-120603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_in3[2:0] 3'010 + case + assign $1\dec62_sv_in3[2:0] 3'000 + end + sync always + update \dec62_sv_in3 $0\dec62_sv_in3[2:0] + end + attribute \src "libresoc.v:120615.3-120627.6" + process $proc$libresoc.v:120615$4503 + assign { } { } + assign { } { } + assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] + attribute \src "libresoc.v:120616.5-120616.29" + switch \initial + attribute \src "libresoc.v:120616.9-120616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_out[2:0] 3'000 + case + assign $1\dec62_sv_out[2:0] 3'000 + end + sync always + update \dec62_sv_out $0\dec62_sv_out[2:0] + end + attribute \src "libresoc.v:120628.3-120640.6" + process $proc$libresoc.v:120628$4504 + assign { } { } + assign { } { } + assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120629.5-120629.29" + switch \initial + attribute \src "libresoc.v:120629.9-120629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_out2[2:0] 3'001 + case + assign $1\dec62_sv_out2[2:0] 3'000 + end + sync always + update \dec62_sv_out2 $0\dec62_sv_out2[2:0] + end + attribute \src "libresoc.v:120641.3-120653.6" + process $proc$libresoc.v:120641$4505 + assign { } { } + assign { } { } + assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:120642.5-120642.29" + switch \initial + attribute \src "libresoc.v:120642.9-120642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_cr_in[2:0] 3'000 + case + assign $1\dec62_sv_cr_in[2:0] 3'000 + end + sync always + update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] + end + attribute \src "libresoc.v:120654.3-120666.6" + process $proc$libresoc.v:120654$4506 + assign { } { } + assign { } { } + assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:120655.5-120655.29" + switch \initial + attribute \src "libresoc.v:120655.9-120655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_cr_out[2:0] 3'000 + case + assign $1\dec62_sv_cr_out[2:0] 3'000 + end + sync always + update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] + end + attribute \src "libresoc.v:120667.3-120679.6" + process $proc$libresoc.v:120667$4507 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:120668.5-120668.29" + switch \initial + attribute \src "libresoc.v:120668.9-120668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:120680.3-120692.6" + process $proc$libresoc.v:120680$4508 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:120681.5-120681.29" + switch \initial + attribute \src "libresoc.v:120681.9-120681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:120693.3-120705.6" + process $proc$libresoc.v:120693$4509 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:120694.5-120694.29" + switch \initial + attribute \src "libresoc.v:120694.9-120694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:120706.3-120718.6" + process $proc$libresoc.v:120706$4510 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:120707.5-120707.29" + switch \initial + attribute \src "libresoc.v:120707.9-120707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:120719.3-120731.6" + process $proc$libresoc.v:120719$4511 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:120720.5-120720.29" + switch \initial + attribute \src "libresoc.v:120720.9-120720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:120732.3-120744.6" + process $proc$libresoc.v:120732$4512 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:120733.5-120733.29" + switch \initial + attribute \src "libresoc.v:120733.9-120733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10110000 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:120745.3-120757.6" + process $proc$libresoc.v:120745$4513 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:120746.5-120746.29" + switch \initial + attribute \src "libresoc.v:120746.9-120746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:120758.3-120770.6" + process $proc$libresoc.v:120758$4514 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:120759.5-120759.29" + switch \initial + attribute \src "libresoc.v:120759.9-120759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:120771.3-120783.6" + process $proc$libresoc.v:120771$4515 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:120772.5-120772.29" + switch \initial + attribute \src "libresoc.v:120772.9-120772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:120784.3-120796.6" + process $proc$libresoc.v:120784$4516 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:120785.5-120785.29" + switch \initial + attribute \src "libresoc.v:120785.9-120785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:120797.3-120809.6" + process $proc$libresoc.v:120797$4517 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:120798.5-120798.29" + switch \initial + attribute \src "libresoc.v:120798.9-120798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:120810.3-120822.6" + process $proc$libresoc.v:120810$4518 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:120811.5-120811.29" + switch \initial + attribute \src "libresoc.v:120811.9-120811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:120823.3-120835.6" + process $proc$libresoc.v:120823$4519 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:120824.5-120824.29" + switch \initial + attribute \src "libresoc.v:120824.9-120824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:120836.3-120848.6" + process $proc$libresoc.v:120836$4520 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:120837.5-120837.29" + switch \initial + attribute \src "libresoc.v:120837.9-120837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:120849.3-120861.6" + process $proc$libresoc.v:120849$4521 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:120850.5-120850.29" + switch \initial + attribute \src "libresoc.v:120850.9-120850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:120862.3-120874.6" + process $proc$libresoc.v:120862$4522 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:120863.5-120863.29" + switch \initial + attribute \src "libresoc.v:120863.9-120863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:120875.3-120887.6" + process $proc$libresoc.v:120875$4523 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:120876.5-120876.29" + switch \initial + attribute \src "libresoc.v:120876.9-120876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:120888.3-120900.6" + process $proc$libresoc.v:120888$4524 + assign { } { } + assign { } { } + assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:120889.5-120889.29" + switch \initial + attribute \src "libresoc.v:120889.9-120889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_SV_Etype[1:0] 2'01 + case + assign $1\dec62_SV_Etype[1:0] 2'00 + end + sync always + update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] + end + attribute \src "libresoc.v:120901.3-120913.6" + process $proc$libresoc.v:120901$4525 + assign { } { } + assign { } { } + assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:120902.5-120902.29" + switch \initial + attribute \src "libresoc.v:120902.9-120902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_SV_Ptype[1:0] 2'10 + case + assign $1\dec62_SV_Ptype[1:0] 2'00 + end + sync always + update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] + end + attribute \src "libresoc.v:120914.3-120926.6" + process $proc$libresoc.v:120914$4526 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:120915.5-120915.29" + switch \initial + attribute \src "libresoc.v:120915.9-120915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:120927.3-120939.6" + process $proc$libresoc.v:120927$4527 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:120928.5-120928.29" + switch \initial + attribute \src "libresoc.v:120928.9-120928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:120940.3-120952.6" + process $proc$libresoc.v:120940$4528 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:120941.5-120941.29" + switch \initial + attribute \src "libresoc.v:120941.9-120941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:120953.3-120965.6" + process $proc$libresoc.v:120953$4529 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] + attribute \src "libresoc.v:120954.5-120954.29" + switch \initial + attribute \src "libresoc.v:120954.9-120954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[2:0] 3'000 + case + assign $1\dec62_out_sel[2:0] 3'000 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:120971.1-121554.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" +attribute \generator "nMigen" +module \dec_ALU + attribute \src "libresoc.v:121517.3-121531.6" + wire width 14 $0\ALU__fn_unit[13:0] + attribute \src "libresoc.v:121504.3-121516.6" + wire width 7 $0\ALU__insn_type[6:0] + attribute \src "libresoc.v:121489.3-121503.6" + wire $0\ALU__write_cr0[0:0] + attribute \src "libresoc.v:120972.7-120972.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:121517.3-121531.6" + wire width 14 $1\ALU__fn_unit[13:0] + attribute \src "libresoc.v:121504.3-121516.6" + wire width 7 $1\ALU__insn_type[6:0] + attribute \src "libresoc.v:121489.3-121503.6" + wire $1\ALU__write_cr0[0:0] + attribute \src "libresoc.v:121405.18-121405.113" + wire $and$libresoc.v:121405$4531_Y + attribute \src "libresoc.v:121407.18-121407.110" + wire $and$libresoc.v:121407$4533_Y + attribute \src "libresoc.v:121420.18-121420.114" + wire $and$libresoc.v:121420$4546_Y + attribute \src "libresoc.v:121421.18-121421.116" + wire $and$libresoc.v:121421$4547_Y + attribute \src "libresoc.v:121423.18-121423.114" + wire $and$libresoc.v:121423$4549_Y + attribute \src "libresoc.v:121425.18-121425.110" + wire $and$libresoc.v:121425$4551_Y + attribute \src "libresoc.v:121426.17-121426.112" + wire $and$libresoc.v:121426$4552_Y + attribute \src "libresoc.v:121427.17-121427.114" + wire $and$libresoc.v:121427$4553_Y + attribute \src "libresoc.v:121408.18-121408.126" + wire $eq$libresoc.v:121408$4534_Y + attribute \src "libresoc.v:121409.18-121409.126" + wire $eq$libresoc.v:121409$4535_Y + attribute \src "libresoc.v:121411.18-121411.110" + wire $eq$libresoc.v:121411$4537_Y + attribute \src "libresoc.v:121412.18-121412.110" + wire $eq$libresoc.v:121412$4538_Y + attribute \src "libresoc.v:121414.18-121414.112" + wire $eq$libresoc.v:121414$4540_Y + attribute \src "libresoc.v:121415.17-121415.130" + wire $eq$libresoc.v:121415$4541_Y + attribute \src "libresoc.v:121417.18-121417.110" + wire $eq$libresoc.v:121417$4543_Y + attribute \src "libresoc.v:121419.18-121419.131" + wire $eq$libresoc.v:121419$4545_Y + attribute \src "libresoc.v:121422.18-121422.131" + wire $eq$libresoc.v:121422$4548_Y + attribute \src "libresoc.v:121428.17-121428.130" + wire $eq$libresoc.v:121428$4554_Y + attribute \src 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\enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_ALU_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_ALU_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + wire \dec_ai_sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:120972.7-120972.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121405$4531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:121405$4531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121407$4533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:121407$4533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121420$4546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:121420$4546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121421$4547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121421$4547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121423$4549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:121423$4549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121425$4551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:121425$4551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121426$4552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:121426$4552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121427$4553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121427$4553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121408$4534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:121408$4534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:121409$4535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:121409$4535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121411$4537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:121411$4537_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121412$4538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:121412$4538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121414$4540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:121414$4540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121415$4541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121415$4541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:121417$4543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:121417$4543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121419$4545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121419$4545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121422$4548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121422$4548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121428$4554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121428$4554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121406$4532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121406$4532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121424$4550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121424$4550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:121410$4536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:121410$4536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121413$4539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:121413$4539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121416$4542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:121416$4542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:121418$4544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:121418$4544_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121429.7-121457.4" + cell \dec \dec + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_OE \dec_ALU_OE + connect \ALU_RA \dec_ALU_RA + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_SPR \dec_ALU_SPR + connect \ALU_UI \dec_ALU_UI + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_sh \dec_ALU_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121458.10-121463.4" + cell \dec_ai \dec_ai + connect \ALU_RA \dec_ALU_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121464.10-121475.4" + cell \dec_bi \dec_bi + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_sh \dec_ALU_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121476.10-121482.4" + cell \dec_oe \dec_oe + connect \ALU_OE \dec_ALU_OE + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121483.10-121488.4" + cell \dec_rc \dec_rc + connect \ALU_Rc \dec_ALU_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:120972.7-120972.20" + process $proc$libresoc.v:120972$4558 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:121489.3-121503.6" + process $proc$libresoc.v:121489$4555 + assign { } { } + assign { } { } + assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] + attribute \src "libresoc.v:121490.5-121490.29" + switch \initial + attribute \src "libresoc.v:121490.9-121490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + switch \dec_ALU_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\ALU__write_cr0[0:0] \dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\ALU__write_cr0[0:0] 1'1 + case + assign $1\ALU__write_cr0[0:0] 1'0 + end + sync always + update \ALU__write_cr0 $0\ALU__write_cr0[0:0] + end + attribute \src "libresoc.v:121504.3-121516.6" + process $proc$libresoc.v:121504$4556 + assign { } { } + assign { } { } + assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] + attribute \src "libresoc.v:121505.5-121505.29" + switch \initial + attribute \src "libresoc.v:121505.9-121505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ALU__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ALU__insn_type[6:0] 7'0000000 + case + assign $1\ALU__insn_type[6:0] \dec_ALU_internal_op + end + sync always + update \ALU__insn_type $0\ALU__insn_type[6:0] + end + attribute \src "libresoc.v:121517.3-121531.6" + process $proc$libresoc.v:121517$4557 + assign { } { } + assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] + attribute \src "libresoc.v:121518.5-121518.29" + switch \initial + attribute \src "libresoc.v:121518.9-121518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ALU__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ALU__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ALU__fn_unit[13:0] \dec_ALU_function_unit + end + sync always + update \ALU__fn_unit $0\ALU__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:121405$4531_Y + connect \$12 $not$libresoc.v:121406$4532_Y + connect \$14 $and$libresoc.v:121407$4533_Y + connect \$16 $eq$libresoc.v:121408$4534_Y + connect \$18 $eq$libresoc.v:121409$4535_Y + connect \$20 $or$libresoc.v:121410$4536_Y + connect \$22 $eq$libresoc.v:121411$4537_Y + connect \$24 $eq$libresoc.v:121412$4538_Y + connect \$26 $or$libresoc.v:121413$4539_Y + connect \$28 $eq$libresoc.v:121414$4540_Y + connect \$2 $eq$libresoc.v:121415$4541_Y + connect \$30 $or$libresoc.v:121416$4542_Y + connect \$32 $eq$libresoc.v:121417$4543_Y + connect \$34 $or$libresoc.v:121418$4544_Y + connect \$36 $eq$libresoc.v:121419$4545_Y + connect \$38 $and$libresoc.v:121420$4546_Y + connect \$40 $and$libresoc.v:121421$4547_Y + connect \$42 $eq$libresoc.v:121422$4548_Y + connect \$44 $and$libresoc.v:121423$4549_Y + connect \$46 $not$libresoc.v:121424$4550_Y + connect \$48 $and$libresoc.v:121425$4551_Y + connect \$4 $and$libresoc.v:121426$4552_Y + connect \$6 $and$libresoc.v:121427$4553_Y + connect \$8 $eq$libresoc.v:121428$4554_Y + connect \ALU__is_signed \dec_ALU_sgn + connect \ALU__is_32bit \dec_ALU_is_32b + connect \ALU__output_carry \dec_ALU_cry_out + connect \ALU__input_carry \dec_ALU_cry_in + connect \ALU__invert_out \dec_ALU_inv_out + connect \ALU__invert_in \dec_ALU_inv_a + connect \ALU__data_len \dec_ALU_ldst_len + connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_ALU_in2_sel + connect \ALU__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \dec_ai_sv_nz \sv_a_nz + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_ALU_SPR [4:0] \dec_ALU_SPR [9:5] } + connect \dec_oe_sel_in \dec_ALU_rc_sel + connect \dec_rc_sel_in \dec_ALU_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \ALU__insn \dec_opcode_in +end +attribute \src "libresoc.v:121558.1-122038.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" +attribute \generator "nMigen" +module \dec_BRANCH + attribute \src "libresoc.v:121988.3-122002.6" + wire width 14 $0\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:122013.3-122025.6" + wire width 7 $0\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:122003.3-122012.6" + wire $0\BRANCH__lk[0:0] + attribute \src "libresoc.v:121559.7-121559.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:121988.3-122002.6" + wire width 14 $1\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:122013.3-122025.6" + wire width 7 $1\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:122003.3-122012.6" + wire $1\BRANCH__lk[0:0] + attribute \src "libresoc.v:121920.18-121920.113" + wire $and$libresoc.v:121920$4559_Y + attribute \src "libresoc.v:121922.18-121922.110" + wire $and$libresoc.v:121922$4561_Y + attribute \src "libresoc.v:121935.18-121935.114" + wire $and$libresoc.v:121935$4574_Y + attribute \src "libresoc.v:121936.18-121936.116" + wire $and$libresoc.v:121936$4575_Y + attribute \src "libresoc.v:121938.18-121938.114" + wire $and$libresoc.v:121938$4577_Y + attribute \src "libresoc.v:121940.18-121940.110" + wire $and$libresoc.v:121940$4579_Y + attribute \src "libresoc.v:121941.17-121941.112" + wire $and$libresoc.v:121941$4580_Y + attribute \src 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output 8 \BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 6 \BRANCH__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 \dec_BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_BRANCH_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_BRANCH_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 1 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121920$4559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:121920$4559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121922$4561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:121922$4561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121935$4574 + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:121933$4572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:121933$4572_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121944.13-121966.4" + cell \dec$141 \dec + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_SPR \dec_BRANCH_SPR + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect 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$1\BRANCH__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\BRANCH__fn_unit[13:0] \dec_BRANCH_function_unit + end + sync always + update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] + end + attribute \src "libresoc.v:122003.3-122012.6" + process $proc$libresoc.v:122003$4584 + assign { } { } + assign { } { } + assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] + attribute \src "libresoc.v:122004.5-122004.29" + switch \initial + attribute \src "libresoc.v:122004.9-122004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" + switch \dec_BRANCH_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK + case + assign $1\BRANCH__lk[0:0] 1'0 + end + sync always + update \BRANCH__lk $0\BRANCH__lk[0:0] + end + attribute \src "libresoc.v:122013.3-122025.6" + process $proc$libresoc.v:122013$4585 + assign { } { } + assign { } { } + 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attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + wire \dec_ai_sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:122419.7-122419.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122852$4614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:122852$4614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122854$4616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:122854$4616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122867$4629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:122867$4629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122868$4630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122868$4630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122870$4632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:122870$4632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122872$4634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:122872$4634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122873$4635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:122873$4635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122874$4636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122874$4636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122855$4617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:122855$4617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:122856$4618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:122856$4618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122858$4620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:122858$4620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122859$4621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:122859$4621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122861$4623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122861$4623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122862$4624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122862$4624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:122864$4626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122864$4626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122866$4628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122866$4628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122869$4631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122869$4631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122875$4637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122875$4637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122853$4615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122853$4615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122871$4633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122871$4633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:122857$4619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122857$4619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122860$4622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:122860$4622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122863$4625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:122863$4625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:122865$4627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:122865$4627_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122876.13-122904.4" + cell \dec$153 \dec + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_OE \dec_DIV_OE + connect \DIV_RA \dec_DIV_RA + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_SPR \dec_DIV_SPR + connect \DIV_UI \dec_DIV_UI + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_sh \dec_DIV_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122905.16-122910.4" + cell \dec_ai$156 \dec_ai + connect \DIV_RA \dec_DIV_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122911.16-122922.4" + cell \dec_bi$157 \dec_bi + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_sh \dec_DIV_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122923.16-122929.4" + cell \dec_oe$155 \dec_oe + connect \DIV_OE \dec_DIV_OE + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122930.16-122935.4" + cell \dec_rc$154 \dec_rc + connect \DIV_Rc \dec_DIV_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:122419.7-122419.20" + process $proc$libresoc.v:122419$4641 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:122936.3-122950.6" + process $proc$libresoc.v:122936$4638 + assign { } { } + assign { } { } + assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] + attribute \src "libresoc.v:122937.5-122937.29" + switch \initial + attribute \src "libresoc.v:122937.9-122937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + switch \dec_DIV_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\DIV__write_cr0[0:0] \dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\DIV__write_cr0[0:0] 1'1 + case + assign $1\DIV__write_cr0[0:0] 1'0 + end + sync always + update \DIV__write_cr0 $0\DIV__write_cr0[0:0] + end + attribute \src "libresoc.v:122951.3-122963.6" + process $proc$libresoc.v:122951$4639 + assign { } { } + assign { } { } + assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] + attribute \src "libresoc.v:122952.5-122952.29" + switch \initial + attribute \src "libresoc.v:122952.9-122952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\DIV__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\DIV__insn_type[6:0] 7'0000000 + case + assign $1\DIV__insn_type[6:0] \dec_DIV_internal_op + end + sync always + update \DIV__insn_type $0\DIV__insn_type[6:0] + end + attribute \src "libresoc.v:122964.3-122978.6" + process $proc$libresoc.v:122964$4640 + assign { } { } + assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] + attribute \src "libresoc.v:122965.5-122965.29" + switch \initial + attribute \src "libresoc.v:122965.9-122965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\DIV__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\DIV__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\DIV__fn_unit[13:0] \dec_DIV_function_unit + end + sync always + update \DIV__fn_unit $0\DIV__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:122852$4614_Y + connect \$12 $not$libresoc.v:122853$4615_Y + connect \$14 $and$libresoc.v:122854$4616_Y + connect \$16 $eq$libresoc.v:122855$4617_Y + connect \$18 $eq$libresoc.v:122856$4618_Y + connect \$20 $or$libresoc.v:122857$4619_Y + connect \$22 $eq$libresoc.v:122858$4620_Y + connect \$24 $eq$libresoc.v:122859$4621_Y + connect \$26 $or$libresoc.v:122860$4622_Y + connect \$28 $eq$libresoc.v:122861$4623_Y + connect \$2 $eq$libresoc.v:122862$4624_Y + connect \$30 $or$libresoc.v:122863$4625_Y + connect \$32 $eq$libresoc.v:122864$4626_Y + connect \$34 $or$libresoc.v:122865$4627_Y + connect \$36 $eq$libresoc.v:122866$4628_Y + connect \$38 $and$libresoc.v:122867$4629_Y + connect \$40 $and$libresoc.v:122868$4630_Y + connect \$42 $eq$libresoc.v:122869$4631_Y + connect \$44 $and$libresoc.v:122870$4632_Y + connect \$46 $not$libresoc.v:122871$4633_Y + connect \$48 $and$libresoc.v:122872$4634_Y + connect \$4 $and$libresoc.v:122873$4635_Y + connect \$6 $and$libresoc.v:122874$4636_Y + connect \$8 $eq$libresoc.v:122875$4637_Y + connect \DIV__is_signed \dec_DIV_sgn + connect \DIV__is_32bit \dec_DIV_is_32b + connect \DIV__output_carry \dec_DIV_cry_out + connect \DIV__input_carry \dec_DIV_cry_in + connect \DIV__invert_out \dec_DIV_inv_out + connect \DIV__invert_in \dec_DIV_inv_a + connect \DIV__data_len \dec_DIV_ldst_len + connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_DIV_in2_sel + connect \DIV__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \dec_ai_sv_nz \sv_a_nz + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_DIV_SPR [4:0] \dec_DIV_SPR [9:5] } + connect \dec_oe_sel_in \dec_DIV_rc_sel + connect \dec_rc_sel_in \dec_DIV_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \DIV__insn \dec_opcode_in +end +attribute \src "libresoc.v:123005.1-123566.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" +attribute \generator "nMigen" +module \dec_LDST + attribute \src "libresoc.v:123530.3-123544.6" + wire width 14 $0\LDST__fn_unit[13:0] + attribute \src "libresoc.v:123517.3-123529.6" + wire width 7 $0\LDST__insn_type[6:0] + attribute \src "libresoc.v:123006.7-123006.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:123530.3-123544.6" + wire width 14 $1\LDST__fn_unit[13:0] + attribute \src "libresoc.v:123517.3-123529.6" + wire width 7 $1\LDST__insn_type[6:0] + attribute \src "libresoc.v:123434.18-123434.113" + wire $and$libresoc.v:123434$4642_Y + attribute \src "libresoc.v:123436.18-123436.110" + wire $and$libresoc.v:123436$4644_Y + attribute \src "libresoc.v:123449.18-123449.114" + wire $and$libresoc.v:123449$4657_Y + attribute \src "libresoc.v:123450.18-123450.116" + wire $and$libresoc.v:123450$4658_Y + attribute \src "libresoc.v:123452.18-123452.114" + wire $and$libresoc.v:123452$4660_Y + attribute \src "libresoc.v:123454.18-123454.110" + wire $and$libresoc.v:123454$4662_Y + attribute \src "libresoc.v:123455.17-123455.112" + wire $and$libresoc.v:123455$4663_Y + attribute \src "libresoc.v:123456.17-123456.114" + wire $and$libresoc.v:123456$4664_Y + attribute \src "libresoc.v:123437.18-123437.127" + wire $eq$libresoc.v:123437$4645_Y + attribute \src "libresoc.v:123438.18-123438.127" + wire $eq$libresoc.v:123438$4646_Y + attribute \src "libresoc.v:123440.18-123440.110" + wire $eq$libresoc.v:123440$4648_Y + attribute \src "libresoc.v:123441.18-123441.110" + wire $eq$libresoc.v:123441$4649_Y + attribute \src "libresoc.v:123443.18-123443.112" + wire $eq$libresoc.v:123443$4651_Y + attribute \src "libresoc.v:123444.17-123444.131" + wire $eq$libresoc.v:123444$4652_Y + attribute \src "libresoc.v:123446.18-123446.110" + wire $eq$libresoc.v:123446$4654_Y + attribute \src "libresoc.v:123448.18-123448.132" + wire $eq$libresoc.v:123448$4656_Y + attribute \src "libresoc.v:123451.18-123451.132" + wire $eq$libresoc.v:123451$4659_Y + attribute \src "libresoc.v:123457.17-123457.131" + wire $eq$libresoc.v:123457$4665_Y + attribute \src "libresoc.v:123435.18-123435.110" + wire $not$libresoc.v:123435$4643_Y + attribute \src "libresoc.v:123453.18-123453.110" + wire $not$libresoc.v:123453$4661_Y + attribute \src "libresoc.v:123439.18-123439.110" + wire $or$libresoc.v:123439$4647_Y + attribute \src "libresoc.v:123442.18-123442.110" + wire $or$libresoc.v:123442$4650_Y + attribute \src "libresoc.v:123445.18-123445.110" + wire $or$libresoc.v:123445$4653_Y + attribute \src "libresoc.v:123447.18-123447.110" + wire $or$libresoc.v:123447$4655_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 14 \LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \LDST__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LDST_br + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_LDST_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + wire \dec_ai_sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:123006.7-123006.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123434$4642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:123434$4642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123436$4644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:123436$4644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123449$4657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:123449$4657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123450$4658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123450$4658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123452$4660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:123452$4660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123454$4662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:123454$4662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123455$4663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:123455$4663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123456$4664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123456$4664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123437$4645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:123437$4645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:123438$4646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:123438$4646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123440$4648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:123440$4648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123441$4649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:123441$4649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123443$4651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:123443$4651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:123444$4652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123444$4652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:123446$4654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:123446$4654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:123448$4656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123448$4656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:123451$4659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123451$4659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:123457$4665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123457$4665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:123435$4643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123435$4643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:123453$4661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123453$4661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:123439$4647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:123439$4647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123442$4650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:123442$4650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123445$4653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:123445$4653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:123447$4655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:123447$4655_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123458.13-123485.4" + cell \dec$166 \dec + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_OE \dec_LDST_OE + connect \LDST_RA \dec_LDST_RA + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_SPR \dec_LDST_SPR + connect \LDST_UI \dec_LDST_UI + connect \LDST_br \dec_LDST_br + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_sh \dec_LDST_sh + connect \LDST_upd \dec_LDST_upd + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123486.16-123491.4" + cell \dec_ai$169 \dec_ai + connect \LDST_RA \dec_LDST_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123492.16-123503.4" + cell \dec_bi$170 \dec_bi + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_sh \dec_LDST_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 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"SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src 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attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 3 \LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \LOGICAL__is_32bit + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_LOGICAL_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LOGICAL_cry_out + attribute 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\enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute 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"OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + wire \dec_ai_sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124026$4691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:124026$4691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:124007$4672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:124007$4672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:124008$4673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:124008$4673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124010$4675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:124010$4675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124011$4676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:124011$4676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124013$4678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:124013$4678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124014$4679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:124014$4679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:124016$4681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:124016$4681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124018$4683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:124018$4683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124021$4686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:124021$4686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124027$4692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:124027$4692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124005$4670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:124005$4670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124023$4688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:124023$4688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:124009$4674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:124009$4674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124012$4677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:124012$4677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124015$4680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:124015$4680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:124017$4682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:124017$4682_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124028.13-124056.4" + cell \dec$145 \dec + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_SPR \dec_LOGICAL_SPR + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124057.16-124062.4" + cell \dec_ai$148 \dec_ai + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124063.16-124074.4" + cell \dec_bi$149 \dec_bi + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124075.16-124081.4" + cell \dec_oe$147 \dec_oe + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + 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\dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\LOGICAL__write_cr0[0:0] 1'1 + case + assign $1\LOGICAL__write_cr0[0:0] 1'0 + end + sync always + update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] + end + attribute \src "libresoc.v:124103.3-124115.6" + process $proc$libresoc.v:124103$4694 + assign { } { } + assign { } { } + assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:124104.5-124104.29" + switch \initial + attribute \src "libresoc.v:124104.9-124104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\LOGICAL__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\LOGICAL__insn_type[6:0] 7'0000000 + case + assign $1\LOGICAL__insn_type[6:0] \dec_LOGICAL_internal_op + end + sync always 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\MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_MUL_UI + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_MUL_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:124158.7-124158.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 14 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124531$4697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:124531$4697_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124533$4699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:124533$4699_Y + end + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124551$4717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:124551$4717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124552$4718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:124552$4718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124553$4719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:124553$4719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:124534$4700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:124534$4700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:124535$4701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:124535$4701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124537$4703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:124537$4703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124538$4704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:124538$4704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124540$4706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:124540$4706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124541$4707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:124541$4707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:124543$4709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:124543$4709_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124545$4711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:124545$4711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124548$4714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:124548$4714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124554$4720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:124554$4720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124532$4698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:124532$4698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124550$4716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:124550$4716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:124536$4702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:124536$4702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124539$4705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:124539$4705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124542$4708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:124542$4708_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:124544$4710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:124544$4710_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124555.13-124576.4" + cell \dec$158 \dec + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_OE \dec_MUL_OE + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_SPR \dec_MUL_SPR + connect \MUL_UI \dec_MUL_UI + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_sh \dec_MUL_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124577.16-124588.4" + cell \dec_bi$161 \dec_bi + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_sh \dec_MUL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124589.16-124595.4" + cell \dec_oe$160 \dec_oe + connect \MUL_OE \dec_MUL_OE + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124596.16-124601.4" + cell \dec_rc$159 \dec_rc + connect \MUL_Rc \dec_MUL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:124158.7-124158.20" + process $proc$libresoc.v:124158$4724 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124602.3-124616.6" + process $proc$libresoc.v:124602$4721 + assign { } { } + assign { } { } + assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] + attribute \src "libresoc.v:124603.5-124603.29" + switch \initial + attribute \src "libresoc.v:124603.9-124603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + switch \dec_MUL_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\MUL__write_cr0[0:0] \dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\MUL__write_cr0[0:0] 1'1 + case + assign $1\MUL__write_cr0[0:0] 1'0 + end + sync always + update \MUL__write_cr0 $0\MUL__write_cr0[0:0] + end + attribute \src "libresoc.v:124617.3-124629.6" + process $proc$libresoc.v:124617$4722 + assign { } { } + assign { } { } + assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] + attribute \src "libresoc.v:124618.5-124618.29" + switch \initial + attribute \src "libresoc.v:124618.9-124618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\MUL__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\MUL__insn_type[6:0] 7'0000000 + case + assign $1\MUL__insn_type[6:0] \dec_MUL_internal_op + end + sync always + update \MUL__insn_type $0\MUL__insn_type[6:0] + end + attribute \src "libresoc.v:124630.3-124644.6" + process $proc$libresoc.v:124630$4723 + assign { } { } + assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] + attribute \src "libresoc.v:124631.5-124631.29" + switch \initial + attribute \src "libresoc.v:124631.9-124631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\MUL__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\MUL__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\MUL__fn_unit[13:0] \dec_MUL_function_unit + end + sync always + update \MUL__fn_unit $0\MUL__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:124531$4697_Y + connect \$12 $not$libresoc.v:124532$4698_Y + connect \$14 $and$libresoc.v:124533$4699_Y + connect \$16 $eq$libresoc.v:124534$4700_Y + connect \$18 $eq$libresoc.v:124535$4701_Y + connect \$20 $or$libresoc.v:124536$4702_Y + connect \$22 $eq$libresoc.v:124537$4703_Y + connect \$24 $eq$libresoc.v:124538$4704_Y + connect \$26 $or$libresoc.v:124539$4705_Y + connect \$28 $eq$libresoc.v:124540$4706_Y + connect \$2 $eq$libresoc.v:124541$4707_Y + connect \$30 $or$libresoc.v:124542$4708_Y + connect \$32 $eq$libresoc.v:124543$4709_Y + connect \$34 $or$libresoc.v:124544$4710_Y + connect \$36 $eq$libresoc.v:124545$4711_Y + connect \$38 $and$libresoc.v:124546$4712_Y + connect \$40 $and$libresoc.v:124547$4713_Y + connect \$42 $eq$libresoc.v:124548$4714_Y + connect \$44 $and$libresoc.v:124549$4715_Y + connect \$46 $not$libresoc.v:124550$4716_Y + connect \$48 $and$libresoc.v:124551$4717_Y + connect \$4 $and$libresoc.v:124552$4718_Y + connect \$6 $and$libresoc.v:124553$4719_Y + connect \$8 $eq$libresoc.v:124554$4720_Y + connect \MUL__is_signed \dec_MUL_sgn + connect \MUL__is_32bit \dec_MUL_is_32b + connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_MUL_SPR [4:0] \dec_MUL_SPR [9:5] } + connect \dec_oe_sel_in \dec_MUL_rc_sel + connect \dec_rc_sel_in \dec_MUL_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \MUL__insn \dec_opcode_in +end +attribute \src "libresoc.v:124663.1-125209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" +attribute \generator "nMigen" +module \dec_SHIFT_ROT + attribute \src "libresoc.v:125175.3-125189.6" + wire width 14 $0\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:125162.3-125174.6" + wire width 7 $0\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:125147.3-125161.6" + wire $0\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:124664.7-124664.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125175.3-125189.6" + wire width 14 $1\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:125162.3-125174.6" + wire width 7 $1\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:125147.3-125161.6" + wire $1\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:125072.18-125072.113" + wire $and$libresoc.v:125072$4725_Y + attribute \src "libresoc.v:125074.18-125074.110" + wire $and$libresoc.v:125074$4727_Y + attribute \src "libresoc.v:125087.18-125087.114" + wire $and$libresoc.v:125087$4740_Y + attribute \src "libresoc.v:125088.18-125088.116" + wire $and$libresoc.v:125088$4741_Y + attribute \src "libresoc.v:125090.18-125090.114" + wire $and$libresoc.v:125090$4743_Y + attribute \src "libresoc.v:125092.18-125092.110" + wire $and$libresoc.v:125092$4745_Y + attribute \src "libresoc.v:125093.17-125093.112" + wire $and$libresoc.v:125093$4746_Y + attribute \src "libresoc.v:125094.17-125094.114" + wire $and$libresoc.v:125094$4747_Y + attribute \src "libresoc.v:125075.18-125075.132" + wire $eq$libresoc.v:125075$4728_Y + attribute \src "libresoc.v:125076.18-125076.132" + wire $eq$libresoc.v:125076$4729_Y + attribute \src "libresoc.v:125078.18-125078.110" + wire $eq$libresoc.v:125078$4731_Y + attribute \src "libresoc.v:125079.18-125079.110" + wire $eq$libresoc.v:125079$4732_Y + attribute \src "libresoc.v:125081.18-125081.112" + wire $eq$libresoc.v:125081$4734_Y + attribute \src "libresoc.v:125082.17-125082.136" + wire $eq$libresoc.v:125082$4735_Y + attribute \src "libresoc.v:125084.18-125084.110" + wire $eq$libresoc.v:125084$4737_Y + attribute \src "libresoc.v:125086.18-125086.137" + wire $eq$libresoc.v:125086$4739_Y + attribute \src "libresoc.v:125089.18-125089.137" + wire $eq$libresoc.v:125089$4742_Y + attribute \src "libresoc.v:125095.17-125095.136" + wire $eq$libresoc.v:125095$4748_Y + attribute \src "libresoc.v:125073.18-125073.110" + wire $not$libresoc.v:125073$4726_Y + attribute \src "libresoc.v:125091.18-125091.110" + wire $not$libresoc.v:125091$4744_Y + attribute \src "libresoc.v:125077.18-125077.110" + wire $or$libresoc.v:125077$4730_Y + attribute \src "libresoc.v:125080.18-125080.110" + wire $or$libresoc.v:125080$4733_Y + attribute \src "libresoc.v:125083.18-125083.110" + wire $or$libresoc.v:125083$4736_Y + attribute \src "libresoc.v:125085.18-125085.110" + wire $or$libresoc.v:125085$4738_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 \dec_SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_SHIFT_ROT_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 \dec_SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 \dec_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 \dec_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:124664.7-124664.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + wire \is_spr_mv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125072$4725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:125072$4725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125074$4727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:125074$4727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125087$4740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:125087$4740_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125088$4741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:125088$4741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125090$4743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:125090$4743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125092$4745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:125092$4745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125093$4746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:125093$4746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125094$4747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:125094$4747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:125075$4728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:125075$4728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:125076$4729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:125076$4729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125078$4731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:125078$4731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125079$4732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:125079$4732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125081$4734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:125081$4734_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125082$4735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:125082$4735_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:125084$4737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:125084$4737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125086$4739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:125086$4739_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125089$4742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:125089$4742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125095$4748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:125095$4748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125073$4726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:125073$4726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125091$4744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:125091$4744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:125077$4730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:125077$4730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125080$4733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:125080$4733_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125083$4736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:125083$4736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:125085$4738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:125085$4738_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125096.13-125121.4" + cell \dec$162 \dec + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_SPR \dec_SHIFT_ROT_SPR + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125122.16-125133.4" + cell \dec_bi$165 \dec_bi + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125134.16-125140.4" + cell \dec_oe$164 \dec_oe + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125141.16-125146.4" + cell \dec_rc$163 \dec_rc + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:124664.7-124664.20" + process $proc$libresoc.v:124664$4752 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125147.3-125161.6" + process $proc$libresoc.v:125147$4749 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:125148.5-125148.29" + switch \initial + attribute \src "libresoc.v:125148.9-125148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + switch \dec_SHIFT_ROT_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\SHIFT_ROT__write_cr0[0:0] \dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\SHIFT_ROT__write_cr0[0:0] 1'1 + case + assign $1\SHIFT_ROT__write_cr0[0:0] 1'0 + end + sync always + update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] + end + attribute \src "libresoc.v:125162.3-125174.6" + process $proc$libresoc.v:125162$4750 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:125163.5-125163.29" + switch \initial + attribute \src "libresoc.v:125163.9-125163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 + case + assign $1\SHIFT_ROT__insn_type[6:0] \dec_SHIFT_ROT_internal_op + end + sync always + update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] + end + attribute \src "libresoc.v:125175.3-125189.6" + process $proc$libresoc.v:125175$4751 + assign { } { } + assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:125176.5-125176.29" + switch \initial + attribute \src "libresoc.v:125176.9-125176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SHIFT_ROT__fn_unit[13:0] \dec_SHIFT_ROT_function_unit + end + sync always + update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:125072$4725_Y + connect \$12 $not$libresoc.v:125073$4726_Y + connect \$14 $and$libresoc.v:125074$4727_Y + connect \$16 $eq$libresoc.v:125075$4728_Y + connect \$18 $eq$libresoc.v:125076$4729_Y + connect \$20 $or$libresoc.v:125077$4730_Y + connect \$22 $eq$libresoc.v:125078$4731_Y + connect \$24 $eq$libresoc.v:125079$4732_Y + connect \$26 $or$libresoc.v:125080$4733_Y + connect \$28 $eq$libresoc.v:125081$4734_Y + connect \$2 $eq$libresoc.v:125082$4735_Y + connect \$30 $or$libresoc.v:125083$4736_Y + connect \$32 $eq$libresoc.v:125084$4737_Y + connect \$34 $or$libresoc.v:125085$4738_Y + connect \$36 $eq$libresoc.v:125086$4739_Y + connect \$38 $and$libresoc.v:125087$4740_Y + connect \$40 $and$libresoc.v:125088$4741_Y + connect \$42 $eq$libresoc.v:125089$4742_Y + connect \$44 $and$libresoc.v:125090$4743_Y + connect \$46 $not$libresoc.v:125091$4744_Y + connect \$48 $and$libresoc.v:125092$4745_Y + connect \$4 $and$libresoc.v:125093$4746_Y + connect \$6 $and$libresoc.v:125094$4747_Y + connect \$8 $eq$libresoc.v:125095$4748_Y + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 + connect \spr { \dec_SHIFT_ROT_SPR [4:0] \dec_SHIFT_ROT_SPR [9:5] } + connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SHIFT_ROT__insn \dec_opcode_in +end +attribute \src "libresoc.v:125213.1-125591.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" +attribute \generator "nMigen" +module \dec_SPR + attribute \src "libresoc.v:125567.3-125581.6" + wire width 14 $0\SPR__fn_unit[13:0] + attribute \src "libresoc.v:125554.3-125566.6" + wire width 7 $0\SPR__insn_type[6:0] + attribute \src "libresoc.v:125214.7-125214.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125567.3-125581.6" + wire width 14 $1\SPR__fn_unit[13:0] + attribute \src "libresoc.v:125554.3-125566.6" + wire width 7 $1\SPR__insn_type[6:0] + attribute \src "libresoc.v:125508.18-125508.113" + wire $and$libresoc.v:125508$4753_Y + attribute \src "libresoc.v:125510.18-125510.110" + wire $and$libresoc.v:125510$4755_Y + attribute \src "libresoc.v:125523.18-125523.114" + wire $and$libresoc.v:125523$4768_Y + attribute \src "libresoc.v:125524.18-125524.116" + wire $and$libresoc.v:125524$4769_Y + attribute \src "libresoc.v:125526.18-125526.114" + wire $and$libresoc.v:125526$4771_Y + attribute \src "libresoc.v:125528.18-125528.110" + wire $and$libresoc.v:125528$4773_Y + attribute \src "libresoc.v:125529.17-125529.112" + wire $and$libresoc.v:125529$4774_Y + attribute \src "libresoc.v:125530.17-125530.114" + wire $and$libresoc.v:125530$4775_Y + attribute \src "libresoc.v:125511.18-125511.126" + wire $eq$libresoc.v:125511$4756_Y + attribute \src "libresoc.v:125512.18-125512.126" + wire $eq$libresoc.v:125512$4757_Y + attribute \src "libresoc.v:125514.18-125514.110" + wire $eq$libresoc.v:125514$4759_Y + attribute \src "libresoc.v:125515.18-125515.110" + wire $eq$libresoc.v:125515$4760_Y + attribute \src "libresoc.v:125517.18-125517.112" + wire $eq$libresoc.v:125517$4762_Y + attribute \src "libresoc.v:125518.17-125518.130" + wire $eq$libresoc.v:125518$4763_Y + attribute \src "libresoc.v:125520.18-125520.110" + wire $eq$libresoc.v:125520$4765_Y + attribute \src "libresoc.v:125522.18-125522.131" + wire $eq$libresoc.v:125522$4767_Y + attribute \src "libresoc.v:125525.18-125525.131" + wire $eq$libresoc.v:125525$4770_Y + attribute \src "libresoc.v:125531.17-125531.130" + wire $eq$libresoc.v:125531$4776_Y + attribute \src "libresoc.v:125509.18-125509.110" + wire $not$libresoc.v:125509$4754_Y + attribute \src "libresoc.v:125527.18-125527.110" + wire $not$libresoc.v:125527$4772_Y + attribute \src "libresoc.v:125513.18-125513.110" + wire $or$libresoc.v:125513$4758_Y + attribute \src "libresoc.v:125516.18-125516.110" + wire $or$libresoc.v:125516$4761_Y + attribute \src "libresoc.v:125519.18-125519.110" + wire $or$libresoc.v:125519$4764_Y + attribute \src "libresoc.v:125521.18-125521.110" + wire $or$libresoc.v:125521$4766_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire \dec_SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 10 \dec_SPR_SPR + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 14 \dec_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute 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\A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:125512$4757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125514$4759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:125514$4759_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125515$4760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:125515$4760_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125517$4762 + parameter \A_SIGNED 0 + parameter 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parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:125516$4761_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125519$4764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:125519$4764_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:125521$4766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:125521$4766_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125532.13-125544.4" + cell \dec$150 \dec + connect \SPR_OE \dec_SPR_OE + connect \SPR_Rc \dec_SPR_Rc + connect \SPR_SPR \dec_SPR_SPR + connect \SPR_cr_out \dec_SPR_cr_out + connect \SPR_function_unit \dec_SPR_function_unit + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_is_32b \dec_SPR_is_32b + connect \SPR_rc_sel \dec_SPR_rc_sel + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125545.16-125549.4" + cell \dec_oe$152 \dec_oe + connect \SPR_OE \dec_SPR_OE + connect \SPR_internal_op \dec_SPR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:125550.16-125553.4" + cell \dec_rc$151 \dec_rc + connect \SPR_Rc \dec_SPR_Rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:125214.7-125214.20" + process $proc$libresoc.v:125214$4779 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125554.3-125566.6" + process $proc$libresoc.v:125554$4777 + assign { } { } + assign { } { } + assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] + attribute \src "libresoc.v:125555.5-125555.29" + switch \initial + attribute \src "libresoc.v:125555.9-125555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\SPR__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SPR__insn_type[6:0] 7'0000000 + case + assign $1\SPR__insn_type[6:0] \dec_SPR_internal_op + end + sync always + update \SPR__insn_type $0\SPR__insn_type[6:0] + end + attribute \src "libresoc.v:125567.3-125581.6" + process $proc$libresoc.v:125567$4778 + assign { } { } + assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] + attribute \src "libresoc.v:125568.5-125568.29" + switch \initial + attribute \src "libresoc.v:125568.9-125568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\SPR__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SPR__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SPR__fn_unit[13:0] \dec_SPR_function_unit + end + sync always + update \SPR__fn_unit $0\SPR__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:125508$4753_Y + connect \$12 $not$libresoc.v:125509$4754_Y + connect \$14 $and$libresoc.v:125510$4755_Y + connect \$16 $eq$libresoc.v:125511$4756_Y + connect \$18 $eq$libresoc.v:125512$4757_Y + connect \$20 $or$libresoc.v:125513$4758_Y + connect \$22 $eq$libresoc.v:125514$4759_Y + connect \$24 $eq$libresoc.v:125515$4760_Y + connect \$26 $or$libresoc.v:125516$4761_Y + connect \$28 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126605$4847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \ALU_sh + connect \Y $extend$libresoc.v:126605$4847_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126606$4849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \ALU_SH32 + connect \Y $extend$libresoc.v:126606$4849_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126609$4853 + parameter \A_SIGNED 0 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126609$4854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126609$4853_Y + connect \Y $pos$libresoc.v:126609$4854_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:126613$4859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126613$4858_Y + connect \Y $pos$libresoc.v:126613$4859_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:126607$4851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126607$4851_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126608$4852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:126608$4852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126610$4855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:126610$4855_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:126611$4856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:126611$4856_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:126612$4857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126612$4857_Y + end + attribute \src "libresoc.v:126527.7-126527.20" + process $proc$libresoc.v:126527$4868 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:126615.3-126661.6" + process $proc$libresoc.v:126615$4860 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:126616.5-126616.29" + switch \initial + attribute \src "libresoc.v:126616.9-126616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:126662.3-126708.6" + process $proc$libresoc.v:126662$4861 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:126663.5-126663.29" + switch \initial + attribute \src "libresoc.v:126663.9-126663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:126709.3-126719.6" + process $proc$libresoc.v:126709$4862 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:126710.5-126710.29" + switch \initial + attribute \src "libresoc.v:126710.9-126710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \ALU_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:126720.3-126730.6" + process $proc$libresoc.v:126720$4863 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:126721.5-126721.29" + switch \initial + attribute \src "libresoc.v:126721.9-126721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:126731.3-126741.6" + process $proc$libresoc.v:126731$4864 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:126732.5-126732.29" + switch \initial + attribute \src "libresoc.v:126732.9-126732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \ALU_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:126742.3-126752.6" + process $proc$libresoc.v:126742$4865 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:126743.5-126743.29" + switch \initial + attribute \src "libresoc.v:126743.9-126743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:126753.3-126763.6" + process $proc$libresoc.v:126753$4866 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:126754.5-126754.29" + switch \initial + attribute \src "libresoc.v:126754.9-126754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:126764.3-126774.6" + process $proc$libresoc.v:126764$4867 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:126765.5-126765.29" + switch \initial + attribute \src "libresoc.v:126765.9-126765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:126605$4848_Y + connect \$11 $pos$libresoc.v:126606$4850_Y + connect \$14 $sshl$libresoc.v:126607$4851_Y + connect \$17 $sshl$libresoc.v:126608$4852_Y + connect \$1 $pos$libresoc.v:126609$4854_Y + connect \$20 $sshl$libresoc.v:126610$4855_Y + connect \$23 $sshl$libresoc.v:126611$4856_Y + connect \$4 $sshl$libresoc.v:126612$4857_Y + connect \$3 $pos$libresoc.v:126613$4859_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:126783.1-127036.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" +attribute \generator "nMigen" +module \dec_bi$144 + attribute \src "libresoc.v:127010.3-127020.6" + wire width 16 $0\bd[15:0] + attribute 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$pos$libresoc.v:126870$4881_Y + attribute \src "libresoc.v:126864.18-126864.117" + wire width 47 $sshl$libresoc.v:126864$4873_Y + attribute \src "libresoc.v:126865.18-126865.116" + wire width 27 $sshl$libresoc.v:126865$4874_Y + attribute \src "libresoc.v:126867.18-126867.116" + wire width 17 $sshl$libresoc.v:126867$4877_Y + attribute \src "libresoc.v:126868.18-126868.116" + wire width 17 $sshl$libresoc.v:126868$4878_Y + attribute \src "libresoc.v:126869.17-126869.109" + wire width 47 $sshl$libresoc.v:126869$4879_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 8 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 9 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 input 7 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 5 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 3 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 4 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 input 6 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:126784.7-126784.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126862$4869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \BRANCH_sh + connect \Y $extend$libresoc.v:126862$4869_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126863$4871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $extend$libresoc.v:126863$4871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126866$4875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $extend$libresoc.v:126866$4875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:126870$4880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:126870$4880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126862$4870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126862$4869_Y + connect \Y $pos$libresoc.v:126862$4870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126863$4872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126863$4871_Y + connect \Y $pos$libresoc.v:126863$4872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126866$4876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126866$4875_Y + connect \Y $pos$libresoc.v:126866$4876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:126870$4881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:126870$4880_Y + connect \Y $pos$libresoc.v:126870$4881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:126864$4873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126864$4873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126865$4874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:126865$4874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126867$4877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:126867$4877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:126868$4878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:126868$4878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:126869$4879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:126869$4879_Y + end + attribute \src "libresoc.v:126784.7-126784.20" + process $proc$libresoc.v:126784$4890 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:126872.3-126918.6" + process $proc$libresoc.v:126872$4882 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:126873.5-126873.29" + switch \initial + attribute \src "libresoc.v:126873.9-126873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:126919.3-126965.6" + process $proc$libresoc.v:126919$4883 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:126920.5-126920.29" + switch \initial + attribute \src "libresoc.v:126920.9-126920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:126966.3-126976.6" + process $proc$libresoc.v:126966$4884 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:126967.5-126967.29" + switch \initial + attribute \src "libresoc.v:126967.9-126967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \BRANCH_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:126977.3-126987.6" + process $proc$libresoc.v:126977$4885 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:126978.5-126978.29" + switch \initial + attribute \src "libresoc.v:126978.9-126978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:126988.3-126998.6" + process $proc$libresoc.v:126988$4886 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:126989.5-126989.29" + switch \initial + attribute \src "libresoc.v:126989.9-126989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \BRANCH_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:126999.3-127009.6" + process $proc$libresoc.v:126999$4887 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:127000.5-127000.29" + switch \initial + attribute \src "libresoc.v:127000.9-127000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:127010.3-127020.6" + process $proc$libresoc.v:127010$4888 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:127011.5-127011.29" + switch \initial + attribute \src "libresoc.v:127011.9-127011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:127021.3-127031.6" + process $proc$libresoc.v:127021$4889 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:127022.5-127022.29" + switch \initial + attribute \src "libresoc.v:127022.9-127022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:126862$4870_Y + connect \$11 $pos$libresoc.v:126863$4872_Y + connect \$14 $sshl$libresoc.v:126864$4873_Y + connect \$17 $sshl$libresoc.v:126865$4874_Y + connect \$1 $pos$libresoc.v:126866$4876_Y + connect \$20 $sshl$libresoc.v:126867$4877_Y + connect \$23 $sshl$libresoc.v:126868$4878_Y + connect \$4 $sshl$libresoc.v:126869$4879_Y + connect \$3 $pos$libresoc.v:126870$4881_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:127040.1-127293.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$149 + attribute \src "libresoc.v:127267.3-127277.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:127278.3-127288.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:127129.3-127175.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:127176.3-127222.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:127041.7-127041.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:127256.3-127266.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:127223.3-127233.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:127234.3-127244.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:127245.3-127255.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:127267.3-127277.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:127278.3-127288.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:127129.3-127175.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:127176.3-127222.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:127256.3-127266.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:127223.3-127233.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:127234.3-127244.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:127245.3-127255.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:127119.17-127119.108" + wire width 64 $extend$libresoc.v:127119$4891_Y + attribute \src "libresoc.v:127120.18-127120.111" + wire width 64 $extend$libresoc.v:127120$4893_Y + attribute \src "libresoc.v:127123.17-127123.108" + wire width 64 $extend$libresoc.v:127123$4897_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 8 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 9 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 input 7 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 5 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 3 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 4 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 input 6 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:127041.7-127041.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127119$4891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_sh + connect \Y $extend$libresoc.v:127119$4891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127120$4893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_SH32 + connect \Y $extend$libresoc.v:127120$4893_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127123$4897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_UI + connect \Y $extend$libresoc.v:127123$4897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127127$4902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:127127$4902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127119$4892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127119$4891_Y + connect \Y $pos$libresoc.v:127119$4892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127120$4894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127120$4893_Y + connect \Y $pos$libresoc.v:127120$4894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127123$4898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127123$4897_Y + connect \Y $pos$libresoc.v:127123$4898_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127127$4903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127127$4902_Y + connect \Y $pos$libresoc.v:127127$4903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127121$4895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127121$4895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127122$4896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:127122$4896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127124$4899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:127124$4899_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127125$4900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:127125$4900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127126$4901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127126$4901_Y + end + attribute \src "libresoc.v:127041.7-127041.20" + process $proc$libresoc.v:127041$4912 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127129.3-127175.6" + process $proc$libresoc.v:127129$4904 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:127130.5-127130.29" + switch \initial + attribute \src "libresoc.v:127130.9-127130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:127176.3-127222.6" + process $proc$libresoc.v:127176$4905 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:127177.5-127177.29" + switch \initial + attribute \src "libresoc.v:127177.9-127177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:127223.3-127233.6" + process $proc$libresoc.v:127223$4906 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:127224.5-127224.29" + switch \initial + attribute \src "libresoc.v:127224.9-127224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LOGICAL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:127234.3-127244.6" + process $proc$libresoc.v:127234$4907 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:127235.5-127235.29" + switch \initial + attribute \src "libresoc.v:127235.9-127235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:127245.3-127255.6" + process $proc$libresoc.v:127245$4908 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:127246.5-127246.29" + switch \initial + attribute \src "libresoc.v:127246.9-127246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LOGICAL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:127256.3-127266.6" + process $proc$libresoc.v:127256$4909 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:127257.5-127257.29" + switch \initial + attribute \src "libresoc.v:127257.9-127257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:127267.3-127277.6" + process $proc$libresoc.v:127267$4910 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:127268.5-127268.29" + switch \initial + attribute \src "libresoc.v:127268.9-127268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:127278.3-127288.6" + process $proc$libresoc.v:127278$4911 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:127279.5-127279.29" + switch \initial + attribute \src "libresoc.v:127279.9-127279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:127119$4892_Y + connect \$11 $pos$libresoc.v:127120$4894_Y + connect \$14 $sshl$libresoc.v:127121$4895_Y + connect \$17 $sshl$libresoc.v:127122$4896_Y + connect \$1 $pos$libresoc.v:127123$4898_Y + connect \$20 $sshl$libresoc.v:127124$4899_Y + connect \$23 $sshl$libresoc.v:127125$4900_Y + connect \$4 $sshl$libresoc.v:127126$4901_Y + connect \$3 $pos$libresoc.v:127127$4903_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:127297.1-127550.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" +attribute \generator "nMigen" +module \dec_bi$157 + attribute \src "libresoc.v:127524.3-127534.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:127535.3-127545.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:127386.3-127432.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:127433.3-127479.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:127298.7-127298.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:127513.3-127523.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:127480.3-127490.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:127491.3-127501.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:127502.3-127512.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:127524.3-127534.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:127535.3-127545.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:127386.3-127432.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:127433.3-127479.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:127513.3-127523.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:127480.3-127490.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:127491.3-127501.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:127502.3-127512.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:127376.17-127376.104" + wire width 64 $extend$libresoc.v:127376$4913_Y + attribute \src "libresoc.v:127377.18-127377.107" + wire width 64 $extend$libresoc.v:127377$4915_Y + attribute \src "libresoc.v:127380.17-127380.104" + wire width 64 $extend$libresoc.v:127380$4919_Y + attribute \src "libresoc.v:127384.17-127384.102" + wire width 64 $extend$libresoc.v:127384$4924_Y + attribute \src "libresoc.v:127376.17-127376.104" + wire width 64 $pos$libresoc.v:127376$4914_Y + attribute \src "libresoc.v:127377.18-127377.107" + wire width 64 $pos$libresoc.v:127377$4916_Y + attribute \src "libresoc.v:127380.17-127380.104" + wire width 64 $pos$libresoc.v:127380$4920_Y + attribute \src "libresoc.v:127384.17-127384.102" + wire width 64 $pos$libresoc.v:127384$4925_Y + attribute \src "libresoc.v:127378.18-127378.114" + wire width 47 $sshl$libresoc.v:127378$4917_Y + attribute \src "libresoc.v:127379.18-127379.113" + wire width 27 $sshl$libresoc.v:127379$4918_Y + attribute \src "libresoc.v:127381.18-127381.113" + wire width 17 $sshl$libresoc.v:127381$4921_Y + attribute \src "libresoc.v:127382.18-127382.113" + wire width 17 $sshl$libresoc.v:127382$4922_Y + attribute \src "libresoc.v:127383.17-127383.109" + wire width 47 $sshl$libresoc.v:127383$4923_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:127298.7-127298.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127376$4913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $extend$libresoc.v:127376$4913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127377$4915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $extend$libresoc.v:127377$4915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127380$4919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $extend$libresoc.v:127380$4919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127384$4924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:127384$4924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127376$4914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127376$4913_Y + connect \Y $pos$libresoc.v:127376$4914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127377$4916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127377$4915_Y + connect \Y $pos$libresoc.v:127377$4916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127380$4920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127380$4919_Y + connect \Y $pos$libresoc.v:127380$4920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127384$4925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127384$4924_Y + connect \Y $pos$libresoc.v:127384$4925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127378$4917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127378$4917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127379$4918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:127379$4918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127381$4921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:127381$4921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127382$4922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:127382$4922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127383$4923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127383$4923_Y + end + attribute \src "libresoc.v:127298.7-127298.20" + process $proc$libresoc.v:127298$4934 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127386.3-127432.6" + process $proc$libresoc.v:127386$4926 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:127387.5-127387.29" + switch \initial + attribute \src "libresoc.v:127387.9-127387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:127433.3-127479.6" + process $proc$libresoc.v:127433$4927 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:127434.5-127434.29" + switch \initial + attribute \src "libresoc.v:127434.9-127434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:127480.3-127490.6" + process $proc$libresoc.v:127480$4928 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:127481.5-127481.29" + switch \initial + attribute \src "libresoc.v:127481.9-127481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \DIV_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:127491.3-127501.6" + process $proc$libresoc.v:127491$4929 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:127492.5-127492.29" + switch \initial + attribute \src "libresoc.v:127492.9-127492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:127502.3-127512.6" + process $proc$libresoc.v:127502$4930 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:127503.5-127503.29" + switch \initial + attribute \src "libresoc.v:127503.9-127503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \DIV_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:127513.3-127523.6" + process $proc$libresoc.v:127513$4931 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:127514.5-127514.29" + switch \initial + attribute \src "libresoc.v:127514.9-127514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:127524.3-127534.6" + process $proc$libresoc.v:127524$4932 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:127525.5-127525.29" + switch \initial + attribute \src "libresoc.v:127525.9-127525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:127535.3-127545.6" + process $proc$libresoc.v:127535$4933 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:127536.5-127536.29" + switch \initial + attribute \src "libresoc.v:127536.9-127536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:127376$4914_Y + connect \$11 $pos$libresoc.v:127377$4916_Y + connect \$14 $sshl$libresoc.v:127378$4917_Y + connect \$17 $sshl$libresoc.v:127379$4918_Y + connect \$1 $pos$libresoc.v:127380$4920_Y + connect \$20 $sshl$libresoc.v:127381$4921_Y + connect \$23 $sshl$libresoc.v:127382$4922_Y + connect \$4 $sshl$libresoc.v:127383$4923_Y + connect \$3 $pos$libresoc.v:127384$4925_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:127554.1-127807.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$161 + attribute \src "libresoc.v:127781.3-127791.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:127792.3-127802.6" + wire width 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+ attribute \src "libresoc.v:127748.3-127758.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:127759.3-127769.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:127633.17-127633.104" + wire width 64 $extend$libresoc.v:127633$4935_Y + attribute \src "libresoc.v:127634.18-127634.107" + wire width 64 $extend$libresoc.v:127634$4937_Y + attribute \src "libresoc.v:127637.17-127637.104" + wire width 64 $extend$libresoc.v:127637$4941_Y + attribute \src "libresoc.v:127641.17-127641.102" + wire width 64 $extend$libresoc.v:127641$4946_Y + attribute \src "libresoc.v:127633.17-127633.104" + wire width 64 $pos$libresoc.v:127633$4936_Y + attribute \src "libresoc.v:127634.18-127634.107" + wire width 64 $pos$libresoc.v:127634$4938_Y + attribute \src "libresoc.v:127637.17-127637.104" + wire width 64 $pos$libresoc.v:127637$4942_Y + attribute \src "libresoc.v:127641.17-127641.102" + wire width 64 $pos$libresoc.v:127641$4947_Y + attribute \src "libresoc.v:127635.18-127635.114" + wire width 47 $sshl$libresoc.v:127635$4939_Y + attribute \src "libresoc.v:127636.18-127636.113" + wire width 27 $sshl$libresoc.v:127636$4940_Y + attribute \src "libresoc.v:127638.18-127638.113" + wire width 17 $sshl$libresoc.v:127638$4943_Y + attribute \src "libresoc.v:127639.18-127639.113" + wire width 17 $sshl$libresoc.v:127639$4944_Y + attribute \src "libresoc.v:127640.17-127640.109" + wire width 47 $sshl$libresoc.v:127640$4945_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:127555.7-127555.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127633$4935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $extend$libresoc.v:127633$4935_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127634$4937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $extend$libresoc.v:127634$4937_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127637$4941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $extend$libresoc.v:127637$4941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127641$4946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:127641$4946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127633$4936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127633$4935_Y + connect \Y $pos$libresoc.v:127633$4936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127634$4938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127634$4937_Y + connect \Y $pos$libresoc.v:127634$4938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127637$4942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127637$4941_Y + connect \Y $pos$libresoc.v:127637$4942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127641$4947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127641$4946_Y + connect \Y $pos$libresoc.v:127641$4947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127635$4939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127635$4939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127636$4940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:127636$4940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127638$4943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:127638$4943_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127639$4944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:127639$4944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127640$4945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127640$4945_Y + end + attribute \src "libresoc.v:127555.7-127555.20" + process $proc$libresoc.v:127555$4956 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127643.3-127689.6" + process $proc$libresoc.v:127643$4948 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:127644.5-127644.29" + switch \initial + attribute \src "libresoc.v:127644.9-127644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:127690.3-127736.6" + process $proc$libresoc.v:127690$4949 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:127691.5-127691.29" + switch \initial + attribute \src "libresoc.v:127691.9-127691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:127737.3-127747.6" + process $proc$libresoc.v:127737$4950 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:127738.5-127738.29" + switch \initial + attribute \src "libresoc.v:127738.9-127738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \MUL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:127748.3-127758.6" + process $proc$libresoc.v:127748$4951 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:127749.5-127749.29" + switch \initial + attribute \src "libresoc.v:127749.9-127749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:127759.3-127769.6" + process $proc$libresoc.v:127759$4952 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:127760.5-127760.29" + switch \initial + attribute \src "libresoc.v:127760.9-127760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \MUL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:127770.3-127780.6" + process $proc$libresoc.v:127770$4953 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:127771.5-127771.29" + switch \initial + attribute \src "libresoc.v:127771.9-127771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:127781.3-127791.6" + process $proc$libresoc.v:127781$4954 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:127782.5-127782.29" + switch \initial + attribute \src "libresoc.v:127782.9-127782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:127792.3-127802.6" + process $proc$libresoc.v:127792$4955 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:127793.5-127793.29" + switch \initial + attribute \src "libresoc.v:127793.9-127793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:127633$4936_Y + connect \$11 $pos$libresoc.v:127634$4938_Y + connect \$14 $sshl$libresoc.v:127635$4939_Y + connect \$17 $sshl$libresoc.v:127636$4940_Y + connect \$1 $pos$libresoc.v:127637$4942_Y + connect \$20 $sshl$libresoc.v:127638$4943_Y + connect \$23 $sshl$libresoc.v:127639$4944_Y + connect \$4 $sshl$libresoc.v:127640$4945_Y + connect \$3 $pos$libresoc.v:127641$4947_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:127811.1-128064.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" +attribute \generator "nMigen" +module \dec_bi$165 + attribute \src "libresoc.v:128038.3-128048.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:128049.3-128059.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:127900.3-127946.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:127947.3-127993.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:127812.7-127812.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128027.3-128037.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:127994.3-128004.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:128005.3-128015.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:128016.3-128026.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:128038.3-128048.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:128049.3-128059.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:127900.3-127946.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:127947.3-127993.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:128027.3-128037.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:127994.3-128004.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:128005.3-128015.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:128016.3-128026.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:127890.17-127890.110" + wire width 64 $extend$libresoc.v:127890$4957_Y + attribute \src "libresoc.v:127891.18-127891.113" + wire width 64 $extend$libresoc.v:127891$4959_Y + attribute \src "libresoc.v:127894.17-127894.110" + wire width 64 $extend$libresoc.v:127894$4963_Y + attribute \src "libresoc.v:127898.17-127898.102" + wire width 64 $extend$libresoc.v:127898$4968_Y + attribute \src "libresoc.v:127890.17-127890.110" + wire width 64 $pos$libresoc.v:127890$4958_Y + attribute \src "libresoc.v:127891.18-127891.113" + wire width 64 $pos$libresoc.v:127891$4960_Y + attribute \src "libresoc.v:127894.17-127894.110" + wire width 64 $pos$libresoc.v:127894$4964_Y + attribute \src "libresoc.v:127898.17-127898.102" + wire width 64 $pos$libresoc.v:127898$4969_Y + attribute \src "libresoc.v:127892.18-127892.120" + wire width 47 $sshl$libresoc.v:127892$4961_Y + attribute \src "libresoc.v:127893.18-127893.119" + wire width 27 $sshl$libresoc.v:127893$4962_Y + attribute \src "libresoc.v:127895.18-127895.119" + wire width 17 $sshl$libresoc.v:127895$4965_Y + attribute \src "libresoc.v:127896.18-127896.119" + wire width 17 $sshl$libresoc.v:127896$4966_Y + attribute \src "libresoc.v:127897.17-127897.109" + wire width 47 $sshl$libresoc.v:127897$4967_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:127812.7-127812.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127890$4957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $extend$libresoc.v:127890$4957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127891$4959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $extend$libresoc.v:127891$4959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127894$4963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $extend$libresoc.v:127894$4963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127898$4968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:127898$4968_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127890$4958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127890$4957_Y + connect \Y $pos$libresoc.v:127890$4958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127891$4960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127891$4959_Y + connect \Y $pos$libresoc.v:127891$4960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127894$4964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127894$4963_Y + connect \Y $pos$libresoc.v:127894$4964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127898$4969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:127898$4968_Y + connect \Y $pos$libresoc.v:127898$4969_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127892$4961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127892$4961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127893$4962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:127893$4962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127895$4965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:127895$4965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127896$4966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:127896$4966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127897$4967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:127897$4967_Y + end + attribute \src "libresoc.v:127812.7-127812.20" + process $proc$libresoc.v:127812$4978 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127900.3-127946.6" + process $proc$libresoc.v:127900$4970 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:127901.5-127901.29" + switch \initial + attribute \src "libresoc.v:127901.9-127901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:127947.3-127993.6" + process $proc$libresoc.v:127947$4971 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:127948.5-127948.29" + switch \initial + attribute \src "libresoc.v:127948.9-127948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:127994.3-128004.6" + process $proc$libresoc.v:127994$4972 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:127995.5-127995.29" + switch \initial + attribute \src "libresoc.v:127995.9-127995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \SHIFT_ROT_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:128005.3-128015.6" + process $proc$libresoc.v:128005$4973 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:128006.5-128006.29" + switch \initial + attribute \src "libresoc.v:128006.9-128006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:128016.3-128026.6" + process $proc$libresoc.v:128016$4974 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:128017.5-128017.29" + switch \initial + attribute \src "libresoc.v:128017.9-128017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \SHIFT_ROT_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:128027.3-128037.6" + process $proc$libresoc.v:128027$4975 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:128028.5-128028.29" + switch \initial + attribute \src "libresoc.v:128028.9-128028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:128038.3-128048.6" + process $proc$libresoc.v:128038$4976 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:128039.5-128039.29" + switch \initial + attribute \src "libresoc.v:128039.9-128039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:128049.3-128059.6" + process $proc$libresoc.v:128049$4977 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:128050.5-128050.29" + switch \initial + attribute \src "libresoc.v:128050.9-128050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:127890$4958_Y + connect \$11 $pos$libresoc.v:127891$4960_Y + connect \$14 $sshl$libresoc.v:127892$4961_Y + connect \$17 $sshl$libresoc.v:127893$4962_Y + connect \$1 $pos$libresoc.v:127894$4964_Y + connect \$20 $sshl$libresoc.v:127895$4965_Y + connect \$23 $sshl$libresoc.v:127896$4966_Y + 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"libresoc.v:128262.3-128272.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:128273.3-128283.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:128295.3-128305.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:128306.3-128316.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:128157.3-128203.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:128204.3-128250.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:128284.3-128294.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:128251.3-128261.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:128262.3-128272.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:128273.3-128283.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:128147.17-128147.105" + wire width 64 $extend$libresoc.v:128147$4979_Y + attribute \src "libresoc.v:128148.18-128148.108" + wire width 64 $extend$libresoc.v:128148$4981_Y + attribute \src "libresoc.v:128151.17-128151.105" + wire width 64 $extend$libresoc.v:128151$4985_Y + attribute \src "libresoc.v:128155.17-128155.102" + wire width 64 $extend$libresoc.v:128155$4990_Y + attribute \src "libresoc.v:128147.17-128147.105" + wire width 64 $pos$libresoc.v:128147$4980_Y + attribute \src "libresoc.v:128148.18-128148.108" + wire width 64 $pos$libresoc.v:128148$4982_Y + attribute \src "libresoc.v:128151.17-128151.105" + wire width 64 $pos$libresoc.v:128151$4986_Y + attribute \src "libresoc.v:128155.17-128155.102" + wire width 64 $pos$libresoc.v:128155$4991_Y + attribute \src "libresoc.v:128149.18-128149.115" + wire width 47 $sshl$libresoc.v:128149$4983_Y + attribute \src "libresoc.v:128150.18-128150.114" + wire width 27 $sshl$libresoc.v:128150$4984_Y + attribute \src "libresoc.v:128152.18-128152.114" + wire width 17 $sshl$libresoc.v:128152$4987_Y + attribute \src "libresoc.v:128153.18-128153.114" + wire width 17 $sshl$libresoc.v:128153$4988_Y + attribute \src "libresoc.v:128154.17-128154.109" + wire width 47 $sshl$libresoc.v:128154$4989_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 8 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 14 input 9 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 24 input 7 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 5 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 3 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:128069.7-128069.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128147$4979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $extend$libresoc.v:128147$4979_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128148$4981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $extend$libresoc.v:128148$4981_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128151$4985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $extend$libresoc.v:128151$4985_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:128155$4990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:128155$4990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128147$4980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:128147$4979_Y + connect \Y $pos$libresoc.v:128147$4980_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128148$4982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:128148$4981_Y + connect \Y $pos$libresoc.v:128148$4982_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128151$4986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:128151$4985_Y + connect \Y $pos$libresoc.v:128151$4986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:128155$4991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:128155$4990_Y + connect \Y $pos$libresoc.v:128155$4991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:128149$4983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:128149$4983_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:128150$4984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:128150$4984_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:128152$4987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:128152$4987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:128153$4988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:128153$4988_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:128154$4989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:128154$4989_Y + end + attribute \src "libresoc.v:128069.7-128069.20" + process $proc$libresoc.v:128069$5000 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128157.3-128203.6" + process $proc$libresoc.v:128157$4992 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:128158.5-128158.29" + switch \initial + attribute \src "libresoc.v:128158.9-128158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:128204.3-128250.6" + process $proc$libresoc.v:128204$4993 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:128205.5-128205.29" + switch \initial + attribute \src "libresoc.v:128205.9-128205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:128251.3-128261.6" + process $proc$libresoc.v:128251$4994 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:128252.5-128252.29" + switch \initial + attribute \src "libresoc.v:128252.9-128252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LDST_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:128262.3-128272.6" + process $proc$libresoc.v:128262$4995 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:128263.5-128263.29" + switch \initial + attribute \src "libresoc.v:128263.9-128263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:128273.3-128283.6" + process $proc$libresoc.v:128273$4996 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:128274.5-128274.29" + switch \initial + attribute \src "libresoc.v:128274.9-128274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LDST_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:128284.3-128294.6" + process $proc$libresoc.v:128284$4997 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:128285.5-128285.29" + switch \initial + attribute \src "libresoc.v:128285.9-128285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:128295.3-128305.6" + process $proc$libresoc.v:128295$4998 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:128296.5-128296.29" + switch \initial + attribute \src "libresoc.v:128296.9-128296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:128306.3-128316.6" + process $proc$libresoc.v:128306$4999 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:128307.5-128307.29" + switch \initial + attribute \src "libresoc.v:128307.9-128307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:128147$4980_Y + connect \$11 $pos$libresoc.v:128148$4982_Y + connect \$14 $sshl$libresoc.v:128149$4983_Y + connect \$17 $sshl$libresoc.v:128150$4984_Y + connect \$1 $pos$libresoc.v:128151$4986_Y + connect \$20 $sshl$libresoc.v:128152$4987_Y + connect \$23 $sshl$libresoc.v:128153$4988_Y + connect \$4 $sshl$libresoc.v:128154$4989_Y + connect \$3 $pos$libresoc.v:128155$4991_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:128325.1-128373.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "libresoc.v:128326.7-128326.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128343.3-128357.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:128358.3-128372.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:128343.3-128357.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:128358.3-128372.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 3 \RS + attribute \src "libresoc.v:128326.7-128326.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128326.7-128326.20" + process $proc$libresoc.v:128326$5003 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128343.3-128357.6" + process $proc$libresoc.v:128343$5001 + assign { } { } + assign { } { } + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:128344.5-128344.29" + switch \initial + attribute \src "libresoc.v:128344.9-128344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "libresoc.v:128358.3-128372.6" + process $proc$libresoc.v:128358$5002 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:128359.5-128359.29" + switch \initial + attribute \src "libresoc.v:128359.9-128359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + case + assign $1\reg_c_ok[0:0] 1'0 + end + sync always + update \reg_c_ok $0\reg_c_ok[0:0] + end +end +attribute \src "libresoc.v:128377.1-128709.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in + attribute \src "libresoc.v:128629.3-128659.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:128660.3-128670.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:128562.3-128572.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128671.3-128681.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128592.3-128602.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128531.3-128561.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128573.3-128591.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:128603.3-128613.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128378.7-128378.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128682.3-128692.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:128693.3-128708.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:128614.3-128628.6" + wire width 2 $0\sv_override[1:0] + attribute \src "libresoc.v:128629.3-128659.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128660.3-128670.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:128562.3-128572.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128671.3-128681.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128592.3-128602.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128531.3-128561.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128573.3-128591.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:128603.3-128613.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128682.3-128692.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:128693.3-128708.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:128614.3-128628.6" + wire width 2 $1\sv_override[1:0] + attribute \src "libresoc.v:128573.3-128591.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:128693.3-128708.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:128524.17-128524.112" + wire $and$libresoc.v:128524$5005_Y + attribute \src "libresoc.v:128526.17-128526.112" + wire $and$libresoc.v:128526$5007_Y + attribute \src "libresoc.v:128523.17-128523.117" + wire $eq$libresoc.v:128523$5004_Y + attribute \src "libresoc.v:128525.17-128525.117" + wire $eq$libresoc.v:128525$5006_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_fxm_ok + attribute \src "libresoc.v:128378.7-128378.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" + wire width 32 input 1 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 18 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire width 2 \sv_override + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $and $and$libresoc.v:128524$5005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:128524$5005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $and $and$libresoc.v:128526$5007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:128526$5007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $eq $eq$libresoc.v:128523$5004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128523$5004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $eq $eq$libresoc.v:128525$5006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128525$5006_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128527.9-128530.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:128378.7-128378.20" + process $proc$libresoc.v:128378$5019 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128531.3-128561.6" + process $proc$libresoc.v:128531$5008 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128532.5-128532.29" + switch \initial + attribute \src "libresoc.v:128532.9-128532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:128562.3-128572.6" + process $proc$libresoc.v:128562$5009 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128563.5-128563.29" + switch \initial + attribute \src "libresoc.v:128563.9-128563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:128573.3-128591.6" + process $proc$libresoc.v:128573$5010 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:128574.5-128574.29" + switch \initial + attribute \src "libresoc.v:128574.9-128574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + attribute \src "libresoc.v:128592.3-128602.6" + process $proc$libresoc.v:128592$5011 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128593.5-128593.29" + switch \initial + attribute \src "libresoc.v:128593.9-128593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:128603.3-128613.6" + process $proc$libresoc.v:128603$5012 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128604.5-128604.29" + switch \initial + attribute \src "libresoc.v:128604.9-128604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:128614.3-128628.6" + process $proc$libresoc.v:128614$5013 + assign { } { } + assign { } { } + assign $0\sv_override[1:0] $1\sv_override[1:0] + attribute \src "libresoc.v:128615.5-128615.29" + switch \initial + attribute \src "libresoc.v:128615.9-128615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\sv_override[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\sv_override[1:0] 2'10 + case + assign $1\sv_override[1:0] 2'00 + end + sync always + update \sv_override $0\sv_override[1:0] + end + attribute \src "libresoc.v:128629.3-128659.6" + process $proc$libresoc.v:128629$5014 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128630.5-128630.29" + switch \initial + attribute \src "libresoc.v:128630.9-128630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\cr_bitfield[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:128660.3-128670.6" + process $proc$libresoc.v:128660$5015 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:128661.5-128661.29" + switch \initial + attribute \src "libresoc.v:128661.9-128661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:128671.3-128681.6" + process $proc$libresoc.v:128671$5016 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128672.5-128672.29" + switch \initial + attribute \src "libresoc.v:128672.9-128672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:128682.3-128692.6" + process $proc$libresoc.v:128682$5017 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:128683.5-128683.29" + switch \initial + attribute \src "libresoc.v:128683.9-128683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:128693.3-128708.6" + process $proc$libresoc.v:128693$5018 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:128694.5-128694.29" + switch \initial + attribute \src "libresoc.v:128694.9-128694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + connect \$1 $eq$libresoc.v:128523$5004_Y + connect \$3 $and$libresoc.v:128524$5005_Y + connect \$5 $eq$libresoc.v:128525$5006_Y + connect \$7 $and$libresoc.v:128526$5007_Y +end +attribute \src "libresoc.v:128713.1-128983.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:128893.3-128915.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:128844.3-128866.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128948.3-128982.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:128867.3-128877.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128714.7-128714.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128916.3-128926.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:128927.3-128947.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:128878.3-128892.6" + wire width 2 $0\sv_override[1:0] + attribute \src "libresoc.v:128893.3-128915.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128844.3-128866.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128948.3-128982.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:128867.3-128877.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128916.3-128926.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:128927.3-128947.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:128878.3-128892.6" + wire width 2 $1\sv_override[1:0] + attribute \src "libresoc.v:128948.3-128982.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:128927.3-128947.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:128948.3-128982.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:128927.3-128947.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:128948.3-128982.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:128837.17-128837.117" + wire $eq$libresoc.v:128837$5020_Y + attribute \src "libresoc.v:128838.17-128838.117" + wire $eq$libresoc.v:128838$5021_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:128714.7-128714.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" + wire width 32 input 1 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 11 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:638" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + wire input 3 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" + wire width 2 \sv_override + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + cell $eq $eq$libresoc.v:128837$5020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:128837$5020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + cell $eq $eq$libresoc.v:128838$5021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:128838$5021_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128839.15-128843.4" + cell \ppick$175 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:128714.7-128714.20" + process $proc$libresoc.v:128714$5029 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128844.3-128866.6" + process $proc$libresoc.v:128844$5022 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128845.5-128845.29" + switch \initial + attribute \src "libresoc.v:128845.9-128845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:128867.3-128877.6" + process $proc$libresoc.v:128867$5023 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128868.5-128868.29" + switch \initial + attribute \src "libresoc.v:128868.9-128868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:128878.3-128892.6" + process $proc$libresoc.v:128878$5024 + assign { } { } + assign { } { } + assign $0\sv_override[1:0] $1\sv_override[1:0] + attribute \src "libresoc.v:128879.5-128879.29" + switch \initial + attribute \src "libresoc.v:128879.9-128879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\sv_override[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\sv_override[1:0] 2'10 + case + assign $1\sv_override[1:0] 2'00 + end + sync always + update \sv_override $0\sv_override[1:0] + end + attribute \src "libresoc.v:128893.3-128915.6" + process $proc$libresoc.v:128893$5025 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128894.5-128894.29" + switch \initial + attribute \src "libresoc.v:128894.9-128894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:128916.3-128926.6" + process $proc$libresoc.v:128916$5026 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:128917.5-128917.29" + switch \initial + attribute \src "libresoc.v:128917.9-128917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:128927.3-128947.6" + process $proc$libresoc.v:128927$5027 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:128928.5-128928.29" + switch \initial + attribute \src "libresoc.v:128928.9-128928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:128948.3-128982.6" + process $proc$libresoc.v:128948$5028 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:128949.5-128949.29" + switch \initial + attribute \src "libresoc.v:128949.9-128949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + switch \sel_in + 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"reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129348$5030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:129348$5030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129349$5031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:129349$5031_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129350$5032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:129350$5032_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + cell $not $not$libresoc.v:129351$5033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:129351$5033_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129352.16-129358.4" + cell \sprmap$174 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:128988.7-128988.20" + process $proc$libresoc.v:128988$5040 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129359.3-129373.6" + process $proc$libresoc.v:129359$5034 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:129360.5-129360.29" + switch \initial + attribute \src "libresoc.v:129360.9-129360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] + end + attribute \src "libresoc.v:129374.3-129388.6" + process $proc$libresoc.v:129374$5035 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:129375.5-129375.29" + switch \initial + attribute \src "libresoc.v:129375.9-129375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:129389.3-129399.6" + process $proc$libresoc.v:129389$5036 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:129390.5-129390.29" + switch \initial + attribute \src "libresoc.v:129390.9-129390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:129400.3-129415.6" + process $proc$libresoc.v:129400$5037 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:129401.5-129401.29" + switch \initial + attribute \src "libresoc.v:129401.9-129401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:129416.3-129432.6" + process $proc$libresoc.v:129416$5038 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:129417.5-129417.29" + switch \initial + attribute \src "libresoc.v:129417.9-129417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end + attribute \src "libresoc.v:129433.3-129471.6" + process $proc$libresoc.v:129433$5039 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:129434.5-129434.29" + switch \initial + attribute \src "libresoc.v:129434.9-129434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:129348$5030_Y + connect \$3 $eq$libresoc.v:129349$5031_Y + connect \$5 $eq$libresoc.v:129350$5032_Y + connect \$7 $not$libresoc.v:129351$5033_Y +end +attribute \src "libresoc.v:129476.1-129644.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:129604.3-129623.6" + wire width 3 $0\fast_o2[2:0] + attribute \src "libresoc.v:129624.3-129643.6" + wire $0\fast_o2_ok[0:0] + attribute \src "libresoc.v:129477.7-129477.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129584.3-129593.6" + wire width 5 $0\reg_o2[4:0] + attribute \src "libresoc.v:129594.3-129603.6" + wire $0\reg_o2_ok[0:0] + attribute \src "libresoc.v:129604.3-129623.6" + wire width 3 $1\fast_o2[2:0] + attribute \src "libresoc.v:129624.3-129643.6" + wire $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:129584.3-129593.6" + wire width 5 $1\reg_o2[4:0] + attribute \src "libresoc.v:129594.3-129603.6" + wire $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:129604.3-129623.6" + wire width 3 $2\fast_o2[2:0] + attribute \src "libresoc.v:129624.3-129643.6" + wire $2\fast_o2_ok[0:0] + attribute \src "libresoc.v:129582.17-129582.108" + wire $eq$libresoc.v:129582$5041_Y + attribute \src "libresoc.v:129583.17-129583.108" + wire $eq$libresoc.v:129583$5042_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 4 \fast_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \fast_o2_ok + attribute \src "libresoc.v:129477.7-129477.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_o2_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + cell $eq $eq$libresoc.v:129582$5041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:129582$5041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + cell $eq $eq$libresoc.v:129583$5042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:129583$5042_Y + end + attribute \src "libresoc.v:129477.7-129477.20" + process $proc$libresoc.v:129477$5047 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129584.3-129593.6" + process $proc$libresoc.v:129584$5043 + assign { } { } + assign { } { } + assign $0\reg_o2[4:0] $1\reg_o2[4:0] + attribute \src "libresoc.v:129585.5-129585.29" + switch \initial + attribute \src "libresoc.v:129585.9-129585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_o2[4:0] \RA + case + assign $1\reg_o2[4:0] 5'00000 + end + sync always + update \reg_o2 $0\reg_o2[4:0] + end + attribute \src "libresoc.v:129594.3-129603.6" + process $proc$libresoc.v:129594$5044 + assign { } { } + assign { } { } + assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:129595.5-129595.29" + switch \initial + attribute \src "libresoc.v:129595.9-129595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_o2_ok[0:0] 1'1 + case + assign $1\reg_o2_ok[0:0] 1'0 + end + sync always + update \reg_o2_ok $0\reg_o2_ok[0:0] + end + attribute \src "libresoc.v:129604.3-129623.6" + process $proc$libresoc.v:129604$5045 + assign { } { } + assign { } { } + assign $0\fast_o2[2:0] $1\fast_o2[2:0] + attribute \src "libresoc.v:129605.5-129605.29" + switch \initial + attribute \src "libresoc.v:129605.9-129605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o2[2:0] $2\fast_o2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o2[2:0] 3'001 + case + assign $2\fast_o2[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o2[2:0] 3'100 + case + assign $1\fast_o2[2:0] 3'000 + end + sync always + update \fast_o2 $0\fast_o2[2:0] + end + attribute \src "libresoc.v:129624.3-129643.6" + process $proc$libresoc.v:129624$5046 + assign { } { } + assign { } { } + assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:129625.5-129625.29" + switch \initial + attribute \src "libresoc.v:129625.9-129625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o2_ok[0:0] 1'1 + case + assign $2\fast_o2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o2_ok[0:0] 1'1 + case + assign $1\fast_o2_ok[0:0] 1'0 + end + sync always + update \fast_o2_ok $0\fast_o2_ok[0:0] + end + connect \$1 $eq$libresoc.v:129582$5041_Y + connect \$3 $eq$libresoc.v:129583$5042_Y +end +attribute \src "libresoc.v:129648.1-129783.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:129649.7-129649.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129741.3-129761.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:129762.3-129782.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:129741.3-129761.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:129762.3-129782.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:129741.3-129761.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:129762.3-129782.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \ALU_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \ALU_internal_op + attribute \src "libresoc.v:129649.7-129649.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:129649.7-129649.20" + process $proc$libresoc.v:129649$5050 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129741.3-129761.6" + process $proc$libresoc.v:129741$5048 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:129742.5-129742.29" + switch \initial + attribute \src "libresoc.v:129742.9-129742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \ALU_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \ALU_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:129762.3-129782.6" + process $proc$libresoc.v:129762$5049 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:129763.5-129763.29" + switch \initial + attribute \src "libresoc.v:129763.9-129763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \ALU_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:129787.1-129920.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$140 + attribute \src "libresoc.v:129788.7-129788.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129878.3-129898.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:129899.3-129919.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:129878.3-129898.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:129899.3-129919.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:129878.3-129898.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:129899.3-129919.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 2 \CR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \CR_internal_op + attribute \src "libresoc.v:129788.7-129788.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:129788.7-129788.20" + process $proc$libresoc.v:129788$5053 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129878.3-129898.6" + process $proc$libresoc.v:129878$5051 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:129879.5-129879.29" + switch \initial + attribute \src "libresoc.v:129879.9-129879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \CR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:129899.3-129919.6" + process $proc$libresoc.v:129899$5052 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:129900.5-129900.29" + switch \initial + attribute \src "libresoc.v:129900.9-129900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:129924.1-130057.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" +attribute \generator "nMigen" +module \dec_oe$143 + attribute \src "libresoc.v:129925.7-129925.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130015.3-130035.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130036.3-130056.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130015.3-130035.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130036.3-130056.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130015.3-130035.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130036.3-130056.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 2 \BRANCH_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \BRANCH_internal_op + attribute \src "libresoc.v:129925.7-129925.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:129925.7-129925.20" + process $proc$libresoc.v:129925$5056 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130015.3-130035.6" + process $proc$libresoc.v:130015$5054 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130016.5-130016.29" + switch \initial + attribute \src "libresoc.v:130016.9-130016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \BRANCH_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \BRANCH_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130036.3-130056.6" + process $proc$libresoc.v:130036$5055 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130037.5-130037.29" + switch \initial + attribute \src "libresoc.v:130037.9-130037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \BRANCH_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130061.1-130196.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$147 + attribute \src "libresoc.v:130062.7-130062.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130154.3-130174.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130175.3-130195.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130154.3-130174.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130175.3-130195.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130154.3-130174.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130175.3-130195.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \LOGICAL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "libresoc.v:130062.7-130062.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:130062.7-130062.20" + process $proc$libresoc.v:130062$5059 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130154.3-130174.6" + process $proc$libresoc.v:130154$5057 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130155.5-130155.29" + switch \initial + attribute \src "libresoc.v:130155.9-130155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \LOGICAL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LOGICAL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130175.3-130195.6" + process $proc$libresoc.v:130175$5058 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130176.5-130176.29" + switch \initial + attribute \src "libresoc.v:130176.9-130176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \LOGICAL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130200.1-130333.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$152 + attribute \src "libresoc.v:130201.7-130201.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130291.3-130311.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130312.3-130332.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130291.3-130311.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130312.3-130332.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130291.3-130311.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130312.3-130332.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 2 \SPR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \SPR_internal_op + attribute \src "libresoc.v:130201.7-130201.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:130201.7-130201.20" + process $proc$libresoc.v:130201$5062 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130291.3-130311.6" + process $proc$libresoc.v:130291$5060 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130292.5-130292.29" + switch \initial + attribute \src "libresoc.v:130292.9-130292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \SPR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SPR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130312.3-130332.6" + process $proc$libresoc.v:130312$5061 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130313.5-130313.29" + switch \initial + attribute \src "libresoc.v:130313.9-130313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \SPR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130337.1-130472.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" +attribute \generator "nMigen" +module \dec_oe$155 + attribute \src "libresoc.v:130338.7-130338.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130430.3-130450.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130451.3-130471.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130430.3-130450.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130451.3-130471.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130430.3-130450.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130451.3-130471.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \DIV_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \DIV_internal_op + attribute \src "libresoc.v:130338.7-130338.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:130338.7-130338.20" + process $proc$libresoc.v:130338$5065 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130430.3-130450.6" + process $proc$libresoc.v:130430$5063 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130431.5-130431.29" + switch \initial + attribute \src "libresoc.v:130431.9-130431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \DIV_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \DIV_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130451.3-130471.6" + process $proc$libresoc.v:130451$5064 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130452.5-130452.29" + switch \initial + attribute \src "libresoc.v:130452.9-130452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \DIV_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130476.1-130611.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$160 + attribute \src "libresoc.v:130477.7-130477.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130569.3-130589.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130590.3-130610.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130569.3-130589.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130590.3-130610.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130569.3-130589.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130590.3-130610.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \MUL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \MUL_internal_op + attribute \src "libresoc.v:130477.7-130477.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:130477.7-130477.20" + process $proc$libresoc.v:130477$5068 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130569.3-130589.6" + process $proc$libresoc.v:130569$5066 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130570.5-130570.29" + switch \initial + attribute \src "libresoc.v:130570.9-130570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \MUL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \MUL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130590.3-130610.6" + process $proc$libresoc.v:130590$5067 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130591.5-130591.29" + switch \initial + attribute \src "libresoc.v:130591.9-130591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \MUL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130615.1-130750.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" +attribute \generator "nMigen" +module \dec_oe$164 + attribute \src "libresoc.v:130616.7-130616.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130708.3-130728.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130729.3-130749.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130708.3-130728.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130729.3-130749.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130708.3-130728.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130729.3-130749.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \SHIFT_ROT_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "libresoc.v:130616.7-130616.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:130616.7-130616.20" + process $proc$libresoc.v:130616$5071 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130708.3-130728.6" + process $proc$libresoc.v:130708$5069 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130709.5-130709.29" + switch \initial + attribute \src "libresoc.v:130709.9-130709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \SHIFT_ROT_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SHIFT_ROT_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130729.3-130749.6" + process $proc$libresoc.v:130729$5070 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130730.5-130730.29" + switch \initial + attribute \src "libresoc.v:130730.9-130730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \SHIFT_ROT_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130754.1-130889.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" +attribute \generator "nMigen" +module \dec_oe$168 + attribute \src "libresoc.v:130755.7-130755.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130847.3-130867.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:130868.3-130888.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130847.3-130867.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:130868.3-130888.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130847.3-130867.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:130868.3-130888.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \LDST_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \LDST_internal_op + attribute \src "libresoc.v:130755.7-130755.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:130755.7-130755.20" + process $proc$libresoc.v:130755$5074 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130847.3-130867.6" + process $proc$libresoc.v:130847$5072 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130848.5-130848.29" + switch \initial + attribute \src "libresoc.v:130848.9-130848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \LDST_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LDST_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:130868.3-130888.6" + process $proc$libresoc.v:130868$5073 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:130869.5-130869.29" + switch \initial + attribute \src "libresoc.v:130869.9-130869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \LDST_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:130893.1-131028.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe$173 + attribute \src "libresoc.v:130894.7-130894.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130986.3-131006.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:131007.3-131027.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:130986.3-131006.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:131007.3-131027.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:130986.3-131006.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:131007.3-131027.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 4 \OE + attribute \src "libresoc.v:130894.7-130894.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:130894.7-130894.20" + process $proc$libresoc.v:130894$5077 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130986.3-131006.6" + process $proc$libresoc.v:130986$5075 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:130987.5-130987.29" + switch \initial + attribute \src "libresoc.v:130987.9-130987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:131007.3-131027.6" + process $proc$libresoc.v:131007$5076 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:131008.5-131008.29" + switch \initial + attribute \src "libresoc.v:131008.9-131008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:131032.1-131086.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:131033.7-131033.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131048.3-131066.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131067.3-131085.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131048.3-131066.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131067.3-131085.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \ALU_Rc + attribute \src "libresoc.v:131033.7-131033.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131033.7-131033.20" + process $proc$libresoc.v:131033$5080 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131048.3-131066.6" + process $proc$libresoc.v:131048$5078 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131049.5-131049.29" + switch \initial + attribute \src "libresoc.v:131049.9-131049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \ALU_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131067.3-131085.6" + process $proc$libresoc.v:131067$5079 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131068.5-131068.29" + switch \initial + attribute \src "libresoc.v:131068.9-131068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131090.1-131142.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$139 + attribute \src "libresoc.v:131091.7-131091.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131104.3-131122.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131123.3-131141.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131104.3-131122.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131123.3-131141.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 1 \CR_Rc + attribute \src "libresoc.v:131091.7-131091.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:131091.7-131091.20" + process $proc$libresoc.v:131091$5083 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131104.3-131122.6" + process $proc$libresoc.v:131104$5081 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131105.5-131105.29" + switch \initial + attribute \src "libresoc.v:131105.9-131105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \CR_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131123.3-131141.6" + process $proc$libresoc.v:131123$5082 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131124.5-131124.29" + switch \initial + attribute \src "libresoc.v:131124.9-131124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131146.1-131198.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" +attribute \generator "nMigen" +module \dec_rc$142 + attribute \src "libresoc.v:131147.7-131147.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131160.3-131178.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131179.3-131197.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131160.3-131178.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131179.3-131197.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 1 \BRANCH_Rc + attribute \src "libresoc.v:131147.7-131147.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:131147.7-131147.20" + process $proc$libresoc.v:131147$5086 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131160.3-131178.6" + process $proc$libresoc.v:131160$5084 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131161.5-131161.29" + switch \initial + attribute \src "libresoc.v:131161.9-131161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \BRANCH_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131179.3-131197.6" + process $proc$libresoc.v:131179$5085 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131180.5-131180.29" + switch \initial + attribute \src "libresoc.v:131180.9-131180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131202.1-131256.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$146 + attribute \src "libresoc.v:131203.7-131203.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131218.3-131236.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131237.3-131255.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131218.3-131236.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131237.3-131255.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \LOGICAL_Rc + attribute \src "libresoc.v:131203.7-131203.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131203.7-131203.20" + process $proc$libresoc.v:131203$5089 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131218.3-131236.6" + process $proc$libresoc.v:131218$5087 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131219.5-131219.29" + switch \initial + attribute \src "libresoc.v:131219.9-131219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LOGICAL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131237.3-131255.6" + process $proc$libresoc.v:131237$5088 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131238.5-131238.29" + switch \initial + attribute \src "libresoc.v:131238.9-131238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131260.1-131312.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$151 + attribute \src "libresoc.v:131261.7-131261.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131274.3-131292.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131293.3-131311.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131274.3-131292.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131293.3-131311.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 1 \SPR_Rc + attribute \src "libresoc.v:131261.7-131261.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:131261.7-131261.20" + process $proc$libresoc.v:131261$5092 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131274.3-131292.6" + process $proc$libresoc.v:131274$5090 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131275.5-131275.29" + switch \initial + attribute \src "libresoc.v:131275.9-131275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SPR_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131293.3-131311.6" + process $proc$libresoc.v:131293$5091 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131294.5-131294.29" + switch \initial + attribute \src "libresoc.v:131294.9-131294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131316.1-131370.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" +attribute \generator "nMigen" +module \dec_rc$154 + attribute \src "libresoc.v:131317.7-131317.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131332.3-131350.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131351.3-131369.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131332.3-131350.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131351.3-131369.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \DIV_Rc + attribute \src "libresoc.v:131317.7-131317.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131317.7-131317.20" + process $proc$libresoc.v:131317$5095 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131332.3-131350.6" + process $proc$libresoc.v:131332$5093 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131333.5-131333.29" + switch \initial + attribute \src "libresoc.v:131333.9-131333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \DIV_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131351.3-131369.6" + process $proc$libresoc.v:131351$5094 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131352.5-131352.29" + switch \initial + attribute \src "libresoc.v:131352.9-131352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131374.1-131428.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$159 + attribute \src "libresoc.v:131375.7-131375.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131390.3-131408.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131409.3-131427.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131390.3-131408.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131409.3-131427.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \MUL_Rc + attribute \src "libresoc.v:131375.7-131375.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131375.7-131375.20" + process $proc$libresoc.v:131375$5098 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131390.3-131408.6" + process $proc$libresoc.v:131390$5096 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131391.5-131391.29" + switch \initial + attribute \src "libresoc.v:131391.9-131391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \MUL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131409.3-131427.6" + process $proc$libresoc.v:131409$5097 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131410.5-131410.29" + switch \initial + attribute \src "libresoc.v:131410.9-131410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131432.1-131486.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" +attribute \generator "nMigen" +module \dec_rc$163 + attribute \src "libresoc.v:131433.7-131433.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131448.3-131466.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131467.3-131485.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131448.3-131466.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131467.3-131485.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \SHIFT_ROT_Rc + attribute \src "libresoc.v:131433.7-131433.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131433.7-131433.20" + process $proc$libresoc.v:131433$5101 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131448.3-131466.6" + process $proc$libresoc.v:131448$5099 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131449.5-131449.29" + switch \initial + attribute \src "libresoc.v:131449.9-131449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SHIFT_ROT_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131467.3-131485.6" + process $proc$libresoc.v:131467$5100 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131468.5-131468.29" + switch \initial + attribute \src "libresoc.v:131468.9-131468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131490.1-131544.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" +attribute \generator "nMigen" +module \dec_rc$167 + attribute \src "libresoc.v:131491.7-131491.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131506.3-131524.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131525.3-131543.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131506.3-131524.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131525.3-131543.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \LDST_Rc + attribute \src "libresoc.v:131491.7-131491.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131491.7-131491.20" + process $proc$libresoc.v:131491$5104 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131506.3-131524.6" + process $proc$libresoc.v:131506$5102 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131507.5-131507.29" + switch \initial + attribute \src "libresoc.v:131507.9-131507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LDST_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131525.3-131543.6" + process $proc$libresoc.v:131525$5103 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131526.5-131526.29" + switch \initial + attribute \src "libresoc.v:131526.9-131526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131548.1-131602.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc$172 + attribute \src "libresoc.v:131549.7-131549.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131564.3-131582.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:131583.3-131601.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:131564.3-131582.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:131583.3-131601.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + wire input 3 \Rc + attribute \src "libresoc.v:131549.7-131549.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:131549.7-131549.20" + process $proc$libresoc.v:131549$5107 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131564.3-131582.6" + process $proc$libresoc.v:131564$5105 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:131565.5-131565.29" + switch \initial + attribute \src "libresoc.v:131565.9-131565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:131583.3-131601.6" + process $proc$libresoc.v:131583$5106 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:131584.5-131584.29" + switch \initial + attribute \src "libresoc.v:131584.9-131584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:131606.1-132850.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" +attribute \generator "nMigen" +module \div0 + attribute \src "libresoc.v:132407.3-132408.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5247 + attribute \src "libresoc.v:132379.3-132380.75" + wire width 4 $0\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 + attribute \src "libresoc.v:132349.3-132350.73" + wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 + attribute \src "libresoc.v:132351.3-132352.87" + wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 + attribute \src "libresoc.v:132353.3-132354.83" + wire $0\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5251 + attribute \src "libresoc.v:132367.3-132368.81" + wire width 2 $0\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5252 + attribute \src "libresoc.v:132381.3-132382.67" + wire width 32 $0\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5253 + attribute \src "libresoc.v:132347.3-132348.77" + wire width 7 $0\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5254 + attribute \src "libresoc.v:132363.3-132364.77" + wire $0\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5255 + attribute \src "libresoc.v:132369.3-132370.79" + wire $0\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 + attribute \src "libresoc.v:132375.3-132376.75" + wire $0\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5257 + attribute \src "libresoc.v:132377.3-132378.77" + wire $0\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 + attribute \src "libresoc.v:132359.3-132360.71" + wire $0\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 + attribute \src "libresoc.v:132361.3-132362.71" + wire $0\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5260 + attribute \src "libresoc.v:132373.3-132374.83" + wire $0\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 + attribute \src "libresoc.v:132357.3-132358.71" + wire $0\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 + attribute \src "libresoc.v:132355.3-132356.71" + wire $0\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 + attribute \src "libresoc.v:132371.3-132372.77" + wire $0\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5264 + attribute \src "libresoc.v:132365.3-132366.71" + wire $0\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:132405.3-132406.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:132760.3-132768.6" + wire $0\alu_l_r_alu$next[0:0]$5334 + attribute \src "libresoc.v:132321.3-132322.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:132751.3-132759.6" + wire $0\alui_l_r_alui$next[0:0]$5331 + attribute \src "libresoc.v:132323.3-132324.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $0\data_r0__o$next[63:0]$5290 + attribute \src "libresoc.v:132343.3-132344.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:132633.3-132654.6" + wire $0\data_r0__o_ok$next[0:0]$5291 + attribute \src "libresoc.v:132345.3-132346.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5298 + attribute \src "libresoc.v:132339.3-132340.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:132655.3-132676.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5299 + attribute \src "libresoc.v:132341.3-132342.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5306 + attribute \src "libresoc.v:132335.3-132336.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:132677.3-132698.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5307 + attribute \src "libresoc.v:132337.3-132338.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:132699.3-132720.6" + wire $0\data_r3__xer_so$next[0:0]$5314 + attribute \src "libresoc.v:132331.3-132332.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:132699.3-132720.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5315 + attribute \src "libresoc.v:132333.3-132334.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:132769.3-132778.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:132779.3-132788.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:132789.3-132798.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:132799.3-132808.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:131607.7-131607.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132549.3-132557.6" + wire $0\opc_l_r_opc$next[0:0]$5232 + attribute \src "libresoc.v:132391.3-132392.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:132540.3-132548.6" + wire $0\opc_l_s_opc$next[0:0]$5229 + attribute \src "libresoc.v:132393.3-132394.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:132809.3-132817.6" + wire width 4 $0\prev_wr_go$next[3:0]$5341 + attribute \src "libresoc.v:132403.3-132404.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:132494.3-132503.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:132585.3-132593.6" + wire width 4 $0\req_l_r_req$next[3:0]$5244 + attribute \src "libresoc.v:132383.3-132384.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:132576.3-132584.6" + wire width 4 $0\req_l_s_req$next[3:0]$5241 + attribute \src "libresoc.v:132385.3-132386.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:132513.3-132521.6" + wire $0\rok_l_r_rdok$next[0:0]$5220 + attribute \src "libresoc.v:132399.3-132400.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:132504.3-132512.6" + wire $0\rok_l_s_rdok$next[0:0]$5217 + attribute \src "libresoc.v:132401.3-132402.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:132531.3-132539.6" + wire $0\rst_l_r_rst$next[0:0]$5226 + attribute \src "libresoc.v:132395.3-132396.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:132522.3-132530.6" + wire $0\rst_l_s_rst$next[0:0]$5223 + attribute \src "libresoc.v:132397.3-132398.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:132567.3-132575.6" + wire width 3 $0\src_l_r_src$next[2:0]$5238 + attribute \src "libresoc.v:132387.3-132388.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:132558.3-132566.6" + wire width 3 $0\src_l_s_src$next[2:0]$5235 + attribute \src "libresoc.v:132389.3-132390.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:132721.3-132730.6" + wire width 64 $0\src_r0$next[63:0]$5322 + attribute \src "libresoc.v:132329.3-132330.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:132731.3-132740.6" + wire width 64 $0\src_r1$next[63:0]$5325 + attribute \src "libresoc.v:132327.3-132328.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:132741.3-132750.6" + wire $0\src_r2$next[0:0]$5328 + attribute \src "libresoc.v:132325.3-132326.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:131737.7-131737.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5265 + attribute \src "libresoc.v:131747.13-131747.49" + wire width 4 $1\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 + attribute \src "libresoc.v:131766.14-131766.53" + wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + attribute \src "libresoc.v:131770.14-131770.72" + wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + attribute \src "libresoc.v:131774.7-131774.47" + wire $1\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 + attribute \src "libresoc.v:131782.13-131782.52" + wire width 2 $1\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5270 + attribute \src "libresoc.v:131786.14-131786.47" + wire width 32 $1\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 + attribute \src "libresoc.v:131865.13-131865.51" + wire width 7 $1\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5272 + attribute \src "libresoc.v:131869.7-131869.44" + wire $1\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5273 + attribute \src "libresoc.v:131873.7-131873.45" + wire $1\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 + attribute \src "libresoc.v:131877.7-131877.43" + wire $1\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5275 + attribute \src "libresoc.v:131881.7-131881.44" + wire $1\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 + attribute \src "libresoc.v:131885.7-131885.41" + wire $1\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 + attribute \src "libresoc.v:131889.7-131889.41" + wire $1\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5278 + attribute \src "libresoc.v:131893.7-131893.47" + wire $1\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 + attribute \src "libresoc.v:131897.7-131897.41" + wire $1\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 + attribute \src "libresoc.v:131901.7-131901.41" + wire $1\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 + attribute \src "libresoc.v:131905.7-131905.44" + wire $1\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5282 + attribute \src "libresoc.v:131909.7-131909.41" + wire $1\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:131935.7-131935.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:132760.3-132768.6" + wire $1\alu_l_r_alu$next[0:0]$5335 + attribute \src "libresoc.v:131943.7-131943.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:132751.3-132759.6" + wire $1\alui_l_r_alui$next[0:0]$5332 + attribute \src "libresoc.v:131955.7-131955.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $1\data_r0__o$next[63:0]$5292 + attribute \src "libresoc.v:131989.14-131989.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:132633.3-132654.6" + wire $1\data_r0__o_ok$next[0:0]$5293 + attribute \src "libresoc.v:131993.7-131993.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5300 + attribute \src "libresoc.v:131997.13-131997.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:132655.3-132676.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5301 + attribute \src "libresoc.v:132001.7-132001.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5308 + attribute \src "libresoc.v:132005.13-132005.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:132677.3-132698.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5309 + attribute \src "libresoc.v:132009.7-132009.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:132699.3-132720.6" + wire $1\data_r3__xer_so$next[0:0]$5316 + attribute \src "libresoc.v:132013.7-132013.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:132699.3-132720.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5317 + attribute \src "libresoc.v:132017.7-132017.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:132769.3-132778.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:132779.3-132788.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:132789.3-132798.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:132799.3-132808.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:132549.3-132557.6" + wire $1\opc_l_r_opc$next[0:0]$5233 + attribute \src "libresoc.v:132037.7-132037.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:132540.3-132548.6" + wire $1\opc_l_s_opc$next[0:0]$5230 + attribute \src "libresoc.v:132041.7-132041.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:132809.3-132817.6" + wire width 4 $1\prev_wr_go$next[3:0]$5342 + attribute \src "libresoc.v:132175.13-132175.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:132494.3-132503.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:132585.3-132593.6" + wire width 4 $1\req_l_r_req$next[3:0]$5245 + attribute \src "libresoc.v:132183.13-132183.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:132576.3-132584.6" + wire width 4 $1\req_l_s_req$next[3:0]$5242 + attribute \src "libresoc.v:132187.13-132187.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:132513.3-132521.6" + wire $1\rok_l_r_rdok$next[0:0]$5221 + attribute \src "libresoc.v:132199.7-132199.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:132504.3-132512.6" + wire $1\rok_l_s_rdok$next[0:0]$5218 + attribute \src "libresoc.v:132203.7-132203.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:132531.3-132539.6" + wire $1\rst_l_r_rst$next[0:0]$5227 + attribute \src "libresoc.v:132207.7-132207.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:132522.3-132530.6" + wire $1\rst_l_s_rst$next[0:0]$5224 + attribute \src "libresoc.v:132211.7-132211.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:132567.3-132575.6" + wire width 3 $1\src_l_r_src$next[2:0]$5239 + attribute \src "libresoc.v:132225.13-132225.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:132558.3-132566.6" + wire width 3 $1\src_l_s_src$next[2:0]$5236 + attribute \src "libresoc.v:132229.13-132229.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:132721.3-132730.6" + wire width 64 $1\src_r0$next[63:0]$5323 + attribute \src "libresoc.v:132237.14-132237.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:132731.3-132740.6" + wire width 64 $1\src_r1$next[63:0]$5326 + attribute \src "libresoc.v:132241.14-132241.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:132741.3-132750.6" + wire $1\src_r2$next[0:0]$5329 + attribute \src "libresoc.v:132245.7-132245.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $2\data_r0__o$next[63:0]$5294 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_div0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_div0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_div0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_div0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_div0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 37 \dest4_o + attribute \src "libresoc.v:131607.7-131607.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + 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\cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:132293$5143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:132258$5108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__zero_a + connect \Y $not$libresoc.v:132258$5108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:132259$5109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:132259$5109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:132261$5111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:132261$5111_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:132274$5124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:132274$5124_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:132276$5126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:132276$5126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:132279$5129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:132279$5129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:132282$5132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:132282$5132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:132288$5138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_ready_i + connect \Y $not$libresoc.v:132288$5138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:132299$5149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:132299$5149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:132287$5137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:132287$5137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:132297$5147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:132297$5147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:132298$5148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:132298$5148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:132300$5150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:132300$5150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:132301$5151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:132301$5151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:132304$5154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:132304$5154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:132310$5160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:132310$5160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:132315$5165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:132315$5165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:132281$5131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:132281$5131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:132285$5135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:132285$5135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:132286$5136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:132286$5136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:132309$5159 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:132309$5159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:132311$5161 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:132311$5161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:132312$5162 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:132312$5162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:132313$5163 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:132313$5163_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:132314$5164 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:132314$5164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:132316$5166 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $ternary$libresoc.v:132316$5166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:132317$5167 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:132317$5167_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132409.12-132445.4" + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_div0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__insn \alu_div0_logical_op__insn + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \n_ready_i \alu_div0_n_ready_i + connect \n_valid_o \alu_div0_n_valid_o + connect \o \alu_div0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_div0_p_ready_o + connect \p_valid_i \alu_div0_p_valid_i + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_ov \alu_div0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_div0_xer_so + connect \xer_so$1 \alu_div0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132446.14-132452.4" + cell \alu_l$90 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132453.15-132459.4" + cell \alui_l$89 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132460.14-132466.4" + cell \opc_l$85 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132467.14-132473.4" + cell \req_l$86 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132474.14-132480.4" + cell \rok_l$88 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132481.14-132486.4" + cell \rst_l$87 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132487.14-132493.4" + cell \src_l$84 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:131607.7-131607.20" + process $proc$libresoc.v:131607$5343 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131737.7-131737.24" + process $proc$libresoc.v:131737$5344 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:131747.13-131747.49" + process $proc$libresoc.v:131747$5345 + assign { } { } + assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:131766.14-131766.53" + process $proc$libresoc.v:131766$5346 + assign { } { } + assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:131770.14-131770.72" + process $proc$libresoc.v:131770$5347 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:131774.7-131774.47" + process $proc$libresoc.v:131774$5348 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:131782.13-131782.52" + process $proc$libresoc.v:131782$5349 + assign { } { } + assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:131786.14-131786.47" + process $proc$libresoc.v:131786$5350 + assign { } { } + assign $1\alu_div0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:131865.13-131865.51" + process $proc$libresoc.v:131865$5351 + assign { } { } + assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:131869.7-131869.44" + process $proc$libresoc.v:131869$5352 + assign { } { } + assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:131873.7-131873.45" + process $proc$libresoc.v:131873$5353 + assign { } { } + assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:131877.7-131877.43" + process $proc$libresoc.v:131877$5354 + assign { } { } + assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:131881.7-131881.44" + process $proc$libresoc.v:131881$5355 + assign { } { } + assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:131885.7-131885.41" + process $proc$libresoc.v:131885$5356 + assign { } { } + assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:131889.7-131889.41" + process $proc$libresoc.v:131889$5357 + assign { } { } + assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:131893.7-131893.47" + process $proc$libresoc.v:131893$5358 + assign { } { } + assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:131897.7-131897.41" + process $proc$libresoc.v:131897$5359 + assign { } { } + assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:131901.7-131901.41" + process $proc$libresoc.v:131901$5360 + assign { } { } + assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:131905.7-131905.44" + process $proc$libresoc.v:131905$5361 + assign { } { } + assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:131909.7-131909.41" + process $proc$libresoc.v:131909$5362 + assign { } { } + assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:131935.7-131935.26" + process $proc$libresoc.v:131935$5363 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:131943.7-131943.25" + process $proc$libresoc.v:131943$5364 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:131955.7-131955.27" + process $proc$libresoc.v:131955$5365 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:131989.14-131989.47" + process $proc$libresoc.v:131989$5366 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:131993.7-131993.27" + process $proc$libresoc.v:131993$5367 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:131997.13-131997.33" + process $proc$libresoc.v:131997$5368 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:132001.7-132001.30" + process $proc$libresoc.v:132001$5369 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:132005.13-132005.35" + process $proc$libresoc.v:132005$5370 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:132009.7-132009.32" + process $proc$libresoc.v:132009$5371 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:132013.7-132013.29" + process $proc$libresoc.v:132013$5372 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:132017.7-132017.32" + process $proc$libresoc.v:132017$5373 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:132037.7-132037.25" + process $proc$libresoc.v:132037$5374 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:132041.7-132041.25" + process $proc$libresoc.v:132041$5375 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:132175.13-132175.30" + process $proc$libresoc.v:132175$5376 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:132183.13-132183.31" + process $proc$libresoc.v:132183$5377 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:132187.13-132187.31" + process $proc$libresoc.v:132187$5378 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:132199.7-132199.26" + process $proc$libresoc.v:132199$5379 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:132203.7-132203.26" + process $proc$libresoc.v:132203$5380 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:132207.7-132207.25" + process $proc$libresoc.v:132207$5381 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:132211.7-132211.25" + process $proc$libresoc.v:132211$5382 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:132225.13-132225.31" + process $proc$libresoc.v:132225$5383 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:132229.13-132229.31" + process $proc$libresoc.v:132229$5384 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:132237.14-132237.43" + process $proc$libresoc.v:132237$5385 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:132241.14-132241.43" + process $proc$libresoc.v:132241$5386 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:132245.7-132245.20" + process $proc$libresoc.v:132245$5387 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:132321.3-132322.39" + process $proc$libresoc.v:132321$5171 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:132323.3-132324.43" + process $proc$libresoc.v:132323$5172 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:132325.3-132326.29" + process $proc$libresoc.v:132325$5173 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:132327.3-132328.29" + process $proc$libresoc.v:132327$5174 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:132329.3-132330.29" + process $proc$libresoc.v:132329$5175 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:132331.3-132332.47" + process $proc$libresoc.v:132331$5176 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:132333.3-132334.53" + process $proc$libresoc.v:132333$5177 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:132335.3-132336.47" + process $proc$libresoc.v:132335$5178 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:132337.3-132338.53" + process $proc$libresoc.v:132337$5179 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:132339.3-132340.43" + process $proc$libresoc.v:132339$5180 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:132341.3-132342.49" + process $proc$libresoc.v:132341$5181 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:132343.3-132344.37" + process $proc$libresoc.v:132343$5182 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:132345.3-132346.43" + process $proc$libresoc.v:132345$5183 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:132347.3-132348.77" + process $proc$libresoc.v:132347$5184 + assign { } { } + assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:132349.3-132350.73" + process $proc$libresoc.v:132349$5185 + assign { } { } + assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:132351.3-132352.87" + process $proc$libresoc.v:132351$5186 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:132353.3-132354.83" + process $proc$libresoc.v:132353$5187 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:132355.3-132356.71" + process $proc$libresoc.v:132355$5188 + assign { } { } + assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:132357.3-132358.71" + process $proc$libresoc.v:132357$5189 + assign { } { } + assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:132359.3-132360.71" + process $proc$libresoc.v:132359$5190 + assign { } { } + assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:132361.3-132362.71" + process $proc$libresoc.v:132361$5191 + assign { } { } + assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:132363.3-132364.77" + process $proc$libresoc.v:132363$5192 + assign { } { } + assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:132365.3-132366.71" + process $proc$libresoc.v:132365$5193 + assign { } { } + assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:132367.3-132368.81" + process $proc$libresoc.v:132367$5194 + assign { } { } + assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:132369.3-132370.79" + process $proc$libresoc.v:132369$5195 + assign { } { } + assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:132371.3-132372.77" + process $proc$libresoc.v:132371$5196 + assign { } { } + assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:132373.3-132374.83" + process $proc$libresoc.v:132373$5197 + assign { } { } + assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:132375.3-132376.75" + process $proc$libresoc.v:132375$5198 + assign { } { } + assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:132377.3-132378.77" + process $proc$libresoc.v:132377$5199 + assign { } { } + assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:132379.3-132380.75" + process $proc$libresoc.v:132379$5200 + assign { } { } + assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:132381.3-132382.67" + process $proc$libresoc.v:132381$5201 + assign { } { } + assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:132383.3-132384.39" + process $proc$libresoc.v:132383$5202 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:132385.3-132386.39" + process $proc$libresoc.v:132385$5203 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:132387.3-132388.39" + process $proc$libresoc.v:132387$5204 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:132389.3-132390.39" + process $proc$libresoc.v:132389$5205 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:132391.3-132392.39" + process $proc$libresoc.v:132391$5206 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:132393.3-132394.39" + process $proc$libresoc.v:132393$5207 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:132395.3-132396.39" + process $proc$libresoc.v:132395$5208 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:132397.3-132398.39" + process $proc$libresoc.v:132397$5209 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:132399.3-132400.41" + process $proc$libresoc.v:132399$5210 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:132401.3-132402.41" + process $proc$libresoc.v:132401$5211 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:132403.3-132404.37" + process $proc$libresoc.v:132403$5212 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:132405.3-132406.40" + process $proc$libresoc.v:132405$5213 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:132407.3-132408.25" + process $proc$libresoc.v:132407$5214 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:132494.3-132503.6" + process $proc$libresoc.v:132494$5215 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:132495.5-132495.29" + switch \initial + attribute \src "libresoc.v:132495.9-132495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:132504.3-132512.6" + process $proc$libresoc.v:132504$5216 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$5217 $1\rok_l_s_rdok$next[0:0]$5218 + attribute \src "libresoc.v:132505.5-132505.29" + switch \initial + attribute \src "libresoc.v:132505.9-132505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$5218 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$5218 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5217 + end + attribute \src "libresoc.v:132513.3-132521.6" + process $proc$libresoc.v:132513$5219 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$5220 $1\rok_l_r_rdok$next[0:0]$5221 + attribute \src "libresoc.v:132514.5-132514.29" + switch \initial + attribute \src "libresoc.v:132514.9-132514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$5221 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$5221 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5220 + end + attribute \src "libresoc.v:132522.3-132530.6" + process $proc$libresoc.v:132522$5222 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$5223 $1\rst_l_s_rst$next[0:0]$5224 + attribute \src "libresoc.v:132523.5-132523.29" + switch \initial + attribute \src "libresoc.v:132523.9-132523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$5224 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$5224 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5223 + end + attribute \src "libresoc.v:132531.3-132539.6" + process $proc$libresoc.v:132531$5225 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$5226 $1\rst_l_r_rst$next[0:0]$5227 + attribute \src "libresoc.v:132532.5-132532.29" + switch \initial + attribute \src "libresoc.v:132532.9-132532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$5227 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$5227 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5226 + end + attribute \src "libresoc.v:132540.3-132548.6" + process $proc$libresoc.v:132540$5228 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$5229 $1\opc_l_s_opc$next[0:0]$5230 + attribute \src "libresoc.v:132541.5-132541.29" + switch \initial + attribute \src "libresoc.v:132541.9-132541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$5230 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$5230 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5229 + end + attribute \src "libresoc.v:132549.3-132557.6" + process $proc$libresoc.v:132549$5231 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$5232 $1\opc_l_r_opc$next[0:0]$5233 + attribute \src "libresoc.v:132550.5-132550.29" + switch \initial + attribute \src "libresoc.v:132550.9-132550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$5233 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$5233 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5232 + end + attribute \src "libresoc.v:132558.3-132566.6" + process $proc$libresoc.v:132558$5234 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$5235 $1\src_l_s_src$next[2:0]$5236 + attribute \src "libresoc.v:132559.5-132559.29" + switch \initial + attribute \src "libresoc.v:132559.9-132559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$5236 3'000 + case + assign $1\src_l_s_src$next[2:0]$5236 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5235 + end + attribute \src "libresoc.v:132567.3-132575.6" + process $proc$libresoc.v:132567$5237 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$5238 $1\src_l_r_src$next[2:0]$5239 + attribute \src "libresoc.v:132568.5-132568.29" + switch \initial + attribute \src "libresoc.v:132568.9-132568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$5239 3'111 + case + assign $1\src_l_r_src$next[2:0]$5239 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5238 + end + attribute \src "libresoc.v:132576.3-132584.6" + process $proc$libresoc.v:132576$5240 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$5241 $1\req_l_s_req$next[3:0]$5242 + attribute \src "libresoc.v:132577.5-132577.29" + switch \initial + attribute \src "libresoc.v:132577.9-132577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$5242 4'0000 + case + assign $1\req_l_s_req$next[3:0]$5242 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5241 + end + attribute \src "libresoc.v:132585.3-132593.6" + process $proc$libresoc.v:132585$5243 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$5244 $1\req_l_r_req$next[3:0]$5245 + attribute \src "libresoc.v:132586.5-132586.29" + switch \initial + attribute \src "libresoc.v:132586.9-132586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$5245 4'1111 + case + assign $1\req_l_r_req$next[3:0]$5245 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5244 + end + attribute \src "libresoc.v:132594.3-132632.6" + process $proc$libresoc.v:132594$5246 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__data_len$next[3:0]$5247 $1\alu_div0_logical_op__data_len$next[3:0]$5265 + assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5251 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 + assign $0\alu_div0_logical_op__insn$next[31:0]$5252 $1\alu_div0_logical_op__insn$next[31:0]$5270 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5253 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5254 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5255 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5257 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5260 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5264 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 + attribute \src "libresoc.v:132595.5-132595.29" + switch \initial + attribute \src "libresoc.v:132595.9-132595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5270 $1\alu_div0_logical_op__data_len$next[3:0]$5265 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + case + assign $1\alu_div0_logical_op__data_len$next[3:0]$5265 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5269 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5270 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5271 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5272 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5273 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5275 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5278 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5282 \alu_div0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 1'0 + case + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 + end + sync always + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5247 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5251 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5252 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5253 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5254 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5255 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5257 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5260 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5264 + end + attribute \src "libresoc.v:132633.3-132654.6" + process $proc$libresoc.v:132633$5289 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$5290 $2\data_r0__o$next[63:0]$5294 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$5291 $3\data_r0__o_ok$next[0:0]$5296 + attribute \src "libresoc.v:132634.5-132634.29" + switch \initial + attribute \src "libresoc.v:132634.9-132634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$5293 $1\data_r0__o$next[63:0]$5292 } { \o_ok \alu_div0_o } + case + assign $1\data_r0__o$next[63:0]$5292 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5293 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o$next[63:0]$5294 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$5294 $1\data_r0__o$next[63:0]$5292 + assign $2\data_r0__o_ok$next[0:0]$5295 $1\data_r0__o_ok$next[0:0]$5293 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$5296 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$5296 $2\data_r0__o_ok$next[0:0]$5295 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$5290 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5291 + end + attribute \src "libresoc.v:132655.3-132676.6" + process $proc$libresoc.v:132655$5297 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$5298 $2\data_r1__cr_a$next[3:0]$5302 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$5299 $3\data_r1__cr_a_ok$next[0:0]$5304 + attribute \src "libresoc.v:132656.5-132656.29" + switch \initial + attribute \src "libresoc.v:132656.9-132656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$5301 $1\data_r1__cr_a$next[3:0]$5300 } { \cr_a_ok \alu_div0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$5300 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5301 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a$next[3:0]$5302 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$5302 $1\data_r1__cr_a$next[3:0]$5300 + assign $2\data_r1__cr_a_ok$next[0:0]$5303 $1\data_r1__cr_a_ok$next[0:0]$5301 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$5304 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$5304 $2\data_r1__cr_a_ok$next[0:0]$5303 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5298 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5299 + end + attribute \src "libresoc.v:132677.3-132698.6" + process $proc$libresoc.v:132677$5305 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$5306 $2\data_r2__xer_ov$next[1:0]$5310 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$5307 $3\data_r2__xer_ov_ok$next[0:0]$5312 + attribute \src "libresoc.v:132678.5-132678.29" + switch \initial + attribute \src "libresoc.v:132678.9-132678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5309 $1\data_r2__xer_ov$next[1:0]$5308 } { \xer_ov_ok \alu_div0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$5308 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5309 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov$next[1:0]$5310 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$5310 $1\data_r2__xer_ov$next[1:0]$5308 + assign $2\data_r2__xer_ov_ok$next[0:0]$5311 $1\data_r2__xer_ov_ok$next[0:0]$5309 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$5312 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$5312 $2\data_r2__xer_ov_ok$next[0:0]$5311 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5306 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5307 + end + attribute \src "libresoc.v:132699.3-132720.6" + process $proc$libresoc.v:132699$5313 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$5314 $2\data_r3__xer_so$next[0:0]$5318 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$5315 $3\data_r3__xer_so_ok$next[0:0]$5320 + attribute \src "libresoc.v:132700.5-132700.29" + switch \initial + attribute \src "libresoc.v:132700.9-132700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5316 } { \xer_so_ok \alu_div0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$5316 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5317 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so$next[0:0]$5318 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$5318 $1\data_r3__xer_so$next[0:0]$5316 + assign $2\data_r3__xer_so_ok$next[0:0]$5319 $1\data_r3__xer_so_ok$next[0:0]$5317 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$5320 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$5320 $2\data_r3__xer_so_ok$next[0:0]$5319 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5314 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5315 + end + attribute \src "libresoc.v:132721.3-132730.6" + process $proc$libresoc.v:132721$5321 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$5322 $1\src_r0$next[63:0]$5323 + attribute \src "libresoc.v:132722.5-132722.29" + switch \initial + attribute \src "libresoc.v:132722.9-132722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$5323 \src_or_imm + case + assign $1\src_r0$next[63:0]$5323 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$5322 + end + attribute \src "libresoc.v:132731.3-132740.6" + process $proc$libresoc.v:132731$5324 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$5325 $1\src_r1$next[63:0]$5326 + attribute \src "libresoc.v:132732.5-132732.29" + switch \initial + attribute \src "libresoc.v:132732.9-132732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$82 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$5326 \src_or_imm$85 + case + assign $1\src_r1$next[63:0]$5326 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$5325 + end + attribute \src "libresoc.v:132741.3-132750.6" + process $proc$libresoc.v:132741$5327 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$5328 $1\src_r2$next[0:0]$5329 + attribute \src "libresoc.v:132742.5-132742.29" + switch \initial + attribute \src "libresoc.v:132742.9-132742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$5329 \src3_i + case + assign $1\src_r2$next[0:0]$5329 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$5328 + end + attribute \src "libresoc.v:132751.3-132759.6" + process $proc$libresoc.v:132751$5330 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$5331 $1\alui_l_r_alui$next[0:0]$5332 + attribute \src "libresoc.v:132752.5-132752.29" + switch \initial + attribute \src "libresoc.v:132752.9-132752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$5332 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$5332 \$94 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5331 + end + attribute \src "libresoc.v:132760.3-132768.6" + process $proc$libresoc.v:132760$5333 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$5334 $1\alu_l_r_alu$next[0:0]$5335 + attribute \src "libresoc.v:132761.5-132761.29" + switch \initial + attribute \src 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64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:132779.3-132788.6" + process $proc$libresoc.v:132779$5337 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:132780.5-132780.29" + switch \initial + attribute \src "libresoc.v:132780.9-132780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$124 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:132789.3-132798.6" + process $proc$libresoc.v:132789$5338 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:132790.5-132790.29" + switch \initial + attribute \src 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wire \next_quotient_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 5 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" + wire width 128 \value + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + cell $add $add$libresoc.v:132903$5388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \i_q_bits_known + connect \B 1'1 + connect \Y $add$libresoc.v:132903$5388_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:132904$5389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $ge$libresoc.v:132904$5389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:132908$5393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $ge$libresoc.v:132908$5393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + cell $not $not$libresoc.v:132907$5392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \difference [127] + connect \Y $not$libresoc.v:132907$5392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sshl $sshl$libresoc.v:132905$5390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 127 + connect \A \divisor + connect \B 6'111111 + connect \Y $sshl$libresoc.v:132905$5390_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sub $sub$libresoc.v:132906$5391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 127 + parameter \Y_WIDTH 129 + connect \A \i_dividend_quotient + connect \B \$2 + connect \Y $sub$libresoc.v:132906$5391_Y + end + attribute \src "libresoc.v:132868.7-132868.20" + process $proc$libresoc.v:132868$5397 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132909.3-132920.6" + process $proc$libresoc.v:132909$5394 + assign { } { } + assign $0\value[127:0] $1\value[127:0] + attribute \src "libresoc.v:132910.5-132910.29" + switch \initial + attribute \src "libresoc.v:132910.9-132910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" + switch \next_quotient_bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\value[127:0] \difference + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\value[127:0] \i_dividend_quotient + end + sync always + update \value $0\value[127:0] + end + attribute \src "libresoc.v:132921.3-132932.6" + process $proc$libresoc.v:132921$5395 + assign { } { } + assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] + attribute \src "libresoc.v:132922.5-132922.29" + switch \initial + attribute \src "libresoc.v:132922.9-132922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_q_bits_known[6:0] \i_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_q_bits_known[6:0] \$10 [6:0] + end + sync always + update \o_q_bits_known $0\o_q_bits_known[6:0] + end + attribute \src "libresoc.v:132933.3-132944.6" + process $proc$libresoc.v:132933$5396 + assign { } { } + assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] + attribute \src "libresoc.v:132934.5-132934.29" + switch \initial + attribute \src "libresoc.v:132934.9-132934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_dividend_quotient[127:0] \i_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } + end + sync always + update \o_dividend_quotient $0\o_dividend_quotient[127:0] + end + connect \$11 $add$libresoc.v:132903$5388_Y + connect \$13 $ge$libresoc.v:132904$5389_Y + connect \$2 $sshl$libresoc.v:132905$5390_Y + connect \$4 $sub$libresoc.v:132906$5391_Y + connect \$6 $not$libresoc.v:132907$5392_Y + connect \$8 $ge$libresoc.v:132908$5393_Y + connect \$1 \$4 + connect \$10 \$11 + connect \next_quotient_bit \$6 + connect \difference \$4 [127:0] +end +attribute \src "libresoc.v:132953.1-133196.10" +attribute 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width 64 output 24 \ra$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 25 \rb$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute 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\dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 16 \dest1__wen + attribute \src "libresoc.v:133201.7-133201.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 2 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 5 \issue__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 7 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 4 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 3 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 9 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 8 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 12 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 11 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \src2__ren + attribute \src "libresoc.v:133281.14-133281.20" + memory width 64 size 8 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5435 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5435 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5436 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5436 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5437 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5437 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5438 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5438 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5439 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5439 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5440 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5440 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5441 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5441 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5442 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5442 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:133302.26-133302.32" + cell $memrd $memrd$\memory$libresoc.v:133302$5420 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:133302$5420_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:133303.30-133303.36" + cell $memrd $memrd$\memory$libresoc.v:133303$5421 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:133303$5421_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:133304.30-133304.36" + cell $memrd $memrd$\memory$libresoc.v:133304$5422 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:133304$5422_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5443 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5443 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:133299$5406_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:133299$5406_DATA + connect \EN $memwr$\memory$libresoc.v:133299$5406_EN + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5444 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5444 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:133300$5407_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:133300$5407_DATA + connect \EN $memwr$\memory$libresoc.v:133300$5407_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5451 + sync always + sync init + end + attribute \src "libresoc.v:133201.7-133201.20" + process $proc$libresoc.v:133201$5445 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133250.7-133250.23" + process $proc$libresoc.v:133250$5446 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:133252.7-133252.28" + process $proc$libresoc.v:133252$5447 + assign { } { } + assign $0\ren_delay$10[0:0]$5448 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5448 + end + attribute \src "libresoc.v:133256.7-133256.28" + process $proc$libresoc.v:133256$5449 + assign { } { } + assign $0\ren_delay$11[0:0]$5450 1'0 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$5450 + end + attribute \src "libresoc.v:133275.3-133276.43" + process $proc$libresoc.v:133275$5408 + assign { } { } + assign $0\ren_delay$11[0:0]$5409 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5409 + end + attribute \src "libresoc.v:133277.3-133278.43" + process $proc$libresoc.v:133277$5410 + assign { } { } + assign $0\ren_delay$10[0:0]$5411 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5411 + end + attribute \src "libresoc.v:133279.3-133280.35" + process $proc$libresoc.v:133279$5412 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:133295.3-133301.6" + process $proc$libresoc.v:133295$5413 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 3'xxx + assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 3'xxx + assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[2:0] \src1__addr + assign $0\_1_[2:0] \src2__addr + assign $0\_2_[2:0] \issue__addr + attribute \src "libresoc.v:133299.5-133299.62" + switch \issue__wen + attribute \src "libresoc.v:133299.9-133299.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 \issue__data_i + assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + attribute \src "libresoc.v:133300.5-133300.58" + switch \dest1__wen + attribute \src "libresoc.v:133300.9-133300.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 \dest1__addr + assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[2:0] + update \_1_ $0\_1_[2:0] + update \_2_ $0\_2_[2:0] + update $memwr$\memory$libresoc.v:133299$5406_ADDR $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 + update $memwr$\memory$libresoc.v:133299$5406_DATA $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 + update $memwr$\memory$libresoc.v:133299$5406_EN $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 + update $memwr$\memory$libresoc.v:133300$5407_ADDR $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 + update $memwr$\memory$libresoc.v:133300$5407_DATA $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 + update $memwr$\memory$libresoc.v:133300$5407_EN $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 + end + attribute \src "libresoc.v:133305.3-133313.6" + process $proc$libresoc.v:133305$5423 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5424 $1\ren_delay$next[0:0]$5425 + attribute \src "libresoc.v:133306.5-133306.29" + switch \initial + attribute \src "libresoc.v:133306.9-133306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5425 1'0 + case + assign $1\ren_delay$next[0:0]$5425 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5424 + end + attribute \src "libresoc.v:133314.3-133323.6" + process $proc$libresoc.v:133314$5426 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:133315.5-133315.29" + switch \initial + attribute \src "libresoc.v:133315.9-133315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:133324.3-133332.6" + process $proc$libresoc.v:133324$5427 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5428 $1\ren_delay$10$next[0:0]$5429 + attribute \src "libresoc.v:133325.5-133325.29" + switch \initial + attribute \src "libresoc.v:133325.9-133325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5429 1'0 + case + assign $1\ren_delay$10$next[0:0]$5429 \src2__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5428 + end + attribute \src "libresoc.v:133333.3-133342.6" + process $proc$libresoc.v:133333$5430 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:133334.5-133334.29" + switch \initial + attribute \src "libresoc.v:133334.9-133334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$4 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:133343.3-133351.6" + process $proc$libresoc.v:133343$5431 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[0:0]$5432 $1\ren_delay$11$next[0:0]$5433 + attribute \src "libresoc.v:133344.5-133344.29" + switch \initial + attribute \src "libresoc.v:133344.9-133344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[0:0]$5433 1'0 + case + assign $1\ren_delay$11$next[0:0]$5433 \issue__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5432 + end + attribute \src "libresoc.v:133352.3-133361.6" + process $proc$libresoc.v:133352$5434 + assign { } { } + assign { } { } + assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] + attribute \src "libresoc.v:133353.5-133353.29" + switch \initial + attribute \src "libresoc.v:133353.9-133353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\issue__data_o[63:0] \memory_r_data$6 + case + assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \issue__data_o $0\issue__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:133302$5420_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:133303$5421_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:133304$5422_DATA + connect \memory_w_data$9 \issue__data_i + connect \memory_w_en$7 \issue__wen + connect \memory_w_addr$8 \issue__addr$1 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$5 \issue__addr + connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:133375.1-135325.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus" +attribute \generator "nMigen" +module \fus + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 330 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 257 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 258 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 259 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 260 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 261 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 262 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 3 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 4 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 25 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 75 \cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 82 \cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 103 \cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 31 \cu_busy_o$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 118 \cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 138 \cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 157 \cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 42 \cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 54 \cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 24 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 30 \cu_issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 74 \cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 81 \cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 102 \cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 117 \cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 137 \cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 156 \cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 41 \cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 53 \cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 160 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 163 \cu_rd__go_i$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 166 \cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 169 \cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 172 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 178 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 181 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 184 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 209 \cu_rd__go_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 159 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 162 \cu_rd__rel_o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 165 \cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 168 \cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 171 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 177 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 180 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 183 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 208 \cu_rd__rel_o$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 26 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 76 \cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 83 \cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 104 \cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 119 \cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 139 \cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 158 \cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 32 \cu_rdmaskn_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 43 \cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 55 \cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 5 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 2 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 221 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 242 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 244 \cu_wr__go_i$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 293 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 224 \cu_wr__go_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 227 \cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 230 \cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 233 \cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 236 \cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 239 \cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 220 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 243 \cu_wr__rel_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 292 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 223 \cu_wr__rel_o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 226 \cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 229 \cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 232 \cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 235 \cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 238 \cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 241 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 250 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 251 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 252 \dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 256 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 266 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 267 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 268 \dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 301 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 310 \dest2_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 272 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 274 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 281 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 282 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 300 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 288 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 289 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 290 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 306 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 280 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 287 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 308 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 273 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 254 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 291 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 294 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 295 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 296 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 297 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 255 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 315 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 316 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 325 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 311 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 314 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 317 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 318 \ldst_port0_exc_$signal$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 319 \ldst_port0_exc_$signal$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 320 \ldst_port0_exc_$signal$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 321 \ldst_port0_exc_$signal$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 322 \ldst_port0_exc_$signal$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 323 \ldst_port0_exc_$signal$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 324 \ldst_port0_exc_$signal$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 312 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 313 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 326 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 327 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 328 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 329 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 307 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 303 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 304 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 253 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 219 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 222 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 225 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 228 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 231 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 234 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 237 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 240 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 33 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 35 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 37 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 34 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 28 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 29 \oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 27 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 100 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 85 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 86 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 87 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 94 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 101 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 84 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 92 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 95 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 98 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 99 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 90 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 91 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 97 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 89 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 88 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 96 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 93 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 72 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 57 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 58 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 59 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 66 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 73 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 56 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 64 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 67 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 70 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 71 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 62 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 63 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 69 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 61 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 60 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 68 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 65 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 106 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 107 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 108 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 116 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 105 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 114 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 115 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 111 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 112 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 110 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 109 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 113 \oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 121 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 123 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 132 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 136 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 134 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 135 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 126 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 127 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 131 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 133 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 125 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 124 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 128 \oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 78 \oper_i_alu_spr0__fn_unit + attribute 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attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute 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attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 141 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 192 \src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 193 \src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 216 \src2_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 218 \src2_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 194 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 195 \src3_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 196 \src3_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 197 \src3_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 199 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 200 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 206 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 210 \src3_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 214 \src3_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 215 \src3_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 198 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 201 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 202 \src4_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 217 \src4_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 204 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 205 \src5_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 211 \src5_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 203 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 212 \src6_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 269 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 270 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 271 \xer_ca_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 275 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 276 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 277 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 278 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 283 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 284 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 285 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 286 \xer_so_ok$131 + attribute \module_not_derived 1 + attribute \src "libresoc.v:134957.8-134999.4" + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok + connect \cu_busy_o \cu_busy_o + connect \cu_issue_i \cu_issue_i + connect \cu_rd__go_i \cu_rd__go_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_wr__go_i \cu_wr__go_i + connect \cu_wr__rel_o \cu_wr__rel_o + connect \dest1_o \dest1_o + connect \dest2_o \dest2_o$115 + connect \dest3_o \dest3_o$122 + connect \dest4_o \dest4_o + connect \dest5_o \dest5_o$132 + connect \o_ok \o_ok + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$65 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135000.11-135027.4" + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$5 + connect \cu_issue_i \cu_issue_i$4 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \dest3_o \dest3_o$147 + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 + connect \src3_i \src3_i$71 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135028.7-135053.4" + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$110 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_issue_i \cu_issue_i$1 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \dest1_o \dest1_o$103 + connect \dest2_o \dest2_o + connect \dest3_o \dest3_o + connect \full_cr_ok \full_cr_ok + connect \o_ok \o_ok$80 + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135054.8-135093.4" + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$112 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_issue_i \cu_issue_i$16 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \dest1_o \dest1_o$107 + connect \dest2_o \dest2_o$117 + connect \dest3_o \dest3_o$127 + connect \dest4_o \dest4_o$134 + connect \o_ok \o_ok$92 + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$62 + connect \xer_ov_ok \xer_ov_ok$125 + connect \xer_so_ok \xer_so_ok$130 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135094.9-135148.4" + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \cu_busy_o$26 + connect \cu_issue_i \cu_issue_i$25 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \cu_wr__go_i$102 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \ea \ea + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \o \o + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135149.12-135184.4" + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$111 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_issue_i \cu_issue_i$10 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \dest1_o \dest1_o$105 + connect \dest2_o \dest2_o$116 + connect \o_ok \o_ok$86 + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \src3_i \src3_i$61 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135185.8-135218.4" + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$113 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_issue_i \cu_issue_i$19 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \dest1_o \dest1_o$108 + connect \dest2_o \dest2_o$118 + connect \dest3_o \dest3_o$128 + connect \dest4_o \dest4_o$135 + connect \o_ok \o_ok$95 + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$63 + connect \xer_ov_ok \xer_ov_ok$126 + connect \xer_so_ok \xer_so_ok$131 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135219.13-135257.4" + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$114 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_issue_i \cu_issue_i$22 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \dest1_o \dest1_o$109 + connect \dest2_o \dest2_o$119 + connect \dest3_o \dest3_o$123 + connect \o_ok \o_ok$98 + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \src5_i \src5_i + connect \xer_ca_ok \xer_ca_ok$121 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135258.8-135290.4" + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$14 + connect \cu_issue_i \cu_issue_i$13 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \dest1_o \dest1_o$106 + connect \dest2_o \dest2_o$150 + connect \dest3_o \dest3_o$143 + connect \dest4_o \dest4_o$133 + connect \dest5_o \dest5_o + connect \dest6_o \dest6_o + connect \fast1_ok \fast1_ok$139 + connect \o_ok \o_ok$89 + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \spr1_ok \spr1_ok + connect \src1_i \src1_i$39 + connect \src2_i \src2_i$79 + connect \src3_i \src3_i$76 + connect \src4_i \src4_i + connect \src5_i \src5_i$66 + connect \src6_i \src6_i + connect \xer_ca_ok \xer_ca_ok$120 + connect \xer_ov_ok \xer_ov_ok$124 + connect \xer_so_ok \xer_so_ok$129 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135291.9-135324.4" + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$8 + connect \cu_issue_i \cu_issue_i$7 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \dest1_o \dest1_o$104 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \dest4_o \dest4_o$148 + connect \dest5_o \dest5_o$149 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \msr_ok \msr_ok + connect \nia_ok \nia_ok$146 + connect \o_ok \o_ok$83 + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 + end +end +attribute \src "libresoc.v:135329.1-135387.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" +attribute \generator "nMigen" +module \idx_l + attribute \src "libresoc.v:135330.7-135330.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135375.3-135383.6" + wire $0\q_int$next[0:0]$5462 + attribute \src "libresoc.v:135373.3-135374.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:135375.3-135383.6" + wire $1\q_int$next[0:0]$5463 + attribute \src "libresoc.v:135354.7-135354.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:135365.17-135365.96" + wire $and$libresoc.v:135365$5452_Y + attribute \src "libresoc.v:135370.17-135370.96" + wire $and$libresoc.v:135370$5457_Y + attribute \src "libresoc.v:135367.18-135367.95" + wire $not$libresoc.v:135367$5454_Y + attribute \src "libresoc.v:135369.17-135369.94" + wire $not$libresoc.v:135369$5456_Y + attribute \src "libresoc.v:135372.17-135372.94" + wire $not$libresoc.v:135372$5459_Y + attribute \src "libresoc.v:135366.18-135366.100" + wire $or$libresoc.v:135366$5453_Y + attribute \src "libresoc.v:135368.18-135368.101" + wire $or$libresoc.v:135368$5455_Y + attribute \src "libresoc.v:135371.17-135371.99" + wire $or$libresoc.v:135371$5458_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:135330.7-135330.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:135365$5452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:135365$5452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:135370$5457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:135370$5457_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:135367$5454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $not$libresoc.v:135367$5454_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:135369$5456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:135369$5456_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:135372$5459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:135372$5459_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:135366$5453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_idx_l + connect \Y $or$libresoc.v:135366$5453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:135368$5455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \B \q_int + connect \Y $or$libresoc.v:135368$5455_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:135371$5458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_idx_l + connect \Y $or$libresoc.v:135371$5458_Y + end + attribute \src "libresoc.v:135330.7-135330.20" + process $proc$libresoc.v:135330$5464 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135354.7-135354.19" + process $proc$libresoc.v:135354$5465 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:135373.3-135374.27" + process $proc$libresoc.v:135373$5460 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:135375.3-135383.6" + process $proc$libresoc.v:135375$5461 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$5462 $1\q_int$next[0:0]$5463 + attribute \src "libresoc.v:135376.5-135376.29" + switch \initial + attribute \src "libresoc.v:135376.9-135376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$5463 1'0 + case + assign $1\q_int$next[0:0]$5463 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$5462 + end + connect \$9 $and$libresoc.v:135365$5452_Y + connect \$11 $or$libresoc.v:135366$5453_Y + connect \$13 $not$libresoc.v:135367$5454_Y + connect \$15 $or$libresoc.v:135368$5455_Y + connect \$1 $not$libresoc.v:135369$5456_Y + connect \$3 $and$libresoc.v:135370$5457_Y + connect \$5 $or$libresoc.v:135371$5458_Y + connect \$7 $not$libresoc.v:135372$5459_Y + connect \qlq_idx_l \$15 + connect \qn_idx_l \$13 + connect \q_idx_l \$11 +end +attribute \src "libresoc.v:135391.1-135770.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.imem" +attribute \generator "nMigen" +module \imem + attribute \src "libresoc.v:135722.3-135731.6" + wire $0\a_busy_o[0:0] + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5534 + attribute \src "libresoc.v:135533.3-135534.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:135732.3-135749.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:135679.3-135701.6" + wire $0\f_fetch_err_o$next[0:0]$5529 + attribute \src "libresoc.v:135535.3-135536.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:135750.3-135767.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $0\ibus__adr$next[44:0]$5524 + attribute \src "libresoc.v:135537.3-135538.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:135547.3-135574.6" + wire $0\ibus__cyc$next[0:0]$5500 + attribute \src "libresoc.v:135545.3-135546.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $0\ibus__sel$next[7:0]$5512 + attribute \src "libresoc.v:135541.3-135542.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:135575.3-135602.6" + wire $0\ibus__stb$next[0:0]$5506 + attribute \src "libresoc.v:135543.3-135544.35" + wire $0\ibus__stb[0:0] + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $0\ibus_rdata$next[63:0]$5518 + attribute \src "libresoc.v:135539.3-135540.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "libresoc.v:135392.7-135392.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135722.3-135731.6" + wire $1\a_busy_o[0:0] + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5535 + attribute \src "libresoc.v:135456.14-135456.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "libresoc.v:135732.3-135749.6" + wire $1\f_busy_o[0:0] + attribute \src "libresoc.v:135679.3-135701.6" + wire $1\f_fetch_err_o$next[0:0]$5530 + attribute \src "libresoc.v:135463.7-135463.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "libresoc.v:135750.3-135767.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $1\ibus__adr$next[44:0]$5525 + attribute \src "libresoc.v:135477.14-135477.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "libresoc.v:135547.3-135574.6" + wire $1\ibus__cyc$next[0:0]$5501 + attribute \src "libresoc.v:135482.7-135482.23" + wire $1\ibus__cyc[0:0] + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $1\ibus__sel$next[7:0]$5513 + attribute \src "libresoc.v:135491.13-135491.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "libresoc.v:135575.3-135602.6" + wire $1\ibus__stb$next[0:0]$5507 + attribute \src "libresoc.v:135496.7-135496.23" + wire $1\ibus__stb[0:0] + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $1\ibus_rdata$next[63:0]$5519 + attribute \src "libresoc.v:135500.14-135500.47" + wire width 64 $1\ibus_rdata[63:0] + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5536 + attribute \src "libresoc.v:135732.3-135749.6" + wire $2\f_busy_o[0:0] + attribute \src "libresoc.v:135679.3-135701.6" + wire $2\f_fetch_err_o$next[0:0]$5531 + attribute \src "libresoc.v:135750.3-135767.6" + wire width 64 $2\f_instr_o[63:0] + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $2\ibus__adr$next[44:0]$5526 + attribute \src "libresoc.v:135547.3-135574.6" + wire $2\ibus__cyc$next[0:0]$5502 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $2\ibus__sel$next[7:0]$5514 + attribute \src "libresoc.v:135575.3-135602.6" + wire $2\ibus__stb$next[0:0]$5508 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $2\ibus_rdata$next[63:0]$5520 + attribute \src "libresoc.v:135702.3-135721.6" + wire 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$or$libresoc.v:135521$5480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:135524$5483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:135524$5483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:135531$5490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:135531$5490_Y + end + attribute \src "libresoc.v:135392.7-135392.20" + process $proc$libresoc.v:135392$5541 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135456.14-135456.44" + process $proc$libresoc.v:135456$5542 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:135463.7-135463.27" + process $proc$libresoc.v:135463$5543 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:135477.14-135477.42" + process $proc$libresoc.v:135477$5544 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:135482.7-135482.23" + process $proc$libresoc.v:135482$5545 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:135491.13-135491.30" + process $proc$libresoc.v:135491$5546 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:135496.7-135496.23" + process $proc$libresoc.v:135496$5547 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:135500.14-135500.47" + process $proc$libresoc.v:135500$5548 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:135533.3-135534.39" + process $proc$libresoc.v:135533$5492 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:135535.3-135536.43" + process $proc$libresoc.v:135535$5493 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:135537.3-135538.35" + process $proc$libresoc.v:135537$5494 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:135539.3-135540.37" + process $proc$libresoc.v:135539$5495 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:135541.3-135542.35" + process $proc$libresoc.v:135541$5496 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:135543.3-135544.35" + process $proc$libresoc.v:135543$5497 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:135545.3-135546.35" + process $proc$libresoc.v:135545$5498 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:135547.3-135574.6" + process $proc$libresoc.v:135547$5499 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$5500 $4\ibus__cyc$next[0:0]$5504 + attribute \src "libresoc.v:135548.5-135548.29" + switch \initial + attribute \src "libresoc.v:135548.9-135548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$5501 $2\ibus__cyc$next[0:0]$5502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$5502 $3\ibus__cyc$next[0:0]$5503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5503 1'0 + case + assign $3\ibus__cyc$next[0:0]$5503 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$5502 1'1 + case + assign $2\ibus__cyc$next[0:0]$5502 \ibus__cyc + end + case + assign $1\ibus__cyc$next[0:0]$5501 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__cyc$next[0:0]$5504 1'0 + case + assign $4\ibus__cyc$next[0:0]$5504 $1\ibus__cyc$next[0:0]$5501 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5500 + end + attribute \src "libresoc.v:135575.3-135602.6" + process $proc$libresoc.v:135575$5505 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$5506 $4\ibus__stb$next[0:0]$5510 + attribute \src "libresoc.v:135576.5-135576.29" + switch \initial + attribute \src "libresoc.v:135576.9-135576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__stb$next[0:0]$5507 $2\ibus__stb$next[0:0]$5508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5508 $3\ibus__stb$next[0:0]$5509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5509 1'0 + case + assign $3\ibus__stb$next[0:0]$5509 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__stb$next[0:0]$5508 1'1 + case + assign $2\ibus__stb$next[0:0]$5508 \ibus__stb + end + case + assign $1\ibus__stb$next[0:0]$5507 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__stb$next[0:0]$5510 1'0 + case + assign $4\ibus__stb$next[0:0]$5510 $1\ibus__stb$next[0:0]$5507 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$5506 + end + attribute \src "libresoc.v:135603.3-135630.6" + process $proc$libresoc.v:135603$5511 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$5512 $4\ibus__sel$next[7:0]$5516 + attribute \src "libresoc.v:135604.5-135604.29" + switch \initial + attribute \src "libresoc.v:135604.9-135604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__sel$next[7:0]$5513 $2\ibus__sel$next[7:0]$5514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__sel$next[7:0]$5514 $3\ibus__sel$next[7:0]$5515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5515 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5515 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$5514 8'11111111 + case + assign $2\ibus__sel$next[7:0]$5514 \ibus__sel + end + case + assign $1\ibus__sel$next[7:0]$5513 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__sel$next[7:0]$5516 8'00000000 + case + assign $4\ibus__sel$next[7:0]$5516 $1\ibus__sel$next[7:0]$5513 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$5512 + end + attribute \src "libresoc.v:135631.3-135655.6" + process $proc$libresoc.v:135631$5517 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$5518 $4\ibus_rdata$next[63:0]$5522 + attribute \src "libresoc.v:135632.5-135632.29" + switch \initial + attribute \src "libresoc.v:135632.9-135632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$5519 $2\ibus_rdata$next[63:0]$5520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$5520 $3\ibus_rdata$next[63:0]$5521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5521 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$5521 \ibus_rdata + end + case + assign $2\ibus_rdata$next[63:0]$5520 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$5519 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus_rdata$next[63:0]$5522 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\ibus_rdata$next[63:0]$5522 $1\ibus_rdata$next[63:0]$5519 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5518 + end + attribute \src "libresoc.v:135656.3-135678.6" + process $proc$libresoc.v:135656$5523 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$5524 $3\ibus__adr$next[44:0]$5527 + attribute \src "libresoc.v:135657.5-135657.29" + switch \initial + attribute \src "libresoc.v:135657.9-135657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__adr$next[44:0]$5525 $2\ibus__adr$next[44:0]$5526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$5526 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$5526 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$5526 \ibus__adr + end + case + assign $1\ibus__adr$next[44:0]$5525 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__adr$next[44:0]$5527 45'000000000000000000000000000000000000000000000 + case + assign $3\ibus__adr$next[44:0]$5527 $1\ibus__adr$next[44:0]$5525 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$5524 + end + attribute \src "libresoc.v:135679.3-135701.6" + process $proc$libresoc.v:135679$5528 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$5529 $3\f_fetch_err_o$next[0:0]$5532 + attribute \src "libresoc.v:135680.5-135680.29" + switch \initial + attribute \src "libresoc.v:135680.9-135680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5530 $2\f_fetch_err_o$next[0:0]$5531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5531 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5531 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5531 \f_fetch_err_o + end + case + assign $1\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_fetch_err_o$next[0:0]$5532 1'0 + case + assign $3\f_fetch_err_o$next[0:0]$5532 $1\f_fetch_err_o$next[0:0]$5530 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5529 + end + attribute \src "libresoc.v:135702.3-135721.6" + process $proc$libresoc.v:135702$5533 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$5534 $3\f_badaddr_o$next[44:0]$5537 + attribute \src "libresoc.v:135703.5-135703.29" + switch \initial + attribute \src "libresoc.v:135703.9-135703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$5535 $2\f_badaddr_o$next[44:0]$5536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5536 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$5536 \f_badaddr_o + end + case + assign $1\f_badaddr_o$next[44:0]$5535 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_badaddr_o$next[44:0]$5537 45'000000000000000000000000000000000000000000000 + case + assign $3\f_badaddr_o$next[44:0]$5537 $1\f_badaddr_o$next[44:0]$5535 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5534 + end + attribute \src "libresoc.v:135722.3-135731.6" + process $proc$libresoc.v:135722$5538 + assign { } { } + assign { } { } + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:135723.5-135723.29" + switch \initial + attribute \src "libresoc.v:135723.9-135723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_busy_o[0:0] \ibus__cyc + case + assign $1\a_busy_o[0:0] 1'0 + end + sync always + update \a_busy_o $0\a_busy_o[0:0] + end + attribute \src "libresoc.v:135732.3-135749.6" + process $proc$libresoc.v:135732$5539 + assign { } { } + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:135733.5-135733.29" + switch \initial + attribute \src "libresoc.v:135733.9-135733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end + case + assign $1\f_busy_o[0:0] 1'0 + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:135750.3-135767.6" + process $proc$libresoc.v:135750$5540 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:135751.5-135751.29" + switch \initial + attribute \src "libresoc.v:135751.9-135751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end + case + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:135507$5466_Y + connect \$11 $not$libresoc.v:135508$5467_Y + connect \$13 $and$libresoc.v:135509$5468_Y + connect \$15 $or$libresoc.v:135510$5469_Y + connect \$17 $not$libresoc.v:135511$5470_Y + connect \$1 $not$libresoc.v:135512$5471_Y + connect \$19 $or$libresoc.v:135513$5472_Y + connect \$21 $not$libresoc.v:135514$5473_Y + connect \$23 $and$libresoc.v:135515$5474_Y + connect \$25 $or$libresoc.v:135516$5475_Y + connect \$27 $not$libresoc.v:135517$5476_Y + connect \$29 $or$libresoc.v:135518$5477_Y + connect \$31 $not$libresoc.v:135519$5478_Y + connect \$33 $and$libresoc.v:135520$5479_Y + connect \$35 $or$libresoc.v:135521$5480_Y + connect \$37 $not$libresoc.v:135522$5481_Y + connect \$3 $and$libresoc.v:135523$5482_Y + connect \$39 $or$libresoc.v:135524$5483_Y + connect \$41 $not$libresoc.v:135525$5484_Y + connect \$43 $and$libresoc.v:135526$5485_Y + connect \$45 $and$libresoc.v:135527$5486_Y + connect \$47 $not$libresoc.v:135528$5487_Y + connect \$49 $and$libresoc.v:135529$5488_Y + connect \$51 $not$libresoc.v:135530$5489_Y + connect \$5 $or$libresoc.v:135531$5490_Y + connect \$7 $not$libresoc.v:135532$5491_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 +end +attribute \src "libresoc.v:135774.1-136101.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" +attribute \generator "nMigen" +module \input + attribute \src "libresoc.v:136064.3-136075.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:135775.7-135775.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:136076.3-136094.6" + wire width 2 $0\xer_ca$23[1:0]$5552 + attribute \src "libresoc.v:136064.3-136075.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:136076.3-136094.6" + wire width 2 $1\xer_ca$23[1:0]$5553 + attribute \src "libresoc.v:136063.18-136063.100" + wire width 64 $not$libresoc.v:136063$5549_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:135775.7-135775.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:136063$5549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:136063$5549_Y + end + attribute \src "libresoc.v:135775.7-135775.20" + process $proc$libresoc.v:135775$5554 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:136064.3-136075.6" + process $proc$libresoc.v:136064$5550 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:136065.5-136065.29" + switch \initial + attribute \src "libresoc.v:136065.9-136065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \alu_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:136076.3-136094.6" + process $proc$libresoc.v:136076$5551 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5552 $1\xer_ca$23[1:0]$5553 + attribute \src "libresoc.v:136077.5-136077.29" + switch \initial + attribute \src "libresoc.v:136077.9-136077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5553 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5553 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5553 \xer_ca + case + assign $1\xer_ca$23[1:0]$5553 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5552 + end + connect \$24 $not$libresoc.v:136063$5549_Y + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:136105.1-136433.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \generator "nMigen" +module \input$113 + attribute \src "libresoc.v:136395.3-136406.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:136106.7-136106.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:136407.3-136425.6" + wire width 2 $0\xer_ca$23[1:0]$5558 + attribute \src "libresoc.v:136395.3-136406.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:136407.3-136425.6" + wire width 2 $1\xer_ca$23[1:0]$5559 + attribute \src "libresoc.v:136394.18-136394.100" + wire width 64 $not$libresoc.v:136394$5555_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:136106.7-136106.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rc$21 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:136394$5555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:136394$5555_Y + end + attribute \src "libresoc.v:136106.7-136106.20" + process $proc$libresoc.v:136106$5560 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:136395.3-136406.6" + process $proc$libresoc.v:136395$5556 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:136396.5-136396.29" + switch \initial + attribute \src "libresoc.v:136396.9-136396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \sr_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:136407.3-136425.6" + process $proc$libresoc.v:136407$5557 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5558 $1\xer_ca$23[1:0]$5559 + attribute \src "libresoc.v:136408.5-136408.29" + switch \initial + attribute \src "libresoc.v:136408.9-136408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5559 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5559 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5559 \xer_ca + case + assign $1\xer_ca$23[1:0]$5559 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5558 + end + connect \$24 $not$libresoc.v:136394$5555_Y + connect \rc$21 \rc + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$20 \b + connect \b \rb + connect \ra$19 \a +end +attribute \src "libresoc.v:136437.1-136740.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" +attribute \generator "nMigen" +module \input$50 + attribute \src "libresoc.v:136722.3-136733.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:136438.7-136438.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:136722.3-136733.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:136721.18-136721.100" + wire width 64 $not$libresoc.v:136721$5561_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:136438.7-136438.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $not$libresoc.v:136721$5561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $not$libresoc.v:136721$5561_Y + end + attribute \src "libresoc.v:136438.7-136438.20" + process $proc$libresoc.v:136438$5563 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:136722.3-136733.6" + process $proc$libresoc.v:136722$5562 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:136723.5-136723.29" + switch \initial + attribute \src "libresoc.v:136723.9-136723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$23 $not$libresoc.v:136721$5561_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \b + connect \ra$20 \a + connect \a \ra +end +attribute \src "libresoc.v:136744.1-137047.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" +attribute \generator "nMigen" +module \input$78 + attribute \src "libresoc.v:137029.3-137040.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:136745.7-136745.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:137029.3-137040.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:137028.18-137028.100" + wire width 64 $not$libresoc.v:137028$5564_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:136745.7-136745.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:137028$5564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:137028$5564_Y + end + attribute \src "libresoc.v:136745.7-136745.20" + process $proc$libresoc.v:136745$5566 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137029.3-137040.6" + process $proc$libresoc.v:137029$5565 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:137030.5-137030.29" + switch \initial + attribute \src "libresoc.v:137030.9-137030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + connect \$23 $not$libresoc.v:137028$5564_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:137051.1-137307.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \generator "nMigen" +module \input$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 \rb + connect \b \rb + connect \ra$14 \a + connect \a \ra +end +attribute \src "libresoc.v:137311.1-137571.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.int" +attribute \generator "nMigen" +module \int + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_0_[4:0] + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_1_[4:0] + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_2_[4:0] + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_3_[4:0] + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_4_[4:0] + attribute \src "libresoc.v:137503.3-137512.6" + wire width 64 $0\dmi__data_o[63:0] + attribute \src "libresoc.v:137312.7-137312.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:137484.3-137493.6" + wire width 64 $0\pred__data_o[63:0] + attribute \src "libresoc.v:137523.3-137531.6" + wire $0\ren_delay$10$next[0:0]$5631 + attribute \src "libresoc.v:137409.3-137410.43" + wire $0\ren_delay$10[0:0]$5607 + attribute \src "libresoc.v:137365.7-137365.28" + wire $0\ren_delay$10[0:0]$5674 + attribute \src "libresoc.v:137542.3-137550.6" + wire $0\ren_delay$11$next[0:0]$5635 + attribute \src "libresoc.v:137407.3-137408.43" + wire $0\ren_delay$11[0:0]$5605 + attribute \src "libresoc.v:137369.7-137369.28" + wire $0\ren_delay$11[0:0]$5676 + attribute \src "libresoc.v:137475.3-137483.6" + wire $0\ren_delay$12$next[0:0]$5622 + attribute \src "libresoc.v:137405.3-137406.43" + wire $0\ren_delay$12[0:0]$5603 + attribute \src "libresoc.v:137373.7-137373.28" + wire $0\ren_delay$12[0:0]$5678 + attribute \src "libresoc.v:137494.3-137502.6" + wire $0\ren_delay$13$next[0:0]$5626 + attribute \src "libresoc.v:137403.3-137404.43" + wire $0\ren_delay$13[0:0]$5601 + attribute \src "libresoc.v:137377.7-137377.28" + wire $0\ren_delay$13[0:0]$5680 + attribute \src "libresoc.v:137466.3-137474.6" + wire $0\ren_delay$next[0:0]$5619 + attribute \src "libresoc.v:137411.3-137412.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:137513.3-137522.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:137532.3-137541.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:137551.3-137560.6" + wire width 64 $0\src3__data_o[63:0] + attribute \src "libresoc.v:137503.3-137512.6" + wire width 64 $1\dmi__data_o[63:0] + attribute \src "libresoc.v:137484.3-137493.6" + wire width 64 $1\pred__data_o[63:0] + attribute \src "libresoc.v:137523.3-137531.6" + wire $1\ren_delay$10$next[0:0]$5632 + attribute \src "libresoc.v:137542.3-137550.6" + wire $1\ren_delay$11$next[0:0]$5636 + attribute \src "libresoc.v:137475.3-137483.6" + wire $1\ren_delay$12$next[0:0]$5623 + attribute \src "libresoc.v:137494.3-137502.6" + wire $1\ren_delay$13$next[0:0]$5627 + attribute \src "libresoc.v:137466.3-137474.6" + wire $1\ren_delay$next[0:0]$5620 + attribute \src "libresoc.v:137363.7-137363.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:137513.3-137522.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:137532.3-137541.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:137551.3-137560.6" + wire width 64 $1\src3__data_o[63:0] + attribute \src "libresoc.v:137461.26-137461.32" + wire width 64 $memrd$\memory$libresoc.v:137461$5613_DATA + attribute \src "libresoc.v:137462.30-137462.36" + wire width 64 $memrd$\memory$libresoc.v:137462$5614_DATA + attribute \src "libresoc.v:137463.30-137463.36" + wire width 64 $memrd$\memory$libresoc.v:137463$5615_DATA + attribute \src "libresoc.v:137464.30-137464.36" + wire width 64 $memrd$\memory$libresoc.v:137464$5616_DATA + attribute \src "libresoc.v:137465.30-137465.36" + wire width 64 $memrd$\memory$libresoc.v:137465$5617_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 5 $memwr$\memory$libresoc.v:137459$5599_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:137459$5599_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:137459$5599_EN + attribute \src "libresoc.v:137448.13-137448.16" + wire width 5 \_0_ + attribute \src "libresoc.v:137449.13-137449.16" + wire width 5 \_1_ + attribute \src "libresoc.v:137450.13-137450.16" + wire width 5 \_2_ + attribute \src "libresoc.v:137451.13-137451.16" + wire width 5 \_3_ + attribute \src "libresoc.v:137452.13-137452.16" + wire width 5 \_4_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 16 \dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 2 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 4 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 3 \dmi__ren + attribute \src "libresoc.v:137312.7-137312.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 \pred__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \pred__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \pred__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 6 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 7 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 9 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 8 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 12 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 11 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \src3__ren + attribute \src "libresoc.v:137413.14-137413.20" + memory width 64 size 32 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5638 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5638 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5639 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5639 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5640 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5640 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5641 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5641 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5642 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5642 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5643 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5643 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5644 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5644 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5645 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5645 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5646 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5646 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5647 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5647 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5648 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5648 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5649 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5649 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5650 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5650 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5651 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5651 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5652 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5652 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5653 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5653 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5654 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5654 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5655 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5655 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5656 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5656 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5657 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5657 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5658 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5658 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5659 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5659 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5660 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5660 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5661 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5661 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5662 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5662 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5663 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5663 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5664 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5664 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5665 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5665 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5666 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5666 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5667 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5667 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5668 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5668 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5669 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5669 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:137461.26-137461.32" + cell $memrd $memrd$\memory$libresoc.v:137461$5613 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137461$5613_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:137462.30-137462.36" + cell $memrd $memrd$\memory$libresoc.v:137462$5614 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137462$5614_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:137463.30-137463.36" + cell $memrd $memrd$\memory$libresoc.v:137463$5615 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137463$5615_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:137464.30-137464.36" + cell $memrd $memrd$\memory$libresoc.v:137464$5616 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_3_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137464$5616_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:137465.30-137465.36" + cell $memrd $memrd$\memory$libresoc.v:137465$5617 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_4_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137465$5617_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5670 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5670 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:137459$5599_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:137459$5599_DATA + connect \EN $memwr$\memory$libresoc.v:137459$5599_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5681 + sync always + sync init + end + attribute \src "libresoc.v:137312.7-137312.20" + process $proc$libresoc.v:137312$5671 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137363.7-137363.23" + process $proc$libresoc.v:137363$5672 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:137365.7-137365.28" + process $proc$libresoc.v:137365$5673 + assign { } { } + assign $0\ren_delay$10[0:0]$5674 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5674 + end + attribute \src "libresoc.v:137369.7-137369.28" + process $proc$libresoc.v:137369$5675 + assign { } { } + assign $0\ren_delay$11[0:0]$5676 1'0 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$5676 + end + attribute \src "libresoc.v:137373.7-137373.28" + process $proc$libresoc.v:137373$5677 + assign { } { } + assign $0\ren_delay$12[0:0]$5678 1'0 + sync always + sync init + update \ren_delay$12 $0\ren_delay$12[0:0]$5678 + end + attribute \src "libresoc.v:137377.7-137377.28" + process $proc$libresoc.v:137377$5679 + assign { } { } + assign $0\ren_delay$13[0:0]$5680 1'0 + sync always + sync init + update \ren_delay$13 $0\ren_delay$13[0:0]$5680 + end + attribute \src "libresoc.v:137403.3-137404.43" + process $proc$libresoc.v:137403$5600 + assign { } { } + assign $0\ren_delay$13[0:0]$5601 \ren_delay$13$next + sync posedge \coresync_clk + update \ren_delay$13 $0\ren_delay$13[0:0]$5601 + end + attribute \src "libresoc.v:137405.3-137406.43" + process $proc$libresoc.v:137405$5602 + assign { } { } + assign $0\ren_delay$12[0:0]$5603 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[0:0]$5603 + end + attribute \src "libresoc.v:137407.3-137408.43" + process $proc$libresoc.v:137407$5604 + assign { } { } + assign $0\ren_delay$11[0:0]$5605 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5605 + end + attribute \src "libresoc.v:137409.3-137410.43" + process $proc$libresoc.v:137409$5606 + assign { } { } + assign $0\ren_delay$10[0:0]$5607 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5607 + end + attribute \src "libresoc.v:137411.3-137412.35" + process $proc$libresoc.v:137411$5608 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:137453.3-137460.6" + process $proc$libresoc.v:137453$5609 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 5'xxxxx + assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[4:0] \src1__addr + assign $0\_1_[4:0] \src2__addr + assign $0\_2_[4:0] \src3__addr + assign $0\_3_[4:0] 5'00000 + assign $0\_4_[4:0] \dmi__addr + attribute \src "libresoc.v:137459.5-137459.58" + switch \dest1__wen + attribute \src "libresoc.v:137459.9-137459.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 \dest1__addr + assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update \_2_ $0\_2_[4:0] + update \_3_ $0\_3_[4:0] + update \_4_ $0\_4_[4:0] + update $memwr$\memory$libresoc.v:137459$5599_ADDR $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 + update $memwr$\memory$libresoc.v:137459$5599_DATA $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 + update $memwr$\memory$libresoc.v:137459$5599_EN $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 + end + attribute \src "libresoc.v:137466.3-137474.6" + process $proc$libresoc.v:137466$5618 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5619 $1\ren_delay$next[0:0]$5620 + attribute \src "libresoc.v:137467.5-137467.29" + switch \initial + attribute \src "libresoc.v:137467.9-137467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5620 1'0 + case + assign $1\ren_delay$next[0:0]$5620 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5619 + end + attribute \src "libresoc.v:137475.3-137483.6" + process $proc$libresoc.v:137475$5621 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[0:0]$5622 $1\ren_delay$12$next[0:0]$5623 + attribute \src "libresoc.v:137476.5-137476.29" + switch \initial + attribute \src "libresoc.v:137476.9-137476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[0:0]$5623 1'0 + case + assign $1\ren_delay$12$next[0:0]$5623 \pred__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5622 + end + attribute \src "libresoc.v:137484.3-137493.6" + process $proc$libresoc.v:137484$5624 + assign { } { } + assign { } { } + assign $0\pred__data_o[63:0] $1\pred__data_o[63:0] + attribute \src "libresoc.v:137485.5-137485.29" + switch \initial + attribute \src "libresoc.v:137485.9-137485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pred__data_o[63:0] \memory_r_data$7 + case + assign $1\pred__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \pred__data_o $0\pred__data_o[63:0] + end + attribute \src "libresoc.v:137494.3-137502.6" + process $proc$libresoc.v:137494$5625 + assign { } { } + assign { } { } + assign $0\ren_delay$13$next[0:0]$5626 $1\ren_delay$13$next[0:0]$5627 + attribute \src "libresoc.v:137495.5-137495.29" + switch \initial + attribute \src "libresoc.v:137495.9-137495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$13$next[0:0]$5627 1'0 + case + assign $1\ren_delay$13$next[0:0]$5627 \dmi__ren + end + sync always + update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5626 + end + attribute \src "libresoc.v:137503.3-137512.6" + process $proc$libresoc.v:137503$5628 + assign { } { } + assign { } { } + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "libresoc.v:137504.5-137504.29" + switch \initial + attribute \src "libresoc.v:137504.9-137504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__data_o[63:0] \memory_r_data$9 + case + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi__data_o $0\dmi__data_o[63:0] + end + attribute \src "libresoc.v:137513.3-137522.6" + process $proc$libresoc.v:137513$5629 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:137514.5-137514.29" + switch \initial + attribute \src "libresoc.v:137514.9-137514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:137523.3-137531.6" + process $proc$libresoc.v:137523$5630 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5631 $1\ren_delay$10$next[0:0]$5632 + attribute \src "libresoc.v:137524.5-137524.29" + switch \initial + attribute \src "libresoc.v:137524.9-137524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5632 1'0 + case + assign $1\ren_delay$10$next[0:0]$5632 \src2__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5631 + end + attribute \src "libresoc.v:137532.3-137541.6" + process $proc$libresoc.v:137532$5633 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:137533.5-137533.29" + switch \initial + attribute \src "libresoc.v:137533.9-137533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$3 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:137542.3-137550.6" + process $proc$libresoc.v:137542$5634 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[0:0]$5635 $1\ren_delay$11$next[0:0]$5636 + attribute \src "libresoc.v:137543.5-137543.29" + switch \initial + attribute \src "libresoc.v:137543.9-137543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[0:0]$5636 1'0 + case + assign $1\ren_delay$11$next[0:0]$5636 \src3__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5635 + end + attribute \src "libresoc.v:137551.3-137560.6" + process $proc$libresoc.v:137551$5637 + assign { } { } + assign { } { } + assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] + attribute \src "libresoc.v:137552.5-137552.29" + switch \initial + attribute \src "libresoc.v:137552.9-137552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[63:0] \memory_r_data$5 + case + assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src3__data_o $0\src3__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:137461$5613_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:137462$5614_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:137463$5615_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:137464$5616_DATA + connect \memory_r_data$9 $memrd$\memory$libresoc.v:137465$5617_DATA + connect \pred__addr 5'00000 + connect \pred__ren 1'0 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$8 \dmi__addr + connect \memory_r_addr$6 5'00000 + connect \memory_r_addr$4 \src3__addr + connect \memory_r_addr$2 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:137575.1-140282.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:139714.3-139740.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:139362.3-139377.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6091 + attribute \src "libresoc.v:139265.3-139266.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $0\dmi0__din$next[63:0]$6104 + attribute \src "libresoc.v:139261.3-139262.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:139564.3-139580.6" + wire $0\dmi0_addrsr__oe$next[0:0]$6028 + attribute \src "libresoc.v:139293.3-139294.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 + attribute \src "libresoc.v:139291.3-139292.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:139546.3-139554.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$6022 + attribute \src "libresoc.v:139297.3-139298.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:139555.3-139563.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + attribute \src "libresoc.v:139295.3-139296.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 + attribute \src "libresoc.v:139259.3-139260.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 + attribute \src "libresoc.v:139285.3-139286.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 + attribute \src "libresoc.v:139283.3-139284.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:139602.3-139610.6" + wire $0\dmi0_datasr_update_core$next[0:0]$6037 + attribute \src "libresoc.v:139289.3-139290.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:139611.3-139619.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + attribute \src "libresoc.v:139287.3-139288.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $0\fsm_state$499$next[2:0]$6097 + attribute \src "libresoc.v:139263.3-139264.45" + wire width 3 $0\fsm_state$499[2:0]$5943 + attribute \src "libresoc.v:138217.13-138217.35" + wire width 3 $0\fsm_state$499[2:0]$6146 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $0\fsm_state$next[2:0]$6074 + attribute \src "libresoc.v:139271.3-139272.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:137576.7-137576.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $0\io_bd$next[151:0]$6129 + attribute \src "libresoc.v:139323.3-139324.27" + wire width 152 $0\io_bd[151:0] + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $0\io_sr$next[151:0]$6125 + attribute \src "libresoc.v:139325.3-139326.27" + wire width 152 $0\io_sr[151:0] + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6068 + attribute \src "libresoc.v:139273.3-139274.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 + attribute \src "libresoc.v:139269.3-139270.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:139452.3-139468.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 + attribute \src "libresoc.v:139309.3-139310.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 + attribute \src "libresoc.v:139307.3-139308.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:139434.3-139442.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + attribute \src "libresoc.v:139313.3-139314.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:139443.3-139451.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + attribute \src "libresoc.v:139311.3-139312.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 + attribute \src "libresoc.v:139267.3-139268.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 + attribute \src "libresoc.v:139301.3-139302.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 + attribute \src "libresoc.v:139299.3-139300.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:139490.3-139498.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 + attribute \src "libresoc.v:139305.3-139306.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:139499.3-139507.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + attribute \src "libresoc.v:139303.3-139304.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:139396.3-139412.6" + wire $0\sr0__oe$next[0:0]$5983 + attribute \src "libresoc.v:139317.3-139318.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $0\sr0_reg$next[2:0]$5987 + attribute \src "libresoc.v:139315.3-139316.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:139378.3-139386.6" + wire $0\sr0_update_core$next[0:0]$5977 + attribute \src "libresoc.v:139321.3-139322.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:139387.3-139395.6" + wire $0\sr0_update_core_prev$next[0:0]$5980 + attribute \src "libresoc.v:139319.3-139320.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:140030.3-140039.6" + wire width 3 $0\sr5__i[2:0] + attribute \src "libresoc.v:139676.3-139692.6" + wire $0\sr5__oe$next[0:0]$6058 + attribute \src "libresoc.v:139277.3-139278.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $0\sr5_reg$next[2:0]$6062 + attribute \src "libresoc.v:139275.3-139276.31" + wire width 3 $0\sr5_reg[2:0] + attribute \src "libresoc.v:139658.3-139666.6" + wire $0\sr5_update_core$next[0:0]$6052 + attribute \src "libresoc.v:139281.3-139282.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:139667.3-139675.6" + wire $0\sr5_update_core_prev$next[0:0]$6055 + attribute \src "libresoc.v:139279.3-139280.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_dcache_en$next[0:0]$6114 + attribute \src "libresoc.v:139255.3-139256.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_icache_en$next[0:0]$6115 + attribute \src "libresoc.v:139253.3-139254.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_sram_en$next[0:0]$6116 + attribute \src "libresoc.v:139257.3-139258.37" + wire $0\wb_sram_en[0:0] + attribute \src "libresoc.v:139714.3-139740.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:139362.3-139377.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6092 + attribute \src "libresoc.v:138130.13-138130.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $1\dmi0__din$next[63:0]$6105 + attribute \src "libresoc.v:138135.14-138135.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:139564.3-139580.6" + wire $1\dmi0_addrsr__oe$next[0:0]$6029 + attribute \src "libresoc.v:138149.7-138149.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 + attribute \src "libresoc.v:138157.13-138157.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:139546.3-139554.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:138165.7-138165.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:139555.3-139563.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:138169.7-138169.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 + attribute \src "libresoc.v:138173.14-138173.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 + attribute \src "libresoc.v:138179.13-138179.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 + attribute \src "libresoc.v:138187.14-138187.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:139602.3-139610.6" + wire $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:138195.7-138195.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:139611.3-139619.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:138199.7-138199.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $1\fsm_state$499$next[2:0]$6098 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $1\fsm_state$next[2:0]$6075 + attribute \src "libresoc.v:138215.13-138215.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $1\io_bd$next[151:0]$6130 + attribute \src "libresoc.v:138415.15-138415.66" + wire width 152 $1\io_bd[151:0] + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $1\io_sr$next[151:0]$6126 + attribute \src "libresoc.v:138427.15-138427.66" + wire width 152 $1\io_sr[151:0] + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6069 + attribute \src "libresoc.v:138436.14-138436.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 + attribute \src "libresoc.v:138445.14-138445.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:139452.3-139468.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 + attribute \src "libresoc.v:138459.7-138459.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + attribute \src "libresoc.v:138467.14-138467.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:139434.3-139442.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:138475.7-138475.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:139443.3-139451.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:138479.7-138479.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 + attribute \src "libresoc.v:138483.14-138483.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 + attribute \src "libresoc.v:138489.13-138489.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 + attribute \src "libresoc.v:138497.14-138497.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:139490.3-139498.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:138505.7-138505.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:139499.3-139507.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:138509.7-138509.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:139396.3-139412.6" + wire $1\sr0__oe$next[0:0]$5984 + attribute \src "libresoc.v:138931.7-138931.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $1\sr0_reg$next[2:0]$5988 + attribute \src "libresoc.v:138939.13-138939.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:139378.3-139386.6" + wire $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:138947.7-138947.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:139387.3-139395.6" + wire $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:138951.7-138951.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:140030.3-140039.6" + wire width 3 $1\sr5__i[2:0] + attribute \src "libresoc.v:139676.3-139692.6" + wire $1\sr5__oe$next[0:0]$6059 + attribute \src "libresoc.v:138961.7-138961.21" + wire $1\sr5__oe[0:0] + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $1\sr5_reg$next[2:0]$6063 + attribute \src "libresoc.v:138969.13-138969.27" + wire width 3 $1\sr5_reg[2:0] + attribute \src "libresoc.v:139658.3-139666.6" + wire $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:138977.7-138977.29" + wire $1\sr5_update_core[0:0] + attribute \src "libresoc.v:139667.3-139675.6" + wire $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:138981.7-138981.34" + wire $1\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_dcache_en$next[0:0]$6117 + attribute \src "libresoc.v:138986.7-138986.26" + wire $1\wb_dcache_en[0:0] + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_icache_en$next[0:0]$6118 + attribute \src "libresoc.v:138991.7-138991.26" + wire $1\wb_icache_en[0:0] + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_sram_en$next[0:0]$6119 + attribute \src "libresoc.v:138996.7-138996.24" + wire $1\wb_sram_en[0:0] + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6093 + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $2\dmi0__din$next[63:0]$6106 + attribute \src "libresoc.v:139564.3-139580.6" + wire $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $2\fsm_state$499$next[2:0]$6099 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $2\fsm_state$next[2:0]$6076 + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $2\io_bd$next[151:0]$6131 + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $2\io_sr$next[151:0]$6127 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6070 + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 + attribute \src "libresoc.v:139452.3-139468.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 + attribute \src "libresoc.v:139396.3-139412.6" + wire $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $2\sr0_reg$next[2:0]$5989 + attribute \src "libresoc.v:139676.3-139692.6" + wire $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $2\sr5_reg$next[2:0]$6064 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_dcache_en$next[0:0]$6120 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_icache_en$next[0:0]$6121 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_sram_en$next[0:0]$6122 + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6094 + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $3\fsm_state$499$next[2:0]$6100 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $3\fsm_state$next[2:0]$6077 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6071 + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $3\sr5_reg$next[2:0]$6065 + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $4\fsm_state$499$next[2:0]$6101 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $4\fsm_state$next[2:0]$6078 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $5\fsm_state$499$next[2:0]$6102 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139217.19-139217.112" + wire width 30 $add$libresoc.v:139217$5900_Y + attribute \src "libresoc.v:139218.19-139218.112" + wire width 30 $add$libresoc.v:139218$5901_Y + attribute \src "libresoc.v:139225.19-139225.112" + wire width 5 $add$libresoc.v:139225$5909_Y + attribute \src "libresoc.v:139226.19-139226.112" + wire width 5 $add$libresoc.v:139226$5910_Y + attribute \src "libresoc.v:139043.18-139043.112" + wire $and$libresoc.v:139043$5726_Y + attribute \src "libresoc.v:139110.18-139110.108" + wire $and$libresoc.v:139110$5793_Y + attribute \src "libresoc.v:139121.18-139121.110" + wire $and$libresoc.v:139121$5804_Y + attribute \src "libresoc.v:139147.19-139147.110" + wire $and$libresoc.v:139147$5830_Y + attribute \src "libresoc.v:139150.19-139150.114" + wire $and$libresoc.v:139150$5833_Y + attribute \src "libresoc.v:139152.19-139152.112" + wire $and$libresoc.v:139152$5835_Y + attribute \src "libresoc.v:139155.19-139155.113" + wire $and$libresoc.v:139155$5838_Y + attribute \src "libresoc.v:139157.19-139157.121" + wire $and$libresoc.v:139157$5840_Y + attribute \src "libresoc.v:139160.19-139160.114" + wire $and$libresoc.v:139160$5843_Y + attribute \src "libresoc.v:139162.19-139162.112" + wire $and$libresoc.v:139162$5845_Y + attribute \src "libresoc.v:139164.19-139164.113" + wire $and$libresoc.v:139164$5847_Y + attribute \src "libresoc.v:139168.19-139168.132" + wire $and$libresoc.v:139168$5851_Y + attribute \src "libresoc.v:139172.19-139172.114" + wire $and$libresoc.v:139172$5855_Y + attribute \src "libresoc.v:139174.19-139174.112" + wire $and$libresoc.v:139174$5857_Y + attribute \src "libresoc.v:139176.19-139176.113" + wire $and$libresoc.v:139176$5859_Y + attribute \src "libresoc.v:139179.19-139179.132" + wire $and$libresoc.v:139179$5862_Y + attribute \src "libresoc.v:139182.19-139182.114" + wire $and$libresoc.v:139182$5865_Y + attribute \src "libresoc.v:139184.19-139184.112" + wire $and$libresoc.v:139184$5867_Y + attribute \src "libresoc.v:139186.19-139186.113" + wire $and$libresoc.v:139186$5869_Y + attribute \src "libresoc.v:139188.18-139188.108" + wire $and$libresoc.v:139188$5871_Y + attribute \src "libresoc.v:139189.19-139189.129" + wire $and$libresoc.v:139189$5872_Y + attribute \src "libresoc.v:139193.19-139193.114" + wire $and$libresoc.v:139193$5876_Y + attribute \src "libresoc.v:139195.19-139195.112" + wire $and$libresoc.v:139195$5878_Y + attribute \src "libresoc.v:139197.19-139197.113" + wire $and$libresoc.v:139197$5880_Y + attribute \src "libresoc.v:139199.18-139199.111" + wire $and$libresoc.v:139199$5882_Y + attribute \src "libresoc.v:139200.19-139200.129" + wire $and$libresoc.v:139200$5883_Y + attribute \src "libresoc.v:139203.19-139203.114" + wire $and$libresoc.v:139203$5886_Y + attribute \src "libresoc.v:139205.19-139205.112" + wire $and$libresoc.v:139205$5888_Y + attribute \src "libresoc.v:139207.19-139207.113" + wire $and$libresoc.v:139207$5890_Y + attribute \src "libresoc.v:139209.19-139209.121" + wire $and$libresoc.v:139209$5892_Y + attribute \src "libresoc.v:139242.17-139242.106" + wire $and$libresoc.v:139242$5926_Y + attribute \src "libresoc.v:138999.17-138999.110" + wire $eq$libresoc.v:138999$5682_Y + attribute \src "libresoc.v:139010.18-139010.111" + wire $eq$libresoc.v:139010$5693_Y + attribute \src "libresoc.v:139021.18-139021.111" + wire $eq$libresoc.v:139021$5704_Y + attribute \src "libresoc.v:139054.17-139054.110" + wire $eq$libresoc.v:139054$5737_Y + attribute \src "libresoc.v:139055.18-139055.111" + wire $eq$libresoc.v:139055$5738_Y + attribute \src "libresoc.v:139066.18-139066.111" + wire $eq$libresoc.v:139066$5749_Y + attribute \src "libresoc.v:139088.18-139088.111" + wire $eq$libresoc.v:139088$5771_Y + attribute \src "libresoc.v:139132.18-139132.111" + wire $eq$libresoc.v:139132$5815_Y + attribute \src "libresoc.v:139141.19-139141.112" + wire $eq$libresoc.v:139141$5824_Y + attribute \src "libresoc.v:139142.19-139142.112" + wire $eq$libresoc.v:139142$5825_Y + attribute \src "libresoc.v:139143.18-139143.111" + wire $eq$libresoc.v:139143$5826_Y + attribute \src "libresoc.v:139145.19-139145.112" + wire $eq$libresoc.v:139145$5828_Y + attribute \src "libresoc.v:139148.19-139148.112" + wire $eq$libresoc.v:139148$5831_Y + attribute \src "libresoc.v:139158.19-139158.112" + wire $eq$libresoc.v:139158$5841_Y + attribute \src "libresoc.v:139165.17-139165.110" + wire $eq$libresoc.v:139165$5848_Y + attribute \src "libresoc.v:139166.18-139166.111" + wire $eq$libresoc.v:139166$5849_Y + attribute \src "libresoc.v:139169.19-139169.112" + wire $eq$libresoc.v:139169$5852_Y + attribute \src "libresoc.v:139170.19-139170.112" + wire $eq$libresoc.v:139170$5853_Y + attribute \src "libresoc.v:139180.19-139180.112" + wire $eq$libresoc.v:139180$5863_Y + attribute \src "libresoc.v:139190.19-139190.112" + wire $eq$libresoc.v:139190$5873_Y + attribute \src "libresoc.v:139191.19-139191.112" + wire $eq$libresoc.v:139191$5874_Y + attribute \src "libresoc.v:139201.19-139201.112" + wire $eq$libresoc.v:139201$5884_Y + attribute \src "libresoc.v:139210.18-139210.111" + wire $eq$libresoc.v:139210$5893_Y + attribute \src "libresoc.v:139211.19-139211.110" + wire $eq$libresoc.v:139211$5894_Y + attribute \src "libresoc.v:139213.19-139213.110" + wire $eq$libresoc.v:139213$5896_Y + attribute \src "libresoc.v:139214.19-139214.110" + wire $eq$libresoc.v:139214$5897_Y + attribute \src "libresoc.v:139216.19-139216.110" + wire $eq$libresoc.v:139216$5899_Y + attribute \src "libresoc.v:139220.18-139220.111" + wire $eq$libresoc.v:139220$5904_Y + attribute \src "libresoc.v:139221.19-139221.116" + wire $eq$libresoc.v:139221$5905_Y + attribute \src "libresoc.v:139222.19-139222.116" + wire $eq$libresoc.v:139222$5906_Y + attribute \src "libresoc.v:139224.19-139224.116" + wire $eq$libresoc.v:139224$5908_Y + attribute \src "libresoc.v:139219.19-139219.106" + wire width 8 $extend$libresoc.v:139219$5902_Y + attribute \src "libresoc.v:139149.19-139149.109" + wire $ne$libresoc.v:139149$5832_Y + attribute \src "libresoc.v:139151.19-139151.109" + wire $ne$libresoc.v:139151$5834_Y + attribute \src "libresoc.v:139153.19-139153.109" + wire $ne$libresoc.v:139153$5836_Y + attribute \src "libresoc.v:139159.19-139159.120" + wire $ne$libresoc.v:139159$5842_Y + attribute \src "libresoc.v:139161.19-139161.120" + wire $ne$libresoc.v:139161$5844_Y + attribute \src "libresoc.v:139163.19-139163.120" + wire $ne$libresoc.v:139163$5846_Y + attribute \src "libresoc.v:139171.19-139171.120" + wire $ne$libresoc.v:139171$5854_Y + attribute \src "libresoc.v:139173.19-139173.120" + wire $ne$libresoc.v:139173$5856_Y + attribute \src "libresoc.v:139175.19-139175.120" + wire $ne$libresoc.v:139175$5858_Y + attribute \src "libresoc.v:139181.19-139181.117" + wire $ne$libresoc.v:139181$5864_Y + attribute \src "libresoc.v:139183.19-139183.117" + wire $ne$libresoc.v:139183$5866_Y + attribute \src "libresoc.v:139185.19-139185.117" + wire $ne$libresoc.v:139185$5868_Y + attribute \src "libresoc.v:139192.19-139192.117" + wire $ne$libresoc.v:139192$5875_Y + attribute \src "libresoc.v:139194.19-139194.117" + wire $ne$libresoc.v:139194$5877_Y + attribute \src "libresoc.v:139196.19-139196.117" + wire $ne$libresoc.v:139196$5879_Y + attribute \src "libresoc.v:139202.19-139202.109" + wire $ne$libresoc.v:139202$5885_Y + attribute \src "libresoc.v:139204.19-139204.109" + wire $ne$libresoc.v:139204$5887_Y + attribute \src "libresoc.v:139206.19-139206.109" + wire $ne$libresoc.v:139206$5889_Y + attribute \src "libresoc.v:139156.19-139156.110" + wire $not$libresoc.v:139156$5839_Y + attribute \src "libresoc.v:139167.19-139167.121" + wire $not$libresoc.v:139167$5850_Y + attribute \src "libresoc.v:139178.19-139178.121" + wire $not$libresoc.v:139178$5861_Y + attribute \src "libresoc.v:139187.19-139187.118" + wire $not$libresoc.v:139187$5870_Y + attribute \src "libresoc.v:139198.19-139198.118" + wire $not$libresoc.v:139198$5881_Y + attribute \src "libresoc.v:139208.19-139208.110" + wire $not$libresoc.v:139208$5891_Y + attribute \src "libresoc.v:139212.19-139212.100" + wire $not$libresoc.v:139212$5895_Y + attribute \src "libresoc.v:139032.18-139032.104" + wire $or$libresoc.v:139032$5715_Y + attribute \src "libresoc.v:139077.18-139077.104" + wire $or$libresoc.v:139077$5760_Y + attribute \src "libresoc.v:139099.18-139099.104" + wire $or$libresoc.v:139099$5782_Y + attribute \src "libresoc.v:139144.19-139144.107" + wire $or$libresoc.v:139144$5827_Y + attribute \src "libresoc.v:139146.19-139146.107" + wire $or$libresoc.v:139146$5829_Y + attribute \src "libresoc.v:139154.18-139154.104" + wire $or$libresoc.v:139154$5837_Y + attribute \src "libresoc.v:139177.18-139177.104" + wire $or$libresoc.v:139177$5860_Y + attribute \src "libresoc.v:139215.19-139215.107" + wire $or$libresoc.v:139215$5898_Y + attribute \src "libresoc.v:139223.19-139223.107" + wire $or$libresoc.v:139223$5907_Y + attribute \src "libresoc.v:139231.17-139231.101" + wire $or$libresoc.v:139231$5915_Y + attribute \src "libresoc.v:139219.19-139219.106" + wire width 8 $pos$libresoc.v:139219$5903_Y + attribute \src "libresoc.v:139000.18-139000.133" + wire $ternary$libresoc.v:139000$5683_Y + attribute \src "libresoc.v:139001.19-139001.133" + wire $ternary$libresoc.v:139001$5684_Y + attribute \src "libresoc.v:139002.19-139002.134" + wire $ternary$libresoc.v:139002$5685_Y + attribute \src "libresoc.v:139003.19-139003.133" + wire $ternary$libresoc.v:139003$5686_Y + attribute \src "libresoc.v:139004.19-139004.132" + wire $ternary$libresoc.v:139004$5687_Y + attribute \src "libresoc.v:139005.19-139005.133" + wire $ternary$libresoc.v:139005$5688_Y + attribute \src "libresoc.v:139006.19-139006.133" + wire $ternary$libresoc.v:139006$5689_Y + attribute \src "libresoc.v:139007.19-139007.132" + wire $ternary$libresoc.v:139007$5690_Y + attribute \src "libresoc.v:139008.19-139008.133" + wire $ternary$libresoc.v:139008$5691_Y + attribute \src "libresoc.v:139009.19-139009.133" + wire $ternary$libresoc.v:139009$5692_Y + attribute \src "libresoc.v:139011.19-139011.132" + wire $ternary$libresoc.v:139011$5694_Y + attribute \src "libresoc.v:139012.19-139012.133" + wire $ternary$libresoc.v:139012$5695_Y + attribute \src "libresoc.v:139013.19-139013.133" + wire $ternary$libresoc.v:139013$5696_Y + attribute \src "libresoc.v:139014.19-139014.132" + wire $ternary$libresoc.v:139014$5697_Y + attribute \src "libresoc.v:139015.19-139015.133" + wire $ternary$libresoc.v:139015$5698_Y + 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wire \$449 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$451 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$453 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$457 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$463 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$480 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$483 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$485 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + wire \$489 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$492 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$494 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$497 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$500 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$502 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$504 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + wire \$506 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$508 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$509 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$511 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$512 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 325 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 163 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 316 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 326 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 327 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 164 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 165 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$499$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__pad__oe + attribute \src "libresoc.v:137576.7-137576.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 152 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 152 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 152 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 152 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 323 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 317 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 319 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 324 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 322 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 318 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 320 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 321 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire width 3 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire width 3 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire output 9 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire \wb_dcache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire output 10 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire output 8 \wb_sram_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \wb_sram_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:139217$5900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:139217$5900_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:139218$5901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:139218$5901_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:139225$5909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:139225$5909_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:139226$5910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:139226$5910_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:139043$5726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139043$5726_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:139110$5793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$27 + connect \Y $and$libresoc.v:139110$5793_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:139121$5804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139121$5804_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:139147$5830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$363 + connect \Y $and$libresoc.v:139147$5830_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:139150$5833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$369 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139150$5833_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:139152$5835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$373 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139152$5835_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139155$5838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$377 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139155$5838_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:139157$5840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$381 + connect \Y $and$libresoc.v:139157$5840_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:139160$5843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$387 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139160$5843_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:139162$5845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139162$5845_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139164$5847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$395 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139164$5847_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:139168$5851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$399 + connect \Y $and$libresoc.v:139168$5851_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:139172$5855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$407 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139172$5855_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:139174$5857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$411 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139174$5857_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139176$5859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139176$5859_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:139179$5862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$419 + connect \Y $and$libresoc.v:139179$5862_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:139182$5865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$425 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139182$5865_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:139184$5867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$429 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139184$5867_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139186$5869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$433 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139186$5869_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:139188$5871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:139188$5871_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:139189$5872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core_prev + connect \B \$437 + connect \Y $and$libresoc.v:139189$5872_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:139193$5876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$445 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139193$5876_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:139195$5878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$449 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139195$5878_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139197$5880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$453 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139197$5880_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:139199$5882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139199$5882_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:139200$5883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core_prev + connect \B \$457 + connect \Y $and$libresoc.v:139200$5883_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:139203$5886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$463 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:139203$5886_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:139205$5888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$467 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:139205$5888_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139207$5890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$471 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139207$5890_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:139209$5892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core_prev + connect \B \$475 + connect \Y $and$libresoc.v:139209$5892_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $and $and$libresoc.v:139242$5926 + parameter \A_SIGNED 0 + parameter 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$ne$libresoc.v:139204$5887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:139204$5887_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:139206$5889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:139206$5889_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:139156$5839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:139156$5839_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:139167$5850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:139167$5850_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:139178$5861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:139178$5861_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:139187$5870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:139187$5870_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:139198$5881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:139198$5881_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:139208$5891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core + connect \Y $not$libresoc.v:139208$5891_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:139212$5895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$480 + connect \Y $not$libresoc.v:139212$5895_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:139032$5715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:139032$5715_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:139077$5760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:139077$5760_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:139099$5782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:139099$5782_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:139144$5827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$355 + connect \B \$357 + connect \Y $or$libresoc.v:139144$5827_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:139146$5829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:139146$5829_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:139154$5837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:139154$5837_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:139177$5860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:139177$5860_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:139215$5898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$483 + connect \B \$485 + connect \Y $or$libresoc.v:139215$5898_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:139223$5907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$500 + connect \B \$502 + connect \Y $or$libresoc.v:139223$5907_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:139231$5915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:139231$5915_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $pos$libresoc.v:139219$5903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:139219$5902_Y + connect \Y $pos$libresoc.v:139219$5903_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139000$5683 + parameter \WIDTH 1 + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139000$5683_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139001$5684 + parameter \WIDTH 1 + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139001$5684_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139002$5685 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139002$5685_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139003$5686 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139003$5686_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139004$5687 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139004$5687_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139005$5688 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139005$5688_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139006$5689 + parameter \WIDTH 1 + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139006$5689_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139007$5690 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139007$5690_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139008$5691 + parameter \WIDTH 1 + connect \A \gpio_s1__core__oe + connect \B \io_bd [32] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139008$5691_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139009$5692 + parameter \WIDTH 1 + connect \A \gpio_s2__pad__i + connect \B \io_bd [33] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139009$5692_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139011$5694 + parameter \WIDTH 1 + connect \A \gpio_s2__core__o + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139011$5694_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139012$5695 + parameter \WIDTH 1 + connect \A \gpio_s2__core__oe + connect \B \io_bd [35] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139012$5695_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139013$5696 + parameter \WIDTH 1 + connect \A \gpio_s3__pad__i + connect \B \io_bd [36] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139013$5696_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139014$5697 + parameter \WIDTH 1 + connect \A \gpio_s3__core__o + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139014$5697_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139015$5698 + parameter \WIDTH 1 + connect \A \gpio_s3__core__oe + connect \B \io_bd [38] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139015$5698_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139016$5699 + parameter \WIDTH 1 + connect \A \gpio_s4__pad__i + connect \B \io_bd [39] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139016$5699_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139017$5700 + parameter \WIDTH 1 + connect \A \gpio_s4__core__o + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139017$5700_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139018$5701 + parameter \WIDTH 1 + connect \A \gpio_s4__core__oe + connect \B \io_bd [41] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139018$5701_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139019$5702 + parameter \WIDTH 1 + connect \A \gpio_s5__pad__i + connect \B \io_bd [42] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139019$5702_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139020$5703 + parameter \WIDTH 1 + connect \A \gpio_s5__core__o + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139020$5703_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139022$5705 + parameter \WIDTH 1 + connect \A \gpio_s5__core__oe + connect \B \io_bd [44] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139022$5705_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139023$5706 + parameter \WIDTH 1 + connect \A \gpio_s6__pad__i + connect \B \io_bd [45] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139023$5706_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139024$5707 + parameter \WIDTH 1 + connect \A \gpio_s6__core__o + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139024$5707_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139025$5708 + parameter \WIDTH 1 + connect \A \gpio_s6__core__oe + connect \B \io_bd [47] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139025$5708_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139026$5709 + parameter \WIDTH 1 + connect \A \gpio_s7__pad__i + connect \B \io_bd [48] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139026$5709_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139027$5710 + parameter \WIDTH 1 + connect \A \gpio_s7__core__o + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139027$5710_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139028$5711 + parameter \WIDTH 1 + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139028$5711_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139029$5712 + parameter \WIDTH 1 + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139029$5712_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139030$5713 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139030$5713_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139031$5714 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139031$5714_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139033$5716 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139033$5716_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139034$5717 + parameter \WIDTH 1 + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139034$5717_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139035$5718 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139035$5718_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139036$5719 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139036$5719_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139037$5720 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139037$5720_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139038$5721 + parameter \WIDTH 1 + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139038$5721_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139039$5722 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139039$5722_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139040$5723 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139040$5723_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139041$5724 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139041$5724_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139042$5725 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139042$5725_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139044$5727 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139044$5727_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139045$5728 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139045$5728_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139046$5729 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139046$5729_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139047$5730 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139047$5730_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139048$5731 + parameter \WIDTH 1 + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139048$5731_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139049$5732 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139049$5732_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139050$5733 + parameter \WIDTH 1 + connect \A \sd0_data0__core__o + connect \B \io_bd [70] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139050$5733_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139051$5734 + parameter \WIDTH 1 + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139051$5734_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139052$5735 + parameter \WIDTH 1 + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139052$5735_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139053$5736 + parameter \WIDTH 1 + connect \A \sd0_data1__core__o + connect \B \io_bd [73] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139053$5736_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139056$5739 + parameter \WIDTH 1 + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139056$5739_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139057$5740 + parameter \WIDTH 1 + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139057$5740_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139058$5741 + parameter \WIDTH 1 + connect \A \sd0_data2__core__o + connect \B \io_bd [76] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139058$5741_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139059$5742 + parameter \WIDTH 1 + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139059$5742_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139060$5743 + parameter \WIDTH 1 + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139060$5743_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139061$5744 + parameter \WIDTH 1 + connect \A \sd0_data3__core__o + connect \B \io_bd [79] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139061$5744_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139062$5745 + parameter \WIDTH 1 + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139062$5745_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139063$5746 + parameter \WIDTH 1 + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139063$5746_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139064$5747 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139064$5747_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139065$5748 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139065$5748_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139067$5750 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139067$5750_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139068$5751 + parameter \WIDTH 1 + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139068$5751_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139069$5752 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139069$5752_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139070$5753 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139070$5753_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139071$5754 + parameter \WIDTH 1 + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139071$5754_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139072$5755 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139072$5755_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139073$5756 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139073$5756_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139074$5757 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139074$5757_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139075$5758 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139075$5758_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139076$5759 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139076$5759_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139078$5761 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139078$5761_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139079$5762 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139079$5762_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139080$5763 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139080$5763_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139081$5764 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139081$5764_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139082$5765 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139082$5765_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139083$5766 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139083$5766_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139084$5767 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139084$5767_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139085$5768 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139085$5768_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139086$5769 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139086$5769_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139087$5770 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139087$5770_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139089$5772 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139089$5772_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139090$5773 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139090$5773_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139091$5774 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139091$5774_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139092$5775 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139092$5775_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139093$5776 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139093$5776_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139094$5777 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139094$5777_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139095$5778 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139095$5778_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139096$5779 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139096$5779_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139097$5780 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139097$5780_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139098$5781 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139098$5781_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139100$5783 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139100$5783_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139101$5784 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139101$5784_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139102$5785 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139102$5785_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139103$5786 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139103$5786_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139104$5787 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139104$5787_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139105$5788 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139105$5788_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139106$5789 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139106$5789_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139107$5790 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139107$5790_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139108$5791 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139108$5791_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139109$5792 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139109$5792_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139111$5794 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139111$5794_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139112$5795 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139112$5795_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139113$5796 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139113$5796_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139114$5797 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [127] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139114$5797_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139115$5798 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [128] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139115$5798_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139116$5799 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139116$5799_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139117$5800 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [130] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139117$5800_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139118$5801 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [131] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139118$5801_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139119$5802 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139119$5802_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139120$5803 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [133] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139120$5803_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139122$5805 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [134] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139122$5805_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139123$5806 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139123$5806_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139124$5807 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [136] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139124$5807_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139125$5808 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [137] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139125$5808_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139126$5809 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139126$5809_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139127$5810 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [139] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139127$5810_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139128$5811 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [140] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139128$5811_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139129$5812 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139129$5812_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139130$5813 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [142] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139130$5813_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139131$5814 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [143] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139131$5814_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139133$5816 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139133$5816_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139134$5817 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [145] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139134$5817_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139135$5818 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [146] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139135$5818_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139136$5819 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139136$5819_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139137$5820 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [148] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139137$5820_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139138$5821 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [149] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139138$5821_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139139$5822 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139139$5822_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139140$5823 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [151] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139140$5823_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139227$5911 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139227$5911_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139228$5912 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139228$5912_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:139229$5913 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139229$5913_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139230$5914 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139230$5914_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139232$5916 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139232$5916_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139233$5917 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139233$5917_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139234$5918 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139234$5918_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139235$5919 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139235$5919_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139236$5920 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139236$5920_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139237$5921 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139237$5921_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139238$5922 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139238$5922_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139239$5923 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139239$5923_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139240$5924 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139240$5924_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139241$5925 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139241$5925_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139243$5927 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139243$5927_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139244$5928 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139244$5928_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139245$5929 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139245$5929_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139246$5930 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139246$5930_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139247$5931 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139247$5931_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139248$5932 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139248$5932_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139249$5933 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139249$5933_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:139250$5934 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:139250$5934_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:139251$5935 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139251$5935_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:139252$5936 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:139252$5936_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:139327.8-139339.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:139340.12-139350.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \id_bypass \_idblock_id_bypass + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:139351.12-139361.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:137576.7-137576.20" + process $proc$libresoc.v:137576$6132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:138130.13-138130.32" + process $proc$libresoc.v:138130$6133 + assign { } { } + assign $1\dmi0__addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:138135.14-138135.46" + process $proc$libresoc.v:138135$6134 + assign { } { } + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0__din $1\dmi0__din[63:0] + end + attribute \src "libresoc.v:138149.7-138149.29" + process $proc$libresoc.v:138149$6135 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:138157.13-138157.36" + process $proc$libresoc.v:138157$6136 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:138165.7-138165.37" + process $proc$libresoc.v:138165$6137 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:138169.7-138169.42" + process $proc$libresoc.v:138169$6138 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:138173.14-138173.51" + process $proc$libresoc.v:138173$6139 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:138179.13-138179.35" + process $proc$libresoc.v:138179$6140 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:138187.14-138187.52" + process $proc$libresoc.v:138187$6141 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:138195.7-138195.37" + process $proc$libresoc.v:138195$6142 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:138199.7-138199.42" + process $proc$libresoc.v:138199$6143 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:138215.13-138215.29" + process $proc$libresoc.v:138215$6144 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] + end + attribute \src "libresoc.v:138217.13-138217.35" + process $proc$libresoc.v:138217$6145 + assign { } { } + assign $0\fsm_state$499[2:0]$6146 3'000 + sync always + sync init + update \fsm_state$499 $0\fsm_state$499[2:0]$6146 + end + attribute \src "libresoc.v:138415.15-138415.66" + process $proc$libresoc.v:138415$6147 + assign { } { } + assign $1\io_bd[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[151:0] + end + attribute \src "libresoc.v:138427.15-138427.66" + process $proc$libresoc.v:138427$6148 + assign { } { } + assign $1\io_sr[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[151:0] + end + attribute \src "libresoc.v:138436.14-138436.41" + process $proc$libresoc.v:138436$6149 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:138445.14-138445.51" + process $proc$libresoc.v:138445$6150 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:138459.7-138459.32" + process $proc$libresoc.v:138459$6151 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:138467.14-138467.47" + process $proc$libresoc.v:138467$6152 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:138475.7-138475.40" + process $proc$libresoc.v:138475$6153 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:138479.7-138479.45" + process $proc$libresoc.v:138479$6154 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:138483.14-138483.54" + process $proc$libresoc.v:138483$6155 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:138489.13-138489.38" + process $proc$libresoc.v:138489$6156 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:138497.14-138497.55" + process $proc$libresoc.v:138497$6157 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:138505.7-138505.40" + process $proc$libresoc.v:138505$6158 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:138509.7-138509.45" + process $proc$libresoc.v:138509$6159 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:138931.7-138931.21" + process $proc$libresoc.v:138931$6160 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:138939.13-138939.27" + process $proc$libresoc.v:138939$6161 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] + end + attribute \src "libresoc.v:138947.7-138947.29" + process $proc$libresoc.v:138947$6162 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:138951.7-138951.34" + process $proc$libresoc.v:138951$6163 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:138961.7-138961.21" + process $proc$libresoc.v:138961$6164 + assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] + end + attribute \src "libresoc.v:138969.13-138969.27" + process $proc$libresoc.v:138969$6165 + assign { } { } + assign $1\sr5_reg[2:0] 3'000 + sync always + sync init + update \sr5_reg $1\sr5_reg[2:0] + end + attribute \src "libresoc.v:138977.7-138977.29" + process $proc$libresoc.v:138977$6166 + assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] + end + attribute \src "libresoc.v:138981.7-138981.34" + process $proc$libresoc.v:138981$6167 + assign { } { } + assign $1\sr5_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:138986.7-138986.26" + process $proc$libresoc.v:138986$6168 + assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:138991.7-138991.26" + process $proc$libresoc.v:138991$6169 + assign { } { } + assign $1\wb_icache_en[0:0] 1'1 + sync always + sync init + update \wb_icache_en $1\wb_icache_en[0:0] + end + attribute \src "libresoc.v:138996.7-138996.24" + process $proc$libresoc.v:138996$6170 + assign { } { } + assign $1\wb_sram_en[0:0] 1'1 + sync always + sync init + update \wb_sram_en $1\wb_sram_en[0:0] + end + attribute \src "libresoc.v:139253.3-139254.41" + process $proc$libresoc.v:139253$5937 + assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] + end + attribute \src "libresoc.v:139255.3-139256.41" + process $proc$libresoc.v:139255$5938 + assign { } { } + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:139257.3-139258.37" + process $proc$libresoc.v:139257$5939 + assign { } { } + assign $0\wb_sram_en[0:0] \wb_sram_en$next + sync posedge \clk + update \wb_sram_en $0\wb_sram_en[0:0] + end + attribute \src "libresoc.v:139259.3-139260.45" + process $proc$libresoc.v:139259$5940 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:139261.3-139262.35" + process $proc$libresoc.v:139261$5941 + assign { } { } + assign $0\dmi0__din[63:0] \dmi0__din$next + sync posedge \clk + update \dmi0__din $0\dmi0__din[63:0] + end + attribute \src "libresoc.v:139263.3-139264.45" + process $proc$libresoc.v:139263$5942 + assign { } { } + assign $0\fsm_state$499[2:0]$5943 \fsm_state$499$next + sync posedge \clk + update \fsm_state$499 $0\fsm_state$499[2:0]$5943 + end + attribute \src "libresoc.v:139265.3-139266.41" + process $proc$libresoc.v:139265$5944 + assign { } { } + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next + sync posedge \clk + update \dmi0__addr_i $0\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:139267.3-139268.51" + process $proc$libresoc.v:139267$5945 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:139269.3-139270.45" + process $proc$libresoc.v:139269$5946 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:139271.3-139272.35" + process $proc$libresoc.v:139271$5947 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:139273.3-139274.41" + process $proc$libresoc.v:139273$5948 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:139275.3-139276.31" + process $proc$libresoc.v:139275$5949 + assign { } { } + assign $0\sr5_reg[2:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[2:0] + end + attribute \src "libresoc.v:139277.3-139278.31" + process $proc$libresoc.v:139277$5950 + assign { } { } + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] + end + attribute \src "libresoc.v:139279.3-139280.57" + process $proc$libresoc.v:139279$5951 + assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:139281.3-139282.47" + process $proc$libresoc.v:139281$5952 + assign { } { } + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] + end + attribute \src "libresoc.v:139283.3-139284.47" + process $proc$libresoc.v:139283$5953 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:139285.3-139286.47" + process $proc$libresoc.v:139285$5954 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:139287.3-139288.73" + process $proc$libresoc.v:139287$5955 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:139289.3-139290.63" + process $proc$libresoc.v:139289$5956 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:139291.3-139292.47" + process $proc$libresoc.v:139291$5957 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:139293.3-139294.47" + process $proc$libresoc.v:139293$5958 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:139295.3-139296.73" + process $proc$libresoc.v:139295$5959 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:139297.3-139298.63" + process $proc$libresoc.v:139297$5960 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:139299.3-139300.53" + process $proc$libresoc.v:139299$5961 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:139301.3-139302.53" + process $proc$libresoc.v:139301$5962 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:139303.3-139304.79" + process $proc$libresoc.v:139303$5963 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:139305.3-139306.69" + process $proc$libresoc.v:139305$5964 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:139307.3-139308.53" + process $proc$libresoc.v:139307$5965 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:139309.3-139310.53" + process $proc$libresoc.v:139309$5966 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:139311.3-139312.79" + process $proc$libresoc.v:139311$5967 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:139313.3-139314.69" + process $proc$libresoc.v:139313$5968 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:139315.3-139316.31" + process $proc$libresoc.v:139315$5969 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] + end + attribute \src "libresoc.v:139317.3-139318.31" + process $proc$libresoc.v:139317$5970 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:139319.3-139320.57" + process $proc$libresoc.v:139319$5971 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:139321.3-139322.47" + process $proc$libresoc.v:139321$5972 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] + end + attribute \src "libresoc.v:139323.3-139324.27" + process $proc$libresoc.v:139323$5973 + assign { } { } + assign $0\io_bd[151:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[151:0] + end + attribute \src "libresoc.v:139325.3-139326.27" + process $proc$libresoc.v:139325$5974 + assign { } { } + assign $0\io_sr[151:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[151:0] + end + attribute \src "libresoc.v:139362.3-139377.6" + process $proc$libresoc.v:139362$5975 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:139363.5-139363.29" + switch \initial + attribute \src "libresoc.v:139363.9-139363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$365 \_idblock_select_id \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [151] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] + end + attribute \src "libresoc.v:139378.3-139386.6" + process $proc$libresoc.v:139378$5976 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:139379.5-139379.29" + switch \initial + attribute \src "libresoc.v:139379.9-139379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$5978 1'0 + case + assign $1\sr0_update_core$next[0:0]$5978 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 + end + attribute \src "libresoc.v:139387.3-139395.6" + process $proc$libresoc.v:139387$5979 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:139388.5-139388.29" + switch \initial + attribute \src "libresoc.v:139388.9-139388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 + end + attribute \src "libresoc.v:139396.3-139412.6" + process $proc$libresoc.v:139396$5982 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:139397.5-139397.29" + switch \initial + attribute \src "libresoc.v:139397.9-139397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$383 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$5984 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$5984 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$5985 1'0 + case + assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 + end + attribute \src "libresoc.v:139413.3-139433.6" + process $proc$libresoc.v:139413$5986 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:139414.5-139414.29" + switch \initial + attribute \src "libresoc.v:139414.9-139414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$5988 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$5989 \sr0__i + case + assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$5990 3'000 + case + assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 + end + attribute \src "libresoc.v:139434.3-139442.6" + process $proc$libresoc.v:139434$5991 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:139435.5-139435.29" + switch \initial + attribute \src "libresoc.v:139435.9-139435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + end + attribute \src "libresoc.v:139443.3-139451.6" + process $proc$libresoc.v:139443$5994 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:139444.5-139444.29" + switch \initial + attribute \src "libresoc.v:139444.9-139444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + end + attribute \src "libresoc.v:139452.3-139468.6" + process $proc$libresoc.v:139452$5997 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:139453.5-139453.29" + switch \initial + attribute \src "libresoc.v:139453.9-139453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$401 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 + end + attribute \src "libresoc.v:139469.3-139489.6" + process $proc$libresoc.v:139469$6001 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:139470.5-139470.29" + switch \initial + attribute \src "libresoc.v:139470.9-139470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 + end + attribute \src "libresoc.v:139490.3-139498.6" + process $proc$libresoc.v:139490$6006 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:139491.5-139491.29" + switch \initial + attribute \src "libresoc.v:139491.9-139491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 + end + attribute \src "libresoc.v:139499.3-139507.6" + process $proc$libresoc.v:139499$6009 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:139500.5-139500.29" + switch \initial + attribute \src "libresoc.v:139500.9-139500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + end + attribute \src "libresoc.v:139508.3-139524.6" + process $proc$libresoc.v:139508$6012 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:139509.5-139509.29" + switch \initial + attribute \src "libresoc.v:139509.9-139509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$421 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 $1\jtag_wb_datasr__oe$next[1:0]$6014 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 + end + attribute \src "libresoc.v:139525.3-139545.6" + process $proc$libresoc.v:139525$6016 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:139526.5-139526.29" + switch \initial + attribute \src "libresoc.v:139526.9-139526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 $1\jtag_wb_datasr_reg$next[63:0]$6018 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 $2\jtag_wb_datasr_reg$next[63:0]$6019 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 + end + attribute \src "libresoc.v:139546.3-139554.6" + process $proc$libresoc.v:139546$6021 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:139547.5-139547.29" + switch \initial + attribute \src "libresoc.v:139547.9-139547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 + end + attribute \src "libresoc.v:139555.3-139563.6" + process $proc$libresoc.v:139555$6024 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:139556.5-139556.29" + switch \initial + attribute \src "libresoc.v:139556.9-139556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + end + attribute \src "libresoc.v:139564.3-139580.6" + process $proc$libresoc.v:139564$6027 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:139565.5-139565.29" + switch \initial + attribute \src "libresoc.v:139565.9-139565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$439 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 + end + attribute \src "libresoc.v:139581.3-139601.6" + process $proc$libresoc.v:139581$6031 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:139582.5-139582.29" + switch \initial + attribute \src "libresoc.v:139582.9-139582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 + end + attribute \src "libresoc.v:139602.3-139610.6" + process $proc$libresoc.v:139602$6036 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:139603.5-139603.29" + switch \initial + attribute \src "libresoc.v:139603.9-139603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 + end + attribute \src "libresoc.v:139611.3-139619.6" + process $proc$libresoc.v:139611$6039 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:139612.5-139612.29" + switch \initial + attribute \src "libresoc.v:139612.9-139612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + end + attribute \src "libresoc.v:139620.3-139636.6" + process $proc$libresoc.v:139620$6042 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:139621.5-139621.29" + switch \initial + attribute \src "libresoc.v:139621.9-139621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$459 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 + end + attribute \src "libresoc.v:139637.3-139657.6" + process $proc$libresoc.v:139637$6046 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:139638.5-139638.29" + switch \initial + attribute \src "libresoc.v:139638.9-139638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 + end + attribute \src "libresoc.v:139658.3-139666.6" + process $proc$libresoc.v:139658$6051 + assign { } { } + assign { } { } + assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:139659.5-139659.29" + switch \initial + attribute \src "libresoc.v:139659.9-139659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core$next[0:0]$6053 1'0 + case + assign $1\sr5_update_core$next[0:0]$6053 \sr5_update + end + sync always + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 + end + attribute \src "libresoc.v:139667.3-139675.6" + process $proc$libresoc.v:139667$6054 + assign { } { } + assign { } { } + assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:139668.5-139668.29" + switch \initial + attribute \src "libresoc.v:139668.9-139668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 + case + assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core + end + sync always + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 + end + attribute \src "libresoc.v:139676.3-139692.6" + process $proc$libresoc.v:139676$6057 + assign { } { } + assign { } { } + assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:139677.5-139677.29" + switch \initial + attribute \src "libresoc.v:139677.9-139677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$477 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__oe$next[0:0]$6059 \sr5_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr5__oe$next[0:0]$6059 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5__oe$next[0:0]$6060 1'0 + case + assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 + end + sync always + update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 + end + attribute \src "libresoc.v:139693.3-139713.6" + process $proc$libresoc.v:139693$6061 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr5_reg$next[2:0]$6062 $3\sr5_reg$next[2:0]$6065 + attribute \src "libresoc.v:139694.5-139694.29" + switch \initial + attribute \src "libresoc.v:139694.9-139694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_reg$next[2:0]$6063 { \TAP_bus__tdi \sr5_reg [2:1] } + case + assign $1\sr5_reg$next[2:0]$6063 \sr5_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5_reg$next[2:0]$6064 \sr5__i + case + assign $2\sr5_reg$next[2:0]$6064 $1\sr5_reg$next[2:0]$6063 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr5_reg$next[2:0]$6065 3'000 + case + assign $3\sr5_reg$next[2:0]$6065 $2\sr5_reg$next[2:0]$6064 + end + sync always + update \sr5_reg$next $0\sr5_reg$next[2:0]$6062 + end + attribute \src "libresoc.v:139714.3-139740.6" + process $proc$libresoc.v:139714$6066 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:139715.5-139715.29" + switch \initial + attribute \src "libresoc.v:139715.9-139715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:139741.3-139773.6" + process $proc$libresoc.v:139741$6067 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:139742.5-139742.29" + switch \initial + attribute \src "libresoc.v:139742.9-139742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$6070 \$491 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$6071 \$494 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 + end + attribute \src "libresoc.v:139774.3-139826.6" + process $proc$libresoc.v:139774$6073 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139775.5-139775.29" + switch \initial + attribute \src "libresoc.v:139775.9-139775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$6076 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$6076 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$6076 3'010 + case + assign $2\fsm_state$next[2:0]$6076 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$6077 3'000 + case + assign $3\fsm_state$next[2:0]$6077 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$6078 3'001 + case + assign $4\fsm_state$next[2:0]$6078 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$6075 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$6079 3'000 + case + assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$6074 + end + attribute \src "libresoc.v:139827.3-139853.6" + process $proc$libresoc.v:139827$6080 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:139828.5-139828.29" + switch \initial + attribute \src "libresoc.v:139828.9-139828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 + end + attribute \src "libresoc.v:139854.3-139874.6" + process $proc$libresoc.v:139854$6085 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:139855.5-139855.29" + switch \initial + attribute \src "libresoc.v:139855.9-139855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 + end + attribute \src "libresoc.v:139875.3-139907.6" + process $proc$libresoc.v:139875$6090 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:139876.5-139876.29" + switch \initial + attribute \src "libresoc.v:139876.9-139876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$499 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$6093 \$508 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$6094 \$511 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i + end + case + assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 + end + sync always + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 + end + attribute \src "libresoc.v:139908.3-139960.6" + process $proc$libresoc.v:139908$6096 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$499$next[2:0]$6097 $5\fsm_state$499$next[2:0]$6102 + attribute \src "libresoc.v:139909.5-139909.29" + switch \initial + attribute \src "libresoc.v:139909.9-139909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$499 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$499$next[2:0]$6098 $2\fsm_state$499$next[2:0]$6099 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$499$next[2:0]$6099 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$499$next[2:0]$6099 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$499$next[2:0]$6099 3'010 + case + assign $2\fsm_state$499$next[2:0]$6099 \fsm_state$499 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$499$next[2:0]$6098 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$499$next[2:0]$6098 $3\fsm_state$499$next[2:0]$6100 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$499$next[2:0]$6100 3'000 + case + assign $3\fsm_state$499$next[2:0]$6100 \fsm_state$499 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$499$next[2:0]$6098 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$499$next[2:0]$6098 $4\fsm_state$499$next[2:0]$6101 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$499$next[2:0]$6101 3'001 + case + assign $4\fsm_state$499$next[2:0]$6101 \fsm_state$499 + end + case + assign $1\fsm_state$499$next[2:0]$6098 \fsm_state$499 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$499$next[2:0]$6102 3'000 + case + assign $5\fsm_state$499$next[2:0]$6102 $1\fsm_state$499$next[2:0]$6098 + end + sync always + update \fsm_state$499$next $0\fsm_state$499$next[2:0]$6097 + end + attribute \src "libresoc.v:139961.3-139987.6" + process $proc$libresoc.v:139961$6103 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:139962.5-139962.29" + switch \initial + attribute \src "libresoc.v:139962.9-139962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$499 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + end + case + assign $1\dmi0__din$next[63:0]$6105 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 + end + sync always + update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 + end + attribute \src "libresoc.v:139988.3-140008.6" + process $proc$libresoc.v:139988$6108 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:139989.5-139989.29" + switch \initial + attribute \src "libresoc.v:139989.9-139989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$499 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 + end + attribute \src "libresoc.v:140009.3-140029.6" + process $proc$libresoc.v:140009$6113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6120 + assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6121 + assign $0\wb_sram_en$next[0:0]$6116 $2\wb_sram_en$next[0:0]$6122 + attribute \src "libresoc.v:140010.5-140010.29" + switch \initial + attribute \src "libresoc.v:140010.9-140010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:106" + switch \sr5__oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\wb_sram_en$next[0:0]$6119 $1\wb_dcache_en$next[0:0]$6117 $1\wb_icache_en$next[0:0]$6118 } \sr5__o + case + assign $1\wb_dcache_en$next[0:0]$6117 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6118 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6119 \wb_sram_en + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $2\wb_icache_en$next[0:0]$6121 1'1 + assign $2\wb_dcache_en$next[0:0]$6120 1'1 + assign $2\wb_sram_en$next[0:0]$6122 1'1 + case + assign $2\wb_dcache_en$next[0:0]$6120 $1\wb_dcache_en$next[0:0]$6117 + assign $2\wb_icache_en$next[0:0]$6121 $1\wb_icache_en$next[0:0]$6118 + assign $2\wb_sram_en$next[0:0]$6122 $1\wb_sram_en$next[0:0]$6119 + end + sync always + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6116 + end + attribute \src "libresoc.v:140030.3-140039.6" + process $proc$libresoc.v:140030$6123 + assign { } { } + assign { } { } + assign $0\sr5__i[2:0] $1\sr5__i[2:0] + attribute \src "libresoc.v:140031.5-140031.29" + switch \initial + attribute \src "libresoc.v:140031.9-140031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:109" + switch \sr5__ie + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__i[2:0] { \wb_sram_en \wb_dcache_en \wb_icache_en } + case + assign $1\sr5__i[2:0] 3'000 + end + sync always + update \sr5__i $0\sr5__i[2:0] + end + attribute \src "libresoc.v:140040.3-140057.6" + process $proc$libresoc.v:140040$6124 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[151:0]$6125 $2\io_sr$next[151:0]$6127 + attribute \src "libresoc.v:140041.5-140041.29" + switch \initial + attribute \src "libresoc.v:140041.9-140041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[151:0]$6126 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[151:0]$6126 { \io_sr [150:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[151:0]$6126 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[151:0]$6127 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[151:0]$6127 $1\io_sr$next[151:0]$6126 + end + sync always + update \io_sr$next $0\io_sr$next[151:0]$6125 + end + attribute \src "libresoc.v:140058.3-140078.6" + process $proc$libresoc.v:140058$6128 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[151:0]$6129 $2\io_bd$next[151:0]$6131 + attribute \src "libresoc.v:140059.5-140059.29" + switch \initial + attribute \src "libresoc.v:140059.9-140059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[151:0]$6130 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[151:0]$6130 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[151:0]$6130 \io_sr + case + assign $1\io_bd$next[151:0]$6130 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[151:0]$6131 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[151:0]$6131 $1\io_bd$next[151:0]$6130 + end + sync always + update \io_bd$next $0\io_bd$next[151:0]$6129 + end + connect \$9 $eq$libresoc.v:138999$5682_Y + connect \$99 $ternary$libresoc.v:139000$5683_Y + connect \$101 $ternary$libresoc.v:139001$5684_Y + connect \$103 $ternary$libresoc.v:139002$5685_Y + connect \$105 $ternary$libresoc.v:139003$5686_Y + connect \$107 $ternary$libresoc.v:139004$5687_Y + connect \$109 $ternary$libresoc.v:139005$5688_Y + connect \$111 $ternary$libresoc.v:139006$5689_Y + connect \$113 $ternary$libresoc.v:139007$5690_Y + connect \$115 $ternary$libresoc.v:139008$5691_Y + connect \$117 $ternary$libresoc.v:139009$5692_Y + connect \$11 $eq$libresoc.v:139010$5693_Y + connect \$119 $ternary$libresoc.v:139011$5694_Y + connect \$121 $ternary$libresoc.v:139012$5695_Y + connect \$123 $ternary$libresoc.v:139013$5696_Y + connect \$125 $ternary$libresoc.v:139014$5697_Y + connect \$127 $ternary$libresoc.v:139015$5698_Y + connect \$129 $ternary$libresoc.v:139016$5699_Y + connect \$131 $ternary$libresoc.v:139017$5700_Y + connect \$133 $ternary$libresoc.v:139018$5701_Y + connect \$135 $ternary$libresoc.v:139019$5702_Y + connect \$137 $ternary$libresoc.v:139020$5703_Y + connect \$13 $eq$libresoc.v:139021$5704_Y + connect \$139 $ternary$libresoc.v:139022$5705_Y + connect \$141 $ternary$libresoc.v:139023$5706_Y + connect \$143 $ternary$libresoc.v:139024$5707_Y + connect \$145 $ternary$libresoc.v:139025$5708_Y + connect \$147 $ternary$libresoc.v:139026$5709_Y + connect \$149 $ternary$libresoc.v:139027$5710_Y + connect \$151 $ternary$libresoc.v:139028$5711_Y + connect \$153 $ternary$libresoc.v:139029$5712_Y + connect \$155 $ternary$libresoc.v:139030$5713_Y + connect \$157 $ternary$libresoc.v:139031$5714_Y + connect \$15 $or$libresoc.v:139032$5715_Y + connect \$159 $ternary$libresoc.v:139033$5716_Y + connect \$161 $ternary$libresoc.v:139034$5717_Y + connect \$163 $ternary$libresoc.v:139035$5718_Y + connect \$165 $ternary$libresoc.v:139036$5719_Y + connect \$167 $ternary$libresoc.v:139037$5720_Y + connect \$169 $ternary$libresoc.v:139038$5721_Y + connect \$171 $ternary$libresoc.v:139039$5722_Y + connect \$173 $ternary$libresoc.v:139040$5723_Y + connect \$175 $ternary$libresoc.v:139041$5724_Y + connect \$177 $ternary$libresoc.v:139042$5725_Y + connect \$17 $and$libresoc.v:139043$5726_Y + connect \$179 $ternary$libresoc.v:139044$5727_Y + connect \$181 $ternary$libresoc.v:139045$5728_Y + connect \$183 $ternary$libresoc.v:139046$5729_Y + connect \$185 $ternary$libresoc.v:139047$5730_Y + connect \$187 $ternary$libresoc.v:139048$5731_Y + connect \$189 $ternary$libresoc.v:139049$5732_Y + connect \$191 $ternary$libresoc.v:139050$5733_Y + connect \$193 $ternary$libresoc.v:139051$5734_Y + connect \$195 $ternary$libresoc.v:139052$5735_Y + connect \$197 $ternary$libresoc.v:139053$5736_Y + connect \$1 $eq$libresoc.v:139054$5737_Y + connect \$19 $eq$libresoc.v:139055$5738_Y + connect \$199 $ternary$libresoc.v:139056$5739_Y + connect \$201 $ternary$libresoc.v:139057$5740_Y + connect \$203 $ternary$libresoc.v:139058$5741_Y + connect \$205 $ternary$libresoc.v:139059$5742_Y + connect \$207 $ternary$libresoc.v:139060$5743_Y + connect \$209 $ternary$libresoc.v:139061$5744_Y + connect \$211 $ternary$libresoc.v:139062$5745_Y + connect \$213 $ternary$libresoc.v:139063$5746_Y + connect \$215 $ternary$libresoc.v:139064$5747_Y + connect \$217 $ternary$libresoc.v:139065$5748_Y + connect \$21 $eq$libresoc.v:139066$5749_Y + connect \$219 $ternary$libresoc.v:139067$5750_Y + connect \$221 $ternary$libresoc.v:139068$5751_Y + connect \$223 $ternary$libresoc.v:139069$5752_Y + connect \$225 $ternary$libresoc.v:139070$5753_Y + connect \$227 $ternary$libresoc.v:139071$5754_Y + connect \$229 $ternary$libresoc.v:139072$5755_Y + connect \$231 $ternary$libresoc.v:139073$5756_Y + connect \$233 $ternary$libresoc.v:139074$5757_Y + connect \$235 $ternary$libresoc.v:139075$5758_Y + connect \$237 $ternary$libresoc.v:139076$5759_Y + connect \$23 $or$libresoc.v:139077$5760_Y + connect \$239 $ternary$libresoc.v:139078$5761_Y + connect \$241 $ternary$libresoc.v:139079$5762_Y + connect \$243 $ternary$libresoc.v:139080$5763_Y + connect \$245 $ternary$libresoc.v:139081$5764_Y + connect \$247 $ternary$libresoc.v:139082$5765_Y + connect \$249 $ternary$libresoc.v:139083$5766_Y + connect \$251 $ternary$libresoc.v:139084$5767_Y + connect \$253 $ternary$libresoc.v:139085$5768_Y + connect \$255 $ternary$libresoc.v:139086$5769_Y + connect \$257 $ternary$libresoc.v:139087$5770_Y + connect \$25 $eq$libresoc.v:139088$5771_Y + connect \$259 $ternary$libresoc.v:139089$5772_Y + connect \$261 $ternary$libresoc.v:139090$5773_Y + connect \$263 $ternary$libresoc.v:139091$5774_Y + connect \$265 $ternary$libresoc.v:139092$5775_Y + connect \$267 $ternary$libresoc.v:139093$5776_Y + connect \$269 $ternary$libresoc.v:139094$5777_Y + connect \$271 $ternary$libresoc.v:139095$5778_Y + connect \$273 $ternary$libresoc.v:139096$5779_Y + connect \$275 $ternary$libresoc.v:139097$5780_Y + connect \$277 $ternary$libresoc.v:139098$5781_Y + connect \$27 $or$libresoc.v:139099$5782_Y + connect \$279 $ternary$libresoc.v:139100$5783_Y + connect \$281 $ternary$libresoc.v:139101$5784_Y + connect \$283 $ternary$libresoc.v:139102$5785_Y + connect \$285 $ternary$libresoc.v:139103$5786_Y + connect \$287 $ternary$libresoc.v:139104$5787_Y + connect \$289 $ternary$libresoc.v:139105$5788_Y + connect \$291 $ternary$libresoc.v:139106$5789_Y + connect \$293 $ternary$libresoc.v:139107$5790_Y + connect \$295 $ternary$libresoc.v:139108$5791_Y + connect \$297 $ternary$libresoc.v:139109$5792_Y + connect \$29 $and$libresoc.v:139110$5793_Y + connect \$299 $ternary$libresoc.v:139111$5794_Y + connect \$301 $ternary$libresoc.v:139112$5795_Y + connect \$303 $ternary$libresoc.v:139113$5796_Y + connect \$305 $ternary$libresoc.v:139114$5797_Y + connect \$307 $ternary$libresoc.v:139115$5798_Y + connect \$309 $ternary$libresoc.v:139116$5799_Y + connect \$311 $ternary$libresoc.v:139117$5800_Y + connect \$313 $ternary$libresoc.v:139118$5801_Y + connect \$315 $ternary$libresoc.v:139119$5802_Y + connect \$317 $ternary$libresoc.v:139120$5803_Y + connect \$31 $and$libresoc.v:139121$5804_Y + connect \$319 $ternary$libresoc.v:139122$5805_Y + connect \$321 $ternary$libresoc.v:139123$5806_Y + connect \$323 $ternary$libresoc.v:139124$5807_Y + connect \$325 $ternary$libresoc.v:139125$5808_Y + connect \$327 $ternary$libresoc.v:139126$5809_Y + connect \$329 $ternary$libresoc.v:139127$5810_Y + connect \$331 $ternary$libresoc.v:139128$5811_Y + connect \$333 $ternary$libresoc.v:139129$5812_Y + connect \$335 $ternary$libresoc.v:139130$5813_Y + connect \$337 $ternary$libresoc.v:139131$5814_Y + connect \$33 $eq$libresoc.v:139132$5815_Y + connect \$339 $ternary$libresoc.v:139133$5816_Y + connect \$341 $ternary$libresoc.v:139134$5817_Y + connect \$343 $ternary$libresoc.v:139135$5818_Y + connect \$345 $ternary$libresoc.v:139136$5819_Y + connect \$347 $ternary$libresoc.v:139137$5820_Y + connect \$349 $ternary$libresoc.v:139138$5821_Y + connect \$351 $ternary$libresoc.v:139139$5822_Y + connect \$353 $ternary$libresoc.v:139140$5823_Y + connect \$355 $eq$libresoc.v:139141$5824_Y + connect \$357 $eq$libresoc.v:139142$5825_Y + connect \$35 $eq$libresoc.v:139143$5826_Y + connect \$359 $or$libresoc.v:139144$5827_Y + connect \$361 $eq$libresoc.v:139145$5828_Y + connect \$363 $or$libresoc.v:139146$5829_Y + connect \$365 $and$libresoc.v:139147$5830_Y + connect \$367 $eq$libresoc.v:139148$5831_Y + connect \$369 $ne$libresoc.v:139149$5832_Y + connect \$371 $and$libresoc.v:139150$5833_Y + connect \$373 $ne$libresoc.v:139151$5834_Y + connect \$375 $and$libresoc.v:139152$5835_Y + connect \$377 $ne$libresoc.v:139153$5836_Y + connect \$37 $or$libresoc.v:139154$5837_Y + connect \$379 $and$libresoc.v:139155$5838_Y + connect \$381 $not$libresoc.v:139156$5839_Y + connect \$383 $and$libresoc.v:139157$5840_Y + connect \$385 $eq$libresoc.v:139158$5841_Y + connect \$387 $ne$libresoc.v:139159$5842_Y + connect \$389 $and$libresoc.v:139160$5843_Y + connect \$391 $ne$libresoc.v:139161$5844_Y + connect \$393 $and$libresoc.v:139162$5845_Y + connect \$395 $ne$libresoc.v:139163$5846_Y + connect \$397 $and$libresoc.v:139164$5847_Y + connect \$3 $eq$libresoc.v:139165$5848_Y + connect \$39 $eq$libresoc.v:139166$5849_Y + connect \$399 $not$libresoc.v:139167$5850_Y + connect \$401 $and$libresoc.v:139168$5851_Y + connect \$403 $eq$libresoc.v:139169$5852_Y + connect \$405 $eq$libresoc.v:139170$5853_Y + connect \$407 $ne$libresoc.v:139171$5854_Y + connect \$409 $and$libresoc.v:139172$5855_Y + connect \$411 $ne$libresoc.v:139173$5856_Y + connect \$413 $and$libresoc.v:139174$5857_Y + connect \$415 $ne$libresoc.v:139175$5858_Y + connect \$417 $and$libresoc.v:139176$5859_Y + connect \$41 $or$libresoc.v:139177$5860_Y + connect \$419 $not$libresoc.v:139178$5861_Y + connect \$421 $and$libresoc.v:139179$5862_Y + connect \$423 $eq$libresoc.v:139180$5863_Y + connect \$425 $ne$libresoc.v:139181$5864_Y + connect \$427 $and$libresoc.v:139182$5865_Y + connect \$429 $ne$libresoc.v:139183$5866_Y + connect \$431 $and$libresoc.v:139184$5867_Y + connect \$433 $ne$libresoc.v:139185$5868_Y + connect \$435 $and$libresoc.v:139186$5869_Y + connect \$437 $not$libresoc.v:139187$5870_Y + connect \$43 $and$libresoc.v:139188$5871_Y + connect \$439 $and$libresoc.v:139189$5872_Y + connect \$441 $eq$libresoc.v:139190$5873_Y + connect \$443 $eq$libresoc.v:139191$5874_Y + connect \$445 $ne$libresoc.v:139192$5875_Y + connect \$447 $and$libresoc.v:139193$5876_Y + connect \$449 $ne$libresoc.v:139194$5877_Y + connect \$451 $and$libresoc.v:139195$5878_Y + connect \$453 $ne$libresoc.v:139196$5879_Y + connect \$455 $and$libresoc.v:139197$5880_Y + connect \$457 $not$libresoc.v:139198$5881_Y + connect \$45 $and$libresoc.v:139199$5882_Y + connect \$459 $and$libresoc.v:139200$5883_Y + connect \$461 $eq$libresoc.v:139201$5884_Y + connect \$463 $ne$libresoc.v:139202$5885_Y + connect \$465 $and$libresoc.v:139203$5886_Y + connect \$467 $ne$libresoc.v:139204$5887_Y + connect \$469 $and$libresoc.v:139205$5888_Y + connect \$471 $ne$libresoc.v:139206$5889_Y + connect \$473 $and$libresoc.v:139207$5890_Y + connect \$475 $not$libresoc.v:139208$5891_Y + connect \$477 $and$libresoc.v:139209$5892_Y + connect \$47 $eq$libresoc.v:139210$5893_Y + connect \$480 $eq$libresoc.v:139211$5894_Y + connect \$479 $not$libresoc.v:139212$5895_Y + connect \$483 $eq$libresoc.v:139213$5896_Y + connect \$485 $eq$libresoc.v:139214$5897_Y + connect \$487 $or$libresoc.v:139215$5898_Y + connect \$489 $eq$libresoc.v:139216$5899_Y + connect \$492 $add$libresoc.v:139217$5900_Y + connect \$495 $add$libresoc.v:139218$5901_Y + connect \$497 $pos$libresoc.v:139219$5903_Y + connect \$49 $eq$libresoc.v:139220$5904_Y + connect \$500 $eq$libresoc.v:139221$5905_Y + connect \$502 $eq$libresoc.v:139222$5906_Y + connect \$504 $or$libresoc.v:139223$5907_Y + connect \$506 $eq$libresoc.v:139224$5908_Y + connect \$509 $add$libresoc.v:139225$5909_Y + connect \$512 $add$libresoc.v:139226$5910_Y + connect \$51 $ternary$libresoc.v:139227$5911_Y + connect \$53 $ternary$libresoc.v:139228$5912_Y + connect \$55 $ternary$libresoc.v:139229$5913_Y + connect \$57 $ternary$libresoc.v:139230$5914_Y + connect \$5 $or$libresoc.v:139231$5915_Y + connect \$59 $ternary$libresoc.v:139232$5916_Y + connect \$61 $ternary$libresoc.v:139233$5917_Y + connect \$63 $ternary$libresoc.v:139234$5918_Y + connect \$65 $ternary$libresoc.v:139235$5919_Y + connect \$67 $ternary$libresoc.v:139236$5920_Y + connect \$69 $ternary$libresoc.v:139237$5921_Y + connect \$71 $ternary$libresoc.v:139238$5922_Y + connect \$73 $ternary$libresoc.v:139239$5923_Y + connect \$75 $ternary$libresoc.v:139240$5924_Y + connect \$77 $ternary$libresoc.v:139241$5925_Y + connect \$7 $and$libresoc.v:139242$5926_Y + connect \$79 $ternary$libresoc.v:139243$5927_Y + connect \$81 $ternary$libresoc.v:139244$5928_Y + connect \$83 $ternary$libresoc.v:139245$5929_Y + connect \$85 $ternary$libresoc.v:139246$5930_Y + connect \$87 $ternary$libresoc.v:139247$5931_Y + connect \$89 $ternary$libresoc.v:139248$5932_Y + connect \$91 $ternary$libresoc.v:139249$5933_Y + connect \$93 $ternary$libresoc.v:139250$5934_Y + connect \$95 $ternary$libresoc.v:139251$5935_Y + connect \$97 $ternary$libresoc.v:139252$5936_Y + connect \$491 \$492 + connect \$494 \$495 + connect \$508 \$509 + connect \$511 \$512 + connect \sr5__ie 1'0 + connect \sr0__i \sr0__o + connect \dmi0__we_i \$506 + connect \dmi0__req_i \$504 + connect \dmi0_addrsr__i \$497 + connect \jtag_wb__we \$489 + connect \jtag_wb__stb \$487 + connect \jtag_wb__cyc \$479 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \sr5_update \$473 + connect \sr5_shift \$469 + connect \sr5_capture \$465 + connect \sr5_isir \$461 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$455 + connect \dmi0_datasr_shift \$451 + connect \dmi0_datasr_capture \$447 + connect \dmi0_datasr_isir { \$443 \$441 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$435 + connect \dmi0_addrsr_shift \$431 + connect \dmi0_addrsr_capture \$427 + connect \dmi0_addrsr_isir \$423 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$417 + connect \jtag_wb_datasr_shift \$413 + connect \jtag_wb_datasr_capture \$409 + connect \jtag_wb_datasr_isir { \$405 \$403 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$397 + connect \jtag_wb_addrsr_shift \$393 + connect \jtag_wb_addrsr_capture \$389 + connect \jtag_wb_addrsr_isir \$385 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$379 + connect \sr0_shift \$375 + connect \sr0_capture \$371 + connect \sr0_isir \$367 + connect \sr0__o \sr0_reg + connect \sdr_dq_15__pad__oe \$353 + connect \sdr_dq_15__pad__o \$351 + connect \sdr_dq_15__core__i \$349 + connect \sdr_dq_14__pad__oe \$347 + connect \sdr_dq_14__pad__o \$345 + connect \sdr_dq_14__core__i \$343 + connect \sdr_dq_13__pad__oe \$341 + connect \sdr_dq_13__pad__o \$339 + connect \sdr_dq_13__core__i \$337 + connect \sdr_dq_12__pad__oe \$335 + connect \sdr_dq_12__pad__o \$333 + connect \sdr_dq_12__core__i \$331 + connect \sdr_dq_11__pad__oe \$329 + connect \sdr_dq_11__pad__o \$327 + connect \sdr_dq_11__core__i \$325 + connect \sdr_dq_10__pad__oe \$323 + connect \sdr_dq_10__pad__o \$321 + connect \sdr_dq_10__core__i \$319 + connect \sdr_dq_9__pad__oe \$317 + connect \sdr_dq_9__pad__o \$315 + connect \sdr_dq_9__core__i \$313 + connect \sdr_dq_8__pad__oe \$311 + connect \sdr_dq_8__pad__o \$309 + connect \sdr_dq_8__core__i \$307 + connect \sdr_dm_1__pad__o \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 +end +attribute \src "libresoc.v:140286.1-140475.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0" +attribute \generator "nMigen" +module \l0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 23 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 28 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 22 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 27 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 30 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 24 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 26 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 25 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 29 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \pimem_ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" + wire \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" + wire \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" + wire \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" + wire \pimem_x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire input 21 \wb_dcache_en + attribute \module_not_derived 1 + attribute \src "libresoc.v:140391.12-140425.4" + cell \l0$130 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 + connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140426.9-140448.4" + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \wb_dcache_en \wb_dcache_en + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140449.9-140473.4" + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + connect \pimem_ldst_port0_exc_$signal 1'0 +end +attribute \src "libresoc.v:140479.1-140887.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" +attribute \generator "nMigen" +module \l0$130 + attribute \src "libresoc.v:140742.3-140756.6" + wire $0\idx_l$23$next[0:0]$6210 + attribute \src "libresoc.v:140642.3-140643.35" + wire $0\idx_l$23[0:0]$6177 + attribute \src "libresoc.v:140500.7-140500.24" + wire $0\idx_l$23[0:0]$6232 + attribute \src "libresoc.v:140797.3-140806.6" + wire $0\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:140787.3-140796.6" + wire $0\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:140480.7-140480.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140663.3-140672.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6179 + attribute \src "libresoc.v:140673.3-140682.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6182 + attribute \src "libresoc.v:140715.3-140724.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:140705.3-140714.6" + wire $0\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:140777.3-140786.6" + wire $0\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:140852.3-140861.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6227 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6194 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6195 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6196 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6197 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6198 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6199 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6200 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal[0:0]$6193 + attribute \src "libresoc.v:140862.3-140871.6" + wire $0\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:140832.3-140841.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6221 + attribute \src "libresoc.v:140842.3-140851.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6224 + attribute \src "libresoc.v:140694.3-140704.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:140694.3-140704.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:140767.3-140776.6" + wire $0\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:140757.3-140766.6" + wire $0\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:140683.3-140693.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6185 + attribute \src "libresoc.v:140683.3-140693.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6186 + attribute \src "libresoc.v:140640.3-140641.36" + wire $0\reset_delay[0:0] + attribute \src "libresoc.v:140822.3-140831.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "libresoc.v:140807.3-140821.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "libresoc.v:140742.3-140756.6" + wire $1\idx_l$23$next[0:0]$6211 + attribute \src "libresoc.v:140797.3-140806.6" + wire $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:140787.3-140796.6" + wire $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:140663.3-140672.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6180 + attribute \src "libresoc.v:140673.3-140682.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6183 + attribute \src "libresoc.v:140715.3-140724.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:140705.3-140714.6" + wire $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:140777.3-140786.6" + wire $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:140852.3-140861.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6228 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6202 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6203 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6204 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6205 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6206 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6207 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6208 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal[0:0]$6201 + attribute \src "libresoc.v:140862.3-140871.6" + wire $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:140832.3-140841.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6222 + attribute \src "libresoc.v:140842.3-140851.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6225 + attribute \src "libresoc.v:140694.3-140704.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:140694.3-140704.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:140767.3-140776.6" + wire $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:140757.3-140766.6" + wire $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:140683.3-140693.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6187 + attribute \src "libresoc.v:140683.3-140693.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6188 + attribute \src "libresoc.v:140627.7-140627.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:140822.3-140831.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:140807.3-140821.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:140742.3-140756.6" + wire $2\idx_l$23$next[0:0]$6212 + attribute \src "libresoc.v:140807.3-140821.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:140638.18-140638.103" + wire $not$libresoc.v:140638$6173_Y + attribute \src "libresoc.v:140639.18-140639.118" + wire $not$libresoc.v:140639$6174_Y + attribute \src "libresoc.v:140636.18-140636.134" + wire $or$libresoc.v:140636$6171_Y + attribute \src "libresoc.v:140637.18-140637.120" + wire $ternary$libresoc.v:140637$6172_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \idx_l$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \idx_l$23$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \idx_l_r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \idx_l_s_idx_l + attribute \src "libresoc.v:140480.7-140480.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 output 25 \ldst_port0_addr_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \ldst_port0_addr_i_ok$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 27 \ldst_port0_addr_ok_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 23 \ldst_port0_busy_o$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 24 \ldst_port0_data_len$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 32 \ldst_port0_exc_$signal$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 21 \ldst_port0_is_ld_i$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 22 \ldst_port0_is_st_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 28 \ldst_port0_ld_data_o$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \ldst_port0_ld_data_o_ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \ldst_port0_st_data_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \ldst_port0_st_data_i_ok$17 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire \pick_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire \pick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $not$libresoc.v:140638$6173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pick_n + connect \Y $not$libresoc.v:140638$6173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $not$libresoc.v:140639$6174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o$10 + connect \Y $not$libresoc.v:140639$6174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $or$libresoc.v:140636$6171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:140636$6171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:140637$6172 + parameter \WIDTH 1 + connect \A \idx_l$23 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $ternary$libresoc.v:140637$6172_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140644.9-140650.4" + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \r_idx_l \idx_l_r_idx_l + connect \s_idx_l \idx_l_s_idx_l + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140651.8-140655.4" + cell \pick \pick + connect \i \pick_i + connect \n \pick_n + connect \o \pick_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140656.17-140662.4" + cell \reset_l$131 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \src "libresoc.v:140480.7-140480.20" + process $proc$libresoc.v:140480$6230 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:140500.7-140500.24" + process $proc$libresoc.v:140500$6231 + assign { } { } + assign $0\idx_l$23[0:0]$6232 1'0 + sync always + sync init + update \idx_l$23 $0\idx_l$23[0:0]$6232 + end + attribute \src "libresoc.v:140627.7-140627.25" + process $proc$libresoc.v:140627$6233 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:140640.3-140641.36" + process $proc$libresoc.v:140640$6175 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:140642.3-140643.35" + process $proc$libresoc.v:140642$6176 + assign { } { } + assign $0\idx_l$23[0:0]$6177 \idx_l$23$next + sync posedge \coresync_clk + update \idx_l$23 $0\idx_l$23[0:0]$6177 + end + attribute \src "libresoc.v:140663.3-140672.6" + process $proc$libresoc.v:140663$6178 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i$12[47:0]$6179 $1\ldst_port0_addr_i$12[47:0]$6180 + attribute \src "libresoc.v:140664.5-140664.29" + switch \initial + attribute \src "libresoc.v:140664.9-140664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i$12[47:0]$6180 \$32 [47:0] + case + assign $1\ldst_port0_addr_i$12[47:0]$6180 48'000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6179 + end + attribute \src "libresoc.v:140673.3-140682.6" + process $proc$libresoc.v:140673$6181 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$13[0:0]$6182 $1\ldst_port0_addr_i_ok$13[0:0]$6183 + attribute \src "libresoc.v:140674.5-140674.29" + switch \initial + attribute \src "libresoc.v:140674.9-140674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 \ldst_port0_addr_i_ok + case + assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 1'0 + end + sync always + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6182 + end + attribute \src "libresoc.v:140683.3-140693.6" + process $proc$libresoc.v:140683$6184 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_st_data_i$18[63:0]$6185 $1\ldst_port0_st_data_i$18[63:0]$6187 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6186 $1\ldst_port0_st_data_i_ok$17[0:0]$6188 + attribute \src "libresoc.v:140684.5-140684.29" + switch \initial + attribute \src "libresoc.v:140684.9-140684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6188 $1\ldst_port0_st_data_i$18[63:0]$6187 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + case + assign $1\ldst_port0_st_data_i$18[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6188 1'0 + end + sync always + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6185 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6186 + end + attribute \src "libresoc.v:140694.3-140704.6" + process $proc$libresoc.v:140694$6189 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:140695.5-140695.29" + switch \initial + attribute \src "libresoc.v:140695.9-140695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:140705.3-140714.6" + process $proc$libresoc.v:140705$6190 + assign { } { } + assign { } { } + assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:140706.5-140706.29" + switch \initial + attribute \src "libresoc.v:140706.9-140706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 + case + assign $1\ldst_port0_busy_o[0:0] 1'0 + end + sync always + update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] + end + attribute \src "libresoc.v:140715.3-140724.6" + process $proc$libresoc.v:140715$6191 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:140716.5-140716.29" + switch \initial + attribute \src "libresoc.v:140716.9-140716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:140725.3-140741.6" + process $proc$libresoc.v:140725$6192 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_exc_$signal[0:0]$6193 $1\ldst_port0_exc_$signal[0:0]$6201 + assign $0\ldst_port0_exc_$signal$1[0:0]$6194 $1\ldst_port0_exc_$signal$1[0:0]$6202 + assign $0\ldst_port0_exc_$signal$2[0:0]$6195 $1\ldst_port0_exc_$signal$2[0:0]$6203 + assign $0\ldst_port0_exc_$signal$3[0:0]$6196 $1\ldst_port0_exc_$signal$3[0:0]$6204 + assign $0\ldst_port0_exc_$signal$4[0:0]$6197 $1\ldst_port0_exc_$signal$4[0:0]$6205 + assign $0\ldst_port0_exc_$signal$5[0:0]$6198 $1\ldst_port0_exc_$signal$5[0:0]$6206 + assign $0\ldst_port0_exc_$signal$6[0:0]$6199 $1\ldst_port0_exc_$signal$6[0:0]$6207 + assign $0\ldst_port0_exc_$signal$7[0:0]$6200 $1\ldst_port0_exc_$signal$7[0:0]$6208 + attribute \src "libresoc.v:140726.5-140726.29" + switch \initial + attribute \src "libresoc.v:140726.9-140726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6208 $1\ldst_port0_exc_$signal$6[0:0]$6207 $1\ldst_port0_exc_$signal$5[0:0]$6206 $1\ldst_port0_exc_$signal$4[0:0]$6205 $1\ldst_port0_exc_$signal$3[0:0]$6204 $1\ldst_port0_exc_$signal$2[0:0]$6203 $1\ldst_port0_exc_$signal$1[0:0]$6202 $1\ldst_port0_exc_$signal[0:0]$6201 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + case + assign $1\ldst_port0_exc_$signal[0:0]$6201 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6202 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6203 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6204 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6205 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6206 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6207 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6208 1'0 + end + sync always + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6193 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6194 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6195 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6196 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6197 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6198 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6199 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6200 + end + attribute \src "libresoc.v:140742.3-140756.6" + process $proc$libresoc.v:140742$6209 + assign { } { } + assign { } { } + assign { } { } + assign $0\idx_l$23$next[0:0]$6210 $2\idx_l$23$next[0:0]$6212 + attribute \src "libresoc.v:140743.5-140743.29" + switch \initial + attribute \src "libresoc.v:140743.9-140743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l$23$next[0:0]$6211 \pick_o + case + assign $1\idx_l$23$next[0:0]$6211 \idx_l$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\idx_l$23$next[0:0]$6212 1'0 + case + assign $2\idx_l$23$next[0:0]$6212 $1\idx_l$23$next[0:0]$6211 + end + sync always + update \idx_l$23$next $0\idx_l$23$next[0:0]$6210 + end + attribute \src "libresoc.v:140757.3-140766.6" + process $proc$libresoc.v:140757$6213 + assign { } { } + assign { } { } + assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:140758.5-140758.29" + switch \initial + attribute \src "libresoc.v:140758.9-140758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 + case + assign $1\ldst_port0_mmu_done[0:0] 1'0 + end + sync always + update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] + end + attribute \src "libresoc.v:140767.3-140776.6" + process $proc$libresoc.v:140767$6214 + assign { } { } + assign { } { } + assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:140768.5-140768.29" + switch \initial + attribute \src "libresoc.v:140768.9-140768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 + case + assign $1\ldst_port0_ldst_error[0:0] 1'0 + end + sync always + update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] + end + attribute \src "libresoc.v:140777.3-140786.6" + process $proc$libresoc.v:140777$6215 + assign { } { } + assign { } { } + assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:140778.5-140778.29" + switch \initial + attribute \src "libresoc.v:140778.9-140778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 + case + assign $1\ldst_port0_cache_paradox[0:0] 1'0 + end + sync always + update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] + end + attribute \src "libresoc.v:140787.3-140796.6" + process $proc$libresoc.v:140787$6216 + assign { } { } + assign { } { } + assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:140788.5-140788.29" + switch \initial + attribute \src "libresoc.v:140788.9-140788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch \$26 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_s_idx_l[0:0] 1'1 + case + assign $1\idx_l_s_idx_l[0:0] 1'0 + end + sync always + update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] + end + attribute \src "libresoc.v:140797.3-140806.6" + process $proc$libresoc.v:140797$6217 + assign { } { } + assign { } { } + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:140798.5-140798.29" + switch \initial + attribute \src "libresoc.v:140798.9-140798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_r_idx_l[0:0] 1'1 + case + assign $1\idx_l_r_idx_l[0:0] 1'1 + end + sync always + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] + end + attribute \src "libresoc.v:140807.3-140821.6" + process $proc$libresoc.v:140807$6218 + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:140808.5-140808.29" + switch \initial + attribute \src "libresoc.v:140808.9-140808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch \$28 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] 1'1 + case + assign $2\reset_l_s_reset[0:0] 1'0 + end + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:140822.3-140831.6" + process $proc$libresoc.v:140822$6219 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:140823.5-140823.29" + switch \initial + attribute \src "libresoc.v:140823.9-140823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:140832.3-140841.6" + process $proc$libresoc.v:140832$6220 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_ld_i$8[0:0]$6221 $1\ldst_port0_is_ld_i$8[0:0]$6222 + attribute \src "libresoc.v:140833.5-140833.29" + switch \initial + attribute \src "libresoc.v:140833.9-140833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_ld_i$8[0:0]$6222 \ldst_port0_is_ld_i + case + assign $1\ldst_port0_is_ld_i$8[0:0]$6222 1'0 + end + sync always + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6221 + end + attribute \src "libresoc.v:140842.3-140851.6" + process $proc$libresoc.v:140842$6223 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_st_i$9[0:0]$6224 $1\ldst_port0_is_st_i$9[0:0]$6225 + attribute \src "libresoc.v:140843.5-140843.29" + switch \initial + attribute \src "libresoc.v:140843.9-140843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_st_i$9[0:0]$6225 \ldst_port0_is_st_i + case + assign $1\ldst_port0_is_st_i$9[0:0]$6225 1'0 + end + sync always + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6224 + end + attribute \src "libresoc.v:140852.3-140861.6" + process $proc$libresoc.v:140852$6226 + assign { } { } + assign { } { } + assign $0\ldst_port0_data_len$11[3:0]$6227 $1\ldst_port0_data_len$11[3:0]$6228 + attribute \src "libresoc.v:140853.5-140853.29" + switch \initial + attribute \src "libresoc.v:140853.9-140853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_data_len$11[3:0]$6228 \ldst_port0_data_len + case + assign $1\ldst_port0_data_len$11[3:0]$6228 4'0000 + end + sync always + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6227 + end + attribute \src "libresoc.v:140862.3-140871.6" + process $proc$libresoc.v:140862$6229 + assign { } { } + assign { } { } + assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:140863.5-140863.29" + switch \initial + attribute \src "libresoc.v:140863.9-140863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 + case + assign $1\ldst_port0_go_die_i[0:0] 1'0 + end + sync always + update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] + end + connect \$20 $or$libresoc.v:140636$6171_Y + connect \$24 $ternary$libresoc.v:140637$6172_Y + connect \$26 $not$libresoc.v:140638$6173_Y + connect \$28 $not$libresoc.v:140639$6174_Y + connect \$22 \$24 + connect \$32 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$30 1'0 + connect \ldst_port0_exc_$signal$33 1'0 + connect \ldst_port0_exc_$signal$34 1'0 + connect \ldst_port0_exc_$signal$35 1'0 + connect \ldst_port0_exc_$signal$36 1'0 + connect \ldst_port0_exc_$signal$37 1'0 + connect \ldst_port0_exc_$signal$38 1'0 + connect \ldst_port0_exc_$signal$39 1'0 + connect \ldst_port0_mmu_done$40 1'0 + connect \ldst_port0_ldst_error$41 1'0 + connect \ldst_port0_cache_paradox$42 1'0 + connect \reset_delay$next \reset_l_q_reset + connect \pick_i \$20 +end +attribute \src "libresoc.v:140891.1-140949.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" +attribute \generator "nMigen" +module \ld_active + attribute \src "libresoc.v:140892.7-140892.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140937.3-140945.6" + wire $0\q_int$next[0:0]$6244 + attribute \src "libresoc.v:140935.3-140936.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:140937.3-140945.6" + wire $1\q_int$next[0:0]$6245 + attribute \src "libresoc.v:140914.7-140914.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:140927.17-140927.96" + wire $and$libresoc.v:140927$6234_Y + attribute \src "libresoc.v:140932.17-140932.96" + wire $and$libresoc.v:140932$6239_Y + attribute \src "libresoc.v:140929.18-140929.99" + wire $not$libresoc.v:140929$6236_Y + attribute \src "libresoc.v:140931.17-140931.98" + wire $not$libresoc.v:140931$6238_Y + attribute \src "libresoc.v:140934.17-140934.98" + wire $not$libresoc.v:140934$6241_Y + attribute \src "libresoc.v:140928.18-140928.104" + wire $or$libresoc.v:140928$6235_Y + attribute \src "libresoc.v:140930.18-140930.105" + wire $or$libresoc.v:140930$6237_Y + attribute \src "libresoc.v:140933.17-140933.103" + wire $or$libresoc.v:140933$6240_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:140892.7-140892.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:140927$6234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:140927$6234_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:140932$6239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:140932$6239_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:140929$6236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $not$libresoc.v:140929$6236_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:140931$6238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:140931$6238_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:140934$6241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:140934$6241_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:140928$6235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_ld_active + connect \Y $or$libresoc.v:140928$6235_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:140930$6237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $or$libresoc.v:140930$6237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:140933$6240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_ld_active + connect \Y $or$libresoc.v:140933$6240_Y + end + attribute \src "libresoc.v:140892.7-140892.20" + process $proc$libresoc.v:140892$6246 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:140914.7-140914.19" + process $proc$libresoc.v:140914$6247 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:140935.3-140936.27" + process $proc$libresoc.v:140935$6242 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:140937.3-140945.6" + process $proc$libresoc.v:140937$6243 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6244 $1\q_int$next[0:0]$6245 + attribute \src "libresoc.v:140938.5-140938.29" + switch \initial + attribute \src "libresoc.v:140938.9-140938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6245 1'0 + case + assign $1\q_int$next[0:0]$6245 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6244 + end + connect \$9 $and$libresoc.v:140927$6234_Y + connect \$11 $or$libresoc.v:140928$6235_Y + connect \$13 $not$libresoc.v:140929$6236_Y + connect \$15 $or$libresoc.v:140930$6237_Y + connect \$1 $not$libresoc.v:140931$6238_Y + connect \$3 $and$libresoc.v:140932$6239_Y + connect \$5 $or$libresoc.v:140933$6240_Y + connect \$7 $not$libresoc.v:140934$6241_Y + connect \qlq_ld_active \$15 + connect \qn_ld_active \$13 + connect \q_ld_active \$11 +end +attribute \src "libresoc.v:140953.1-142316.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" +attribute \generator "nMigen" +module \ldst0 + attribute \src "libresoc.v:141971.3-141979.6" + wire $0\adr_l_r_adr$next[0:0]$6390 + attribute \src "libresoc.v:141853.3-141854.39" + wire $0\adr_l_r_adr[0:0] + attribute \src "libresoc.v:141799.3-141800.21" + wire $0\alu_ok[0:0] + attribute \src "libresoc.v:142136.3-142145.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:142146.3-142155.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:142126.3-142135.6" + wire width 64 $0\ea_r$next[63:0]$6478 + attribute \src "libresoc.v:141801.3-141802.25" + wire width 64 $0\ea_r[63:0] + attribute \src "libresoc.v:140954.7-140954.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:142201.3-142220.6" + wire width 64 $0\ldd_o[63:0] + attribute \src "libresoc.v:142165.3-142188.6" + wire width 64 $0\lddata_r[63:0] + attribute \src "libresoc.v:142068.3-142077.6" + wire width 64 $0\ldo_r$next[63:0]$6463 + attribute \src "libresoc.v:141809.3-141810.27" + wire width 64 $0\ldo_r[63:0] + attribute \src "libresoc.v:141797.3-141798.33" + wire width 96 $0\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:142156.3-142164.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6483 + attribute \src "libresoc.v:141795.3-141796.57" + wire $0\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:142245.3-142256.6" + wire width 64 $0\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:142016.3-142024.6" + wire $0\lsd_l_r_lsd$next[0:0]$6405 + attribute \src "libresoc.v:141843.3-141844.39" + wire $0\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:141944.3-141952.6" + wire $0\opc_l_r_opc$next[0:0]$6381 + attribute \src "libresoc.v:141859.3-141860.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:141935.3-141943.6" + wire $0\opc_l_s_opc$next[0:0]$6378 + attribute \src "libresoc.v:141861.3-141862.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__byte_reverse$next[0:0]$6408 + attribute \src "libresoc.v:141835.3-141836.57" + wire $0\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6409 + attribute \src "libresoc.v:141833.3-141834.49" + wire width 4 $0\oper_r__data_len[3:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6410 + attribute \src "libresoc.v:141813.3-141814.47" + wire width 14 $0\oper_r__fn_unit[13:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6411 + attribute \src "libresoc.v:141815.3-141816.61" + wire width 64 $0\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6412 + attribute \src "libresoc.v:141817.3-141818.57" + wire $0\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $0\oper_r__insn$next[31:0]$6413 + attribute \src "libresoc.v:141841.3-141842.41" + wire width 32 $0\oper_r__insn[31:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6414 + attribute \src "libresoc.v:141811.3-141812.51" + wire width 7 $0\oper_r__insn_type[6:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__is_32bit$next[0:0]$6415 + attribute \src "libresoc.v:141829.3-141830.49" + wire $0\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__is_signed$next[0:0]$6416 + attribute \src "libresoc.v:141831.3-141832.51" + wire $0\oper_r__is_signed[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6417 + attribute \src "libresoc.v:141839.3-141840.51" + wire width 2 $0\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__oe__oe$next[0:0]$6418 + attribute \src "libresoc.v:141825.3-141826.45" + wire $0\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__oe__ok$next[0:0]$6419 + attribute \src "libresoc.v:141827.3-141828.45" + wire $0\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__rc__ok$next[0:0]$6420 + attribute \src "libresoc.v:141823.3-141824.45" + wire $0\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__rc__rc$next[0:0]$6421 + attribute \src "libresoc.v:141821.3-141822.45" + wire $0\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__sign_extend$next[0:0]$6422 + attribute \src "libresoc.v:141837.3-141838.55" + wire $0\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__zero_a$next[0:0]$6423 + attribute \src "libresoc.v:141819.3-141820.45" + wire $0\oper_r__zero_a[0:0] + attribute \src "libresoc.v:141863.3-141864.28" + wire $0\p_st_go[0:0] + attribute \src "libresoc.v:142189.3-142200.6" + wire width 64 $0\revnorev[63:0] + attribute \src "libresoc.v:141962.3-141970.6" + wire width 3 $0\src_l_r_src$next[2:0]$6387 + attribute \src "libresoc.v:141855.3-141856.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:141953.3-141961.6" + wire width 3 $0\src_l_s_src$next[2:0]$6384 + attribute \src "libresoc.v:141857.3-141858.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $0\src_r0$next[63:0]$6466 + attribute \src "libresoc.v:141807.3-141808.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $0\src_r1$next[63:0]$6470 + attribute \src "libresoc.v:141805.3-141806.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $0\src_r2$next[63:0]$6474 + attribute \src "libresoc.v:141803.3-141804.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:142221.3-142244.6" + wire width 64 $0\stdata_r[63:0] + attribute \src "libresoc.v:142007.3-142015.6" + wire $0\sto_l_r_sto$next[0:0]$6402 + attribute \src "libresoc.v:141845.3-141846.39" + wire $0\sto_l_r_sto[0:0] + attribute \src "libresoc.v:141998.3-142006.6" + wire $0\upd_l_r_upd$next[0:0]$6399 + attribute \src "libresoc.v:141847.3-141848.39" + wire $0\upd_l_r_upd[0:0] + attribute \src "libresoc.v:141989.3-141997.6" + wire $0\upd_l_s_upd$next[0:0]$6396 + attribute \src "libresoc.v:141849.3-141850.39" + wire $0\upd_l_s_upd[0:0] + attribute \src "libresoc.v:141980.3-141988.6" + wire $0\wri_l_r_wri$next[0:0]$6393 + attribute \src "libresoc.v:141851.3-141852.39" + wire $0\wri_l_r_wri[0:0] + attribute \src "libresoc.v:141971.3-141979.6" + wire $1\adr_l_r_adr$next[0:0]$6391 + attribute \src "libresoc.v:141150.7-141150.25" + wire $1\adr_l_r_adr[0:0] + attribute \src "libresoc.v:141164.7-141164.20" + wire $1\alu_ok[0:0] + attribute \src "libresoc.v:142136.3-142145.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:142146.3-142155.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:142126.3-142135.6" + wire width 64 $1\ea_r$next[63:0]$6479 + attribute \src "libresoc.v:141210.14-141210.41" + wire width 64 $1\ea_r[63:0] + attribute \src "libresoc.v:142201.3-142220.6" + wire width 64 $1\ldd_o[63:0] + attribute \src "libresoc.v:142165.3-142188.6" + wire width 64 $1\lddata_r[63:0] + attribute \src "libresoc.v:142068.3-142077.6" + wire width 64 $1\ldo_r$next[63:0]$6464 + attribute \src "libresoc.v:141240.14-141240.42" + wire width 64 $1\ldo_r[63:0] + attribute \src "libresoc.v:141245.14-141245.62" + wire width 96 $1\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:142156.3-142164.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6484 + attribute \src "libresoc.v:141250.7-141250.34" + wire $1\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:142245.3-142256.6" + wire width 64 $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:142016.3-142024.6" + wire $1\lsd_l_r_lsd$next[0:0]$6406 + attribute \src "libresoc.v:141299.7-141299.25" + wire $1\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:141944.3-141952.6" + wire $1\opc_l_r_opc$next[0:0]$6382 + attribute \src "libresoc.v:141313.7-141313.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:141935.3-141943.6" + wire $1\opc_l_s_opc$next[0:0]$6379 + attribute \src "libresoc.v:141317.7-141317.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__byte_reverse$next[0:0]$6424 + attribute \src "libresoc.v:141448.7-141448.34" + wire $1\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6425 + attribute \src "libresoc.v:141452.13-141452.36" + wire width 4 $1\oper_r__data_len[3:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6426 + attribute \src "libresoc.v:141471.14-141471.40" + wire width 14 $1\oper_r__fn_unit[13:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6427 + attribute \src "libresoc.v:141475.14-141475.59" + wire width 64 $1\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6428 + attribute \src "libresoc.v:141479.7-141479.34" + wire $1\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $1\oper_r__insn$next[31:0]$6429 + attribute \src "libresoc.v:141483.14-141483.34" + wire width 32 $1\oper_r__insn[31:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6430 + attribute \src "libresoc.v:141562.13-141562.38" + wire width 7 $1\oper_r__insn_type[6:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__is_32bit$next[0:0]$6431 + attribute \src "libresoc.v:141566.7-141566.30" + wire $1\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__is_signed$next[0:0]$6432 + attribute \src "libresoc.v:141570.7-141570.31" + wire $1\oper_r__is_signed[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6433 + attribute \src "libresoc.v:141579.13-141579.37" + wire width 2 $1\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__oe__oe$next[0:0]$6434 + attribute \src "libresoc.v:141583.7-141583.28" + wire $1\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__oe__ok$next[0:0]$6435 + attribute \src "libresoc.v:141587.7-141587.28" + wire $1\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__rc__ok$next[0:0]$6436 + attribute \src "libresoc.v:141591.7-141591.28" + wire $1\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__rc__rc$next[0:0]$6437 + attribute \src "libresoc.v:141595.7-141595.28" + wire $1\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__sign_extend$next[0:0]$6438 + attribute \src "libresoc.v:141599.7-141599.33" + wire $1\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__zero_a$next[0:0]$6439 + attribute \src "libresoc.v:141603.7-141603.28" + wire $1\oper_r__zero_a[0:0] + attribute \src "libresoc.v:141607.7-141607.21" + wire $1\p_st_go[0:0] + attribute \src "libresoc.v:142189.3-142200.6" + wire width 64 $1\revnorev[63:0] + attribute \src "libresoc.v:141962.3-141970.6" + wire width 3 $1\src_l_r_src$next[2:0]$6388 + attribute \src "libresoc.v:141649.13-141649.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:141953.3-141961.6" + wire width 3 $1\src_l_s_src$next[2:0]$6385 + attribute \src "libresoc.v:141653.13-141653.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $1\src_r0$next[63:0]$6467 + attribute \src "libresoc.v:141657.14-141657.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $1\src_r1$next[63:0]$6471 + attribute \src "libresoc.v:141661.14-141661.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $1\src_r2$next[63:0]$6475 + attribute \src "libresoc.v:141665.14-141665.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:142221.3-142244.6" + wire width 64 $1\stdata_r[63:0] + attribute \src "libresoc.v:142007.3-142015.6" + wire $1\sto_l_r_sto$next[0:0]$6403 + attribute \src "libresoc.v:141675.7-141675.25" + wire $1\sto_l_r_sto[0:0] + attribute \src "libresoc.v:141998.3-142006.6" + wire $1\upd_l_r_upd$next[0:0]$6400 + attribute \src "libresoc.v:141685.7-141685.25" + wire $1\upd_l_r_upd[0:0] + attribute \src "libresoc.v:141989.3-141997.6" + wire $1\upd_l_s_upd$next[0:0]$6397 + attribute \src "libresoc.v:141689.7-141689.25" + wire $1\upd_l_s_upd[0:0] + attribute \src "libresoc.v:141980.3-141988.6" + wire $1\wri_l_r_wri$next[0:0]$6394 + attribute \src "libresoc.v:141699.7-141699.25" + wire $1\wri_l_r_wri[0:0] + attribute \src "libresoc.v:142201.3-142220.6" + wire width 64 $2\ldd_o[63:0] + attribute \src "libresoc.v:142165.3-142188.6" + wire width 64 $2\lddata_r[63:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__byte_reverse$next[0:0]$6440 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6441 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6442 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6443 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6444 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $2\oper_r__insn$next[31:0]$6445 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6446 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__is_32bit$next[0:0]$6447 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__is_signed$next[0:0]$6448 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6449 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__oe__oe$next[0:0]$6450 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__oe__ok$next[0:0]$6451 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__rc__ok$next[0:0]$6452 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__rc__rc$next[0:0]$6453 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__sign_extend$next[0:0]$6454 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__zero_a$next[0:0]$6455 + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $2\src_r0$next[63:0]$6468 + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $2\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $2\src_r2$next[63:0]$6476 + attribute \src "libresoc.v:142221.3-142244.6" + wire width 64 $2\stdata_r[63:0] + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6456 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6457 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__oe__oe$next[0:0]$6458 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__oe__ok$next[0:0]$6459 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__rc__ok$next[0:0]$6460 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__rc__rc$next[0:0]$6461 + attribute \src "libresoc.v:141781.18-141781.124" + wire width 65 $add$libresoc.v:141781$6328_Y + attribute \src "libresoc.v:141704.19-141704.118" + wire $and$libresoc.v:141704$6248_Y + attribute \src "libresoc.v:141705.19-141705.125" + wire $and$libresoc.v:141705$6249_Y + attribute \src "libresoc.v:141706.19-141706.120" + wire $and$libresoc.v:141706$6250_Y + attribute \src "libresoc.v:141707.19-141707.125" + wire $and$libresoc.v:141707$6251_Y + attribute \src "libresoc.v:141708.19-141708.118" + wire $and$libresoc.v:141708$6252_Y + attribute \src "libresoc.v:141710.19-141710.119" + wire $and$libresoc.v:141710$6254_Y + attribute \src "libresoc.v:141711.19-141711.123" + wire $and$libresoc.v:141711$6255_Y + attribute \src "libresoc.v:141712.19-141712.123" + wire $and$libresoc.v:141712$6256_Y + attribute \src "libresoc.v:141713.19-141713.120" + wire $and$libresoc.v:141713$6257_Y + attribute \src "libresoc.v:141714.19-141714.123" + wire $and$libresoc.v:141714$6258_Y + attribute \src "libresoc.v:141715.19-141715.119" + wire $and$libresoc.v:141715$6259_Y + attribute \src "libresoc.v:141716.19-141716.123" + wire $and$libresoc.v:141716$6260_Y + attribute \src "libresoc.v:141717.19-141717.125" + wire $and$libresoc.v:141717$6261_Y + attribute \src "libresoc.v:141719.19-141719.116" + wire $and$libresoc.v:141719$6263_Y + attribute \src "libresoc.v:141721.19-141721.120" + wire $and$libresoc.v:141721$6265_Y + attribute \src "libresoc.v:141722.19-141722.123" + wire $and$libresoc.v:141722$6266_Y + attribute \src "libresoc.v:141726.19-141726.125" + wire $and$libresoc.v:141726$6270_Y + attribute \src "libresoc.v:141727.19-141727.123" + wire $and$libresoc.v:141727$6271_Y + attribute \src "libresoc.v:141732.19-141732.116" + wire $and$libresoc.v:141732$6276_Y + attribute \src "libresoc.v:141734.19-141734.116" + wire $and$libresoc.v:141734$6278_Y + attribute \src "libresoc.v:141737.19-141737.118" + wire $and$libresoc.v:141737$6281_Y + attribute \src "libresoc.v:141739.19-141739.125" + wire $and$libresoc.v:141739$6283_Y + attribute \src "libresoc.v:141742.19-141742.160" + wire width 3 $and$libresoc.v:141742$6286_Y + attribute \src "libresoc.v:141743.19-141743.122" + wire $and$libresoc.v:141743$6287_Y + attribute \src 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output 2 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 31 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 30 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 33 \ea + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \ea_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \ea_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$185 + attribute \src "libresoc.v:140954.7-140954.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" + wire \ld_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" + wire \ld_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" + wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" + wire width 64 \ldd_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" + wire width 64 \lddata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 38 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 \ldst_port0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \ldst_port0_addr_i_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 48 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 34 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 37 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 40 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 41 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 42 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 43 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 44 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 45 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 46 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 47 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 35 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 36 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 49 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 50 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 51 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" + wire \load_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \lod_l_qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \lod_l_r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \lsd_l_q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \lsd_l_r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \lsd_l_r_lsd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \lsd_l_s_lsd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" + wire \op_is_st + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \oper_r__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + 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end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" + cell $or $or$libresoc.v:141790$6337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $or$libresoc.v:141790$6337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $or $or$libresoc.v:141791$6338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $or$libresoc.v:141791$6338_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $pos$libresoc.v:141745$6290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 96 + parameter \Y_WIDTH 96 + connect \A $extend$libresoc.v:141745$6289_Y + connect \Y $pos$libresoc.v:141745$6290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:141747$6293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:141747$6292_Y + connect \Y $pos$libresoc.v:141747$6293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:141748$6294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $pos$libresoc.v:141748$6294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:141750$6296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $pos$libresoc.v:141750$6296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:141752$6299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:141752$6298_Y + connect \Y $pos$libresoc.v:141752$6299_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:141753$6300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $pos$libresoc.v:141753$6300_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:141754$6301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $pos$libresoc.v:141754$6301_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:141777$6324 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $ternary$libresoc.v:141777$6324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:141778$6325 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $ternary$libresoc.v:141778$6325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" + cell $mux $ternary$libresoc.v:141779$6326 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $ternary$libresoc.v:141779$6326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" + cell $mux $ternary$libresoc.v:141780$6327 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok + connect \Y $ternary$libresoc.v:141780$6327_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141865.9-141871.4" + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_adr \adr_l_q_adr + connect \r_adr \adr_l_r_adr + connect \s_adr \adr_l_s_adr + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141872.15-141878.4" + cell \alu_l$128 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141879.9-141885.4" + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \qn_lod \lod_l_qn_lod + connect \r_lod \lod_l_r_lod + connect \s_lod \lod_l_s_lod + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141886.9-141892.4" + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_lsd \lsd_l_q_lsd + connect \r_lsd \lsd_l_r_lsd + connect \s_lsd \lsd_l_s_lsd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141893.15-141899.4" + cell \opc_l$126 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141900.15-141906.4" + cell \rst_l$129 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rst \rst_l_q_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141907.15-141913.4" + cell \src_l$127 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141914.9-141920.4" + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_sto \sto_l_q_sto + connect \r_sto \sto_l_r_sto + connect \s_sto \sto_l_s_sto + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141921.9-141927.4" + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_upd \upd_l_q_upd + connect \r_upd \upd_l_r_upd + connect \s_upd \upd_l_s_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141928.9-141934.4" + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_wri \wri_l_q_wri + connect \r_wri \wri_l_r_wri + connect \s_wri \wri_l_s_wri + end + attribute \src "libresoc.v:140954.7-140954.20" + process $proc$libresoc.v:140954$6490 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:141150.7-141150.25" + process $proc$libresoc.v:141150$6491 + assign { } { } + assign $1\adr_l_r_adr[0:0] 1'1 + sync always + sync init + update \adr_l_r_adr $1\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:141164.7-141164.20" + process $proc$libresoc.v:141164$6492 + assign { } { } + assign $1\alu_ok[0:0] 1'0 + sync always + sync init + update \alu_ok $1\alu_ok[0:0] + end + attribute \src "libresoc.v:141210.14-141210.41" + process $proc$libresoc.v:141210$6493 + assign { } { } + assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ea_r $1\ea_r[63:0] + end + attribute \src "libresoc.v:141240.14-141240.42" + process $proc$libresoc.v:141240$6494 + assign { } { } + assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldo_r $1\ldo_r[63:0] + end + attribute \src "libresoc.v:141245.14-141245.62" + process $proc$libresoc.v:141245$6495 + assign { } { } + assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:141250.7-141250.34" + process $proc$libresoc.v:141250$6496 + assign { } { } + assign $1\ldst_port0_addr_i_ok[0:0] 1'0 + sync always + sync init + update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:141299.7-141299.25" + process $proc$libresoc.v:141299$6497 + assign { } { } + assign $1\lsd_l_r_lsd[0:0] 1'1 + sync always + sync init + update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:141313.7-141313.25" + process $proc$libresoc.v:141313$6498 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:141317.7-141317.25" + process $proc$libresoc.v:141317$6499 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:141448.7-141448.34" + process $proc$libresoc.v:141448$6500 + assign { } { } + assign $1\oper_r__byte_reverse[0:0] 1'0 + sync always + sync init + update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:141452.13-141452.36" + process $proc$libresoc.v:141452$6501 + assign { } { } + assign $1\oper_r__data_len[3:0] 4'0000 + sync always + sync init + update \oper_r__data_len $1\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:141471.14-141471.40" + process $proc$libresoc.v:141471$6502 + assign { } { } + assign $1\oper_r__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] + end + attribute \src "libresoc.v:141475.14-141475.59" + process $proc$libresoc.v:141475$6503 + assign { } { } + assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:141479.7-141479.34" + process $proc$libresoc.v:141479$6504 + assign { } { } + assign $1\oper_r__imm_data__ok[0:0] 1'0 + sync always + sync init + update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:141483.14-141483.34" + process $proc$libresoc.v:141483$6505 + assign { } { } + assign $1\oper_r__insn[31:0] 0 + sync always + sync init + update \oper_r__insn $1\oper_r__insn[31:0] + end + attribute \src "libresoc.v:141562.13-141562.38" + process $proc$libresoc.v:141562$6506 + assign { } { } + assign $1\oper_r__insn_type[6:0] 7'0000000 + sync always + sync init + update \oper_r__insn_type $1\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:141566.7-141566.30" + process $proc$libresoc.v:141566$6507 + assign { } { } + assign $1\oper_r__is_32bit[0:0] 1'0 + sync always + sync init + update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:141570.7-141570.31" + process $proc$libresoc.v:141570$6508 + assign { } { } + assign $1\oper_r__is_signed[0:0] 1'0 + sync always + sync init + update \oper_r__is_signed $1\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:141579.13-141579.37" + process $proc$libresoc.v:141579$6509 + assign { } { } + assign $1\oper_r__ldst_mode[1:0] 2'00 + sync always + sync init + update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:141583.7-141583.28" + process $proc$libresoc.v:141583$6510 + assign { } { } + assign $1\oper_r__oe__oe[0:0] 1'0 + sync always + sync init + update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:141587.7-141587.28" + process $proc$libresoc.v:141587$6511 + assign { } { } + assign $1\oper_r__oe__ok[0:0] 1'0 + sync always + sync init + update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:141591.7-141591.28" + process $proc$libresoc.v:141591$6512 + assign { } { } + assign $1\oper_r__rc__ok[0:0] 1'0 + sync always + sync init + update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:141595.7-141595.28" + process $proc$libresoc.v:141595$6513 + assign { } { } + assign $1\oper_r__rc__rc[0:0] 1'0 + sync always + sync init + update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:141599.7-141599.33" + process $proc$libresoc.v:141599$6514 + assign { } { } + assign $1\oper_r__sign_extend[0:0] 1'0 + sync always + sync init + update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:141603.7-141603.28" + process $proc$libresoc.v:141603$6515 + assign { } { } + assign $1\oper_r__zero_a[0:0] 1'0 + sync always + sync init + update \oper_r__zero_a $1\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:141607.7-141607.21" + process $proc$libresoc.v:141607$6516 + assign { } { } + assign $1\p_st_go[0:0] 1'0 + sync always + sync init + update \p_st_go $1\p_st_go[0:0] + end + attribute \src "libresoc.v:141649.13-141649.31" + process $proc$libresoc.v:141649$6517 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:141653.13-141653.31" + process $proc$libresoc.v:141653$6518 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:141657.14-141657.43" + process $proc$libresoc.v:141657$6519 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:141661.14-141661.43" + process $proc$libresoc.v:141661$6520 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:141665.14-141665.43" + process $proc$libresoc.v:141665$6521 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:141675.7-141675.25" + process $proc$libresoc.v:141675$6522 + assign { } { } + assign $1\sto_l_r_sto[0:0] 1'1 + sync always + sync init + update \sto_l_r_sto $1\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:141685.7-141685.25" + process $proc$libresoc.v:141685$6523 + assign { } { } + assign $1\upd_l_r_upd[0:0] 1'1 + sync always + sync init + update \upd_l_r_upd $1\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:141689.7-141689.25" + process $proc$libresoc.v:141689$6524 + assign { } { } + assign $1\upd_l_s_upd[0:0] 1'0 + sync always + sync init + update \upd_l_s_upd $1\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:141699.7-141699.25" + process $proc$libresoc.v:141699$6525 + assign { } { } + assign $1\wri_l_r_wri[0:0] 1'1 + sync always + sync init + update \wri_l_r_wri $1\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:141795.3-141796.57" + process $proc$libresoc.v:141795$6342 + assign { } { } + assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:141797.3-141798.33" + process $proc$libresoc.v:141797$6343 + assign { } { } + assign $0\ldst_port0_addr_i[95:0] \$175 + sync posedge \coresync_clk + update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:141799.3-141800.21" + process $proc$libresoc.v:141799$6344 + assign { } { } + assign $0\alu_ok[0:0] \$96 + sync posedge \coresync_clk + update \alu_ok $0\alu_ok[0:0] + end + attribute \src "libresoc.v:141801.3-141802.25" + process $proc$libresoc.v:141801$6345 + assign { } { } + assign $0\ea_r[63:0] \ea_r$next + sync posedge \coresync_clk + update \ea_r $0\ea_r[63:0] + end + attribute \src "libresoc.v:141803.3-141804.29" + process $proc$libresoc.v:141803$6346 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:141805.3-141806.29" + process $proc$libresoc.v:141805$6347 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:141807.3-141808.29" + process $proc$libresoc.v:141807$6348 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:141809.3-141810.27" + process $proc$libresoc.v:141809$6349 + assign { } { } + assign $0\ldo_r[63:0] \ldo_r$next + sync posedge \coresync_clk + update \ldo_r $0\ldo_r[63:0] + end + attribute \src "libresoc.v:141811.3-141812.51" + process $proc$libresoc.v:141811$6350 + assign { } { } + assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + sync posedge \coresync_clk + update \oper_r__insn_type $0\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:141813.3-141814.47" + process $proc$libresoc.v:141813$6351 + assign { } { } + assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next + sync posedge \coresync_clk + update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] + end + attribute \src "libresoc.v:141815.3-141816.61" + process $proc$libresoc.v:141815$6352 + assign { } { } + assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + sync posedge \coresync_clk + update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:141817.3-141818.57" + process $proc$libresoc.v:141817$6353 + assign { } { } + assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + sync posedge \coresync_clk + update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:141819.3-141820.45" + process $proc$libresoc.v:141819$6354 + assign { } { } + assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + sync posedge \coresync_clk + update \oper_r__zero_a $0\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:141821.3-141822.45" + process $proc$libresoc.v:141821$6355 + assign { } { } + assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + sync posedge \coresync_clk + update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:141823.3-141824.45" + process $proc$libresoc.v:141823$6356 + assign { } { } + assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + sync posedge \coresync_clk + update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:141825.3-141826.45" + process $proc$libresoc.v:141825$6357 + assign { } { } + assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + sync posedge \coresync_clk + update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:141827.3-141828.45" + process $proc$libresoc.v:141827$6358 + assign { } { } + assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + sync posedge \coresync_clk + update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:141829.3-141830.49" + process $proc$libresoc.v:141829$6359 + assign { } { } + assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + sync posedge \coresync_clk + update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:141831.3-141832.51" + process $proc$libresoc.v:141831$6360 + assign { } { } + assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + sync posedge \coresync_clk + update \oper_r__is_signed $0\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:141833.3-141834.49" + process $proc$libresoc.v:141833$6361 + assign { } { } + assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + sync posedge \coresync_clk + update \oper_r__data_len $0\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:141835.3-141836.57" + process $proc$libresoc.v:141835$6362 + assign { } { } + assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + sync posedge \coresync_clk + update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:141837.3-141838.55" + process $proc$libresoc.v:141837$6363 + assign { } { } + assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + sync posedge \coresync_clk + update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:141839.3-141840.51" + process $proc$libresoc.v:141839$6364 + assign { } { } + assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + sync posedge \coresync_clk + update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:141841.3-141842.41" + process $proc$libresoc.v:141841$6365 + assign { } { } + assign $0\oper_r__insn[31:0] \oper_r__insn$next + sync posedge \coresync_clk + update \oper_r__insn $0\oper_r__insn[31:0] + end + attribute \src "libresoc.v:141843.3-141844.39" + process $proc$libresoc.v:141843$6366 + assign { } { } + assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + sync posedge \coresync_clk + update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:141845.3-141846.39" + process $proc$libresoc.v:141845$6367 + assign { } { } + assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + sync posedge \coresync_clk + update \sto_l_r_sto $0\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:141847.3-141848.39" + process $proc$libresoc.v:141847$6368 + assign { } { } + assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + sync posedge \coresync_clk + update \upd_l_r_upd $0\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:141849.3-141850.39" + process $proc$libresoc.v:141849$6369 + assign { } { } + assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + sync posedge \coresync_clk + update \upd_l_s_upd $0\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:141851.3-141852.39" + process $proc$libresoc.v:141851$6370 + assign { } { } + assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + sync posedge \coresync_clk + update \wri_l_r_wri $0\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:141853.3-141854.39" + process $proc$libresoc.v:141853$6371 + assign { } { } + assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + sync posedge \coresync_clk + update \adr_l_r_adr $0\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:141855.3-141856.39" + process $proc$libresoc.v:141855$6372 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:141857.3-141858.39" + process $proc$libresoc.v:141857$6373 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:141859.3-141860.39" + process $proc$libresoc.v:141859$6374 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:141861.3-141862.39" + process $proc$libresoc.v:141861$6375 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:141863.3-141864.28" + process $proc$libresoc.v:141863$6376 + assign { } { } + assign $0\p_st_go[0:0] \cu_st__go_i + sync posedge \coresync_clk + update \p_st_go $0\p_st_go[0:0] + end + attribute \src "libresoc.v:141935.3-141943.6" + process $proc$libresoc.v:141935$6377 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6378 $1\opc_l_s_opc$next[0:0]$6379 + attribute \src "libresoc.v:141936.5-141936.29" + switch \initial + attribute \src "libresoc.v:141936.9-141936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6379 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6379 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6378 + end + attribute \src "libresoc.v:141944.3-141952.6" + process $proc$libresoc.v:141944$6380 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6381 $1\opc_l_r_opc$next[0:0]$6382 + attribute \src "libresoc.v:141945.5-141945.29" + switch \initial + attribute \src "libresoc.v:141945.9-141945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6382 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6382 \reset_o + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6381 + end + attribute \src "libresoc.v:141953.3-141961.6" + process $proc$libresoc.v:141953$6383 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6384 $1\src_l_s_src$next[2:0]$6385 + attribute \src "libresoc.v:141954.5-141954.29" + switch \initial + attribute \src "libresoc.v:141954.9-141954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6385 3'000 + case + assign $1\src_l_s_src$next[2:0]$6385 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6384 + end + attribute \src "libresoc.v:141962.3-141970.6" + process $proc$libresoc.v:141962$6386 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6387 $1\src_l_r_src$next[2:0]$6388 + attribute \src "libresoc.v:141963.5-141963.29" + switch \initial + attribute \src "libresoc.v:141963.9-141963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6388 3'111 + case + assign $1\src_l_r_src$next[2:0]$6388 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6387 + end + attribute \src "libresoc.v:141971.3-141979.6" + process $proc$libresoc.v:141971$6389 + assign { } { } + assign { } { } + assign $0\adr_l_r_adr$next[0:0]$6390 $1\adr_l_r_adr$next[0:0]$6391 + attribute \src "libresoc.v:141972.5-141972.29" + switch \initial + attribute \src "libresoc.v:141972.9-141972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adr_l_r_adr$next[0:0]$6391 1'1 + case + assign $1\adr_l_r_adr$next[0:0]$6391 \reset_a + end + sync always + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6390 + end + attribute \src "libresoc.v:141980.3-141988.6" + process $proc$libresoc.v:141980$6392 + assign { } { } + assign { } { } + assign $0\wri_l_r_wri$next[0:0]$6393 $1\wri_l_r_wri$next[0:0]$6394 + attribute \src "libresoc.v:141981.5-141981.29" + switch \initial + attribute \src "libresoc.v:141981.9-141981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wri_l_r_wri$next[0:0]$6394 1'1 + case + assign $1\wri_l_r_wri$next[0:0]$6394 \$38 [0] + end + sync always + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6393 + end + attribute \src "libresoc.v:141989.3-141997.6" + process $proc$libresoc.v:141989$6395 + assign { } { } + assign { } { } + assign $0\upd_l_s_upd$next[0:0]$6396 $1\upd_l_s_upd$next[0:0]$6397 + attribute \src "libresoc.v:141990.5-141990.29" + switch \initial + attribute \src "libresoc.v:141990.9-141990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_s_upd$next[0:0]$6397 1'0 + case + assign $1\upd_l_s_upd$next[0:0]$6397 \reset_i + end + sync always + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6396 + end + attribute \src "libresoc.v:141998.3-142006.6" + process $proc$libresoc.v:141998$6398 + assign { } { } + assign { } { } + assign $0\upd_l_r_upd$next[0:0]$6399 $1\upd_l_r_upd$next[0:0]$6400 + attribute \src "libresoc.v:141999.5-141999.29" + switch \initial + attribute \src "libresoc.v:141999.9-141999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_r_upd$next[0:0]$6400 1'1 + case + assign $1\upd_l_r_upd$next[0:0]$6400 \reset_u + end + sync always + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6399 + end + attribute \src "libresoc.v:142007.3-142015.6" + process $proc$libresoc.v:142007$6401 + assign { } { } + assign { } { } + assign $0\sto_l_r_sto$next[0:0]$6402 $1\sto_l_r_sto$next[0:0]$6403 + attribute \src "libresoc.v:142008.5-142008.29" + switch \initial + attribute \src "libresoc.v:142008.9-142008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sto_l_r_sto$next[0:0]$6403 1'1 + case + assign $1\sto_l_r_sto$next[0:0]$6403 \$59 + end + sync always + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6402 + end + attribute \src "libresoc.v:142016.3-142024.6" + process $proc$libresoc.v:142016$6404 + assign { } { } + assign { } { } + assign $0\lsd_l_r_lsd$next[0:0]$6405 $1\lsd_l_r_lsd$next[0:0]$6406 + attribute \src "libresoc.v:142017.5-142017.29" + switch \initial + attribute \src "libresoc.v:142017.9-142017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsd_l_r_lsd$next[0:0]$6406 1'1 + case + assign $1\lsd_l_r_lsd$next[0:0]$6406 \$63 + end + sync always + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6405 + end + attribute \src "libresoc.v:142025.3-142067.6" + process $proc$libresoc.v:142025$6407 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__byte_reverse$next[0:0]$6408 $2\oper_r__byte_reverse$next[0:0]$6440 + assign $0\oper_r__data_len$next[3:0]$6409 $2\oper_r__data_len$next[3:0]$6441 + assign $0\oper_r__fn_unit$next[13:0]$6410 $2\oper_r__fn_unit$next[13:0]$6442 + assign { } { } + assign { } { } + assign $0\oper_r__insn$next[31:0]$6413 $2\oper_r__insn$next[31:0]$6445 + assign $0\oper_r__insn_type$next[6:0]$6414 $2\oper_r__insn_type$next[6:0]$6446 + assign $0\oper_r__is_32bit$next[0:0]$6415 $2\oper_r__is_32bit$next[0:0]$6447 + assign $0\oper_r__is_signed$next[0:0]$6416 $2\oper_r__is_signed$next[0:0]$6448 + assign $0\oper_r__ldst_mode$next[1:0]$6417 $2\oper_r__ldst_mode$next[1:0]$6449 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__sign_extend$next[0:0]$6422 $2\oper_r__sign_extend$next[0:0]$6454 + assign $0\oper_r__zero_a$next[0:0]$6423 $2\oper_r__zero_a$next[0:0]$6455 + assign $0\oper_r__imm_data__data$next[63:0]$6411 $3\oper_r__imm_data__data$next[63:0]$6456 + assign $0\oper_r__imm_data__ok$next[0:0]$6412 $3\oper_r__imm_data__ok$next[0:0]$6457 + assign $0\oper_r__oe__oe$next[0:0]$6418 $3\oper_r__oe__oe$next[0:0]$6458 + assign $0\oper_r__oe__ok$next[0:0]$6419 $3\oper_r__oe__ok$next[0:0]$6459 + assign $0\oper_r__rc__ok$next[0:0]$6420 $3\oper_r__rc__ok$next[0:0]$6460 + assign $0\oper_r__rc__rc$next[0:0]$6421 $3\oper_r__rc__rc$next[0:0]$6461 + attribute \src "libresoc.v:142026.5-142026.29" + switch \initial + attribute \src "libresoc.v:142026.9-142026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\oper_r__insn$next[31:0]$6429 $1\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__data_len$next[3:0]$6425 $1\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__zero_a$next[0:0]$6439 $1\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__insn_type$next[6:0]$6430 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + case + assign $1\oper_r__byte_reverse$next[0:0]$6424 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6425 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6426 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6427 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6428 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6429 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6430 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6431 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6432 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6433 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6434 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6435 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6436 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6437 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6438 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6439 \oper_r__zero_a + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" + switch \cu_done_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\oper_r__insn$next[31:0]$6445 $2\oper_r__ldst_mode$next[1:0]$6449 $2\oper_r__sign_extend$next[0:0]$6454 $2\oper_r__byte_reverse$next[0:0]$6440 $2\oper_r__data_len$next[3:0]$6441 $2\oper_r__is_signed$next[0:0]$6448 $2\oper_r__is_32bit$next[0:0]$6447 $2\oper_r__oe__ok$next[0:0]$6451 $2\oper_r__oe__oe$next[0:0]$6450 $2\oper_r__rc__ok$next[0:0]$6452 $2\oper_r__rc__rc$next[0:0]$6453 $2\oper_r__zero_a$next[0:0]$6455 $2\oper_r__imm_data__ok$next[0:0]$6444 $2\oper_r__imm_data__data$next[63:0]$6443 $2\oper_r__fn_unit$next[13:0]$6442 $2\oper_r__insn_type$next[6:0]$6446 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\oper_r__byte_reverse$next[0:0]$6440 $1\oper_r__byte_reverse$next[0:0]$6424 + assign $2\oper_r__data_len$next[3:0]$6441 $1\oper_r__data_len$next[3:0]$6425 + assign $2\oper_r__fn_unit$next[13:0]$6442 $1\oper_r__fn_unit$next[13:0]$6426 + assign $2\oper_r__imm_data__data$next[63:0]$6443 $1\oper_r__imm_data__data$next[63:0]$6427 + assign $2\oper_r__imm_data__ok$next[0:0]$6444 $1\oper_r__imm_data__ok$next[0:0]$6428 + assign $2\oper_r__insn$next[31:0]$6445 $1\oper_r__insn$next[31:0]$6429 + assign $2\oper_r__insn_type$next[6:0]$6446 $1\oper_r__insn_type$next[6:0]$6430 + assign $2\oper_r__is_32bit$next[0:0]$6447 $1\oper_r__is_32bit$next[0:0]$6431 + assign $2\oper_r__is_signed$next[0:0]$6448 $1\oper_r__is_signed$next[0:0]$6432 + assign $2\oper_r__ldst_mode$next[1:0]$6449 $1\oper_r__ldst_mode$next[1:0]$6433 + assign $2\oper_r__oe__oe$next[0:0]$6450 $1\oper_r__oe__oe$next[0:0]$6434 + assign $2\oper_r__oe__ok$next[0:0]$6451 $1\oper_r__oe__ok$next[0:0]$6435 + assign $2\oper_r__rc__ok$next[0:0]$6452 $1\oper_r__rc__ok$next[0:0]$6436 + assign $2\oper_r__rc__rc$next[0:0]$6453 $1\oper_r__rc__rc$next[0:0]$6437 + assign $2\oper_r__sign_extend$next[0:0]$6454 $1\oper_r__sign_extend$next[0:0]$6438 + assign $2\oper_r__zero_a$next[0:0]$6455 $1\oper_r__zero_a$next[0:0]$6439 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\oper_r__imm_data__data$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6457 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6461 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6460 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6458 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6459 1'0 + case + assign $3\oper_r__imm_data__data$next[63:0]$6456 $2\oper_r__imm_data__data$next[63:0]$6443 + assign $3\oper_r__imm_data__ok$next[0:0]$6457 $2\oper_r__imm_data__ok$next[0:0]$6444 + assign $3\oper_r__oe__oe$next[0:0]$6458 $2\oper_r__oe__oe$next[0:0]$6450 + assign $3\oper_r__oe__ok$next[0:0]$6459 $2\oper_r__oe__ok$next[0:0]$6451 + assign $3\oper_r__rc__ok$next[0:0]$6460 $2\oper_r__rc__ok$next[0:0]$6452 + assign $3\oper_r__rc__rc$next[0:0]$6461 $2\oper_r__rc__rc$next[0:0]$6453 + end + sync always + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6408 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6409 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6410 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6411 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6412 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6413 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6414 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6415 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6416 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6417 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6418 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6419 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6420 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6421 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6422 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6423 + end + attribute \src "libresoc.v:142068.3-142077.6" + process $proc$libresoc.v:142068$6462 + assign { } { } + assign { } { } + assign $0\ldo_r$next[63:0]$6463 $1\ldo_r$next[63:0]$6464 + attribute \src "libresoc.v:142069.5-142069.29" + switch \initial + attribute \src "libresoc.v:142069.9-142069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \ld_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldo_r$next[63:0]$6464 \ldd_o + case + assign $1\ldo_r$next[63:0]$6464 \ldo_r + end + sync always + update \ldo_r$next $0\ldo_r$next[63:0]$6463 + end + attribute \src "libresoc.v:142078.3-142093.6" + process $proc$libresoc.v:142078$6465 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6466 $2\src_r0$next[63:0]$6468 + attribute \src "libresoc.v:142079.5-142079.29" + switch \initial + attribute \src "libresoc.v:142079.9-142079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6467 \src1_i + case + assign $1\src_r0$next[63:0]$6467 \src_r0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r0$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r0$next[63:0]$6468 $1\src_r0$next[63:0]$6467 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6466 + end + attribute \src "libresoc.v:142094.3-142109.6" + process $proc$libresoc.v:142094$6469 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6470 $2\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:142095.5-142095.29" + switch \initial + attribute \src "libresoc.v:142095.9-142095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6471 \src2_i + case + assign $1\src_r1$next[63:0]$6471 \src_r1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r1$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6471 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6470 + end + attribute \src "libresoc.v:142110.3-142125.6" + process $proc$libresoc.v:142110$6473 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$6474 $2\src_r2$next[63:0]$6476 + attribute \src "libresoc.v:142111.5-142111.29" + switch \initial + attribute \src "libresoc.v:142111.9-142111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$6475 \src3_i + case + assign $1\src_r2$next[63:0]$6475 \src_r2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r2$next[63:0]$6476 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r2$next[63:0]$6476 $1\src_r2$next[63:0]$6475 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$6474 + end + attribute \src "libresoc.v:142126.3-142135.6" + process $proc$libresoc.v:142126$6477 + assign { } { } + assign { } { } + assign $0\ea_r$next[63:0]$6478 $1\ea_r$next[63:0]$6479 + attribute \src "libresoc.v:142127.5-142127.29" + switch \initial + attribute \src "libresoc.v:142127.9-142127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \alu_l_q_alu + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ea_r$next[63:0]$6479 \alu_o + case + assign $1\ea_r$next[63:0]$6479 \ea_r + end + sync always + update \ea_r$next $0\ea_r$next[63:0]$6478 + end + attribute \src "libresoc.v:142136.3-142145.6" + process $proc$libresoc.v:142136$6480 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:142137.5-142137.29" + switch \initial + attribute \src "libresoc.v:142137.9-142137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" + switch \cu_wr__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \ldd_r + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:142146.3-142155.6" + process $proc$libresoc.v:142146$6481 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:142147.5-142147.29" + switch \initial + attribute \src "libresoc.v:142147.9-142147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + switch \$164 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \addr_r + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:142156.3-142164.6" + process $proc$libresoc.v:142156$6482 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$next[0:0]$6483 $1\ldst_port0_addr_i_ok$next[0:0]$6484 + attribute \src "libresoc.v:142157.5-142157.29" + switch \initial + attribute \src "libresoc.v:142157.9-142157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 1'0 + case + assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 \$177 + end + sync always + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6483 + end + attribute \src "libresoc.v:142165.3-142188.6" + process $proc$libresoc.v:142165$6485 + assign { } { } + assign { } { } + assign $0\lddata_r[63:0] $1\lddata_r[63:0] + attribute \src "libresoc.v:142166.5-142166.29" + switch \initial + attribute \src "libresoc.v:142166.9-142166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lddata_r[63:0] $2\lddata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\lddata_r[63:0] \$186 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\lddata_r[63:0] \$188 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\lddata_r[63:0] \$190 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + case + assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \lddata_r $0\lddata_r[63:0] + end + attribute \src "libresoc.v:142189.3-142200.6" + process $proc$libresoc.v:142189$6486 + assign { } { } + assign $0\revnorev[63:0] $1\revnorev[63:0] + attribute \src "libresoc.v:142190.5-142190.29" + switch \initial + attribute \src "libresoc.v:142190.9-142190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\revnorev[63:0] \lddata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\revnorev[63:0] \ldst_port0_ld_data_o + end + sync always + update \revnorev $0\revnorev[63:0] + end + attribute \src "libresoc.v:142201.3-142220.6" + process $proc$libresoc.v:142201$6487 + assign { } { } + assign $0\ldd_o[63:0] $1\ldd_o[63:0] + attribute \src "libresoc.v:142202.5-142202.29" + switch \initial + attribute \src "libresoc.v:142202.9-142202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" + switch \oper_r__sign_extend + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldd_o[63:0] $2\ldd_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + switch \$192 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldd_o[63:0] \revnorev + end + sync always + update \ldd_o $0\ldd_o[63:0] + end + attribute \src "libresoc.v:142221.3-142244.6" + process $proc$libresoc.v:142221$6488 + assign { } { } + assign { } { } + assign $0\stdata_r[63:0] $1\stdata_r[63:0] + attribute \src "libresoc.v:142222.5-142222.29" + switch \initial + attribute \src "libresoc.v:142222.9-142222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata_r[63:0] $2\stdata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\stdata_r[63:0] \$194 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\stdata_r[63:0] \$196 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\stdata_r[63:0] \$198 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + case + assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata_r $0\stdata_r[63:0] + end + attribute \src "libresoc.v:142245.3-142256.6" + process $proc$libresoc.v:142245$6489 + assign { } { } + assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:142246.5-142246.29" + switch \initial + attribute \src "libresoc.v:142246.9-142246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \stdata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \src_r2 + end + sync always + update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] + end + connect \$100 $and$libresoc.v:141704$6248_Y + connect \$102 $and$libresoc.v:141705$6249_Y + connect \$104 $and$libresoc.v:141706$6250_Y + connect \$106 $and$libresoc.v:141707$6251_Y + connect \$108 $and$libresoc.v:141708$6252_Y + connect \$10 $or$libresoc.v:141709$6253_Y + connect \$110 $and$libresoc.v:141710$6254_Y + connect \$112 $and$libresoc.v:141711$6255_Y + connect \$114 $and$libresoc.v:141712$6256_Y + connect \$116 $and$libresoc.v:141713$6257_Y + connect \$118 $and$libresoc.v:141714$6258_Y + connect \$120 $and$libresoc.v:141715$6259_Y + connect \$122 $and$libresoc.v:141716$6260_Y + connect \$124 $and$libresoc.v:141717$6261_Y + connect \$126 $eq$libresoc.v:141718$6262_Y + connect \$128 $and$libresoc.v:141719$6263_Y + connect \$12 $or$libresoc.v:141720$6264_Y + connect \$130 $and$libresoc.v:141721$6265_Y + connect \$132 $and$libresoc.v:141722$6266_Y + connect \$134 $or$libresoc.v:141723$6267_Y + connect \$136 $or$libresoc.v:141724$6268_Y + connect \$138 $or$libresoc.v:141725$6269_Y + connect \$140 $and$libresoc.v:141726$6270_Y + connect \$142 $and$libresoc.v:141727$6271_Y + connect \$145 $or$libresoc.v:141728$6272_Y + connect \$147 $or$libresoc.v:141729$6273_Y + connect \$144 $not$libresoc.v:141730$6274_Y + connect \$14 $or$libresoc.v:141731$6275_Y + connect \$150 $and$libresoc.v:141732$6276_Y + connect \$152 $or$libresoc.v:141733$6277_Y + connect \$154 $and$libresoc.v:141734$6278_Y + connect \$156 $not$libresoc.v:141735$6279_Y + connect \$158 $or$libresoc.v:141736$6280_Y + connect \$160 $and$libresoc.v:141737$6281_Y + connect \$162 $eq$libresoc.v:141738$6282_Y + connect \$164 $and$libresoc.v:141739$6283_Y + connect \$167 $eq$libresoc.v:141740$6284_Y + connect \$16 $or$libresoc.v:141741$6285_Y + connect \$169 $and$libresoc.v:141742$6286_Y + connect \$171 $and$libresoc.v:141743$6287_Y + connect \$173 $and$libresoc.v:141744$6288_Y + connect \$175 $pos$libresoc.v:141745$6290_Y + connect \$177 $and$libresoc.v:141746$6291_Y + connect \$186 $pos$libresoc.v:141747$6293_Y + connect \$188 $pos$libresoc.v:141748$6294_Y + connect \$18 $or$libresoc.v:141749$6295_Y + connect \$190 $pos$libresoc.v:141750$6296_Y + connect \$192 $eq$libresoc.v:141751$6297_Y + connect \$194 $pos$libresoc.v:141752$6299_Y + connect \$196 $pos$libresoc.v:141753$6300_Y + connect \$198 $pos$libresoc.v:141754$6301_Y + connect \$20 $or$libresoc.v:141755$6302_Y + connect \$22 $eq$libresoc.v:141756$6303_Y + connect \$24 $eq$libresoc.v:141757$6304_Y + connect \$26 $and$libresoc.v:141758$6305_Y + connect \$28 $and$libresoc.v:141759$6306_Y + connect \$30 $not$libresoc.v:141760$6307_Y + connect \$32 $and$libresoc.v:141761$6308_Y + connect \$34 $not$libresoc.v:141762$6309_Y + connect \$36 $and$libresoc.v:141763$6310_Y + connect \$39 $not$libresoc.v:141764$6311_Y + connect \$41 $eq$libresoc.v:141765$6312_Y + connect \$43 $and$libresoc.v:141766$6313_Y + connect \$45 $or$libresoc.v:141767$6314_Y + connect \$47 $not$libresoc.v:141768$6315_Y + connect \$49 $eq$libresoc.v:141769$6316_Y + connect \$51 $and$libresoc.v:141770$6317_Y + connect \$53 $or$libresoc.v:141771$6318_Y + connect \$55 $or$libresoc.v:141772$6319_Y + connect \$57 $and$libresoc.v:141773$6320_Y + connect \$59 $or$libresoc.v:141774$6321_Y + connect \$61 $or$libresoc.v:141775$6322_Y + connect \$63 $or$libresoc.v:141776$6323_Y + connect \$65 $ternary$libresoc.v:141777$6324_Y + connect \$67 $ternary$libresoc.v:141778$6325_Y + connect \$69 $ternary$libresoc.v:141779$6326_Y + connect \$71 $ternary$libresoc.v:141780$6327_Y + connect \$74 $add$libresoc.v:141781$6328_Y + connect \$76 $and$libresoc.v:141782$6329_Y + connect \$78 $not$libresoc.v:141783$6330_Y + connect \$80 $and$libresoc.v:141784$6331_Y + connect \$82 $not$libresoc.v:141785$6332_Y + connect \$84 $and$libresoc.v:141786$6333_Y + connect \$86 $and$libresoc.v:141787$6334_Y + connect \$88 $and$libresoc.v:141788$6335_Y + connect \$8 $or$libresoc.v:141789$6336_Y + connect \$90 $or$libresoc.v:141790$6337_Y + connect \$93 $or$libresoc.v:141791$6338_Y + connect \$92 $not$libresoc.v:141792$6339_Y + connect \$96 $and$libresoc.v:141793$6340_Y + connect \$98 $not$libresoc.v:141794$6341_Y + connect \$38 \$55 + connect \$73 \$74 + connect \$166 \$169 + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \ldst_port0_st_data_i_ok \cu_st__go_i + connect \ld_ok \ldst_port0_ld_data_o_ok + connect \addr_ok \ldst_port0_addr_ok_o + connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } + connect \ldst_port0_addr_i$next \$175 + connect \ldst_port0_data_len \oper_r__data_len + connect \ldst_port0_is_st_i \$173 + connect \ldst_port0_is_ld_i \$171 + connect \cu_wrmask_o \$169 [1:0] + connect \ea \dest2_o + connect \o \dest1_o + connect \cu_done_o \$160 + connect \wr_reset \$154 + connect \wr_any \$138 + connect \cu_wr__rel_o [1] \$132 + connect \cu_wr__rel_o [0] \$122 + connect \cu_st__rel_o \$112 + connect \cu_ad__rel_o \$104 + connect \rd_done \$100 + connect \alu_valid \$96 + connect \rda_any \$90 + connect \cu_rd__rel_o [2] \$88 + connect \cu_rd__rel_o [1:0] \$84 [1:0] + connect \cu_busy_o \opc_l_q_opc + connect \alu_ok$next \alu_valid + connect \alu_o \$74 [63:0] + connect \src2_or_imm \$71 + connect \src1_or_z \$69 + connect \addr_r \$67 + connect \ldd_r \$65 + connect \rst_l_r_rst \cu_issue_i + connect \rst_l_s_rst \addr_ok + connect \lsd_l_s_lsd \cu_issue_i + connect \sto_l_s_sto \$57 + connect \wri_l_s_wri \cu_issue_i + connect \lod_l_r_lod \ld_ok + connect \lod_l_s_lod \reset_i + connect \adr_l_s_adr \reset_i + connect \alu_l_r_alu \$36 + connect \alu_l_s_alu \reset_i + connect \st_o \op_is_st + connect \ld_o \op_is_ld + connect \stwd_mem_o \$28 + connect \load_mem_o \$26 + connect \op_is_ld \$24 + connect \op_is_st \$22 + connect \p_st_go$next \cu_st__go_i + connect \reset_a \$20 + connect \reset_r \$18 + connect \reset_s \$16 + connect \reset_u \$14 + connect \reset_w \$12 + connect \reset_o \$10 + connect \reset_i \$8 +end +attribute \src "libresoc.v:142320.1-142907.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +attribute \generator "nMigen" +module \left_mask + attribute \src "libresoc.v:142321.7-142321.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:142519.3-142906.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:142519.3-142906.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:142519.3-142906.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:142519.3-142906.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:142519.3-142906.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:142519.3-142906.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:142519.3-142906.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:142519.3-142906.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:142519.3-142906.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:142519.3-142906.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:142519.3-142906.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:142519.3-142906.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:142519.3-142906.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:142519.3-142906.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:142519.3-142906.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:142519.3-142906.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:142519.3-142906.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:142519.3-142906.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:142519.3-142906.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:142519.3-142906.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:142519.3-142906.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:142519.3-142906.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:142519.3-142906.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:142519.3-142906.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:142519.3-142906.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:142519.3-142906.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:142519.3-142906.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:142519.3-142906.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:142519.3-142906.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:142519.3-142906.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:142519.3-142906.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:142519.3-142906.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:142519.3-142906.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:142519.3-142906.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:142519.3-142906.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:142519.3-142906.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:142519.3-142906.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:142519.3-142906.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:142519.3-142906.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:142519.3-142906.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:142519.3-142906.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:142519.3-142906.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:142519.3-142906.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:142519.3-142906.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:142519.3-142906.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:142519.3-142906.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:142519.3-142906.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:142519.3-142906.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:142519.3-142906.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:142519.3-142906.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:142519.3-142906.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:142519.3-142906.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:142519.3-142906.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:142519.3-142906.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:142519.3-142906.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:142519.3-142906.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:142519.3-142906.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:142519.3-142906.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:142519.3-142906.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:142519.3-142906.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:142519.3-142906.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:142519.3-142906.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:142519.3-142906.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:142519.3-142906.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:142519.3-142906.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:142455.17-142455.96" + wire $gt$libresoc.v:142455$6526_Y + attribute \src "libresoc.v:142456.18-142456.98" + wire $gt$libresoc.v:142456$6527_Y + attribute \src "libresoc.v:142457.19-142457.99" + wire $gt$libresoc.v:142457$6528_Y + attribute \src "libresoc.v:142458.19-142458.99" + wire $gt$libresoc.v:142458$6529_Y + attribute \src "libresoc.v:142459.19-142459.99" + wire $gt$libresoc.v:142459$6530_Y + attribute \src "libresoc.v:142460.19-142460.99" + wire $gt$libresoc.v:142460$6531_Y + attribute \src "libresoc.v:142461.19-142461.99" + wire $gt$libresoc.v:142461$6532_Y + attribute \src "libresoc.v:142462.19-142462.99" + wire $gt$libresoc.v:142462$6533_Y + attribute \src "libresoc.v:142463.19-142463.99" + wire $gt$libresoc.v:142463$6534_Y + attribute \src "libresoc.v:142464.19-142464.99" + wire $gt$libresoc.v:142464$6535_Y + attribute \src "libresoc.v:142465.19-142465.99" + wire $gt$libresoc.v:142465$6536_Y + attribute \src "libresoc.v:142466.18-142466.97" + wire $gt$libresoc.v:142466$6537_Y + attribute \src "libresoc.v:142467.19-142467.99" + wire $gt$libresoc.v:142467$6538_Y + attribute \src "libresoc.v:142468.19-142468.99" + wire $gt$libresoc.v:142468$6539_Y + attribute \src "libresoc.v:142469.19-142469.99" + wire $gt$libresoc.v:142469$6540_Y + attribute \src "libresoc.v:142470.19-142470.99" + wire $gt$libresoc.v:142470$6541_Y + attribute \src "libresoc.v:142471.19-142471.99" + wire $gt$libresoc.v:142471$6542_Y + attribute \src "libresoc.v:142472.18-142472.97" + wire $gt$libresoc.v:142472$6543_Y + attribute \src "libresoc.v:142473.18-142473.97" + wire $gt$libresoc.v:142473$6544_Y + attribute \src "libresoc.v:142474.18-142474.97" + wire $gt$libresoc.v:142474$6545_Y + attribute \src "libresoc.v:142475.17-142475.96" + wire $gt$libresoc.v:142475$6546_Y + attribute \src "libresoc.v:142476.18-142476.97" + wire $gt$libresoc.v:142476$6547_Y + attribute \src "libresoc.v:142477.18-142477.97" + wire $gt$libresoc.v:142477$6548_Y + attribute \src "libresoc.v:142478.18-142478.97" + wire $gt$libresoc.v:142478$6549_Y + attribute \src "libresoc.v:142479.18-142479.97" + wire $gt$libresoc.v:142479$6550_Y + attribute \src "libresoc.v:142480.18-142480.97" + wire $gt$libresoc.v:142480$6551_Y + attribute \src "libresoc.v:142481.18-142481.97" + wire $gt$libresoc.v:142481$6552_Y + attribute \src "libresoc.v:142482.18-142482.97" + wire $gt$libresoc.v:142482$6553_Y + attribute \src "libresoc.v:142483.18-142483.98" + wire $gt$libresoc.v:142483$6554_Y + attribute \src "libresoc.v:142484.18-142484.98" + wire $gt$libresoc.v:142484$6555_Y + attribute \src "libresoc.v:142485.18-142485.98" + wire $gt$libresoc.v:142485$6556_Y + attribute \src "libresoc.v:142486.17-142486.96" + wire $gt$libresoc.v:142486$6557_Y + attribute \src "libresoc.v:142487.18-142487.98" + wire $gt$libresoc.v:142487$6558_Y + attribute \src "libresoc.v:142488.18-142488.98" + wire $gt$libresoc.v:142488$6559_Y + attribute \src "libresoc.v:142489.18-142489.98" + wire $gt$libresoc.v:142489$6560_Y + attribute \src "libresoc.v:142490.18-142490.98" + wire $gt$libresoc.v:142490$6561_Y + attribute \src "libresoc.v:142491.18-142491.98" + wire $gt$libresoc.v:142491$6562_Y + attribute \src "libresoc.v:142492.18-142492.98" + wire $gt$libresoc.v:142492$6563_Y + attribute \src "libresoc.v:142493.18-142493.98" + wire $gt$libresoc.v:142493$6564_Y + attribute \src "libresoc.v:142494.18-142494.98" + wire $gt$libresoc.v:142494$6565_Y + attribute \src "libresoc.v:142495.18-142495.98" + wire $gt$libresoc.v:142495$6566_Y + attribute \src "libresoc.v:142496.18-142496.98" + wire $gt$libresoc.v:142496$6567_Y + attribute \src "libresoc.v:142497.17-142497.96" + wire $gt$libresoc.v:142497$6568_Y + attribute \src "libresoc.v:142498.18-142498.98" + wire $gt$libresoc.v:142498$6569_Y + attribute \src "libresoc.v:142499.18-142499.98" + wire $gt$libresoc.v:142499$6570_Y + attribute \src "libresoc.v:142500.18-142500.98" + wire $gt$libresoc.v:142500$6571_Y + attribute \src "libresoc.v:142501.18-142501.98" + wire $gt$libresoc.v:142501$6572_Y + attribute \src "libresoc.v:142502.18-142502.98" + wire $gt$libresoc.v:142502$6573_Y + attribute \src "libresoc.v:142503.18-142503.98" + wire $gt$libresoc.v:142503$6574_Y + attribute \src "libresoc.v:142504.18-142504.98" + wire $gt$libresoc.v:142504$6575_Y + attribute \src "libresoc.v:142505.18-142505.98" + wire $gt$libresoc.v:142505$6576_Y + attribute \src "libresoc.v:142506.18-142506.98" + wire $gt$libresoc.v:142506$6577_Y + attribute \src "libresoc.v:142507.18-142507.98" + wire $gt$libresoc.v:142507$6578_Y + attribute \src "libresoc.v:142508.17-142508.96" + wire $gt$libresoc.v:142508$6579_Y + attribute \src "libresoc.v:142509.18-142509.98" + wire $gt$libresoc.v:142509$6580_Y + attribute \src "libresoc.v:142510.18-142510.98" + wire $gt$libresoc.v:142510$6581_Y + attribute \src "libresoc.v:142511.18-142511.98" + wire $gt$libresoc.v:142511$6582_Y + attribute \src "libresoc.v:142512.18-142512.98" + wire $gt$libresoc.v:142512$6583_Y + attribute \src "libresoc.v:142513.18-142513.98" + wire $gt$libresoc.v:142513$6584_Y + attribute \src "libresoc.v:142514.18-142514.98" + wire $gt$libresoc.v:142514$6585_Y + attribute \src "libresoc.v:142515.18-142515.98" + wire $gt$libresoc.v:142515$6586_Y + attribute \src "libresoc.v:142516.18-142516.98" + wire $gt$libresoc.v:142516$6587_Y + attribute \src "libresoc.v:142517.18-142517.98" + wire $gt$libresoc.v:142517$6588_Y + attribute \src "libresoc.v:142518.18-142518.98" + wire $gt$libresoc.v:142518$6589_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$99 + attribute \src "libresoc.v:142321.7-142321.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142455$6526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:142455$6526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142456$6527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:142456$6527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142457$6528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:142457$6528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142458$6529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:142458$6529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142459$6530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:142459$6530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142460$6531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:142460$6531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142461$6532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:142461$6532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142462$6533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:142462$6533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142463$6534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:142463$6534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142464$6535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:142464$6535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142465$6536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:142465$6536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142466$6537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:142466$6537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142467$6538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:142467$6538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142468$6539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:142468$6539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142469$6540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:142469$6540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142470$6541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:142470$6541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142471$6542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:142471$6542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142472$6543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:142472$6543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142473$6544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:142473$6544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142474$6545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:142474$6545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142475$6546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:142475$6546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142476$6547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:142476$6547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142477$6548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:142477$6548_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142478$6549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:142478$6549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142479$6550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:142479$6550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142480$6551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:142480$6551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142481$6552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:142481$6552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142482$6553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:142482$6553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142483$6554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:142483$6554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142484$6555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:142484$6555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142485$6556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:142485$6556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142486$6557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:142486$6557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142487$6558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:142487$6558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142488$6559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:142488$6559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142489$6560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:142489$6560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142490$6561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:142490$6561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142491$6562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:142491$6562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142492$6563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:142492$6563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142493$6564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:142493$6564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142494$6565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:142494$6565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142495$6566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:142495$6566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142496$6567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:142496$6567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142497$6568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$libresoc.v:142497$6568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142498$6569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:142498$6569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142499$6570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:142499$6570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142500$6571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:142500$6571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142501$6572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:142501$6572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142502$6573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:142502$6573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142503$6574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:142503$6574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142504$6575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:142504$6575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142505$6576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:142505$6576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142506$6577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:142506$6577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142507$6578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:142507$6578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142508$6579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:142508$6579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142509$6580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:142509$6580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142510$6581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:142510$6581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142511$6582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:142511$6582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142512$6583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:142512$6583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142513$6584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:142513$6584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142514$6585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:142514$6585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142515$6586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:142515$6586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142516$6587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:142516$6587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142517$6588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:142517$6588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:142518$6589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:142518$6589_Y + end + attribute \src "libresoc.v:142321.7-142321.20" + process $proc$libresoc.v:142321$6591 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:142519.3-142906.6" + process $proc$libresoc.v:142519$6590 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:142520.5-142520.29" + switch \initial + attribute \src "libresoc.v:142520.9-142520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:142455$6526_Y + connect \$99 $gt$libresoc.v:142456$6527_Y + connect \$101 $gt$libresoc.v:142457$6528_Y + connect \$103 $gt$libresoc.v:142458$6529_Y + connect \$105 $gt$libresoc.v:142459$6530_Y + connect \$107 $gt$libresoc.v:142460$6531_Y + connect \$109 $gt$libresoc.v:142461$6532_Y + connect \$111 $gt$libresoc.v:142462$6533_Y + connect \$113 $gt$libresoc.v:142463$6534_Y + connect \$115 $gt$libresoc.v:142464$6535_Y + connect \$117 $gt$libresoc.v:142465$6536_Y + connect \$11 $gt$libresoc.v:142466$6537_Y + connect \$119 $gt$libresoc.v:142467$6538_Y + connect \$121 $gt$libresoc.v:142468$6539_Y + connect \$123 $gt$libresoc.v:142469$6540_Y + connect \$125 $gt$libresoc.v:142470$6541_Y + connect \$127 $gt$libresoc.v:142471$6542_Y + connect \$13 $gt$libresoc.v:142472$6543_Y + connect \$15 $gt$libresoc.v:142473$6544_Y + connect \$17 $gt$libresoc.v:142474$6545_Y + connect \$1 $gt$libresoc.v:142475$6546_Y + connect \$19 $gt$libresoc.v:142476$6547_Y + connect \$21 $gt$libresoc.v:142477$6548_Y + connect \$23 $gt$libresoc.v:142478$6549_Y + connect \$25 $gt$libresoc.v:142479$6550_Y + connect \$27 $gt$libresoc.v:142480$6551_Y + connect \$29 $gt$libresoc.v:142481$6552_Y + connect \$31 $gt$libresoc.v:142482$6553_Y + connect \$33 $gt$libresoc.v:142483$6554_Y + connect \$35 $gt$libresoc.v:142484$6555_Y + connect \$37 $gt$libresoc.v:142485$6556_Y + connect \$3 $gt$libresoc.v:142486$6557_Y + connect \$39 $gt$libresoc.v:142487$6558_Y + connect \$41 $gt$libresoc.v:142488$6559_Y + connect \$43 $gt$libresoc.v:142489$6560_Y + connect \$45 $gt$libresoc.v:142490$6561_Y + connect \$47 $gt$libresoc.v:142491$6562_Y + connect \$49 $gt$libresoc.v:142492$6563_Y + connect \$51 $gt$libresoc.v:142493$6564_Y + connect \$53 $gt$libresoc.v:142494$6565_Y + connect \$55 $gt$libresoc.v:142495$6566_Y + connect \$57 $gt$libresoc.v:142496$6567_Y + connect \$5 $gt$libresoc.v:142497$6568_Y + connect \$59 $gt$libresoc.v:142498$6569_Y + connect \$61 $gt$libresoc.v:142499$6570_Y + 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"/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 4 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $extend$libresoc.v:142935$6595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$7 + connect \Y $extend$libresoc.v:142935$6595_Y + end + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $sub$libresoc.v:142933$6593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 21 + connect \A \$2 + connect \B 1'1 + connect \Y $sub$libresoc.v:142933$6593_Y + end + connect \$2 $sshl$libresoc.v:142932$6592_Y + connect \$4 $sub$libresoc.v:142933$6593_Y + connect \$7 $sshl$libresoc.v:142934$6594_Y + connect \$6 $pos$libresoc.v:142935$6596_Y + connect \$1 \$4 + connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } + connect \lexp_o \$6 + connect \binlen \$4 [16:0] +end +attribute \src "libresoc.v:142944.1-143002.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" +attribute \generator "nMigen" +module \lod_l + attribute \src "libresoc.v:142945.7-142945.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:142990.3-142998.6" + wire $0\q_int$next[0:0]$6607 + attribute \src "libresoc.v:142988.3-142989.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:142990.3-142998.6" + wire $1\q_int$next[0:0]$6608 + attribute \src "libresoc.v:142967.7-142967.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:142980.17-142980.96" + wire $and$libresoc.v:142980$6597_Y + attribute \src "libresoc.v:142985.17-142985.96" + wire $and$libresoc.v:142985$6602_Y + attribute \src "libresoc.v:142982.18-142982.93" + wire $not$libresoc.v:142982$6599_Y + attribute \src "libresoc.v:142984.17-142984.92" + wire $not$libresoc.v:142984$6601_Y + attribute \src "libresoc.v:142987.17-142987.92" + wire $not$libresoc.v:142987$6604_Y + attribute \src "libresoc.v:142981.18-142981.98" + wire $or$libresoc.v:142981$6598_Y + attribute \src "libresoc.v:142983.18-142983.99" + wire $or$libresoc.v:142983$6600_Y + attribute \src "libresoc.v:142986.17-142986.97" + wire $or$libresoc.v:142986$6603_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:142945.7-142945.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:142980$6597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:142980$6597_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:142985$6602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:142985$6602_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:142982$6599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \Y $not$libresoc.v:142982$6599_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:142984$6601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:142984$6601_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:142987$6604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:142987$6604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:142981$6598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lod + connect \Y $or$libresoc.v:142981$6598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:142983$6600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \B \q_int + connect \Y $or$libresoc.v:142983$6600_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:142986$6603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lod + connect \Y $or$libresoc.v:142986$6603_Y + end + attribute \src "libresoc.v:142945.7-142945.20" + process $proc$libresoc.v:142945$6609 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:142967.7-142967.19" + process $proc$libresoc.v:142967$6610 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:142988.3-142989.27" + process $proc$libresoc.v:142988$6605 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:142990.3-142998.6" + process $proc$libresoc.v:142990$6606 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6607 $1\q_int$next[0:0]$6608 + attribute \src "libresoc.v:142991.5-142991.29" + switch \initial + attribute \src "libresoc.v:142991.9-142991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6608 1'0 + case + assign $1\q_int$next[0:0]$6608 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6607 + end + connect \$9 $and$libresoc.v:142980$6597_Y + connect \$11 $or$libresoc.v:142981$6598_Y + connect \$13 $not$libresoc.v:142982$6599_Y + connect \$15 $or$libresoc.v:142983$6600_Y + connect \$1 $not$libresoc.v:142984$6601_Y + connect \$3 $and$libresoc.v:142985$6602_Y + connect \$5 $or$libresoc.v:142986$6603_Y + connect \$7 $not$libresoc.v:142987$6604_Y + connect \qlq_lod \$15 + connect \qn_lod \$13 + connect \q_lod \$11 +end +attribute \src "libresoc.v:143006.1-144126.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" +attribute \generator "nMigen" +module \logical0 + attribute \src "libresoc.v:143751.3-143752.24" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:143749.3-143750.44" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:144056.3-144064.6" + wire $0\alu_l_r_alu$next[0:0]$6811 + attribute \src "libresoc.v:143673.3-143674.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6740 + attribute \src "libresoc.v:143723.3-143724.83" + wire width 4 $0\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 + attribute \src "libresoc.v:143693.3-143694.81" + wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 + attribute \src "libresoc.v:143695.3-143696.95" + wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 + attribute \src "libresoc.v:143697.3-143698.91" + wire $0\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 + attribute \src "libresoc.v:143711.3-143712.89" + wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6745 + attribute \src "libresoc.v:143725.3-143726.75" + wire width 32 $0\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 + attribute \src "libresoc.v:143691.3-143692.85" + wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 + attribute \src "libresoc.v:143707.3-143708.85" + wire $0\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 + attribute \src "libresoc.v:143713.3-143714.87" + wire $0\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 + attribute \src "libresoc.v:143719.3-143720.83" + wire $0\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 + attribute \src "libresoc.v:143721.3-143722.85" + wire $0\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 + attribute \src "libresoc.v:143703.3-143704.79" + wire $0\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 + attribute \src "libresoc.v:143705.3-143706.79" + wire $0\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 + attribute \src "libresoc.v:143717.3-143718.91" + wire $0\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 + attribute \src "libresoc.v:143701.3-143702.79" + wire $0\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 + attribute \src "libresoc.v:143699.3-143700.79" + wire $0\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 + attribute \src "libresoc.v:143715.3-143716.85" + wire $0\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 + attribute \src "libresoc.v:143709.3-143710.79" + wire $0\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:144047.3-144055.6" + wire $0\alui_l_r_alui$next[0:0]$6808 + attribute \src "libresoc.v:143675.3-143676.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $0\data_r0__o$next[63:0]$6783 + attribute \src "libresoc.v:143687.3-143688.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:143973.3-143994.6" + wire $0\data_r0__o_ok$next[0:0]$6784 + attribute \src "libresoc.v:143689.3-143690.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6791 + attribute \src "libresoc.v:143683.3-143684.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:143995.3-144016.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6792 + attribute \src "libresoc.v:143685.3-143686.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:144065.3-144074.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:144075.3-144084.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:143007.7-143007.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143889.3-143897.6" + wire $0\opc_l_r_opc$next[0:0]$6725 + attribute \src "libresoc.v:143735.3-143736.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:143880.3-143888.6" + wire $0\opc_l_s_opc$next[0:0]$6722 + attribute \src "libresoc.v:143737.3-143738.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:144085.3-144093.6" + wire width 2 $0\prev_wr_go$next[1:0]$6816 + attribute \src "libresoc.v:143747.3-143748.37" + wire width 2 $0\prev_wr_go[1:0] + attribute \src "libresoc.v:143834.3-143843.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:143925.3-143933.6" + wire width 2 $0\req_l_r_req$next[1:0]$6737 + attribute \src "libresoc.v:143727.3-143728.39" + wire width 2 $0\req_l_r_req[1:0] + attribute \src "libresoc.v:143916.3-143924.6" + wire width 2 $0\req_l_s_req$next[1:0]$6734 + attribute \src "libresoc.v:143729.3-143730.39" + wire width 2 $0\req_l_s_req[1:0] + attribute \src "libresoc.v:143853.3-143861.6" + wire $0\rok_l_r_rdok$next[0:0]$6713 + attribute \src "libresoc.v:143743.3-143744.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:143844.3-143852.6" + wire $0\rok_l_s_rdok$next[0:0]$6710 + attribute \src "libresoc.v:143745.3-143746.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:143871.3-143879.6" + wire $0\rst_l_r_rst$next[0:0]$6719 + attribute \src "libresoc.v:143739.3-143740.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:143862.3-143870.6" + wire $0\rst_l_s_rst$next[0:0]$6716 + attribute \src "libresoc.v:143741.3-143742.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:143907.3-143915.6" + wire width 3 $0\src_l_r_src$next[2:0]$6731 + attribute \src "libresoc.v:143731.3-143732.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:143898.3-143906.6" + wire width 3 $0\src_l_s_src$next[2:0]$6728 + attribute \src "libresoc.v:143733.3-143734.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:144017.3-144026.6" + wire width 64 $0\src_r0$next[63:0]$6799 + attribute \src "libresoc.v:143681.3-143682.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:144027.3-144036.6" + wire width 64 $0\src_r1$next[63:0]$6802 + attribute \src "libresoc.v:143679.3-143680.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:144037.3-144046.6" + wire $0\src_r2$next[0:0]$6805 + attribute \src "libresoc.v:143677.3-143678.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:143125.7-143125.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:143135.7-143135.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:144056.3-144064.6" + wire $1\alu_l_r_alu$next[0:0]$6812 + attribute \src "libresoc.v:143143.7-143143.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 + attribute \src "libresoc.v:143151.13-143151.53" + wire width 4 $1\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 + attribute \src "libresoc.v:143170.14-143170.57" + wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + attribute \src "libresoc.v:143174.14-143174.76" + wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + attribute \src "libresoc.v:143178.7-143178.51" + wire $1\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 + attribute \src "libresoc.v:143186.13-143186.56" + wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6763 + attribute \src "libresoc.v:143190.14-143190.51" + wire width 32 $1\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 + attribute \src "libresoc.v:143269.13-143269.55" + wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 + attribute \src "libresoc.v:143273.7-143273.48" + wire $1\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 + attribute \src "libresoc.v:143277.7-143277.49" + wire $1\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 + attribute \src "libresoc.v:143281.7-143281.47" + wire $1\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 + attribute \src "libresoc.v:143285.7-143285.48" + wire $1\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 + attribute \src "libresoc.v:143289.7-143289.45" + wire $1\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 + attribute \src "libresoc.v:143293.7-143293.45" + wire $1\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 + attribute \src "libresoc.v:143297.7-143297.51" + wire $1\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 + attribute \src "libresoc.v:143301.7-143301.45" + wire $1\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 + attribute \src "libresoc.v:143305.7-143305.45" + wire $1\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 + attribute \src "libresoc.v:143309.7-143309.48" + wire $1\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 + attribute \src "libresoc.v:143313.7-143313.45" + wire $1\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:144047.3-144055.6" + wire $1\alui_l_r_alui$next[0:0]$6809 + attribute \src "libresoc.v:143339.7-143339.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $1\data_r0__o$next[63:0]$6785 + attribute \src "libresoc.v:143373.14-143373.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:143973.3-143994.6" + wire $1\data_r0__o_ok$next[0:0]$6786 + attribute \src "libresoc.v:143377.7-143377.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6793 + attribute \src "libresoc.v:143381.13-143381.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:143995.3-144016.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6794 + attribute \src "libresoc.v:143385.7-143385.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:144065.3-144074.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:144075.3-144084.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:143889.3-143897.6" + wire $1\opc_l_r_opc$next[0:0]$6726 + attribute \src "libresoc.v:143399.7-143399.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:143880.3-143888.6" + wire $1\opc_l_s_opc$next[0:0]$6723 + attribute \src "libresoc.v:143403.7-143403.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:144085.3-144093.6" + wire width 2 $1\prev_wr_go$next[1:0]$6817 + attribute \src "libresoc.v:143537.13-143537.30" + wire width 2 $1\prev_wr_go[1:0] + attribute \src "libresoc.v:143834.3-143843.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:143925.3-143933.6" + wire width 2 $1\req_l_r_req$next[1:0]$6738 + attribute \src "libresoc.v:143545.13-143545.31" + wire width 2 $1\req_l_r_req[1:0] + attribute \src "libresoc.v:143916.3-143924.6" + wire width 2 $1\req_l_s_req$next[1:0]$6735 + attribute \src "libresoc.v:143549.13-143549.31" + wire width 2 $1\req_l_s_req[1:0] + attribute \src "libresoc.v:143853.3-143861.6" + wire $1\rok_l_r_rdok$next[0:0]$6714 + attribute \src "libresoc.v:143561.7-143561.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:143844.3-143852.6" + wire $1\rok_l_s_rdok$next[0:0]$6711 + attribute \src "libresoc.v:143565.7-143565.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:143871.3-143879.6" + wire $1\rst_l_r_rst$next[0:0]$6720 + attribute \src "libresoc.v:143569.7-143569.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:143862.3-143870.6" + wire $1\rst_l_s_rst$next[0:0]$6717 + attribute \src "libresoc.v:143573.7-143573.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:143907.3-143915.6" + wire width 3 $1\src_l_r_src$next[2:0]$6732 + attribute \src "libresoc.v:143587.13-143587.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:143898.3-143906.6" + wire width 3 $1\src_l_s_src$next[2:0]$6729 + attribute \src "libresoc.v:143591.13-143591.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:144017.3-144026.6" + wire width 64 $1\src_r0$next[63:0]$6800 + attribute \src "libresoc.v:143599.14-143599.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:144027.3-144036.6" + wire width 64 $1\src_r1$next[63:0]$6803 + attribute \src "libresoc.v:143603.14-143603.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:144037.3-144046.6" + wire $1\src_r2$next[0:0]$6806 + attribute \src "libresoc.v:143607.7-143607.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $2\data_r0__o$next[63:0]$6787 + attribute \src "libresoc.v:143973.3-143994.6" + wire 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\alu_logical0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_logical0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_logical0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_logical0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_logical0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_logical0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_logical0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 2 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "libresoc.v:143007.7-143007.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:143651$6646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:143651$6646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:143652$6647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:143652$6647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:143653$6648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:143653$6648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:143656$6651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:143656$6651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:143657$6652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$4 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:143657$6652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:143663$6658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \Y $reduce_and$libresoc.v:143663$6658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:143634$6629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \Y $reduce_or$libresoc.v:143634$6629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:143637$6632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:143637$6632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:143638$6633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:143638$6633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:143660$6655 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:143660$6655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:143661$6656 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:143661$6656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:143662$6657 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:143662$6657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:143664$6659 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:143664$6659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:143665$6660 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:143665$6660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:143666$6661 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $ternary$libresoc.v:143666$6661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:143667$6662 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:143667$6662_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143753.14-143759.4" + cell \alu_l$61 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143760.16-143792.4" + cell \alu_logical0 \alu_logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_logical0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \n_ready_i \alu_logical0_n_ready_i + connect \n_valid_o \alu_logical0_n_valid_o + connect \o \alu_logical0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_logical0_p_ready_o + connect \p_valid_i \alu_logical0_p_valid_i + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143793.15-143799.4" + cell \alui_l$60 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143800.14-143806.4" + cell \opc_l$56 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143807.14-143813.4" + cell \req_l$57 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143814.14-143820.4" + cell \rok_l$59 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143821.14-143826.4" + cell \rst_l$58 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143827.14-143833.4" + cell \src_l$55 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:143007.7-143007.20" + process $proc$libresoc.v:143007$6818 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143125.7-143125.24" + process $proc$libresoc.v:143125$6819 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:143135.7-143135.26" + process $proc$libresoc.v:143135$6820 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:143143.7-143143.25" + process $proc$libresoc.v:143143$6821 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:143151.13-143151.53" + process $proc$libresoc.v:143151$6822 + assign { } { } + assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:143170.14-143170.57" + process $proc$libresoc.v:143170$6823 + assign { } { } + assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:143174.14-143174.76" + process $proc$libresoc.v:143174$6824 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:143178.7-143178.51" + process $proc$libresoc.v:143178$6825 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:143186.13-143186.56" + process $proc$libresoc.v:143186$6826 + assign { } { } + assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:143190.14-143190.51" + process $proc$libresoc.v:143190$6827 + assign { } { } + assign $1\alu_logical0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:143269.13-143269.55" + process $proc$libresoc.v:143269$6828 + assign { } { } + assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:143273.7-143273.48" + process $proc$libresoc.v:143273$6829 + assign { } { } + assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:143277.7-143277.49" + process $proc$libresoc.v:143277$6830 + assign { } { } + assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:143281.7-143281.47" + process $proc$libresoc.v:143281$6831 + assign { } { } + assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:143285.7-143285.48" + process $proc$libresoc.v:143285$6832 + assign { } { } + assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:143289.7-143289.45" + process $proc$libresoc.v:143289$6833 + assign { } { } + assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:143293.7-143293.45" + process $proc$libresoc.v:143293$6834 + assign { } { } + assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:143297.7-143297.51" + process $proc$libresoc.v:143297$6835 + assign { } { } + assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:143301.7-143301.45" + process $proc$libresoc.v:143301$6836 + assign { } { } + assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:143305.7-143305.45" + process $proc$libresoc.v:143305$6837 + assign { } { } + assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:143309.7-143309.48" + process $proc$libresoc.v:143309$6838 + assign { } { } + assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:143313.7-143313.45" + process $proc$libresoc.v:143313$6839 + assign { } { } + assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:143339.7-143339.27" + process $proc$libresoc.v:143339$6840 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:143373.14-143373.47" + process $proc$libresoc.v:143373$6841 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:143377.7-143377.27" + process $proc$libresoc.v:143377$6842 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:143381.13-143381.33" + process $proc$libresoc.v:143381$6843 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:143385.7-143385.30" + process $proc$libresoc.v:143385$6844 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:143399.7-143399.25" + process $proc$libresoc.v:143399$6845 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:143403.7-143403.25" + process $proc$libresoc.v:143403$6846 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:143537.13-143537.30" + process $proc$libresoc.v:143537$6847 + assign { } { } + assign $1\prev_wr_go[1:0] 2'00 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[1:0] + end + attribute \src "libresoc.v:143545.13-143545.31" + process $proc$libresoc.v:143545$6848 + assign { } { } + assign $1\req_l_r_req[1:0] 2'11 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[1:0] + end + attribute \src "libresoc.v:143549.13-143549.31" + process $proc$libresoc.v:143549$6849 + assign { } { } + assign $1\req_l_s_req[1:0] 2'00 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[1:0] + end + attribute \src "libresoc.v:143561.7-143561.26" + process $proc$libresoc.v:143561$6850 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:143565.7-143565.26" + process $proc$libresoc.v:143565$6851 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:143569.7-143569.25" + process $proc$libresoc.v:143569$6852 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:143573.7-143573.25" + process $proc$libresoc.v:143573$6853 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:143587.13-143587.31" + process $proc$libresoc.v:143587$6854 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:143591.13-143591.31" + process $proc$libresoc.v:143591$6855 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:143599.14-143599.43" + process $proc$libresoc.v:143599$6856 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:143603.14-143603.43" + process $proc$libresoc.v:143603$6857 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:143607.7-143607.20" + process $proc$libresoc.v:143607$6858 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:143673.3-143674.39" + process $proc$libresoc.v:143673$6668 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:143675.3-143676.43" + process $proc$libresoc.v:143675$6669 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:143677.3-143678.29" + process $proc$libresoc.v:143677$6670 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:143679.3-143680.29" + process $proc$libresoc.v:143679$6671 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:143681.3-143682.29" + process $proc$libresoc.v:143681$6672 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:143683.3-143684.43" + process $proc$libresoc.v:143683$6673 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:143685.3-143686.49" + process $proc$libresoc.v:143685$6674 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:143687.3-143688.37" + process $proc$libresoc.v:143687$6675 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:143689.3-143690.43" + process $proc$libresoc.v:143689$6676 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:143691.3-143692.85" + process $proc$libresoc.v:143691$6677 + assign { } { } + assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:143693.3-143694.81" + process $proc$libresoc.v:143693$6678 + assign { } { } + assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:143695.3-143696.95" + process $proc$libresoc.v:143695$6679 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:143697.3-143698.91" + process $proc$libresoc.v:143697$6680 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:143699.3-143700.79" + process $proc$libresoc.v:143699$6681 + assign { } { } + assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:143701.3-143702.79" + process $proc$libresoc.v:143701$6682 + assign { } { } + assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:143703.3-143704.79" + process $proc$libresoc.v:143703$6683 + assign { } { } + assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:143705.3-143706.79" + process $proc$libresoc.v:143705$6684 + assign { } { } + assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:143707.3-143708.85" + process $proc$libresoc.v:143707$6685 + assign { } { } + assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:143709.3-143710.79" + process $proc$libresoc.v:143709$6686 + assign { } { } + assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:143711.3-143712.89" + process $proc$libresoc.v:143711$6687 + assign { } { } + assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:143713.3-143714.87" + process $proc$libresoc.v:143713$6688 + assign { } { } + assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:143715.3-143716.85" + process $proc$libresoc.v:143715$6689 + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:143717.3-143718.91" + process $proc$libresoc.v:143717$6690 + assign { } { } + assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:143719.3-143720.83" + process $proc$libresoc.v:143719$6691 + assign { } { } + assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:143721.3-143722.85" + process $proc$libresoc.v:143721$6692 + assign { } { } + assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:143723.3-143724.83" + process $proc$libresoc.v:143723$6693 + assign { } { } + assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:143725.3-143726.75" + process $proc$libresoc.v:143725$6694 + assign { } { } + assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:143727.3-143728.39" + process $proc$libresoc.v:143727$6695 + assign { } { } + assign $0\req_l_r_req[1:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[1:0] + end + attribute \src "libresoc.v:143729.3-143730.39" + process $proc$libresoc.v:143729$6696 + assign { } { } + assign $0\req_l_s_req[1:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[1:0] + end + attribute \src "libresoc.v:143731.3-143732.39" + process $proc$libresoc.v:143731$6697 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:143733.3-143734.39" + process $proc$libresoc.v:143733$6698 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:143735.3-143736.39" + process $proc$libresoc.v:143735$6699 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:143737.3-143738.39" + process $proc$libresoc.v:143737$6700 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:143739.3-143740.39" + process $proc$libresoc.v:143739$6701 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:143741.3-143742.39" + process $proc$libresoc.v:143741$6702 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:143743.3-143744.41" + process $proc$libresoc.v:143743$6703 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:143745.3-143746.41" + process $proc$libresoc.v:143745$6704 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:143747.3-143748.37" + process $proc$libresoc.v:143747$6705 + assign { } { } + assign $0\prev_wr_go[1:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[1:0] + end + attribute \src "libresoc.v:143749.3-143750.44" + process $proc$libresoc.v:143749$6706 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:143751.3-143752.24" + process $proc$libresoc.v:143751$6707 + assign { } { } + assign $0\all_rd_dly[0:0] \$9 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:143834.3-143843.6" + process $proc$libresoc.v:143834$6708 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:143835.5-143835.29" + switch \initial + attribute \src "libresoc.v:143835.9-143835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$45 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:143844.3-143852.6" + process $proc$libresoc.v:143844$6709 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$6710 $1\rok_l_s_rdok$next[0:0]$6711 + attribute \src "libresoc.v:143845.5-143845.29" + switch \initial + attribute \src "libresoc.v:143845.9-143845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$6711 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$6711 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6710 + end + attribute \src "libresoc.v:143853.3-143861.6" + process $proc$libresoc.v:143853$6712 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$6713 $1\rok_l_r_rdok$next[0:0]$6714 + attribute \src "libresoc.v:143854.5-143854.29" + switch \initial + attribute \src "libresoc.v:143854.9-143854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$6714 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$6714 \$63 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6713 + end + attribute \src "libresoc.v:143862.3-143870.6" + process $proc$libresoc.v:143862$6715 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$6716 $1\rst_l_s_rst$next[0:0]$6717 + attribute \src "libresoc.v:143863.5-143863.29" + switch \initial + attribute \src "libresoc.v:143863.9-143863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$6717 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$6717 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6716 + end + attribute \src "libresoc.v:143871.3-143879.6" + process $proc$libresoc.v:143871$6718 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$6719 $1\rst_l_r_rst$next[0:0]$6720 + attribute \src "libresoc.v:143872.5-143872.29" + switch \initial + attribute \src "libresoc.v:143872.9-143872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$6720 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$6720 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6719 + end + attribute \src "libresoc.v:143880.3-143888.6" + process $proc$libresoc.v:143880$6721 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6722 $1\opc_l_s_opc$next[0:0]$6723 + attribute \src "libresoc.v:143881.5-143881.29" + switch \initial + attribute \src "libresoc.v:143881.9-143881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6723 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6723 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6722 + end + attribute \src "libresoc.v:143889.3-143897.6" + process $proc$libresoc.v:143889$6724 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6725 $1\opc_l_r_opc$next[0:0]$6726 + attribute \src "libresoc.v:143890.5-143890.29" + switch \initial + attribute \src "libresoc.v:143890.9-143890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6726 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6726 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6725 + end + attribute \src "libresoc.v:143898.3-143906.6" + process $proc$libresoc.v:143898$6727 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6728 $1\src_l_s_src$next[2:0]$6729 + attribute \src "libresoc.v:143899.5-143899.29" + switch \initial + attribute \src "libresoc.v:143899.9-143899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6729 3'000 + case + assign $1\src_l_s_src$next[2:0]$6729 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6728 + end + attribute \src "libresoc.v:143907.3-143915.6" + process $proc$libresoc.v:143907$6730 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6731 $1\src_l_r_src$next[2:0]$6732 + attribute \src "libresoc.v:143908.5-143908.29" + switch \initial + attribute \src "libresoc.v:143908.9-143908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6732 3'111 + case + assign $1\src_l_r_src$next[2:0]$6732 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6731 + end + attribute \src "libresoc.v:143916.3-143924.6" + process $proc$libresoc.v:143916$6733 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[1:0]$6734 $1\req_l_s_req$next[1:0]$6735 + attribute \src "libresoc.v:143917.5-143917.29" + switch \initial + attribute \src "libresoc.v:143917.9-143917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[1:0]$6735 2'00 + case + assign $1\req_l_s_req$next[1:0]$6735 \$65 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6734 + end + attribute \src "libresoc.v:143925.3-143933.6" + process $proc$libresoc.v:143925$6736 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[1:0]$6737 $1\req_l_r_req$next[1:0]$6738 + attribute \src "libresoc.v:143926.5-143926.29" + switch \initial + attribute \src "libresoc.v:143926.9-143926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[1:0]$6738 2'11 + case + assign $1\req_l_r_req$next[1:0]$6738 \$67 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6737 + end + attribute \src "libresoc.v:143934.3-143972.6" + process $proc$libresoc.v:143934$6739 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6740 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6745 $1\alu_logical0_logical_op__insn$next[31:0]$6763 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 + attribute \src "libresoc.v:143935.5-143935.29" + switch \initial + attribute \src "libresoc.v:143935.9-143935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6763 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + case + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6758 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6763 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 \alu_logical0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 1'0 + case + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 + end + sync always + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6740 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6745 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 + end + attribute \src "libresoc.v:143973.3-143994.6" + process $proc$libresoc.v:143973$6782 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$6783 $2\data_r0__o$next[63:0]$6787 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$6784 $3\data_r0__o_ok$next[0:0]$6789 + attribute \src "libresoc.v:143974.5-143974.29" + switch \initial + attribute \src "libresoc.v:143974.9-143974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$6786 $1\data_r0__o$next[63:0]$6785 } { \o_ok \alu_logical0_o } + case + assign $1\data_r0__o$next[63:0]$6785 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6786 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$6788 $2\data_r0__o$next[63:0]$6787 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$6787 $1\data_r0__o$next[63:0]$6785 + assign $2\data_r0__o_ok$next[0:0]$6788 $1\data_r0__o_ok$next[0:0]$6786 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$6789 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$6789 $2\data_r0__o_ok$next[0:0]$6788 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$6783 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6784 + end + attribute \src "libresoc.v:143995.3-144016.6" + process $proc$libresoc.v:143995$6790 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$6791 $2\data_r1__cr_a$next[3:0]$6795 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$6792 $3\data_r1__cr_a_ok$next[0:0]$6797 + attribute \src "libresoc.v:143996.5-143996.29" + switch \initial + attribute \src "libresoc.v:143996.9-143996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$6794 $1\data_r1__cr_a$next[3:0]$6793 } { \cr_a_ok \alu_logical0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$6793 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6794 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$6796 $2\data_r1__cr_a$next[3:0]$6795 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$6795 $1\data_r1__cr_a$next[3:0]$6793 + assign $2\data_r1__cr_a_ok$next[0:0]$6796 $1\data_r1__cr_a_ok$next[0:0]$6794 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$6797 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$6797 $2\data_r1__cr_a_ok$next[0:0]$6796 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6791 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6792 + end + attribute \src "libresoc.v:144017.3-144026.6" + process $proc$libresoc.v:144017$6798 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6799 $1\src_r0$next[63:0]$6800 + attribute \src "libresoc.v:144018.5-144018.29" + switch \initial + attribute \src "libresoc.v:144018.9-144018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6800 \src_or_imm + case + assign $1\src_r0$next[63:0]$6800 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6799 + end + attribute \src "libresoc.v:144027.3-144036.6" + process $proc$libresoc.v:144027$6801 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6802 $1\src_r1$next[63:0]$6803 + attribute \src "libresoc.v:144028.5-144028.29" + switch \initial + attribute \src "libresoc.v:144028.9-144028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6803 \src_or_imm$80 + case + assign $1\src_r1$next[63:0]$6803 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6802 + end + attribute \src "libresoc.v:144037.3-144046.6" + process $proc$libresoc.v:144037$6804 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$6805 $1\src_r2$next[0:0]$6806 + attribute \src "libresoc.v:144038.5-144038.29" + switch \initial + attribute \src "libresoc.v:144038.9-144038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$6806 \src3_i + case + assign $1\src_r2$next[0:0]$6806 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$6805 + end + attribute \src "libresoc.v:144047.3-144055.6" + process $proc$libresoc.v:144047$6807 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$6808 $1\alui_l_r_alui$next[0:0]$6809 + attribute \src "libresoc.v:144048.5-144048.29" + switch \initial + attribute \src "libresoc.v:144048.9-144048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$6809 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$6809 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6808 + end + attribute \src "libresoc.v:144056.3-144064.6" + process $proc$libresoc.v:144056$6810 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$6811 $1\alu_l_r_alu$next[0:0]$6812 + attribute \src "libresoc.v:144057.5-144057.29" + switch \initial + attribute \src "libresoc.v:144057.9-144057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$6812 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$6812 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6811 + end + attribute \src "libresoc.v:144065.3-144074.6" + process $proc$libresoc.v:144065$6813 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:144066.5-144066.29" + switch \initial + attribute \src "libresoc.v:144066.9-144066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:144075.3-144084.6" + process $proc$libresoc.v:144075$6814 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:144076.5-144076.29" + switch \initial + attribute \src "libresoc.v:144076.9-144076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:144085.3-144093.6" + process $proc$libresoc.v:144085$6815 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[1:0]$6816 $1\prev_wr_go$next[1:0]$6817 + attribute \src "libresoc.v:144086.5-144086.29" + switch \initial + attribute \src "libresoc.v:144086.9-144086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[1:0]$6817 2'00 + case + assign $1\prev_wr_go$next[1:0]$6817 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6816 + end + connect \$9 $and$libresoc.v:143616$6611_Y + connect \$99 $and$libresoc.v:143617$6612_Y + connect \$101 $not$libresoc.v:143618$6613_Y + connect \$103 $and$libresoc.v:143619$6614_Y + connect \$105 $and$libresoc.v:143620$6615_Y + connect \$107 $and$libresoc.v:143621$6616_Y + connect \$109 $and$libresoc.v:143622$6617_Y + connect \$111 $and$libresoc.v:143623$6618_Y + connect \$113 $and$libresoc.v:143624$6619_Y + connect \$115 $and$libresoc.v:143625$6620_Y + connect \$11 $not$libresoc.v:143626$6621_Y + connect \$13 $and$libresoc.v:143627$6622_Y + connect \$15 $not$libresoc.v:143628$6623_Y + connect \$17 $and$libresoc.v:143629$6624_Y + connect \$1 $and$libresoc.v:143630$6625_Y + connect \$19 $and$libresoc.v:143631$6626_Y + connect \$23 $not$libresoc.v:143632$6627_Y + connect \$25 $and$libresoc.v:143633$6628_Y + connect \$22 $reduce_or$libresoc.v:143634$6629_Y + connect \$21 $not$libresoc.v:143635$6630_Y + connect \$29 $and$libresoc.v:143636$6631_Y + connect \$31 $reduce_or$libresoc.v:143637$6632_Y + connect \$33 $reduce_or$libresoc.v:143638$6633_Y + connect \$35 $or$libresoc.v:143639$6634_Y + connect \$37 $not$libresoc.v:143640$6635_Y + connect \$39 $and$libresoc.v:143641$6636_Y + connect \$41 $and$libresoc.v:143642$6637_Y + connect \$43 $eq$libresoc.v:143643$6638_Y + connect \$45 $and$libresoc.v:143644$6639_Y + connect \$47 $eq$libresoc.v:143645$6640_Y + connect \$4 $not$libresoc.v:143646$6641_Y + connect \$49 $and$libresoc.v:143647$6642_Y + connect \$51 $and$libresoc.v:143648$6643_Y + connect \$53 $and$libresoc.v:143649$6644_Y + connect \$55 $or$libresoc.v:143650$6645_Y + connect \$57 $or$libresoc.v:143651$6646_Y + connect \$59 $or$libresoc.v:143652$6647_Y + connect \$61 $or$libresoc.v:143653$6648_Y + connect \$63 $and$libresoc.v:143654$6649_Y + connect \$65 $and$libresoc.v:143655$6650_Y + connect \$67 $or$libresoc.v:143656$6651_Y + connect \$6 $or$libresoc.v:143657$6652_Y + connect \$69 $and$libresoc.v:143658$6653_Y + connect \$71 $and$libresoc.v:143659$6654_Y + connect \$73 $ternary$libresoc.v:143660$6655_Y + connect \$75 $ternary$libresoc.v:143661$6656_Y + connect \$78 $ternary$libresoc.v:143662$6657_Y + connect \$3 $reduce_and$libresoc.v:143663$6658_Y + connect \$81 $ternary$libresoc.v:143664$6659_Y + connect \$83 $ternary$libresoc.v:143665$6660_Y + connect \$85 $ternary$libresoc.v:143666$6661_Y + connect \$87 $ternary$libresoc.v:143667$6662_Y + connect \$89 $and$libresoc.v:143668$6663_Y + connect \$91 $and$libresoc.v:143669$6664_Y + connect \$93 $and$libresoc.v:143670$6665_Y + connect \$95 $not$libresoc.v:143671$6666_Y + connect \$97 $not$libresoc.v:143672$6667_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$111 + connect \cu_rd__rel_o \$103 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_logical0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_logical0_p_valid_i \alui_l_q_alui + connect \alu_logical0_xer_so \$87 + connect \alu_logical0_rb \$85 + connect \alu_logical0_ra \$83 + connect \src_or_imm$80 \$81 + connect \src_sel$77 \$78 + connect \src_or_imm \$75 + connect \src_sel \$73 + connect \cu_wrmask_o { \$71 \$69 } + connect \reset_r \$61 + connect \reset_w \$59 + connect \rst_r \$57 + connect \reset \$55 + connect \wr_any \$35 + connect \cu_done_o \$29 + connect \alu_pulsem { \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$17 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_logical0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$13 + connect \all_rd_dly$next \all_rd + connect \all_rd \$9 +end +attribute \src "libresoc.v:144130.1-145521.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" +attribute \generator "nMigen" +module \logical_pipe1 + attribute \src "libresoc.v:145460.3-145478.6" + wire width 4 $0\cr_a$next[3:0]$6943 + attribute \src "libresoc.v:145220.3-145221.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:145460.3-145478.6" + wire $0\cr_a_ok$next[0:0]$6944 + attribute \src "libresoc.v:145222.3-145223.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:144131.7-144131.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6894 + attribute \src "libresoc.v:145260.3-145261.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6895 + attribute \src "libresoc.v:145230.3-145231.55" + wire width 14 $0\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6896 + attribute \src "libresoc.v:145232.3-145233.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6897 + attribute \src "libresoc.v:145234.3-145235.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6898 + attribute \src "libresoc.v:145248.3-145249.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 32 $0\logical_op__insn$next[31:0]$6899 + attribute \src "libresoc.v:145262.3-145263.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6900 + attribute \src "libresoc.v:145228.3-145229.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__invert_in$next[0:0]$6901 + attribute \src "libresoc.v:145244.3-145245.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__invert_out$next[0:0]$6902 + attribute \src "libresoc.v:145250.3-145251.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__is_32bit$next[0:0]$6903 + attribute \src "libresoc.v:145256.3-145257.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__is_signed$next[0:0]$6904 + attribute \src "libresoc.v:145258.3-145259.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__oe__oe$next[0:0]$6905 + attribute \src "libresoc.v:145240.3-145241.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__oe__ok$next[0:0]$6906 + attribute \src "libresoc.v:145242.3-145243.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__output_carry$next[0:0]$6907 + attribute \src "libresoc.v:145254.3-145255.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__rc__ok$next[0:0]$6908 + attribute \src "libresoc.v:145238.3-145239.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__rc__rc$next[0:0]$6909 + attribute \src "libresoc.v:145236.3-145237.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__write_cr0$next[0:0]$6910 + attribute \src "libresoc.v:145252.3-145253.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__zero_a$next[0:0]$6911 + attribute \src "libresoc.v:145246.3-145247.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:145386.3-145398.6" + wire width 2 $0\muxid$next[1:0]$6891 + attribute \src "libresoc.v:145264.3-145265.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:145441.3-145459.6" + wire width 64 $0\o$next[63:0]$6937 + attribute \src "libresoc.v:145224.3-145225.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:145441.3-145459.6" + wire $0\o_ok$next[0:0]$6938 + attribute \src "libresoc.v:145226.3-145227.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:145368.3-145385.6" + wire $0\r_busy$next[0:0]$6887 + attribute \src "libresoc.v:145266.3-145267.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:145479.3-145497.6" + wire $0\xer_so$next[0:0]$6949 + attribute \src "libresoc.v:145216.3-145217.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:145479.3-145497.6" + wire $0\xer_so_ok$next[0:0]$6950 + attribute \src "libresoc.v:145218.3-145219.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:145460.3-145478.6" + wire width 4 $1\cr_a$next[3:0]$6945 + attribute \src "libresoc.v:144140.13-144140.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:145460.3-145478.6" + wire $1\cr_a_ok$next[0:0]$6946 + attribute \src "libresoc.v:144149.7-144149.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6912 + attribute \src "libresoc.v:144434.13-144434.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6913 + attribute \src "libresoc.v:144458.14-144458.44" + wire width 14 $1\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6914 + attribute \src "libresoc.v:144497.14-144497.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6915 + attribute \src "libresoc.v:144506.7-144506.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6916 + attribute \src "libresoc.v:144519.13-144519.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 32 $1\logical_op__insn$next[31:0]$6917 + attribute \src "libresoc.v:144536.14-144536.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6918 + attribute \src "libresoc.v:144620.13-144620.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__invert_in$next[0:0]$6919 + attribute \src "libresoc.v:144779.7-144779.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__invert_out$next[0:0]$6920 + attribute \src "libresoc.v:144788.7-144788.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__is_32bit$next[0:0]$6921 + attribute \src "libresoc.v:144797.7-144797.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__is_signed$next[0:0]$6922 + attribute \src "libresoc.v:144806.7-144806.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__oe__oe$next[0:0]$6923 + attribute \src "libresoc.v:144815.7-144815.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__oe__ok$next[0:0]$6924 + attribute \src "libresoc.v:144824.7-144824.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__output_carry$next[0:0]$6925 + attribute \src "libresoc.v:144833.7-144833.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__rc__ok$next[0:0]$6926 + attribute \src "libresoc.v:144842.7-144842.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__rc__rc$next[0:0]$6927 + attribute \src "libresoc.v:144851.7-144851.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__write_cr0$next[0:0]$6928 + attribute \src "libresoc.v:144860.7-144860.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__zero_a$next[0:0]$6929 + attribute \src "libresoc.v:144869.7-144869.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:145386.3-145398.6" + wire width 2 $1\muxid$next[1:0]$6892 + attribute \src "libresoc.v:145154.13-145154.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:145441.3-145459.6" + wire width 64 $1\o$next[63:0]$6939 + attribute \src "libresoc.v:145169.14-145169.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:145441.3-145459.6" + wire $1\o_ok$next[0:0]$6940 + attribute \src "libresoc.v:145176.7-145176.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:145368.3-145385.6" + wire $1\r_busy$next[0:0]$6888 + attribute \src "libresoc.v:145190.7-145190.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:145479.3-145497.6" + wire $1\xer_so$next[0:0]$6951 + attribute \src "libresoc.v:145199.7-145199.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:145479.3-145497.6" + wire $1\xer_so_ok$next[0:0]$6952 + attribute \src "libresoc.v:145208.7-145208.23" + wire $1\xer_so_ok[0:0] + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 53 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:144131.7-144131.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute 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"ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + 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\enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 33 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 42 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$60 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_logical_op__fn_unit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok$47 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 52 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:145215$6859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$63 + connect \B \p_ready_o + connect \Y $and$libresoc.v:145215$6859_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145268.14-145313.4" + cell \input$50 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$38 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$39 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$20 \input_ra$40 + connect \rb \input_rb + connect \rb$21 \input_rb$41 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145314.13-145359.4" + cell \main$51 \main + connect \logical_op__data_len \main_logical_op__data_len + connect \logical_op__data_len$18 \main_logical_op__data_len$60 + connect \logical_op__fn_unit \main_logical_op__fn_unit + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 + connect \logical_op__imm_data__data \main_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 + connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 + connect \logical_op__input_carry \main_logical_op__input_carry + connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 + connect \logical_op__insn \main_logical_op__insn + connect \logical_op__insn$19 \main_logical_op__insn$61 + connect \logical_op__insn_type \main_logical_op__insn_type + connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 + connect \logical_op__invert_in \main_logical_op__invert_in + connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 + connect \logical_op__invert_out \main_logical_op__invert_out + connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 + connect \logical_op__is_32bit \main_logical_op__is_32bit + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok \main_logical_op__oe__ok + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__rc__ok \main_logical_op__rc__ok + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$43 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_so$20 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145360.10-145363.4" + cell \n$49 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145364.10-145367.4" + cell \p$48 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:144131.7-144131.20" + process $proc$libresoc.v:144131$6954 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:144140.13-144140.24" + process $proc$libresoc.v:144140$6955 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:144149.7-144149.21" + process $proc$libresoc.v:144149$6956 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:144434.13-144434.40" + process $proc$libresoc.v:144434$6957 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:144458.14-144458.44" + process $proc$libresoc.v:144458$6958 + assign { } { } + assign $1\logical_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:144497.14-144497.63" + process $proc$libresoc.v:144497$6959 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:144506.7-144506.38" + process $proc$libresoc.v:144506$6960 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:144519.13-144519.43" + process $proc$libresoc.v:144519$6961 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:144536.14-144536.38" + process $proc$libresoc.v:144536$6962 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:144620.13-144620.42" + process $proc$libresoc.v:144620$6963 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:144779.7-144779.35" + process $proc$libresoc.v:144779$6964 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:144788.7-144788.36" + process $proc$libresoc.v:144788$6965 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:144797.7-144797.34" + process $proc$libresoc.v:144797$6966 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:144806.7-144806.35" + process $proc$libresoc.v:144806$6967 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:144815.7-144815.32" + process $proc$libresoc.v:144815$6968 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:144824.7-144824.32" + process $proc$libresoc.v:144824$6969 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:144833.7-144833.38" + process $proc$libresoc.v:144833$6970 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:144842.7-144842.32" + process $proc$libresoc.v:144842$6971 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:144851.7-144851.32" + process $proc$libresoc.v:144851$6972 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:144860.7-144860.35" + process $proc$libresoc.v:144860$6973 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:144869.7-144869.32" + process $proc$libresoc.v:144869$6974 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:145154.13-145154.25" + process $proc$libresoc.v:145154$6975 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:145169.14-145169.38" + process $proc$libresoc.v:145169$6976 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:145176.7-145176.18" + process $proc$libresoc.v:145176$6977 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:145190.7-145190.20" + process $proc$libresoc.v:145190$6978 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:145199.7-145199.20" + process $proc$libresoc.v:145199$6979 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:145208.7-145208.23" + process $proc$libresoc.v:145208$6980 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:145216.3-145217.29" + process $proc$libresoc.v:145216$6860 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:145218.3-145219.35" + process $proc$libresoc.v:145218$6861 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:145220.3-145221.25" + process $proc$libresoc.v:145220$6862 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:145222.3-145223.31" + process $proc$libresoc.v:145222$6863 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:145224.3-145225.19" + process $proc$libresoc.v:145224$6864 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:145226.3-145227.25" + process $proc$libresoc.v:145226$6865 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:145228.3-145229.59" + process $proc$libresoc.v:145228$6866 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:145230.3-145231.55" + process $proc$libresoc.v:145230$6867 + assign { } { } + assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:145232.3-145233.69" + process $proc$libresoc.v:145232$6868 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:145234.3-145235.65" + process $proc$libresoc.v:145234$6869 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:145236.3-145237.53" + process $proc$libresoc.v:145236$6870 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:145238.3-145239.53" + process $proc$libresoc.v:145238$6871 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:145240.3-145241.53" + process $proc$libresoc.v:145240$6872 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:145242.3-145243.53" + process $proc$libresoc.v:145242$6873 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:145244.3-145245.59" + process $proc$libresoc.v:145244$6874 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:145246.3-145247.53" + process $proc$libresoc.v:145246$6875 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:145248.3-145249.63" + process $proc$libresoc.v:145248$6876 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:145250.3-145251.61" + process $proc$libresoc.v:145250$6877 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:145252.3-145253.59" + process $proc$libresoc.v:145252$6878 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:145254.3-145255.65" + process $proc$libresoc.v:145254$6879 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:145256.3-145257.57" + process $proc$libresoc.v:145256$6880 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:145258.3-145259.59" + process $proc$libresoc.v:145258$6881 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:145260.3-145261.57" + process $proc$libresoc.v:145260$6882 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:145262.3-145263.49" + process $proc$libresoc.v:145262$6883 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:145264.3-145265.27" + process $proc$libresoc.v:145264$6884 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:145266.3-145267.29" + process $proc$libresoc.v:145266$6885 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:145368.3-145385.6" + process $proc$libresoc.v:145368$6886 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6887 $2\r_busy$next[0:0]$6889 + attribute \src "libresoc.v:145369.5-145369.29" + switch \initial + attribute \src "libresoc.v:145369.9-145369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6888 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6888 1'0 + case + assign $1\r_busy$next[0:0]$6888 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6889 1'0 + case + assign $2\r_busy$next[0:0]$6889 $1\r_busy$next[0:0]$6888 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6887 + end + attribute \src "libresoc.v:145386.3-145398.6" + process $proc$libresoc.v:145386$6890 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$6891 $1\muxid$next[1:0]$6892 + attribute \src "libresoc.v:145387.5-145387.29" + switch \initial + attribute \src "libresoc.v:145387.9-145387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$6892 \muxid$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$6892 \muxid$66 + case + assign $1\muxid$next[1:0]$6892 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$6891 + end + attribute \src "libresoc.v:145399.3-145440.6" + process $proc$libresoc.v:145399$6893 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$6894 $1\logical_op__data_len$next[3:0]$6912 + assign $0\logical_op__fn_unit$next[13:0]$6895 $1\logical_op__fn_unit$next[13:0]$6913 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$6898 $1\logical_op__input_carry$next[1:0]$6916 + assign $0\logical_op__insn$next[31:0]$6899 $1\logical_op__insn$next[31:0]$6917 + assign $0\logical_op__insn_type$next[6:0]$6900 $1\logical_op__insn_type$next[6:0]$6918 + assign $0\logical_op__invert_in$next[0:0]$6901 $1\logical_op__invert_in$next[0:0]$6919 + assign $0\logical_op__invert_out$next[0:0]$6902 $1\logical_op__invert_out$next[0:0]$6920 + assign $0\logical_op__is_32bit$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6921 + assign $0\logical_op__is_signed$next[0:0]$6904 $1\logical_op__is_signed$next[0:0]$6922 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$6907 $1\logical_op__output_carry$next[0:0]$6925 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$6910 $1\logical_op__write_cr0$next[0:0]$6928 + assign $0\logical_op__zero_a$next[0:0]$6911 $1\logical_op__zero_a$next[0:0]$6929 + assign $0\logical_op__imm_data__data$next[63:0]$6896 $2\logical_op__imm_data__data$next[63:0]$6930 + assign $0\logical_op__imm_data__ok$next[0:0]$6897 $2\logical_op__imm_data__ok$next[0:0]$6931 + assign $0\logical_op__oe__oe$next[0:0]$6905 $2\logical_op__oe__oe$next[0:0]$6932 + assign $0\logical_op__oe__ok$next[0:0]$6906 $2\logical_op__oe__ok$next[0:0]$6933 + assign $0\logical_op__rc__ok$next[0:0]$6908 $2\logical_op__rc__ok$next[0:0]$6934 + assign $0\logical_op__rc__rc$next[0:0]$6909 $2\logical_op__rc__rc$next[0:0]$6935 + attribute \src "libresoc.v:145400.5-145400.29" + switch \initial + attribute \src "libresoc.v:145400.9-145400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + case + assign $1\logical_op__data_len$next[3:0]$6912 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6913 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6914 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6915 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6916 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6917 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6918 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6919 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6920 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6921 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6922 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6923 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6924 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6925 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6926 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6927 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6928 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6929 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6931 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6935 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6934 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6932 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6933 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$6930 $1\logical_op__imm_data__data$next[63:0]$6914 + assign $2\logical_op__imm_data__ok$next[0:0]$6931 $1\logical_op__imm_data__ok$next[0:0]$6915 + assign $2\logical_op__oe__oe$next[0:0]$6932 $1\logical_op__oe__oe$next[0:0]$6923 + assign $2\logical_op__oe__ok$next[0:0]$6933 $1\logical_op__oe__ok$next[0:0]$6924 + assign $2\logical_op__rc__ok$next[0:0]$6934 $1\logical_op__rc__ok$next[0:0]$6926 + assign $2\logical_op__rc__rc$next[0:0]$6935 $1\logical_op__rc__rc$next[0:0]$6927 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6894 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6895 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6896 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6897 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6898 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6899 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6900 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6901 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6902 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6903 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6904 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6905 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6906 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6907 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6908 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6909 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6910 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6911 + end + attribute \src "libresoc.v:145441.3-145459.6" + process $proc$libresoc.v:145441$6936 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$6937 $1\o$next[63:0]$6939 + assign { } { } + assign $0\o_ok$next[0:0]$6938 $2\o_ok$next[0:0]$6941 + attribute \src "libresoc.v:145442.5-145442.29" + switch \initial + attribute \src "libresoc.v:145442.9-145442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$6939 \o + assign $1\o_ok$next[0:0]$6940 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$6941 1'0 + case + assign $2\o_ok$next[0:0]$6941 $1\o_ok$next[0:0]$6940 + end + sync always + update \o$next $0\o$next[63:0]$6937 + update \o_ok$next $0\o_ok$next[0:0]$6938 + end + attribute \src "libresoc.v:145460.3-145478.6" + process $proc$libresoc.v:145460$6942 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$6943 $1\cr_a$next[3:0]$6945 + assign { } { } + assign $0\cr_a_ok$next[0:0]$6944 $2\cr_a_ok$next[0:0]$6947 + attribute \src "libresoc.v:145461.5-145461.29" + switch \initial + attribute \src "libresoc.v:145461.9-145461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$6945 \cr_a + assign $1\cr_a_ok$next[0:0]$6946 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$6947 1'0 + case + assign $2\cr_a_ok$next[0:0]$6947 $1\cr_a_ok$next[0:0]$6946 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$6943 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6944 + end + attribute \src "libresoc.v:145479.3-145497.6" + process $proc$libresoc.v:145479$6948 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$6949 $1\xer_so$next[0:0]$6951 + assign { } { } + assign $0\xer_so_ok$next[0:0]$6950 $2\xer_so_ok$next[0:0]$6953 + attribute \src "libresoc.v:145480.5-145480.29" + switch \initial + attribute \src "libresoc.v:145480.9-145480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$6951 \xer_so + assign $1\xer_so_ok$next[0:0]$6952 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$6953 1'0 + case + assign $2\xer_so_ok$next[0:0]$6953 $1\xer_so_ok$next[0:0]$6952 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$6949 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6950 + end + connect \$64 $and$libresoc.v:145215$6859_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + connect \muxid$66 \main_muxid$43 + connect \p_valid_i_p_ready_o \$64 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$63 \p_valid_i + connect \main_xer_so \input_xer_so$42 + connect \main_rb \input_rb$41 + connect \main_ra \input_ra$40 + connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:145525.1-146558.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \generator "nMigen" +module \logical_pipe2 + attribute \src "libresoc.v:146525.3-146543.6" + wire width 4 $0\cr_a$22$next[3:0]$7086 + attribute \src "libresoc.v:146329.3-146330.33" + wire width 4 $0\cr_a$22[3:0]$6983 + attribute \src "libresoc.v:145537.13-145537.29" + wire width 4 $0\cr_a$22[3:0]$7093 + attribute \src "libresoc.v:146525.3-146543.6" + wire $0\cr_a_ok$23$next[0:0]$7087 + attribute \src "libresoc.v:146331.3-146332.39" + wire $0\cr_a_ok$23[0:0]$6985 + attribute \src "libresoc.v:145546.7-145546.26" + wire $0\cr_a_ok$23[0:0]$7095 + attribute \src "libresoc.v:145526.7-145526.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146464.3-146505.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$7037 + attribute \src "libresoc.v:146369.3-146370.65" + wire width 4 $0\logical_op__data_len$18[3:0]$7023 + attribute \src "libresoc.v:145557.13-145557.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7097 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7038 + attribute \src "libresoc.v:146339.3-146340.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6993 + attribute \src "libresoc.v:145596.14-145596.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7099 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7039 + attribute \src "libresoc.v:146341.3-146342.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6995 + attribute \src "libresoc.v:145620.14-145620.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7101 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$7040 + attribute \src "libresoc.v:146343.3-146344.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6997 + attribute \src "libresoc.v:145629.7-145629.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7103 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$7041 + attribute \src "libresoc.v:146357.3-146358.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$7011 + attribute \src "libresoc.v:145646.13-145646.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7105 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$7042 + attribute \src "libresoc.v:146371.3-146372.57" + wire width 32 $0\logical_op__insn$19[31:0]$7025 + attribute \src "libresoc.v:145659.14-145659.43" + wire width 32 $0\logical_op__insn$19[31:0]$7107 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$7043 + attribute \src "libresoc.v:146337.3-146338.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6991 + attribute \src "libresoc.v:145818.13-145818.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7109 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__invert_in$10$next[0:0]$7044 + attribute \src "libresoc.v:146353.3-146354.67" + wire $0\logical_op__invert_in$10[0:0]$7007 + attribute \src "libresoc.v:145902.7-145902.40" + wire $0\logical_op__invert_in$10[0:0]$7111 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__invert_out$13$next[0:0]$7045 + attribute \src "libresoc.v:146359.3-146360.69" + wire $0\logical_op__invert_out$13[0:0]$7013 + attribute \src "libresoc.v:145911.7-145911.41" + wire $0\logical_op__invert_out$13[0:0]$7113 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__is_32bit$16$next[0:0]$7046 + attribute \src "libresoc.v:146365.3-146366.65" + wire $0\logical_op__is_32bit$16[0:0]$7019 + attribute \src "libresoc.v:145920.7-145920.39" + wire $0\logical_op__is_32bit$16[0:0]$7115 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__is_signed$17$next[0:0]$7047 + attribute \src "libresoc.v:146367.3-146368.67" + wire $0\logical_op__is_signed$17[0:0]$7021 + attribute \src "libresoc.v:145929.7-145929.40" + wire $0\logical_op__is_signed$17[0:0]$7117 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7048 + attribute \src "libresoc.v:146349.3-146350.59" + wire $0\logical_op__oe__oe$8[0:0]$7003 + attribute \src "libresoc.v:145940.7-145940.36" + wire $0\logical_op__oe__oe$8[0:0]$7119 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7049 + attribute \src "libresoc.v:146351.3-146352.59" + wire $0\logical_op__oe__ok$9[0:0]$7005 + attribute \src "libresoc.v:145949.7-145949.36" + wire $0\logical_op__oe__ok$9[0:0]$7121 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__output_carry$15$next[0:0]$7050 + attribute \src "libresoc.v:146363.3-146364.73" + wire $0\logical_op__output_carry$15[0:0]$7017 + attribute \src "libresoc.v:145956.7-145956.43" + wire $0\logical_op__output_carry$15[0:0]$7123 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7051 + attribute \src "libresoc.v:146347.3-146348.59" + wire $0\logical_op__rc__ok$7[0:0]$7001 + attribute \src "libresoc.v:145967.7-145967.36" + wire $0\logical_op__rc__ok$7[0:0]$7125 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7052 + attribute \src "libresoc.v:146345.3-146346.59" + wire $0\logical_op__rc__rc$6[0:0]$6999 + attribute \src "libresoc.v:145976.7-145976.36" + wire $0\logical_op__rc__rc$6[0:0]$7127 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7053 + attribute \src "libresoc.v:146361.3-146362.67" + wire $0\logical_op__write_cr0$14[0:0]$7015 + attribute \src "libresoc.v:145983.7-145983.40" + wire $0\logical_op__write_cr0$14[0:0]$7129 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__zero_a$11$next[0:0]$7054 + attribute \src "libresoc.v:146355.3-146356.61" + wire $0\logical_op__zero_a$11[0:0]$7009 + attribute \src "libresoc.v:145992.7-145992.37" + wire $0\logical_op__zero_a$11[0:0]$7131 + attribute \src "libresoc.v:146451.3-146463.6" + wire width 2 $0\muxid$1$next[1:0]$7034 + attribute \src "libresoc.v:146373.3-146374.33" + wire width 2 $0\muxid$1[1:0]$7027 + attribute \src "libresoc.v:146001.13-146001.29" + wire width 2 $0\muxid$1[1:0]$7133 + attribute \src "libresoc.v:146506.3-146524.6" + wire width 64 $0\o$20$next[63:0]$7080 + attribute \src "libresoc.v:146333.3-146334.27" + wire width 64 $0\o$20[63:0]$6987 + attribute \src "libresoc.v:146016.14-146016.43" + wire width 64 $0\o$20[63:0]$7135 + attribute \src "libresoc.v:146506.3-146524.6" + wire $0\o_ok$21$next[0:0]$7081 + attribute \src "libresoc.v:146335.3-146336.33" + wire $0\o_ok$21[0:0]$6989 + attribute \src "libresoc.v:146025.7-146025.23" + wire $0\o_ok$21[0:0]$7137 + attribute \src "libresoc.v:146433.3-146450.6" + wire $0\r_busy$next[0:0]$7030 + attribute \src "libresoc.v:146375.3-146376.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:146525.3-146543.6" + wire width 4 $1\cr_a$22$next[3:0]$7088 + attribute \src "libresoc.v:146525.3-146543.6" + wire $1\cr_a_ok$23$next[0:0]$7089 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7055 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7056 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7057 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7058 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7059 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7060 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7061 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__invert_in$10$next[0:0]$7062 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__invert_out$13$next[0:0]$7063 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7064 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__is_signed$17$next[0:0]$7065 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7066 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7067 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__output_carry$15$next[0:0]$7068 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7069 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7070 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7071 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__zero_a$11$next[0:0]$7072 + attribute \src "libresoc.v:146451.3-146463.6" + wire width 2 $1\muxid$1$next[1:0]$7035 + attribute \src "libresoc.v:146506.3-146524.6" + wire width 64 $1\o$20$next[63:0]$7082 + attribute \src "libresoc.v:146506.3-146524.6" + wire $1\o_ok$21$next[0:0]$7083 + attribute \src "libresoc.v:146433.3-146450.6" + wire $1\r_busy$next[0:0]$7031 + attribute \src "libresoc.v:146319.7-146319.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:146525.3-146543.6" + wire $2\cr_a_ok$23$next[0:0]$7090 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7073 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7074 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7075 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7076 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7077 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7078 + attribute \src "libresoc.v:146506.3-146524.6" + wire $2\o_ok$21$next[0:0]$7084 + attribute \src "libresoc.v:146433.3-146450.6" + wire $2\r_busy$next[0:0]$7032 + attribute \src "libresoc.v:146328.18-146328.118" + wire $and$libresoc.v:146328$6981_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$73 + attribute \src "libresoc.v:145526.7-145526.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:146328$6981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$libresoc.v:146328$6981_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146377.10-146380.4" + cell \n$53 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146381.15-146428.4" + cell \output$54 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$20 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$44 + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146429.10-146432.4" + cell \p$52 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:145526.7-145526.20" + process $proc$libresoc.v:145526$7091 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145537.13-145537.29" + process $proc$libresoc.v:145537$7092 + assign { } { } + assign $0\cr_a$22[3:0]$7093 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$7093 + end + attribute \src "libresoc.v:145546.7-145546.26" + process $proc$libresoc.v:145546$7094 + assign { } { } + assign $0\cr_a_ok$23[0:0]$7095 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7095 + end + attribute \src "libresoc.v:145557.13-145557.45" + process $proc$libresoc.v:145557$7096 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$7097 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7097 + end + attribute \src "libresoc.v:145596.14-145596.48" + process $proc$libresoc.v:145596$7098 + assign { } { } + assign $0\logical_op__fn_unit$3[13:0]$7099 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7099 + end + attribute \src "libresoc.v:145620.14-145620.67" + process $proc$libresoc.v:145620$7100 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$7101 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7101 + end + attribute \src "libresoc.v:145629.7-145629.42" + process $proc$libresoc.v:145629$7102 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$7103 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7103 + end + attribute \src "libresoc.v:145646.13-145646.48" + process $proc$libresoc.v:145646$7104 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$7105 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7105 + end + attribute \src "libresoc.v:145659.14-145659.43" + process $proc$libresoc.v:145659$7106 + assign { } { } + assign $0\logical_op__insn$19[31:0]$7107 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7107 + end + attribute \src "libresoc.v:145818.13-145818.46" + process $proc$libresoc.v:145818$7108 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$7109 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7109 + end + attribute \src "libresoc.v:145902.7-145902.40" + process $proc$libresoc.v:145902$7110 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$7111 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7111 + end + attribute \src "libresoc.v:145911.7-145911.41" + process $proc$libresoc.v:145911$7112 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$7113 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7113 + end + attribute \src "libresoc.v:145920.7-145920.39" + process $proc$libresoc.v:145920$7114 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$7115 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7115 + end + attribute \src "libresoc.v:145929.7-145929.40" + process $proc$libresoc.v:145929$7116 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$7117 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7117 + end + attribute \src "libresoc.v:145940.7-145940.36" + process $proc$libresoc.v:145940$7118 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$7119 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7119 + end + attribute \src "libresoc.v:145949.7-145949.36" + process $proc$libresoc.v:145949$7120 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$7121 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7121 + end + attribute \src "libresoc.v:145956.7-145956.43" + process $proc$libresoc.v:145956$7122 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$7123 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7123 + end + attribute \src "libresoc.v:145967.7-145967.36" + process $proc$libresoc.v:145967$7124 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$7125 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7125 + end + attribute \src "libresoc.v:145976.7-145976.36" + process $proc$libresoc.v:145976$7126 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$7127 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7127 + end + attribute \src "libresoc.v:145983.7-145983.40" + process $proc$libresoc.v:145983$7128 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$7129 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7129 + end + attribute \src "libresoc.v:145992.7-145992.37" + process $proc$libresoc.v:145992$7130 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$7131 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7131 + end + attribute \src "libresoc.v:146001.13-146001.29" + process $proc$libresoc.v:146001$7132 + assign { } { } + assign $0\muxid$1[1:0]$7133 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7133 + end + attribute \src "libresoc.v:146016.14-146016.43" + process $proc$libresoc.v:146016$7134 + assign { } { } + assign $0\o$20[63:0]$7135 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$7135 + end + attribute \src "libresoc.v:146025.7-146025.23" + process $proc$libresoc.v:146025$7136 + assign { } { } + assign $0\o_ok$21[0:0]$7137 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$7137 + end + attribute \src "libresoc.v:146319.7-146319.20" + process $proc$libresoc.v:146319$7138 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:146329.3-146330.33" + process $proc$libresoc.v:146329$6982 + assign { } { } + assign $0\cr_a$22[3:0]$6983 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$6983 + end + attribute \src "libresoc.v:146331.3-146332.39" + process $proc$libresoc.v:146331$6984 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6985 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6985 + end + attribute \src "libresoc.v:146333.3-146334.27" + process $proc$libresoc.v:146333$6986 + assign { } { } + assign $0\o$20[63:0]$6987 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$6987 + end + attribute \src "libresoc.v:146335.3-146336.33" + process $proc$libresoc.v:146335$6988 + assign { } { } + assign $0\o_ok$21[0:0]$6989 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$6989 + end + attribute \src "libresoc.v:146337.3-146338.65" + process $proc$libresoc.v:146337$6990 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6991 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6991 + end + attribute \src "libresoc.v:146339.3-146340.61" + process $proc$libresoc.v:146339$6992 + assign { } { } + assign $0\logical_op__fn_unit$3[13:0]$6993 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6993 + end + attribute \src "libresoc.v:146341.3-146342.75" + process $proc$libresoc.v:146341$6994 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6995 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6995 + end + attribute \src "libresoc.v:146343.3-146344.71" + process $proc$libresoc.v:146343$6996 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$6997 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6997 + end + attribute \src "libresoc.v:146345.3-146346.59" + process $proc$libresoc.v:146345$6998 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6999 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6999 + end + attribute \src "libresoc.v:146347.3-146348.59" + process $proc$libresoc.v:146347$7000 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$7001 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7001 + end + attribute \src "libresoc.v:146349.3-146350.59" + process $proc$libresoc.v:146349$7002 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$7003 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7003 + end + attribute \src "libresoc.v:146351.3-146352.59" + process $proc$libresoc.v:146351$7004 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$7005 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7005 + end + attribute \src "libresoc.v:146353.3-146354.67" + process $proc$libresoc.v:146353$7006 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$7007 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7007 + end + attribute \src "libresoc.v:146355.3-146356.61" + process $proc$libresoc.v:146355$7008 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$7009 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7009 + end + attribute \src "libresoc.v:146357.3-146358.71" + process $proc$libresoc.v:146357$7010 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$7011 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7011 + end + attribute \src "libresoc.v:146359.3-146360.69" + process $proc$libresoc.v:146359$7012 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$7013 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7013 + end + attribute \src "libresoc.v:146361.3-146362.67" + process $proc$libresoc.v:146361$7014 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$7015 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7015 + end + attribute \src "libresoc.v:146363.3-146364.73" + process $proc$libresoc.v:146363$7016 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$7017 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7017 + end + attribute \src "libresoc.v:146365.3-146366.65" + process $proc$libresoc.v:146365$7018 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$7019 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7019 + end + attribute \src "libresoc.v:146367.3-146368.67" + process $proc$libresoc.v:146367$7020 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$7021 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7021 + end + attribute \src "libresoc.v:146369.3-146370.65" + process $proc$libresoc.v:146369$7022 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$7023 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7023 + end + attribute \src "libresoc.v:146371.3-146372.57" + process $proc$libresoc.v:146371$7024 + assign { } { } + assign $0\logical_op__insn$19[31:0]$7025 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7025 + end + attribute \src "libresoc.v:146373.3-146374.33" + process $proc$libresoc.v:146373$7026 + assign { } { } + assign $0\muxid$1[1:0]$7027 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7027 + end + attribute \src "libresoc.v:146375.3-146376.29" + process $proc$libresoc.v:146375$7028 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:146433.3-146450.6" + process $proc$libresoc.v:146433$7029 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7030 $2\r_busy$next[0:0]$7032 + attribute \src "libresoc.v:146434.5-146434.29" + switch \initial + attribute \src "libresoc.v:146434.9-146434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7031 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7031 1'0 + case + assign $1\r_busy$next[0:0]$7031 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7032 1'0 + case + assign $2\r_busy$next[0:0]$7032 $1\r_busy$next[0:0]$7031 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7030 + end + attribute \src "libresoc.v:146451.3-146463.6" + process $proc$libresoc.v:146451$7033 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7034 $1\muxid$1$next[1:0]$7035 + attribute \src "libresoc.v:146452.5-146452.29" + switch \initial + attribute \src "libresoc.v:146452.9-146452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7035 \muxid$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7035 \muxid$51 + case + assign $1\muxid$1$next[1:0]$7035 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7034 + end + attribute \src "libresoc.v:146464.3-146505.6" + process $proc$libresoc.v:146464$7036 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$7037 $1\logical_op__data_len$18$next[3:0]$7055 + assign $0\logical_op__fn_unit$3$next[13:0]$7038 $1\logical_op__fn_unit$3$next[13:0]$7056 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$7041 $1\logical_op__input_carry$12$next[1:0]$7059 + assign $0\logical_op__insn$19$next[31:0]$7042 $1\logical_op__insn$19$next[31:0]$7060 + assign $0\logical_op__insn_type$2$next[6:0]$7043 $1\logical_op__insn_type$2$next[6:0]$7061 + assign $0\logical_op__invert_in$10$next[0:0]$7044 $1\logical_op__invert_in$10$next[0:0]$7062 + assign $0\logical_op__invert_out$13$next[0:0]$7045 $1\logical_op__invert_out$13$next[0:0]$7063 + assign $0\logical_op__is_32bit$16$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7064 + assign $0\logical_op__is_signed$17$next[0:0]$7047 $1\logical_op__is_signed$17$next[0:0]$7065 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$7050 $1\logical_op__output_carry$15$next[0:0]$7068 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$7053 $1\logical_op__write_cr0$14$next[0:0]$7071 + assign $0\logical_op__zero_a$11$next[0:0]$7054 $1\logical_op__zero_a$11$next[0:0]$7072 + assign $0\logical_op__imm_data__data$4$next[63:0]$7039 $2\logical_op__imm_data__data$4$next[63:0]$7073 + assign $0\logical_op__imm_data__ok$5$next[0:0]$7040 $2\logical_op__imm_data__ok$5$next[0:0]$7074 + assign $0\logical_op__oe__oe$8$next[0:0]$7048 $2\logical_op__oe__oe$8$next[0:0]$7075 + assign $0\logical_op__oe__ok$9$next[0:0]$7049 $2\logical_op__oe__ok$9$next[0:0]$7076 + assign $0\logical_op__rc__ok$7$next[0:0]$7051 $2\logical_op__rc__ok$7$next[0:0]$7077 + assign $0\logical_op__rc__rc$6$next[0:0]$7052 $2\logical_op__rc__rc$6$next[0:0]$7078 + attribute \src "libresoc.v:146465.5-146465.29" + switch \initial + attribute \src "libresoc.v:146465.9-146465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + case + assign $1\logical_op__data_len$18$next[3:0]$7055 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$7056 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7057 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7058 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7059 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7060 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7061 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7062 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7063 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7064 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7065 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7066 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7067 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7068 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7069 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7070 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7071 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7072 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$7073 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7078 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7077 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7075 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7076 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$7073 $1\logical_op__imm_data__data$4$next[63:0]$7057 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 $1\logical_op__imm_data__ok$5$next[0:0]$7058 + assign $2\logical_op__oe__oe$8$next[0:0]$7075 $1\logical_op__oe__oe$8$next[0:0]$7066 + assign $2\logical_op__oe__ok$9$next[0:0]$7076 $1\logical_op__oe__ok$9$next[0:0]$7067 + assign $2\logical_op__rc__ok$7$next[0:0]$7077 $1\logical_op__rc__ok$7$next[0:0]$7069 + assign $2\logical_op__rc__rc$6$next[0:0]$7078 $1\logical_op__rc__rc$6$next[0:0]$7070 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7037 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7038 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7039 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7040 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7041 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7042 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7043 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7044 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7045 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7046 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7047 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7048 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7049 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7050 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7051 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7052 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7053 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7054 + end + attribute \src "libresoc.v:146506.3-146524.6" + process $proc$libresoc.v:146506$7079 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$7080 $1\o$20$next[63:0]$7082 + assign { } { } + assign $0\o_ok$21$next[0:0]$7081 $2\o_ok$21$next[0:0]$7084 + attribute \src "libresoc.v:146507.5-146507.29" + switch \initial + attribute \src "libresoc.v:146507.9-146507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } + case + assign $1\o$20$next[63:0]$7082 \o$20 + assign $1\o_ok$21$next[0:0]$7083 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$7084 1'0 + case + assign $2\o_ok$21$next[0:0]$7084 $1\o_ok$21$next[0:0]$7083 + end + sync always + update \o$20$next $0\o$20$next[63:0]$7080 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7081 + end + attribute \src "libresoc.v:146525.3-146543.6" + process $proc$libresoc.v:146525$7085 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$7086 $1\cr_a$22$next[3:0]$7088 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$7087 $2\cr_a_ok$23$next[0:0]$7090 + attribute \src "libresoc.v:146526.5-146526.29" + switch \initial + attribute \src "libresoc.v:146526.9-146526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } + case + assign $1\cr_a$22$next[3:0]$7088 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7089 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$7090 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$7090 $1\cr_a_ok$23$next[0:0]$7089 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$7086 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7087 + end + connect \$49 $and$libresoc.v:146328$6981_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } + connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "ls180.v:4.1-10804.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10226$1_ADDR[3:0]$2768 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10226$1_DATA[63:0]$2769 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10226$1_EN[63:0]$2770 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10228$2_ADDR[3:0]$2771 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10228$2_DATA[63:0]$2772 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10228$2_EN[63:0]$2773 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10230$3_ADDR[3:0]$2774 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10230$3_DATA[63:0]$2775 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10230$3_EN[63:0]$2776 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10232$4_ADDR[3:0]$2777 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10232$4_DATA[63:0]$2778 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10232$4_EN[63:0]$2779 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10234$5_ADDR[3:0]$2780 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10234$5_DATA[63:0]$2781 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10234$5_EN[63:0]$2782 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10236$6_ADDR[3:0]$2783 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10236$6_DATA[63:0]$2784 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10236$6_EN[63:0]$2785 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10238$7_ADDR[3:0]$2786 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10238$7_DATA[63:0]$2787 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10238$7_EN[63:0]$2788 + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0$memwr$\mem$ls180.v:10240$8_ADDR[3:0]$2789 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10240$8_DATA[63:0]$2790 + attribute \src "ls180.v:10224.1-10242.4" + wire width 64 $0$memwr$\mem$ls180.v:10240$8_EN[63:0]$2791 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10254$9_ADDR[3:0]$2794 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10254$9_DATA[63:0]$2795 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10254$9_EN[63:0]$2796 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10256$10_ADDR[3:0]$2797 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10256$10_DATA[63:0]$2798 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10256$10_EN[63:0]$2799 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10258$11_ADDR[3:0]$2800 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10258$11_DATA[63:0]$2801 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10258$11_EN[63:0]$2802 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10260$12_ADDR[3:0]$2803 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10260$12_DATA[63:0]$2804 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10260$12_EN[63:0]$2805 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10262$13_ADDR[3:0]$2806 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10262$13_DATA[63:0]$2807 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10262$13_EN[63:0]$2808 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10264$14_ADDR[3:0]$2809 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10264$14_DATA[63:0]$2810 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10264$14_EN[63:0]$2811 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10266$15_ADDR[3:0]$2812 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10266$15_DATA[63:0]$2813 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10266$15_EN[63:0]$2814 + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10268$16_ADDR[3:0]$2815 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10268$16_DATA[63:0]$2816 + attribute \src "ls180.v:10252.1-10270.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10268$16_EN[63:0]$2817 + attribute \src "ls180.v:10280.1-10284.4" + wire width 3 $0$memwr$\storage$ls180.v:10282$17_ADDR[2:0]$2820 + attribute \src "ls180.v:10280.1-10284.4" + wire width 25 $0$memwr$\storage$ls180.v:10282$17_DATA[24:0]$2821 + attribute \src "ls180.v:10280.1-10284.4" + wire width 25 $0$memwr$\storage$ls180.v:10282$17_EN[24:0]$2822 + attribute \src "ls180.v:10294.1-10298.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10296$18_ADDR[2:0]$2827 + attribute \src "ls180.v:10294.1-10298.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10296$18_DATA[24:0]$2828 + attribute \src "ls180.v:10294.1-10298.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10296$18_EN[24:0]$2829 + attribute \src "ls180.v:10308.1-10312.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10310$19_ADDR[2:0]$2834 + attribute \src "ls180.v:10308.1-10312.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10310$19_DATA[24:0]$2835 + attribute \src "ls180.v:10308.1-10312.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10310$19_EN[24:0]$2836 + attribute \src "ls180.v:10322.1-10326.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10324$20_ADDR[2:0]$2841 + attribute \src "ls180.v:10322.1-10326.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10324$20_DATA[24:0]$2842 + attribute \src "ls180.v:10322.1-10326.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10324$20_EN[24:0]$2843 + attribute \src "ls180.v:10337.1-10341.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10339$21_ADDR[3:0]$2848 + attribute \src "ls180.v:10337.1-10341.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10339$21_DATA[9:0]$2849 + attribute \src "ls180.v:10337.1-10341.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10339$21_EN[9:0]$2850 + attribute \src "ls180.v:10354.1-10358.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10356$22_ADDR[3:0]$2855 + attribute \src "ls180.v:10354.1-10358.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10356$22_DATA[9:0]$2856 + attribute \src "ls180.v:10354.1-10358.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10356$22_EN[9:0]$2857 + attribute \src "ls180.v:10370.1-10374.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10372$23_ADDR[4:0]$2862 + attribute \src "ls180.v:10370.1-10374.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10372$23_DATA[9:0]$2863 + attribute \src "ls180.v:10370.1-10374.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10372$23_EN[9:0]$2864 + attribute \src "ls180.v:10384.1-10388.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10386$24_ADDR[4:0]$2869 + attribute \src "ls180.v:10384.1-10388.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10386$24_DATA[9:0]$2870 + attribute \src "ls180.v:10384.1-10388.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10386$24_EN[9:0]$2871 + attribute \src "ls180.v:3315.1-3408.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3472.1-3565.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3629.1-3722.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3786.1-3879.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6677.1-6693.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:6898.1-6914.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:6915.1-6931.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:6983.1-6990.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:6991.1-6998.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:6999.1-7006.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:7007.1-7014.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:7015.1-7022.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:7023.1-7030.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:7031.1-7038.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:7039.1-7046.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6694.1-6710.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7047.1-7054.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:7055.1-7062.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:7063.1-7070.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:7071.1-7078.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:7079.1-7098.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:7099.1-7118.4" + wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:7119.1-7138.4" + wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:7139.1-7158.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:7159.1-7178.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:7179.1-7198.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6711.1-6727.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:7199.1-7218.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:7219.1-7238.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6728.1-6744.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6745.1-6761.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6762.1-6778.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6830.1-6846.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6847.1-6863.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6864.1-6880.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6881.1-6897.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6779.1-6795.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6796.1-6812.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6813.1-6829.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:6932.1-6948.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:6949.1-6965.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:6966.1-6982.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:5917.1-5928.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5761.1-5797.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5761.1-5797.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1948.5-1948.55" + wire $0\builder_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1944.12-1944.65" + wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1952.5-1952.55" + wire $0\builder_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5761.1-5797.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5761.1-5797.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5761.1-5797.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5761.1-5797.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5761.1-5797.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1934.12-1934.52" + wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1938.5-1938.44" + wire $0\builder_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:5761.1-5797.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1935.12-1935.54" + wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1937.11-1937.50" + wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] + attribute \src "ls180.v:1939.5-1939.44" + wire $0\builder_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1941.5-1941.43" + wire $0\builder_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:1833.5-1833.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1834.5-1834.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1835.5-1835.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1836.5-1836.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5761.1-5797.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3221.1-3251.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5559.1-5598.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5656.1-5692.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4801.1-4873.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4646.1-4739.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4536.1-4612.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4773.1-4800.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4502.1-4535.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:5917.1-5928.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:5917.1-5928.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5822.1-5834.4" + wire width 10 $0\builder_slave_sel[9:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 10 $0\builder_slave_sel_r[9:0] + attribute \src "ls180.v:4333.1-4381.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:4392.1-4440.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7358.1-7386.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7387.1-7415.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7239.1-7255.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7256.1-7272.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7273.1-7289.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7290.1-7306.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7307.1-7323.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7324.1-7340.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7341.1-7357.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:4312.1-4316.4" + wire width 16 $0\gpio_o[15:0] + attribute \src "ls180.v:4317.1-4321.4" + wire width 16 $0\gpio_oe[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_converter0_counter[0:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_converter0_dat_r[63:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_converter0_skip[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_converter1_counter[0:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_converter1_dat_r[63:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_converter1_skip[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 24 $0\main_dummy[23:0] + attribute \src "ls180.v:1040.12-1040.53" + wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] + attribute \src "ls180.v:1042.12-1042.54" + wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] + attribute \src "ls180.v:7473.1-7483.4" + wire width 16 $0\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:7484.1-7494.4" + wire width 16 $0\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7515.1-7517.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1621.11-1621.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1620.11-1620.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:274.5-274.51" + wire $0\main_interface0_converted_interface_err[0:0] + attribute \src "ls180.v:5618.1-5655.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1712.11-1712.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1711.11-1711.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1704.12-1704.45" + wire width 64 $0\main_interface1_bus_dat_w[63:0] + attribute \src "ls180.v:5618.1-5655.4" + wire width 8 $0\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:289.5-289.51" + wire $0\main_interface1_converted_interface_err[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:196.12-196.74" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + attribute \src "ls180.v:200.5-200.69" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + attribute \src "ls180.v:185.5-185.72" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + attribute \src "ls180.v:188.11-188.79" + wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + attribute \src "ls180.v:173.12-173.78" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + attribute \src "ls180.v:75.11-75.52" + wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:74.11-74.52" + wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:86.11-86.52" + wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:85.11-85.52" + wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:2842.1-2847.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:115.11-115.55" + wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:114.11-114.55" + wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:2861.1-2907.4" + wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:2849.1-2859.4" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:2861.1-2907.4" + wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:2861.1-2907.4" + wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:2921.1-2967.4" + wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:2909.1-2919.4" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:2921.1-2967.4" + wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:2921.1-2967.4" + wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:217.5-217.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:3030.1-3040.4" + wire width 8 $0\main_libresocsim_we[7:0] + attribute \src "ls180.v:3046.1-3051.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:4132.1-4178.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:4120.1-4130.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:4132.1-4178.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:259.5-259.36" + wire $0\main_ram_bus_ram_bus_err[0:0] + attribute \src "ls180.v:3055.1-3065.4" + wire width 8 $0\main_ram_we[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1645.5-1645.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5526.1-5533.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5559.1-5598.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5559.1-5598.4" + wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:5559.1-5598.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5559.1-5598.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5559.1-5598.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5559.1-5598.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5559.1-5598.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1454.5-1454.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5214.1-5221.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5270.1-5277.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5224.1-5231.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5280.1-5287.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5234.1-5241.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5290.1-5297.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5244.1-5251.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5300.1-5307.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5259.1-5266.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1560.5-1560.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5253.1-5258.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:5206.1-5211.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:5126.1-5205.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:5088.1-5095.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:5098.1-5105.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:5108.1-5115.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:5118.1-5125.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1517.5-1517.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:5126.1-5205.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:5126.1-5205.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:5066.1-5073.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:5704.1-5732.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:5618.1-5655.4" + wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5656.1-5692.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5656.1-5692.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5656.1-5692.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5656.1-5692.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5656.1-5692.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5656.1-5692.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1725.5-1725.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5618.1-5655.4" + wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:5618.1-5655.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1781.5-1781.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5746.1-5753.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4472.1-4500.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1246.5-1246.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1247.5-1247.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1227.5-1227.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4646.1-4739.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1200.5-1200.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1201.5-1201.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1202.5-1202.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1204.5-1204.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1205.5-1205.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1207.11-1207.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1208.5-1208.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1213.11-1213.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1214.5-1214.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4646.1-4739.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4646.1-4739.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4646.1-4739.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4536.1-4612.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4536.1-4612.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4536.1-4612.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4536.1-4612.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4536.1-4612.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4536.1-4612.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1190.11-1190.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1191.5-1191.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4536.1-4612.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4907.1-5008.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1402.5-1402.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1403.5-1403.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1383.5-1383.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1354.5-1354.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1355.5-1355.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1356.5-1356.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1358.5-1358.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1359.5-1359.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1361.11-1361.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1362.5-1362.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1365.5-1365.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1366.5-1366.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1367.11-1367.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1368.5-1368.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1375.5-1375.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4907.1-5008.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4907.1-5008.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4907.1-5008.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4801.1-4873.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4801.1-4873.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1324.5-1324.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1325.5-1325.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1305.5-1305.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4773.1-4800.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4773.1-4800.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4773.1-4800.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4773.1-4800.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1292.5-1292.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1293.5-1293.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1294.5-1294.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1295.5-1295.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1296.5-1296.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1297.5-1297.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1298.11-1298.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1299.11-1299.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1300.5-1300.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1290.5-1290.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4801.1-4873.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1279.5-1279.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1280.5-1280.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4801.1-4873.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4801.1-4873.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4801.1-4873.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5308.1-5498.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4801.1-4873.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4801.1-4873.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4773.1-4800.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4502.1-4535.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4502.1-4535.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1172.5-1172.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4502.1-4535.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4502.1-4535.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4502.1-4535.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4502.1-4535.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4502.1-4535.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3277.1-3284.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:494.5-494.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:477.5-477.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:478.5-478.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3299.1-3306.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3266.1-3273.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:3964.1-3972.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3315.1-3408.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:536.32-536.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:534.32-534.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3434.1-3441.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:576.5-576.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:559.5-559.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:560.5-560.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3456.1-3463.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3423.1-3430.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:3973.1-3981.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3472.1-3565.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:618.32-618.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:616.32-616.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3591.1-3598.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:658.5-658.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:641.5-641.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:642.5-642.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3613.1-3620.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3580.1-3587.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:3982.1-3990.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3629.1-3722.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:700.32-700.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:698.32-698.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3748.1-3755.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:740.5-740.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:723.5-723.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:724.5-724.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3770.1-3777.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3737.1-3744.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:3991.1-3999.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3786.1-3879.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:782.32-782.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:780.32-780.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3913.1-3918.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:3919.1-3924.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:3925.1-3930.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:790.5-790.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3899.1-3905.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:788.5-788.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:787.5-787.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:785.5-785.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:786.5-786.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:3946.1-3951.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:3952.1-3957.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:3958.1-3963.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:3932.1-3938.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3221.1-3251.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:438.5-438.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:439.5-439.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3221.1-3251.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:374.5-374.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:423.5-423.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:4100.1-4113.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:4100.1-4113.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:324.5-324.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3162.1-3178.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3162.1-3178.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3162.1-3178.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3162.1-3178.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:3104.1-3158.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:821.12-821.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:822.11-822.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3221.1-3251.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:3104.1-3158.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:3104.1-3158.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:824.5-824.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:825.5-825.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:4004.1-4076.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:829.32-829.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:827.32-827.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:876.5-876.54" + wire $0\main_socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_socbushandler_counter[0:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 64 $0\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_socbushandler_skip[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_spimaster11_storage[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster12_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spimaster16_storage[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster17_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster1_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_spimaster1_storage[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster21_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster22_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster23_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spimaster24_re[0:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_spimaster27_count[2:0] + attribute \src "ls180.v:4333.1-4381.4" + wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster2_done[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:4333.1-4381.4" + wire $0\main_spimaster3_irq[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1063.12-1063.47" + wire width 16 $0\main_spimaster8_clk_divider[15:0] + attribute \src "ls180.v:6442.1-6447.4" + wire $0\main_spimaster9_start[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 16 $0\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_spisdcard_count[2:0] + attribute \src "ls180.v:4392.1-4440.4" + wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_done0[0:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_irq[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spisdcard_miso[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:4392.1-4440.4" + wire $0\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 3 $0\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:6488.1-6493.4" + wire $0\main_spisdcard_start1[0:0] + attribute \src "ls180.v:4240.1-4244.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4229.1-4233.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:912.5-912.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:913.5-913.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:1039.5-1039.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4234.1-4239.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:1021.5-1021.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4292.1-4299.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4223.1-4228.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:984.5-984.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:967.5-967.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:968.5-968.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4262.1-4269.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:4132.1-4178.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:2981.1-3027.4" + wire width 30 $0\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:2969.1-2979.4" + wire width 32 $0\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:2981.1-3027.4" + wire width 4 $0\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:2981.1-3027.4" + wire $0\main_wb_sdram_we[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:10224.1-10242.4" + wire width 4 $0\memadr[3:0] + attribute \src "ls180.v:10252.1-10270.4" + wire width 4 $0\memadr_1[3:0] + attribute \src "ls180.v:10280.1-10284.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10294.1-10298.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10308.1-10312.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10322.1-10326.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10337.1-10341.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10343.1-10346.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10354.1-10358.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10360.1-10363.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10370.1-10374.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10384.1-10388.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7591.1-10220.4" + wire width 2 $0\pwm[1:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7519.1-7589.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7519.1-7589.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\spimaster_clk[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\spimaster_cs_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\spimaster_mosi[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:7591.1-10220.4" + wire $0\uart_tx[0:0] + attribute \src "ls180.v:1812.11-1812.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1811.11-1811.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1814.11-1814.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1813.11-1813.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1816.11-1816.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1815.11-1815.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1818.11-1818.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1817.11-1817.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2671.5-2671.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2684.5-2684.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2685.5-2685.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2689.12-2689.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2690.5-2690.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2691.5-2691.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2692.12-2692.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2693.5-2693.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2694.5-2694.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2695.12-2695.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2696.5-2696.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2672.12-2672.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2697.5-2697.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2698.12-2698.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2699.5-2699.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2700.5-2700.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2701.12-2701.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2702.12-2702.50" + wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:2703.11-2703.48" + wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:2704.5-2704.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2705.5-2705.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2706.5-2706.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2673.11-2673.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2707.11-2707.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2708.11-2708.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2674.5-2674.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2675.5-2675.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2676.5-2676.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2680.5-2680.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2681.12-2681.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2682.11-2682.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2683.5-2683.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2677.5-2677.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2678.5-2678.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2679.5-2679.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2686.5-2686.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2687.5-2687.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2688.5-2688.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1798.5-1798.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1797.5-1797.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1802.5-1802.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1801.5-1801.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1806.5-1806.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1805.5-1805.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1843.5-1843.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1842.5-1842.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:1971.12-1971.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:1968.5-1968.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:1965.11-1965.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:1975.11-1975.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2477.11-2477.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2510.11-2510.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2551.11-2551.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2616.11-2616.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2641.11-2641.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2016.11-2016.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2045.11-2045.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2058.11-2058.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2099.11-2099.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2140.11-2140.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2205.11-2205.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2338.11-2338.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2419.11-2419.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2436.11-2436.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1930.12-1930.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2667.12-2667.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2668.5-2668.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1932.11-1932.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2665.11-2665.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2666.5-2666.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1931.5-1931.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2669.5-2669.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2670.5-2670.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1940.5-1940.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1936.12-1936.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1820.11-1820.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1819.11-1819.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2774.32-2774.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2775.32-2775.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2794.32-2794.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2795.32-2795.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2796.32-2796.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2797.32-2797.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2798.32-2798.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2799.32-2799.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2800.32-2800.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2801.32-2801.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2802.32-2802.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2803.32-2803.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2804.32-2804.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2805.32-2805.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2806.32-2806.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2807.32-2807.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2776.32-2776.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2777.32-2777.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2778.32-2778.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2779.32-2779.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2780.32-2780.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2781.32-2781.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2782.32-2782.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2783.32-2783.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2784.32-2784.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2785.32-2785.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2786.32-2786.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2787.32-2787.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2788.32-2788.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2789.32-2789.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2790.32-2790.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2791.32-2791.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2792.32-2792.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2793.32-2793.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1838.5-1838.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1839.5-1839.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1840.5-1840.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1841.5-1841.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1837.5-1837.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2664.11-2664.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1810.11-1810.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1809.11-1809.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1919.11-1919.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1918.11-1918.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1887.5-1887.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1886.5-1886.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1899.11-1899.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1898.11-1898.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1923.5-1923.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1922.5-1922.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1927.11-1927.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1926.11-1926.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1875.11-1875.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1874.11-1874.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1863.11-1863.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1862.11-1862.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1859.11-1859.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1858.11-1858.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1871.5-1871.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1870.5-1870.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1879.11-1879.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1878.11-1878.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1855.5-1855.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1854.5-1854.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:1959.5-1959.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1955.12-1955.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:1966.11-1966.36" + wire width 10 $1\builder_slave_sel[9:0] + attribute \src "ls180.v:1967.11-1967.38" + wire width 10 $1\builder_slave_sel_r[9:0] + attribute \src "ls180.v:1847.11-1847.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1846.11-1846.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1851.11-1851.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1850.11-1850.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2663.11-2663.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2716.5-2716.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2717.5-2717.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2709.11-2709.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2710.12-2710.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2711.5-2711.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2712.5-2712.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2713.5-2713.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2714.5-2714.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2715.5-2715.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:893.5-893.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:276.5-276.35" + wire $1\main_converter0_counter[0:0] + attribute \src "ls180.v:1799.5-1799.57" + wire $1\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1800.5-1800.60" + wire $1\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:278.12-278.41" + wire width 64 $1\main_converter0_dat_r[63:0] + attribute \src "ls180.v:275.5-275.32" + wire $1\main_converter0_skip[0:0] + attribute \src "ls180.v:291.5-291.35" + wire $1\main_converter1_counter[0:0] + attribute \src "ls180.v:1803.5-1803.57" + wire $1\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1804.5-1804.60" + wire $1\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:293.12-293.41" + wire width 64 $1\main_converter1_dat_r[63:0] + attribute \src "ls180.v:290.5-290.32" + wire $1\main_converter1_skip[0:0] + attribute \src "ls180.v:890.5-890.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1844.5-1844.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1845.5-1845.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:892.12-892.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:889.5-889.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:312.12-312.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:313.5-313.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:1130.12-1130.30" + wire width 24 $1\main_dummy[23:0] + attribute \src "ls180.v:1041.12-1041.49" + wire width 16 $1\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:1047.5-1047.40" + wire $1\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:1046.12-1046.53" + wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:1051.5-1051.41" + wire $1\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:1050.12-1050.54" + wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:1048.12-1048.49" + wire width 16 $1\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:1155.5-1155.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1154.11-1154.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:297.5-297.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:270.5-270.51" + wire $1\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:1703.12-1703.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1707.5-1707.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1706.11-1706.41" + wire width 8 $1\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:1708.5-1708.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1710.5-1710.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:285.5-285.51" + wire $1\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:63.12-63.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:227.5-227.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:226.5-226.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:247.5-247.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:246.5-246.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:65.12-65.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:88.12-88.58" + wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:92.5-92.50" + wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:89.12-89.60" + wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:91.11-91.56" + wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:93.5-93.50" + wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:95.5-95.49" + wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:97.12-97.58" + wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:101.5-101.50" + wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:98.12-98.60" + wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:100.11-100.56" + wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:102.5-102.50" + wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:104.5-104.49" + wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:223.5-223.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:222.12-222.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:213.5-213.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:225.5-225.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:224.12-224.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:56.5-56.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:55.5-55.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:58.5-58.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:57.12-57.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:229.5-229.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:228.5-228.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:248.12-248.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:230.12-230.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:220.11-220.37" + wire width 8 $1\main_libresocsim_we[7:0] + attribute \src "ls180.v:236.5-236.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:237.5-237.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:234.5-234.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:881.12-881.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:885.5-885.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:882.12-882.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:884.11-884.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:886.5-886.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:888.5-888.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:1134.12-1134.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1136.5-1136.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1135.5-1135.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1140.5-1140.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1139.12-1139.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1138.5-1138.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1137.12-1137.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1144.12-1144.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1146.5-1146.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1145.5-1145.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1150.5-1150.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1149.12-1149.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1148.5-1148.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1147.12-1147.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:255.5-255.36" + wire $1\main_ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:262.11-262.29" + wire width 8 $1\main_ram_we[7:0] + attribute \src "ls180.v:314.11-314.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:1672.11-1672.50" + wire width 3 $1\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:1668.5-1668.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1669.5-1669.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1670.12-1670.66" + wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:1671.11-1671.77" + wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1674.5-1674.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1647.11-1647.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1644.11-1644.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1646.11-1646.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1648.11-1648.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1682.12-1682.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1683.12-1683.60" + wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:1680.5-1680.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1690.5-1690.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1689.12-1689.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1694.5-1694.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1693.5-1693.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1692.5-1692.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1691.12-1691.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1698.5-1698.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1697.5-1697.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1700.12-1700.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1920.12-1920.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1921.5-1921.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1685.5-1685.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1695.5-1695.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1464.5-1464.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1463.12-1463.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1462.5-1462.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1461.11-1461.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1448.5-1448.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1447.12-1447.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1450.5-1450.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1449.12-1449.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1603.11-1603.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1904.11-1904.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1905.5-1905.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1604.5-1604.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1900.5-1900.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1901.5-1901.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1605.5-1605.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1908.5-1908.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1909.5-1909.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1455.13-1455.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1916.13-1916.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1917.5-1917.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1606.5-1606.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1910.5-1910.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1911.5-1911.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1564.11-1564.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1570.5-1570.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1569.12-1569.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1565.12-1565.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1577.5-1577.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1576.12-1576.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1572.12-1572.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1584.5-1584.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1583.12-1583.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1579.12-1579.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1591.5-1591.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1590.12-1590.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1586.12-1586.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1593.12-1593.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1594.12-1594.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1595.12-1595.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1596.12-1596.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1598.12-1598.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1599.12-1599.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1600.12-1600.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1601.12-1601.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1555.5-1555.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1556.5-1556.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1557.11-1557.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1554.5-1554.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1553.5-1553.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1558.5-1558.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1563.11-1563.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1597.5-1597.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1520.11-1520.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1896.11-1896.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1897.5-1897.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1525.12-1525.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1521.12-1521.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1532.12-1532.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1528.12-1528.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1539.12-1539.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1535.12-1535.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1546.12-1546.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1542.12-1542.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1549.12-1549.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1888.12-1888.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1889.5-1889.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1550.12-1550.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1890.12-1890.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1891.5-1891.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1551.12-1551.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1892.12-1892.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1893.5-1893.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1552.12-1552.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1894.12-1894.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1895.5-1895.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1511.5-1511.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1518.5-1518.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1519.11-1519.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1516.5-1516.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1515.5-1515.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1507.11-1507.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1465.11-1465.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1608.12-1608.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1906.12-1906.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1907.5-1907.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1609.5-1609.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1902.5-1902.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1903.5-1903.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1610.5-1610.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1912.5-1912.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1913.5-1913.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1611.5-1611.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1914.5-1914.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1915.5-1915.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1756.11-1756.48" + wire width 3 $1\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:1754.11-1754.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1730.5-1730.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1729.12-1729.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1728.12-1728.45" + wire width 64 $1\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:1924.12-1924.75" + wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:1925.5-1925.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1735.5-1735.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1734.5-1734.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1733.5-1733.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1732.5-1732.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1731.12-1731.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1738.5-1738.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1737.5-1737.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1742.12-1742.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1928.12-1928.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1929.5-1929.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1721.5-1721.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1722.12-1722.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1720.5-1720.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1719.5-1719.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1726.5-1726.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1727.12-1727.60" + wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:1723.5-1723.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1783.11-1783.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1780.11-1780.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1782.11-1782.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1784.11-1784.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1164.5-1164.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1167.5-1167.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1168.5-1168.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1166.11-1166.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1162.5-1162.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1161.11-1161.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1270.5-1270.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1271.5-1271.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1272.11-1272.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1268.5-1268.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1255.11-1255.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1251.5-1251.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1252.5-1252.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1253.11-1253.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1254.11-1254.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1257.5-1257.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1273.5-1273.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1868.5-1868.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1869.5-1869.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1243.5-1243.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1238.5-1238.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1225.11-1225.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1864.11-1864.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1865.5-1865.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1210.5-1210.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1211.5-1211.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1212.5-1212.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1217.5-1217.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1218.11-1218.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1216.5-1216.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1215.5-1215.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1221.5-1221.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1222.11-1222.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1223.11-1223.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1220.5-1220.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1219.5-1219.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1224.12-1224.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1866.12-1866.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1867.5-1867.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1197.11-1197.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1860.11-1860.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1861.5-1861.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1196.5-1196.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1187.5-1187.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1188.5-1188.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1189.5-1189.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1194.5-1194.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1195.11-1195.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1193.5-1193.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1192.5-1192.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1381.11-1381.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1880.11-1880.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1881.5-1881.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1426.5-1426.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1427.5-1427.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1428.11-1428.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1424.5-1424.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1411.5-1411.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1407.5-1407.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1408.5-1408.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1409.11-1409.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1410.11-1410.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1413.5-1413.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1429.5-1429.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1884.5-1884.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1885.5-1885.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1399.5-1399.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1394.5-1394.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1364.5-1364.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1371.5-1371.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1372.11-1372.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1370.5-1370.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1369.5-1369.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1376.5-1376.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1377.11-1377.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1378.11-1378.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1374.5-1374.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1373.5-1373.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1379.5-1379.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1380.12-1380.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1882.12-1882.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1883.5-1883.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1289.11-1289.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1876.11-1876.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1877.5-1877.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1348.5-1348.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1349.5-1349.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1350.11-1350.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1346.5-1346.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1333.11-1333.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1329.5-1329.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1330.5-1330.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1331.11-1331.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1332.11-1332.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1335.5-1335.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1351.5-1351.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1872.5-1872.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1873.5-1873.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1321.5-1321.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1316.5-1316.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1303.5-1303.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1278.5-1278.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1281.11-1281.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1282.5-1282.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1285.5-1285.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1286.5-1286.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1287.11-1287.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1284.5-1284.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1283.5-1283.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1301.5-1301.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1288.5-1288.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1302.5-1302.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1182.11-1182.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1856.11-1856.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1857.5-1857.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1177.5-1177.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1178.5-1178.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1179.5-1179.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1180.11-1180.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1181.5-1181.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1431.5-1431.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1434.11-1434.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:376.5-376.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:375.12-375.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:378.5-378.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:377.11-377.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:474.5-474.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:496.11-496.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:493.11-493.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:495.11-495.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:497.11-497.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:520.5-520.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:521.5-521.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:523.12-523.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:522.5-522.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:518.5-518.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:466.12-466.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:468.5-468.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:471.5-471.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:472.5-472.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:473.5-473.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:469.5-469.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:470.5-470.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:465.5-465.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:464.5-464.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:463.5-463.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:461.5-461.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:460.5-460.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:524.12-524.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:528.5-528.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:529.5-529.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:527.5-527.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:525.5-525.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:532.11-532.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:531.32-531.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:556.5-556.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:578.11-578.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:575.11-575.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:577.11-577.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:579.11-579.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:602.5-602.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:603.5-603.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:605.12-605.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:604.5-604.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:600.5-600.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:548.12-548.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:550.5-550.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:553.5-553.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:554.5-554.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:555.5-555.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:551.5-551.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:552.5-552.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:547.5-547.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:546.5-546.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:545.5-545.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:543.5-543.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:542.5-542.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:606.12-606.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:610.5-610.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:611.5-611.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:609.5-609.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:607.5-607.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:614.11-614.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:613.32-613.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:638.5-638.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:660.11-660.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:657.11-657.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:659.11-659.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:661.11-661.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:684.5-684.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:685.5-685.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:687.12-687.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:686.5-686.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:682.5-682.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:630.12-630.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:632.5-632.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:635.5-635.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:636.5-636.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:637.5-637.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:633.5-633.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:634.5-634.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:629.5-629.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:628.5-628.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:627.5-627.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:625.5-625.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:624.5-624.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:688.12-688.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:692.5-692.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:693.5-693.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:691.5-691.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:689.5-689.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:696.11-696.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:695.32-695.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:720.5-720.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:742.11-742.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:739.11-739.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:741.11-741.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:743.11-743.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:766.5-766.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:767.5-767.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:769.12-769.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:768.5-768.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:764.5-764.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:712.12-712.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:714.5-714.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:717.5-717.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:718.5-718.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:719.5-719.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:715.5-715.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:716.5-716.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:711.5-711.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:710.5-710.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:709.5-709.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:707.5-707.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:706.5-706.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:770.12-770.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:774.5-774.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:775.5-775.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:773.5-773.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:771.5-771.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:778.11-778.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:777.32-777.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:793.5-793.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:794.5-794.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:795.5-795.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:801.11-801.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:799.11-799.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:811.5-811.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:812.5-812.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:813.5-813.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:808.5-808.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:819.11-819.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:817.11-817.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:806.5-806.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:803.5-803.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:804.5-804.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:432.5-432.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:433.12-433.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:434.11-434.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:435.5-435.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:436.5-436.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:437.5-437.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:431.5-431.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:430.5-430.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:370.5-370.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:369.11-369.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:414.12-414.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:415.11-415.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:416.5-416.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:417.5-417.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:418.5-418.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:427.5-427.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:419.5-419.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:425.5-425.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:838.5-838.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:841.5-841.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:411.12-411.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:412.11-412.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:317.5-317.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:318.5-318.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:319.5-319.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:329.12-329.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:330.5-330.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:320.5-320.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:356.5-356.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:347.12-347.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:348.11-348.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:349.5-349.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:353.5-353.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:350.5-350.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:354.5-354.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:351.5-351.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:360.5-360.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:355.5-355.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:352.5-352.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:357.12-357.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:358.5-358.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:359.11-359.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:448.5-448.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:447.5-447.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:368.5-368.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:454.5-454.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:453.11-453.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:452.5-452.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:449.5-449.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:345.12-345.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:346.5-346.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:381.12-381.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:823.11-823.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:367.11-367.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:832.5-832.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:831.32-831.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:840.11-840.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:843.11-843.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:445.11-445.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:835.11-835.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:834.32-834.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:380.5-380.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:379.12-379.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:872.5-872.54" + wire $1\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:878.5-878.38" + wire $1\main_socbushandler_counter[0:0] + attribute \src "ls180.v:1807.5-1807.60" + wire $1\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1808.5-1808.63" + wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:880.12-880.44" + wire width 64 $1\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:877.5-877.35" + wire $1\main_socbushandler_skip[0:0] + attribute \src "ls180.v:1066.12-1066.44" + wire width 16 $1\main_spimaster11_storage[15:0] + attribute \src "ls180.v:1067.5-1067.31" + wire $1\main_spimaster12_re[0:0] + attribute \src "ls180.v:1071.11-1071.42" + wire width 8 $1\main_spimaster16_storage[7:0] + attribute \src "ls180.v:1072.5-1072.31" + wire $1\main_spimaster17_re[0:0] + attribute \src "ls180.v:1128.5-1128.30" + wire $1\main_spimaster1_re[0:0] + attribute \src "ls180.v:1127.12-1127.45" + wire width 16 $1\main_spimaster1_storage[15:0] + attribute \src "ls180.v:1076.5-1076.36" + wire $1\main_spimaster21_storage[0:0] + attribute \src "ls180.v:1077.5-1077.31" + wire $1\main_spimaster22_re[0:0] + attribute \src "ls180.v:1078.5-1078.36" + wire $1\main_spimaster23_storage[0:0] + attribute \src "ls180.v:1079.5-1079.31" + wire $1\main_spimaster24_re[0:0] + attribute \src "ls180.v:1080.5-1080.39" + wire $1\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:1081.5-1081.38" + wire $1\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:1082.11-1082.40" + wire width 3 $1\main_spimaster27_count[2:0] + attribute \src "ls180.v:1848.11-1848.62" + wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1849.5-1849.59" + wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:1083.5-1083.39" + wire $1\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:1084.5-1084.39" + wire $1\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:1057.5-1057.32" + wire $1\main_spimaster2_done[0:0] + attribute \src "ls180.v:1085.12-1085.48" + wire width 16 $1\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:1088.11-1088.44" + wire width 8 $1\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:1089.11-1089.43" + wire width 3 $1\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:1090.11-1090.44" + wire width 8 $1\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:1058.5-1058.31" + wire $1\main_spimaster3_irq[0:0] + attribute \src "ls180.v:1060.11-1060.38" + wire width 8 $1\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1064.5-1064.33" + wire $1\main_spimaster9_start[0:0] + attribute \src "ls180.v:1121.12-1121.47" + wire width 16 $1\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:1116.5-1116.37" + wire $1\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:1103.5-1103.37" + wire $1\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:1102.12-1102.50" + wire width 16 $1\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:1118.11-1118.38" + wire width 3 $1\main_spisdcard_count[2:0] + attribute \src "ls180.v:1852.11-1852.60" + wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1853.5-1853.57" + wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1117.5-1117.36" + wire $1\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:1113.5-1113.32" + wire $1\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:1112.5-1112.37" + wire $1\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:1093.5-1093.32" + wire $1\main_spisdcard_done0[0:0] + attribute \src "ls180.v:1094.5-1094.30" + wire $1\main_spisdcard_irq[0:0] + attribute \src "ls180.v:1115.5-1115.38" + wire $1\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:1114.5-1114.43" + wire $1\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:1096.11-1096.37" + wire width 8 $1\main_spisdcard_miso[7:0] + attribute \src "ls180.v:1126.11-1126.42" + wire width 8 $1\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:1120.5-1120.37" + wire $1\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:1124.11-1124.42" + wire width 8 $1\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:1119.5-1119.37" + wire $1\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:1108.5-1108.34" + wire $1\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:1125.11-1125.41" + wire width 3 $1\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:1107.11-1107.45" + wire width 8 $1\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:1100.5-1100.33" + wire $1\main_spisdcard_start1[0:0] + attribute \src "ls180.v:948.11-948.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:950.5-950.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:944.11-944.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:949.11-949.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:916.12-916.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:906.12-906.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:899.5-899.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:920.11-920.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:921.5-921.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:918.5-918.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:919.11-919.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:901.5-901.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:914.11-914.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:910.5-910.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:898.12-898.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:908.11-908.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:909.5-909.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:907.11-907.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:915.5-915.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:905.5-905.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:939.5-939.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:1023.11-1023.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:1020.11-1020.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:1022.11-1022.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:1013.5-1013.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:1024.11-1024.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:940.5-940.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:937.5-937.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:934.5-934.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:986.11-986.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:983.11-983.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:985.11-985.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:976.5-976.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:987.11-987.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:935.5-935.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:932.5-932.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:864.5-864.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:858.12-858.37" + wire width 30 $1\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:862.5-862.29" + wire $1\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:859.12-859.39" + wire width 32 $1\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:861.11-861.35" + wire width 4 $1\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:863.5-863.29" + wire $1\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:865.5-865.28" + wire $1\main_wb_sdram_we[0:0] + attribute \src "ls180.v:894.5-894.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2890.56-2890.86" + wire $add$ls180.v:2890$34_Y + attribute \src "ls180.v:2950.56-2950.86" + wire $add$ls180.v:2950$45_Y + attribute \src "ls180.v:3010.59-3010.92" + wire $add$ls180.v:3010$56_Y + attribute \src "ls180.v:4161.54-4161.83" + wire $add$ls180.v:4161$586_Y + attribute \src "ls180.v:4261.36-4261.89" + wire width 5 $add$ls180.v:4261$632_Y + attribute \src "ls180.v:4291.36-4291.89" + wire width 5 $add$ls180.v:4291$643_Y + attribute \src "ls180.v:4357.54-4357.83" + wire width 3 $add$ls180.v:4357$658_Y + attribute \src "ls180.v:4416.52-4416.79" + wire width 3 $add$ls180.v:4416$666_Y + attribute \src "ls180.v:4520.58-4520.86" + wire width 8 $add$ls180.v:4520$694_Y + attribute \src "ls180.v:4577.58-4577.86" + wire width 8 $add$ls180.v:4577$697_Y + attribute \src "ls180.v:4594.58-4594.86" + wire width 8 $add$ls180.v:4594$699_Y + attribute \src "ls180.v:4687.59-4687.87" + wire width 8 $add$ls180.v:4687$716_Y + attribute \src "ls180.v:4712.59-4712.87" + wire width 8 $add$ls180.v:4712$719_Y + attribute \src "ls180.v:4834.53-4834.82" + wire width 8 $add$ls180.v:4834$736_Y + attribute \src "ls180.v:4945.65-4945.114" + wire width 10 $add$ls180.v:4945$750_Y + attribute \src "ls180.v:4950.62-4950.91" + wire width 10 $add$ls180.v:4950$753_Y + attribute \src "ls180.v:4976.61-4976.90" + wire width 10 $add$ls180.v:4976$756_Y + attribute \src "ls180.v:5180.80-5180.117" + wire width 3 $add$ls180.v:5180$941_Y + attribute \src "ls180.v:5374.54-5374.82" + wire width 3 $add$ls180.v:5374$1016_Y + attribute \src "ls180.v:5426.55-5426.84" + wire width 32 $add$ls180.v:5426$1026_Y + attribute \src "ls180.v:5452.57-5452.86" + wire width 32 $add$ls180.v:5452$1034_Y + attribute \src "ls180.v:5573.51-5573.134" + wire width 32 $add$ls180.v:5573$1050_Y + attribute \src "ls180.v:5576.77-5576.125" + wire width 32 $add$ls180.v:5576$1052_Y + attribute \src "ls180.v:5669.50-5669.105" + wire width 32 $add$ls180.v:5669$1061_Y + attribute \src "ls180.v:5671.77-5671.111" + wire width 32 $add$ls180.v:5671$1062_Y + attribute \src "ls180.v:7651.36-7651.70" + wire width 32 $add$ls180.v:7651$2487_Y + attribute \src "ls180.v:7740.37-7740.72" + wire width 4 $add$ls180.v:7740$2511_Y + attribute \src "ls180.v:7757.60-7757.119" + wire width 3 $add$ls180.v:7757$2515_Y + attribute \src "ls180.v:7760.60-7760.119" + wire width 3 $add$ls180.v:7760$2516_Y + attribute \src "ls180.v:7764.59-7764.116" + wire width 4 $add$ls180.v:7764$2521_Y + attribute \src "ls180.v:7803.60-7803.119" + wire width 3 $add$ls180.v:7803$2531_Y + attribute \src "ls180.v:7806.60-7806.119" + wire width 3 $add$ls180.v:7806$2532_Y + attribute \src "ls180.v:7810.59-7810.116" + wire width 4 $add$ls180.v:7810$2537_Y + attribute \src "ls180.v:7849.60-7849.119" + wire width 3 $add$ls180.v:7849$2547_Y + attribute \src "ls180.v:7852.60-7852.119" + wire width 3 $add$ls180.v:7852$2548_Y + attribute \src "ls180.v:7856.59-7856.116" + wire width 4 $add$ls180.v:7856$2553_Y + attribute \src "ls180.v:7895.60-7895.119" + wire width 3 $add$ls180.v:7895$2563_Y + attribute \src "ls180.v:7898.60-7898.119" + wire width 3 $add$ls180.v:7898$2564_Y + attribute \src "ls180.v:7902.59-7902.116" + wire width 4 $add$ls180.v:7902$2569_Y + attribute \src "ls180.v:8132.34-8132.66" + wire width 4 $add$ls180.v:8132$2623_Y + attribute \src "ls180.v:8148.73-8148.131" + wire width 33 $add$ls180.v:8148$2626_Y + attribute \src "ls180.v:8161.34-8161.66" + wire width 4 $add$ls180.v:8161$2630_Y + attribute \src "ls180.v:8180.73-8180.131" + wire width 33 $add$ls180.v:8180$2633_Y + attribute \src "ls180.v:8206.33-8206.65" + wire width 4 $add$ls180.v:8206$2641_Y + attribute \src "ls180.v:8209.33-8209.65" + wire width 4 $add$ls180.v:8209$2642_Y + attribute \src "ls180.v:8213.33-8213.64" + wire width 5 $add$ls180.v:8213$2647_Y + attribute \src "ls180.v:8228.33-8228.65" + wire width 4 $add$ls180.v:8228$2652_Y + attribute \src "ls180.v:8231.33-8231.65" + wire width 4 $add$ls180.v:8231$2653_Y + attribute \src "ls180.v:8235.33-8235.64" + wire width 5 $add$ls180.v:8235$2658_Y + attribute \src "ls180.v:8256.35-8256.70" + wire width 16 $add$ls180.v:8256$2660_Y + attribute \src "ls180.v:8291.34-8291.68" + wire width 16 $add$ls180.v:8291$2665_Y + attribute \src "ls180.v:8327.25-8327.49" + wire width 32 $add$ls180.v:8327$2670_Y + attribute \src "ls180.v:8341.25-8341.49" + wire width 32 $add$ls180.v:8341$2674_Y + attribute \src "ls180.v:8355.31-8355.61" + wire width 9 $add$ls180.v:8355$2679_Y + attribute \src "ls180.v:8378.45-8378.88" + wire width 3 $add$ls180.v:8378$2683_Y + attribute \src "ls180.v:8424.71-8424.114" + wire width 4 $add$ls180.v:8424$2689_Y + attribute \src "ls180.v:8459.46-8459.90" + wire width 3 $add$ls180.v:8459$2695_Y + attribute \src "ls180.v:8505.72-8505.116" + wire width 4 $add$ls180.v:8505$2701_Y + attribute \src "ls180.v:8538.47-8538.92" + wire $add$ls180.v:8538$2707_Y + attribute \src "ls180.v:8566.73-8566.118" + wire width 2 $add$ls180.v:8566$2713_Y + attribute \src "ls180.v:8678.39-8678.75" + wire width 4 $add$ls180.v:8678$2726_Y + attribute \src "ls180.v:8739.37-8739.73" + wire width 5 $add$ls180.v:8739$2730_Y + attribute \src "ls180.v:8742.37-8742.73" + wire width 5 $add$ls180.v:8742$2731_Y + attribute \src "ls180.v:8746.36-8746.70" + wire width 6 $add$ls180.v:8746$2736_Y + attribute \src "ls180.v:8761.41-8761.80" + wire width 3 $add$ls180.v:8761$2740_Y + attribute \src "ls180.v:8807.67-8807.106" + wire width 4 $add$ls180.v:8807$2746_Y + attribute \src "ls180.v:8833.39-8833.76" + wire width 3 $add$ls180.v:8833$2748_Y + attribute \src "ls180.v:8837.37-8837.73" + wire width 5 $add$ls180.v:8837$2752_Y + attribute \src "ls180.v:8840.37-8840.73" + wire width 5 $add$ls180.v:8840$2753_Y + attribute \src "ls180.v:8844.36-8844.70" + wire width 6 $add$ls180.v:8844$2758_Y + attribute \src "ls180.v:2884.9-2884.90" + wire $and$ls180.v:2884$29_Y + attribute \src "ls180.v:2902.9-2902.90" + wire $and$ls180.v:2902$36_Y + attribute \src "ls180.v:2944.9-2944.90" + wire $and$ls180.v:2944$40_Y + attribute \src "ls180.v:2962.9-2962.90" + wire $and$ls180.v:2962$47_Y + attribute \src "ls180.v:3004.9-3004.96" + wire $and$ls180.v:3004$51_Y + attribute \src "ls180.v:3022.9-3022.96" + wire $and$ls180.v:3022$58_Y + attribute \src "ls180.v:3032.31-3032.90" + wire $and$ls180.v:3032$60_Y + attribute \src "ls180.v:3032.30-3032.121" + wire $and$ls180.v:3032$61_Y + attribute \src "ls180.v:3032.29-3032.156" + wire $and$ls180.v:3032$62_Y + attribute \src "ls180.v:3033.31-3033.90" + wire $and$ls180.v:3033$63_Y + attribute \src "ls180.v:3033.30-3033.121" + wire $and$ls180.v:3033$64_Y + attribute \src "ls180.v:3033.29-3033.156" + wire $and$ls180.v:3033$65_Y + attribute \src "ls180.v:3034.31-3034.90" + wire $and$ls180.v:3034$66_Y + attribute \src "ls180.v:3034.30-3034.121" + wire $and$ls180.v:3034$67_Y + attribute \src "ls180.v:3034.29-3034.156" + wire $and$ls180.v:3034$68_Y + attribute \src "ls180.v:3035.31-3035.90" + wire $and$ls180.v:3035$69_Y + attribute \src "ls180.v:3035.30-3035.121" + wire $and$ls180.v:3035$70_Y + attribute \src "ls180.v:3035.29-3035.156" + wire $and$ls180.v:3035$71_Y + attribute \src "ls180.v:3036.31-3036.90" + wire $and$ls180.v:3036$72_Y + attribute \src "ls180.v:3036.30-3036.121" + wire $and$ls180.v:3036$73_Y + attribute \src "ls180.v:3036.29-3036.156" + wire $and$ls180.v:3036$74_Y + attribute \src "ls180.v:3037.31-3037.90" + wire $and$ls180.v:3037$75_Y + attribute \src "ls180.v:3037.30-3037.121" + wire $and$ls180.v:3037$76_Y + attribute \src "ls180.v:3037.29-3037.156" + wire $and$ls180.v:3037$77_Y + attribute \src "ls180.v:3038.31-3038.90" + wire $and$ls180.v:3038$78_Y + attribute \src "ls180.v:3038.30-3038.121" + wire $and$ls180.v:3038$79_Y + attribute \src "ls180.v:3038.29-3038.156" + wire $and$ls180.v:3038$80_Y + attribute \src "ls180.v:3039.31-3039.90" + wire $and$ls180.v:3039$81_Y + attribute \src "ls180.v:3039.30-3039.121" + wire $and$ls180.v:3039$82_Y + attribute \src "ls180.v:3039.29-3039.156" + wire $and$ls180.v:3039$83_Y + attribute \src "ls180.v:3048.7-3048.89" + wire $and$ls180.v:3048$86_Y + attribute \src "ls180.v:3053.32-3053.111" + wire $and$ls180.v:3053$87_Y + attribute \src "ls180.v:3057.23-3057.74" + wire $and$ls180.v:3057$89_Y + attribute \src "ls180.v:3057.22-3057.101" + wire $and$ls180.v:3057$90_Y + attribute \src "ls180.v:3057.21-3057.132" + wire $and$ls180.v:3057$91_Y + attribute \src "ls180.v:3058.23-3058.74" + wire $and$ls180.v:3058$92_Y + attribute \src "ls180.v:3058.22-3058.101" + wire $and$ls180.v:3058$93_Y + attribute \src "ls180.v:3058.21-3058.132" + wire $and$ls180.v:3058$94_Y + attribute \src "ls180.v:3059.23-3059.74" + wire $and$ls180.v:3059$95_Y + attribute \src "ls180.v:3059.22-3059.101" + wire $and$ls180.v:3059$96_Y + attribute \src "ls180.v:3059.21-3059.132" + wire $and$ls180.v:3059$97_Y + attribute \src "ls180.v:3060.21-3060.132" + wire $and$ls180.v:3060$100_Y + attribute \src "ls180.v:3060.23-3060.74" + wire $and$ls180.v:3060$98_Y + attribute \src "ls180.v:3060.22-3060.101" + wire $and$ls180.v:3060$99_Y + attribute \src "ls180.v:3061.23-3061.74" + wire $and$ls180.v:3061$101_Y + attribute \src "ls180.v:3061.22-3061.101" + wire $and$ls180.v:3061$102_Y + attribute \src "ls180.v:3061.21-3061.132" + wire $and$ls180.v:3061$103_Y + attribute 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"ls180.v:4714.10-4714.39" + wire $eq$ls180.v:4714$720_Y + attribute \src "ls180.v:4751.39-4751.94" + wire $eq$ls180.v:4751$724_Y + attribute \src "ls180.v:4788.32-4788.89" + wire $eq$ls180.v:4788$733_Y + attribute \src "ls180.v:4836.10-4836.40" + wire $eq$ls180.v:4836$737_Y + attribute \src "ls180.v:4885.40-4885.98" + wire $eq$ls180.v:4885$739_Y + attribute \src "ls180.v:4936.9-4936.41" + wire $eq$ls180.v:4936$749_Y + attribute \src "ls180.v:4945.37-4945.123" + wire $eq$ls180.v:4945$752_Y + attribute \src "ls180.v:4968.9-4968.41" + wire $eq$ls180.v:4968$755_Y + attribute \src "ls180.v:4978.10-4978.41" + wire $eq$ls180.v:4978$757_Y + attribute \src "ls180.v:5147.9-5147.47" + wire $eq$ls180.v:5147$939_Y + attribute \src "ls180.v:5177.10-5177.48" + wire $eq$ls180.v:5177$940_Y + attribute \src "ls180.v:5208.10-5208.78" + wire $eq$ls180.v:5208$945_Y + attribute \src "ls180.v:5208.83-5208.151" + wire $eq$ls180.v:5208$946_Y + attribute \src "ls180.v:5208.157-5208.225" + wire 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$eq$ls180.v:5815$1088_Y + attribute \src "ls180.v:5816.68-5816.89" + wire $eq$ls180.v:5816$1090_Y + attribute \src "ls180.v:5817.68-5817.89" + wire $eq$ls180.v:5817$1092_Y + attribute \src "ls180.v:5818.71-5818.92" + wire $eq$ls180.v:5818$1094_Y + attribute \src "ls180.v:5819.57-5819.78" + wire $eq$ls180.v:5819$1096_Y + attribute \src "ls180.v:5820.57-5820.78" + wire $eq$ls180.v:5820$1098_Y + attribute \src "ls180.v:5824.27-5824.59" + wire $eq$ls180.v:5824$1101_Y + attribute \src "ls180.v:5825.27-5825.60" + wire $eq$ls180.v:5825$1102_Y + attribute \src "ls180.v:5826.27-5826.68" + wire $eq$ls180.v:5826$1103_Y + attribute \src "ls180.v:5827.27-5827.65" + wire $eq$ls180.v:5827$1104_Y + attribute \src "ls180.v:5828.27-5828.59" + wire $eq$ls180.v:5828$1105_Y + attribute \src "ls180.v:5829.27-5829.59" + wire $eq$ls180.v:5829$1106_Y + attribute \src "ls180.v:5830.27-5830.59" + wire $eq$ls180.v:5830$1107_Y + attribute \src "ls180.v:5831.27-5831.59" + wire $eq$ls180.v:5831$1108_Y + attribute \src "ls180.v:5832.27-5832.61" + wire $eq$ls180.v:5832$1109_Y + attribute \src "ls180.v:5833.27-5833.65" + wire $eq$ls180.v:5833$1110_Y + attribute \src "ls180.v:5929.24-5929.45" + wire $eq$ls180.v:5929$1162_Y + attribute \src "ls180.v:5930.32-5930.77" + wire $eq$ls180.v:5930$1163_Y + attribute \src "ls180.v:5932.97-5932.141" + wire $eq$ls180.v:5932$1165_Y + attribute \src "ls180.v:5933.100-5933.144" + wire $eq$ls180.v:5933$1169_Y + attribute \src "ls180.v:5935.99-5935.143" + wire $eq$ls180.v:5935$1172_Y + attribute \src "ls180.v:5936.102-5936.146" + wire $eq$ls180.v:5936$1176_Y + attribute \src "ls180.v:5938.99-5938.143" + wire $eq$ls180.v:5938$1179_Y + attribute \src "ls180.v:5939.102-5939.146" + wire $eq$ls180.v:5939$1183_Y + attribute \src "ls180.v:5941.99-5941.143" + wire $eq$ls180.v:5941$1186_Y + attribute \src "ls180.v:5942.102-5942.146" + wire $eq$ls180.v:5942$1190_Y + attribute \src "ls180.v:5944.99-5944.143" + wire $eq$ls180.v:5944$1193_Y + attribute \src "ls180.v:5945.102-5945.146" + wire $eq$ls180.v:5945$1197_Y + attribute \src "ls180.v:5947.102-5947.146" + wire $eq$ls180.v:5947$1200_Y + attribute \src "ls180.v:5948.105-5948.149" + wire $eq$ls180.v:5948$1204_Y + attribute \src "ls180.v:5950.102-5950.146" + wire $eq$ls180.v:5950$1207_Y + attribute \src "ls180.v:5951.105-5951.149" + wire $eq$ls180.v:5951$1211_Y + attribute \src "ls180.v:5953.102-5953.146" + wire $eq$ls180.v:5953$1214_Y + attribute \src "ls180.v:5954.105-5954.149" + wire $eq$ls180.v:5954$1218_Y + attribute \src "ls180.v:5956.102-5956.146" + wire $eq$ls180.v:5956$1221_Y + attribute \src "ls180.v:5957.105-5957.149" + wire $eq$ls180.v:5957$1225_Y + attribute \src "ls180.v:5968.32-5968.77" + wire $eq$ls180.v:5968$1227_Y + attribute \src "ls180.v:5970.94-5970.138" + wire $eq$ls180.v:5970$1229_Y + attribute \src "ls180.v:5971.97-5971.141" + wire $eq$ls180.v:5971$1233_Y + attribute \src "ls180.v:5973.94-5973.138" + wire $eq$ls180.v:5973$1236_Y + attribute \src "ls180.v:5974.97-5974.141" + wire $eq$ls180.v:5974$1240_Y + attribute \src "ls180.v:5976.94-5976.138" + wire $eq$ls180.v:5976$1243_Y + attribute \src "ls180.v:5977.97-5977.141" + wire $eq$ls180.v:5977$1247_Y + attribute \src "ls180.v:5979.94-5979.138" + wire $eq$ls180.v:5979$1250_Y + attribute \src "ls180.v:5980.97-5980.141" + wire $eq$ls180.v:5980$1254_Y + attribute \src "ls180.v:5982.95-5982.139" + wire $eq$ls180.v:5982$1257_Y + attribute \src "ls180.v:5983.98-5983.142" + wire $eq$ls180.v:5983$1261_Y + attribute \src "ls180.v:5985.95-5985.139" + wire $eq$ls180.v:5985$1264_Y + attribute \src "ls180.v:5986.98-5986.142" + wire $eq$ls180.v:5986$1268_Y + attribute \src "ls180.v:5994.32-5994.78" + wire $eq$ls180.v:5994$1270_Y + attribute \src "ls180.v:5996.93-5996.135" + wire $eq$ls180.v:5996$1272_Y + attribute \src "ls180.v:5997.96-5997.138" + wire $eq$ls180.v:5997$1276_Y + attribute \src "ls180.v:5999.92-5999.134" + wire $eq$ls180.v:5999$1279_Y + attribute \src "ls180.v:6000.95-6000.137" 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$eq$ls180.v:6026$1326_Y + attribute \src "ls180.v:6028.98-6028.142" + wire $eq$ls180.v:6028$1329_Y + attribute \src "ls180.v:6029.101-6029.145" + wire $eq$ls180.v:6029$1333_Y + attribute \src "ls180.v:6031.98-6031.142" + wire $eq$ls180.v:6031$1336_Y + attribute \src "ls180.v:6032.101-6032.145" + wire $eq$ls180.v:6032$1340_Y + attribute \src "ls180.v:6034.98-6034.142" + wire $eq$ls180.v:6034$1343_Y + attribute \src "ls180.v:6035.101-6035.145" + wire $eq$ls180.v:6035$1347_Y + attribute \src "ls180.v:6045.32-6045.78" + wire $eq$ls180.v:6045$1349_Y + attribute \src "ls180.v:6047.98-6047.142" + wire $eq$ls180.v:6047$1351_Y + attribute \src "ls180.v:6048.101-6048.145" + wire $eq$ls180.v:6048$1355_Y + attribute \src "ls180.v:6050.97-6050.141" + wire $eq$ls180.v:6050$1358_Y + attribute \src "ls180.v:6051.100-6051.144" + wire $eq$ls180.v:6051$1362_Y + attribute \src "ls180.v:6053.97-6053.141" + wire $eq$ls180.v:6053$1365_Y + attribute \src "ls180.v:6054.100-6054.144" + wire $eq$ls180.v:6054$1369_Y + attribute \src "ls180.v:6056.97-6056.141" + wire $eq$ls180.v:6056$1372_Y + attribute \src "ls180.v:6057.100-6057.144" + wire $eq$ls180.v:6057$1376_Y + attribute \src "ls180.v:6059.97-6059.141" + wire $eq$ls180.v:6059$1379_Y + attribute \src "ls180.v:6060.100-6060.144" + wire $eq$ls180.v:6060$1383_Y + attribute \src "ls180.v:6062.98-6062.142" + wire $eq$ls180.v:6062$1386_Y + attribute \src "ls180.v:6063.101-6063.145" + wire $eq$ls180.v:6063$1390_Y + attribute \src "ls180.v:6065.98-6065.142" + wire $eq$ls180.v:6065$1393_Y + attribute \src "ls180.v:6066.101-6066.145" + wire $eq$ls180.v:6066$1397_Y + attribute \src "ls180.v:6068.98-6068.142" + wire $eq$ls180.v:6068$1400_Y + attribute \src "ls180.v:6069.101-6069.145" + wire $eq$ls180.v:6069$1404_Y + attribute \src "ls180.v:6071.98-6071.142" + wire $eq$ls180.v:6071$1407_Y + attribute \src "ls180.v:6072.101-6072.145" + wire $eq$ls180.v:6072$1411_Y + attribute \src "ls180.v:6082.32-6082.78" + wire $eq$ls180.v:6082$1413_Y + attribute \src "ls180.v:6084.100-6084.144" + wire $eq$ls180.v:6084$1415_Y + attribute \src "ls180.v:6085.103-6085.147" + wire $eq$ls180.v:6085$1419_Y + attribute \src "ls180.v:6087.100-6087.144" + wire $eq$ls180.v:6087$1422_Y + attribute \src "ls180.v:6088.103-6088.147" + wire $eq$ls180.v:6088$1426_Y + attribute \src "ls180.v:6090.100-6090.144" + wire $eq$ls180.v:6090$1429_Y + attribute \src "ls180.v:6091.103-6091.147" + wire $eq$ls180.v:6091$1433_Y + attribute \src "ls180.v:6093.100-6093.144" + wire $eq$ls180.v:6093$1436_Y + attribute \src "ls180.v:6094.103-6094.147" + wire $eq$ls180.v:6094$1440_Y + attribute \src "ls180.v:6096.100-6096.144" + wire $eq$ls180.v:6096$1443_Y + attribute \src "ls180.v:6097.103-6097.147" + wire $eq$ls180.v:6097$1447_Y + attribute \src "ls180.v:6099.100-6099.144" + wire $eq$ls180.v:6099$1450_Y + attribute \src "ls180.v:6100.103-6100.147" + wire $eq$ls180.v:6100$1454_Y + attribute \src "ls180.v:6102.100-6102.144" + wire $eq$ls180.v:6102$1457_Y + attribute \src "ls180.v:6103.103-6103.147" + wire $eq$ls180.v:6103$1461_Y + attribute \src "ls180.v:6105.100-6105.144" + wire $eq$ls180.v:6105$1464_Y + attribute \src "ls180.v:6106.103-6106.147" + wire $eq$ls180.v:6106$1468_Y + attribute \src "ls180.v:6108.102-6108.146" + wire $eq$ls180.v:6108$1471_Y + attribute \src "ls180.v:6109.105-6109.149" + wire $eq$ls180.v:6109$1475_Y + attribute \src "ls180.v:6111.102-6111.146" + wire $eq$ls180.v:6111$1478_Y + attribute \src "ls180.v:6112.105-6112.149" + wire $eq$ls180.v:6112$1482_Y + attribute \src "ls180.v:6114.102-6114.147" + wire $eq$ls180.v:6114$1485_Y + attribute \src "ls180.v:6115.105-6115.150" + wire $eq$ls180.v:6115$1489_Y + attribute \src "ls180.v:6117.102-6117.147" + wire $eq$ls180.v:6117$1492_Y + attribute \src "ls180.v:6118.105-6118.150" + wire $eq$ls180.v:6118$1496_Y + attribute \src "ls180.v:6120.102-6120.147" + wire $eq$ls180.v:6120$1499_Y + attribute \src "ls180.v:6121.105-6121.150" + wire $eq$ls180.v:6121$1503_Y + attribute \src "ls180.v:6123.99-6123.144" + wire $eq$ls180.v:6123$1506_Y + attribute \src "ls180.v:6124.102-6124.147" + wire $eq$ls180.v:6124$1510_Y + attribute \src "ls180.v:6126.100-6126.145" + wire $eq$ls180.v:6126$1513_Y + attribute \src "ls180.v:6127.103-6127.148" + wire $eq$ls180.v:6127$1517_Y + attribute \src "ls180.v:6144.32-6144.78" + wire $eq$ls180.v:6144$1519_Y + attribute \src "ls180.v:6146.104-6146.148" + wire $eq$ls180.v:6146$1521_Y + attribute \src "ls180.v:6147.107-6147.151" + wire $eq$ls180.v:6147$1525_Y + attribute \src "ls180.v:6149.104-6149.148" + wire $eq$ls180.v:6149$1528_Y + attribute \src "ls180.v:6150.107-6150.151" + wire $eq$ls180.v:6150$1532_Y + attribute \src "ls180.v:6152.104-6152.148" + wire $eq$ls180.v:6152$1535_Y + attribute \src "ls180.v:6153.107-6153.151" + wire $eq$ls180.v:6153$1539_Y + attribute \src "ls180.v:6155.104-6155.148" + wire $eq$ls180.v:6155$1542_Y + attribute \src "ls180.v:6156.107-6156.151" + wire $eq$ls180.v:6156$1546_Y + attribute \src "ls180.v:6158.103-6158.147" + wire $eq$ls180.v:6158$1549_Y + attribute \src "ls180.v:6159.106-6159.150" + wire $eq$ls180.v:6159$1553_Y + attribute \src "ls180.v:6161.103-6161.147" + wire $eq$ls180.v:6161$1556_Y + attribute \src "ls180.v:6162.106-6162.150" + wire $eq$ls180.v:6162$1560_Y + attribute \src "ls180.v:6164.103-6164.147" + wire $eq$ls180.v:6164$1563_Y + attribute \src "ls180.v:6165.106-6165.150" + wire $eq$ls180.v:6165$1567_Y + attribute \src "ls180.v:6167.103-6167.147" + wire $eq$ls180.v:6167$1570_Y + attribute \src "ls180.v:6168.106-6168.150" + wire $eq$ls180.v:6168$1574_Y + attribute \src "ls180.v:6170.94-6170.138" + wire $eq$ls180.v:6170$1577_Y + attribute \src "ls180.v:6171.97-6171.141" + wire $eq$ls180.v:6171$1581_Y + attribute \src "ls180.v:6173.105-6173.149" + wire $eq$ls180.v:6173$1584_Y + attribute \src "ls180.v:6174.108-6174.152" + wire $eq$ls180.v:6174$1588_Y + attribute \src "ls180.v:6176.105-6176.150" + wire $eq$ls180.v:6176$1591_Y + attribute \src "ls180.v:6177.108-6177.153" + wire $eq$ls180.v:6177$1595_Y + attribute \src "ls180.v:6179.105-6179.150" + wire $eq$ls180.v:6179$1598_Y + attribute \src "ls180.v:6180.108-6180.153" + wire $eq$ls180.v:6180$1602_Y + attribute \src "ls180.v:6182.105-6182.150" + wire $eq$ls180.v:6182$1605_Y + attribute \src "ls180.v:6183.108-6183.153" + wire $eq$ls180.v:6183$1609_Y + attribute \src "ls180.v:6185.105-6185.150" + wire $eq$ls180.v:6185$1612_Y + attribute \src "ls180.v:6186.108-6186.153" + wire $eq$ls180.v:6186$1616_Y + attribute \src "ls180.v:6188.105-6188.150" + wire $eq$ls180.v:6188$1619_Y + attribute \src "ls180.v:6189.108-6189.153" + wire $eq$ls180.v:6189$1623_Y + attribute \src "ls180.v:6191.104-6191.149" + wire $eq$ls180.v:6191$1626_Y + attribute \src "ls180.v:6192.107-6192.152" + wire $eq$ls180.v:6192$1630_Y + attribute \src "ls180.v:6194.104-6194.149" + wire $eq$ls180.v:6194$1633_Y + attribute \src "ls180.v:6195.107-6195.152" + wire $eq$ls180.v:6195$1637_Y + attribute \src "ls180.v:6197.104-6197.149" + wire $eq$ls180.v:6197$1640_Y + attribute \src "ls180.v:6198.107-6198.152" + wire $eq$ls180.v:6198$1644_Y + attribute \src "ls180.v:6200.104-6200.149" + wire $eq$ls180.v:6200$1647_Y + attribute \src "ls180.v:6201.107-6201.152" + wire $eq$ls180.v:6201$1651_Y + attribute \src "ls180.v:6203.104-6203.149" + wire $eq$ls180.v:6203$1654_Y + attribute \src "ls180.v:6204.107-6204.152" + wire $eq$ls180.v:6204$1658_Y + attribute \src "ls180.v:6206.104-6206.149" + wire $eq$ls180.v:6206$1661_Y + attribute \src "ls180.v:6207.107-6207.152" + wire $eq$ls180.v:6207$1665_Y + attribute \src "ls180.v:6209.104-6209.149" + wire $eq$ls180.v:6209$1668_Y + attribute \src "ls180.v:6210.107-6210.152" + wire $eq$ls180.v:6210$1672_Y + attribute \src "ls180.v:6212.104-6212.149" + wire $eq$ls180.v:6212$1675_Y + attribute \src "ls180.v:6213.107-6213.152" + wire $eq$ls180.v:6213$1679_Y + attribute \src "ls180.v:6215.104-6215.149" + wire $eq$ls180.v:6215$1682_Y + attribute \src "ls180.v:6216.107-6216.152" + wire $eq$ls180.v:6216$1686_Y + attribute \src "ls180.v:6218.104-6218.149" + wire $eq$ls180.v:6218$1689_Y + attribute \src "ls180.v:6219.107-6219.152" + wire $eq$ls180.v:6219$1693_Y + attribute \src "ls180.v:6221.100-6221.145" + wire $eq$ls180.v:6221$1696_Y + attribute \src "ls180.v:6222.103-6222.148" + wire $eq$ls180.v:6222$1700_Y + attribute \src "ls180.v:6224.101-6224.146" + wire $eq$ls180.v:6224$1703_Y + attribute \src "ls180.v:6225.104-6225.149" + wire $eq$ls180.v:6225$1707_Y + attribute \src "ls180.v:6227.104-6227.149" + wire $eq$ls180.v:6227$1710_Y + attribute \src "ls180.v:6228.107-6228.152" + wire $eq$ls180.v:6228$1714_Y + attribute \src "ls180.v:6230.104-6230.149" + wire $eq$ls180.v:6230$1717_Y + attribute \src "ls180.v:6231.107-6231.152" + wire $eq$ls180.v:6231$1721_Y + attribute \src "ls180.v:6233.103-6233.148" + wire $eq$ls180.v:6233$1724_Y + attribute \src "ls180.v:6234.106-6234.151" + wire $eq$ls180.v:6234$1728_Y + attribute \src "ls180.v:6236.103-6236.148" + wire $eq$ls180.v:6236$1731_Y + attribute \src "ls180.v:6237.106-6237.151" + wire $eq$ls180.v:6237$1735_Y + attribute \src "ls180.v:6239.103-6239.148" + wire $eq$ls180.v:6239$1738_Y + attribute \src "ls180.v:6240.106-6240.151" + wire $eq$ls180.v:6240$1742_Y + attribute \src "ls180.v:6242.103-6242.148" + wire $eq$ls180.v:6242$1745_Y + attribute \src "ls180.v:6243.106-6243.151" + wire $eq$ls180.v:6243$1749_Y + attribute \src "ls180.v:6279.32-6279.78" + wire $eq$ls180.v:6279$1751_Y + attribute \src "ls180.v:6281.100-6281.144" + wire $eq$ls180.v:6281$1753_Y + attribute \src "ls180.v:6282.103-6282.147" + wire $eq$ls180.v:6282$1757_Y + attribute \src "ls180.v:6284.100-6284.144" + wire $eq$ls180.v:6284$1760_Y + attribute \src "ls180.v:6285.103-6285.147" + wire $eq$ls180.v:6285$1764_Y + attribute \src "ls180.v:6287.100-6287.144" + wire $eq$ls180.v:6287$1767_Y + attribute \src "ls180.v:6288.103-6288.147" + wire $eq$ls180.v:6288$1771_Y + attribute \src "ls180.v:6290.100-6290.144" + wire $eq$ls180.v:6290$1774_Y + attribute \src "ls180.v:6291.103-6291.147" + wire $eq$ls180.v:6291$1778_Y + attribute \src "ls180.v:6293.100-6293.144" + wire $eq$ls180.v:6293$1781_Y + attribute \src "ls180.v:6294.103-6294.147" + wire $eq$ls180.v:6294$1785_Y + attribute \src "ls180.v:6296.100-6296.144" + wire $eq$ls180.v:6296$1788_Y + attribute \src "ls180.v:6297.103-6297.147" + wire $eq$ls180.v:6297$1792_Y + attribute \src "ls180.v:6299.100-6299.144" + wire $eq$ls180.v:6299$1795_Y + attribute \src "ls180.v:6300.103-6300.147" + wire $eq$ls180.v:6300$1799_Y + attribute \src "ls180.v:6302.100-6302.144" + wire $eq$ls180.v:6302$1802_Y + attribute \src "ls180.v:6303.103-6303.147" + wire $eq$ls180.v:6303$1806_Y + attribute \src "ls180.v:6305.102-6305.146" + wire $eq$ls180.v:6305$1809_Y + attribute \src "ls180.v:6306.105-6306.149" + wire $eq$ls180.v:6306$1813_Y + attribute \src "ls180.v:6308.102-6308.146" + wire $eq$ls180.v:6308$1816_Y + attribute \src "ls180.v:6309.105-6309.149" + wire $eq$ls180.v:6309$1820_Y + attribute \src "ls180.v:6311.102-6311.147" + wire $eq$ls180.v:6311$1823_Y + attribute \src "ls180.v:6312.105-6312.150" + wire $eq$ls180.v:6312$1827_Y + attribute \src "ls180.v:6314.102-6314.147" + wire $eq$ls180.v:6314$1830_Y + attribute \src "ls180.v:6315.105-6315.150" + wire $eq$ls180.v:6315$1834_Y + attribute \src "ls180.v:6317.102-6317.147" + wire $eq$ls180.v:6317$1837_Y + attribute \src "ls180.v:6318.105-6318.150" + wire $eq$ls180.v:6318$1841_Y + attribute \src "ls180.v:6320.99-6320.144" + wire $eq$ls180.v:6320$1844_Y + attribute \src "ls180.v:6321.102-6321.147" + wire $eq$ls180.v:6321$1848_Y + attribute \src "ls180.v:6323.100-6323.145" + wire $eq$ls180.v:6323$1851_Y + attribute \src "ls180.v:6324.103-6324.148" + wire $eq$ls180.v:6324$1855_Y + attribute \src "ls180.v:6326.102-6326.147" + wire $eq$ls180.v:6326$1858_Y + attribute \src "ls180.v:6327.105-6327.150" + wire $eq$ls180.v:6327$1862_Y + attribute \src "ls180.v:6329.102-6329.147" + wire $eq$ls180.v:6329$1865_Y + attribute \src "ls180.v:6330.105-6330.150" + wire $eq$ls180.v:6330$1869_Y + attribute \src "ls180.v:6332.102-6332.147" + wire $eq$ls180.v:6332$1872_Y + attribute \src "ls180.v:6333.105-6333.150" + wire $eq$ls180.v:6333$1876_Y + attribute \src "ls180.v:6335.102-6335.147" + wire $eq$ls180.v:6335$1879_Y + attribute \src "ls180.v:6336.105-6336.150" + wire $eq$ls180.v:6336$1883_Y + attribute \src "ls180.v:6358.32-6358.78" + wire $eq$ls180.v:6358$1885_Y + attribute \src "ls180.v:6360.102-6360.146" + wire $eq$ls180.v:6360$1887_Y + attribute \src "ls180.v:6361.105-6361.149" + wire $eq$ls180.v:6361$1891_Y + attribute \src "ls180.v:6363.107-6363.151" + wire $eq$ls180.v:6363$1894_Y + attribute \src "ls180.v:6364.110-6364.154" + wire $eq$ls180.v:6364$1898_Y + attribute \src "ls180.v:6366.107-6366.151" + wire $eq$ls180.v:6366$1901_Y + attribute \src "ls180.v:6367.110-6367.154" + wire $eq$ls180.v:6367$1905_Y + attribute \src "ls180.v:6369.100-6369.144" + wire $eq$ls180.v:6369$1908_Y + attribute \src "ls180.v:6370.103-6370.147" + wire $eq$ls180.v:6370$1912_Y + attribute \src "ls180.v:6375.32-6375.77" + wire $eq$ls180.v:6375$1914_Y + attribute \src "ls180.v:6377.104-6377.148" + wire $eq$ls180.v:6377$1916_Y + attribute \src "ls180.v:6378.107-6378.151" + wire $eq$ls180.v:6378$1920_Y + attribute \src "ls180.v:6380.108-6380.152" + wire $eq$ls180.v:6380$1923_Y + attribute \src "ls180.v:6381.111-6381.155" + wire $eq$ls180.v:6381$1927_Y + attribute \src "ls180.v:6383.98-6383.142" + wire $eq$ls180.v:6383$1930_Y + attribute \src "ls180.v:6384.101-6384.145" + wire $eq$ls180.v:6384$1934_Y + attribute \src "ls180.v:6386.108-6386.152" + wire $eq$ls180.v:6386$1937_Y + attribute \src "ls180.v:6387.111-6387.155" + wire $eq$ls180.v:6387$1941_Y + attribute \src "ls180.v:6389.108-6389.152" + wire $eq$ls180.v:6389$1944_Y + attribute \src "ls180.v:6390.111-6390.155" + wire $eq$ls180.v:6390$1948_Y + attribute \src "ls180.v:6392.109-6392.153" + wire $eq$ls180.v:6392$1951_Y + attribute \src "ls180.v:6393.112-6393.156" + wire $eq$ls180.v:6393$1955_Y + attribute \src "ls180.v:6395.107-6395.151" + wire $eq$ls180.v:6395$1958_Y + attribute \src "ls180.v:6396.110-6396.154" + wire $eq$ls180.v:6396$1962_Y + attribute \src "ls180.v:6398.107-6398.151" + wire $eq$ls180.v:6398$1965_Y + attribute \src "ls180.v:6399.110-6399.154" + wire $eq$ls180.v:6399$1969_Y + attribute \src "ls180.v:6401.107-6401.151" + wire $eq$ls180.v:6401$1972_Y + attribute \src "ls180.v:6402.110-6402.154" + wire $eq$ls180.v:6402$1976_Y + attribute \src "ls180.v:6404.107-6404.151" + wire $eq$ls180.v:6404$1979_Y + attribute \src "ls180.v:6405.110-6405.154" + wire $eq$ls180.v:6405$1983_Y + attribute \src "ls180.v:6420.33-6420.79" + wire $eq$ls180.v:6420$1985_Y + attribute \src "ls180.v:6422.102-6422.147" + wire $eq$ls180.v:6422$1987_Y + attribute \src "ls180.v:6423.105-6423.150" + wire $eq$ls180.v:6423$1991_Y + attribute \src "ls180.v:6425.102-6425.147" + wire $eq$ls180.v:6425$1994_Y + attribute \src "ls180.v:6426.105-6426.150" + wire $eq$ls180.v:6426$1998_Y + attribute \src "ls180.v:6428.100-6428.145" + wire $eq$ls180.v:6428$2001_Y + attribute \src "ls180.v:6429.103-6429.148" + wire $eq$ls180.v:6429$2005_Y + attribute \src "ls180.v:6431.99-6431.144" + wire $eq$ls180.v:6431$2008_Y + attribute \src "ls180.v:6432.102-6432.147" + wire $eq$ls180.v:6432$2012_Y + attribute \src "ls180.v:6434.98-6434.143" + wire $eq$ls180.v:6434$2015_Y + attribute \src "ls180.v:6435.101-6435.146" + wire $eq$ls180.v:6435$2019_Y + attribute \src "ls180.v:6437.97-6437.142" + wire $eq$ls180.v:6437$2022_Y + attribute \src "ls180.v:6438.100-6438.145" + wire $eq$ls180.v:6438$2026_Y + attribute \src "ls180.v:6440.103-6440.148" + wire $eq$ls180.v:6440$2029_Y + attribute \src "ls180.v:6441.106-6441.151" + wire $eq$ls180.v:6441$2033_Y + attribute \src "ls180.v:6460.33-6460.79" + wire $eq$ls180.v:6460$2036_Y + attribute \src "ls180.v:6462.102-6462.147" + wire $eq$ls180.v:6462$2038_Y + attribute \src "ls180.v:6463.105-6463.150" + wire $eq$ls180.v:6463$2042_Y + attribute \src "ls180.v:6465.102-6465.147" + wire $eq$ls180.v:6465$2045_Y + attribute \src "ls180.v:6466.105-6466.150" + wire $eq$ls180.v:6466$2049_Y + attribute \src "ls180.v:6468.100-6468.145" + wire $eq$ls180.v:6468$2052_Y + attribute \src "ls180.v:6469.103-6469.148" + wire $eq$ls180.v:6469$2056_Y + attribute \src "ls180.v:6471.99-6471.144" + wire $eq$ls180.v:6471$2059_Y + attribute \src "ls180.v:6472.102-6472.147" + wire $eq$ls180.v:6472$2063_Y + attribute \src "ls180.v:6474.98-6474.143" + wire $eq$ls180.v:6474$2066_Y + attribute \src "ls180.v:6475.101-6475.146" + wire $eq$ls180.v:6475$2070_Y + attribute \src "ls180.v:6477.97-6477.142" + wire $eq$ls180.v:6477$2073_Y + attribute \src "ls180.v:6478.100-6478.145" + wire $eq$ls180.v:6478$2077_Y + attribute \src "ls180.v:6480.103-6480.148" + wire $eq$ls180.v:6480$2080_Y + attribute \src "ls180.v:6481.106-6481.151" + wire $eq$ls180.v:6481$2084_Y + attribute \src "ls180.v:6483.106-6483.151" + wire $eq$ls180.v:6483$2087_Y + attribute \src "ls180.v:6484.109-6484.154" + wire $eq$ls180.v:6484$2091_Y + attribute \src "ls180.v:6486.106-6486.151" + wire $eq$ls180.v:6486$2094_Y + attribute \src "ls180.v:6487.109-6487.154" + wire $eq$ls180.v:6487$2098_Y + attribute \src "ls180.v:6508.33-6508.79" + wire $eq$ls180.v:6508$2101_Y + attribute \src "ls180.v:6510.99-6510.144" + wire $eq$ls180.v:6510$2103_Y + attribute \src "ls180.v:6511.102-6511.147" + wire $eq$ls180.v:6511$2107_Y + attribute \src "ls180.v:6513.99-6513.144" + wire $eq$ls180.v:6513$2110_Y + attribute \src "ls180.v:6514.102-6514.147" + wire $eq$ls180.v:6514$2114_Y + attribute \src "ls180.v:6516.99-6516.144" + wire $eq$ls180.v:6516$2117_Y + attribute \src "ls180.v:6517.102-6517.147" + wire $eq$ls180.v:6517$2121_Y + attribute \src "ls180.v:6519.99-6519.144" + wire $eq$ls180.v:6519$2124_Y + attribute \src "ls180.v:6520.102-6520.147" + wire $eq$ls180.v:6520$2128_Y + attribute \src "ls180.v:6522.101-6522.146" + wire $eq$ls180.v:6522$2131_Y + attribute \src "ls180.v:6523.104-6523.149" + wire $eq$ls180.v:6523$2135_Y + attribute \src "ls180.v:6525.101-6525.146" + wire $eq$ls180.v:6525$2138_Y + attribute \src "ls180.v:6526.104-6526.149" + wire $eq$ls180.v:6526$2142_Y + attribute \src "ls180.v:6528.101-6528.146" + wire $eq$ls180.v:6528$2145_Y + attribute \src "ls180.v:6529.104-6529.149" + wire $eq$ls180.v:6529$2149_Y + attribute \src "ls180.v:6531.101-6531.146" + wire $eq$ls180.v:6531$2152_Y + attribute \src "ls180.v:6532.104-6532.149" + wire $eq$ls180.v:6532$2156_Y + attribute \src "ls180.v:6534.97-6534.142" + wire $eq$ls180.v:6534$2159_Y + attribute \src "ls180.v:6535.100-6535.145" + wire $eq$ls180.v:6535$2163_Y + attribute \src "ls180.v:6537.107-6537.152" + wire $eq$ls180.v:6537$2166_Y + attribute \src "ls180.v:6538.110-6538.155" + wire $eq$ls180.v:6538$2170_Y + attribute \src "ls180.v:6540.100-6540.146" + wire $eq$ls180.v:6540$2173_Y + attribute \src "ls180.v:6541.103-6541.149" + wire $eq$ls180.v:6541$2177_Y + attribute \src "ls180.v:6543.100-6543.146" + wire $eq$ls180.v:6543$2180_Y + attribute \src "ls180.v:6544.103-6544.149" + wire $eq$ls180.v:6544$2184_Y + attribute \src "ls180.v:6546.100-6546.146" + wire $eq$ls180.v:6546$2187_Y + attribute \src "ls180.v:6547.103-6547.149" + wire $eq$ls180.v:6547$2191_Y + attribute \src "ls180.v:6549.100-6549.146" + wire $eq$ls180.v:6549$2194_Y + attribute \src "ls180.v:6550.103-6550.149" + wire $eq$ls180.v:6550$2198_Y + attribute \src "ls180.v:6552.112-6552.158" + wire $eq$ls180.v:6552$2201_Y + attribute \src "ls180.v:6553.115-6553.161" + wire $eq$ls180.v:6553$2205_Y + attribute \src "ls180.v:6555.113-6555.159" + wire $eq$ls180.v:6555$2208_Y + attribute \src "ls180.v:6556.116-6556.162" + wire $eq$ls180.v:6556$2212_Y + attribute \src "ls180.v:6558.104-6558.150" + wire $eq$ls180.v:6558$2215_Y + attribute \src "ls180.v:6559.107-6559.153" + wire $eq$ls180.v:6559$2219_Y + attribute \src "ls180.v:6576.33-6576.79" + wire $eq$ls180.v:6576$2221_Y + attribute \src "ls180.v:6578.90-6578.135" + wire $eq$ls180.v:6578$2223_Y + attribute \src "ls180.v:6579.93-6579.138" + wire $eq$ls180.v:6579$2227_Y + attribute \src "ls180.v:6581.100-6581.145" + wire $eq$ls180.v:6581$2230_Y + attribute \src "ls180.v:6582.103-6582.148" + wire $eq$ls180.v:6582$2234_Y + attribute \src "ls180.v:6584.101-6584.146" + wire $eq$ls180.v:6584$2237_Y + attribute \src "ls180.v:6585.104-6585.149" + wire $eq$ls180.v:6585$2241_Y + attribute \src "ls180.v:6587.105-6587.150" + wire $eq$ls180.v:6587$2244_Y + attribute \src "ls180.v:6588.108-6588.153" + wire $eq$ls180.v:6588$2248_Y + attribute \src "ls180.v:6590.106-6590.151" + wire $eq$ls180.v:6590$2251_Y + attribute \src "ls180.v:6591.109-6591.154" + wire $eq$ls180.v:6591$2255_Y + attribute \src "ls180.v:6593.104-6593.149" + wire $eq$ls180.v:6593$2258_Y + attribute \src "ls180.v:6594.107-6594.152" + wire $eq$ls180.v:6594$2262_Y + attribute \src "ls180.v:6596.101-6596.146" + wire $eq$ls180.v:6596$2265_Y + attribute \src "ls180.v:6597.104-6597.149" + wire $eq$ls180.v:6597$2269_Y + attribute \src "ls180.v:6599.100-6599.145" + wire $eq$ls180.v:6599$2272_Y + attribute \src "ls180.v:6600.103-6600.148" + wire $eq$ls180.v:6600$2276_Y + attribute \src "ls180.v:6610.33-6610.79" + wire $eq$ls180.v:6610$2278_Y + attribute \src "ls180.v:6612.106-6612.151" + wire $eq$ls180.v:6612$2280_Y + attribute \src "ls180.v:6613.109-6613.154" + wire $eq$ls180.v:6613$2284_Y + attribute \src "ls180.v:6615.106-6615.151" + wire $eq$ls180.v:6615$2287_Y + attribute \src "ls180.v:6616.109-6616.154" + wire $eq$ls180.v:6616$2291_Y + attribute \src "ls180.v:6618.106-6618.151" + wire $eq$ls180.v:6618$2294_Y + attribute \src "ls180.v:6619.109-6619.154" + wire $eq$ls180.v:6619$2298_Y + attribute \src "ls180.v:6621.106-6621.151" + wire $eq$ls180.v:6621$2301_Y + attribute \src "ls180.v:6622.109-6622.154" + wire $eq$ls180.v:6622$2305_Y + attribute \src "ls180.v:7003.41-7003.81" + wire $eq$ls180.v:7003$2342_Y + attribute \src "ls180.v:7003.144-7003.177" + wire $eq$ls180.v:7003$2343_Y + attribute \src "ls180.v:7003.219-7003.252" + wire $eq$ls180.v:7003$2346_Y + attribute \src "ls180.v:7003.294-7003.327" + wire $eq$ls180.v:7003$2349_Y + attribute \src "ls180.v:7027.41-7027.81" + wire $eq$ls180.v:7027$2358_Y + attribute \src "ls180.v:7027.144-7027.177" + wire $eq$ls180.v:7027$2359_Y + attribute \src "ls180.v:7027.219-7027.252" + wire $eq$ls180.v:7027$2362_Y + attribute \src "ls180.v:7027.294-7027.327" + wire $eq$ls180.v:7027$2365_Y + attribute \src "ls180.v:7051.41-7051.81" + wire $eq$ls180.v:7051$2374_Y + attribute \src "ls180.v:7051.144-7051.177" + wire $eq$ls180.v:7051$2375_Y + attribute \src "ls180.v:7051.219-7051.252" + wire $eq$ls180.v:7051$2378_Y + attribute \src "ls180.v:7051.294-7051.327" + wire $eq$ls180.v:7051$2381_Y + attribute \src "ls180.v:7075.41-7075.81" + wire $eq$ls180.v:7075$2390_Y + attribute \src "ls180.v:7075.144-7075.177" + wire $eq$ls180.v:7075$2391_Y + attribute \src "ls180.v:7075.219-7075.252" + wire $eq$ls180.v:7075$2394_Y + attribute \src "ls180.v:7075.294-7075.327" + wire $eq$ls180.v:7075$2397_Y + attribute \src "ls180.v:7659.8-7659.38" + wire $eq$ls180.v:7659$2491_Y + attribute \src "ls180.v:7694.8-7694.42" + wire $eq$ls180.v:7694$2502_Y + attribute \src "ls180.v:7714.38-7714.74" + wire $eq$ls180.v:7714$2505_Y + attribute \src "ls180.v:7721.7-7721.43" + wire $eq$ls180.v:7721$2507_Y + attribute \src "ls180.v:7728.7-7728.43" + wire $eq$ls180.v:7728$2508_Y + attribute \src "ls180.v:7736.7-7736.43" + wire $eq$ls180.v:7736$2509_Y + attribute \src "ls180.v:7788.9-7788.54" + wire $eq$ls180.v:7788$2527_Y + attribute \src "ls180.v:7834.9-7834.54" + wire $eq$ls180.v:7834$2543_Y + attribute \src "ls180.v:7880.9-7880.54" + wire $eq$ls180.v:7880$2559_Y + attribute \src "ls180.v:7926.9-7926.54" + wire $eq$ls180.v:7926$2575_Y + attribute \src "ls180.v:8076.9-8076.41" + wire $eq$ls180.v:8076$2587_Y + attribute \src "ls180.v:8091.9-8091.41" + wire $eq$ls180.v:8091$2590_Y + attribute \src "ls180.v:8097.49-8097.82" + wire $eq$ls180.v:8097$2591_Y + attribute \src "ls180.v:8097.131-8097.164" + wire $eq$ls180.v:8097$2594_Y + attribute \src "ls180.v:8097.213-8097.246" + wire $eq$ls180.v:8097$2597_Y + attribute \src "ls180.v:8097.295-8097.328" + wire $eq$ls180.v:8097$2600_Y + attribute \src "ls180.v:8098.50-8098.83" + wire $eq$ls180.v:8098$2603_Y + attribute \src "ls180.v:8098.132-8098.165" + wire $eq$ls180.v:8098$2606_Y + attribute \src "ls180.v:8098.214-8098.247" + wire $eq$ls180.v:8098$2609_Y + attribute \src "ls180.v:8098.296-8098.329" + wire $eq$ls180.v:8098$2612_Y + attribute \src "ls180.v:8133.9-8133.42" + wire $eq$ls180.v:8133$2624_Y + attribute \src "ls180.v:8136.10-8136.43" + wire $eq$ls180.v:8136$2625_Y + attribute \src "ls180.v:8162.9-8162.42" + wire $eq$ls180.v:8162$2631_Y + attribute \src "ls180.v:8167.10-8167.43" + wire $eq$ls180.v:8167$2632_Y + attribute \src "ls180.v:8374.9-8374.53" + wire $eq$ls180.v:8374$2681_Y + attribute \src "ls180.v:8455.9-8455.54" + wire $eq$ls180.v:8455$2693_Y + attribute \src "ls180.v:8534.9-8534.55" + wire $eq$ls180.v:8534$2705_Y + attribute \src "ls180.v:8757.9-8757.49" + wire $eq$ls180.v:8757$2738_Y + attribute \src "ls180.v:8333.8-8333.54" + wire $ge$ls180.v:8333$2673_Y + attribute \src "ls180.v:8347.8-8347.54" + wire $ge$ls180.v:8347$2677_Y + attribute \src "ls180.v:5255.47-5255.83" + wire $gt$ls180.v:5255$965_Y + attribute \src "ls180.v:5261.7-5261.43" + wire $lt$ls180.v:5261$968_Y + attribute \src "ls180.v:8328.8-8328.43" + wire $lt$ls180.v:8328$2671_Y + attribute \src "ls180.v:8342.8-8342.43" + wire $lt$ls180.v:8342$2675_Y + attribute \src "ls180.v:10244.33-10244.36" + wire width 64 $memrd$\mem$ls180.v:10244$2792_DATA + attribute \src "ls180.v:10272.25-10272.30" + wire width 64 $memrd$\mem_1$ls180.v:10272$2818_DATA + attribute \src "ls180.v:10283.12-10283.19" + wire width 25 $memrd$\storage$ls180.v:10283$2823_DATA + attribute \src "ls180.v:10290.68-10290.75" + wire width 25 $memrd$\storage$ls180.v:10290$2825_DATA + attribute \src "ls180.v:10297.14-10297.23" + wire width 25 $memrd$\storage_1$ls180.v:10297$2830_DATA + attribute \src "ls180.v:10304.68-10304.77" + wire width 25 $memrd$\storage_1$ls180.v:10304$2832_DATA + attribute \src "ls180.v:10311.14-10311.23" + wire width 25 $memrd$\storage_2$ls180.v:10311$2837_DATA + attribute \src "ls180.v:10318.68-10318.77" + wire width 25 $memrd$\storage_2$ls180.v:10318$2839_DATA + attribute \src "ls180.v:10325.14-10325.23" + wire width 25 $memrd$\storage_3$ls180.v:10325$2844_DATA + attribute \src "ls180.v:10332.68-10332.77" + wire width 25 $memrd$\storage_3$ls180.v:10332$2846_DATA + attribute \src "ls180.v:10340.14-10340.23" + wire width 10 $memrd$\storage_4$ls180.v:10340$2851_DATA + attribute \src "ls180.v:10345.15-10345.24" + wire width 10 $memrd$\storage_4$ls180.v:10345$2853_DATA + attribute \src "ls180.v:10357.14-10357.23" + wire width 10 $memrd$\storage_5$ls180.v:10357$2858_DATA + attribute \src "ls180.v:10362.15-10362.24" + wire width 10 $memrd$\storage_5$ls180.v:10362$2860_DATA + attribute \src "ls180.v:10373.14-10373.23" + wire width 10 $memrd$\storage_6$ls180.v:10373$2865_DATA + attribute \src "ls180.v:10380.45-10380.54" + wire width 10 $memrd$\storage_6$ls180.v:10380$2867_DATA + attribute \src "ls180.v:10387.14-10387.23" + wire width 10 $memrd$\storage_7$ls180.v:10387$2872_DATA + attribute \src "ls180.v:10394.45-10394.54" + wire width 10 $memrd$\storage_7$ls180.v:10394$2874_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10226$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10226$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10226$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10228$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10228$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10228$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10230$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10230$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10230$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10232$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10232$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10232$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10234$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10234$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10234$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10236$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10236$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10236$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10238$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10238$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10238$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem$ls180.v:10240$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10240$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10240$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10254$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10254$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10254$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10256$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10256$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10256$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10258$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10258$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10258$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10260$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10260$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10260$12_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10262$13_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10262$13_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10262$13_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10264$14_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10264$14_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10264$14_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10266$15_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10266$15_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10266$15_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\mem_1$ls180.v:10268$16_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10268$16_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10268$16_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10282$17_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10282$17_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10282$17_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10296$18_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10296$18_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10296$18_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10310$19_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10310$19_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10310$19_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10324$20_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10324$20_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10324$20_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10339$21_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10339$21_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10339$21_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10356$22_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10356$22_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10356$22_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10372$23_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10372$23_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10372$23_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10386$24_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10386$24_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10386$24_EN + attribute \src "ls180.v:3044.41-3044.71" + wire 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$xor$ls180.v:5058$858_Y + attribute \src "ls180.v:5058.164-5058.278" + wire $xor$ls180.v:5058$859_Y + attribute \src "ls180.v:5059.360-5059.432" + wire $xor$ls180.v:5059$860_Y + attribute \src "ls180.v:5059.205-5059.277" + wire $xor$ls180.v:5059$861_Y + attribute \src "ls180.v:5059.164-5059.278" + wire $xor$ls180.v:5059$862_Y + attribute \src "ls180.v:5060.360-5060.432" + wire $xor$ls180.v:5060$863_Y + attribute \src "ls180.v:5060.205-5060.277" + wire $xor$ls180.v:5060$864_Y + attribute \src "ls180.v:5060.164-5060.278" + wire $xor$ls180.v:5060$865_Y + attribute \src "ls180.v:5061.360-5061.432" + wire $xor$ls180.v:5061$866_Y + attribute \src "ls180.v:5061.205-5061.277" + wire $xor$ls180.v:5061$867_Y + attribute \src "ls180.v:5061.164-5061.278" + wire $xor$ls180.v:5061$868_Y + attribute \src "ls180.v:5062.360-5062.432" + wire $xor$ls180.v:5062$869_Y + attribute \src "ls180.v:5062.205-5062.277" + wire $xor$ls180.v:5062$870_Y + attribute \src "ls180.v:5062.164-5062.278" + wire $xor$ls180.v:5062$871_Y + attribute \src "ls180.v:5063.360-5063.432" + wire $xor$ls180.v:5063$872_Y + attribute \src "ls180.v:5063.205-5063.277" + wire $xor$ls180.v:5063$873_Y + attribute \src "ls180.v:5063.164-5063.278" + wire $xor$ls180.v:5063$874_Y + attribute \src "ls180.v:5064.360-5064.432" + wire $xor$ls180.v:5064$875_Y + attribute \src "ls180.v:5064.205-5064.277" + wire $xor$ls180.v:5064$876_Y + attribute \src "ls180.v:5064.164-5064.278" + wire $xor$ls180.v:5064$877_Y + attribute \src "ls180.v:5065.360-5065.432" + wire $xor$ls180.v:5065$878_Y + attribute \src "ls180.v:5065.205-5065.277" + wire $xor$ls180.v:5065$879_Y + attribute \src "ls180.v:5065.164-5065.278" + wire $xor$ls180.v:5065$880_Y + attribute \src "ls180.v:5086.899-5086.983" + wire $xor$ls180.v:5086$894_Y + attribute \src "ls180.v:5086.634-5086.718" + wire $xor$ls180.v:5086$895_Y + attribute \src "ls180.v:5086.588-5086.719" + wire $xor$ls180.v:5086$896_Y + attribute \src "ls180.v:5086.234-5086.318" + wire $xor$ls180.v:5086$897_Y + attribute \src "ls180.v:5086.187-5086.319" + wire $xor$ls180.v:5086$898_Y + attribute \src "ls180.v:5087.899-5087.983" + wire $xor$ls180.v:5087$899_Y + attribute \src "ls180.v:5087.634-5087.718" + wire $xor$ls180.v:5087$900_Y + attribute \src "ls180.v:5087.588-5087.719" + wire $xor$ls180.v:5087$901_Y + attribute \src "ls180.v:5087.234-5087.318" + wire $xor$ls180.v:5087$902_Y + attribute \src "ls180.v:5087.187-5087.319" + wire $xor$ls180.v:5087$903_Y + attribute \src "ls180.v:5096.899-5096.983" + wire $xor$ls180.v:5096$905_Y + attribute \src "ls180.v:5096.634-5096.718" + wire $xor$ls180.v:5096$906_Y + attribute \src "ls180.v:5096.588-5096.719" + wire $xor$ls180.v:5096$907_Y + attribute \src "ls180.v:5096.234-5096.318" + wire $xor$ls180.v:5096$908_Y + attribute \src "ls180.v:5096.187-5096.319" + wire $xor$ls180.v:5096$909_Y + attribute \src "ls180.v:5097.899-5097.983" + wire $xor$ls180.v:5097$910_Y + attribute \src "ls180.v:5097.634-5097.718" + wire $xor$ls180.v:5097$911_Y + attribute \src "ls180.v:5097.588-5097.719" + wire $xor$ls180.v:5097$912_Y + attribute \src "ls180.v:5097.234-5097.318" + wire $xor$ls180.v:5097$913_Y + attribute \src "ls180.v:5097.187-5097.319" + wire $xor$ls180.v:5097$914_Y + attribute \src "ls180.v:5106.899-5106.983" + wire $xor$ls180.v:5106$916_Y + attribute \src "ls180.v:5106.634-5106.718" + wire $xor$ls180.v:5106$917_Y + attribute \src "ls180.v:5106.588-5106.719" + wire $xor$ls180.v:5106$918_Y + attribute \src "ls180.v:5106.234-5106.318" + wire $xor$ls180.v:5106$919_Y + attribute \src "ls180.v:5106.187-5106.319" + wire $xor$ls180.v:5106$920_Y + attribute \src "ls180.v:5107.899-5107.983" + wire $xor$ls180.v:5107$921_Y + attribute \src "ls180.v:5107.634-5107.718" + wire $xor$ls180.v:5107$922_Y + attribute \src "ls180.v:5107.588-5107.719" + wire $xor$ls180.v:5107$923_Y + attribute \src "ls180.v:5107.234-5107.318" + wire $xor$ls180.v:5107$924_Y + attribute \src "ls180.v:5107.187-5107.319" + wire $xor$ls180.v:5107$925_Y + attribute \src "ls180.v:5116.899-5116.983" + wire $xor$ls180.v:5116$927_Y + attribute \src "ls180.v:5116.634-5116.718" + wire $xor$ls180.v:5116$928_Y + attribute \src "ls180.v:5116.588-5116.719" + wire $xor$ls180.v:5116$929_Y + attribute \src "ls180.v:5116.234-5116.318" + wire $xor$ls180.v:5116$930_Y + attribute \src "ls180.v:5116.187-5116.319" + wire $xor$ls180.v:5116$931_Y + attribute \src "ls180.v:5117.899-5117.983" + wire $xor$ls180.v:5117$932_Y + attribute \src "ls180.v:5117.634-5117.718" + wire $xor$ls180.v:5117$933_Y + attribute \src "ls180.v:5117.588-5117.719" + wire $xor$ls180.v:5117$934_Y + attribute \src "ls180.v:5117.234-5117.318" + wire $xor$ls180.v:5117$935_Y + attribute \src "ls180.v:5117.187-5117.319" + wire $xor$ls180.v:5117$936_Y + attribute \src "ls180.v:5268.879-5268.961" + wire $xor$ls180.v:5268$969_Y + attribute \src "ls180.v:5268.620-5268.702" + wire $xor$ls180.v:5268$970_Y + attribute \src "ls180.v:5268.575-5268.703" + wire $xor$ls180.v:5268$971_Y + attribute \src "ls180.v:5268.229-5268.311" + wire $xor$ls180.v:5268$972_Y + attribute \src "ls180.v:5268.183-5268.312" + wire $xor$ls180.v:5268$973_Y + attribute \src "ls180.v:5269.879-5269.961" + wire $xor$ls180.v:5269$974_Y + attribute \src "ls180.v:5269.620-5269.702" + wire $xor$ls180.v:5269$975_Y + attribute \src "ls180.v:5269.575-5269.703" + wire $xor$ls180.v:5269$976_Y + attribute \src "ls180.v:5269.229-5269.311" + wire $xor$ls180.v:5269$977_Y + attribute \src "ls180.v:5269.183-5269.312" + wire $xor$ls180.v:5269$978_Y + attribute \src "ls180.v:5278.879-5278.961" + wire $xor$ls180.v:5278$980_Y + attribute \src "ls180.v:5278.620-5278.702" + wire $xor$ls180.v:5278$981_Y + attribute \src "ls180.v:5278.575-5278.703" + wire $xor$ls180.v:5278$982_Y + attribute \src "ls180.v:5278.229-5278.311" + wire $xor$ls180.v:5278$983_Y + attribute \src "ls180.v:5278.183-5278.312" + wire $xor$ls180.v:5278$984_Y + attribute \src "ls180.v:5279.879-5279.961" + wire $xor$ls180.v:5279$985_Y + attribute \src "ls180.v:5279.620-5279.702" + wire $xor$ls180.v:5279$986_Y + attribute \src "ls180.v:5279.575-5279.703" + wire $xor$ls180.v:5279$987_Y + attribute \src "ls180.v:5279.229-5279.311" + wire $xor$ls180.v:5279$988_Y + attribute \src "ls180.v:5279.183-5279.312" + wire $xor$ls180.v:5279$989_Y + attribute \src "ls180.v:5288.879-5288.961" + wire $xor$ls180.v:5288$991_Y + attribute \src "ls180.v:5288.620-5288.702" + wire $xor$ls180.v:5288$992_Y + attribute \src "ls180.v:5288.575-5288.703" + wire $xor$ls180.v:5288$993_Y + attribute \src "ls180.v:5288.229-5288.311" + wire $xor$ls180.v:5288$994_Y + attribute \src "ls180.v:5288.183-5288.312" + wire $xor$ls180.v:5288$995_Y + attribute \src "ls180.v:5289.183-5289.312" + wire $xor$ls180.v:5289$1000_Y + attribute \src "ls180.v:5289.879-5289.961" + wire $xor$ls180.v:5289$996_Y + attribute \src "ls180.v:5289.620-5289.702" + wire $xor$ls180.v:5289$997_Y + attribute \src "ls180.v:5289.575-5289.703" + wire $xor$ls180.v:5289$998_Y + attribute \src "ls180.v:5289.229-5289.311" + wire $xor$ls180.v:5289$999_Y + attribute \src "ls180.v:5298.879-5298.961" + wire $xor$ls180.v:5298$1002_Y + attribute \src "ls180.v:5298.620-5298.702" + wire $xor$ls180.v:5298$1003_Y + attribute \src "ls180.v:5298.575-5298.703" + wire $xor$ls180.v:5298$1004_Y + attribute \src "ls180.v:5298.229-5298.311" + wire $xor$ls180.v:5298$1005_Y + attribute \src "ls180.v:5298.183-5298.312" + wire $xor$ls180.v:5298$1006_Y + attribute \src "ls180.v:5299.879-5299.961" + wire $xor$ls180.v:5299$1007_Y + attribute \src "ls180.v:5299.620-5299.702" + wire $xor$ls180.v:5299$1008_Y + attribute \src "ls180.v:5299.575-5299.703" + wire $xor$ls180.v:5299$1009_Y + attribute \src "ls180.v:5299.229-5299.311" + wire $xor$ls180.v:5299$1010_Y + attribute \src "ls180.v:5299.183-5299.312" + wire $xor$ls180.v:5299$1011_Y + attribute \src "ls180.v:1812.11-1812.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1811.11-1811.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1814.11-1814.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1813.11-1813.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1816.11-1816.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1815.11-1815.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1818.11-1818.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1817.11-1817.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2671.5-2671.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2672.12-2672.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2684.5-2684.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2685.5-2685.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2689.12-2689.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2690.5-2690.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2691.5-2691.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2692.12-2692.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2693.5-2693.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2694.5-2694.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2695.12-2695.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2696.5-2696.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2673.11-2673.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2697.5-2697.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2698.12-2698.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2699.5-2699.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2700.5-2700.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2701.12-2701.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2702.12-2702.42" + wire width 64 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2703.11-2703.41" + wire width 8 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2704.5-2704.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2705.5-2705.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2706.5-2706.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2674.5-2674.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2707.11-2707.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2708.11-2708.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2675.5-2675.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2676.5-2676.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2680.5-2680.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2681.12-2681.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2682.11-2682.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2683.5-2683.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2677.5-2677.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2678.5-2678.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2679.5-2679.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2686.5-2686.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2687.5-2687.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2688.5-2688.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1798.5-1798.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1797.5-1797.29" + wire \builder_converter0_state + attribute \src "ls180.v:1802.5-1802.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1801.5-1801.29" + wire \builder_converter1_state + attribute \src "ls180.v:1806.5-1806.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1805.5-1805.29" + wire \builder_converter2_state + attribute \src "ls180.v:1843.5-1843.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1842.5-1842.28" + wire \builder_converter_state + attribute \src "ls180.v:1971.12-1971.25" + wire width 20 \builder_count + attribute \src "ls180.v:2659.13-2659.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2662.12-2662.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2661.12-2661.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2660.6-2660.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:2009.12-2009.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:2008.6-2008.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:2011.12-2011.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:2010.6-2010.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:2005.12-2005.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:2004.6-2004.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:2007.12-2007.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:2006.6-2006.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:2001.12-2001.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:2000.6-2000.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:2003.12-2003.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:2002.6-2002.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:1997.12-1997.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:1996.6-1996.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:1999.12-1999.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:1998.6-1998.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:1977.6-1977.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:1976.6-1976.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:1979.6-1979.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:1978.6-1978.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:1993.12-1993.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:1992.6-1992.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:1995.12-1995.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:1994.6-1994.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:1989.12-1989.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:1988.6-1988.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:1991.12-1991.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:1990.6-1990.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:1985.12-1985.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:1984.6-1984.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:1987.12-1987.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:1986.6-1986.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:1981.12-1981.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:1980.6-1980.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:1983.12-1983.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:1982.6-1982.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:2012.6-2012.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2483.12-2483.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2482.6-2482.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2485.12-2485.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2484.6-2484.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2479.12-2479.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2478.6-2478.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2481.12-2481.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2480.6-2480.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2499.6-2499.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2498.6-2498.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2501.6-2501.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2500.6-2500.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2503.6-2503.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2502.6-2502.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2505.6-2505.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2504.6-2504.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2495.12-2495.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2494.6-2494.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2497.12-2497.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2496.6-2496.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2491.12-2491.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2490.6-2490.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2493.12-2493.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2492.6-2492.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2506.6-2506.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2487.6-2487.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2486.6-2486.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2489.6-2489.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2488.6-2488.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2544.12-2544.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2543.6-2543.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2546.12-2546.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2545.6-2545.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2540.12-2540.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2539.6-2539.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2542.12-2542.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2541.6-2541.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2516.12-2516.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2515.6-2515.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2518.12-2518.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2517.6-2517.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2512.12-2512.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2511.6-2511.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2514.12-2514.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2513.6-2513.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2532.6-2532.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2531.6-2531.30" + wire \builder_csrbank11_cs0_re + attribute \src "ls180.v:2534.6-2534.29" + wire \builder_csrbank11_cs0_w + attribute \src "ls180.v:2533.6-2533.30" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2536.6-2536.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2535.6-2535.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2538.6-2538.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2537.6-2537.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2528.12-2528.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2527.6-2527.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2530.12-2530.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2529.6-2529.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2524.12-2524.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2523.6-2523.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2526.12-2526.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2525.6-2525.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2547.6-2547.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2520.6-2520.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2519.6-2519.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2522.6-2522.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2521.6-2521.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2585.6-2585.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2584.6-2584.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2587.6-2587.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2586.6-2586.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2609.6-2609.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2608.6-2608.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2611.6-2611.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2610.6-2610.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2565.12-2565.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2564.6-2564.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2567.12-2567.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2566.6-2566.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2561.12-2561.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2560.6-2560.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2563.12-2563.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2562.6-2562.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2557.12-2557.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2556.6-2556.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2559.12-2559.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2558.6-2558.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2553.12-2553.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2552.6-2552.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2555.12-2555.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2554.6-2554.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2581.12-2581.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2580.6-2580.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2583.12-2583.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2582.6-2582.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2577.12-2577.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2576.6-2576.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2579.12-2579.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2578.6-2578.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2573.12-2573.39" + wire width 8 \builder_csrbank12_reload2_r + attribute \src "ls180.v:2572.6-2572.34" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2575.12-2575.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2574.6-2574.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2569.12-2569.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2568.6-2568.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2571.12-2571.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2570.6-2570.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2612.6-2612.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2589.6-2589.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2588.6-2588.40" + wire \builder_csrbank12_update_value0_re + attribute \src "ls180.v:2591.6-2591.39" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2590.6-2590.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2605.12-2605.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2604.6-2604.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2607.12-2607.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2606.6-2606.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2601.12-2601.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2600.6-2600.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2603.12-2603.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2602.6-2602.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2597.12-2597.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2596.6-2596.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2599.12-2599.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2598.6-2598.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2593.12-2593.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2592.6-2592.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2595.12-2595.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2594.6-2594.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2626.12-2626.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2625.6-2625.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2628.12-2628.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2627.6-2627.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2622.6-2622.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2621.6-2621.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2624.6-2624.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2623.6-2623.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2634.6-2634.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2633.6-2633.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2636.6-2636.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2635.6-2635.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2637.6-2637.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2630.6-2630.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2629.6-2629.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2632.6-2632.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2631.6-2631.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2618.6-2618.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2617.6-2617.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2620.6-2620.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2619.6-2619.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2658.6-2658.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2655.12-2655.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2654.6-2654.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2657.12-2657.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2656.6-2656.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2651.12-2651.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2650.6-2650.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2653.12-2653.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2652.6-2652.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2647.12-2647.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2646.6-2646.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2649.12-2649.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2648.6-2648.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2643.12-2643.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2642.6-2642.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2645.12-2645.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2644.6-2644.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:2030.12-2030.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:2029.6-2029.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:2032.12-2032.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:2031.6-2031.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:2026.12-2026.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:2025.6-2025.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:2028.12-2028.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:2027.6-2027.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:2022.12-2022.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:2021.6-2021.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:2024.12-2024.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:2023.6-2023.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:2018.12-2018.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:2017.6-2017.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:2020.12-2020.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:2019.6-2019.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:2038.12-2038.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:2037.6-2037.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:2040.12-2040.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:2039.6-2039.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:2034.12-2034.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:2033.6-2033.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:2036.12-2036.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:2035.6-2035.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:2041.6-2041.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:2051.6-2051.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:2050.6-2050.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:2053.6-2053.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:2052.6-2052.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:2054.6-2054.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:2047.12-2047.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:2046.6-2046.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:2049.12-2049.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:2048.6-2048.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:2060.6-2060.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:2059.6-2059.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:2062.6-2062.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:2061.6-2061.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2092.12-2092.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2091.6-2091.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2094.12-2094.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2093.6-2093.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2088.12-2088.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2087.6-2087.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2090.12-2090.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2089.6-2089.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2084.12-2084.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2083.6-2083.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2086.12-2086.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2085.6-2085.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:2080.12-2080.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:2079.6-2079.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:2082.12-2082.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:2081.6-2081.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2095.6-2095.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:2076.12-2076.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:2075.6-2075.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:2078.12-2078.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:2077.6-2077.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:2072.12-2072.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:2071.6-2071.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:2074.12-2074.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:2073.6-2073.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:2068.12-2068.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:2067.6-2067.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:2070.12-2070.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:2069.6-2069.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:2064.12-2064.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:2063.6-2063.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:2066.12-2066.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:2065.6-2065.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2101.6-2101.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2100.6-2100.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2103.6-2103.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2102.6-2102.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2133.12-2133.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2132.6-2132.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2135.12-2135.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2134.6-2134.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2129.12-2129.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2128.6-2128.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2131.12-2131.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2130.6-2130.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2125.12-2125.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2124.6-2124.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2127.12-2127.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2126.6-2126.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2121.12-2121.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2120.6-2120.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2123.12-2123.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2122.6-2122.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2136.6-2136.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2117.12-2117.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2116.6-2116.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2119.12-2119.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2118.6-2118.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2113.12-2113.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2112.6-2112.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2115.12-2115.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2114.6-2114.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2109.12-2109.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2108.6-2108.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2111.12-2111.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2110.6-2110.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2105.12-2105.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2104.6-2104.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2107.12-2107.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2106.6-2106.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2170.12-2170.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2169.6-2169.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2172.12-2172.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2171.6-2171.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2166.12-2166.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2165.6-2165.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2168.12-2168.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2167.6-2167.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2162.12-2162.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2161.6-2161.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2164.12-2164.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2163.6-2163.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2158.12-2158.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2157.6-2157.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2160.12-2160.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2159.6-2159.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2154.12-2154.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2153.6-2153.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2156.12-2156.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2155.6-2155.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2150.12-2150.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2149.6-2149.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2152.12-2152.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2151.6-2151.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2146.12-2146.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2145.6-2145.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2148.12-2148.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2147.6-2147.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2142.12-2142.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2141.6-2141.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2144.12-2144.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2143.6-2143.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2194.6-2194.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2193.6-2193.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2196.6-2196.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2195.6-2195.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2190.6-2190.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2189.6-2189.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2192.6-2192.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2191.6-2191.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2186.12-2186.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2185.6-2185.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2188.12-2188.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2187.6-2187.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2182.12-2182.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2181.6-2181.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2184.12-2184.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2183.6-2183.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2178.12-2178.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2177.6-2177.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2180.12-2180.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2179.6-2179.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2174.12-2174.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2173.6-2173.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2176.12-2176.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2175.6-2175.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2198.6-2198.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2197.6-2197.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2200.6-2200.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2199.6-2199.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2201.6-2201.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2331.12-2331.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2330.6-2330.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2333.12-2333.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2332.6-2332.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2327.12-2327.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2326.6-2326.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2329.12-2329.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2328.6-2328.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2323.12-2323.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2322.6-2322.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2325.12-2325.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2324.6-2324.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2319.12-2319.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2318.6-2318.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2321.12-2321.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2320.6-2320.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2315.12-2315.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2314.6-2314.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2317.12-2317.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2316.6-2316.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2311.12-2311.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2310.6-2310.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2313.12-2313.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2312.6-2312.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2219.12-2219.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2218.6-2218.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2221.12-2221.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2220.6-2220.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2215.12-2215.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2214.6-2214.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2217.12-2217.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2216.6-2216.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2211.12-2211.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2210.6-2210.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2213.12-2213.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2212.6-2212.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2207.12-2207.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2206.6-2206.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2209.12-2209.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2208.6-2208.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2235.12-2235.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2234.6-2234.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2237.12-2237.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2236.6-2236.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2231.12-2231.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2230.6-2230.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2233.12-2233.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2232.6-2232.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2227.12-2227.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2226.6-2226.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2229.12-2229.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2228.6-2228.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2223.12-2223.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2222.6-2222.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2225.12-2225.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2224.6-2224.38" + wire \builder_csrbank6_cmd_command3_we + attribute \src "ls180.v:2303.12-2303.40" + wire width 4 \builder_csrbank6_cmd_event_r + attribute \src "ls180.v:2302.6-2302.35" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2305.12-2305.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2304.6-2304.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2299.12-2299.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2298.6-2298.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2301.12-2301.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2300.6-2300.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2259.12-2259.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2258.6-2258.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2261.12-2261.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2260.6-2260.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2255.12-2255.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2254.6-2254.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2257.12-2257.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2256.6-2256.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2251.12-2251.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2250.6-2250.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2253.12-2253.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2252.6-2252.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2247.12-2247.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2246.6-2246.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2249.12-2249.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2248.6-2248.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2243.12-2243.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2242.6-2242.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2245.12-2245.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2244.6-2244.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2239.12-2239.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2238.6-2238.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2241.12-2241.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2240.6-2240.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2295.12-2295.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2294.6-2294.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2297.12-2297.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2296.6-2296.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2291.12-2291.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2290.6-2290.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2293.12-2293.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2292.6-2292.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2287.12-2287.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2286.6-2286.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2289.12-2289.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2288.6-2288.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2283.12-2283.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2282.6-2282.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2285.12-2285.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2284.6-2284.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2279.12-2279.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2278.6-2278.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2281.12-2281.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2280.6-2280.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2275.12-2275.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2274.6-2274.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2277.12-2277.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2276.6-2276.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2271.12-2271.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2270.6-2270.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2273.12-2273.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2272.6-2272.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2267.12-2267.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2266.6-2266.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2269.12-2269.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2268.6-2268.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2263.12-2263.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2262.6-2262.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2265.12-2265.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2264.6-2264.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2307.12-2307.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2306.6-2306.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2309.12-2309.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2308.6-2308.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2334.6-2334.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2368.12-2368.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2367.6-2367.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2370.12-2370.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2369.6-2369.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2364.12-2364.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2363.6-2363.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2366.12-2366.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2365.6-2365.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2360.12-2360.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2359.6-2359.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2362.12-2362.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2361.6-2361.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2356.12-2356.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2355.6-2355.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2358.12-2358.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2357.6-2357.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2352.12-2352.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2351.6-2351.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2354.12-2354.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2353.6-2353.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2348.12-2348.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2347.6-2347.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2350.12-2350.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2349.6-2349.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2344.12-2344.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2343.6-2343.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2346.12-2346.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2345.6-2345.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2340.12-2340.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2339.6-2339.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2342.12-2342.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2341.6-2341.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2392.6-2392.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2391.6-2391.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2394.6-2394.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2393.6-2393.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2388.6-2388.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2387.6-2387.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2390.6-2390.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2389.6-2389.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2384.12-2384.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2383.6-2383.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2386.12-2386.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2385.6-2385.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2380.12-2380.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2379.6-2379.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2382.12-2382.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2381.6-2381.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2376.12-2376.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2375.6-2375.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2378.12-2378.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2377.6-2377.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2372.12-2372.42" + wire width 8 \builder_csrbank7_dma_length3_r + attribute \src "ls180.v:2371.6-2371.37" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2374.12-2374.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2373.6-2373.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2396.6-2396.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2395.6-2395.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2398.6-2398.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2397.6-2397.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2412.12-2412.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2411.6-2411.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2414.12-2414.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2413.6-2413.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2408.12-2408.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2407.6-2407.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2410.12-2410.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2409.6-2409.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2404.12-2404.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2403.6-2403.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2406.12-2406.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2405.6-2405.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2400.12-2400.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2399.6-2399.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2402.12-2402.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2401.6-2401.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2415.6-2415.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2421.6-2421.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2420.6-2420.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2423.6-2423.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2422.6-2422.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2429.12-2429.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2428.6-2428.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2431.12-2431.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2430.6-2430.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2425.6-2425.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2424.6-2424.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2427.6-2427.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2426.6-2426.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2432.6-2432.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2438.12-2438.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2437.6-2437.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2440.12-2440.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2439.6-2439.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2450.12-2450.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2449.6-2449.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2452.12-2452.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2451.6-2451.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2446.12-2446.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2445.6-2445.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2448.12-2448.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2447.6-2447.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2454.12-2454.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2453.6-2453.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2456.12-2456.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2455.6-2455.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2442.12-2442.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2441.6-2441.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2444.12-2444.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2443.6-2443.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2470.12-2470.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2469.6-2469.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2472.12-2472.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2471.6-2471.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2466.12-2466.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2465.6-2465.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2468.12-2468.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2467.6-2467.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2462.12-2462.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2461.6-2461.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2464.12-2464.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2463.6-2463.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2458.12-2458.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2457.6-2457.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2460.12-2460.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2459.6-2459.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2473.6-2473.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:1970.6-1970.18" + wire \builder_done + attribute \src "ls180.v:1968.5-1968.18" + wire \builder_error + attribute \src "ls180.v:1965.11-1965.24" + wire width 3 \builder_grant + attribute \src "ls180.v:1972.13-1972.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:1975.11-1975.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:1974.12-1974.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:1973.6-1973.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2474.13-2474.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2477.11-2477.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2476.12-2476.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2475.6-2475.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2507.13-2507.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2510.11-2510.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2509.12-2509.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2508.6-2508.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2548.13-2548.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2551.11-2551.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2550.12-2550.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2549.6-2549.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2613.13-2613.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2616.11-2616.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2615.12-2615.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2614.6-2614.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:2638.13-2638.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2641.11-2641.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2640.12-2640.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2639.6-2639.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:2013.13-2013.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:2016.11-2016.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:2015.12-2015.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:2014.6-2014.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:2042.13-2042.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:2045.11-2045.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:2044.12-2044.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:2043.6-2043.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:2055.13-2055.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:2058.11-2058.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:2057.12-2057.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:2056.6-2056.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2096.13-2096.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2099.11-2099.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2098.12-2098.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2097.6-2097.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2137.13-2137.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2140.11-2140.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2139.12-2139.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2138.6-2138.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2202.13-2202.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2205.11-2205.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2204.12-2204.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2203.6-2203.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2335.13-2335.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2338.11-2338.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2337.12-2337.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2336.6-2336.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2416.13-2416.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2419.11-2419.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2418.12-2418.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2417.6-2417.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2433.13-2433.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2436.11-2436.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2435.12-2435.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2434.6-2434.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1930.12-1930.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2667.12-2667.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2668.5-2668.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1948.5-1948.48" + wire \builder_libresocsim_converted_interface_ack + attribute \src "ls180.v:1942.13-1942.56" + wire width 30 \builder_libresocsim_converted_interface_adr + attribute \src "ls180.v:1951.12-1951.55" + wire width 2 \builder_libresocsim_converted_interface_bte + attribute \src "ls180.v:1950.12-1950.55" + wire width 3 \builder_libresocsim_converted_interface_cti + attribute \src "ls180.v:1946.6-1946.49" + wire \builder_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1944.12-1944.57" + wire width 64 \builder_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1943.13-1943.58" + wire width 64 \builder_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1952.5-1952.48" + wire \builder_libresocsim_converted_interface_err + attribute \src "ls180.v:1945.12-1945.55" + wire width 8 \builder_libresocsim_converted_interface_sel + attribute \src "ls180.v:1947.6-1947.49" + wire \builder_libresocsim_converted_interface_stb + attribute \src "ls180.v:1949.6-1949.48" + wire \builder_libresocsim_converted_interface_we + attribute \src "ls180.v:1933.12-1933.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1932.11-1932.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2665.11-2665.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2666.5-2666.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1931.5-1931.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2669.5-2669.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2670.5-2670.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1940.5-1940.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1934.12-1934.44" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1938.5-1938.37" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1936.12-1936.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1935.12-1935.46" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1937.11-1937.43" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1939.5-1939.37" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1941.5-1941.36" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1833.5-1833.20" + wire \builder_locked0 + attribute \src "ls180.v:1834.5-1834.20" + wire \builder_locked1 + attribute \src "ls180.v:1835.5-1835.20" + wire \builder_locked2 + attribute \src "ls180.v:1836.5-1836.20" + wire \builder_locked3 + attribute \src "ls180.v:1820.11-1820.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1819.11-1819.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2774.32-2774.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2775.32-2775.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2794.32-2794.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2795.32-2795.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2796.32-2796.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2797.32-2797.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2798.32-2798.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2799.32-2799.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2800.32-2800.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2801.32-2801.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2802.32-2802.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2803.32-2803.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2804.32-2804.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2805.32-2805.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2806.32-2806.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2807.32-2807.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2776.32-2776.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2777.32-2777.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2778.32-2778.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2779.32-2779.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2780.32-2780.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2781.32-2781.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2782.32-2782.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2783.32-2783.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2784.32-2784.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2785.32-2785.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2786.32-2786.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2787.32-2787.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2788.32-2788.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2789.32-2789.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2790.32-2790.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2791.32-2791.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2792.32-2792.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2793.32-2793.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1838.5-1838.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1839.5-1839.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1840.5-1840.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1841.5-1841.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1837.5-1837.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2664.11-2664.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1810.11-1810.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1809.11-1809.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:1964.12-1964.27" + wire width 5 \builder_request + attribute \src "ls180.v:1823.6-1823.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1822.6-1822.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1821.6-1821.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1826.6-1826.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1825.6-1825.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1824.6-1824.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1829.6-1829.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1828.6-1828.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1827.6-1827.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1832.6-1832.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1831.6-1831.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1830.6-1830.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1919.11-1919.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1918.11-1918.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1887.5-1887.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1886.5-1886.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1899.11-1899.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1898.11-1898.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1923.5-1923.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1922.5-1922.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1927.11-1927.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1926.11-1926.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1875.11-1875.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1874.11-1874.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1863.11-1863.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1862.11-1862.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1859.11-1859.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1858.11-1858.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1871.5-1871.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1870.5-1870.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1879.11-1879.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1878.11-1878.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1855.5-1855.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1854.5-1854.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:1959.5-1959.23" + wire \builder_shared_ack + attribute \src "ls180.v:1953.13-1953.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:1962.12-1962.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1961.12-1961.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1957.6-1957.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1955.12-1955.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1954.13-1954.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:1963.6-1963.24" + wire \builder_shared_err + attribute \src "ls180.v:1956.12-1956.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:1958.6-1958.24" + wire \builder_shared_stb + attribute \src "ls180.v:1960.6-1960.23" + wire \builder_shared_we + attribute \src "ls180.v:1966.11-1966.28" + wire width 10 \builder_slave_sel + attribute \src "ls180.v:1967.11-1967.30" + wire width 10 \builder_slave_sel_r + attribute \src "ls180.v:1847.11-1847.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1846.11-1846.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1851.11-1851.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1850.11-1850.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2663.11-2663.24" + wire width 2 \builder_state + attribute \src "ls180.v:2716.5-2716.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2717.5-2717.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2709.11-2709.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2710.12-2710.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2711.5-2711.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2712.5-2712.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2713.5-2713.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2714.5-2714.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2715.5-2715.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:1969.6-1969.18" + wire \builder_wait + attribute \src "ls180.v:31.19-31.23" + wire width 3 input 27 \eint + attribute \src "ls180.v:195.12-195.18" + wire width 3 \eint_1 + attribute \src "ls180.v:32.21-32.27" + wire width 16 output 28 \gpio_i + attribute \src "ls180.v:33.20-33.26" + wire width 16 output 29 \gpio_o + attribute \src "ls180.v:34.20-34.27" + wire width 16 output 30 \gpio_oe + attribute \src "ls180.v:35.14-35.21" + wire output 31 \i2c_scl + attribute \src "ls180.v:36.14-36.23" + wire output 32 \i2c_sda_i + attribute \src "ls180.v:37.14-37.23" + wire output 33 \i2c_sda_o + attribute \src "ls180.v:38.14-38.24" + wire output 34 \i2c_sda_oe + attribute \src "ls180.v:49.13-49.21" + wire input 45 \jtag_tck + attribute \src "ls180.v:50.13-50.21" + wire input 46 \jtag_tdi + attribute \src "ls180.v:51.14-51.22" + wire output 47 \jtag_tdo + attribute \src "ls180.v:48.13-48.21" + wire input 44 \jtag_tms + attribute \src "ls180.v:895.6-895.18" + wire \main_ack_cmd + attribute \src "ls180.v:897.6-897.20" + wire \main_ack_rdata + attribute \src "ls180.v:896.6-896.20" + wire \main_ack_wdata + attribute \src "ls180.v:893.5-893.22" + wire \main_cmd_consumed + attribute \src "ls180.v:276.5-276.28" + wire \main_converter0_counter + attribute \src "ls180.v:1799.5-1799.50" + wire \main_converter0_counter_converter0_next_value + attribute \src "ls180.v:1800.5-1800.53" + wire \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:278.12-278.33" + wire width 64 \main_converter0_dat_r + attribute \src "ls180.v:277.6-277.27" + wire \main_converter0_reset + attribute \src "ls180.v:275.5-275.25" + wire \main_converter0_skip + attribute \src "ls180.v:291.5-291.28" + wire \main_converter1_counter + attribute \src "ls180.v:1803.5-1803.50" + wire \main_converter1_counter_converter1_next_value + attribute \src "ls180.v:1804.5-1804.53" + wire \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:293.12-293.33" + wire width 64 \main_converter1_dat_r + attribute \src "ls180.v:292.6-292.27" + wire \main_converter1_reset + attribute \src "ls180.v:290.5-290.25" + wire \main_converter1_skip + attribute \src "ls180.v:890.5-890.27" + wire \main_converter_counter + attribute \src "ls180.v:1844.5-1844.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1845.5-1845.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:892.12-892.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:891.6-891.26" + wire \main_converter_reset + attribute \src "ls180.v:889.5-889.24" + wire \main_converter_skip + attribute \src "ls180.v:307.6-307.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:298.13-298.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:299.12-299.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:300.6-300.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:304.6-304.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:301.6-301.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:305.6-305.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:302.6-302.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:312.12-312.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:311.6-311.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:313.5-313.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:306.6-306.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:303.6-303.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:308.13-308.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:309.6-309.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:310.12-310.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:1130.12-1130.22" + wire width 24 \main_dummy + attribute \src "ls180.v:1040.12-1040.45" + wire width 16 \main_gpiotristateasic0_oe_storage + attribute \src "ls180.v:1042.12-1042.46" + wire width 16 \main_gpiotristateasic0_out_storage + attribute \src "ls180.v:1043.13-1043.42" + wire width 16 \main_gpiotristateasic0_pads_i + attribute \src "ls180.v:1044.13-1044.42" + wire width 16 \main_gpiotristateasic0_pads_o + attribute \src "ls180.v:1045.13-1045.43" + wire width 16 \main_gpiotristateasic0_pads_oe + attribute \src "ls180.v:1041.12-1041.41" + wire width 16 \main_gpiotristateasic0_status + attribute \src "ls180.v:1047.5-1047.33" + wire \main_gpiotristateasic1_oe_re + attribute \src "ls180.v:1046.12-1046.45" + wire width 16 \main_gpiotristateasic1_oe_storage + attribute \src "ls180.v:1051.5-1051.34" + wire \main_gpiotristateasic1_out_re + attribute \src "ls180.v:1050.12-1050.46" + wire width 16 \main_gpiotristateasic1_out_storage + attribute \src "ls180.v:1052.13-1052.42" + wire width 16 \main_gpiotristateasic1_pads_i + attribute \src "ls180.v:1053.13-1053.42" + wire width 16 \main_gpiotristateasic1_pads_o + attribute \src "ls180.v:1054.13-1054.43" + wire width 16 \main_gpiotristateasic1_pads_oe + attribute \src "ls180.v:1048.12-1048.41" + wire width 16 \main_gpiotristateasic1_status + attribute \src "ls180.v:1049.6-1049.31" + wire \main_gpiotristateasic1_we + attribute \src "ls180.v:1152.6-1152.17" + wire \main_i2c_oe + attribute \src "ls180.v:1155.5-1155.16" + wire \main_i2c_re + attribute \src "ls180.v:1151.6-1151.18" + wire \main_i2c_scl + attribute \src "ls180.v:1153.6-1153.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1156.6-1156.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1157.6-1157.21" + wire \main_i2c_status + attribute \src "ls180.v:1154.11-1154.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1158.6-1158.17" + wire \main_i2c_we + attribute \src "ls180.v:297.5-297.17" + wire \main_int_rst + attribute \src "ls180.v:1618.6-1618.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1612.13-1612.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1621.11-1621.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1620.11-1620.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1616.6-1616.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1614.13-1614.38" + wire width 64 \main_interface0_bus_dat_r + attribute \src "ls180.v:1613.13-1613.38" + wire width 64 \main_interface0_bus_dat_w + attribute \src "ls180.v:1622.6-1622.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1615.12-1615.35" + wire width 8 \main_interface0_bus_sel + attribute \src "ls180.v:1617.6-1617.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1619.6-1619.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:270.5-270.44" + wire \main_interface0_converted_interface_ack + attribute \src "ls180.v:264.13-264.52" + wire width 30 \main_interface0_converted_interface_adr + attribute \src "ls180.v:273.12-273.51" + wire width 2 \main_interface0_converted_interface_bte + attribute \src "ls180.v:272.12-272.51" + wire width 3 \main_interface0_converted_interface_cti + attribute \src "ls180.v:268.6-268.45" + wire \main_interface0_converted_interface_cyc + attribute \src "ls180.v:266.13-266.54" + wire width 64 \main_interface0_converted_interface_dat_r + attribute \src "ls180.v:265.13-265.54" + wire width 64 \main_interface0_converted_interface_dat_w + attribute \src "ls180.v:274.5-274.44" + wire \main_interface0_converted_interface_err + attribute \src "ls180.v:267.12-267.51" + wire width 8 \main_interface0_converted_interface_sel + attribute \src "ls180.v:269.6-269.45" + wire \main_interface0_converted_interface_stb + attribute \src "ls180.v:271.6-271.44" + wire \main_interface0_converted_interface_we + attribute \src "ls180.v:1709.6-1709.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1703.12-1703.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1712.11-1712.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1711.11-1711.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1707.5-1707.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1705.13-1705.38" + wire width 64 \main_interface1_bus_dat_r + attribute \src "ls180.v:1704.12-1704.37" + wire width 64 \main_interface1_bus_dat_w + attribute \src "ls180.v:1713.6-1713.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1706.11-1706.34" + wire width 8 \main_interface1_bus_sel + attribute \src "ls180.v:1708.5-1708.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1710.5-1710.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:285.5-285.44" + wire \main_interface1_converted_interface_ack + attribute \src "ls180.v:279.13-279.52" + wire width 30 \main_interface1_converted_interface_adr + attribute \src "ls180.v:288.12-288.51" + wire width 2 \main_interface1_converted_interface_bte + attribute \src "ls180.v:287.12-287.51" + wire width 3 \main_interface1_converted_interface_cti + attribute \src "ls180.v:283.6-283.45" + wire \main_interface1_converted_interface_cyc + attribute \src "ls180.v:281.13-281.54" + wire width 64 \main_interface1_converted_interface_dat_r + attribute \src "ls180.v:280.13-280.54" + wire width 64 \main_interface1_converted_interface_dat_w + attribute \src "ls180.v:289.5-289.44" + wire \main_interface1_converted_interface_err + attribute \src "ls180.v:282.12-282.51" + wire width 8 \main_interface1_converted_interface_sel + attribute \src "ls180.v:284.6-284.45" + wire \main_interface1_converted_interface_stb + attribute \src "ls180.v:286.6-286.44" + wire \main_interface1_converted_interface_we + attribute \src "ls180.v:218.12-218.32" + wire width 4 \main_libresocsim_adr + attribute \src "ls180.v:62.6-62.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:63.12-63.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:59.13-59.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:60.6-60.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:219.13-219.35" + wire width 64 \main_libresocsim_dat_r + attribute \src "ls180.v:221.13-221.35" + wire width 64 \main_libresocsim_dat_w + attribute \src "ls180.v:227.5-227.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:226.5-226.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:243.6-243.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:242.6-242.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:245.6-245.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:244.6-244.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:247.5-247.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:239.6-239.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:238.6-238.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:241.6-241.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:240.6-240.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:246.5-246.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:232.6-232.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:165.6-165.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:166.6-166.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:167.13-167.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:169.12-169.45" + wire width 2 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:196.12-196.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:197.13-197.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:198.13-198.68" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:199.6-199.61" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:200.5-200.62" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:201.6-201.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:202.6-202.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:184.6-184.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + attribute \src "ls180.v:185.5-185.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + attribute \src "ls180.v:186.6-186.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + attribute \src "ls180.v:187.6-187.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + attribute \src "ls180.v:188.11-188.72" + wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i + attribute \src "ls180.v:189.12-189.73" + wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o + attribute \src "ls180.v:190.6-190.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + attribute \src "ls180.v:172.13-172.68" + wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:181.12-181.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:178.6-178.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:180.6-180.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:179.6-179.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:182.12-182.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:173.12-173.70" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:174.13-174.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:175.6-175.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:177.6-177.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:176.6-176.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:203.6-203.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:205.6-205.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:206.6-206.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:204.6-204.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:191.6-191.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + attribute \src "ls180.v:193.6-193.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + attribute \src "ls180.v:194.6-194.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:192.6-192.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + attribute \src "ls180.v:72.6-72.40" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:66.13-66.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.11-75.45" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.11-74.45" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:70.6-70.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:68.13-68.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:67.13-67.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:76.6-76.40" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:69.12-69.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:71.6-71.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:73.6-73.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:83.6-83.40" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:77.13-77.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:86.11-86.45" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.11-85.45" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:79.13-79.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:78.13-78.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:87.6-87.40" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:80.12-80.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:82.6-82.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:84.6-84.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:123.6-123.46" + wire \main_libresocsim_libresoc_interface0_ack + attribute \src "ls180.v:117.13-117.53" + wire width 29 \main_libresocsim_libresoc_interface0_adr + attribute \src "ls180.v:126.12-126.52" + wire width 2 \main_libresocsim_libresoc_interface0_bte + attribute \src "ls180.v:125.12-125.52" + wire width 3 \main_libresocsim_libresoc_interface0_cti + attribute \src "ls180.v:121.6-121.46" + wire \main_libresocsim_libresoc_interface0_cyc + attribute \src "ls180.v:119.13-119.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_r + attribute \src "ls180.v:118.13-118.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_w + attribute \src "ls180.v:127.6-127.46" + wire \main_libresocsim_libresoc_interface0_err + attribute \src "ls180.v:120.12-120.52" + wire width 8 \main_libresocsim_libresoc_interface0_sel + attribute \src "ls180.v:122.6-122.46" + wire \main_libresocsim_libresoc_interface0_stb + attribute \src "ls180.v:124.6-124.45" + wire \main_libresocsim_libresoc_interface0_we + attribute \src "ls180.v:134.6-134.46" + wire \main_libresocsim_libresoc_interface1_ack + attribute \src "ls180.v:128.13-128.53" + wire width 29 \main_libresocsim_libresoc_interface1_adr + attribute \src "ls180.v:137.12-137.52" + wire width 2 \main_libresocsim_libresoc_interface1_bte + attribute \src "ls180.v:136.12-136.52" + wire width 3 \main_libresocsim_libresoc_interface1_cti + attribute \src "ls180.v:132.6-132.46" + wire \main_libresocsim_libresoc_interface1_cyc + attribute \src "ls180.v:130.13-130.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_r + attribute \src "ls180.v:129.13-129.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_w + attribute \src "ls180.v:138.6-138.46" + wire \main_libresocsim_libresoc_interface1_err + attribute \src "ls180.v:131.12-131.52" + wire width 8 \main_libresocsim_libresoc_interface1_sel + attribute \src "ls180.v:133.6-133.46" + wire \main_libresocsim_libresoc_interface1_stb + attribute \src "ls180.v:135.6-135.45" + wire \main_libresocsim_libresoc_interface1_we + attribute \src "ls180.v:145.6-145.46" + wire \main_libresocsim_libresoc_interface2_ack + attribute \src "ls180.v:139.13-139.53" + wire width 29 \main_libresocsim_libresoc_interface2_adr + attribute \src "ls180.v:148.12-148.52" + wire width 2 \main_libresocsim_libresoc_interface2_bte + attribute \src "ls180.v:147.12-147.52" + wire width 3 \main_libresocsim_libresoc_interface2_cti + attribute \src "ls180.v:143.6-143.46" + wire \main_libresocsim_libresoc_interface2_cyc + attribute \src "ls180.v:141.13-141.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_r + attribute \src "ls180.v:140.13-140.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_w + attribute \src "ls180.v:149.6-149.46" + wire \main_libresocsim_libresoc_interface2_err + attribute \src "ls180.v:142.12-142.52" + wire width 8 \main_libresocsim_libresoc_interface2_sel + attribute \src "ls180.v:144.6-144.46" + wire \main_libresocsim_libresoc_interface2_stb + attribute \src "ls180.v:146.6-146.45" + wire \main_libresocsim_libresoc_interface2_we + attribute \src "ls180.v:156.6-156.46" + wire \main_libresocsim_libresoc_interface3_ack + attribute \src "ls180.v:150.13-150.53" + wire width 29 \main_libresocsim_libresoc_interface3_adr + attribute \src "ls180.v:159.12-159.52" + wire width 2 \main_libresocsim_libresoc_interface3_bte + attribute \src "ls180.v:158.12-158.52" + wire width 3 \main_libresocsim_libresoc_interface3_cti + attribute \src "ls180.v:154.6-154.46" + wire \main_libresocsim_libresoc_interface3_cyc + attribute \src "ls180.v:152.13-152.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_r + attribute \src "ls180.v:151.13-151.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_w + attribute \src "ls180.v:160.6-160.46" + wire \main_libresocsim_libresoc_interface3_err + attribute \src "ls180.v:153.12-153.52" + wire width 8 \main_libresocsim_libresoc_interface3_sel + attribute \src "ls180.v:155.6-155.46" + wire \main_libresocsim_libresoc_interface3_stb + attribute \src "ls180.v:157.6-157.45" + wire \main_libresocsim_libresoc_interface3_we + attribute \src "ls180.v:65.12-65.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:161.6-161.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:163.6-163.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:164.6-164.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:162.6-162.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:112.6-112.43" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:106.13-106.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:115.11-115.48" + wire width 2 \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:114.11-114.48" + wire width 3 \main_libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:110.6-110.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:108.13-108.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:107.13-107.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:116.6-116.43" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:109.12-109.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:111.6-111.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:113.6-113.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:168.6-168.40" + wire \main_libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:170.6-170.41" + wire \main_libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:64.6-64.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:94.6-94.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:88.12-88.50" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:92.5-92.43" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:90.13-90.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:89.12-89.52" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:96.6-96.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:91.11-91.49" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:93.5-93.43" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:95.5-95.42" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:97.12-97.50" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:101.5-101.43" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:99.13-99.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:98.12-98.52" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:105.6-105.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:100.11-100.49" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:102.5-102.43" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:104.5-104.42" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:223.5-223.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:222.12-222.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:213.5-213.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:207.13-207.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:216.12-216.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:215.12-215.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:211.6-211.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:209.13-209.43" + wire width 64 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:208.13-208.43" + wire width 64 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:217.5-217.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:210.12-210.40" + wire width 8 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:212.6-212.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:214.6-214.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:225.5-225.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:224.12-224.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:61.6-61.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:56.5-56.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:55.5-55.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:58.5-58.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:57.12-57.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:229.5-229.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:228.5-228.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:248.12-248.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:230.12-230.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:231.6-231.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:220.11-220.30" + wire width 8 \main_libresocsim_we + attribute \src "ls180.v:236.5-236.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:237.5-237.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:234.5-234.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:233.6-233.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:235.6-235.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:887.6-887.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:881.12-881.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:885.5-885.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:883.13-883.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:882.12-882.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:884.11-884.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:886.5-886.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:888.5-888.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:1129.13-1129.20" + wire width 24 \main_nc + attribute \src "ls180.v:848.6-848.24" + wire \main_port_cmd_last + attribute \src "ls180.v:850.13-850.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:849.6-849.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:847.6-847.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:846.6-846.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:845.6-845.21" + wire \main_port_flush + attribute \src "ls180.v:857.13-857.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:856.6-856.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:855.6-855.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:853.13-853.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:854.12-854.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:852.6-852.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:851.6-851.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1134.12-1134.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:1131.6-1131.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1136.5-1136.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1135.5-1135.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1133.13-1133.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1140.5-1140.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1139.12-1139.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1132.13-1132.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1138.5-1138.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1137.12-1137.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1144.12-1144.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1141.6-1141.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1146.5-1146.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1145.5-1145.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1143.13-1143.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1150.5-1150.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1149.12-1149.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1142.13-1142.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1148.5-1148.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1147.12-1147.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:260.12-260.24" + wire width 4 \main_ram_adr + attribute \src "ls180.v:255.5-255.29" + wire \main_ram_bus_ram_bus_ack + attribute \src "ls180.v:249.13-249.37" + wire width 30 \main_ram_bus_ram_bus_adr + attribute \src "ls180.v:258.12-258.36" + wire width 2 \main_ram_bus_ram_bus_bte + attribute \src "ls180.v:257.12-257.36" + wire width 3 \main_ram_bus_ram_bus_cti + attribute \src "ls180.v:253.6-253.30" + wire \main_ram_bus_ram_bus_cyc + attribute \src "ls180.v:251.13-251.39" + wire width 64 \main_ram_bus_ram_bus_dat_r + attribute \src "ls180.v:250.13-250.39" + wire width 64 \main_ram_bus_ram_bus_dat_w + attribute \src "ls180.v:259.5-259.29" + wire \main_ram_bus_ram_bus_err + attribute \src "ls180.v:252.12-252.36" + wire width 8 \main_ram_bus_ram_bus_sel + attribute \src "ls180.v:254.6-254.30" + wire \main_ram_bus_ram_bus_stb + attribute \src "ls180.v:256.6-256.29" + wire \main_ram_bus_ram_bus_we + attribute \src "ls180.v:261.13-261.27" + wire width 64 \main_ram_dat_r + attribute \src "ls180.v:263.13-263.27" + wire width 64 \main_ram_dat_w + attribute \src "ls180.v:262.11-262.22" + wire width 8 \main_ram_we + attribute \src "ls180.v:314.11-314.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:1672.11-1672.43" + wire width 3 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1673.6-1673.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1663.6-1663.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1664.6-1664.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1665.12-1665.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1662.6-1662.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1661.6-1661.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1668.5-1668.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1669.5-1669.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1670.12-1670.58" + wire width 64 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1671.11-1671.70" + wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1667.6-1667.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1666.6-1666.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1674.5-1674.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1647.11-1647.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1652.6-1652.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1656.6-1656.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1657.6-1657.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1655.12-1655.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1659.6-1659.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1660.6-1660.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1658.12-1658.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1644.11-1644.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1646.11-1646.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1653.12-1653.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1654.12-1654.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1645.5-1645.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1630.6-1630.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1631.6-1631.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1632.12-1632.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1629.6-1629.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1628.6-1628.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1635.6-1635.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1636.6-1636.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1637.12-1637.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1634.6-1634.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1633.6-1633.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1642.12-1642.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1643.12-1643.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1640.6-1640.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1641.6-1641.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1638.6-1638.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1639.6-1639.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1648.11-1648.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1649.12-1649.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1651.12-1651.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1650.6-1650.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1625.6-1625.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1626.6-1626.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1682.12-1682.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1627.12-1627.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1683.12-1683.52" + wire width 64 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1624.6-1624.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1681.6-1681.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1623.6-1623.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1680.5-1680.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1677.6-1677.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1678.6-1678.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1679.13-1679.56" + wire width 64 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1676.6-1676.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1675.6-1675.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1699.13-1699.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1690.5-1690.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1689.12-1689.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1694.5-1694.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1693.5-1693.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1701.13-1701.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1692.5-1692.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1691.12-1691.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1698.5-1698.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1697.5-1697.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1700.12-1700.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1920.12-1920.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1921.5-1921.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1702.6-1702.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1686.6-1686.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1687.6-1687.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1688.13-1688.65" + wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1685.5-1685.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1684.6-1684.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1695.5-1695.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1696.6-1696.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1464.5-1464.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1463.12-1463.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1462.5-1462.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1461.11-1461.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1448.5-1448.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1447.12-1447.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1450.5-1450.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1449.12-1449.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1603.11-1603.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1904.11-1904.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1905.5-1905.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1604.5-1604.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1900.5-1900.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1901.5-1901.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1605.5-1605.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1908.5-1908.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1909.5-1909.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1457.12-1457.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1458.6-1458.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1455.13-1455.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1916.13-1916.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1917.5-1917.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1456.6-1456.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1452.6-1452.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1451.6-1451.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1454.5-1454.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1453.6-1453.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1606.5-1606.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1910.5-1910.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1911.5-1911.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1602.12-1602.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1564.11-1564.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1570.5-1570.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1569.12-1569.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1565.12-1565.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1566.13-1566.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1567.13-1567.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1571.6-1571.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1568.12-1568.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1577.5-1577.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1576.12-1576.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1572.12-1572.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1573.13-1573.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1574.13-1574.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1578.6-1578.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1575.12-1575.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1584.5-1584.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1583.12-1583.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1579.12-1579.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1580.13-1580.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1581.13-1581.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1585.6-1585.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1582.12-1582.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1591.5-1591.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1590.12-1590.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1586.12-1586.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1587.13-1587.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1588.13-1588.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1592.6-1592.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1589.12-1589.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1593.12-1593.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1594.12-1594.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1595.12-1595.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1596.12-1596.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1598.12-1598.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1599.12-1599.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1600.12-1600.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1601.12-1601.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1555.5-1555.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1556.5-1556.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1557.11-1557.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1554.5-1554.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1553.5-1553.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1560.5-1560.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1561.6-1561.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1562.12-1562.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1559.6-1559.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1558.5-1558.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1563.11-1563.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1597.5-1597.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1520.11-1520.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1896.11-1896.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1897.5-1897.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1526.6-1526.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1525.12-1525.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1521.12-1521.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1522.13-1522.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1523.13-1523.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1527.6-1527.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1524.12-1524.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1533.6-1533.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1532.12-1532.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1528.12-1528.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1529.13-1529.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1530.13-1530.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1534.6-1534.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1531.12-1531.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1540.6-1540.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1539.12-1539.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1535.12-1535.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1536.13-1536.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1537.13-1537.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1541.6-1541.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1538.12-1538.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1547.6-1547.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1546.12-1546.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1542.12-1542.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1543.13-1543.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1544.13-1544.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1548.6-1548.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1545.12-1545.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1549.12-1549.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1888.12-1888.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1889.5-1889.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1550.12-1550.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1890.12-1890.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1891.5-1891.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1551.12-1551.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1892.12-1892.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1893.5-1893.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1552.12-1552.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1894.12-1894.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1895.5-1895.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1512.6-1512.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1513.6-1513.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1514.12-1514.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1511.5-1511.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1510.6-1510.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1517.5-1517.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1518.5-1518.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1519.11-1519.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1516.5-1516.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1515.5-1515.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1508.6-1508.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1507.11-1507.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1465.11-1465.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1466.12-1466.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1475.12-1475.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1476.12-1476.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1477.12-1477.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1478.12-1478.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1479.12-1479.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1480.12-1480.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1481.12-1481.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1482.12-1482.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1483.12-1483.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1484.12-1484.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1467.12-1467.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1485.12-1485.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1486.12-1486.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1487.12-1487.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1488.12-1488.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1489.12-1489.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1490.12-1490.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1491.12-1491.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1492.12-1492.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1493.12-1493.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1494.12-1494.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1468.12-1468.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1495.12-1495.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1496.12-1496.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1497.12-1497.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1498.12-1498.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1499.12-1499.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1500.12-1500.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1501.12-1501.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1502.12-1502.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1503.12-1503.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1504.12-1504.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1469.12-1469.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1505.12-1505.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1470.12-1470.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1471.12-1471.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1472.12-1472.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1473.12-1473.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1474.12-1474.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1509.6-1509.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1506.13-1506.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1608.12-1608.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1906.12-1906.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1907.5-1907.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1609.5-1609.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1902.5-1902.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1903.5-1903.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1610.5-1610.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1912.5-1912.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1913.5-1913.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1459.12-1459.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1460.6-1460.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1611.5-1611.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1914.5-1914.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1915.5-1915.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1607.12-1607.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1439.6-1439.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1440.6-1440.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1441.12-1441.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1438.6-1438.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1437.6-1437.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1444.6-1444.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1445.6-1445.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1446.12-1446.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1443.6-1443.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1442.6-1442.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1757.6-1757.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1758.6-1758.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1756.11-1756.41" + wire width 3 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1747.6-1747.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1748.6-1748.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1749.13-1749.57" + wire width 64 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1746.6-1746.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1745.6-1745.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1752.6-1752.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1753.6-1753.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1754.11-1754.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1755.6-1755.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1751.6-1751.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1750.6-1750.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1741.13-1741.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1730.5-1730.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1729.12-1729.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1728.12-1728.37" + wire width 64 \main_sdmem2block_dma_data + attribute \src "ls180.v:1924.12-1924.67" + wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1925.5-1925.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1735.5-1735.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1736.6-1736.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1734.5-1734.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1733.5-1733.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1743.13-1743.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1732.5-1732.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1731.12-1731.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1738.5-1738.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1737.5-1737.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1742.12-1742.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1928.12-1928.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1929.5-1929.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1739.13-1739.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1740.6-1740.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1744.6-1744.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1721.5-1721.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1722.12-1722.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1720.5-1720.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1719.5-1719.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1725.5-1725.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1726.5-1726.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1727.12-1727.52" + wire width 64 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1724.6-1724.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1723.5-1723.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1783.11-1783.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1788.6-1788.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1792.6-1792.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1793.6-1793.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1791.12-1791.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1795.6-1795.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1796.6-1796.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1794.12-1794.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1780.11-1780.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1782.11-1782.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1789.12-1789.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1790.12-1790.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1781.5-1781.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1766.6-1766.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1767.6-1767.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1768.12-1768.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1765.6-1765.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1764.6-1764.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1771.6-1771.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1772.6-1772.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1773.12-1773.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1770.6-1770.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1769.6-1769.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1778.12-1778.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1779.12-1779.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1776.6-1776.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1777.6-1777.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1774.6-1774.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1775.6-1775.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1784.11-1784.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1785.12-1785.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1787.12-1787.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1786.6-1786.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1716.6-1716.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1761.6-1761.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1717.6-1717.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1762.6-1762.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1718.12-1718.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1763.12-1763.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1715.6-1715.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1760.6-1760.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1714.6-1714.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1759.6-1759.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1165.6-1165.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1164.5-1164.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1167.5-1167.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1168.5-1168.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1166.11-1166.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1162.5-1162.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1163.6-1163.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1161.11-1161.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1265.6-1265.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1266.6-1266.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1267.12-1267.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1264.6-1264.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1263.6-1263.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1270.5-1270.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1271.5-1271.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1272.11-1272.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1269.6-1269.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1268.5-1268.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1255.11-1255.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1256.6-1256.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1246.5-1246.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1247.5-1247.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1248.6-1248.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1245.6-1245.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1244.6-1244.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1251.5-1251.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1252.5-1252.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1253.11-1253.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1254.11-1254.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1250.6-1250.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1249.6-1249.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1257.5-1257.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1228.6-1228.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1229.6-1229.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1230.6-1230.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1231.6-1231.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1232.6-1232.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1233.6-1233.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1234.12-1234.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1235.12-1235.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1236.6-1236.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1227.5-1227.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1226.6-1226.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1273.5-1273.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1868.5-1868.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1869.5-1869.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1243.5-1243.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1239.6-1239.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1260.6-1260.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1240.6-1240.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1261.6-1261.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1241.12-1241.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1262.12-1262.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1238.5-1238.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1259.6-1259.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1237.6-1237.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1258.6-1258.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1242.6-1242.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1225.11-1225.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1864.11-1864.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1865.5-1865.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1200.5-1200.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1201.5-1201.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1202.5-1202.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1203.6-1203.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1204.5-1204.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1205.5-1205.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1206.12-1206.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1207.11-1207.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1208.5-1208.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1199.6-1199.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1198.6-1198.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1210.5-1210.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1211.5-1211.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1212.5-1212.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1213.11-1213.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1214.5-1214.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1209.6-1209.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1217.5-1217.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1218.11-1218.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1216.5-1216.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1215.5-1215.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1221.5-1221.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1222.11-1222.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1223.11-1223.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1220.5-1220.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1219.5-1219.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1224.12-1224.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1866.12-1866.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1867.5-1867.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1197.11-1197.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1860.11-1860.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1861.5-1861.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1196.5-1196.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1184.6-1184.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1185.12-1185.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1183.6-1183.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1187.5-1187.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1188.5-1188.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1189.5-1189.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1190.11-1190.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1191.5-1191.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1186.6-1186.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1194.5-1194.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1195.11-1195.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1193.5-1193.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1192.5-1192.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1381.11-1381.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1880.11-1880.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1881.5-1881.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1421.6-1421.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1422.6-1422.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1423.12-1423.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1420.6-1420.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1419.6-1419.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1426.5-1426.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1427.5-1427.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1428.11-1428.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1425.6-1425.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1424.5-1424.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1411.5-1411.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1412.6-1412.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1402.5-1402.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1403.5-1403.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1404.12-1404.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1401.6-1401.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1400.6-1400.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1407.5-1407.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1408.5-1408.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1409.11-1409.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1410.11-1410.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1406.6-1406.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1405.6-1405.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1413.5-1413.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1384.6-1384.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1385.6-1385.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1386.6-1386.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1387.6-1387.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1388.6-1388.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1389.6-1389.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1390.12-1390.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1391.12-1391.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1392.6-1392.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1383.5-1383.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1382.6-1382.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1429.5-1429.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1884.5-1884.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1885.5-1885.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1399.5-1399.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1395.6-1395.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1416.6-1416.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1396.6-1396.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1417.6-1417.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1397.12-1397.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1418.12-1418.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1394.5-1394.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1415.6-1415.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1393.6-1393.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1414.6-1414.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1398.6-1398.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1354.5-1354.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1355.5-1355.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1356.5-1356.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1357.6-1357.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1358.5-1358.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1359.5-1359.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1360.12-1360.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1361.11-1361.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1362.5-1362.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1353.6-1353.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1352.6-1352.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1364.5-1364.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1365.5-1365.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1366.5-1366.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1367.11-1367.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1368.5-1368.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1363.6-1363.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1371.5-1371.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1372.11-1372.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1370.5-1370.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1369.5-1369.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1375.5-1375.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1376.5-1376.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1377.11-1377.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1378.11-1378.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1374.5-1374.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1373.5-1373.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1379.5-1379.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1380.12-1380.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1882.12-1882.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1883.5-1883.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1289.11-1289.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1876.11-1876.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1877.5-1877.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1343.6-1343.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1344.6-1344.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1345.12-1345.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1342.6-1342.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1341.6-1341.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1348.5-1348.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1349.5-1349.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1350.11-1350.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1347.6-1347.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1346.5-1346.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1333.11-1333.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1334.6-1334.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1324.5-1324.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1325.5-1325.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1326.6-1326.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1323.6-1323.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1322.6-1322.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1329.5-1329.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1330.5-1330.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1331.11-1331.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1332.11-1332.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1328.6-1328.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1327.6-1327.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1335.5-1335.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1306.6-1306.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1307.6-1307.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1308.6-1308.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1309.6-1309.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1310.6-1310.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1311.6-1311.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1312.12-1312.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1313.12-1313.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1314.6-1314.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1305.5-1305.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1304.6-1304.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1351.5-1351.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1872.5-1872.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1873.5-1873.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1321.5-1321.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1317.6-1317.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1338.6-1338.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1318.6-1318.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1339.6-1339.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1319.12-1319.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1340.12-1340.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1316.5-1316.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1337.6-1337.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1315.6-1315.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1336.6-1336.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1320.6-1320.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1303.5-1303.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1292.5-1292.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1293.5-1293.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1294.5-1294.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1295.5-1295.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1296.5-1296.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1297.5-1297.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1298.11-1298.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1299.11-1299.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1300.5-1300.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1291.6-1291.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1290.5-1290.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1275.6-1275.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1276.12-1276.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1274.6-1274.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1278.5-1278.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1279.5-1279.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1280.5-1280.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1281.11-1281.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1282.5-1282.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1277.6-1277.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1285.5-1285.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1286.5-1286.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1287.11-1287.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1284.5-1284.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1283.5-1283.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1301.5-1301.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1288.5-1288.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1302.5-1302.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1182.11-1182.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1856.11-1856.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1857.5-1857.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1170.6-1170.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1169.6-1169.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1172.5-1172.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1171.6-1171.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1174.6-1174.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1175.12-1175.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1173.6-1173.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1177.5-1177.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1178.5-1178.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1179.5-1179.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1180.11-1180.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1181.5-1181.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1176.6-1176.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1430.6-1430.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1431.5-1431.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1432.6-1432.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1433.6-1433.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1434.11-1434.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1435.12-1435.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1436.6-1436.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1159.6-1159.23" + wire \main_sdphy_status + attribute \src "ls180.v:1160.6-1160.19" + wire \main_sdphy_we + attribute \src "ls180.v:376.5-376.26" + wire \main_sdram_address_re + attribute \src "ls180.v:375.12-375.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:378.5-378.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:377.11-377.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:474.5-474.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:496.11-496.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:501.6-501.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:506.6-506.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:507.6-507.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:505.13-505.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:504.6-504.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:510.6-510.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:511.6-511.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:509.13-509.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:508.6-508.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:493.11-493.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:495.11-495.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:502.12-502.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:503.13-503.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:494.5-494.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:477.5-477.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:478.5-478.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:480.13-480.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:479.6-479.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:476.6-476.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:475.6-475.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:483.6-483.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:484.6-484.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:486.13-486.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:485.6-485.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:482.6-482.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:481.6-481.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:491.13-491.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:492.13-492.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:489.6-489.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:490.6-490.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:487.6-487.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:488.6-488.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:497.11-497.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:498.13-498.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:500.13-500.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:499.6-499.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:514.6-514.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:515.6-515.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:517.13-517.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:516.6-516.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:513.6-513.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:512.6-512.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:520.5-520.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:521.5-521.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:523.12-523.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:522.5-522.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:519.6-519.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:518.5-518.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:466.12-466.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:467.12-467.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:468.5-468.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:471.5-471.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:472.5-472.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:473.5-473.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:469.5-469.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:470.5-470.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:465.5-465.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:464.5-464.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:463.5-463.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:462.6-462.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:458.13-458.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:459.6-459.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:461.5-461.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:456.6-456.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:455.6-455.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:460.5-460.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:457.6-457.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:524.12-524.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:528.5-528.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:529.5-529.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:526.6-526.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:527.5-527.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:525.5-525.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:536.32-536.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:535.6-535.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:534.32-534.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:533.6-533.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:532.11-532.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:531.32-531.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:530.6-530.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:556.5-556.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:578.11-578.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:583.6-583.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:588.6-588.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:589.6-589.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:587.13-587.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:586.6-586.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:592.6-592.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:593.6-593.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:591.13-591.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:590.6-590.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:575.11-575.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:577.11-577.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:584.12-584.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:585.13-585.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:576.5-576.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:559.5-559.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:560.5-560.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:562.13-562.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:561.6-561.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:558.6-558.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:557.6-557.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:565.6-565.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:566.6-566.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:568.13-568.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:567.6-567.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:564.6-564.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:563.6-563.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:573.13-573.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:574.13-574.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:571.6-571.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:572.6-572.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:569.6-569.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:570.6-570.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:579.11-579.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:580.13-580.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:582.13-582.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:581.6-581.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:596.6-596.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:597.6-597.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:599.13-599.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:598.6-598.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:595.6-595.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:594.6-594.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:602.5-602.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:603.5-603.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:605.12-605.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:604.5-604.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:601.6-601.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:600.5-600.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:548.12-548.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:549.12-549.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:550.5-550.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:553.5-553.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:554.5-554.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:555.5-555.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:551.5-551.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:552.5-552.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:547.5-547.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:546.5-546.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:545.5-545.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:544.6-544.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:540.13-540.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:541.6-541.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:543.5-543.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:538.6-538.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:537.6-537.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:542.5-542.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:539.6-539.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:606.12-606.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:610.5-610.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:611.5-611.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:608.6-608.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:609.5-609.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:607.5-607.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:618.32-618.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:617.6-617.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:616.32-616.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:615.6-615.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:614.11-614.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:613.32-613.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:612.6-612.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:638.5-638.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:660.11-660.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:665.6-665.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:670.6-670.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:671.6-671.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:669.13-669.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:668.6-668.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:674.6-674.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:675.6-675.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:673.13-673.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:672.6-672.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:657.11-657.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:659.11-659.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:666.12-666.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:667.13-667.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:658.5-658.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:641.5-641.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:642.5-642.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:644.13-644.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:643.6-643.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:640.6-640.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:639.6-639.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:647.6-647.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:648.6-648.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:650.13-650.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:649.6-649.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:646.6-646.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:645.6-645.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:655.13-655.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:656.13-656.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:653.6-653.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:654.6-654.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:651.6-651.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:652.6-652.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:661.11-661.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:662.13-662.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:664.13-664.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:663.6-663.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:678.6-678.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:679.6-679.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:681.13-681.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:680.6-680.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:677.6-677.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:676.6-676.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:684.5-684.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:685.5-685.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:687.12-687.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:686.5-686.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:683.6-683.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:682.5-682.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:630.12-630.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:631.12-631.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:632.5-632.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:635.5-635.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:636.5-636.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:637.5-637.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:633.5-633.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:634.5-634.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:629.5-629.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:628.5-628.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:627.5-627.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:626.6-626.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:622.13-622.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:623.6-623.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:625.5-625.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:620.6-620.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:619.6-619.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:624.5-624.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:621.6-621.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:688.12-688.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:692.5-692.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:693.5-693.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:690.6-690.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:691.5-691.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:689.5-689.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:700.32-700.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:699.6-699.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:698.32-698.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:697.6-697.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:696.11-696.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:695.32-695.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:694.6-694.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:720.5-720.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:742.11-742.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:747.6-747.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:752.6-752.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:753.6-753.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:751.13-751.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:750.6-750.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:756.6-756.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:757.6-757.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:755.13-755.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:754.6-754.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:739.11-739.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:741.11-741.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:748.12-748.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:749.13-749.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:740.5-740.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:723.5-723.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:724.5-724.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:726.13-726.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:725.6-725.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:722.6-722.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:721.6-721.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:729.6-729.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:730.6-730.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:732.13-732.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:731.6-731.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:728.6-728.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:727.6-727.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:737.13-737.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:738.13-738.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:735.6-735.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:736.6-736.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:733.6-733.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:734.6-734.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:743.11-743.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:744.13-744.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:746.13-746.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:745.6-745.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:760.6-760.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:761.6-761.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:763.13-763.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:762.6-762.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:759.6-759.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:758.6-758.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:766.5-766.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:767.5-767.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:769.12-769.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:768.5-768.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:765.6-765.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:764.5-764.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:712.12-712.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:713.12-713.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:714.5-714.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:717.5-717.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:718.5-718.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:719.5-719.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:715.5-715.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:716.5-716.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:711.5-711.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:710.5-710.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:709.5-709.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:708.6-708.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:704.13-704.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:705.6-705.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:707.5-707.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:702.6-702.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:701.6-701.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:706.5-706.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:703.6-703.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:770.12-770.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:774.5-774.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:775.5-775.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:772.6-772.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:773.5-773.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:771.5-771.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:782.32-782.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:781.6-781.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:780.32-780.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:779.6-779.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:778.11-778.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:777.32-777.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:776.6-776.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:784.6-784.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:802.6-802.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:791.13-791.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:792.12-792.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:793.5-793.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:796.6-796.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:797.6-797.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:798.6-798.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:794.5-794.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:795.5-795.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:790.5-790.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:789.6-789.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:801.11-801.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:800.12-800.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:799.11-799.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:788.5-788.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:787.5-787.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:785.5-785.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:786.5-786.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:820.6-820.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:809.13-809.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:810.12-810.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:811.5-811.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:814.6-814.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:815.6-815.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:816.6-816.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:812.5-812.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:813.5-813.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:808.5-808.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:807.6-807.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:819.11-819.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:818.12-818.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:817.11-817.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:806.5-806.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:805.6-805.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:803.5-803.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:804.5-804.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:364.6-364.20" + wire \main_sdram_cke + attribute \src "ls180.v:432.5-432.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:433.12-433.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:434.11-434.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:435.5-435.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:438.5-438.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:439.5-439.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:436.5-436.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:437.5-437.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:431.5-431.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:430.5-430.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:372.6-372.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:371.6-371.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:374.5-374.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:373.6-373.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:370.5-370.26" + wire \main_sdram_command_re + attribute \src "ls180.v:369.11-369.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:423.5-423.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:414.12-414.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:415.11-415.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:416.5-416.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:420.6-420.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:417.5-417.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:421.6-421.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:418.5-418.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:428.13-428.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:427.5-427.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:429.6-429.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:422.6-422.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:419.5-419.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:424.13-424.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:425.5-425.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:426.12-426.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:838.5-838.19" + wire \main_sdram_en0 + attribute \src "ls180.v:841.5-841.19" + wire \main_sdram_en1 + attribute \src "ls180.v:844.6-844.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:386.13-386.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:387.6-387.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:389.6-389.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:384.6-384.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:383.6-383.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:388.6-388.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:385.6-385.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:393.13-393.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:394.6-394.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:396.6-396.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:391.6-391.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:390.6-390.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:395.6-395.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:392.6-392.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:400.13-400.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:401.6-401.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:403.6-403.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:398.6-398.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:397.6-397.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:402.6-402.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:399.6-399.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:407.13-407.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:408.6-408.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:410.6-410.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:405.6-405.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:404.6-404.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:409.6-409.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:406.6-406.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:413.13-413.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:411.12-411.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:412.11-412.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:324.5-324.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:315.13-315.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:316.12-316.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:317.5-317.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:321.6-321.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:318.5-318.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:322.6-322.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:319.5-319.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:329.12-329.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:328.6-328.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:330.5-330.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:323.6-323.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:320.5-320.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:325.13-325.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:326.6-326.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:327.12-327.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:356.5-356.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:347.12-347.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:348.11-348.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:349.5-349.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:353.5-353.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:350.5-350.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:354.5-354.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:351.5-351.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:361.13-361.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:360.5-360.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:362.6-362.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:355.5-355.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:352.5-352.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:357.12-357.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:358.5-358.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:359.11-359.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:839.6-839.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:842.6-842.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:821.12-821.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:822.11-822.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:365.6-365.20" + wire \main_sdram_odt + attribute \src "ls180.v:448.5-448.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:446.6-446.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:447.5-447.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:783.6-783.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:368.5-368.18" + wire \main_sdram_re + attribute \src "ls180.v:836.6-836.31" + wire \main_sdram_read_available + attribute \src "ls180.v:366.6-366.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:363.6-363.20" + wire \main_sdram_sel + attribute \src "ls180.v:454.5-454.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:453.11-453.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:450.6-450.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:452.5-452.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:449.5-449.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:451.6-451.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:340.6-340.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:331.13-331.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:332.12-332.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:333.6-333.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:337.6-337.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:334.6-334.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:338.6-338.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:335.6-335.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:345.12-345.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:344.6-344.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:346.5-346.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:339.6-339.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:336.6-336.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:341.13-341.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:342.6-342.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:343.12-343.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:381.12-381.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:824.5-824.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:825.5-825.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:823.11-823.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:367.11-367.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:832.5-832.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:831.32-831.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:830.6-830.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:829.32-829.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:828.6-828.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:840.11-840.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:843.11-843.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:443.12-443.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:445.11-445.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:442.6-442.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:444.6-444.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:441.6-441.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:827.32-827.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:826.6-826.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:835.11-835.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:834.32-834.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:833.6-833.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:440.6-440.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:382.6-382.19" + wire \main_sdram_we + attribute \src "ls180.v:380.5-380.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:379.12-379.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:837.6-837.32" + wire \main_sdram_write_available + attribute \src "ls180.v:872.5-872.47" + wire \main_socbushandler_converted_interface_ack + attribute \src "ls180.v:866.13-866.55" + wire width 30 \main_socbushandler_converted_interface_adr + attribute \src "ls180.v:875.12-875.54" + wire width 2 \main_socbushandler_converted_interface_bte + attribute \src "ls180.v:874.12-874.54" + wire width 3 \main_socbushandler_converted_interface_cti + attribute \src "ls180.v:870.6-870.48" + wire \main_socbushandler_converted_interface_cyc + attribute \src "ls180.v:868.13-868.57" + wire width 64 \main_socbushandler_converted_interface_dat_r + attribute \src "ls180.v:867.13-867.57" + wire width 64 \main_socbushandler_converted_interface_dat_w + attribute \src "ls180.v:876.5-876.47" + wire \main_socbushandler_converted_interface_err + attribute \src "ls180.v:869.12-869.54" + wire width 8 \main_socbushandler_converted_interface_sel + attribute \src "ls180.v:871.6-871.48" + wire \main_socbushandler_converted_interface_stb + attribute \src "ls180.v:873.6-873.47" + wire \main_socbushandler_converted_interface_we + attribute \src "ls180.v:878.5-878.31" + wire \main_socbushandler_counter + attribute \src "ls180.v:1807.5-1807.53" + wire \main_socbushandler_counter_converter2_next_value + attribute \src "ls180.v:1808.5-1808.56" + wire \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:880.12-880.36" + wire width 64 \main_socbushandler_dat_r + attribute \src "ls180.v:879.6-879.30" + wire \main_socbushandler_reset + attribute \src "ls180.v:877.5-877.28" + wire \main_socbushandler_skip + attribute \src "ls180.v:1055.6-1055.27" + wire \main_spimaster0_start + attribute \src "ls180.v:1065.12-1065.35" + wire width 8 \main_spimaster10_length + attribute \src "ls180.v:1066.12-1066.36" + wire width 16 \main_spimaster11_storage + attribute \src "ls180.v:1067.5-1067.24" + wire \main_spimaster12_re + attribute \src "ls180.v:1068.6-1068.27" + wire \main_spimaster13_done + attribute \src "ls180.v:1069.6-1069.29" + wire \main_spimaster14_status + attribute \src "ls180.v:1070.6-1070.25" + wire \main_spimaster15_we + attribute \src "ls180.v:1071.11-1071.35" + wire width 8 \main_spimaster16_storage + attribute \src "ls180.v:1072.5-1072.24" + wire \main_spimaster17_re + attribute \src "ls180.v:1073.12-1073.35" + wire width 8 \main_spimaster18_status + attribute \src "ls180.v:1074.6-1074.25" + wire \main_spimaster19_we + attribute \src "ls180.v:1056.12-1056.34" + wire width 8 \main_spimaster1_length + attribute \src "ls180.v:1128.5-1128.23" + wire \main_spimaster1_re + attribute \src "ls180.v:1127.12-1127.35" + wire width 16 \main_spimaster1_storage + attribute \src "ls180.v:1075.6-1075.26" + wire \main_spimaster20_sel + attribute \src "ls180.v:1076.5-1076.29" + wire \main_spimaster21_storage + attribute \src "ls180.v:1077.5-1077.24" + wire \main_spimaster22_re + attribute \src "ls180.v:1078.5-1078.29" + wire \main_spimaster23_storage + attribute \src "ls180.v:1079.5-1079.24" + wire \main_spimaster24_re + attribute \src "ls180.v:1080.5-1080.32" + wire \main_spimaster25_clk_enable + attribute \src "ls180.v:1081.5-1081.31" + wire \main_spimaster26_cs_enable + attribute \src "ls180.v:1082.11-1082.33" + wire width 3 \main_spimaster27_count + attribute \src "ls180.v:1848.11-1848.55" + wire width 3 \main_spimaster27_count_spimaster0_next_value + attribute \src "ls180.v:1849.5-1849.52" + wire \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:1083.5-1083.32" + wire \main_spimaster28_mosi_latch + attribute \src "ls180.v:1084.5-1084.32" + wire \main_spimaster29_miso_latch + attribute \src "ls180.v:1057.5-1057.25" + wire \main_spimaster2_done + attribute \src "ls180.v:1085.12-1085.40" + wire width 16 \main_spimaster30_clk_divider + attribute \src "ls180.v:1086.6-1086.31" + wire \main_spimaster31_clk_rise + attribute \src "ls180.v:1087.6-1087.31" + wire \main_spimaster32_clk_fall + attribute \src "ls180.v:1088.11-1088.37" + wire width 8 \main_spimaster33_mosi_data + attribute \src "ls180.v:1089.11-1089.36" + wire width 3 \main_spimaster34_mosi_sel + attribute \src "ls180.v:1090.11-1090.37" + wire width 8 \main_spimaster35_miso_data + attribute \src "ls180.v:1058.5-1058.24" + wire \main_spimaster3_irq + attribute \src "ls180.v:1059.12-1059.32" + wire width 8 \main_spimaster4_mosi + attribute \src "ls180.v:1060.11-1060.31" + wire width 8 \main_spimaster5_miso + attribute \src "ls180.v:1061.6-1061.24" + wire \main_spimaster6_cs + attribute \src "ls180.v:1062.6-1062.30" + wire \main_spimaster7_loopback + attribute \src "ls180.v:1063.12-1063.39" + wire width 16 \main_spimaster8_clk_divider + attribute \src "ls180.v:1064.5-1064.26" + wire \main_spimaster9_start + attribute \src "ls180.v:1099.13-1099.40" + wire width 16 \main_spisdcard_clk_divider0 + attribute \src "ls180.v:1121.12-1121.39" + wire width 16 \main_spisdcard_clk_divider1 + attribute \src "ls180.v:1116.5-1116.30" + wire \main_spisdcard_clk_enable + attribute \src "ls180.v:1123.6-1123.29" + wire \main_spisdcard_clk_fall + attribute \src "ls180.v:1122.6-1122.29" + wire \main_spisdcard_clk_rise + attribute \src "ls180.v:1103.5-1103.30" + wire \main_spisdcard_control_re + attribute \src "ls180.v:1102.12-1102.42" + wire width 16 \main_spisdcard_control_storage + attribute \src "ls180.v:1118.11-1118.31" + wire width 3 \main_spisdcard_count + attribute \src "ls180.v:1852.11-1852.53" + wire width 3 \main_spisdcard_count_spimaster1_next_value + attribute \src "ls180.v:1853.5-1853.50" + wire \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:1097.6-1097.23" + wire \main_spisdcard_cs + attribute \src "ls180.v:1117.5-1117.29" + wire \main_spisdcard_cs_enable + attribute \src "ls180.v:1113.5-1113.25" + wire \main_spisdcard_cs_re + attribute \src "ls180.v:1112.5-1112.30" + wire \main_spisdcard_cs_storage + attribute \src "ls180.v:1093.5-1093.25" + wire \main_spisdcard_done0 + attribute \src "ls180.v:1104.6-1104.26" + wire \main_spisdcard_done1 + attribute \src "ls180.v:1094.5-1094.23" + wire \main_spisdcard_irq + attribute \src "ls180.v:1092.12-1092.34" + wire width 8 \main_spisdcard_length0 + attribute \src "ls180.v:1101.12-1101.34" + wire width 8 \main_spisdcard_length1 + attribute \src "ls180.v:1098.6-1098.29" + wire \main_spisdcard_loopback + attribute \src "ls180.v:1115.5-1115.31" + wire \main_spisdcard_loopback_re + attribute \src "ls180.v:1114.5-1114.36" + wire \main_spisdcard_loopback_storage + attribute \src "ls180.v:1096.11-1096.30" + wire width 8 \main_spisdcard_miso + attribute \src "ls180.v:1126.11-1126.35" + wire width 8 \main_spisdcard_miso_data + attribute \src "ls180.v:1120.5-1120.30" + wire \main_spisdcard_miso_latch + attribute \src "ls180.v:1109.12-1109.38" + wire width 8 \main_spisdcard_miso_status + attribute \src "ls180.v:1110.6-1110.28" + wire \main_spisdcard_miso_we + attribute \src "ls180.v:1095.12-1095.31" + wire width 8 \main_spisdcard_mosi + attribute \src "ls180.v:1124.11-1124.35" + wire width 8 \main_spisdcard_mosi_data + attribute \src "ls180.v:1119.5-1119.30" + wire \main_spisdcard_mosi_latch + attribute \src "ls180.v:1108.5-1108.27" + wire \main_spisdcard_mosi_re + attribute \src "ls180.v:1125.11-1125.34" + wire width 3 \main_spisdcard_mosi_sel + attribute \src "ls180.v:1107.11-1107.38" + wire width 8 \main_spisdcard_mosi_storage + attribute \src "ls180.v:1111.6-1111.24" + wire \main_spisdcard_sel + attribute \src "ls180.v:1091.6-1091.27" + wire \main_spisdcard_start0 + attribute \src "ls180.v:1100.5-1100.26" + wire \main_spisdcard_start1 + attribute \src "ls180.v:1105.6-1105.34" + wire \main_spisdcard_status_status + attribute \src "ls180.v:1106.6-1106.30" + wire \main_spisdcard_status_we + attribute \src "ls180.v:946.12-946.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:945.6-945.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:948.11-948.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:947.6-947.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:950.5-950.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:942.12-942.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:941.6-941.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:944.11-944.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:943.6-943.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:949.11-949.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:930.6-930.19" + wire \main_uart_irq + attribute \src "ls180.v:916.12-916.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:906.12-906.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:899.5-899.21" + wire \main_uart_phy_re + attribute \src "ls180.v:917.6-917.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:920.11-920.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:921.5-921.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:918.5-918.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:919.11-919.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:902.6-902.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:903.6-903.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:904.12-904.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:901.5-901.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:900.6-900.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:912.5-912.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:913.5-913.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:914.11-914.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:911.6-911.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:910.5-910.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:898.12-898.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:908.11-908.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:909.5-909.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:907.11-907.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:915.5-915.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:905.5-905.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:1039.5-1039.20" + wire \main_uart_reset + attribute \src "ls180.v:939.5-939.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:1023.11-1023.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:1028.6-1028.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:1034.6-1034.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:1035.6-1035.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:1033.12-1033.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:1037.6-1037.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:1038.6-1038.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:1036.12-1036.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:1020.11-1020.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:1032.12-1032.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:1022.11-1022.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:1029.12-1029.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:1030.12-1030.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:1031.6-1031.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:1012.6-1012.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:1013.5-1013.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:1021.5-1021.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:1004.6-1004.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:1005.6-1005.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:1006.12-1006.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:1003.6-1003.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:1002.6-1002.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:1009.6-1009.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:1010.6-1010.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:1011.12-1011.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:1008.6-1008.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:1007.6-1007.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:1018.12-1018.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:1019.12-1019.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:1016.6-1016.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:1017.6-1017.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:1014.6-1014.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:1015.6-1015.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:1024.11-1024.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:1025.12-1025.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:1027.12-1027.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:1026.6-1026.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:940.5-940.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:937.5-937.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:936.6-936.25" + wire \main_uart_rx_status + attribute \src "ls180.v:938.6-938.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:928.6-928.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:929.6-929.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:953.6-953.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:954.6-954.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:923.12-923.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:922.6-922.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:925.12-925.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:924.6-924.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:934.5-934.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:986.11-986.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:991.6-991.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:997.6-997.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:998.6-998.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:996.12-996.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:1000.6-1000.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:1001.6-1001.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:999.12-999.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:983.11-983.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:995.12-995.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:985.11-985.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:992.12-992.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:993.12-993.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:994.6-994.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:975.6-975.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:976.5-976.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:984.5-984.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:967.5-967.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:968.5-968.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:969.12-969.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:966.6-966.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:965.6-965.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:972.6-972.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:973.6-973.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:974.12-974.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:971.6-971.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:970.6-970.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:981.12-981.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:982.12-982.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:979.6-979.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:980.6-980.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:977.6-977.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:978.6-978.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:987.11-987.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:988.12-988.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:990.12-990.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:989.6-989.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:935.5-935.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:932.5-932.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:931.6-931.25" + wire \main_uart_tx_status + attribute \src "ls180.v:933.6-933.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:951.6-951.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:952.6-952.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:926.6-926.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:927.6-927.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:957.6-957.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:958.6-958.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:959.12-959.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:956.6-956.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:955.6-955.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:962.6-962.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:963.6-963.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:964.12-964.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:961.6-961.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:960.6-960.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:864.5-864.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:858.12-858.29" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:862.5-862.22" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:860.13-860.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:859.12-859.31" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:861.11-861.28" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:863.5-863.22" + wire \main_wb_sdram_stb + attribute \src "ls180.v:865.5-865.21" + wire \main_wb_sdram_we + attribute \src "ls180.v:894.5-894.24" + wire \main_wdata_consumed + attribute \src "ls180.v:10223.11-10223.17" + wire width 4 \memadr + attribute \src "ls180.v:10251.11-10251.19" + wire width 4 \memadr_1 + attribute \src "ls180.v:10279.12-10279.18" + wire width 25 \memdat + attribute \src "ls180.v:10293.12-10293.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10307.12-10307.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10321.12-10321.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10335.11-10335.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10336.11-10336.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10352.11-10352.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10353.11-10353.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10369.11-10369.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10383.11-10383.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:52.20-52.22" + wire width 24 input 48 \nc + attribute \src "ls180.v:296.6-296.13" + wire \por_clk + attribute \src "ls180.v:5.19-5.22" + wire width 2 output 1 \pwm + attribute \src "ls180.v:171.12-171.17" + wire width 2 \pwm_1 + attribute \src "ls180.v:20.13-20.23" + wire output 16 \sdcard_clk + attribute \src "ls180.v:21.14-21.26" + wire output 17 \sdcard_cmd_i + attribute \src "ls180.v:22.13-22.25" + wire output 18 \sdcard_cmd_o + attribute \src "ls180.v:23.13-23.26" + wire output 19 \sdcard_cmd_oe + attribute \src "ls180.v:24.20-24.33" + wire width 4 output 20 \sdcard_data_i + attribute \src "ls180.v:25.19-25.32" + wire width 4 output 21 \sdcard_data_o + attribute \src "ls180.v:26.13-26.27" + wire output 22 \sdcard_data_oe + attribute \src "ls180.v:8.20-8.27" + wire width 13 output 4 \sdram_a + attribute \src "ls180.v:17.19-17.27" + wire width 2 output 13 \sdram_ba + attribute \src "ls180.v:14.13-14.24" + wire output 10 \sdram_cas_n + attribute \src "ls180.v:16.13-16.22" + wire output 12 \sdram_cke + attribute \src "ls180.v:19.13-19.24" + wire output 15 \sdram_clock + attribute \src "ls180.v:183.6-183.19" + wire \sdram_clock_1 + attribute \src "ls180.v:15.13-15.23" + wire output 11 \sdram_cs_n + attribute \src "ls180.v:18.19-18.27" + wire width 2 output 14 \sdram_dm + attribute \src "ls180.v:9.21-9.31" + wire width 16 output 5 \sdram_dq_i + attribute \src "ls180.v:10.20-10.30" + wire width 16 output 6 \sdram_dq_o + attribute \src "ls180.v:11.13-11.24" + wire output 7 \sdram_dq_oe + attribute \src "ls180.v:13.13-13.24" + wire output 9 \sdram_ras_n + attribute \src "ls180.v:12.13-12.23" + wire output 8 \sdram_we_n + attribute \src "ls180.v:2718.6-2718.15" + wire \sdrio_clk + attribute \src "ls180.v:2719.6-2719.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2728.6-2728.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2729.6-2729.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2730.6-2730.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2731.6-2731.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2732.6-2732.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2733.6-2733.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2734.6-2734.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2735.6-2735.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2736.6-2736.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2737.6-2737.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2720.6-2720.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2738.6-2738.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2739.6-2739.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2740.6-2740.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2741.6-2741.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2742.6-2742.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2743.6-2743.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2744.6-2744.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2745.6-2745.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2746.6-2746.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2747.6-2747.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2721.6-2721.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2748.6-2748.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2749.6-2749.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2750.6-2750.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2751.6-2751.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2752.6-2752.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2753.6-2753.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2754.6-2754.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2755.6-2755.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2756.6-2756.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2757.6-2757.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2722.6-2722.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2758.6-2758.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2759.6-2759.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2760.6-2760.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2761.6-2761.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2762.6-2762.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2763.6-2763.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2764.6-2764.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2765.6-2765.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2766.6-2766.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2767.6-2767.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2723.6-2723.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2768.6-2768.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2769.6-2769.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2770.6-2770.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2771.6-2771.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2772.6-2772.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2773.6-2773.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2808.6-2808.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2809.6-2809.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2810.6-2810.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2811.6-2811.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2724.6-2724.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2812.6-2812.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2813.6-2813.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2814.6-2814.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2815.6-2815.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2816.6-2816.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2817.6-2817.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2818.6-2818.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2819.6-2819.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2820.6-2820.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2725.6-2725.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2726.6-2726.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2727.6-2727.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:39.13-39.26" + wire output 35 \spimaster_clk + attribute \src "ls180.v:41.13-41.27" + wire output 37 \spimaster_cs_n + attribute \src "ls180.v:42.13-42.27" + wire input 38 \spimaster_miso + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spimaster_mosi + attribute \src "ls180.v:27.13-27.26" + wire output 23 \spisdcard_clk + attribute \src "ls180.v:29.13-29.27" + wire output 25 \spisdcard_cs_n + attribute \src "ls180.v:30.13-30.27" + wire input 26 \spisdcard_miso + attribute \src "ls180.v:28.13-28.27" + wire output 24 \spisdcard_mosi + attribute \src "ls180.v:43.13-43.20" + wire input 39 \sys_clk + attribute \src "ls180.v:294.6-294.15" + wire \sys_clk_1 + attribute \src "ls180.v:45.19-45.31" + wire width 2 input 41 \sys_clksel_i + attribute \src "ls180.v:46.14-46.26" + wire output 42 \sys_pll_18_o + attribute \src "ls180.v:47.14-47.27" + wire output 43 \sys_pll_lck_o + attribute \src "ls180.v:44.13-44.20" + wire input 40 \sys_rst + attribute \src "ls180.v:295.6-295.15" + wire \sys_rst_1 + attribute \src "ls180.v:7.13-7.20" + wire input 3 \uart_rx + attribute \src "ls180.v:6.13-6.20" + wire output 2 \uart_tx + attribute \src "ls180.v:10222.12-10222.15" + memory width 64 size 16 \mem + attribute \src "ls180.v:10250.12-10250.17" + memory width 64 size 16 \mem_1 + attribute \src "ls180.v:10278.12-10278.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10292.12-10292.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10306.12-10306.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10320.12-10320.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10334.11-10334.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10351.11-10351.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10368.11-10368.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10382.11-10382.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2890.56-2890.86" + cell $add $add$ls180.v:2890$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2890$34_Y + end + attribute \src "ls180.v:2950.56-2950.86" + cell $add $add$ls180.v:2950$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2950$45_Y + end + attribute \src "ls180.v:3010.59-3010.92" + cell $add $add$ls180.v:3010$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_counter + connect \B 1'1 + connect \Y $add$ls180.v:3010$56_Y + end + attribute \src "ls180.v:4161.54-4161.83" + cell $add $add$ls180.v:4161$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4161$586_Y + end + attribute \src "ls180.v:4261.36-4261.89" + cell $add $add$ls180.v:4261$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4261$632_Y + end + attribute \src "ls180.v:4291.36-4291.89" + cell $add $add$ls180.v:4291$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4291$643_Y + end + attribute \src "ls180.v:4357.54-4357.83" + cell $add $add$ls180.v:4357$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster27_count + connect \B 1'1 + connect \Y $add$ls180.v:4357$658_Y + end + attribute \src "ls180.v:4416.52-4416.79" + cell $add $add$ls180.v:4416$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_count + connect \B 1'1 + connect \Y $add$ls180.v:4416$666_Y + end + attribute \src "ls180.v:4520.58-4520.86" + cell $add $add$ls180.v:4520$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4520$694_Y + end + attribute \src "ls180.v:4577.58-4577.86" + cell $add $add$ls180.v:4577$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4577$697_Y + end + attribute \src "ls180.v:4594.58-4594.86" + cell $add $add$ls180.v:4594$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4594$699_Y + end + attribute \src "ls180.v:4687.59-4687.87" + cell $add $add$ls180.v:4687$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4687$716_Y + end + attribute \src "ls180.v:4712.59-4712.87" + cell $add $add$ls180.v:4712$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4712$719_Y + end + attribute \src "ls180.v:4834.53-4834.82" + cell $add $add$ls180.v:4834$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4834$736_Y + end + attribute \src "ls180.v:4945.65-4945.114" + cell $add $add$ls180.v:4945$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:4945$750_Y + end + attribute \src "ls180.v:4950.62-4950.91" + cell $add $add$ls180.v:4950$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4950$753_Y + end + attribute \src "ls180.v:4976.61-4976.90" + cell $add $add$ls180.v:4976$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4976$756_Y + end + attribute \src "ls180.v:5180.80-5180.117" + cell $add $add$ls180.v:5180$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:5180$941_Y + end + attribute \src "ls180.v:5374.54-5374.82" + cell $add $add$ls180.v:5374$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5374$1016_Y + end + attribute \src "ls180.v:5426.55-5426.84" + cell $add $add$ls180.v:5426$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5426$1026_Y + end + attribute \src "ls180.v:5452.57-5452.86" + cell $add $add$ls180.v:5452$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5452$1034_Y + end + attribute \src "ls180.v:5573.51-5573.134" + cell $add $add$ls180.v:5573$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5573$1050_Y + end + attribute \src "ls180.v:5576.77-5576.125" + cell $add $add$ls180.v:5576$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5576$1052_Y + end + attribute \src "ls180.v:5669.50-5669.105" + cell $add $add$ls180.v:5669$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5669$1061_Y + end + attribute \src "ls180.v:5671.77-5671.111" + cell $add $add$ls180.v:5671$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5671$1062_Y + end + attribute \src "ls180.v:7651.36-7651.70" + cell $add $add$ls180.v:7651$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7651$2487_Y + end + attribute \src "ls180.v:7740.37-7740.72" + cell $add $add$ls180.v:7740$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7740$2511_Y + end + attribute \src "ls180.v:7757.60-7757.119" + cell $add $add$ls180.v:7757$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7757$2515_Y + end + attribute \src "ls180.v:7760.60-7760.119" + cell $add $add$ls180.v:7760$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7760$2516_Y + end + attribute \src "ls180.v:7764.59-7764.116" + cell $add $add$ls180.v:7764$2521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7764$2521_Y + end + attribute \src "ls180.v:7803.60-7803.119" + cell $add $add$ls180.v:7803$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7803$2531_Y + end + attribute \src "ls180.v:7806.60-7806.119" + cell $add $add$ls180.v:7806$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7806$2532_Y + end + attribute \src "ls180.v:7810.59-7810.116" + cell $add $add$ls180.v:7810$2537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7810$2537_Y + end + attribute \src "ls180.v:7849.60-7849.119" + cell $add $add$ls180.v:7849$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7849$2547_Y + end + attribute \src "ls180.v:7852.60-7852.119" + cell $add $add$ls180.v:7852$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7852$2548_Y + end + attribute \src "ls180.v:7856.59-7856.116" + cell $add $add$ls180.v:7856$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7856$2553_Y + end + attribute \src "ls180.v:7895.60-7895.119" + cell $add $add$ls180.v:7895$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7895$2563_Y + end + attribute \src "ls180.v:7898.60-7898.119" + cell $add $add$ls180.v:7898$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7898$2564_Y + end + attribute \src "ls180.v:7902.59-7902.116" + cell $add $add$ls180.v:7902$2569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7902$2569_Y + end + attribute \src "ls180.v:8132.34-8132.66" + cell $add $add$ls180.v:8132$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8132$2623_Y + end + attribute \src "ls180.v:8148.73-8148.131" + cell $add $add$ls180.v:8148$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8148$2626_Y + end + attribute \src "ls180.v:8161.34-8161.66" + cell $add $add$ls180.v:8161$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8161$2630_Y + end + attribute \src "ls180.v:8180.73-8180.131" + cell $add $add$ls180.v:8180$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8180$2633_Y + end + attribute \src "ls180.v:8206.33-8206.65" + cell $add $add$ls180.v:8206$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8206$2641_Y + end + attribute \src "ls180.v:8209.33-8209.65" + cell $add $add$ls180.v:8209$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8209$2642_Y + end + attribute \src "ls180.v:8213.33-8213.64" + cell $add $add$ls180.v:8213$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8213$2647_Y + end + attribute \src "ls180.v:8228.33-8228.65" + cell $add $add$ls180.v:8228$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8228$2652_Y + end + attribute \src "ls180.v:8231.33-8231.65" + cell $add $add$ls180.v:8231$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8231$2653_Y + end + attribute \src "ls180.v:8235.33-8235.64" + cell $add $add$ls180.v:8235$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8235$2658_Y + end + attribute \src "ls180.v:8256.35-8256.70" + cell $add $add$ls180.v:8256$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster30_clk_divider + connect \B 1'1 + connect \Y $add$ls180.v:8256$2660_Y + end + attribute \src "ls180.v:8291.34-8291.68" + cell $add $add$ls180.v:8291$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8291$2665_Y + end + attribute \src "ls180.v:8327.25-8327.49" + cell $add $add$ls180.v:8327$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8327$2670_Y + end + attribute \src "ls180.v:8341.25-8341.49" + cell $add $add$ls180.v:8341$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8341$2674_Y + end + attribute \src "ls180.v:8355.31-8355.61" + cell $add $add$ls180.v:8355$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8355$2679_Y + end + attribute \src "ls180.v:8378.45-8378.88" + cell $add $add$ls180.v:8378$2683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8378$2683_Y + end + attribute \src "ls180.v:8424.71-8424.114" + cell $add $add$ls180.v:8424$2689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8424$2689_Y + end + attribute \src "ls180.v:8459.46-8459.90" + cell $add $add$ls180.v:8459$2695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8459$2695_Y + end + attribute \src "ls180.v:8505.72-8505.116" + cell $add $add$ls180.v:8505$2701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8505$2701_Y + end + attribute \src "ls180.v:8538.47-8538.92" + cell $add $add$ls180.v:8538$2707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8538$2707_Y + end + attribute \src "ls180.v:8566.73-8566.118" + cell $add $add$ls180.v:8566$2713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8566$2713_Y + end + attribute \src "ls180.v:8678.39-8678.75" + cell $add $add$ls180.v:8678$2726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8678$2726_Y + end + attribute \src "ls180.v:8739.37-8739.73" + cell $add $add$ls180.v:8739$2730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8739$2730_Y + end + attribute \src "ls180.v:8742.37-8742.73" + cell $add $add$ls180.v:8742$2731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8742$2731_Y + end + attribute \src "ls180.v:8746.36-8746.70" + cell $add $add$ls180.v:8746$2736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8746$2736_Y + end + attribute \src "ls180.v:8761.41-8761.80" + cell $add $add$ls180.v:8761$2740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8761$2740_Y + end + attribute \src "ls180.v:8807.67-8807.106" + cell $add $add$ls180.v:8807$2746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8807$2746_Y + end + attribute \src "ls180.v:8833.39-8833.76" + cell $add $add$ls180.v:8833$2748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8833$2748_Y + end + attribute \src "ls180.v:8837.37-8837.73" + cell $add $add$ls180.v:8837$2752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8837$2752_Y + end + attribute \src "ls180.v:8840.37-8840.73" + cell $add $add$ls180.v:8840$2753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8840$2753_Y + end + attribute \src "ls180.v:8844.36-8844.70" + cell $add $add$ls180.v:8844$2758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8844$2758_Y + end + attribute \src "ls180.v:2884.9-2884.90" + cell $and $and$ls180.v:2884$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2884$29_Y + end + attribute \src "ls180.v:2902.9-2902.90" + cell $and $and$ls180.v:2902$36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2902$36_Y + end + attribute \src "ls180.v:2944.9-2944.90" + cell $and $and$ls180.v:2944$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2944$40_Y + end + attribute \src "ls180.v:2962.9-2962.90" + cell $and $and$ls180.v:2962$47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2962$47_Y + end + attribute \src "ls180.v:3004.9-3004.96" + cell $and $and$ls180.v:3004$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3004$51_Y + end + attribute \src "ls180.v:3022.9-3022.96" + cell $and $and$ls180.v:3022$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3022$58_Y + end + attribute \src "ls180.v:3032.31-3032.90" + cell $and $and$ls180.v:3032$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3032$60_Y + end + attribute \src "ls180.v:3032.30-3032.121" + cell $and $and$ls180.v:3032$61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3032$60_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3032$61_Y + end + attribute \src "ls180.v:3032.29-3032.156" + cell $and $and$ls180.v:3032$62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3032$61_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:3032$62_Y + end + attribute \src "ls180.v:3033.31-3033.90" + cell $and $and$ls180.v:3033$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3033$63_Y + end + attribute \src "ls180.v:3033.30-3033.121" + cell $and $and$ls180.v:3033$64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3033$63_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3033$64_Y + end + attribute \src "ls180.v:3033.29-3033.156" + cell $and $and$ls180.v:3033$65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3033$64_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:3033$65_Y + end + attribute \src "ls180.v:3034.31-3034.90" + cell $and $and$ls180.v:3034$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3034$66_Y + end + attribute \src "ls180.v:3034.30-3034.121" + cell $and $and$ls180.v:3034$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3034$66_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3034$67_Y + end + attribute \src "ls180.v:3034.29-3034.156" + cell $and $and$ls180.v:3034$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3034$67_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:3034$68_Y + end + attribute \src "ls180.v:3035.31-3035.90" + cell $and $and$ls180.v:3035$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3035$69_Y + end + attribute \src "ls180.v:3035.30-3035.121" + cell $and $and$ls180.v:3035$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3035$69_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3035$70_Y + end + attribute \src "ls180.v:3035.29-3035.156" + cell $and $and$ls180.v:3035$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3035$70_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:3035$71_Y + end + attribute \src "ls180.v:3036.31-3036.90" + cell $and $and$ls180.v:3036$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3036$72_Y + end + attribute \src "ls180.v:3036.30-3036.121" + cell $and $and$ls180.v:3036$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3036$72_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3036$73_Y + end + attribute \src "ls180.v:3036.29-3036.156" + cell $and $and$ls180.v:3036$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3036$73_Y + connect \B \main_libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:3036$74_Y + end + attribute \src "ls180.v:3037.31-3037.90" + cell $and $and$ls180.v:3037$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3037$75_Y + end + attribute \src "ls180.v:3037.30-3037.121" + cell $and $and$ls180.v:3037$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3037$75_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3037$76_Y + end + attribute \src "ls180.v:3037.29-3037.156" + cell $and $and$ls180.v:3037$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3037$76_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:3037$77_Y + end + attribute \src "ls180.v:3038.31-3038.90" + cell $and $and$ls180.v:3038$78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3038$78_Y + end + attribute \src "ls180.v:3038.30-3038.121" + cell $and $and$ls180.v:3038$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3038$78_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3038$79_Y + end + attribute \src "ls180.v:3038.29-3038.156" + cell $and $and$ls180.v:3038$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3038$79_Y + connect \B \main_libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:3038$80_Y + end + attribute \src "ls180.v:3039.31-3039.90" + cell $and $and$ls180.v:3039$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3039$81_Y + end + attribute \src "ls180.v:3039.30-3039.121" + cell $and $and$ls180.v:3039$82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3039$81_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3039$82_Y + end + attribute \src "ls180.v:3039.29-3039.156" + cell $and $and$ls180.v:3039$83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3039$82_Y + connect \B \main_libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:3039$83_Y + end + attribute \src "ls180.v:3048.7-3048.89" + cell $and $and$ls180.v:3048$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:3048$86_Y + end + attribute \src "ls180.v:3053.32-3053.111" + cell $and $and$ls180.v:3053$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:3053$87_Y + end + attribute \src "ls180.v:3057.23-3057.74" + cell $and $and$ls180.v:3057$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3057$89_Y + end + attribute \src "ls180.v:3057.22-3057.101" + cell $and $and$ls180.v:3057$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3057$89_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3057$90_Y + end + attribute \src "ls180.v:3057.21-3057.132" + cell $and $and$ls180.v:3057$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3057$90_Y + connect \B \main_ram_bus_ram_bus_sel [0] + connect \Y $and$ls180.v:3057$91_Y + end + attribute \src "ls180.v:3058.23-3058.74" + cell $and $and$ls180.v:3058$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3058$92_Y + end + attribute \src "ls180.v:3058.22-3058.101" + cell $and $and$ls180.v:3058$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3058$92_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3058$93_Y + end + attribute \src "ls180.v:3058.21-3058.132" + cell $and $and$ls180.v:3058$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3058$93_Y + connect \B \main_ram_bus_ram_bus_sel [1] + connect \Y $and$ls180.v:3058$94_Y + end + attribute \src "ls180.v:3059.23-3059.74" + cell $and $and$ls180.v:3059$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3059$95_Y + end + attribute \src "ls180.v:3059.22-3059.101" + cell $and $and$ls180.v:3059$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3059$95_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3059$96_Y + end + attribute \src "ls180.v:3059.21-3059.132" + cell $and $and$ls180.v:3059$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3059$96_Y + connect \B \main_ram_bus_ram_bus_sel [2] + connect \Y $and$ls180.v:3059$97_Y + end + attribute \src "ls180.v:3060.21-3060.132" + cell $and $and$ls180.v:3060$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3060$99_Y + connect \B \main_ram_bus_ram_bus_sel [3] + connect \Y $and$ls180.v:3060$100_Y + end + attribute \src "ls180.v:3060.23-3060.74" + cell $and $and$ls180.v:3060$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3060$98_Y + end + attribute \src "ls180.v:3060.22-3060.101" + cell $and $and$ls180.v:3060$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3060$98_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3060$99_Y + end + attribute \src "ls180.v:3061.23-3061.74" + cell $and $and$ls180.v:3061$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3061$101_Y + end + attribute \src "ls180.v:3061.22-3061.101" + cell $and $and$ls180.v:3061$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3061$101_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3061$102_Y + end + attribute \src "ls180.v:3061.21-3061.132" + cell $and $and$ls180.v:3061$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3061$102_Y + connect \B \main_ram_bus_ram_bus_sel [4] + connect \Y $and$ls180.v:3061$103_Y + end + attribute \src "ls180.v:3062.23-3062.74" + cell $and $and$ls180.v:3062$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3062$104_Y + end + attribute \src "ls180.v:3062.22-3062.101" + cell $and $and$ls180.v:3062$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3062$104_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3062$105_Y + end + attribute \src "ls180.v:3062.21-3062.132" + cell $and $and$ls180.v:3062$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3062$105_Y + connect \B \main_ram_bus_ram_bus_sel [5] + connect \Y $and$ls180.v:3062$106_Y + end + attribute \src "ls180.v:3063.23-3063.74" + cell $and $and$ls180.v:3063$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3063$107_Y + end + attribute \src "ls180.v:3063.22-3063.101" + cell $and $and$ls180.v:3063$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3063$107_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3063$108_Y + end + attribute \src "ls180.v:3063.21-3063.132" + cell $and $and$ls180.v:3063$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3063$108_Y + connect \B \main_ram_bus_ram_bus_sel [6] + connect \Y $and$ls180.v:3063$109_Y + end + attribute \src "ls180.v:3064.23-3064.74" + cell $and $and$ls180.v:3064$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3064$110_Y + end + attribute \src "ls180.v:3064.22-3064.101" + cell $and $and$ls180.v:3064$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3064$110_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3064$111_Y + end + attribute \src "ls180.v:3064.21-3064.132" + cell $and $and$ls180.v:3064$112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3064$111_Y + connect \B \main_ram_bus_ram_bus_sel [7] + connect \Y $and$ls180.v:3064$112_Y + end + attribute \src "ls180.v:3181.40-3181.99" + cell $and $and$ls180.v:3181$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3181$119_Y + end + attribute \src "ls180.v:3182.40-3182.99" + cell $and $and$ls180.v:3182$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3182$120_Y + end + attribute \src "ls180.v:3220.38-3220.103" + cell $and $and$ls180.v:3220$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3220$125_Y + connect \Y $and$ls180.v:3220$126_Y + end + attribute \src "ls180.v:3274.50-3274.119" + cell $and $and$ls180.v:3274$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3274$134_Y + end + attribute \src "ls180.v:3274.49-3274.167" + cell $and $and$ls180.v:3274$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3274$134_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3274$135_Y + end + attribute \src "ls180.v:3275.49-3275.118" + cell $and $and$ls180.v:3275$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3275$136_Y + end + attribute \src "ls180.v:3275.48-3275.154" + cell $and $and$ls180.v:3275$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3275$136_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3275$137_Y + end + attribute \src "ls180.v:3276.50-3276.119" + cell $and $and$ls180.v:3276$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3276$138_Y + end + attribute \src "ls180.v:3276.49-3276.155" + cell $and $and$ls180.v:3276$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3276$138_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3276$139_Y + end + attribute \src "ls180.v:3279.7-3279.114" + cell $and $and$ls180.v:3279$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3279$141_Y + end + attribute \src "ls180.v:3308.66-3308.246" + cell $and $and$ls180.v:3308$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3308$146_Y + connect \Y $and$ls180.v:3308$147_Y + end + attribute \src "ls180.v:3309.64-3309.187" + cell $and $and$ls180.v:3309$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3309$148_Y + end + attribute \src "ls180.v:3333.9-3333.86" + cell $and $and$ls180.v:3333$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3333$154_Y + end + attribute \src "ls180.v:3345.9-3345.86" + cell $and $and$ls180.v:3345$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3345$155_Y + end + attribute \src "ls180.v:3395.13-3395.87" + cell $and $and$ls180.v:3395$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3395$157_Y + end + attribute \src "ls180.v:3431.50-3431.119" + cell $and $and$ls180.v:3431$164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3431$164_Y + end + attribute \src "ls180.v:3431.49-3431.167" + cell $and $and$ls180.v:3431$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3431$164_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3431$165_Y + end + attribute \src "ls180.v:3432.49-3432.118" + cell $and $and$ls180.v:3432$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3432$166_Y + end + attribute \src "ls180.v:3432.48-3432.154" + cell $and $and$ls180.v:3432$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3432$166_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3432$167_Y + end + attribute \src "ls180.v:3433.50-3433.119" + cell $and $and$ls180.v:3433$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3433$168_Y + end + attribute \src "ls180.v:3433.49-3433.155" + cell $and $and$ls180.v:3433$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3433$168_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3433$169_Y + end + attribute \src "ls180.v:3436.7-3436.114" + cell $and $and$ls180.v:3436$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3436$171_Y + end + attribute \src "ls180.v:3465.66-3465.246" + cell $and $and$ls180.v:3465$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3465$176_Y + connect \Y $and$ls180.v:3465$177_Y + end + attribute \src "ls180.v:3466.64-3466.187" + cell $and $and$ls180.v:3466$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3466$178_Y + end + attribute \src "ls180.v:3490.9-3490.86" + cell $and $and$ls180.v:3490$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3490$184_Y + end + attribute \src "ls180.v:3502.9-3502.86" + cell $and $and$ls180.v:3502$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3502$185_Y + end + attribute \src "ls180.v:3552.13-3552.87" + cell $and $and$ls180.v:3552$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3552$187_Y + end + attribute \src "ls180.v:3588.50-3588.119" + cell $and $and$ls180.v:3588$194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3588$194_Y + end + attribute \src "ls180.v:3588.49-3588.167" + cell $and $and$ls180.v:3588$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3588$194_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3588$195_Y + end + attribute \src "ls180.v:3589.49-3589.118" + cell $and $and$ls180.v:3589$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3589$196_Y + end + attribute \src "ls180.v:3589.48-3589.154" + cell $and $and$ls180.v:3589$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3589$196_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3589$197_Y + end + attribute \src "ls180.v:3590.50-3590.119" + cell $and $and$ls180.v:3590$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3590$198_Y + end + attribute \src "ls180.v:3590.49-3590.155" + cell $and $and$ls180.v:3590$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3590$198_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3590$199_Y + end + attribute \src "ls180.v:3593.7-3593.114" + cell $and $and$ls180.v:3593$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3593$201_Y + end + attribute \src "ls180.v:3622.66-3622.246" + cell $and $and$ls180.v:3622$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3622$206_Y + connect \Y $and$ls180.v:3622$207_Y + end + attribute \src "ls180.v:3623.64-3623.187" + cell $and $and$ls180.v:3623$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3623$208_Y + end + attribute \src "ls180.v:3647.9-3647.86" + cell $and $and$ls180.v:3647$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3647$214_Y + end + attribute \src "ls180.v:3659.9-3659.86" + cell $and $and$ls180.v:3659$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3659$215_Y + end + attribute \src "ls180.v:3709.13-3709.87" + cell $and $and$ls180.v:3709$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3709$217_Y + end + attribute \src "ls180.v:3745.50-3745.119" + cell $and $and$ls180.v:3745$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3745$224_Y + end + attribute \src "ls180.v:3745.49-3745.167" + cell $and $and$ls180.v:3745$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3745$224_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3745$225_Y + end + attribute \src "ls180.v:3746.49-3746.118" + cell $and $and$ls180.v:3746$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3746$226_Y + end + attribute \src "ls180.v:3746.48-3746.154" + cell $and $and$ls180.v:3746$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3746$226_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3746$227_Y + end + attribute \src "ls180.v:3747.50-3747.119" + cell $and $and$ls180.v:3747$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3747$228_Y + end + attribute \src "ls180.v:3747.49-3747.155" + cell $and $and$ls180.v:3747$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3747$228_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3747$229_Y + end + attribute \src "ls180.v:3750.7-3750.114" + cell $and $and$ls180.v:3750$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3750$231_Y + end + attribute \src "ls180.v:3779.66-3779.246" + cell $and $and$ls180.v:3779$237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3779$236_Y + connect \Y $and$ls180.v:3779$237_Y + end + attribute \src "ls180.v:3780.64-3780.187" + cell $and $and$ls180.v:3780$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3780$238_Y + end + attribute \src "ls180.v:3804.9-3804.86" + cell $and $and$ls180.v:3804$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3804$244_Y + end + attribute \src "ls180.v:3816.9-3816.86" + cell $and $and$ls180.v:3816$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3816$245_Y + end + attribute \src "ls180.v:3866.13-3866.87" + cell $and $and$ls180.v:3866$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3866$247_Y + end + attribute \src "ls180.v:3881.37-3881.102" + cell $and $and$ls180.v:3881$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3881$248_Y + end + attribute \src "ls180.v:3881.108-3881.188" + cell $and $and$ls180.v:3881$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3881$249_Y + connect \Y $and$ls180.v:3881$250_Y + end + attribute \src "ls180.v:3881.107-3881.231" + cell $and $and$ls180.v:3881$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3881$250_Y + connect \B $not$ls180.v:3881$251_Y + connect \Y $and$ls180.v:3881$252_Y + end + attribute \src "ls180.v:3881.36-3881.232" + cell $and $and$ls180.v:3881$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3881$248_Y + connect \B $and$ls180.v:3881$252_Y + connect \Y $and$ls180.v:3881$253_Y + end + attribute \src "ls180.v:3882.37-3882.102" + cell $and $and$ls180.v:3882$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3882$254_Y + end + attribute \src "ls180.v:3882.108-3882.188" + cell $and $and$ls180.v:3882$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3882$255_Y + connect \Y $and$ls180.v:3882$256_Y + end + attribute \src "ls180.v:3882.107-3882.231" + cell $and $and$ls180.v:3882$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3882$256_Y + connect \B $not$ls180.v:3882$257_Y + connect \Y $and$ls180.v:3882$258_Y + end + attribute \src "ls180.v:3882.36-3882.232" + cell $and $and$ls180.v:3882$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3882$254_Y + connect \B $and$ls180.v:3882$258_Y + connect \Y $and$ls180.v:3882$259_Y + end + attribute \src "ls180.v:3883.34-3883.85" + cell $and $and$ls180.v:3883$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3883$260_Y + end + attribute \src "ls180.v:3884.37-3884.102" + cell $and $and$ls180.v:3884$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3884$261_Y + end + attribute \src "ls180.v:3884.36-3884.194" + cell $and $and$ls180.v:3884$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3884$261_Y + connect \B $or$ls180.v:3884$262_Y + connect \Y $and$ls180.v:3884$263_Y + end + attribute \src "ls180.v:3886.37-3886.102" + cell $and $and$ls180.v:3886$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3886$264_Y + end + attribute \src "ls180.v:3886.36-3886.148" + cell $and $and$ls180.v:3886$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3886$264_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3886$265_Y + end + attribute \src "ls180.v:3887.40-3887.119" + cell $and $and$ls180.v:3887$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3887$266_Y + end + attribute \src "ls180.v:3887.124-3887.203" + cell $and $and$ls180.v:3887$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3887$267_Y + end + attribute \src "ls180.v:3887.209-3887.288" + cell $and $and$ls180.v:3887$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3887$269_Y + end + attribute \src "ls180.v:3887.294-3887.373" + cell $and $and$ls180.v:3887$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3887$271_Y + end + attribute \src "ls180.v:3888.41-3888.121" + cell $and $and$ls180.v:3888$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3888$273_Y + end + attribute \src "ls180.v:3888.126-3888.206" + cell $and $and$ls180.v:3888$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3888$274_Y + end + attribute \src "ls180.v:3888.212-3888.292" + cell $and $and$ls180.v:3888$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3888$276_Y + end + attribute \src "ls180.v:3888.298-3888.378" + cell $and $and$ls180.v:3888$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3888$278_Y + end + attribute \src "ls180.v:3895.38-3895.111" + cell $and $and$ls180.v:3895$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3895$282_Y + end + attribute \src "ls180.v:3895.37-3895.150" + cell $and $and$ls180.v:3895$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3895$282_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3895$283_Y + end + attribute \src "ls180.v:3895.36-3895.189" + cell $and $and$ls180.v:3895$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3895$283_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3895$284_Y + end + attribute \src "ls180.v:3901.77-3901.153" + cell $and $and$ls180.v:3901$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3901$287_Y + end + attribute \src "ls180.v:3901.162-3901.246" + cell $and $and$ls180.v:3901$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3901$288_Y + connect \Y $and$ls180.v:3901$289_Y + end + attribute \src "ls180.v:3901.161-3901.291" + cell $and $and$ls180.v:3901$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3901$289_Y + connect \B $not$ls180.v:3901$290_Y + connect \Y $and$ls180.v:3901$291_Y + end + attribute \src "ls180.v:3901.76-3901.333" + cell $and $and$ls180.v:3901$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3901$287_Y + connect \B $or$ls180.v:3901$293_Y + connect \Y $and$ls180.v:3901$294_Y + end + attribute \src "ls180.v:3901.338-3901.505" + cell $and $and$ls180.v:3901$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3901$295_Y + connect \B $eq$ls180.v:3901$296_Y + connect \Y $and$ls180.v:3901$297_Y + end + attribute \src "ls180.v:3901.38-3901.507" + cell $and $and$ls180.v:3901$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3901$298_Y + connect \Y $and$ls180.v:3901$299_Y + end + attribute \src "ls180.v:3902.77-3902.153" + cell $and $and$ls180.v:3902$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3902$300_Y + end + attribute \src "ls180.v:3902.162-3902.246" + cell $and $and$ls180.v:3902$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3902$301_Y + connect \Y $and$ls180.v:3902$302_Y + end + attribute \src "ls180.v:3902.161-3902.291" + cell $and $and$ls180.v:3902$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3902$302_Y + connect \B $not$ls180.v:3902$303_Y + connect \Y $and$ls180.v:3902$304_Y + end + attribute \src "ls180.v:3902.76-3902.333" + cell $and $and$ls180.v:3902$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3902$300_Y + connect \B $or$ls180.v:3902$306_Y + connect \Y $and$ls180.v:3902$307_Y + end + attribute \src "ls180.v:3902.338-3902.505" + cell $and $and$ls180.v:3902$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3902$308_Y + connect \B $eq$ls180.v:3902$309_Y + connect \Y $and$ls180.v:3902$310_Y + end + attribute \src "ls180.v:3902.38-3902.507" + cell $and $and$ls180.v:3902$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3902$311_Y + connect \Y $and$ls180.v:3902$312_Y + end + attribute \src "ls180.v:3903.77-3903.153" + cell $and $and$ls180.v:3903$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3903$313_Y + end + attribute \src "ls180.v:3903.162-3903.246" + cell $and $and$ls180.v:3903$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3903$314_Y + connect \Y $and$ls180.v:3903$315_Y + end + attribute \src "ls180.v:3903.161-3903.291" + cell $and $and$ls180.v:3903$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3903$315_Y + connect \B $not$ls180.v:3903$316_Y + connect \Y $and$ls180.v:3903$317_Y + end + attribute \src "ls180.v:3903.76-3903.333" + cell $and $and$ls180.v:3903$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3903$313_Y + connect \B $or$ls180.v:3903$319_Y + connect \Y $and$ls180.v:3903$320_Y + end + attribute \src "ls180.v:3903.338-3903.505" + cell $and $and$ls180.v:3903$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3903$321_Y + connect \B $eq$ls180.v:3903$322_Y + connect \Y $and$ls180.v:3903$323_Y + end + attribute \src "ls180.v:3903.38-3903.507" + cell $and $and$ls180.v:3903$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3903$324_Y + connect \Y $and$ls180.v:3903$325_Y + end + attribute \src "ls180.v:3904.77-3904.153" + cell $and $and$ls180.v:3904$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3904$326_Y + end + attribute \src "ls180.v:3904.162-3904.246" + cell $and $and$ls180.v:3904$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3904$327_Y + connect \Y $and$ls180.v:3904$328_Y + end + attribute \src "ls180.v:3904.161-3904.291" + cell $and $and$ls180.v:3904$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3904$328_Y + connect \B $not$ls180.v:3904$329_Y + connect \Y $and$ls180.v:3904$330_Y + end + attribute \src "ls180.v:3904.76-3904.333" + cell $and $and$ls180.v:3904$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3904$326_Y + connect \B $or$ls180.v:3904$332_Y + connect \Y $and$ls180.v:3904$333_Y + end + attribute \src "ls180.v:3904.338-3904.505" + cell $and $and$ls180.v:3904$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3904$334_Y + connect \B $eq$ls180.v:3904$335_Y + connect \Y $and$ls180.v:3904$336_Y + end + attribute \src "ls180.v:3904.38-3904.507" + cell $and $and$ls180.v:3904$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3904$337_Y + connect \Y $and$ls180.v:3904$338_Y + end + attribute \src "ls180.v:3934.77-3934.153" + cell $and $and$ls180.v:3934$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3934$345_Y + end + attribute \src "ls180.v:3934.162-3934.246" + cell $and $and$ls180.v:3934$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3934$346_Y + connect \Y $and$ls180.v:3934$347_Y + end + attribute \src "ls180.v:3934.161-3934.291" + cell $and $and$ls180.v:3934$349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3934$347_Y + connect \B $not$ls180.v:3934$348_Y + connect \Y $and$ls180.v:3934$349_Y + end + attribute \src "ls180.v:3934.76-3934.333" + cell $and $and$ls180.v:3934$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3934$345_Y + connect \B $or$ls180.v:3934$351_Y + connect \Y $and$ls180.v:3934$352_Y + end + attribute \src "ls180.v:3934.338-3934.505" + cell $and $and$ls180.v:3934$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3934$353_Y + connect \B $eq$ls180.v:3934$354_Y + connect \Y $and$ls180.v:3934$355_Y + end + attribute \src "ls180.v:3934.38-3934.507" + cell $and $and$ls180.v:3934$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3934$356_Y + connect \Y $and$ls180.v:3934$357_Y + end + attribute \src "ls180.v:3935.77-3935.153" + cell $and $and$ls180.v:3935$358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3935$358_Y + end + attribute \src "ls180.v:3935.162-3935.246" + cell $and $and$ls180.v:3935$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3935$359_Y + connect \Y $and$ls180.v:3935$360_Y + end + attribute \src "ls180.v:3935.161-3935.291" + cell $and $and$ls180.v:3935$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3935$360_Y + connect \B $not$ls180.v:3935$361_Y + connect \Y $and$ls180.v:3935$362_Y + end + attribute \src "ls180.v:3935.76-3935.333" + cell $and $and$ls180.v:3935$365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3935$358_Y + connect \B $or$ls180.v:3935$364_Y + connect \Y $and$ls180.v:3935$365_Y + end + attribute \src "ls180.v:3935.338-3935.505" + cell $and $and$ls180.v:3935$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3935$366_Y + connect \B $eq$ls180.v:3935$367_Y + connect \Y $and$ls180.v:3935$368_Y + end + attribute \src "ls180.v:3935.38-3935.507" + cell $and $and$ls180.v:3935$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3935$369_Y + connect \Y $and$ls180.v:3935$370_Y + end + attribute \src "ls180.v:3936.77-3936.153" + cell $and $and$ls180.v:3936$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3936$371_Y + end + attribute \src "ls180.v:3936.162-3936.246" + cell $and $and$ls180.v:3936$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3936$372_Y + connect \Y $and$ls180.v:3936$373_Y + end + attribute \src "ls180.v:3936.161-3936.291" + cell $and $and$ls180.v:3936$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3936$373_Y + connect \B $not$ls180.v:3936$374_Y + connect \Y $and$ls180.v:3936$375_Y + end + attribute \src "ls180.v:3936.76-3936.333" + cell $and $and$ls180.v:3936$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3936$371_Y + connect \B $or$ls180.v:3936$377_Y + connect \Y $and$ls180.v:3936$378_Y + end + attribute \src "ls180.v:3936.338-3936.505" + cell $and $and$ls180.v:3936$381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3936$379_Y + connect \B $eq$ls180.v:3936$380_Y + connect \Y $and$ls180.v:3936$381_Y + end + attribute \src "ls180.v:3936.38-3936.507" + cell $and $and$ls180.v:3936$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3936$382_Y + connect \Y $and$ls180.v:3936$383_Y + end + attribute \src "ls180.v:3937.77-3937.153" + cell $and $and$ls180.v:3937$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3937$384_Y + end + attribute \src "ls180.v:3937.162-3937.246" + cell $and $and$ls180.v:3937$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3937$385_Y + connect \Y $and$ls180.v:3937$386_Y + end + attribute \src "ls180.v:3937.161-3937.291" + cell $and $and$ls180.v:3937$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3937$386_Y + connect \B $not$ls180.v:3937$387_Y + connect \Y $and$ls180.v:3937$388_Y + end + attribute \src "ls180.v:3937.76-3937.333" + cell $and $and$ls180.v:3937$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3937$384_Y + connect \B $or$ls180.v:3937$390_Y + connect \Y $and$ls180.v:3937$391_Y + end + attribute \src "ls180.v:3937.338-3937.505" + cell $and $and$ls180.v:3937$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3937$392_Y + connect \B $eq$ls180.v:3937$393_Y + connect \Y $and$ls180.v:3937$394_Y + end + attribute \src "ls180.v:3937.38-3937.507" + cell $and $and$ls180.v:3937$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3937$395_Y + connect \Y $and$ls180.v:3937$396_Y + end + attribute \src "ls180.v:3966.8-3966.73" + cell $and $and$ls180.v:3966$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3966$401_Y + end + attribute \src "ls180.v:3966.7-3966.114" + cell $and $and$ls180.v:3966$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$401_Y + connect \B $eq$ls180.v:3966$402_Y + connect \Y $and$ls180.v:3966$403_Y + end + attribute \src "ls180.v:3969.8-3969.73" + cell $and $and$ls180.v:3969$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3969$404_Y + end + attribute \src "ls180.v:3969.7-3969.114" + cell $and $and$ls180.v:3969$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3969$404_Y + connect \B $eq$ls180.v:3969$405_Y + connect \Y $and$ls180.v:3969$406_Y + end + attribute \src "ls180.v:3975.8-3975.73" + cell $and $and$ls180.v:3975$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3975$408_Y + end + attribute \src "ls180.v:3975.7-3975.114" + cell $and $and$ls180.v:3975$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3975$408_Y + connect \B $eq$ls180.v:3975$409_Y + connect \Y $and$ls180.v:3975$410_Y + end + attribute \src "ls180.v:3978.8-3978.73" + cell $and $and$ls180.v:3978$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3978$411_Y + end + attribute \src "ls180.v:3978.7-3978.114" + cell $and $and$ls180.v:3978$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3978$411_Y + connect \B $eq$ls180.v:3978$412_Y + connect \Y $and$ls180.v:3978$413_Y + end + attribute \src "ls180.v:3984.8-3984.73" + cell $and $and$ls180.v:3984$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3984$415_Y + end + attribute \src "ls180.v:3984.7-3984.114" + cell $and $and$ls180.v:3984$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3984$415_Y + connect \B $eq$ls180.v:3984$416_Y + connect \Y $and$ls180.v:3984$417_Y + end + attribute \src "ls180.v:3987.8-3987.73" + cell $and $and$ls180.v:3987$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3987$418_Y + end + attribute \src "ls180.v:3987.7-3987.114" + cell $and $and$ls180.v:3987$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$418_Y + connect \B $eq$ls180.v:3987$419_Y + connect \Y $and$ls180.v:3987$420_Y + end + attribute \src "ls180.v:3993.8-3993.73" + cell $and $and$ls180.v:3993$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3993$422_Y + end + attribute \src "ls180.v:3993.7-3993.114" + cell $and $and$ls180.v:3993$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3993$422_Y + connect \B $eq$ls180.v:3993$423_Y + connect \Y $and$ls180.v:3993$424_Y + end + attribute \src "ls180.v:3996.8-3996.73" + cell $and $and$ls180.v:3996$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3996$425_Y + end + attribute \src "ls180.v:3996.7-3996.114" + cell $and $and$ls180.v:3996$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3996$425_Y + connect \B $eq$ls180.v:3996$426_Y + connect \Y $and$ls180.v:3996$427_Y + end + attribute \src "ls180.v:4021.71-4021.151" + cell $and $and$ls180.v:4021$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:4021$431_Y + connect \Y $and$ls180.v:4021$432_Y + end + attribute \src "ls180.v:4021.70-4021.194" + cell $and $and$ls180.v:4021$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$432_Y + connect \B $not$ls180.v:4021$433_Y + connect \Y $and$ls180.v:4021$434_Y + end + attribute \src "ls180.v:4021.41-4021.222" + cell $and $and$ls180.v:4021$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:4021$436_Y + connect \Y $and$ls180.v:4021$437_Y + end + attribute \src "ls180.v:4059.71-4059.151" + cell $and $and$ls180.v:4059$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:4059$440_Y + connect \Y $and$ls180.v:4059$441_Y + end + attribute \src "ls180.v:4059.70-4059.194" + cell $and $and$ls180.v:4059$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4059$441_Y + connect \B $not$ls180.v:4059$442_Y + connect \Y $and$ls180.v:4059$443_Y + end + attribute \src "ls180.v:4059.41-4059.222" + cell $and $and$ls180.v:4059$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:4059$445_Y + connect \Y $and$ls180.v:4059$446_Y + end + attribute \src "ls180.v:4077.110-4077.179" + cell $and $and$ls180.v:4077$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4077$450_Y + connect \Y $and$ls180.v:4077$451_Y + end + attribute \src "ls180.v:4077.185-4077.254" + cell $and $and$ls180.v:4077$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4077$453_Y + connect \Y $and$ls180.v:4077$454_Y + end + attribute \src "ls180.v:4077.260-4077.329" + cell $and $and$ls180.v:4077$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4077$456_Y + connect \Y $and$ls180.v:4077$457_Y + end + attribute \src "ls180.v:4077.41-4077.332" + cell $and $and$ls180.v:4077$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4077$449_Y + connect \B $not$ls180.v:4077$459_Y + connect \Y $and$ls180.v:4077$460_Y + end + attribute \src "ls180.v:4077.40-4077.355" + cell $and $and$ls180.v:4077$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4077$460_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4077$461_Y + end + attribute \src "ls180.v:4078.34-4078.106" + cell $and $and$ls180.v:4078$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4078$462_Y + connect \B $not$ls180.v:4078$463_Y + connect \Y $and$ls180.v:4078$464_Y + end + attribute \src "ls180.v:4082.110-4082.179" + cell $and $and$ls180.v:4082$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4082$466_Y + connect \Y $and$ls180.v:4082$467_Y + end + attribute \src "ls180.v:4082.185-4082.254" + cell $and $and$ls180.v:4082$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4082$469_Y + connect \Y $and$ls180.v:4082$470_Y + end + attribute \src "ls180.v:4082.260-4082.329" + cell $and $and$ls180.v:4082$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4082$472_Y + connect \Y $and$ls180.v:4082$473_Y + end + attribute \src "ls180.v:4082.41-4082.332" + cell $and $and$ls180.v:4082$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4082$465_Y + connect \B $not$ls180.v:4082$475_Y + connect \Y $and$ls180.v:4082$476_Y + end + attribute \src "ls180.v:4082.40-4082.355" + cell $and $and$ls180.v:4082$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4082$476_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4082$477_Y + end + attribute \src "ls180.v:4083.34-4083.106" + cell $and $and$ls180.v:4083$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4083$478_Y + connect \B $not$ls180.v:4083$479_Y + connect \Y $and$ls180.v:4083$480_Y + end + attribute \src "ls180.v:4087.110-4087.179" + cell $and $and$ls180.v:4087$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4087$482_Y + connect \Y $and$ls180.v:4087$483_Y + end + attribute \src "ls180.v:4087.185-4087.254" + cell $and $and$ls180.v:4087$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4087$485_Y + connect \Y $and$ls180.v:4087$486_Y + end + attribute \src "ls180.v:4087.260-4087.329" + cell $and $and$ls180.v:4087$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4087$488_Y + connect \Y $and$ls180.v:4087$489_Y + end + attribute \src "ls180.v:4087.41-4087.332" + cell $and $and$ls180.v:4087$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4087$481_Y + connect \B $not$ls180.v:4087$491_Y + connect \Y $and$ls180.v:4087$492_Y + end + attribute \src "ls180.v:4087.40-4087.355" + cell $and $and$ls180.v:4087$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4087$492_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4087$493_Y + end + attribute \src "ls180.v:4088.34-4088.106" + cell $and $and$ls180.v:4088$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4088$494_Y + connect \B $not$ls180.v:4088$495_Y + connect \Y $and$ls180.v:4088$496_Y + end + attribute \src "ls180.v:4092.110-4092.179" + cell $and $and$ls180.v:4092$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4092$498_Y + connect \Y $and$ls180.v:4092$499_Y + end + attribute \src "ls180.v:4092.185-4092.254" + cell $and $and$ls180.v:4092$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4092$501_Y + connect \Y $and$ls180.v:4092$502_Y + end + attribute \src "ls180.v:4092.260-4092.329" + cell $and $and$ls180.v:4092$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4092$504_Y + connect \Y $and$ls180.v:4092$505_Y + end + attribute \src "ls180.v:4092.41-4092.332" + cell $and $and$ls180.v:4092$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4092$497_Y + connect \B $not$ls180.v:4092$507_Y + connect \Y $and$ls180.v:4092$508_Y + end + attribute \src "ls180.v:4092.40-4092.355" + cell $and $and$ls180.v:4092$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4092$508_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4092$509_Y + end + attribute \src "ls180.v:4093.34-4093.106" + cell $and $and$ls180.v:4093$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4093$510_Y + connect \B $not$ls180.v:4093$511_Y + connect \Y $and$ls180.v:4093$512_Y + end + attribute \src "ls180.v:4097.151-4097.220" + cell $and $and$ls180.v:4097$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4097$515_Y + connect \Y $and$ls180.v:4097$516_Y + end + attribute \src "ls180.v:4097.226-4097.295" + cell $and $and$ls180.v:4097$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4097$518_Y + connect \Y $and$ls180.v:4097$519_Y + end + attribute \src "ls180.v:4097.301-4097.370" + cell $and $and$ls180.v:4097$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4097$521_Y + connect \Y $and$ls180.v:4097$522_Y + end + attribute \src "ls180.v:4097.82-4097.373" + cell $and $and$ls180.v:4097$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$514_Y + connect \B $not$ls180.v:4097$524_Y + connect \Y $and$ls180.v:4097$525_Y + end + attribute \src "ls180.v:4097.43-4097.374" + cell $and $and$ls180.v:4097$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$513_Y + connect \B $and$ls180.v:4097$525_Y + connect \Y $and$ls180.v:4097$526_Y + end + attribute \src "ls180.v:4097.42-4097.410" + cell $and $and$ls180.v:4097$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4097$526_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:4097$527_Y + end + attribute \src "ls180.v:4097.525-4097.594" + cell $and $and$ls180.v:4097$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4097$531_Y + connect \Y $and$ls180.v:4097$532_Y + end + attribute \src "ls180.v:4097.600-4097.669" + cell $and $and$ls180.v:4097$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4097$534_Y + connect \Y $and$ls180.v:4097$535_Y + end + attribute \src "ls180.v:4097.675-4097.744" + cell $and $and$ls180.v:4097$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4097$537_Y + connect \Y $and$ls180.v:4097$538_Y + end + attribute \src "ls180.v:4097.456-4097.747" + cell $and $and$ls180.v:4097$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$530_Y + connect \B $not$ls180.v:4097$540_Y + connect \Y $and$ls180.v:4097$541_Y + end + attribute \src "ls180.v:4097.417-4097.748" + cell $and $and$ls180.v:4097$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$529_Y + connect \B $and$ls180.v:4097$541_Y + connect \Y $and$ls180.v:4097$542_Y + end + attribute \src "ls180.v:4097.416-4097.784" + cell $and $and$ls180.v:4097$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4097$542_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:4097$543_Y + end + attribute \src "ls180.v:4097.899-4097.968" + cell $and $and$ls180.v:4097$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4097$547_Y + connect \Y $and$ls180.v:4097$548_Y + end + attribute \src "ls180.v:4097.974-4097.1043" + cell $and $and$ls180.v:4097$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4097$550_Y + connect \Y $and$ls180.v:4097$551_Y + end + attribute \src "ls180.v:4097.1049-4097.1118" + cell $and $and$ls180.v:4097$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4097$553_Y + connect \Y $and$ls180.v:4097$554_Y + end + attribute \src "ls180.v:4097.830-4097.1121" + cell $and $and$ls180.v:4097$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$546_Y + connect \B $not$ls180.v:4097$556_Y + connect \Y $and$ls180.v:4097$557_Y + end + attribute \src "ls180.v:4097.791-4097.1122" + cell $and $and$ls180.v:4097$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$545_Y + connect \B $and$ls180.v:4097$557_Y + connect \Y $and$ls180.v:4097$558_Y + end + attribute \src "ls180.v:4097.790-4097.1158" + cell $and $and$ls180.v:4097$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4097$558_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:4097$559_Y + end + attribute \src "ls180.v:4097.1273-4097.1342" + cell $and $and$ls180.v:4097$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4097$563_Y + connect \Y $and$ls180.v:4097$564_Y + end + attribute \src "ls180.v:4097.1348-4097.1417" + cell $and $and$ls180.v:4097$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4097$566_Y + connect \Y $and$ls180.v:4097$567_Y + end + attribute \src "ls180.v:4097.1423-4097.1492" + cell $and $and$ls180.v:4097$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4097$569_Y + connect \Y $and$ls180.v:4097$570_Y + end + attribute \src "ls180.v:4097.1204-4097.1495" + cell $and $and$ls180.v:4097$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$562_Y + connect \B $not$ls180.v:4097$572_Y + connect \Y $and$ls180.v:4097$573_Y + end + attribute \src "ls180.v:4097.1165-4097.1496" + cell $and $and$ls180.v:4097$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4097$561_Y + connect \B $and$ls180.v:4097$573_Y + connect \Y $and$ls180.v:4097$574_Y + end + attribute \src "ls180.v:4097.1164-4097.1532" + cell $and $and$ls180.v:4097$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4097$574_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:4097$575_Y + end + attribute \src "ls180.v:4155.9-4155.46" + cell $and $and$ls180.v:4155$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4155$581_Y + end + attribute \src "ls180.v:4173.9-4173.46" + cell $and $and$ls180.v:4173$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4173$588_Y + end + attribute \src "ls180.v:4186.32-4186.75" + cell $and $and$ls180.v:4186$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4186$592_Y + end + attribute \src "ls180.v:4186.31-4186.99" + cell $and $and$ls180.v:4186$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4186$592_Y + connect \B $not$ls180.v:4186$593_Y + connect \Y $and$ls180.v:4186$594_Y + end + attribute \src "ls180.v:4187.34-4187.102" + cell $and $and$ls180.v:4187$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4187$595_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4187$596_Y + end + attribute \src "ls180.v:4187.33-4187.128" + cell $and $and$ls180.v:4187$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4187$596_Y + connect \B $not$ls180.v:4187$597_Y + connect \Y $and$ls180.v:4187$598_Y + end + attribute \src "ls180.v:4188.33-4188.104" + cell $and $and$ls180.v:4188$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4188$599_Y + connect \B $not$ls180.v:4188$600_Y + connect \Y $and$ls180.v:4188$601_Y + end + attribute \src "ls180.v:4189.49-4189.85" + cell $and $and$ls180.v:4189$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4189$602_Y + end + attribute \src "ls180.v:4189.90-4189.129" + cell $and $and$ls180.v:4189$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4189$603_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4189$604_Y + end + attribute \src "ls180.v:4189.32-4189.131" + cell $and $and$ls180.v:4189$606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4189$605_Y + connect \Y $and$ls180.v:4189$606_Y + end + attribute \src "ls180.v:4190.25-4190.66" + cell $and $and$ls180.v:4190$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4190$607_Y + end + attribute \src "ls180.v:4191.27-4191.72" + cell $and $and$ls180.v:4191$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4191$609_Y + end + attribute \src "ls180.v:4192.26-4192.71" + cell $and $and$ls180.v:4192$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4192$611_Y + end + attribute \src "ls180.v:4221.64-4221.88" + cell $and $and$ls180.v:4221$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4221$617_Y + end + attribute \src "ls180.v:4225.7-4225.78" + cell $and $and$ls180.v:4225$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4225$621_Y + end + attribute \src "ls180.v:4236.7-4236.78" + cell $and $and$ls180.v:4236$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4236$624_Y + end + attribute \src "ls180.v:4245.26-4245.97" + cell $and $and$ls180.v:4245$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4245$626_Y + end + attribute \src "ls180.v:4245.102-4245.173" + cell $and $and$ls180.v:4245$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4245$627_Y + end + attribute \src "ls180.v:4260.41-4260.133" + cell $and $and$ls180.v:4260$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4260$630_Y + connect \Y $and$ls180.v:4260$631_Y + end + attribute \src "ls180.v:4271.39-4271.136" + cell $and $and$ls180.v:4271$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4271$635_Y + connect \Y $and$ls180.v:4271$636_Y + end + attribute \src "ls180.v:4272.37-4272.104" + cell $and $and$ls180.v:4272$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4272$637_Y + end + attribute \src "ls180.v:4290.41-4290.133" + cell $and $and$ls180.v:4290$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4290$641_Y + connect \Y $and$ls180.v:4290$642_Y + end + attribute \src "ls180.v:4301.39-4301.136" + cell $and $and$ls180.v:4301$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4301$646_Y + connect \Y $and$ls180.v:4301$647_Y + end + attribute \src "ls180.v:4302.37-4302.104" + cell $and $and$ls180.v:4302$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4302$648_Y + end + attribute \src "ls180.v:4501.33-4501.86" + cell $and $and$ls180.v:4501$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4501$691_Y + connect \Y $and$ls180.v:4501$692_Y + end + attribute \src "ls180.v:4605.9-4605.68" + cell $and $and$ls180.v:4605$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4605$701_Y + end + attribute \src "ls180.v:4625.53-4625.145" + cell $and $and$ls180.v:4625$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4625$703_Y + connect \Y $and$ls180.v:4625$704_Y + end + attribute \src "ls180.v:4644.52-4644.137" + cell $and $and$ls180.v:4644$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4644$707_Y + end + attribute \src "ls180.v:4685.9-4685.68" + cell $and $and$ls180.v:4685$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4685$715_Y + end + attribute \src "ls180.v:4723.9-4723.68" + cell $and $and$ls180.v:4723$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4723$721_Y + end + attribute \src "ls180.v:4732.10-4732.69" + cell $and $and$ls180.v:4732$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4732$722_Y + end + attribute \src "ls180.v:4732.9-4732.93" + cell $and $and$ls180.v:4732$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4732$722_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4732$723_Y + end + attribute \src "ls180.v:4752.54-4752.117" + cell $and $and$ls180.v:4752$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4752$725_Y + end + attribute \src "ls180.v:4771.53-4771.140" + cell $and $and$ls180.v:4771$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4771$728_Y + end + attribute \src "ls180.v:4868.9-4868.70" + cell $and $and$ls180.v:4868$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4868$738_Y + end + attribute \src "ls180.v:4886.55-4886.120" + cell $and $and$ls180.v:4886$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4886$740_Y + end + attribute \src "ls180.v:4905.54-4905.143" + cell $and $and$ls180.v:4905$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4905$743_Y + end + attribute \src "ls180.v:4987.9-4987.70" + cell $and $and$ls180.v:4987$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:4987$758_Y + end + attribute \src "ls180.v:4994.9-4994.70" + cell $and $and$ls180.v:4994$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:4994$759_Y + end + attribute \src "ls180.v:5075.48-5075.124" + cell $and $and$ls180.v:5075$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5075$882_Y + end + attribute \src "ls180.v:5075.47-5075.165" + cell $and $and$ls180.v:5075$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5075$882_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5075$883_Y + end + attribute \src "ls180.v:5076.50-5076.127" + cell $and $and$ls180.v:5076$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5076$884_Y + end + attribute \src "ls180.v:5078.48-5078.124" + cell $and $and$ls180.v:5078$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5078$885_Y + end + attribute \src "ls180.v:5078.47-5078.165" + cell $and $and$ls180.v:5078$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5078$885_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5078$886_Y + end + attribute \src "ls180.v:5079.50-5079.127" + cell $and $and$ls180.v:5079$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5079$887_Y + end + attribute \src "ls180.v:5081.48-5081.124" + cell $and $and$ls180.v:5081$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5081$888_Y + end + attribute \src "ls180.v:5081.47-5081.165" + cell $and $and$ls180.v:5081$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5081$888_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5081$889_Y + end + attribute \src "ls180.v:5082.50-5082.127" + cell $and $and$ls180.v:5082$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5082$890_Y + end + attribute \src "ls180.v:5084.48-5084.124" + cell $and $and$ls180.v:5084$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5084$891_Y + end + attribute \src "ls180.v:5084.47-5084.165" + cell $and $and$ls180.v:5084$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5084$891_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5084$892_Y + end + attribute \src "ls180.v:5085.50-5085.127" + cell $and $and$ls180.v:5085$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5085$893_Y + end + attribute \src "ls180.v:5198.10-5198.86" + cell $and $and$ls180.v:5198$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:5198$942_Y + end + attribute \src "ls180.v:5198.9-5198.127" + cell $and $and$ls180.v:5198$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5198$942_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5198$943_Y + end + attribute \src "ls180.v:5208.9-5208.152" + cell $and $and$ls180.v:5208$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:5208$945_Y + connect \B $eq$ls180.v:5208$946_Y + connect \Y $and$ls180.v:5208$947_Y + end + attribute \src "ls180.v:5208.8-5208.226" + cell $and $and$ls180.v:5208$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5208$947_Y + connect \B $eq$ls180.v:5208$948_Y + connect \Y $and$ls180.v:5208$949_Y + end + attribute \src "ls180.v:5208.7-5208.300" + cell $and $and$ls180.v:5208$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5208$949_Y + connect \B $eq$ls180.v:5208$950_Y + connect \Y $and$ls180.v:5208$951_Y + end + attribute \src "ls180.v:5213.49-5213.124" + cell $and $and$ls180.v:5213$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5213$952_Y + end + attribute \src "ls180.v:5223.49-5223.124" + cell $and $and$ls180.v:5223$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5223$955_Y + end + attribute \src "ls180.v:5233.49-5233.124" + cell $and $and$ls180.v:5233$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5233$958_Y + end + attribute \src "ls180.v:5243.49-5243.124" + cell $and $and$ls180.v:5243$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5243$961_Y + end + attribute \src "ls180.v:5255.7-5255.84" + cell $and $and$ls180.v:5255$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5255$965_Y + connect \Y $and$ls180.v:5255$966_Y + end + attribute \src "ls180.v:5373.9-5373.64" + cell $and $and$ls180.v:5373$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5373$1015_Y + end + attribute \src "ls180.v:5425.10-5425.66" + cell $and $and$ls180.v:5425$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5425$1024_Y + end + attribute \src "ls180.v:5425.9-5425.97" + cell $and $and$ls180.v:5425$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5425$1024_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5425$1025_Y + end + attribute \src "ls180.v:5451.11-5451.71" + cell $and $and$ls180.v:5451$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5451$1033_Y + end + attribute \src "ls180.v:5535.43-5535.152" + cell $and $and$ls180.v:5535$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5535$1040_Y + connect \Y $and$ls180.v:5535$1041_Y + end + attribute \src "ls180.v:5536.41-5536.116" + cell $and $and$ls180.v:5536$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5536$1042_Y + end + attribute \src "ls180.v:5548.48-5548.125" + cell $and $and$ls180.v:5548$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5548$1047_Y + end + attribute \src "ls180.v:5575.9-5575.102" + cell $and $and$ls180.v:5575$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5575$1051_Y + end + attribute \src "ls180.v:5648.9-5648.58" + cell $and $and$ls180.v:5648$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5648$1057_Y + end + attribute \src "ls180.v:5701.51-5701.123" + cell $and $and$ls180.v:5701$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5701$1065_Y + end + attribute \src "ls180.v:5702.50-5702.120" + cell $and $and$ls180.v:5702$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5702$1066_Y + end + attribute \src "ls180.v:5703.49-5703.122" + cell $and $and$ls180.v:5703$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5703$1067_Y + end + attribute \src "ls180.v:5755.43-5755.152" + cell $and $and$ls180.v:5755$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5755$1071_Y + connect \Y $and$ls180.v:5755$1072_Y + end + attribute \src "ls180.v:5756.41-5756.116" + cell $and $and$ls180.v:5756$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5756$1073_Y + end + attribute \src "ls180.v:5788.9-5788.76" + cell $and $and$ls180.v:5788$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5788$1077_Y + end + attribute \src "ls180.v:5791.44-5791.120" + cell $and $and$ls180.v:5791$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5791$1078_Y + connect \Y $and$ls180.v:5791$1079_Y + end + attribute \src "ls180.v:5811.46-5811.90" + cell $and $and$ls180.v:5811$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5811$1080_Y + connect \Y $and$ls180.v:5811$1081_Y + end + attribute \src "ls180.v:5812.46-5812.90" + cell $and $and$ls180.v:5812$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5812$1082_Y + connect \Y $and$ls180.v:5812$1083_Y + end + attribute \src "ls180.v:5813.49-5813.93" + cell $and $and$ls180.v:5813$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5813$1084_Y + connect \Y $and$ls180.v:5813$1085_Y + end + attribute \src "ls180.v:5814.35-5814.79" + cell $and $and$ls180.v:5814$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5814$1086_Y + connect \Y $and$ls180.v:5814$1087_Y + end + attribute \src "ls180.v:5815.35-5815.79" + cell $and $and$ls180.v:5815$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5815$1088_Y + connect \Y $and$ls180.v:5815$1089_Y + end + attribute \src "ls180.v:5816.46-5816.90" + cell $and $and$ls180.v:5816$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5816$1090_Y + connect \Y $and$ls180.v:5816$1091_Y + end + attribute \src "ls180.v:5817.46-5817.90" + cell $and $and$ls180.v:5817$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5817$1092_Y + connect \Y $and$ls180.v:5817$1093_Y + end + attribute \src "ls180.v:5818.49-5818.93" + cell $and $and$ls180.v:5818$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5818$1094_Y + connect \Y $and$ls180.v:5818$1095_Y + end + attribute \src "ls180.v:5819.35-5819.79" + cell $and $and$ls180.v:5819$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5819$1096_Y + connect \Y $and$ls180.v:5819$1097_Y + end + attribute \src "ls180.v:5820.35-5820.79" + cell $and $and$ls180.v:5820$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5820$1098_Y + connect \Y $and$ls180.v:5820$1099_Y + end + attribute \src "ls180.v:5905.40-5905.81" + cell $and $and$ls180.v:5905$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:5905$1111_Y + end + attribute \src "ls180.v:5906.36-5906.77" + cell $and $and$ls180.v:5906$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:5906$1112_Y + end + attribute \src "ls180.v:5907.51-5907.92" + cell $and $and$ls180.v:5907$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:5907$1113_Y + end + attribute \src "ls180.v:5908.51-5908.92" + cell $and $and$ls180.v:5908$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:5908$1114_Y + end + attribute \src "ls180.v:5909.52-5909.93" + cell $and $and$ls180.v:5909$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:5909$1115_Y + end + attribute \src "ls180.v:5910.52-5910.93" + cell $and $and$ls180.v:5910$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [5] + connect \Y $and$ls180.v:5910$1116_Y + end + attribute \src "ls180.v:5911.52-5911.93" + cell $and $and$ls180.v:5911$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [6] + connect \Y $and$ls180.v:5911$1117_Y + end + attribute \src "ls180.v:5912.52-5912.93" + cell $and $and$ls180.v:5912$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [7] + connect \Y $and$ls180.v:5912$1118_Y + end + attribute \src "ls180.v:5913.54-5913.95" + cell $and $and$ls180.v:5913$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [8] + connect \Y $and$ls180.v:5913$1119_Y + end + attribute \src "ls180.v:5914.55-5914.96" + cell $and $and$ls180.v:5914$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [9] + connect \Y $and$ls180.v:5914$1120_Y + end + attribute \src "ls180.v:5916.25-5916.64" + cell $and $and$ls180.v:5916$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:5916$1130_Y + end + attribute \src "ls180.v:5916.24-5916.89" + cell $and $and$ls180.v:5916$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5916$1130_Y + connect \B $not$ls180.v:5916$1131_Y + connect \Y $and$ls180.v:5916$1132_Y + end + attribute \src "ls180.v:5922.36-5922.97" + cell $and $and$ls180.v:5922$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:5922$1143_Y + end + attribute \src "ls180.v:5922.102-5922.159" + cell $and $and$ls180.v:5922$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_ram_bus_ram_bus_dat_r + connect \Y $and$ls180.v:5922$1144_Y + end + attribute \src "ls180.v:5922.165-5922.237" + cell $and $and$ls180.v:5922$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_interface0_converted_interface_dat_r + connect \Y $and$ls180.v:5922$1146_Y + end + attribute \src "ls180.v:5922.243-5922.315" + cell $and $and$ls180.v:5922$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_interface1_converted_interface_dat_r + connect \Y $and$ls180.v:5922$1148_Y + end + attribute \src "ls180.v:5922.321-5922.394" + cell $and $and$ls180.v:5922$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \main_libresocsim_libresoc_interface0_dat_r + connect \Y $and$ls180.v:5922$1150_Y + end + attribute \src "ls180.v:5922.400-5922.473" + cell $and $and$ls180.v:5922$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } + connect \B \main_libresocsim_libresoc_interface1_dat_r + connect \Y $and$ls180.v:5922$1152_Y + end + attribute \src "ls180.v:5922.479-5922.552" + cell $and $and$ls180.v:5922$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \B \main_libresocsim_libresoc_interface2_dat_r + connect \Y $and$ls180.v:5922$1154_Y + end + attribute \src "ls180.v:5922.558-5922.631" + cell $and $and$ls180.v:5922$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } + connect \B \main_libresocsim_libresoc_interface3_dat_r + connect \Y $and$ls180.v:5922$1156_Y + end + attribute \src "ls180.v:5922.637-5922.712" + cell $and $and$ls180.v:5922$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } + connect \B \main_socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:5922$1158_Y + end + attribute \src "ls180.v:5922.718-5922.794" + cell $and $and$ls180.v:5922$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } + connect \B \builder_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:5922$1160_Y + end + attribute \src "ls180.v:5932.39-5932.92" + cell $and $and$ls180.v:5932$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5932$1164_Y + end + attribute \src "ls180.v:5932.38-5932.142" + cell $and $and$ls180.v:5932$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5932$1164_Y + connect \B $eq$ls180.v:5932$1165_Y + connect \Y $and$ls180.v:5932$1166_Y + end + attribute \src "ls180.v:5933.39-5933.95" + cell $and $and$ls180.v:5933$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5933$1167_Y + connect \Y $and$ls180.v:5933$1168_Y + end + attribute \src "ls180.v:5933.38-5933.145" + cell $and $and$ls180.v:5933$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5933$1168_Y + connect \B $eq$ls180.v:5933$1169_Y + connect \Y $and$ls180.v:5933$1170_Y + end + attribute \src "ls180.v:5935.41-5935.94" + cell $and $and$ls180.v:5935$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5935$1171_Y + end + attribute \src "ls180.v:5935.40-5935.144" + cell $and $and$ls180.v:5935$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5935$1171_Y + connect \B $eq$ls180.v:5935$1172_Y + connect \Y $and$ls180.v:5935$1173_Y + end + attribute \src "ls180.v:5936.41-5936.97" + cell $and $and$ls180.v:5936$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5936$1174_Y + connect \Y $and$ls180.v:5936$1175_Y + end + attribute \src "ls180.v:5936.40-5936.147" + cell $and $and$ls180.v:5936$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5936$1175_Y + connect \B $eq$ls180.v:5936$1176_Y + connect \Y $and$ls180.v:5936$1177_Y + end + attribute \src "ls180.v:5938.41-5938.94" + cell $and $and$ls180.v:5938$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5938$1178_Y + end + attribute \src "ls180.v:5938.40-5938.144" + cell $and $and$ls180.v:5938$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5938$1178_Y + connect \B $eq$ls180.v:5938$1179_Y + connect \Y $and$ls180.v:5938$1180_Y + end + attribute \src "ls180.v:5939.41-5939.97" + cell $and $and$ls180.v:5939$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5939$1181_Y + connect \Y $and$ls180.v:5939$1182_Y + end + attribute \src "ls180.v:5939.40-5939.147" + cell $and $and$ls180.v:5939$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5939$1182_Y + connect \B $eq$ls180.v:5939$1183_Y + connect \Y $and$ls180.v:5939$1184_Y + end + attribute \src "ls180.v:5941.41-5941.94" + cell $and $and$ls180.v:5941$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5941$1185_Y + end + attribute \src "ls180.v:5941.40-5941.144" + cell $and $and$ls180.v:5941$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5941$1185_Y + connect \B $eq$ls180.v:5941$1186_Y + connect \Y $and$ls180.v:5941$1187_Y + end + attribute \src "ls180.v:5942.41-5942.97" + cell $and $and$ls180.v:5942$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5942$1188_Y + connect \Y $and$ls180.v:5942$1189_Y + end + attribute \src "ls180.v:5942.40-5942.147" + cell $and $and$ls180.v:5942$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5942$1189_Y + connect \B $eq$ls180.v:5942$1190_Y + connect \Y $and$ls180.v:5942$1191_Y + end + attribute \src "ls180.v:5944.41-5944.94" + cell $and $and$ls180.v:5944$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5944$1192_Y + end + attribute \src "ls180.v:5944.40-5944.144" + cell $and $and$ls180.v:5944$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5944$1192_Y + connect \B $eq$ls180.v:5944$1193_Y + connect \Y $and$ls180.v:5944$1194_Y + end + attribute \src "ls180.v:5945.41-5945.97" + cell $and $and$ls180.v:5945$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5945$1195_Y + connect \Y $and$ls180.v:5945$1196_Y + end + attribute \src "ls180.v:5945.40-5945.147" + cell $and $and$ls180.v:5945$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5945$1196_Y + connect \B $eq$ls180.v:5945$1197_Y + connect \Y $and$ls180.v:5945$1198_Y + end + attribute \src "ls180.v:5947.44-5947.97" + cell $and $and$ls180.v:5947$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5947$1199_Y + end + attribute \src "ls180.v:5947.43-5947.147" + cell $and $and$ls180.v:5947$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5947$1199_Y + connect \B $eq$ls180.v:5947$1200_Y + connect \Y $and$ls180.v:5947$1201_Y + end + attribute \src "ls180.v:5948.44-5948.100" + cell $and $and$ls180.v:5948$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5948$1202_Y + connect \Y $and$ls180.v:5948$1203_Y + end + attribute \src "ls180.v:5948.43-5948.150" + cell $and $and$ls180.v:5948$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5948$1203_Y + connect \B $eq$ls180.v:5948$1204_Y + connect \Y $and$ls180.v:5948$1205_Y + end + attribute \src "ls180.v:5950.44-5950.97" + cell $and $and$ls180.v:5950$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5950$1206_Y + end + attribute \src "ls180.v:5950.43-5950.147" + cell $and $and$ls180.v:5950$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5950$1206_Y + connect \B $eq$ls180.v:5950$1207_Y + connect \Y $and$ls180.v:5950$1208_Y + end + attribute \src "ls180.v:5951.44-5951.100" + cell $and $and$ls180.v:5951$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5951$1209_Y + connect \Y $and$ls180.v:5951$1210_Y + end + attribute \src "ls180.v:5951.43-5951.150" + cell $and $and$ls180.v:5951$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5951$1210_Y + connect \B $eq$ls180.v:5951$1211_Y + connect \Y $and$ls180.v:5951$1212_Y + end + attribute \src "ls180.v:5953.44-5953.97" + cell $and $and$ls180.v:5953$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5953$1213_Y + end + attribute \src "ls180.v:5953.43-5953.147" + cell $and $and$ls180.v:5953$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5953$1213_Y + connect \B $eq$ls180.v:5953$1214_Y + connect \Y $and$ls180.v:5953$1215_Y + end + attribute \src "ls180.v:5954.44-5954.100" + cell $and $and$ls180.v:5954$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5954$1216_Y + connect \Y $and$ls180.v:5954$1217_Y + end + attribute \src "ls180.v:5954.43-5954.150" + cell $and $and$ls180.v:5954$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5954$1217_Y + connect \B $eq$ls180.v:5954$1218_Y + connect \Y $and$ls180.v:5954$1219_Y + end + attribute \src "ls180.v:5956.44-5956.97" + cell $and $and$ls180.v:5956$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5956$1220_Y + end + attribute \src "ls180.v:5956.43-5956.147" + cell $and $and$ls180.v:5956$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5956$1220_Y + connect \B $eq$ls180.v:5956$1221_Y + connect \Y $and$ls180.v:5956$1222_Y + end + attribute \src "ls180.v:5957.44-5957.100" + cell $and $and$ls180.v:5957$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5957$1223_Y + connect \Y $and$ls180.v:5957$1224_Y + end + attribute \src "ls180.v:5957.43-5957.150" + cell $and $and$ls180.v:5957$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5957$1224_Y + connect \B $eq$ls180.v:5957$1225_Y + connect \Y $and$ls180.v:5957$1226_Y + end + attribute \src "ls180.v:5970.36-5970.89" + cell $and $and$ls180.v:5970$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5970$1228_Y + end + attribute \src "ls180.v:5970.35-5970.139" + cell $and $and$ls180.v:5970$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5970$1228_Y + connect \B $eq$ls180.v:5970$1229_Y + connect \Y $and$ls180.v:5970$1230_Y + end + attribute \src "ls180.v:5971.36-5971.92" + cell $and $and$ls180.v:5971$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5971$1231_Y + connect \Y $and$ls180.v:5971$1232_Y + end + attribute \src "ls180.v:5971.35-5971.142" + cell $and $and$ls180.v:5971$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5971$1232_Y + connect \B $eq$ls180.v:5971$1233_Y + connect \Y $and$ls180.v:5971$1234_Y + end + attribute \src "ls180.v:5973.36-5973.89" + cell $and $and$ls180.v:5973$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5973$1235_Y + end + attribute \src "ls180.v:5973.35-5973.139" + cell $and $and$ls180.v:5973$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5973$1235_Y + connect \B $eq$ls180.v:5973$1236_Y + connect \Y $and$ls180.v:5973$1237_Y + end + attribute \src "ls180.v:5974.36-5974.92" + cell $and $and$ls180.v:5974$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5974$1238_Y + connect \Y $and$ls180.v:5974$1239_Y + end + attribute \src "ls180.v:5974.35-5974.142" + cell $and $and$ls180.v:5974$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5974$1239_Y + connect \B $eq$ls180.v:5974$1240_Y + connect \Y $and$ls180.v:5974$1241_Y + end + attribute \src "ls180.v:5976.36-5976.89" + cell $and $and$ls180.v:5976$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5976$1242_Y + end + attribute \src "ls180.v:5976.35-5976.139" + cell $and $and$ls180.v:5976$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5976$1242_Y + connect \B $eq$ls180.v:5976$1243_Y + connect \Y $and$ls180.v:5976$1244_Y + end + attribute \src "ls180.v:5977.36-5977.92" + cell $and $and$ls180.v:5977$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5977$1245_Y + connect \Y $and$ls180.v:5977$1246_Y + end + attribute \src "ls180.v:5977.35-5977.142" + cell $and $and$ls180.v:5977$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5977$1246_Y + connect \B $eq$ls180.v:5977$1247_Y + connect \Y $and$ls180.v:5977$1248_Y + end + attribute \src "ls180.v:5979.36-5979.89" + cell $and $and$ls180.v:5979$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5979$1249_Y + end + attribute \src "ls180.v:5979.35-5979.139" + cell $and $and$ls180.v:5979$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5979$1249_Y + connect \B $eq$ls180.v:5979$1250_Y + connect \Y $and$ls180.v:5979$1251_Y + end + attribute \src "ls180.v:5980.36-5980.92" + cell $and $and$ls180.v:5980$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5980$1252_Y + connect \Y $and$ls180.v:5980$1253_Y + end + attribute \src "ls180.v:5980.35-5980.142" + cell $and $and$ls180.v:5980$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5980$1253_Y + connect \B $eq$ls180.v:5980$1254_Y + connect \Y $and$ls180.v:5980$1255_Y + end + attribute \src "ls180.v:5982.37-5982.90" + cell $and $and$ls180.v:5982$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5982$1256_Y + end + attribute \src "ls180.v:5982.36-5982.140" + cell $and $and$ls180.v:5982$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5982$1256_Y + connect \B $eq$ls180.v:5982$1257_Y + connect \Y $and$ls180.v:5982$1258_Y + end + attribute \src "ls180.v:5983.37-5983.93" + cell $and $and$ls180.v:5983$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5983$1259_Y + connect \Y $and$ls180.v:5983$1260_Y + end + attribute \src "ls180.v:5983.36-5983.143" + cell $and $and$ls180.v:5983$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5983$1260_Y + connect \B $eq$ls180.v:5983$1261_Y + connect \Y $and$ls180.v:5983$1262_Y + end + attribute \src "ls180.v:5985.37-5985.90" + cell $and $and$ls180.v:5985$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5985$1263_Y + end + attribute \src "ls180.v:5985.36-5985.140" + cell $and $and$ls180.v:5985$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5985$1263_Y + connect \B $eq$ls180.v:5985$1264_Y + connect \Y $and$ls180.v:5985$1265_Y + end + attribute \src "ls180.v:5986.37-5986.93" + cell $and $and$ls180.v:5986$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5986$1266_Y + connect \Y $and$ls180.v:5986$1267_Y + end + attribute \src "ls180.v:5986.36-5986.143" + cell $and $and$ls180.v:5986$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5986$1267_Y + connect \B $eq$ls180.v:5986$1268_Y + connect \Y $and$ls180.v:5986$1269_Y + end + attribute \src "ls180.v:5996.35-5996.88" + cell $and $and$ls180.v:5996$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5996$1271_Y + end + attribute \src "ls180.v:5996.34-5996.136" + cell $and $and$ls180.v:5996$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5996$1271_Y + connect \B $eq$ls180.v:5996$1272_Y + connect \Y $and$ls180.v:5996$1273_Y + end + attribute \src "ls180.v:5997.35-5997.91" + cell $and $and$ls180.v:5997$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5997$1274_Y + connect \Y $and$ls180.v:5997$1275_Y + end + attribute \src "ls180.v:5997.34-5997.139" + cell $and $and$ls180.v:5997$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5997$1275_Y + connect \B $eq$ls180.v:5997$1276_Y + connect \Y $and$ls180.v:5997$1277_Y + end + attribute \src "ls180.v:5999.34-5999.87" + cell $and $and$ls180.v:5999$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5999$1278_Y + end + attribute \src "ls180.v:5999.33-5999.135" + cell $and $and$ls180.v:5999$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5999$1278_Y + connect \B $eq$ls180.v:5999$1279_Y + connect \Y $and$ls180.v:5999$1280_Y + end + attribute \src "ls180.v:6000.34-6000.90" + cell $and $and$ls180.v:6000$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:6000$1281_Y + connect \Y $and$ls180.v:6000$1282_Y + end + attribute \src "ls180.v:6000.33-6000.138" + cell $and $and$ls180.v:6000$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6000$1282_Y + connect \B $eq$ls180.v:6000$1283_Y + connect \Y $and$ls180.v:6000$1284_Y + end + attribute \src "ls180.v:6010.40-6010.93" + cell $and $and$ls180.v:6010$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6010$1286_Y + end + attribute \src "ls180.v:6010.39-6010.143" + cell $and $and$ls180.v:6010$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6010$1286_Y + connect \B $eq$ls180.v:6010$1287_Y + connect \Y $and$ls180.v:6010$1288_Y + end + attribute \src "ls180.v:6011.40-6011.96" + cell $and $and$ls180.v:6011$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6011$1289_Y + connect \Y $and$ls180.v:6011$1290_Y + end + attribute \src "ls180.v:6011.39-6011.146" + cell $and $and$ls180.v:6011$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6011$1290_Y + connect \B $eq$ls180.v:6011$1291_Y + connect \Y $and$ls180.v:6011$1292_Y + end + attribute \src "ls180.v:6013.39-6013.92" + cell $and $and$ls180.v:6013$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6013$1293_Y + end + attribute \src "ls180.v:6013.38-6013.142" + cell $and $and$ls180.v:6013$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6013$1293_Y + connect \B $eq$ls180.v:6013$1294_Y + connect \Y $and$ls180.v:6013$1295_Y + end + attribute \src "ls180.v:6014.39-6014.95" + cell $and $and$ls180.v:6014$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6014$1296_Y + connect \Y $and$ls180.v:6014$1297_Y + end + attribute \src "ls180.v:6014.38-6014.145" + cell $and $and$ls180.v:6014$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6014$1297_Y + connect \B $eq$ls180.v:6014$1298_Y + connect \Y $and$ls180.v:6014$1299_Y + end + attribute \src "ls180.v:6016.39-6016.92" + cell $and $and$ls180.v:6016$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6016$1300_Y + end + attribute \src "ls180.v:6016.38-6016.142" + cell $and $and$ls180.v:6016$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6016$1300_Y + connect \B $eq$ls180.v:6016$1301_Y + connect \Y $and$ls180.v:6016$1302_Y + end + attribute \src "ls180.v:6017.39-6017.95" + cell $and $and$ls180.v:6017$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6017$1303_Y + connect \Y $and$ls180.v:6017$1304_Y + end + attribute \src "ls180.v:6017.38-6017.145" + cell $and $and$ls180.v:6017$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6017$1304_Y + connect \B $eq$ls180.v:6017$1305_Y + connect \Y $and$ls180.v:6017$1306_Y + end + attribute \src "ls180.v:6019.39-6019.92" + cell $and $and$ls180.v:6019$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6019$1307_Y + end + attribute \src "ls180.v:6019.38-6019.142" + cell $and $and$ls180.v:6019$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6019$1307_Y + connect \B $eq$ls180.v:6019$1308_Y + connect \Y $and$ls180.v:6019$1309_Y + end + attribute \src "ls180.v:6020.39-6020.95" + cell $and $and$ls180.v:6020$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6020$1310_Y + connect \Y $and$ls180.v:6020$1311_Y + end + attribute \src "ls180.v:6020.38-6020.145" + cell $and $and$ls180.v:6020$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6020$1311_Y + connect \B $eq$ls180.v:6020$1312_Y + connect \Y $and$ls180.v:6020$1313_Y + end + attribute \src "ls180.v:6022.39-6022.92" + cell $and $and$ls180.v:6022$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6022$1314_Y + end + attribute \src "ls180.v:6022.38-6022.142" + cell $and $and$ls180.v:6022$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6022$1314_Y + connect \B $eq$ls180.v:6022$1315_Y + connect \Y $and$ls180.v:6022$1316_Y + end + attribute \src "ls180.v:6023.39-6023.95" + cell $and $and$ls180.v:6023$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6023$1317_Y + connect \Y $and$ls180.v:6023$1318_Y + end + attribute \src "ls180.v:6023.38-6023.145" + cell $and $and$ls180.v:6023$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6023$1318_Y + connect \B $eq$ls180.v:6023$1319_Y + connect \Y $and$ls180.v:6023$1320_Y + end + attribute \src "ls180.v:6025.40-6025.93" + cell $and $and$ls180.v:6025$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6025$1321_Y + end + attribute \src "ls180.v:6025.39-6025.143" + cell $and $and$ls180.v:6025$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6025$1321_Y + connect \B $eq$ls180.v:6025$1322_Y + connect \Y $and$ls180.v:6025$1323_Y + end + attribute \src "ls180.v:6026.40-6026.96" + cell $and $and$ls180.v:6026$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6026$1324_Y + connect \Y $and$ls180.v:6026$1325_Y + end + attribute \src "ls180.v:6026.39-6026.146" + cell $and $and$ls180.v:6026$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6026$1325_Y + connect \B $eq$ls180.v:6026$1326_Y + connect \Y $and$ls180.v:6026$1327_Y + end + attribute \src "ls180.v:6028.40-6028.93" + cell $and $and$ls180.v:6028$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6028$1328_Y + end + attribute \src "ls180.v:6028.39-6028.143" + cell $and $and$ls180.v:6028$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6028$1328_Y + connect \B $eq$ls180.v:6028$1329_Y + connect \Y $and$ls180.v:6028$1330_Y + end + attribute \src "ls180.v:6029.40-6029.96" + cell $and $and$ls180.v:6029$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6029$1331_Y + connect \Y $and$ls180.v:6029$1332_Y + end + attribute \src "ls180.v:6029.39-6029.146" + cell $and $and$ls180.v:6029$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6029$1332_Y + connect \B $eq$ls180.v:6029$1333_Y + connect \Y $and$ls180.v:6029$1334_Y + end + attribute \src "ls180.v:6031.40-6031.93" + cell $and $and$ls180.v:6031$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6031$1335_Y + end + attribute \src "ls180.v:6031.39-6031.143" + cell $and $and$ls180.v:6031$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6031$1335_Y + connect \B $eq$ls180.v:6031$1336_Y + connect \Y $and$ls180.v:6031$1337_Y + end + attribute \src "ls180.v:6032.40-6032.96" + cell $and $and$ls180.v:6032$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6032$1338_Y + connect \Y $and$ls180.v:6032$1339_Y + end + attribute \src "ls180.v:6032.39-6032.146" + cell $and $and$ls180.v:6032$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6032$1339_Y + connect \B $eq$ls180.v:6032$1340_Y + connect \Y $and$ls180.v:6032$1341_Y + end + attribute \src "ls180.v:6034.40-6034.93" + cell $and $and$ls180.v:6034$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6034$1342_Y + end + attribute \src "ls180.v:6034.39-6034.143" + cell $and $and$ls180.v:6034$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6034$1342_Y + connect \B $eq$ls180.v:6034$1343_Y + connect \Y $and$ls180.v:6034$1344_Y + end + attribute \src "ls180.v:6035.40-6035.96" + cell $and $and$ls180.v:6035$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6035$1345_Y + connect \Y $and$ls180.v:6035$1346_Y + end + attribute \src "ls180.v:6035.39-6035.146" + cell $and $and$ls180.v:6035$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6035$1346_Y + connect \B $eq$ls180.v:6035$1347_Y + connect \Y $and$ls180.v:6035$1348_Y + end + attribute \src "ls180.v:6047.40-6047.93" + cell $and $and$ls180.v:6047$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6047$1350_Y + end + attribute \src "ls180.v:6047.39-6047.143" + cell $and $and$ls180.v:6047$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6047$1350_Y + connect \B $eq$ls180.v:6047$1351_Y + connect \Y $and$ls180.v:6047$1352_Y + end + attribute \src "ls180.v:6048.40-6048.96" + cell $and $and$ls180.v:6048$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6048$1353_Y + connect \Y $and$ls180.v:6048$1354_Y + end + attribute \src "ls180.v:6048.39-6048.146" + cell $and $and$ls180.v:6048$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6048$1354_Y + connect \B $eq$ls180.v:6048$1355_Y + connect \Y $and$ls180.v:6048$1356_Y + end + attribute \src "ls180.v:6050.39-6050.92" + cell $and $and$ls180.v:6050$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6050$1357_Y + end + attribute \src "ls180.v:6050.38-6050.142" + cell $and $and$ls180.v:6050$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6050$1357_Y + connect \B $eq$ls180.v:6050$1358_Y + connect \Y $and$ls180.v:6050$1359_Y + end + attribute \src "ls180.v:6051.39-6051.95" + cell $and $and$ls180.v:6051$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6051$1360_Y + connect \Y $and$ls180.v:6051$1361_Y + end + attribute \src "ls180.v:6051.38-6051.145" + cell $and $and$ls180.v:6051$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6051$1361_Y + connect \B $eq$ls180.v:6051$1362_Y + connect \Y $and$ls180.v:6051$1363_Y + end + attribute \src "ls180.v:6053.39-6053.92" + cell $and $and$ls180.v:6053$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6053$1364_Y + end + attribute \src "ls180.v:6053.38-6053.142" + cell $and $and$ls180.v:6053$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6053$1364_Y + connect \B $eq$ls180.v:6053$1365_Y + connect \Y $and$ls180.v:6053$1366_Y + end + attribute \src "ls180.v:6054.39-6054.95" + cell $and $and$ls180.v:6054$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6054$1367_Y + connect \Y $and$ls180.v:6054$1368_Y + end + attribute \src "ls180.v:6054.38-6054.145" + cell $and $and$ls180.v:6054$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6054$1368_Y + connect \B $eq$ls180.v:6054$1369_Y + connect \Y $and$ls180.v:6054$1370_Y + end + attribute \src "ls180.v:6056.39-6056.92" + cell $and $and$ls180.v:6056$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6056$1371_Y + end + attribute \src "ls180.v:6056.38-6056.142" + cell $and $and$ls180.v:6056$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6056$1371_Y + connect \B $eq$ls180.v:6056$1372_Y + connect \Y $and$ls180.v:6056$1373_Y + end + attribute \src "ls180.v:6057.39-6057.95" + cell $and $and$ls180.v:6057$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6057$1374_Y + connect \Y $and$ls180.v:6057$1375_Y + end + attribute \src "ls180.v:6057.38-6057.145" + cell $and $and$ls180.v:6057$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6057$1375_Y + connect \B $eq$ls180.v:6057$1376_Y + connect \Y $and$ls180.v:6057$1377_Y + end + attribute \src "ls180.v:6059.39-6059.92" + cell $and $and$ls180.v:6059$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6059$1378_Y + end + attribute \src "ls180.v:6059.38-6059.142" + cell $and $and$ls180.v:6059$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1378_Y + connect \B $eq$ls180.v:6059$1379_Y + connect \Y $and$ls180.v:6059$1380_Y + end + attribute \src "ls180.v:6060.39-6060.95" + cell $and $and$ls180.v:6060$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6060$1381_Y + connect \Y $and$ls180.v:6060$1382_Y + end + attribute \src "ls180.v:6060.38-6060.145" + cell $and $and$ls180.v:6060$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6060$1382_Y + connect \B $eq$ls180.v:6060$1383_Y + connect \Y $and$ls180.v:6060$1384_Y + end + attribute \src "ls180.v:6062.40-6062.93" + cell $and $and$ls180.v:6062$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6062$1385_Y + end + attribute \src "ls180.v:6062.39-6062.143" + cell $and $and$ls180.v:6062$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1385_Y + connect \B $eq$ls180.v:6062$1386_Y + connect \Y $and$ls180.v:6062$1387_Y + end + attribute \src "ls180.v:6063.40-6063.96" + cell $and $and$ls180.v:6063$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6063$1388_Y + connect \Y $and$ls180.v:6063$1389_Y + end + attribute \src "ls180.v:6063.39-6063.146" + cell $and $and$ls180.v:6063$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6063$1389_Y + connect \B $eq$ls180.v:6063$1390_Y + connect \Y $and$ls180.v:6063$1391_Y + end + attribute \src "ls180.v:6065.40-6065.93" + cell $and $and$ls180.v:6065$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6065$1392_Y + end + attribute \src "ls180.v:6065.39-6065.143" + cell $and $and$ls180.v:6065$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1392_Y + connect \B $eq$ls180.v:6065$1393_Y + connect \Y $and$ls180.v:6065$1394_Y + end + attribute \src "ls180.v:6066.40-6066.96" + cell $and $and$ls180.v:6066$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6066$1395_Y + connect \Y $and$ls180.v:6066$1396_Y + end + attribute \src "ls180.v:6066.39-6066.146" + cell $and $and$ls180.v:6066$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6066$1396_Y + connect \B $eq$ls180.v:6066$1397_Y + connect \Y $and$ls180.v:6066$1398_Y + end + attribute \src "ls180.v:6068.40-6068.93" + cell $and $and$ls180.v:6068$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6068$1399_Y + end + attribute \src "ls180.v:6068.39-6068.143" + cell $and $and$ls180.v:6068$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6068$1399_Y + connect \B $eq$ls180.v:6068$1400_Y + connect \Y $and$ls180.v:6068$1401_Y + end + attribute \src "ls180.v:6069.40-6069.96" + cell $and $and$ls180.v:6069$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6069$1402_Y + connect \Y $and$ls180.v:6069$1403_Y + end + attribute \src "ls180.v:6069.39-6069.146" + cell $and $and$ls180.v:6069$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6069$1403_Y + connect \B $eq$ls180.v:6069$1404_Y + connect \Y $and$ls180.v:6069$1405_Y + end + attribute \src "ls180.v:6071.40-6071.93" + cell $and $and$ls180.v:6071$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6071$1406_Y + end + attribute \src "ls180.v:6071.39-6071.143" + cell $and $and$ls180.v:6071$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6071$1406_Y + connect \B $eq$ls180.v:6071$1407_Y + connect \Y $and$ls180.v:6071$1408_Y + end + attribute \src "ls180.v:6072.40-6072.96" + cell $and $and$ls180.v:6072$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6072$1409_Y + connect \Y $and$ls180.v:6072$1410_Y + end + attribute \src "ls180.v:6072.39-6072.146" + cell $and $and$ls180.v:6072$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6072$1410_Y + connect \B $eq$ls180.v:6072$1411_Y + connect \Y $and$ls180.v:6072$1412_Y + end + attribute \src "ls180.v:6084.42-6084.95" + cell $and $and$ls180.v:6084$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6084$1414_Y + end + attribute \src "ls180.v:6084.41-6084.145" + cell $and $and$ls180.v:6084$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6084$1414_Y + connect \B $eq$ls180.v:6084$1415_Y + connect \Y $and$ls180.v:6084$1416_Y + end + attribute \src "ls180.v:6085.42-6085.98" + cell $and $and$ls180.v:6085$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6085$1417_Y + connect \Y $and$ls180.v:6085$1418_Y + end + attribute \src "ls180.v:6085.41-6085.148" + cell $and $and$ls180.v:6085$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6085$1418_Y + connect \B $eq$ls180.v:6085$1419_Y + connect \Y $and$ls180.v:6085$1420_Y + end + attribute \src "ls180.v:6087.42-6087.95" + cell $and $and$ls180.v:6087$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6087$1421_Y + end + attribute \src "ls180.v:6087.41-6087.145" + cell $and $and$ls180.v:6087$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6087$1421_Y + connect \B $eq$ls180.v:6087$1422_Y + connect \Y $and$ls180.v:6087$1423_Y + end + attribute \src "ls180.v:6088.42-6088.98" + cell $and $and$ls180.v:6088$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6088$1424_Y + connect \Y $and$ls180.v:6088$1425_Y + end + attribute \src "ls180.v:6088.41-6088.148" + cell $and $and$ls180.v:6088$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6088$1425_Y + connect \B $eq$ls180.v:6088$1426_Y + connect \Y $and$ls180.v:6088$1427_Y + end + attribute \src "ls180.v:6090.42-6090.95" + cell $and $and$ls180.v:6090$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6090$1428_Y + end + attribute \src "ls180.v:6090.41-6090.145" + cell $and $and$ls180.v:6090$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6090$1428_Y + connect \B $eq$ls180.v:6090$1429_Y + connect \Y $and$ls180.v:6090$1430_Y + end + attribute \src "ls180.v:6091.42-6091.98" + cell $and $and$ls180.v:6091$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6091$1431_Y + connect \Y $and$ls180.v:6091$1432_Y + end + attribute \src "ls180.v:6091.41-6091.148" + cell $and $and$ls180.v:6091$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6091$1432_Y + connect \B $eq$ls180.v:6091$1433_Y + connect \Y $and$ls180.v:6091$1434_Y + end + attribute \src "ls180.v:6093.42-6093.95" + cell $and $and$ls180.v:6093$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6093$1435_Y + end + attribute \src "ls180.v:6093.41-6093.145" + cell $and $and$ls180.v:6093$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6093$1435_Y + connect \B $eq$ls180.v:6093$1436_Y + connect \Y $and$ls180.v:6093$1437_Y + end + attribute \src "ls180.v:6094.42-6094.98" + cell $and $and$ls180.v:6094$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6094$1438_Y + connect \Y $and$ls180.v:6094$1439_Y + end + attribute \src "ls180.v:6094.41-6094.148" + cell $and $and$ls180.v:6094$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6094$1439_Y + connect \B $eq$ls180.v:6094$1440_Y + connect \Y $and$ls180.v:6094$1441_Y + end + attribute \src "ls180.v:6096.42-6096.95" + cell $and $and$ls180.v:6096$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6096$1442_Y + end + attribute \src "ls180.v:6096.41-6096.145" + cell $and $and$ls180.v:6096$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6096$1442_Y + connect \B $eq$ls180.v:6096$1443_Y + connect \Y $and$ls180.v:6096$1444_Y + end + attribute \src "ls180.v:6097.42-6097.98" + cell $and $and$ls180.v:6097$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6097$1445_Y + connect \Y $and$ls180.v:6097$1446_Y + end + attribute \src "ls180.v:6097.41-6097.148" + cell $and $and$ls180.v:6097$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6097$1446_Y + connect \B $eq$ls180.v:6097$1447_Y + connect \Y $and$ls180.v:6097$1448_Y + end + attribute \src "ls180.v:6099.42-6099.95" + cell $and $and$ls180.v:6099$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6099$1449_Y + end + attribute \src "ls180.v:6099.41-6099.145" + cell $and $and$ls180.v:6099$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6099$1449_Y + connect \B $eq$ls180.v:6099$1450_Y + connect \Y $and$ls180.v:6099$1451_Y + end + attribute \src "ls180.v:6100.42-6100.98" + cell $and $and$ls180.v:6100$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6100$1452_Y + connect \Y $and$ls180.v:6100$1453_Y + end + attribute \src "ls180.v:6100.41-6100.148" + cell $and $and$ls180.v:6100$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6100$1453_Y + connect \B $eq$ls180.v:6100$1454_Y + connect \Y $and$ls180.v:6100$1455_Y + end + attribute \src "ls180.v:6102.42-6102.95" + cell $and $and$ls180.v:6102$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6102$1456_Y + end + attribute \src "ls180.v:6102.41-6102.145" + cell $and $and$ls180.v:6102$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6102$1456_Y + connect \B $eq$ls180.v:6102$1457_Y + connect \Y $and$ls180.v:6102$1458_Y + end + attribute \src "ls180.v:6103.42-6103.98" + cell $and $and$ls180.v:6103$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6103$1459_Y + connect \Y $and$ls180.v:6103$1460_Y + end + attribute \src "ls180.v:6103.41-6103.148" + cell $and $and$ls180.v:6103$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6103$1460_Y + connect \B $eq$ls180.v:6103$1461_Y + connect \Y $and$ls180.v:6103$1462_Y + end + attribute \src "ls180.v:6105.42-6105.95" + cell $and $and$ls180.v:6105$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6105$1463_Y + end + attribute \src "ls180.v:6105.41-6105.145" + cell $and $and$ls180.v:6105$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6105$1463_Y + connect \B $eq$ls180.v:6105$1464_Y + connect \Y $and$ls180.v:6105$1465_Y + end + attribute \src "ls180.v:6106.42-6106.98" + cell $and $and$ls180.v:6106$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6106$1466_Y + connect \Y $and$ls180.v:6106$1467_Y + end + attribute \src "ls180.v:6106.41-6106.148" + cell $and $and$ls180.v:6106$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6106$1467_Y + connect \B $eq$ls180.v:6106$1468_Y + connect \Y $and$ls180.v:6106$1469_Y + end + attribute \src "ls180.v:6108.44-6108.97" + cell $and $and$ls180.v:6108$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6108$1470_Y + end + attribute \src "ls180.v:6108.43-6108.147" + cell $and $and$ls180.v:6108$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6108$1470_Y + connect \B $eq$ls180.v:6108$1471_Y + connect \Y $and$ls180.v:6108$1472_Y + end + attribute \src "ls180.v:6109.44-6109.100" + cell $and $and$ls180.v:6109$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6109$1473_Y + connect \Y $and$ls180.v:6109$1474_Y + end + attribute \src "ls180.v:6109.43-6109.150" + cell $and $and$ls180.v:6109$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6109$1474_Y + connect \B $eq$ls180.v:6109$1475_Y + connect \Y $and$ls180.v:6109$1476_Y + end + attribute \src "ls180.v:6111.44-6111.97" + cell $and $and$ls180.v:6111$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6111$1477_Y + end + attribute \src "ls180.v:6111.43-6111.147" + cell $and $and$ls180.v:6111$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6111$1477_Y + connect \B $eq$ls180.v:6111$1478_Y + connect \Y $and$ls180.v:6111$1479_Y + end + attribute \src "ls180.v:6112.44-6112.100" + cell $and $and$ls180.v:6112$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6112$1480_Y + connect \Y $and$ls180.v:6112$1481_Y + end + attribute \src "ls180.v:6112.43-6112.150" + cell $and $and$ls180.v:6112$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6112$1481_Y + connect \B $eq$ls180.v:6112$1482_Y + connect \Y $and$ls180.v:6112$1483_Y + end + attribute \src "ls180.v:6114.44-6114.97" + cell $and $and$ls180.v:6114$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6114$1484_Y + end + attribute \src "ls180.v:6114.43-6114.148" + cell $and $and$ls180.v:6114$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6114$1484_Y + connect \B $eq$ls180.v:6114$1485_Y + connect \Y $and$ls180.v:6114$1486_Y + end + attribute \src "ls180.v:6115.44-6115.100" + cell $and $and$ls180.v:6115$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6115$1487_Y + connect \Y $and$ls180.v:6115$1488_Y + end + attribute \src "ls180.v:6115.43-6115.151" + cell $and $and$ls180.v:6115$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6115$1488_Y + connect \B $eq$ls180.v:6115$1489_Y + connect \Y $and$ls180.v:6115$1490_Y + end + attribute \src "ls180.v:6117.44-6117.97" + cell $and $and$ls180.v:6117$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6117$1491_Y + end + attribute \src "ls180.v:6117.43-6117.148" + cell $and $and$ls180.v:6117$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6117$1491_Y + connect \B $eq$ls180.v:6117$1492_Y + connect \Y $and$ls180.v:6117$1493_Y + end + attribute \src "ls180.v:6118.44-6118.100" + cell $and $and$ls180.v:6118$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6118$1494_Y + connect \Y $and$ls180.v:6118$1495_Y + end + attribute \src "ls180.v:6118.43-6118.151" + cell $and $and$ls180.v:6118$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6118$1495_Y + connect \B $eq$ls180.v:6118$1496_Y + connect \Y $and$ls180.v:6118$1497_Y + end + attribute \src "ls180.v:6120.44-6120.97" + cell $and $and$ls180.v:6120$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6120$1498_Y + end + attribute \src "ls180.v:6120.43-6120.148" + cell $and $and$ls180.v:6120$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6120$1498_Y + connect \B $eq$ls180.v:6120$1499_Y + connect \Y $and$ls180.v:6120$1500_Y + end + attribute \src "ls180.v:6121.44-6121.100" + cell $and $and$ls180.v:6121$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6121$1501_Y + connect \Y $and$ls180.v:6121$1502_Y + end + attribute \src "ls180.v:6121.43-6121.151" + cell $and $and$ls180.v:6121$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6121$1502_Y + connect \B $eq$ls180.v:6121$1503_Y + connect \Y $and$ls180.v:6121$1504_Y + end + attribute \src "ls180.v:6123.41-6123.94" + cell $and $and$ls180.v:6123$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6123$1505_Y + end + attribute \src "ls180.v:6123.40-6123.145" + cell $and $and$ls180.v:6123$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6123$1505_Y + connect \B $eq$ls180.v:6123$1506_Y + connect \Y $and$ls180.v:6123$1507_Y + end + attribute \src "ls180.v:6124.41-6124.97" + cell $and $and$ls180.v:6124$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6124$1508_Y + connect \Y $and$ls180.v:6124$1509_Y + end + attribute \src "ls180.v:6124.40-6124.148" + cell $and $and$ls180.v:6124$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6124$1509_Y + connect \B $eq$ls180.v:6124$1510_Y + connect \Y $and$ls180.v:6124$1511_Y + end + attribute \src "ls180.v:6126.42-6126.95" + cell $and $and$ls180.v:6126$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6126$1512_Y + end + attribute \src "ls180.v:6126.41-6126.146" + cell $and $and$ls180.v:6126$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6126$1512_Y + connect \B $eq$ls180.v:6126$1513_Y + connect \Y $and$ls180.v:6126$1514_Y + end + attribute \src "ls180.v:6127.42-6127.98" + cell $and $and$ls180.v:6127$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6127$1515_Y + connect \Y $and$ls180.v:6127$1516_Y + end + attribute \src "ls180.v:6127.41-6127.149" + cell $and $and$ls180.v:6127$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6127$1516_Y + connect \B $eq$ls180.v:6127$1517_Y + connect \Y $and$ls180.v:6127$1518_Y + end + attribute \src "ls180.v:6146.46-6146.99" + cell $and $and$ls180.v:6146$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6146$1520_Y + end + attribute \src "ls180.v:6146.45-6146.149" + cell $and $and$ls180.v:6146$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6146$1520_Y + connect \B $eq$ls180.v:6146$1521_Y + connect \Y $and$ls180.v:6146$1522_Y + end + attribute \src "ls180.v:6147.46-6147.102" + cell $and $and$ls180.v:6147$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6147$1523_Y + connect \Y $and$ls180.v:6147$1524_Y + end + attribute \src "ls180.v:6147.45-6147.152" + cell $and $and$ls180.v:6147$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6147$1524_Y + connect \B $eq$ls180.v:6147$1525_Y + connect \Y $and$ls180.v:6147$1526_Y + end + attribute \src "ls180.v:6149.46-6149.99" + cell $and $and$ls180.v:6149$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6149$1527_Y + end + attribute \src "ls180.v:6149.45-6149.149" + cell $and $and$ls180.v:6149$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6149$1527_Y + connect \B $eq$ls180.v:6149$1528_Y + connect \Y $and$ls180.v:6149$1529_Y + end + attribute \src "ls180.v:6150.46-6150.102" + cell $and $and$ls180.v:6150$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6150$1530_Y + connect \Y $and$ls180.v:6150$1531_Y + end + attribute \src "ls180.v:6150.45-6150.152" + cell $and $and$ls180.v:6150$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6150$1531_Y + connect \B $eq$ls180.v:6150$1532_Y + connect \Y $and$ls180.v:6150$1533_Y + end + attribute \src "ls180.v:6152.46-6152.99" + cell $and $and$ls180.v:6152$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6152$1534_Y + end + attribute \src "ls180.v:6152.45-6152.149" + cell $and $and$ls180.v:6152$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6152$1534_Y + connect \B $eq$ls180.v:6152$1535_Y + connect \Y $and$ls180.v:6152$1536_Y + end + attribute \src "ls180.v:6153.46-6153.102" + cell $and $and$ls180.v:6153$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6153$1537_Y + connect \Y $and$ls180.v:6153$1538_Y + end + attribute \src "ls180.v:6153.45-6153.152" + cell $and $and$ls180.v:6153$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6153$1538_Y + connect \B $eq$ls180.v:6153$1539_Y + connect \Y $and$ls180.v:6153$1540_Y + end + attribute \src "ls180.v:6155.46-6155.99" + cell $and $and$ls180.v:6155$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6155$1541_Y + end + attribute \src "ls180.v:6155.45-6155.149" + cell $and $and$ls180.v:6155$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6155$1541_Y + connect \B $eq$ls180.v:6155$1542_Y + connect \Y $and$ls180.v:6155$1543_Y + end + attribute \src "ls180.v:6156.46-6156.102" + cell $and $and$ls180.v:6156$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6156$1544_Y + connect \Y $and$ls180.v:6156$1545_Y + end + attribute \src "ls180.v:6156.45-6156.152" + cell $and $and$ls180.v:6156$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6156$1545_Y + connect \B $eq$ls180.v:6156$1546_Y + connect \Y $and$ls180.v:6156$1547_Y + end + attribute \src "ls180.v:6158.45-6158.98" + cell $and $and$ls180.v:6158$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6158$1548_Y + end + attribute \src "ls180.v:6158.44-6158.148" + cell $and $and$ls180.v:6158$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1548_Y + connect \B $eq$ls180.v:6158$1549_Y + connect \Y $and$ls180.v:6158$1550_Y + end + attribute \src "ls180.v:6159.45-6159.101" + cell $and $and$ls180.v:6159$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6159$1551_Y + connect \Y $and$ls180.v:6159$1552_Y + end + attribute \src "ls180.v:6159.44-6159.151" + cell $and $and$ls180.v:6159$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6159$1552_Y + connect \B $eq$ls180.v:6159$1553_Y + connect \Y $and$ls180.v:6159$1554_Y + end + attribute \src "ls180.v:6161.45-6161.98" + cell $and $and$ls180.v:6161$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6161$1555_Y + end + attribute \src "ls180.v:6161.44-6161.148" + cell $and $and$ls180.v:6161$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6161$1555_Y + connect \B $eq$ls180.v:6161$1556_Y + connect \Y $and$ls180.v:6161$1557_Y + end + attribute \src "ls180.v:6162.45-6162.101" + cell $and $and$ls180.v:6162$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6162$1558_Y + connect \Y $and$ls180.v:6162$1559_Y + end + attribute \src "ls180.v:6162.44-6162.151" + cell $and $and$ls180.v:6162$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6162$1559_Y + connect \B $eq$ls180.v:6162$1560_Y + connect \Y $and$ls180.v:6162$1561_Y + end + attribute \src "ls180.v:6164.45-6164.98" + cell $and $and$ls180.v:6164$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6164$1562_Y + end + attribute \src "ls180.v:6164.44-6164.148" + cell $and $and$ls180.v:6164$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6164$1562_Y + connect \B $eq$ls180.v:6164$1563_Y + connect \Y $and$ls180.v:6164$1564_Y + end + attribute \src "ls180.v:6165.45-6165.101" + cell $and $and$ls180.v:6165$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6165$1565_Y + connect \Y $and$ls180.v:6165$1566_Y + end + attribute \src "ls180.v:6165.44-6165.151" + cell $and $and$ls180.v:6165$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6165$1566_Y + connect \B $eq$ls180.v:6165$1567_Y + connect \Y $and$ls180.v:6165$1568_Y + end + attribute \src "ls180.v:6167.45-6167.98" + cell $and $and$ls180.v:6167$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6167$1569_Y + end + attribute \src "ls180.v:6167.44-6167.148" + cell $and $and$ls180.v:6167$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6167$1569_Y + connect \B $eq$ls180.v:6167$1570_Y + connect \Y $and$ls180.v:6167$1571_Y + end + attribute \src "ls180.v:6168.45-6168.101" + cell $and $and$ls180.v:6168$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6168$1572_Y + connect \Y $and$ls180.v:6168$1573_Y + end + attribute \src "ls180.v:6168.44-6168.151" + cell $and $and$ls180.v:6168$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6168$1573_Y + connect \B $eq$ls180.v:6168$1574_Y + connect \Y $and$ls180.v:6168$1575_Y + end + attribute \src "ls180.v:6170.36-6170.89" + cell $and $and$ls180.v:6170$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6170$1576_Y + end + attribute \src "ls180.v:6170.35-6170.139" + cell $and $and$ls180.v:6170$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6170$1576_Y + connect \B $eq$ls180.v:6170$1577_Y + connect \Y $and$ls180.v:6170$1578_Y + end + attribute \src "ls180.v:6171.36-6171.92" + cell $and $and$ls180.v:6171$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6171$1579_Y + connect \Y $and$ls180.v:6171$1580_Y + end + attribute \src "ls180.v:6171.35-6171.142" + cell $and $and$ls180.v:6171$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6171$1580_Y + connect \B $eq$ls180.v:6171$1581_Y + connect \Y $and$ls180.v:6171$1582_Y + end + attribute \src "ls180.v:6173.47-6173.100" + cell $and $and$ls180.v:6173$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6173$1583_Y + end + attribute \src "ls180.v:6173.46-6173.150" + cell $and $and$ls180.v:6173$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6173$1583_Y + connect \B $eq$ls180.v:6173$1584_Y + connect \Y $and$ls180.v:6173$1585_Y + end + attribute \src "ls180.v:6174.47-6174.103" + cell $and $and$ls180.v:6174$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6174$1586_Y + connect \Y $and$ls180.v:6174$1587_Y + end + attribute \src "ls180.v:6174.46-6174.153" + cell $and $and$ls180.v:6174$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6174$1587_Y + connect \B $eq$ls180.v:6174$1588_Y + connect \Y $and$ls180.v:6174$1589_Y + end + attribute \src "ls180.v:6176.47-6176.100" + cell $and $and$ls180.v:6176$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6176$1590_Y + end + attribute \src "ls180.v:6176.46-6176.151" + cell $and $and$ls180.v:6176$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6176$1590_Y + connect \B $eq$ls180.v:6176$1591_Y + connect \Y $and$ls180.v:6176$1592_Y + end + attribute \src "ls180.v:6177.47-6177.103" + cell $and $and$ls180.v:6177$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6177$1593_Y + connect \Y $and$ls180.v:6177$1594_Y + end + attribute \src "ls180.v:6177.46-6177.154" + cell $and $and$ls180.v:6177$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6177$1594_Y + connect \B $eq$ls180.v:6177$1595_Y + connect \Y $and$ls180.v:6177$1596_Y + end + attribute \src "ls180.v:6179.47-6179.100" + cell $and $and$ls180.v:6179$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6179$1597_Y + end + attribute \src "ls180.v:6179.46-6179.151" + cell $and $and$ls180.v:6179$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6179$1597_Y + connect \B $eq$ls180.v:6179$1598_Y + connect \Y $and$ls180.v:6179$1599_Y + end + attribute \src "ls180.v:6180.47-6180.103" + cell $and $and$ls180.v:6180$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6180$1600_Y + connect \Y $and$ls180.v:6180$1601_Y + end + attribute \src "ls180.v:6180.46-6180.154" + cell $and $and$ls180.v:6180$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6180$1601_Y + connect \B $eq$ls180.v:6180$1602_Y + connect \Y $and$ls180.v:6180$1603_Y + end + attribute \src "ls180.v:6182.47-6182.100" + cell $and $and$ls180.v:6182$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6182$1604_Y + end + attribute \src "ls180.v:6182.46-6182.151" + cell $and $and$ls180.v:6182$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6182$1604_Y + connect \B $eq$ls180.v:6182$1605_Y + connect \Y $and$ls180.v:6182$1606_Y + end + attribute \src "ls180.v:6183.47-6183.103" + cell $and $and$ls180.v:6183$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6183$1607_Y + connect \Y $and$ls180.v:6183$1608_Y + end + attribute \src "ls180.v:6183.46-6183.154" + cell $and $and$ls180.v:6183$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6183$1608_Y + connect \B $eq$ls180.v:6183$1609_Y + connect \Y $and$ls180.v:6183$1610_Y + end + attribute \src "ls180.v:6185.47-6185.100" + cell $and $and$ls180.v:6185$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6185$1611_Y + end + attribute \src "ls180.v:6185.46-6185.151" + cell $and $and$ls180.v:6185$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6185$1611_Y + connect \B $eq$ls180.v:6185$1612_Y + connect \Y $and$ls180.v:6185$1613_Y + end + attribute \src "ls180.v:6186.47-6186.103" + cell $and $and$ls180.v:6186$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6186$1614_Y + connect \Y $and$ls180.v:6186$1615_Y + end + attribute \src "ls180.v:6186.46-6186.154" + cell $and $and$ls180.v:6186$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6186$1615_Y + connect \B $eq$ls180.v:6186$1616_Y + connect \Y $and$ls180.v:6186$1617_Y + end + attribute \src "ls180.v:6188.47-6188.100" + cell $and $and$ls180.v:6188$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6188$1618_Y + end + attribute \src "ls180.v:6188.46-6188.151" + cell $and $and$ls180.v:6188$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6188$1618_Y + connect \B $eq$ls180.v:6188$1619_Y + connect \Y $and$ls180.v:6188$1620_Y + end + attribute \src "ls180.v:6189.47-6189.103" + cell $and $and$ls180.v:6189$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6189$1621_Y + connect \Y $and$ls180.v:6189$1622_Y + end + attribute \src "ls180.v:6189.46-6189.154" + cell $and $and$ls180.v:6189$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6189$1622_Y + connect \B $eq$ls180.v:6189$1623_Y + connect \Y $and$ls180.v:6189$1624_Y + end + attribute \src "ls180.v:6191.46-6191.99" + cell $and $and$ls180.v:6191$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6191$1625_Y + end + attribute \src "ls180.v:6191.45-6191.150" + cell $and $and$ls180.v:6191$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6191$1625_Y + connect \B $eq$ls180.v:6191$1626_Y + connect \Y $and$ls180.v:6191$1627_Y + end + attribute \src "ls180.v:6192.46-6192.102" + cell $and $and$ls180.v:6192$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6192$1628_Y + connect \Y $and$ls180.v:6192$1629_Y + end + attribute \src "ls180.v:6192.45-6192.153" + cell $and $and$ls180.v:6192$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6192$1629_Y + connect \B $eq$ls180.v:6192$1630_Y + connect \Y $and$ls180.v:6192$1631_Y + end + attribute \src "ls180.v:6194.46-6194.99" + cell $and $and$ls180.v:6194$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6194$1632_Y + end + attribute \src "ls180.v:6194.45-6194.150" + cell $and $and$ls180.v:6194$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6194$1632_Y + connect \B $eq$ls180.v:6194$1633_Y + connect \Y $and$ls180.v:6194$1634_Y + end + attribute \src "ls180.v:6195.46-6195.102" + cell $and $and$ls180.v:6195$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6195$1635_Y + connect \Y $and$ls180.v:6195$1636_Y + end + attribute \src "ls180.v:6195.45-6195.153" + cell $and $and$ls180.v:6195$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6195$1636_Y + connect \B $eq$ls180.v:6195$1637_Y + connect \Y $and$ls180.v:6195$1638_Y + end + attribute \src "ls180.v:6197.46-6197.99" + cell $and $and$ls180.v:6197$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6197$1639_Y + end + attribute \src "ls180.v:6197.45-6197.150" + cell $and $and$ls180.v:6197$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6197$1639_Y + connect \B $eq$ls180.v:6197$1640_Y + connect \Y $and$ls180.v:6197$1641_Y + end + attribute \src "ls180.v:6198.46-6198.102" + cell $and $and$ls180.v:6198$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6198$1642_Y + connect \Y $and$ls180.v:6198$1643_Y + end + attribute \src "ls180.v:6198.45-6198.153" + cell $and $and$ls180.v:6198$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6198$1643_Y + connect \B $eq$ls180.v:6198$1644_Y + connect \Y $and$ls180.v:6198$1645_Y + end + attribute \src "ls180.v:6200.46-6200.99" + cell $and $and$ls180.v:6200$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6200$1646_Y + end + attribute \src "ls180.v:6200.45-6200.150" + cell $and $and$ls180.v:6200$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6200$1646_Y + connect \B $eq$ls180.v:6200$1647_Y + connect \Y $and$ls180.v:6200$1648_Y + end + attribute \src "ls180.v:6201.46-6201.102" + cell $and $and$ls180.v:6201$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6201$1649_Y + connect \Y $and$ls180.v:6201$1650_Y + end + attribute \src "ls180.v:6201.45-6201.153" + cell $and $and$ls180.v:6201$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6201$1650_Y + connect \B $eq$ls180.v:6201$1651_Y + connect \Y $and$ls180.v:6201$1652_Y + end + attribute \src "ls180.v:6203.46-6203.99" + cell $and $and$ls180.v:6203$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6203$1653_Y + end + attribute \src "ls180.v:6203.45-6203.150" + cell $and $and$ls180.v:6203$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6203$1653_Y + connect \B $eq$ls180.v:6203$1654_Y + connect \Y $and$ls180.v:6203$1655_Y + end + attribute \src "ls180.v:6204.46-6204.102" + cell $and $and$ls180.v:6204$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6204$1656_Y + connect \Y $and$ls180.v:6204$1657_Y + end + attribute \src "ls180.v:6204.45-6204.153" + cell $and $and$ls180.v:6204$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6204$1657_Y + connect \B $eq$ls180.v:6204$1658_Y + connect \Y $and$ls180.v:6204$1659_Y + end + attribute \src "ls180.v:6206.46-6206.99" + cell $and $and$ls180.v:6206$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6206$1660_Y + end + attribute \src "ls180.v:6206.45-6206.150" + cell $and $and$ls180.v:6206$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6206$1660_Y + connect \B $eq$ls180.v:6206$1661_Y + connect \Y $and$ls180.v:6206$1662_Y + end + attribute \src "ls180.v:6207.46-6207.102" + cell $and $and$ls180.v:6207$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6207$1663_Y + connect \Y $and$ls180.v:6207$1664_Y + end + attribute \src "ls180.v:6207.45-6207.153" + cell $and $and$ls180.v:6207$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6207$1664_Y + connect \B $eq$ls180.v:6207$1665_Y + connect \Y $and$ls180.v:6207$1666_Y + end + attribute \src "ls180.v:6209.46-6209.99" + cell $and $and$ls180.v:6209$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6209$1667_Y + end + attribute \src "ls180.v:6209.45-6209.150" + cell $and $and$ls180.v:6209$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6209$1667_Y + connect \B $eq$ls180.v:6209$1668_Y + connect \Y $and$ls180.v:6209$1669_Y + end + attribute \src "ls180.v:6210.46-6210.102" + cell $and $and$ls180.v:6210$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6210$1670_Y + connect \Y $and$ls180.v:6210$1671_Y + end + attribute \src "ls180.v:6210.45-6210.153" + cell $and $and$ls180.v:6210$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6210$1671_Y + connect \B $eq$ls180.v:6210$1672_Y + connect \Y $and$ls180.v:6210$1673_Y + end + attribute \src "ls180.v:6212.46-6212.99" + cell $and $and$ls180.v:6212$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6212$1674_Y + end + attribute \src "ls180.v:6212.45-6212.150" + cell $and $and$ls180.v:6212$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6212$1674_Y + connect \B $eq$ls180.v:6212$1675_Y + connect \Y $and$ls180.v:6212$1676_Y + end + attribute \src "ls180.v:6213.46-6213.102" + cell $and $and$ls180.v:6213$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6213$1677_Y + connect \Y $and$ls180.v:6213$1678_Y + end + attribute \src "ls180.v:6213.45-6213.153" + cell $and $and$ls180.v:6213$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6213$1678_Y + connect \B $eq$ls180.v:6213$1679_Y + connect \Y $and$ls180.v:6213$1680_Y + end + attribute \src "ls180.v:6215.46-6215.99" + cell $and $and$ls180.v:6215$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6215$1681_Y + end + attribute \src "ls180.v:6215.45-6215.150" + cell $and $and$ls180.v:6215$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6215$1681_Y + connect \B $eq$ls180.v:6215$1682_Y + connect \Y $and$ls180.v:6215$1683_Y + end + attribute \src "ls180.v:6216.46-6216.102" + cell $and $and$ls180.v:6216$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6216$1684_Y + connect \Y $and$ls180.v:6216$1685_Y + end + attribute \src "ls180.v:6216.45-6216.153" + cell $and $and$ls180.v:6216$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6216$1685_Y + connect \B $eq$ls180.v:6216$1686_Y + connect \Y $and$ls180.v:6216$1687_Y + end + attribute \src "ls180.v:6218.46-6218.99" + cell $and $and$ls180.v:6218$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6218$1688_Y + end + attribute \src "ls180.v:6218.45-6218.150" + cell $and $and$ls180.v:6218$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6218$1688_Y + connect \B $eq$ls180.v:6218$1689_Y + connect \Y $and$ls180.v:6218$1690_Y + end + attribute \src "ls180.v:6219.46-6219.102" + cell $and $and$ls180.v:6219$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6219$1691_Y + connect \Y $and$ls180.v:6219$1692_Y + end + attribute \src "ls180.v:6219.45-6219.153" + cell $and $and$ls180.v:6219$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6219$1692_Y + connect \B $eq$ls180.v:6219$1693_Y + connect \Y $and$ls180.v:6219$1694_Y + end + attribute \src "ls180.v:6221.42-6221.95" + cell $and $and$ls180.v:6221$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6221$1695_Y + end + attribute \src "ls180.v:6221.41-6221.146" + cell $and $and$ls180.v:6221$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6221$1695_Y + connect \B $eq$ls180.v:6221$1696_Y + connect \Y $and$ls180.v:6221$1697_Y + end + attribute \src "ls180.v:6222.42-6222.98" + cell $and $and$ls180.v:6222$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6222$1698_Y + connect \Y $and$ls180.v:6222$1699_Y + end + attribute \src "ls180.v:6222.41-6222.149" + cell $and $and$ls180.v:6222$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6222$1699_Y + connect \B $eq$ls180.v:6222$1700_Y + connect \Y $and$ls180.v:6222$1701_Y + end + attribute \src "ls180.v:6224.43-6224.96" + cell $and $and$ls180.v:6224$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6224$1702_Y + end + attribute \src "ls180.v:6224.42-6224.147" + cell $and $and$ls180.v:6224$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6224$1702_Y + connect \B $eq$ls180.v:6224$1703_Y + connect \Y $and$ls180.v:6224$1704_Y + end + attribute \src "ls180.v:6225.43-6225.99" + cell $and $and$ls180.v:6225$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6225$1705_Y + connect \Y $and$ls180.v:6225$1706_Y + end + attribute \src "ls180.v:6225.42-6225.150" + cell $and $and$ls180.v:6225$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6225$1706_Y + connect \B $eq$ls180.v:6225$1707_Y + connect \Y $and$ls180.v:6225$1708_Y + end + attribute \src "ls180.v:6227.46-6227.99" + cell $and $and$ls180.v:6227$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6227$1709_Y + end + attribute \src "ls180.v:6227.45-6227.150" + cell $and $and$ls180.v:6227$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6227$1709_Y + connect \B $eq$ls180.v:6227$1710_Y + connect \Y $and$ls180.v:6227$1711_Y + end + attribute \src "ls180.v:6228.46-6228.102" + cell $and $and$ls180.v:6228$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6228$1712_Y + connect \Y $and$ls180.v:6228$1713_Y + end + attribute \src "ls180.v:6228.45-6228.153" + cell $and $and$ls180.v:6228$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6228$1713_Y + connect \B $eq$ls180.v:6228$1714_Y + connect \Y $and$ls180.v:6228$1715_Y + end + attribute \src "ls180.v:6230.46-6230.99" + cell $and $and$ls180.v:6230$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6230$1716_Y + end + attribute \src "ls180.v:6230.45-6230.150" + cell $and $and$ls180.v:6230$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6230$1716_Y + connect \B $eq$ls180.v:6230$1717_Y + connect \Y $and$ls180.v:6230$1718_Y + end + attribute \src "ls180.v:6231.46-6231.102" + cell $and $and$ls180.v:6231$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6231$1719_Y + connect \Y $and$ls180.v:6231$1720_Y + end + attribute \src "ls180.v:6231.45-6231.153" + cell $and $and$ls180.v:6231$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6231$1720_Y + connect \B $eq$ls180.v:6231$1721_Y + connect \Y $and$ls180.v:6231$1722_Y + end + attribute \src "ls180.v:6233.45-6233.98" + cell $and $and$ls180.v:6233$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6233$1723_Y + end + attribute \src "ls180.v:6233.44-6233.149" + cell $and $and$ls180.v:6233$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6233$1723_Y + connect \B $eq$ls180.v:6233$1724_Y + connect \Y $and$ls180.v:6233$1725_Y + end + attribute \src "ls180.v:6234.45-6234.101" + cell $and $and$ls180.v:6234$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6234$1726_Y + connect \Y $and$ls180.v:6234$1727_Y + end + attribute \src "ls180.v:6234.44-6234.152" + cell $and $and$ls180.v:6234$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6234$1727_Y + connect \B $eq$ls180.v:6234$1728_Y + connect \Y $and$ls180.v:6234$1729_Y + end + attribute \src "ls180.v:6236.45-6236.98" + cell $and $and$ls180.v:6236$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6236$1730_Y + end + attribute \src "ls180.v:6236.44-6236.149" + cell $and $and$ls180.v:6236$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6236$1730_Y + connect \B $eq$ls180.v:6236$1731_Y + connect \Y $and$ls180.v:6236$1732_Y + end + attribute \src "ls180.v:6237.45-6237.101" + cell $and $and$ls180.v:6237$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6237$1733_Y + connect \Y $and$ls180.v:6237$1734_Y + end + attribute \src "ls180.v:6237.44-6237.152" + cell $and $and$ls180.v:6237$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6237$1734_Y + connect \B $eq$ls180.v:6237$1735_Y + connect \Y $and$ls180.v:6237$1736_Y + end + attribute \src "ls180.v:6239.45-6239.98" + cell $and $and$ls180.v:6239$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6239$1737_Y + end + attribute \src "ls180.v:6239.44-6239.149" + cell $and $and$ls180.v:6239$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6239$1737_Y + connect \B $eq$ls180.v:6239$1738_Y + connect \Y $and$ls180.v:6239$1739_Y + end + attribute \src "ls180.v:6240.45-6240.101" + cell $and $and$ls180.v:6240$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6240$1740_Y + connect \Y $and$ls180.v:6240$1741_Y + end + attribute \src "ls180.v:6240.44-6240.152" + cell $and $and$ls180.v:6240$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6240$1741_Y + connect \B $eq$ls180.v:6240$1742_Y + connect \Y $and$ls180.v:6240$1743_Y + end + attribute \src "ls180.v:6242.45-6242.98" + cell $and $and$ls180.v:6242$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6242$1744_Y + end + attribute \src "ls180.v:6242.44-6242.149" + cell $and $and$ls180.v:6242$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6242$1744_Y + connect \B $eq$ls180.v:6242$1745_Y + connect \Y $and$ls180.v:6242$1746_Y + end + attribute \src "ls180.v:6243.45-6243.101" + cell $and $and$ls180.v:6243$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6243$1747_Y + connect \Y $and$ls180.v:6243$1748_Y + end + attribute \src "ls180.v:6243.44-6243.152" + cell $and $and$ls180.v:6243$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6243$1748_Y + connect \B $eq$ls180.v:6243$1749_Y + connect \Y $and$ls180.v:6243$1750_Y + end + attribute \src "ls180.v:6281.42-6281.95" + cell $and $and$ls180.v:6281$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6281$1752_Y + end + attribute \src "ls180.v:6281.41-6281.145" + cell $and $and$ls180.v:6281$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6281$1752_Y + connect \B $eq$ls180.v:6281$1753_Y + connect \Y $and$ls180.v:6281$1754_Y + end + attribute \src "ls180.v:6282.42-6282.98" + cell $and $and$ls180.v:6282$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6282$1755_Y + connect \Y $and$ls180.v:6282$1756_Y + end + attribute \src "ls180.v:6282.41-6282.148" + cell $and $and$ls180.v:6282$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6282$1756_Y + connect \B $eq$ls180.v:6282$1757_Y + connect \Y $and$ls180.v:6282$1758_Y + end + attribute \src "ls180.v:6284.42-6284.95" + cell $and $and$ls180.v:6284$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6284$1759_Y + end + attribute \src "ls180.v:6284.41-6284.145" + cell $and $and$ls180.v:6284$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6284$1759_Y + connect \B $eq$ls180.v:6284$1760_Y + connect \Y $and$ls180.v:6284$1761_Y + end + attribute \src "ls180.v:6285.42-6285.98" + cell $and $and$ls180.v:6285$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6285$1762_Y + connect \Y $and$ls180.v:6285$1763_Y + end + attribute \src "ls180.v:6285.41-6285.148" + cell $and $and$ls180.v:6285$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6285$1763_Y + connect \B $eq$ls180.v:6285$1764_Y + connect \Y $and$ls180.v:6285$1765_Y + end + attribute \src "ls180.v:6287.42-6287.95" + cell $and $and$ls180.v:6287$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6287$1766_Y + end + attribute \src "ls180.v:6287.41-6287.145" + cell $and $and$ls180.v:6287$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6287$1766_Y + connect \B $eq$ls180.v:6287$1767_Y + connect \Y $and$ls180.v:6287$1768_Y + end + attribute \src "ls180.v:6288.42-6288.98" + cell $and $and$ls180.v:6288$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6288$1769_Y + connect \Y $and$ls180.v:6288$1770_Y + end + attribute \src "ls180.v:6288.41-6288.148" + cell $and $and$ls180.v:6288$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6288$1770_Y + connect \B $eq$ls180.v:6288$1771_Y + connect \Y $and$ls180.v:6288$1772_Y + end + attribute \src "ls180.v:6290.42-6290.95" + cell $and $and$ls180.v:6290$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6290$1773_Y + end + attribute \src "ls180.v:6290.41-6290.145" + cell $and $and$ls180.v:6290$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6290$1773_Y + connect \B $eq$ls180.v:6290$1774_Y + connect \Y $and$ls180.v:6290$1775_Y + end + attribute \src "ls180.v:6291.42-6291.98" + cell $and $and$ls180.v:6291$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6291$1776_Y + connect \Y $and$ls180.v:6291$1777_Y + end + attribute \src "ls180.v:6291.41-6291.148" + cell $and $and$ls180.v:6291$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6291$1777_Y + connect \B $eq$ls180.v:6291$1778_Y + connect \Y $and$ls180.v:6291$1779_Y + end + attribute \src "ls180.v:6293.42-6293.95" + cell $and $and$ls180.v:6293$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6293$1780_Y + end + attribute \src "ls180.v:6293.41-6293.145" + cell $and $and$ls180.v:6293$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6293$1780_Y + connect \B $eq$ls180.v:6293$1781_Y + connect \Y $and$ls180.v:6293$1782_Y + end + attribute \src "ls180.v:6294.42-6294.98" + cell $and $and$ls180.v:6294$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6294$1783_Y + connect \Y $and$ls180.v:6294$1784_Y + end + attribute \src "ls180.v:6294.41-6294.148" + cell $and $and$ls180.v:6294$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6294$1784_Y + connect \B $eq$ls180.v:6294$1785_Y + connect \Y $and$ls180.v:6294$1786_Y + end + attribute \src "ls180.v:6296.42-6296.95" + cell $and $and$ls180.v:6296$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6296$1787_Y + end + attribute \src "ls180.v:6296.41-6296.145" + cell $and $and$ls180.v:6296$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6296$1787_Y + connect \B $eq$ls180.v:6296$1788_Y + connect \Y $and$ls180.v:6296$1789_Y + end + attribute \src "ls180.v:6297.42-6297.98" + cell $and $and$ls180.v:6297$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6297$1790_Y + connect \Y $and$ls180.v:6297$1791_Y + end + attribute \src "ls180.v:6297.41-6297.148" + cell $and $and$ls180.v:6297$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6297$1791_Y + connect \B $eq$ls180.v:6297$1792_Y + connect \Y $and$ls180.v:6297$1793_Y + end + attribute \src "ls180.v:6299.42-6299.95" + cell $and $and$ls180.v:6299$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6299$1794_Y + end + attribute \src "ls180.v:6299.41-6299.145" + cell $and $and$ls180.v:6299$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6299$1794_Y + connect \B $eq$ls180.v:6299$1795_Y + connect \Y $and$ls180.v:6299$1796_Y + end + attribute \src "ls180.v:6300.42-6300.98" + cell $and $and$ls180.v:6300$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6300$1797_Y + connect \Y $and$ls180.v:6300$1798_Y + end + attribute \src "ls180.v:6300.41-6300.148" + cell $and $and$ls180.v:6300$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6300$1798_Y + connect \B $eq$ls180.v:6300$1799_Y + connect \Y $and$ls180.v:6300$1800_Y + end + attribute \src "ls180.v:6302.42-6302.95" + cell $and $and$ls180.v:6302$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6302$1801_Y + end + attribute \src "ls180.v:6302.41-6302.145" + cell $and $and$ls180.v:6302$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6302$1801_Y + connect \B $eq$ls180.v:6302$1802_Y + connect \Y $and$ls180.v:6302$1803_Y + end + attribute \src "ls180.v:6303.42-6303.98" + cell $and $and$ls180.v:6303$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6303$1804_Y + connect \Y $and$ls180.v:6303$1805_Y + end + attribute \src "ls180.v:6303.41-6303.148" + cell $and $and$ls180.v:6303$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6303$1805_Y + connect \B $eq$ls180.v:6303$1806_Y + connect \Y $and$ls180.v:6303$1807_Y + end + attribute \src "ls180.v:6305.44-6305.97" + cell $and $and$ls180.v:6305$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6305$1808_Y + end + attribute \src "ls180.v:6305.43-6305.147" + cell $and $and$ls180.v:6305$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6305$1808_Y + connect \B $eq$ls180.v:6305$1809_Y + connect \Y $and$ls180.v:6305$1810_Y + end + attribute \src "ls180.v:6306.44-6306.100" + cell $and $and$ls180.v:6306$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6306$1811_Y + connect \Y $and$ls180.v:6306$1812_Y + end + attribute \src "ls180.v:6306.43-6306.150" + cell $and $and$ls180.v:6306$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$1812_Y + connect \B $eq$ls180.v:6306$1813_Y + connect \Y $and$ls180.v:6306$1814_Y + end + attribute \src "ls180.v:6308.44-6308.97" + cell $and $and$ls180.v:6308$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6308$1815_Y + end + attribute \src "ls180.v:6308.43-6308.147" + cell $and $and$ls180.v:6308$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6308$1815_Y + connect \B $eq$ls180.v:6308$1816_Y + connect \Y $and$ls180.v:6308$1817_Y + end + attribute \src "ls180.v:6309.44-6309.100" + cell $and $and$ls180.v:6309$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6309$1818_Y + connect \Y $and$ls180.v:6309$1819_Y + end + attribute \src "ls180.v:6309.43-6309.150" + cell $and $and$ls180.v:6309$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$1819_Y + connect \B $eq$ls180.v:6309$1820_Y + connect \Y $and$ls180.v:6309$1821_Y + end + attribute \src "ls180.v:6311.44-6311.97" + cell $and $and$ls180.v:6311$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6311$1822_Y + end + attribute \src "ls180.v:6311.43-6311.148" + cell $and $and$ls180.v:6311$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6311$1822_Y + connect \B $eq$ls180.v:6311$1823_Y + connect \Y $and$ls180.v:6311$1824_Y + end + attribute \src "ls180.v:6312.44-6312.100" + cell $and $and$ls180.v:6312$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6312$1825_Y + connect \Y $and$ls180.v:6312$1826_Y + end + attribute \src "ls180.v:6312.43-6312.151" + cell $and $and$ls180.v:6312$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6312$1826_Y + connect \B $eq$ls180.v:6312$1827_Y + connect \Y $and$ls180.v:6312$1828_Y + end + attribute \src "ls180.v:6314.44-6314.97" + cell $and $and$ls180.v:6314$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6314$1829_Y + end + attribute \src "ls180.v:6314.43-6314.148" + cell $and $and$ls180.v:6314$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6314$1829_Y + connect \B $eq$ls180.v:6314$1830_Y + connect \Y $and$ls180.v:6314$1831_Y + end + attribute \src "ls180.v:6315.44-6315.100" + cell $and $and$ls180.v:6315$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6315$1832_Y + connect \Y $and$ls180.v:6315$1833_Y + end + attribute \src "ls180.v:6315.43-6315.151" + cell $and $and$ls180.v:6315$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6315$1833_Y + connect \B $eq$ls180.v:6315$1834_Y + connect \Y $and$ls180.v:6315$1835_Y + end + attribute \src "ls180.v:6317.44-6317.97" + cell $and $and$ls180.v:6317$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6317$1836_Y + end + attribute \src "ls180.v:6317.43-6317.148" + cell $and $and$ls180.v:6317$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6317$1836_Y + connect \B $eq$ls180.v:6317$1837_Y + connect \Y $and$ls180.v:6317$1838_Y + end + attribute \src "ls180.v:6318.44-6318.100" + cell $and $and$ls180.v:6318$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6318$1839_Y + connect \Y $and$ls180.v:6318$1840_Y + end + attribute \src "ls180.v:6318.43-6318.151" + cell $and $and$ls180.v:6318$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6318$1840_Y + connect \B $eq$ls180.v:6318$1841_Y + connect \Y $and$ls180.v:6318$1842_Y + end + attribute \src "ls180.v:6320.41-6320.94" + cell $and $and$ls180.v:6320$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6320$1843_Y + end + attribute \src "ls180.v:6320.40-6320.145" + cell $and $and$ls180.v:6320$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6320$1843_Y + connect \B $eq$ls180.v:6320$1844_Y + connect \Y $and$ls180.v:6320$1845_Y + end + attribute \src "ls180.v:6321.41-6321.97" + cell $and $and$ls180.v:6321$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6321$1846_Y + connect \Y $and$ls180.v:6321$1847_Y + end + attribute \src "ls180.v:6321.40-6321.148" + cell $and $and$ls180.v:6321$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6321$1847_Y + connect \B $eq$ls180.v:6321$1848_Y + connect \Y $and$ls180.v:6321$1849_Y + end + attribute \src "ls180.v:6323.42-6323.95" + cell $and $and$ls180.v:6323$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6323$1850_Y + end + attribute \src "ls180.v:6323.41-6323.146" + cell $and $and$ls180.v:6323$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6323$1850_Y + connect \B $eq$ls180.v:6323$1851_Y + connect \Y $and$ls180.v:6323$1852_Y + end + attribute \src "ls180.v:6324.42-6324.98" + cell $and $and$ls180.v:6324$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6324$1853_Y + connect \Y $and$ls180.v:6324$1854_Y + end + attribute \src "ls180.v:6324.41-6324.149" + cell $and $and$ls180.v:6324$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6324$1854_Y + connect \B $eq$ls180.v:6324$1855_Y + connect \Y $and$ls180.v:6324$1856_Y + end + attribute \src "ls180.v:6326.44-6326.97" + cell $and $and$ls180.v:6326$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6326$1857_Y + end + attribute \src "ls180.v:6326.43-6326.148" + cell $and $and$ls180.v:6326$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6326$1857_Y + connect \B $eq$ls180.v:6326$1858_Y + connect \Y $and$ls180.v:6326$1859_Y + end + attribute \src "ls180.v:6327.44-6327.100" + cell $and $and$ls180.v:6327$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6327$1860_Y + connect \Y $and$ls180.v:6327$1861_Y + end + attribute \src "ls180.v:6327.43-6327.151" + cell $and $and$ls180.v:6327$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6327$1861_Y + connect \B $eq$ls180.v:6327$1862_Y + connect \Y $and$ls180.v:6327$1863_Y + end + attribute \src "ls180.v:6329.44-6329.97" + cell $and $and$ls180.v:6329$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6329$1864_Y + end + attribute \src "ls180.v:6329.43-6329.148" + cell $and $and$ls180.v:6329$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6329$1864_Y + connect \B $eq$ls180.v:6329$1865_Y + connect \Y $and$ls180.v:6329$1866_Y + end + attribute \src "ls180.v:6330.44-6330.100" + cell $and $and$ls180.v:6330$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6330$1867_Y + connect \Y $and$ls180.v:6330$1868_Y + end + attribute \src "ls180.v:6330.43-6330.151" + cell $and $and$ls180.v:6330$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6330$1868_Y + connect \B $eq$ls180.v:6330$1869_Y + connect \Y $and$ls180.v:6330$1870_Y + end + attribute \src "ls180.v:6332.44-6332.97" + cell $and $and$ls180.v:6332$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6332$1871_Y + end + attribute \src "ls180.v:6332.43-6332.148" + cell $and $and$ls180.v:6332$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6332$1871_Y + connect \B $eq$ls180.v:6332$1872_Y + connect \Y $and$ls180.v:6332$1873_Y + end + attribute \src "ls180.v:6333.44-6333.100" + cell $and $and$ls180.v:6333$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6333$1874_Y + connect \Y $and$ls180.v:6333$1875_Y + end + attribute \src "ls180.v:6333.43-6333.151" + cell $and $and$ls180.v:6333$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6333$1875_Y + connect \B $eq$ls180.v:6333$1876_Y + connect \Y $and$ls180.v:6333$1877_Y + end + attribute \src "ls180.v:6335.44-6335.97" + cell $and $and$ls180.v:6335$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6335$1878_Y + end + attribute \src "ls180.v:6335.43-6335.148" + cell $and $and$ls180.v:6335$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6335$1878_Y + connect \B $eq$ls180.v:6335$1879_Y + connect \Y $and$ls180.v:6335$1880_Y + end + attribute \src "ls180.v:6336.44-6336.100" + cell $and $and$ls180.v:6336$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6336$1881_Y + connect \Y $and$ls180.v:6336$1882_Y + end + attribute \src "ls180.v:6336.43-6336.151" + cell $and $and$ls180.v:6336$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6336$1882_Y + connect \B $eq$ls180.v:6336$1883_Y + connect \Y $and$ls180.v:6336$1884_Y + end + attribute \src "ls180.v:6360.44-6360.97" + cell $and $and$ls180.v:6360$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6360$1886_Y + end + attribute \src "ls180.v:6360.43-6360.147" + cell $and $and$ls180.v:6360$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6360$1886_Y + connect \B $eq$ls180.v:6360$1887_Y + connect \Y $and$ls180.v:6360$1888_Y + end + attribute \src "ls180.v:6361.44-6361.100" + cell $and $and$ls180.v:6361$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6361$1889_Y + connect \Y $and$ls180.v:6361$1890_Y + end + attribute \src "ls180.v:6361.43-6361.150" + cell $and $and$ls180.v:6361$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6361$1890_Y + connect \B $eq$ls180.v:6361$1891_Y + connect \Y $and$ls180.v:6361$1892_Y + end + attribute \src "ls180.v:6363.49-6363.102" + cell $and $and$ls180.v:6363$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6363$1893_Y + end + attribute \src "ls180.v:6363.48-6363.152" + cell $and $and$ls180.v:6363$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6363$1893_Y + connect \B $eq$ls180.v:6363$1894_Y + connect \Y $and$ls180.v:6363$1895_Y + end + attribute \src "ls180.v:6364.49-6364.105" + cell $and $and$ls180.v:6364$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6364$1896_Y + connect \Y $and$ls180.v:6364$1897_Y + end + attribute \src "ls180.v:6364.48-6364.155" + cell $and $and$ls180.v:6364$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6364$1897_Y + connect \B $eq$ls180.v:6364$1898_Y + connect \Y $and$ls180.v:6364$1899_Y + end + attribute \src "ls180.v:6366.49-6366.102" + cell $and $and$ls180.v:6366$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6366$1900_Y + end + attribute \src "ls180.v:6366.48-6366.152" + cell $and $and$ls180.v:6366$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6366$1900_Y + connect \B $eq$ls180.v:6366$1901_Y + connect \Y $and$ls180.v:6366$1902_Y + end + attribute \src "ls180.v:6367.49-6367.105" + cell $and $and$ls180.v:6367$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6367$1903_Y + connect \Y $and$ls180.v:6367$1904_Y + end + attribute \src "ls180.v:6367.48-6367.155" + cell $and $and$ls180.v:6367$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6367$1904_Y + connect \B $eq$ls180.v:6367$1905_Y + connect \Y $and$ls180.v:6367$1906_Y + end + attribute \src "ls180.v:6369.42-6369.95" + cell $and $and$ls180.v:6369$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6369$1907_Y + end + attribute \src "ls180.v:6369.41-6369.145" + cell $and $and$ls180.v:6369$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6369$1907_Y + connect \B $eq$ls180.v:6369$1908_Y + connect \Y $and$ls180.v:6369$1909_Y + end + attribute \src "ls180.v:6370.42-6370.98" + cell $and $and$ls180.v:6370$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6370$1910_Y + connect \Y $and$ls180.v:6370$1911_Y + end + attribute \src "ls180.v:6370.41-6370.148" + cell $and $and$ls180.v:6370$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6370$1911_Y + connect \B $eq$ls180.v:6370$1912_Y + connect \Y $and$ls180.v:6370$1913_Y + end + attribute \src "ls180.v:6377.46-6377.99" + cell $and $and$ls180.v:6377$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6377$1915_Y + end + attribute \src "ls180.v:6377.45-6377.149" + cell $and $and$ls180.v:6377$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6377$1915_Y + connect \B $eq$ls180.v:6377$1916_Y + connect \Y $and$ls180.v:6377$1917_Y + end + attribute \src "ls180.v:6378.46-6378.102" + cell $and $and$ls180.v:6378$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6378$1918_Y + connect \Y $and$ls180.v:6378$1919_Y + end + attribute \src "ls180.v:6378.45-6378.152" + cell $and $and$ls180.v:6378$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6378$1919_Y + connect \B $eq$ls180.v:6378$1920_Y + connect \Y $and$ls180.v:6378$1921_Y + end + attribute \src "ls180.v:6380.50-6380.103" + cell $and $and$ls180.v:6380$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6380$1922_Y + end + attribute \src "ls180.v:6380.49-6380.153" + cell $and $and$ls180.v:6380$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6380$1922_Y + connect \B $eq$ls180.v:6380$1923_Y + connect \Y $and$ls180.v:6380$1924_Y + end + attribute \src "ls180.v:6381.50-6381.106" + cell $and $and$ls180.v:6381$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6381$1925_Y + connect \Y $and$ls180.v:6381$1926_Y + end + attribute \src "ls180.v:6381.49-6381.156" + cell $and $and$ls180.v:6381$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6381$1926_Y + connect \B $eq$ls180.v:6381$1927_Y + connect \Y $and$ls180.v:6381$1928_Y + end + attribute \src "ls180.v:6383.40-6383.93" + cell $and $and$ls180.v:6383$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6383$1929_Y + end + attribute \src "ls180.v:6383.39-6383.143" + cell $and $and$ls180.v:6383$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6383$1929_Y + connect \B $eq$ls180.v:6383$1930_Y + connect \Y $and$ls180.v:6383$1931_Y + end + attribute \src "ls180.v:6384.40-6384.96" + cell $and $and$ls180.v:6384$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6384$1932_Y + connect \Y $and$ls180.v:6384$1933_Y + end + attribute \src "ls180.v:6384.39-6384.146" + cell $and $and$ls180.v:6384$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6384$1933_Y + connect \B $eq$ls180.v:6384$1934_Y + connect \Y $and$ls180.v:6384$1935_Y + end + attribute \src "ls180.v:6386.50-6386.103" + cell $and $and$ls180.v:6386$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6386$1936_Y + end + attribute \src "ls180.v:6386.49-6386.153" + cell $and $and$ls180.v:6386$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6386$1936_Y + connect \B $eq$ls180.v:6386$1937_Y + connect \Y $and$ls180.v:6386$1938_Y + end + attribute \src "ls180.v:6387.50-6387.106" + cell $and $and$ls180.v:6387$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6387$1939_Y + connect \Y $and$ls180.v:6387$1940_Y + end + attribute \src "ls180.v:6387.49-6387.156" + cell $and $and$ls180.v:6387$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6387$1940_Y + connect \B $eq$ls180.v:6387$1941_Y + connect \Y $and$ls180.v:6387$1942_Y + end + attribute \src "ls180.v:6389.50-6389.103" + cell $and $and$ls180.v:6389$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6389$1943_Y + end + attribute \src "ls180.v:6389.49-6389.153" + cell $and $and$ls180.v:6389$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6389$1943_Y + connect \B $eq$ls180.v:6389$1944_Y + connect \Y $and$ls180.v:6389$1945_Y + end + attribute \src "ls180.v:6390.50-6390.106" + cell $and $and$ls180.v:6390$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6390$1946_Y + connect \Y $and$ls180.v:6390$1947_Y + end + attribute \src "ls180.v:6390.49-6390.156" + cell $and $and$ls180.v:6390$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6390$1947_Y + connect \B $eq$ls180.v:6390$1948_Y + connect \Y $and$ls180.v:6390$1949_Y + end + attribute \src "ls180.v:6392.51-6392.104" + cell $and $and$ls180.v:6392$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6392$1950_Y + end + attribute \src "ls180.v:6392.50-6392.154" + cell $and $and$ls180.v:6392$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$1950_Y + connect \B $eq$ls180.v:6392$1951_Y + connect \Y $and$ls180.v:6392$1952_Y + end + attribute \src "ls180.v:6393.51-6393.107" + cell $and $and$ls180.v:6393$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6393$1953_Y + connect \Y $and$ls180.v:6393$1954_Y + end + attribute \src "ls180.v:6393.50-6393.157" + cell $and $and$ls180.v:6393$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$1954_Y + connect \B $eq$ls180.v:6393$1955_Y + connect \Y $and$ls180.v:6393$1956_Y + end + attribute \src "ls180.v:6395.49-6395.102" + cell $and $and$ls180.v:6395$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6395$1957_Y + end + attribute \src "ls180.v:6395.48-6395.152" + cell $and $and$ls180.v:6395$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$1957_Y + connect \B $eq$ls180.v:6395$1958_Y + connect \Y $and$ls180.v:6395$1959_Y + end + attribute \src "ls180.v:6396.49-6396.105" + cell $and $and$ls180.v:6396$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6396$1960_Y + connect \Y $and$ls180.v:6396$1961_Y + end + attribute \src "ls180.v:6396.48-6396.155" + cell $and $and$ls180.v:6396$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$1961_Y + connect \B $eq$ls180.v:6396$1962_Y + connect \Y $and$ls180.v:6396$1963_Y + end + attribute \src "ls180.v:6398.49-6398.102" + cell $and $and$ls180.v:6398$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6398$1964_Y + end + attribute \src "ls180.v:6398.48-6398.152" + cell $and $and$ls180.v:6398$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6398$1964_Y + connect \B $eq$ls180.v:6398$1965_Y + connect \Y $and$ls180.v:6398$1966_Y + end + attribute \src "ls180.v:6399.49-6399.105" + cell $and $and$ls180.v:6399$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6399$1967_Y + connect \Y $and$ls180.v:6399$1968_Y + end + attribute \src "ls180.v:6399.48-6399.155" + cell $and $and$ls180.v:6399$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6399$1968_Y + connect \B $eq$ls180.v:6399$1969_Y + connect \Y $and$ls180.v:6399$1970_Y + end + attribute \src "ls180.v:6401.49-6401.102" + cell $and $and$ls180.v:6401$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6401$1971_Y + end + attribute \src "ls180.v:6401.48-6401.152" + cell $and $and$ls180.v:6401$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6401$1971_Y + connect \B $eq$ls180.v:6401$1972_Y + connect \Y $and$ls180.v:6401$1973_Y + end + attribute \src "ls180.v:6402.49-6402.105" + cell $and $and$ls180.v:6402$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6402$1974_Y + connect \Y $and$ls180.v:6402$1975_Y + end + attribute \src "ls180.v:6402.48-6402.155" + cell $and $and$ls180.v:6402$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6402$1975_Y + connect \B $eq$ls180.v:6402$1976_Y + connect \Y $and$ls180.v:6402$1977_Y + end + attribute \src "ls180.v:6404.49-6404.102" + cell $and $and$ls180.v:6404$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6404$1978_Y + end + attribute \src "ls180.v:6404.48-6404.152" + cell $and $and$ls180.v:6404$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6404$1978_Y + connect \B $eq$ls180.v:6404$1979_Y + connect \Y $and$ls180.v:6404$1980_Y + end + attribute \src "ls180.v:6405.49-6405.105" + cell $and $and$ls180.v:6405$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6405$1981_Y + connect \Y $and$ls180.v:6405$1982_Y + end + attribute \src "ls180.v:6405.48-6405.155" + cell $and $and$ls180.v:6405$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6405$1982_Y + connect \B $eq$ls180.v:6405$1983_Y + connect \Y $and$ls180.v:6405$1984_Y + end + attribute \src "ls180.v:6422.42-6422.97" + cell $and $and$ls180.v:6422$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6422$1986_Y + end + attribute \src "ls180.v:6422.41-6422.148" + cell $and $and$ls180.v:6422$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6422$1986_Y + connect \B $eq$ls180.v:6422$1987_Y + connect \Y $and$ls180.v:6422$1988_Y + end + attribute \src "ls180.v:6423.42-6423.100" + cell $and $and$ls180.v:6423$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6423$1989_Y + connect \Y $and$ls180.v:6423$1990_Y + end + attribute \src "ls180.v:6423.41-6423.151" + cell $and $and$ls180.v:6423$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6423$1990_Y + connect \B $eq$ls180.v:6423$1991_Y + connect \Y $and$ls180.v:6423$1992_Y + end + attribute \src "ls180.v:6425.42-6425.97" + cell $and $and$ls180.v:6425$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6425$1993_Y + end + attribute \src "ls180.v:6425.41-6425.148" + cell $and $and$ls180.v:6425$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6425$1993_Y + connect \B $eq$ls180.v:6425$1994_Y + connect \Y $and$ls180.v:6425$1995_Y + end + attribute \src "ls180.v:6426.42-6426.100" + cell $and $and$ls180.v:6426$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6426$1996_Y + connect \Y $and$ls180.v:6426$1997_Y + end + attribute \src "ls180.v:6426.41-6426.151" + cell $and $and$ls180.v:6426$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6426$1997_Y + connect \B $eq$ls180.v:6426$1998_Y + connect \Y $and$ls180.v:6426$1999_Y + end + attribute \src "ls180.v:6428.40-6428.95" + cell $and $and$ls180.v:6428$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6428$2000_Y + end + attribute \src "ls180.v:6428.39-6428.146" + cell $and $and$ls180.v:6428$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6428$2000_Y + connect \B $eq$ls180.v:6428$2001_Y + connect \Y $and$ls180.v:6428$2002_Y + end + attribute \src "ls180.v:6429.40-6429.98" + cell $and $and$ls180.v:6429$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6429$2003_Y + connect \Y $and$ls180.v:6429$2004_Y + end + attribute \src "ls180.v:6429.39-6429.149" + cell $and $and$ls180.v:6429$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6429$2004_Y + connect \B $eq$ls180.v:6429$2005_Y + connect \Y $and$ls180.v:6429$2006_Y + end + attribute \src "ls180.v:6431.39-6431.94" + cell $and $and$ls180.v:6431$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6431$2007_Y + end + attribute \src "ls180.v:6431.38-6431.145" + cell $and $and$ls180.v:6431$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6431$2007_Y + connect \B $eq$ls180.v:6431$2008_Y + connect \Y $and$ls180.v:6431$2009_Y + end + attribute \src "ls180.v:6432.39-6432.97" + cell $and $and$ls180.v:6432$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6432$2010_Y + connect \Y $and$ls180.v:6432$2011_Y + end + attribute \src "ls180.v:6432.38-6432.148" + cell $and $and$ls180.v:6432$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6432$2011_Y + connect \B $eq$ls180.v:6432$2012_Y + connect \Y $and$ls180.v:6432$2013_Y + end + attribute \src "ls180.v:6434.38-6434.93" + cell $and $and$ls180.v:6434$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6434$2014_Y + end + attribute \src "ls180.v:6434.37-6434.144" + cell $and $and$ls180.v:6434$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6434$2014_Y + connect \B $eq$ls180.v:6434$2015_Y + connect \Y $and$ls180.v:6434$2016_Y + end + attribute \src "ls180.v:6435.38-6435.96" + cell $and $and$ls180.v:6435$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6435$2017_Y + connect \Y $and$ls180.v:6435$2018_Y + end + attribute \src "ls180.v:6435.37-6435.147" + cell $and $and$ls180.v:6435$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6435$2018_Y + connect \B $eq$ls180.v:6435$2019_Y + connect \Y $and$ls180.v:6435$2020_Y + end + attribute \src "ls180.v:6437.37-6437.92" + cell $and $and$ls180.v:6437$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6437$2021_Y + end + attribute \src "ls180.v:6437.36-6437.143" + cell $and $and$ls180.v:6437$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6437$2021_Y + connect \B $eq$ls180.v:6437$2022_Y + connect \Y $and$ls180.v:6437$2023_Y + end + attribute \src "ls180.v:6438.37-6438.95" + cell $and $and$ls180.v:6438$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6438$2024_Y + connect \Y $and$ls180.v:6438$2025_Y + end + attribute \src "ls180.v:6438.36-6438.146" + cell $and $and$ls180.v:6438$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6438$2025_Y + connect \B $eq$ls180.v:6438$2026_Y + connect \Y $and$ls180.v:6438$2027_Y + end + attribute \src "ls180.v:6440.43-6440.98" + cell $and $and$ls180.v:6440$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6440$2028_Y + end + attribute \src "ls180.v:6440.42-6440.149" + cell $and $and$ls180.v:6440$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6440$2028_Y + connect \B $eq$ls180.v:6440$2029_Y + connect \Y $and$ls180.v:6440$2030_Y + end + attribute \src "ls180.v:6441.43-6441.101" + cell $and $and$ls180.v:6441$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6441$2031_Y + connect \Y $and$ls180.v:6441$2032_Y + end + attribute \src "ls180.v:6441.42-6441.152" + cell $and $and$ls180.v:6441$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6441$2032_Y + connect \B $eq$ls180.v:6441$2033_Y + connect \Y $and$ls180.v:6441$2034_Y + end + attribute \src "ls180.v:6462.42-6462.97" + cell $and $and$ls180.v:6462$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6462$2037_Y + end + attribute \src "ls180.v:6462.41-6462.148" + cell $and $and$ls180.v:6462$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6462$2037_Y + connect \B $eq$ls180.v:6462$2038_Y + connect \Y $and$ls180.v:6462$2039_Y + end + attribute \src "ls180.v:6463.42-6463.100" + cell $and $and$ls180.v:6463$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6463$2040_Y + connect \Y $and$ls180.v:6463$2041_Y + end + attribute \src "ls180.v:6463.41-6463.151" + cell $and $and$ls180.v:6463$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6463$2041_Y + connect \B $eq$ls180.v:6463$2042_Y + connect \Y $and$ls180.v:6463$2043_Y + end + attribute \src "ls180.v:6465.42-6465.97" + cell $and $and$ls180.v:6465$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6465$2044_Y + end + attribute \src "ls180.v:6465.41-6465.148" + cell $and $and$ls180.v:6465$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6465$2044_Y + connect \B $eq$ls180.v:6465$2045_Y + connect \Y $and$ls180.v:6465$2046_Y + end + attribute \src "ls180.v:6466.42-6466.100" + cell $and $and$ls180.v:6466$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6466$2047_Y + connect \Y $and$ls180.v:6466$2048_Y + end + attribute \src "ls180.v:6466.41-6466.151" + cell $and $and$ls180.v:6466$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6466$2048_Y + connect \B $eq$ls180.v:6466$2049_Y + connect \Y $and$ls180.v:6466$2050_Y + end + attribute \src "ls180.v:6468.40-6468.95" + cell $and $and$ls180.v:6468$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6468$2051_Y + end + attribute \src "ls180.v:6468.39-6468.146" + cell $and $and$ls180.v:6468$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6468$2051_Y + connect \B $eq$ls180.v:6468$2052_Y + connect \Y $and$ls180.v:6468$2053_Y + end + attribute \src "ls180.v:6469.40-6469.98" + cell $and $and$ls180.v:6469$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6469$2054_Y + connect \Y $and$ls180.v:6469$2055_Y + end + attribute \src "ls180.v:6469.39-6469.149" + cell $and $and$ls180.v:6469$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6469$2055_Y + connect \B $eq$ls180.v:6469$2056_Y + connect \Y $and$ls180.v:6469$2057_Y + end + attribute \src "ls180.v:6471.39-6471.94" + cell $and $and$ls180.v:6471$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6471$2058_Y + end + attribute \src "ls180.v:6471.38-6471.145" + cell $and $and$ls180.v:6471$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6471$2058_Y + connect \B $eq$ls180.v:6471$2059_Y + connect \Y $and$ls180.v:6471$2060_Y + end + attribute \src "ls180.v:6472.39-6472.97" + cell $and $and$ls180.v:6472$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6472$2061_Y + connect \Y $and$ls180.v:6472$2062_Y + end + attribute \src "ls180.v:6472.38-6472.148" + cell $and $and$ls180.v:6472$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6472$2062_Y + connect \B $eq$ls180.v:6472$2063_Y + connect \Y $and$ls180.v:6472$2064_Y + end + attribute \src "ls180.v:6474.38-6474.93" + cell $and $and$ls180.v:6474$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6474$2065_Y + end + attribute \src "ls180.v:6474.37-6474.144" + cell $and $and$ls180.v:6474$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6474$2065_Y + connect \B $eq$ls180.v:6474$2066_Y + connect \Y $and$ls180.v:6474$2067_Y + end + attribute \src "ls180.v:6475.38-6475.96" + cell $and $and$ls180.v:6475$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6475$2068_Y + connect \Y $and$ls180.v:6475$2069_Y + end + attribute \src "ls180.v:6475.37-6475.147" + cell $and $and$ls180.v:6475$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6475$2069_Y + connect \B $eq$ls180.v:6475$2070_Y + connect \Y $and$ls180.v:6475$2071_Y + end + attribute \src "ls180.v:6477.37-6477.92" + cell $and $and$ls180.v:6477$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6477$2072_Y + end + attribute \src "ls180.v:6477.36-6477.143" + cell $and $and$ls180.v:6477$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6477$2072_Y + connect \B $eq$ls180.v:6477$2073_Y + connect \Y $and$ls180.v:6477$2074_Y + end + attribute \src "ls180.v:6478.37-6478.95" + cell $and $and$ls180.v:6478$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6478$2075_Y + connect \Y $and$ls180.v:6478$2076_Y + end + attribute \src "ls180.v:6478.36-6478.146" + cell $and $and$ls180.v:6478$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6478$2076_Y + connect \B $eq$ls180.v:6478$2077_Y + connect \Y $and$ls180.v:6478$2078_Y + end + attribute \src "ls180.v:6480.43-6480.98" + cell $and $and$ls180.v:6480$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6480$2079_Y + end + attribute \src "ls180.v:6480.42-6480.149" + cell $and $and$ls180.v:6480$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6480$2079_Y + connect \B $eq$ls180.v:6480$2080_Y + connect \Y $and$ls180.v:6480$2081_Y + end + attribute \src "ls180.v:6481.43-6481.101" + cell $and $and$ls180.v:6481$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6481$2082_Y + connect \Y $and$ls180.v:6481$2083_Y + end + attribute \src "ls180.v:6481.42-6481.152" + cell $and $and$ls180.v:6481$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6481$2083_Y + connect \B $eq$ls180.v:6481$2084_Y + connect \Y $and$ls180.v:6481$2085_Y + end + attribute \src "ls180.v:6483.46-6483.101" + cell $and $and$ls180.v:6483$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6483$2086_Y + end + attribute \src "ls180.v:6483.45-6483.152" + cell $and $and$ls180.v:6483$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6483$2086_Y + connect \B $eq$ls180.v:6483$2087_Y + connect \Y $and$ls180.v:6483$2088_Y + end + attribute \src "ls180.v:6484.46-6484.104" + cell $and $and$ls180.v:6484$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6484$2089_Y + connect \Y $and$ls180.v:6484$2090_Y + end + attribute \src "ls180.v:6484.45-6484.155" + cell $and $and$ls180.v:6484$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6484$2090_Y + connect \B $eq$ls180.v:6484$2091_Y + connect \Y $and$ls180.v:6484$2092_Y + end + attribute \src "ls180.v:6486.46-6486.101" + cell $and $and$ls180.v:6486$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6486$2093_Y + end + attribute \src "ls180.v:6486.45-6486.152" + cell $and $and$ls180.v:6486$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6486$2093_Y + connect \B $eq$ls180.v:6486$2094_Y + connect \Y $and$ls180.v:6486$2095_Y + end + attribute \src "ls180.v:6487.46-6487.104" + cell $and $and$ls180.v:6487$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6487$2096_Y + connect \Y $and$ls180.v:6487$2097_Y + end + attribute \src "ls180.v:6487.45-6487.155" + cell $and $and$ls180.v:6487$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6487$2097_Y + connect \B $eq$ls180.v:6487$2098_Y + connect \Y $and$ls180.v:6487$2099_Y + end + attribute \src "ls180.v:6510.39-6510.94" + cell $and $and$ls180.v:6510$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6510$2102_Y + end + attribute \src "ls180.v:6510.38-6510.145" + cell $and $and$ls180.v:6510$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6510$2102_Y + connect \B $eq$ls180.v:6510$2103_Y + connect \Y $and$ls180.v:6510$2104_Y + end + attribute \src "ls180.v:6511.39-6511.97" + cell $and $and$ls180.v:6511$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6511$2105_Y + connect \Y $and$ls180.v:6511$2106_Y + end + attribute \src "ls180.v:6511.38-6511.148" + cell $and $and$ls180.v:6511$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6511$2106_Y + connect \B $eq$ls180.v:6511$2107_Y + connect \Y $and$ls180.v:6511$2108_Y + end + attribute \src "ls180.v:6513.39-6513.94" + cell $and $and$ls180.v:6513$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6513$2109_Y + end + attribute \src "ls180.v:6513.38-6513.145" + cell $and $and$ls180.v:6513$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6513$2109_Y + connect \B $eq$ls180.v:6513$2110_Y + connect \Y $and$ls180.v:6513$2111_Y + end + attribute \src "ls180.v:6514.39-6514.97" + cell $and $and$ls180.v:6514$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6514$2112_Y + connect \Y $and$ls180.v:6514$2113_Y + end + attribute \src "ls180.v:6514.38-6514.148" + cell $and $and$ls180.v:6514$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6514$2113_Y + connect \B $eq$ls180.v:6514$2114_Y + connect \Y $and$ls180.v:6514$2115_Y + end + attribute \src "ls180.v:6516.39-6516.94" + cell $and $and$ls180.v:6516$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6516$2116_Y + end + attribute \src "ls180.v:6516.38-6516.145" + cell $and $and$ls180.v:6516$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6516$2116_Y + connect \B $eq$ls180.v:6516$2117_Y + connect \Y $and$ls180.v:6516$2118_Y + end + attribute \src "ls180.v:6517.39-6517.97" + cell $and $and$ls180.v:6517$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6517$2119_Y + connect \Y $and$ls180.v:6517$2120_Y + end + attribute \src "ls180.v:6517.38-6517.148" + cell $and $and$ls180.v:6517$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6517$2120_Y + connect \B $eq$ls180.v:6517$2121_Y + connect \Y $and$ls180.v:6517$2122_Y + end + attribute \src "ls180.v:6519.39-6519.94" + cell $and $and$ls180.v:6519$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6519$2123_Y + end + attribute \src "ls180.v:6519.38-6519.145" + cell $and $and$ls180.v:6519$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6519$2123_Y + connect \B $eq$ls180.v:6519$2124_Y + connect \Y $and$ls180.v:6519$2125_Y + end + attribute \src "ls180.v:6520.39-6520.97" + cell $and $and$ls180.v:6520$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6520$2126_Y + connect \Y $and$ls180.v:6520$2127_Y + end + attribute \src "ls180.v:6520.38-6520.148" + cell $and $and$ls180.v:6520$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6520$2127_Y + connect \B $eq$ls180.v:6520$2128_Y + connect \Y $and$ls180.v:6520$2129_Y + end + attribute \src "ls180.v:6522.41-6522.96" + cell $and $and$ls180.v:6522$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6522$2130_Y + end + attribute \src "ls180.v:6522.40-6522.147" + cell $and $and$ls180.v:6522$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6522$2130_Y + connect \B $eq$ls180.v:6522$2131_Y + connect \Y $and$ls180.v:6522$2132_Y + end + attribute \src "ls180.v:6523.41-6523.99" + cell $and $and$ls180.v:6523$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6523$2133_Y + connect \Y $and$ls180.v:6523$2134_Y + end + attribute \src "ls180.v:6523.40-6523.150" + cell $and $and$ls180.v:6523$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6523$2134_Y + connect \B $eq$ls180.v:6523$2135_Y + connect \Y $and$ls180.v:6523$2136_Y + end + attribute \src "ls180.v:6525.41-6525.96" + cell $and $and$ls180.v:6525$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6525$2137_Y + end + attribute \src "ls180.v:6525.40-6525.147" + cell $and $and$ls180.v:6525$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6525$2137_Y + connect \B $eq$ls180.v:6525$2138_Y + connect \Y $and$ls180.v:6525$2139_Y + end + attribute \src "ls180.v:6526.41-6526.99" + cell $and $and$ls180.v:6526$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6526$2140_Y + connect \Y $and$ls180.v:6526$2141_Y + end + attribute \src "ls180.v:6526.40-6526.150" + cell $and $and$ls180.v:6526$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6526$2141_Y + connect \B $eq$ls180.v:6526$2142_Y + connect \Y $and$ls180.v:6526$2143_Y + end + attribute \src "ls180.v:6528.41-6528.96" + cell $and $and$ls180.v:6528$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6528$2144_Y + end + attribute \src "ls180.v:6528.40-6528.147" + cell $and $and$ls180.v:6528$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6528$2144_Y + connect \B $eq$ls180.v:6528$2145_Y + connect \Y $and$ls180.v:6528$2146_Y + end + attribute \src "ls180.v:6529.41-6529.99" + cell $and $and$ls180.v:6529$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6529$2147_Y + connect \Y $and$ls180.v:6529$2148_Y + end + attribute \src "ls180.v:6529.40-6529.150" + cell $and $and$ls180.v:6529$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6529$2148_Y + connect \B $eq$ls180.v:6529$2149_Y + connect \Y $and$ls180.v:6529$2150_Y + end + attribute \src "ls180.v:6531.41-6531.96" + cell $and $and$ls180.v:6531$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6531$2151_Y + end + attribute \src "ls180.v:6531.40-6531.147" + cell $and $and$ls180.v:6531$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6531$2151_Y + connect \B $eq$ls180.v:6531$2152_Y + connect \Y $and$ls180.v:6531$2153_Y + end + attribute \src "ls180.v:6532.41-6532.99" + cell $and $and$ls180.v:6532$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6532$2154_Y + connect \Y $and$ls180.v:6532$2155_Y + end + attribute \src "ls180.v:6532.40-6532.150" + cell $and $and$ls180.v:6532$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6532$2155_Y + connect \B $eq$ls180.v:6532$2156_Y + connect \Y $and$ls180.v:6532$2157_Y + end + attribute \src "ls180.v:6534.37-6534.92" + cell $and $and$ls180.v:6534$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6534$2158_Y + end + attribute \src "ls180.v:6534.36-6534.143" + cell $and $and$ls180.v:6534$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6534$2158_Y + connect \B $eq$ls180.v:6534$2159_Y + connect \Y $and$ls180.v:6534$2160_Y + end + attribute \src "ls180.v:6535.37-6535.95" + cell $and $and$ls180.v:6535$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6535$2161_Y + connect \Y $and$ls180.v:6535$2162_Y + end + attribute \src "ls180.v:6535.36-6535.146" + cell $and $and$ls180.v:6535$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6535$2162_Y + connect \B $eq$ls180.v:6535$2163_Y + connect \Y $and$ls180.v:6535$2164_Y + end + attribute \src "ls180.v:6537.47-6537.102" + cell $and $and$ls180.v:6537$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6537$2165_Y + end + attribute \src "ls180.v:6537.46-6537.153" + cell $and $and$ls180.v:6537$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6537$2165_Y + connect \B $eq$ls180.v:6537$2166_Y + connect \Y $and$ls180.v:6537$2167_Y + end + attribute \src "ls180.v:6538.47-6538.105" + cell $and $and$ls180.v:6538$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6538$2168_Y + connect \Y $and$ls180.v:6538$2169_Y + end + attribute \src "ls180.v:6538.46-6538.156" + cell $and $and$ls180.v:6538$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6538$2169_Y + connect \B $eq$ls180.v:6538$2170_Y + connect \Y $and$ls180.v:6538$2171_Y + end + attribute \src "ls180.v:6540.40-6540.95" + cell $and $and$ls180.v:6540$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6540$2172_Y + end + attribute \src "ls180.v:6540.39-6540.147" + cell $and $and$ls180.v:6540$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6540$2172_Y + connect \B $eq$ls180.v:6540$2173_Y + connect \Y $and$ls180.v:6540$2174_Y + end + attribute \src "ls180.v:6541.40-6541.98" + cell $and $and$ls180.v:6541$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6541$2175_Y + connect \Y $and$ls180.v:6541$2176_Y + end + attribute \src "ls180.v:6541.39-6541.150" + cell $and $and$ls180.v:6541$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6541$2176_Y + connect \B $eq$ls180.v:6541$2177_Y + connect \Y $and$ls180.v:6541$2178_Y + end + attribute \src "ls180.v:6543.40-6543.95" + cell $and $and$ls180.v:6543$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6543$2179_Y + end + attribute \src "ls180.v:6543.39-6543.147" + cell $and $and$ls180.v:6543$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6543$2179_Y + connect \B $eq$ls180.v:6543$2180_Y + connect \Y $and$ls180.v:6543$2181_Y + end + attribute \src "ls180.v:6544.40-6544.98" + cell $and $and$ls180.v:6544$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6544$2182_Y + connect \Y $and$ls180.v:6544$2183_Y + end + attribute \src "ls180.v:6544.39-6544.150" + cell $and $and$ls180.v:6544$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6544$2183_Y + connect \B $eq$ls180.v:6544$2184_Y + connect \Y $and$ls180.v:6544$2185_Y + end + attribute \src "ls180.v:6546.40-6546.95" + cell $and $and$ls180.v:6546$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6546$2186_Y + end + attribute \src "ls180.v:6546.39-6546.147" + cell $and $and$ls180.v:6546$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6546$2186_Y + connect \B $eq$ls180.v:6546$2187_Y + connect \Y $and$ls180.v:6546$2188_Y + end + attribute \src "ls180.v:6547.40-6547.98" + cell $and $and$ls180.v:6547$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6547$2189_Y + connect \Y $and$ls180.v:6547$2190_Y + end + attribute \src "ls180.v:6547.39-6547.150" + cell $and $and$ls180.v:6547$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6547$2190_Y + connect \B $eq$ls180.v:6547$2191_Y + connect \Y $and$ls180.v:6547$2192_Y + end + attribute \src "ls180.v:6549.40-6549.95" + cell $and $and$ls180.v:6549$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6549$2193_Y + end + attribute \src "ls180.v:6549.39-6549.147" + cell $and $and$ls180.v:6549$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6549$2193_Y + connect \B $eq$ls180.v:6549$2194_Y + connect \Y $and$ls180.v:6549$2195_Y + end + attribute \src "ls180.v:6550.40-6550.98" + cell $and $and$ls180.v:6550$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6550$2196_Y + connect \Y $and$ls180.v:6550$2197_Y + end + attribute \src "ls180.v:6550.39-6550.150" + cell $and $and$ls180.v:6550$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6550$2197_Y + connect \B $eq$ls180.v:6550$2198_Y + connect \Y $and$ls180.v:6550$2199_Y + end + attribute \src "ls180.v:6552.52-6552.107" + cell $and $and$ls180.v:6552$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6552$2200_Y + end + attribute \src "ls180.v:6552.51-6552.159" + cell $and $and$ls180.v:6552$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6552$2200_Y + connect \B $eq$ls180.v:6552$2201_Y + connect \Y $and$ls180.v:6552$2202_Y + end + attribute \src "ls180.v:6553.52-6553.110" + cell $and $and$ls180.v:6553$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6553$2203_Y + connect \Y $and$ls180.v:6553$2204_Y + end + attribute \src "ls180.v:6553.51-6553.162" + cell $and $and$ls180.v:6553$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6553$2204_Y + connect \B $eq$ls180.v:6553$2205_Y + connect \Y $and$ls180.v:6553$2206_Y + end + attribute \src "ls180.v:6555.53-6555.108" + cell $and $and$ls180.v:6555$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6555$2207_Y + end + attribute \src "ls180.v:6555.52-6555.160" + cell $and $and$ls180.v:6555$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6555$2207_Y + connect \B $eq$ls180.v:6555$2208_Y + connect \Y $and$ls180.v:6555$2209_Y + end + attribute \src "ls180.v:6556.53-6556.111" + cell $and $and$ls180.v:6556$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6556$2210_Y + connect \Y $and$ls180.v:6556$2211_Y + end + attribute \src "ls180.v:6556.52-6556.163" + cell $and $and$ls180.v:6556$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6556$2211_Y + connect \B $eq$ls180.v:6556$2212_Y + connect \Y $and$ls180.v:6556$2213_Y + end + attribute \src "ls180.v:6558.44-6558.99" + cell $and $and$ls180.v:6558$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6558$2214_Y + end + attribute \src "ls180.v:6558.43-6558.151" + cell $and $and$ls180.v:6558$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6558$2214_Y + connect \B $eq$ls180.v:6558$2215_Y + connect \Y $and$ls180.v:6558$2216_Y + end + attribute \src "ls180.v:6559.44-6559.102" + cell $and $and$ls180.v:6559$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6559$2217_Y + connect \Y $and$ls180.v:6559$2218_Y + end + attribute \src "ls180.v:6559.43-6559.154" + cell $and $and$ls180.v:6559$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6559$2218_Y + connect \B $eq$ls180.v:6559$2219_Y + connect \Y $and$ls180.v:6559$2220_Y + end + attribute \src "ls180.v:6578.30-6578.85" + cell $and $and$ls180.v:6578$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6578$2222_Y + end + attribute \src "ls180.v:6578.29-6578.136" + cell $and $and$ls180.v:6578$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6578$2222_Y + connect \B $eq$ls180.v:6578$2223_Y + connect \Y $and$ls180.v:6578$2224_Y + end + attribute \src "ls180.v:6579.30-6579.88" + cell $and $and$ls180.v:6579$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6579$2225_Y + connect \Y $and$ls180.v:6579$2226_Y + end + attribute \src "ls180.v:6579.29-6579.139" + cell $and $and$ls180.v:6579$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6579$2226_Y + connect \B $eq$ls180.v:6579$2227_Y + connect \Y $and$ls180.v:6579$2228_Y + end + attribute \src "ls180.v:6581.40-6581.95" + cell $and $and$ls180.v:6581$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6581$2229_Y + end + attribute \src "ls180.v:6581.39-6581.146" + cell $and $and$ls180.v:6581$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6581$2229_Y + connect \B $eq$ls180.v:6581$2230_Y + connect \Y $and$ls180.v:6581$2231_Y + end + attribute \src "ls180.v:6582.40-6582.98" + cell $and $and$ls180.v:6582$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6582$2232_Y + connect \Y $and$ls180.v:6582$2233_Y + end + attribute \src "ls180.v:6582.39-6582.149" + cell $and $and$ls180.v:6582$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6582$2233_Y + connect \B $eq$ls180.v:6582$2234_Y + connect \Y $and$ls180.v:6582$2235_Y + end + attribute \src "ls180.v:6584.41-6584.96" + cell $and $and$ls180.v:6584$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6584$2236_Y + end + attribute \src "ls180.v:6584.40-6584.147" + cell $and $and$ls180.v:6584$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6584$2236_Y + connect \B $eq$ls180.v:6584$2237_Y + connect \Y $and$ls180.v:6584$2238_Y + end + attribute \src "ls180.v:6585.41-6585.99" + cell $and $and$ls180.v:6585$2240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6585$2239_Y + connect \Y $and$ls180.v:6585$2240_Y + end + attribute \src "ls180.v:6585.40-6585.150" + cell $and $and$ls180.v:6585$2242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6585$2240_Y + connect \B $eq$ls180.v:6585$2241_Y + connect \Y $and$ls180.v:6585$2242_Y + end + attribute \src "ls180.v:6587.45-6587.100" + cell $and $and$ls180.v:6587$2243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6587$2243_Y + end + attribute \src "ls180.v:6587.44-6587.151" + cell $and $and$ls180.v:6587$2245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6587$2243_Y + connect \B $eq$ls180.v:6587$2244_Y + connect \Y $and$ls180.v:6587$2245_Y + end + attribute \src "ls180.v:6588.45-6588.103" + cell $and $and$ls180.v:6588$2247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6588$2246_Y + connect \Y $and$ls180.v:6588$2247_Y + end + attribute \src "ls180.v:6588.44-6588.154" + cell $and $and$ls180.v:6588$2249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6588$2247_Y + connect \B $eq$ls180.v:6588$2248_Y + connect \Y $and$ls180.v:6588$2249_Y + end + attribute \src "ls180.v:6590.46-6590.101" + cell $and $and$ls180.v:6590$2250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6590$2250_Y + end + attribute \src "ls180.v:6590.45-6590.152" + cell $and $and$ls180.v:6590$2252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6590$2250_Y + connect \B $eq$ls180.v:6590$2251_Y + connect \Y $and$ls180.v:6590$2252_Y + end + attribute \src "ls180.v:6591.46-6591.104" + cell $and $and$ls180.v:6591$2254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6591$2253_Y + connect \Y $and$ls180.v:6591$2254_Y + end + attribute \src "ls180.v:6591.45-6591.155" + cell $and $and$ls180.v:6591$2256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6591$2254_Y + connect \B $eq$ls180.v:6591$2255_Y + connect \Y $and$ls180.v:6591$2256_Y + end + attribute \src "ls180.v:6593.44-6593.99" + cell $and $and$ls180.v:6593$2257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6593$2257_Y + end + attribute \src "ls180.v:6593.43-6593.150" + cell $and $and$ls180.v:6593$2259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6593$2257_Y + connect \B $eq$ls180.v:6593$2258_Y + connect \Y $and$ls180.v:6593$2259_Y + end + attribute \src "ls180.v:6594.44-6594.102" + cell $and $and$ls180.v:6594$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6594$2260_Y + connect \Y $and$ls180.v:6594$2261_Y + end + attribute \src "ls180.v:6594.43-6594.153" + cell $and $and$ls180.v:6594$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6594$2261_Y + connect \B $eq$ls180.v:6594$2262_Y + connect \Y $and$ls180.v:6594$2263_Y + end + attribute \src "ls180.v:6596.41-6596.96" + cell $and $and$ls180.v:6596$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6596$2264_Y + end + attribute \src "ls180.v:6596.40-6596.147" + cell $and $and$ls180.v:6596$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6596$2264_Y + connect \B $eq$ls180.v:6596$2265_Y + connect \Y $and$ls180.v:6596$2266_Y + end + attribute \src "ls180.v:6597.41-6597.99" + cell $and $and$ls180.v:6597$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6597$2267_Y + connect \Y $and$ls180.v:6597$2268_Y + end + attribute \src "ls180.v:6597.40-6597.150" + cell $and $and$ls180.v:6597$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6597$2268_Y + connect \B $eq$ls180.v:6597$2269_Y + connect \Y $and$ls180.v:6597$2270_Y + end + attribute \src "ls180.v:6599.40-6599.95" + cell $and $and$ls180.v:6599$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6599$2271_Y + end + attribute \src "ls180.v:6599.39-6599.146" + cell $and $and$ls180.v:6599$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6599$2271_Y + connect \B $eq$ls180.v:6599$2272_Y + connect \Y $and$ls180.v:6599$2273_Y + end + attribute \src "ls180.v:6600.40-6600.98" + cell $and $and$ls180.v:6600$2275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6600$2274_Y + connect \Y $and$ls180.v:6600$2275_Y + end + attribute \src "ls180.v:6600.39-6600.149" + cell $and $and$ls180.v:6600$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6600$2275_Y + connect \B $eq$ls180.v:6600$2276_Y + connect \Y $and$ls180.v:6600$2277_Y + end + attribute \src "ls180.v:6612.46-6612.101" + cell $and $and$ls180.v:6612$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6612$2279_Y + end + attribute \src "ls180.v:6612.45-6612.152" + cell $and $and$ls180.v:6612$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6612$2279_Y + connect \B $eq$ls180.v:6612$2280_Y + connect \Y $and$ls180.v:6612$2281_Y + end + attribute \src "ls180.v:6613.46-6613.104" + cell $and $and$ls180.v:6613$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6613$2282_Y + connect \Y $and$ls180.v:6613$2283_Y + end + attribute \src "ls180.v:6613.45-6613.155" + cell $and $and$ls180.v:6613$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6613$2283_Y + connect \B $eq$ls180.v:6613$2284_Y + connect \Y $and$ls180.v:6613$2285_Y + end + attribute \src "ls180.v:6615.46-6615.101" + cell $and $and$ls180.v:6615$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6615$2286_Y + end + attribute \src "ls180.v:6615.45-6615.152" + cell $and $and$ls180.v:6615$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6615$2286_Y + connect \B $eq$ls180.v:6615$2287_Y + connect \Y $and$ls180.v:6615$2288_Y + end + attribute \src "ls180.v:6616.46-6616.104" + cell $and $and$ls180.v:6616$2290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6616$2289_Y + connect \Y $and$ls180.v:6616$2290_Y + end + attribute \src "ls180.v:6616.45-6616.155" + cell $and $and$ls180.v:6616$2292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6616$2290_Y + connect \B $eq$ls180.v:6616$2291_Y + connect \Y $and$ls180.v:6616$2292_Y + end + attribute \src "ls180.v:6618.46-6618.101" + cell $and $and$ls180.v:6618$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6618$2293_Y + end + attribute \src "ls180.v:6618.45-6618.152" + cell $and $and$ls180.v:6618$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6618$2293_Y + connect \B $eq$ls180.v:6618$2294_Y + connect \Y $and$ls180.v:6618$2295_Y + end + attribute \src "ls180.v:6619.46-6619.104" + cell $and $and$ls180.v:6619$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6619$2296_Y + connect \Y $and$ls180.v:6619$2297_Y + end + attribute \src "ls180.v:6619.45-6619.155" + cell $and $and$ls180.v:6619$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6619$2297_Y + connect \B $eq$ls180.v:6619$2298_Y + connect \Y $and$ls180.v:6619$2299_Y + end + attribute \src "ls180.v:6621.46-6621.101" + cell $and $and$ls180.v:6621$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6621$2300_Y + end + attribute \src "ls180.v:6621.45-6621.152" + cell $and $and$ls180.v:6621$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6621$2300_Y + connect \B $eq$ls180.v:6621$2301_Y + connect \Y $and$ls180.v:6621$2302_Y + end + attribute \src "ls180.v:6622.46-6622.104" + cell $and $and$ls180.v:6622$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6622$2303_Y + connect \Y $and$ls180.v:6622$2304_Y + end + attribute \src "ls180.v:6622.45-6622.155" + cell $and $and$ls180.v:6622$2306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6622$2304_Y + connect \B $eq$ls180.v:6622$2305_Y + connect \Y $and$ls180.v:6622$2306_Y + end + attribute \src "ls180.v:7003.109-7003.178" + cell $and $and$ls180.v:7003$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7003$2343_Y + connect \Y $and$ls180.v:7003$2344_Y + end + attribute \src "ls180.v:7003.184-7003.253" + cell $and $and$ls180.v:7003$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7003$2346_Y + connect \Y $and$ls180.v:7003$2347_Y + end + attribute \src "ls180.v:7003.259-7003.328" + cell $and $and$ls180.v:7003$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7003$2349_Y + connect \Y $and$ls180.v:7003$2350_Y + end + attribute \src "ls180.v:7003.40-7003.331" + cell $and $and$ls180.v:7003$2353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7003$2342_Y + connect \B $not$ls180.v:7003$2352_Y + connect \Y $and$ls180.v:7003$2353_Y + end + attribute \src "ls180.v:7003.39-7003.354" + cell $and $and$ls180.v:7003$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7003$2353_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7003$2354_Y + end + attribute \src "ls180.v:7027.109-7027.178" + cell $and $and$ls180.v:7027$2360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7027$2359_Y + connect \Y $and$ls180.v:7027$2360_Y + end + attribute \src "ls180.v:7027.184-7027.253" + cell $and $and$ls180.v:7027$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7027$2362_Y + connect \Y $and$ls180.v:7027$2363_Y + end + attribute \src "ls180.v:7027.259-7027.328" + cell $and $and$ls180.v:7027$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7027$2365_Y + connect \Y $and$ls180.v:7027$2366_Y + end + attribute \src "ls180.v:7027.40-7027.331" + cell $and $and$ls180.v:7027$2369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7027$2358_Y + connect \B $not$ls180.v:7027$2368_Y + connect \Y $and$ls180.v:7027$2369_Y + end + attribute \src "ls180.v:7027.39-7027.354" + cell $and $and$ls180.v:7027$2370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7027$2369_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7027$2370_Y + end + attribute \src "ls180.v:7051.109-7051.178" + cell $and $and$ls180.v:7051$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7051$2375_Y + connect \Y $and$ls180.v:7051$2376_Y + end + attribute \src "ls180.v:7051.184-7051.253" + cell $and $and$ls180.v:7051$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7051$2378_Y + connect \Y $and$ls180.v:7051$2379_Y + end + attribute \src "ls180.v:7051.259-7051.328" + cell $and $and$ls180.v:7051$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7051$2381_Y + connect \Y $and$ls180.v:7051$2382_Y + end + attribute \src "ls180.v:7051.40-7051.331" + cell $and $and$ls180.v:7051$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7051$2374_Y + connect \B $not$ls180.v:7051$2384_Y + connect \Y $and$ls180.v:7051$2385_Y + end + attribute \src "ls180.v:7051.39-7051.354" + cell $and $and$ls180.v:7051$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7051$2385_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7051$2386_Y + end + attribute \src "ls180.v:7075.109-7075.178" + cell $and $and$ls180.v:7075$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7075$2391_Y + connect \Y $and$ls180.v:7075$2392_Y + end + attribute \src "ls180.v:7075.184-7075.253" + cell $and $and$ls180.v:7075$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7075$2394_Y + connect \Y $and$ls180.v:7075$2395_Y + end + attribute \src "ls180.v:7075.259-7075.328" + cell $and $and$ls180.v:7075$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7075$2397_Y + connect \Y $and$ls180.v:7075$2398_Y + end + attribute \src "ls180.v:7075.40-7075.331" + cell $and $and$ls180.v:7075$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7075$2390_Y + connect \B $not$ls180.v:7075$2400_Y + connect \Y $and$ls180.v:7075$2401_Y + end + attribute \src "ls180.v:7075.39-7075.354" + cell $and $and$ls180.v:7075$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7075$2401_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7075$2402_Y + end + attribute \src "ls180.v:7280.39-7280.104" + cell $and $and$ls180.v:7280$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7280$2414_Y + end + attribute \src "ls180.v:7280.38-7280.145" + cell $and $and$ls180.v:7280$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7280$2414_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7280$2415_Y + end + attribute \src "ls180.v:7283.39-7283.104" + cell $and $and$ls180.v:7283$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7283$2416_Y + end + attribute \src "ls180.v:7283.38-7283.145" + cell $and $and$ls180.v:7283$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7283$2416_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7283$2417_Y + end + attribute \src "ls180.v:7286.39-7286.82" + cell $and $and$ls180.v:7286$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7286$2418_Y + end + attribute \src "ls180.v:7286.38-7286.112" + cell $and $and$ls180.v:7286$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7286$2418_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7286$2419_Y + end + attribute \src "ls180.v:7297.39-7297.104" + cell $and $and$ls180.v:7297$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7297$2421_Y + end + attribute \src "ls180.v:7297.38-7297.145" + cell $and $and$ls180.v:7297$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7297$2421_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7297$2422_Y + end + attribute \src "ls180.v:7300.39-7300.104" + cell $and $and$ls180.v:7300$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7300$2423_Y + end + attribute \src "ls180.v:7300.38-7300.145" + cell $and $and$ls180.v:7300$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7300$2423_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7300$2424_Y + end + attribute \src "ls180.v:7303.39-7303.82" + cell $and $and$ls180.v:7303$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7303$2425_Y + end + attribute \src "ls180.v:7303.38-7303.112" + cell $and $and$ls180.v:7303$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7303$2425_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7303$2426_Y + end + attribute \src "ls180.v:7314.39-7314.104" + cell $and $and$ls180.v:7314$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7314$2428_Y + end + attribute \src "ls180.v:7314.38-7314.144" + cell $and $and$ls180.v:7314$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7314$2428_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7314$2429_Y + end + attribute \src "ls180.v:7317.39-7317.104" + cell $and $and$ls180.v:7317$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7317$2430_Y + end + attribute \src "ls180.v:7317.38-7317.144" + cell $and $and$ls180.v:7317$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7317$2430_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7317$2431_Y + end + attribute \src "ls180.v:7320.39-7320.82" + cell $and $and$ls180.v:7320$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7320$2432_Y + end + attribute \src "ls180.v:7320.38-7320.111" + cell $and $and$ls180.v:7320$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7320$2432_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7320$2433_Y + end + attribute \src "ls180.v:7331.39-7331.104" + cell $and $and$ls180.v:7331$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7331$2435_Y + end + attribute \src "ls180.v:7331.38-7331.149" + cell $and $and$ls180.v:7331$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7331$2435_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7331$2436_Y + end + attribute \src "ls180.v:7334.39-7334.104" + cell $and $and$ls180.v:7334$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7334$2437_Y + end + attribute \src "ls180.v:7334.38-7334.149" + cell $and $and$ls180.v:7334$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7334$2437_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7334$2438_Y + end + attribute \src "ls180.v:7337.39-7337.82" + cell $and $and$ls180.v:7337$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7337$2439_Y + end + attribute \src "ls180.v:7337.38-7337.116" + cell $and $and$ls180.v:7337$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7337$2439_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7337$2440_Y + end + attribute \src "ls180.v:7348.39-7348.104" + cell $and $and$ls180.v:7348$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7348$2442_Y + end + attribute \src "ls180.v:7348.38-7348.150" + cell $and $and$ls180.v:7348$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7348$2442_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7348$2443_Y + end + attribute \src "ls180.v:7351.39-7351.104" + cell $and $and$ls180.v:7351$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7351$2444_Y + end + attribute \src "ls180.v:7351.38-7351.150" + cell $and $and$ls180.v:7351$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7351$2444_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7351$2445_Y + end + attribute \src "ls180.v:7354.39-7354.82" + cell $and $and$ls180.v:7354$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7354$2446_Y + end + attribute \src "ls180.v:7354.38-7354.117" + cell $and $and$ls180.v:7354$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7354$2446_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7354$2447_Y + end + attribute \src "ls180.v:7573.18-7573.68" + cell $and $and$ls180.v:7573$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_dfi_p0_wrdata_en + connect \B \main_dfi_p0_wrdata_mask [0] + connect \Y $and$ls180.v:7573$2454_Y + end + attribute \src "ls180.v:7574.18-7574.68" + cell $and $and$ls180.v:7574$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_dfi_p0_wrdata_en + connect \B \main_dfi_p0_wrdata_mask [1] + connect \Y $and$ls180.v:7574$2455_Y + end + attribute \src "ls180.v:7576.17-7576.67" + cell $and $and$ls180.v:7576$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7576$2456_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7576$2457_Y + end + attribute \src "ls180.v:7655.8-7655.67" + cell $and $and$ls180.v:7655$2488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7655$2488_Y + end + attribute \src "ls180.v:7655.7-7655.102" + cell $and $and$ls180.v:7655$2490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7655$2488_Y + connect \B $not$ls180.v:7655$2489_Y + connect \Y $and$ls180.v:7655$2490_Y + end + attribute \src "ls180.v:7674.7-7674.75" + cell $and $and$ls180.v:7674$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7674$2493_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7674$2494_Y + end + attribute \src "ls180.v:7678.8-7678.59" + cell $and $and$ls180.v:7678$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:7678$2495_Y + end + attribute \src "ls180.v:7678.7-7678.90" + cell $and $and$ls180.v:7678$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7678$2495_Y + connect \B $not$ls180.v:7678$2496_Y + connect \Y $and$ls180.v:7678$2497_Y + end + attribute \src "ls180.v:7686.7-7686.56" + cell $and $and$ls180.v:7686$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7686$2498_Y + connect \Y $and$ls180.v:7686$2499_Y + end + attribute \src "ls180.v:7714.7-7714.75" + cell $and $and$ls180.v:7714$2506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7714$2505_Y + connect \Y $and$ls180.v:7714$2506_Y + end + attribute \src "ls180.v:7756.8-7756.131" + cell $and $and$ls180.v:7756$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7756$2512_Y + end + attribute \src "ls180.v:7756.7-7756.190" + cell $and $and$ls180.v:7756$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7756$2512_Y + connect \B $not$ls180.v:7756$2513_Y + connect \Y $and$ls180.v:7756$2514_Y + end + attribute \src "ls180.v:7762.8-7762.131" + cell $and $and$ls180.v:7762$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7762$2517_Y + end + attribute \src "ls180.v:7762.7-7762.190" + cell $and $and$ls180.v:7762$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7762$2517_Y + connect \B $not$ls180.v:7762$2518_Y + connect \Y $and$ls180.v:7762$2519_Y + end + attribute \src "ls180.v:7802.8-7802.131" + cell $and $and$ls180.v:7802$2528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7802$2528_Y + end + attribute \src "ls180.v:7802.7-7802.190" + cell $and $and$ls180.v:7802$2530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7802$2528_Y + connect \B $not$ls180.v:7802$2529_Y + connect \Y $and$ls180.v:7802$2530_Y + end + attribute \src "ls180.v:7808.8-7808.131" + cell $and $and$ls180.v:7808$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7808$2533_Y + end + attribute \src "ls180.v:7808.7-7808.190" + cell $and $and$ls180.v:7808$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7808$2533_Y + connect \B $not$ls180.v:7808$2534_Y + connect \Y $and$ls180.v:7808$2535_Y + end + attribute \src "ls180.v:7848.8-7848.131" + cell $and $and$ls180.v:7848$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7848$2544_Y + end + attribute \src "ls180.v:7848.7-7848.190" + cell $and $and$ls180.v:7848$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7848$2544_Y + connect \B $not$ls180.v:7848$2545_Y + connect \Y $and$ls180.v:7848$2546_Y + end + attribute \src "ls180.v:7854.8-7854.131" + cell $and $and$ls180.v:7854$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7854$2549_Y + end + attribute \src "ls180.v:7854.7-7854.190" + cell $and $and$ls180.v:7854$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7854$2549_Y + connect \B $not$ls180.v:7854$2550_Y + connect \Y $and$ls180.v:7854$2551_Y + end + attribute \src "ls180.v:7894.8-7894.131" + cell $and $and$ls180.v:7894$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7894$2560_Y + end + attribute \src "ls180.v:7894.7-7894.190" + cell $and $and$ls180.v:7894$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7894$2560_Y + connect \B $not$ls180.v:7894$2561_Y + connect \Y $and$ls180.v:7894$2562_Y + end + attribute \src "ls180.v:7900.8-7900.131" + cell $and $and$ls180.v:7900$2565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7900$2565_Y + end + attribute \src "ls180.v:7900.7-7900.190" + cell $and $and$ls180.v:7900$2567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7900$2565_Y + connect \B $not$ls180.v:7900$2566_Y + connect \Y $and$ls180.v:7900$2567_Y + end + attribute \src "ls180.v:8097.48-8097.124" + cell $and $and$ls180.v:8097$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8097$2591_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:8097$2592_Y + end + attribute \src "ls180.v:8097.130-8097.206" + cell $and $and$ls180.v:8097$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8097$2594_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:8097$2595_Y + end + attribute \src "ls180.v:8097.212-8097.288" + cell $and $and$ls180.v:8097$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8097$2597_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:8097$2598_Y + end + attribute \src "ls180.v:8097.294-8097.370" + cell $and $and$ls180.v:8097$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8097$2600_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:8097$2601_Y + end + attribute \src "ls180.v:8098.49-8098.125" + cell $and $and$ls180.v:8098$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8098$2603_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:8098$2604_Y + end + attribute \src "ls180.v:8098.131-8098.207" + cell $and $and$ls180.v:8098$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8098$2606_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:8098$2607_Y + end + attribute \src "ls180.v:8098.213-8098.289" + cell $and $and$ls180.v:8098$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8098$2609_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:8098$2610_Y + end + attribute \src "ls180.v:8098.295-8098.371" + cell $and $and$ls180.v:8098$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8098$2612_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:8098$2613_Y + end + attribute \src "ls180.v:8117.8-8117.49" + cell $and $and$ls180.v:8117$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:8117$2616_Y + end + attribute \src "ls180.v:8120.8-8120.53" + cell $and $and$ls180.v:8120$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:8120$2617_Y + end + attribute \src "ls180.v:8125.8-8125.59" + cell $and $and$ls180.v:8125$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:8125$2618_Y + connect \Y $and$ls180.v:8125$2619_Y + end + attribute \src "ls180.v:8125.7-8125.90" + cell $and $and$ls180.v:8125$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8125$2619_Y + connect \B $not$ls180.v:8125$2620_Y + connect \Y $and$ls180.v:8125$2621_Y + end + attribute \src "ls180.v:8131.8-8131.59" + cell $and $and$ls180.v:8131$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:8131$2622_Y + end + attribute \src "ls180.v:8155.8-8155.48" + cell $and $and$ls180.v:8155$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8155$2628_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:8155$2629_Y + end + attribute \src "ls180.v:8188.7-8188.57" + cell $and $and$ls180.v:8188$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8188$2634_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:8188$2635_Y + end + attribute \src "ls180.v:8195.7-8195.57" + cell $and $and$ls180.v:8195$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8195$2636_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:8195$2637_Y + end + attribute \src "ls180.v:8205.8-8205.75" + cell $and $and$ls180.v:8205$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8205$2638_Y + end + attribute \src "ls180.v:8205.7-8205.107" + cell $and $and$ls180.v:8205$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8205$2638_Y + connect \B $not$ls180.v:8205$2639_Y + connect \Y $and$ls180.v:8205$2640_Y + end + attribute \src "ls180.v:8211.8-8211.75" + cell $and $and$ls180.v:8211$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8211$2643_Y + end + attribute \src "ls180.v:8211.7-8211.107" + cell $and $and$ls180.v:8211$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8211$2643_Y + connect \B $not$ls180.v:8211$2644_Y + connect \Y $and$ls180.v:8211$2645_Y + end + attribute \src "ls180.v:8227.8-8227.75" + cell $and $and$ls180.v:8227$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8227$2649_Y + end + attribute \src "ls180.v:8227.7-8227.107" + cell $and $and$ls180.v:8227$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8227$2649_Y + connect \B $not$ls180.v:8227$2650_Y + connect \Y $and$ls180.v:8227$2651_Y + end + attribute \src "ls180.v:8233.8-8233.75" + cell $and $and$ls180.v:8233$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8233$2654_Y + end + attribute \src "ls180.v:8233.7-8233.107" + cell $and $and$ls180.v:8233$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8233$2654_Y + connect \B $not$ls180.v:8233$2655_Y + connect \Y $and$ls180.v:8233$2656_Y + end + attribute \src "ls180.v:8381.7-8381.96" + cell $and $and$ls180.v:8381$2684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8381$2684_Y + end + attribute \src "ls180.v:8382.8-8382.93" + cell $and $and$ls180.v:8382$2685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8382$2685_Y + end + attribute \src "ls180.v:8390.8-8390.93" + cell $and $and$ls180.v:8390$2686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8390$2686_Y + end + attribute \src "ls180.v:8462.7-8462.98" + cell $and $and$ls180.v:8462$2696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8462$2696_Y + end + attribute \src "ls180.v:8463.8-8463.95" + cell $and $and$ls180.v:8463$2697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8463$2697_Y + end + attribute \src "ls180.v:8471.8-8471.95" + cell $and $and$ls180.v:8471$2698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8471$2698_Y + end + attribute \src "ls180.v:8541.7-8541.100" + cell $and $and$ls180.v:8541$2708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8541$2708_Y + end + attribute \src "ls180.v:8542.8-8542.97" + cell $and $and$ls180.v:8542$2709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8542$2709_Y + end + attribute \src "ls180.v:8550.8-8550.97" + cell $and $and$ls180.v:8550$2710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8550$2710_Y + end + attribute \src "ls180.v:8641.7-8641.82" + cell $and $and$ls180.v:8641$2716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8641$2716_Y + end + attribute \src "ls180.v:8644.7-8644.82" + cell $and $and$ls180.v:8644$2717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8644$2717_Y + end + attribute \src "ls180.v:8647.7-8647.82" + cell $and $and$ls180.v:8647$2718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8647$2718_Y + end + attribute \src "ls180.v:8650.7-8650.82" + cell $and $and$ls180.v:8650$2719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8650$2719_Y + end + attribute \src "ls180.v:8653.7-8653.82" + cell $and $and$ls180.v:8653$2720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8653$2720_Y + end + attribute \src "ls180.v:8658.7-8658.82" + cell $and $and$ls180.v:8658$2721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8658$2721_Y + end + attribute \src "ls180.v:8663.7-8663.82" + cell $and $and$ls180.v:8663$2722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8663$2722_Y + end + attribute \src "ls180.v:8668.7-8668.82" + cell $and $and$ls180.v:8668$2723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8668$2723_Y + end + attribute \src "ls180.v:8673.7-8673.82" + cell $and $and$ls180.v:8673$2724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8673$2724_Y + end + attribute \src "ls180.v:8738.8-8738.83" + cell $and $and$ls180.v:8738$2727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8738$2727_Y + end + attribute \src "ls180.v:8738.7-8738.119" + cell $and $and$ls180.v:8738$2729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8738$2727_Y + connect \B $not$ls180.v:8738$2728_Y + connect \Y $and$ls180.v:8738$2729_Y + end + attribute \src "ls180.v:8744.8-8744.83" + cell $and $and$ls180.v:8744$2732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8744$2732_Y + end + attribute \src "ls180.v:8744.7-8744.119" + cell $and $and$ls180.v:8744$2734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8744$2732_Y + connect \B $not$ls180.v:8744$2733_Y + connect \Y $and$ls180.v:8744$2734_Y + end + attribute \src "ls180.v:8764.7-8764.88" + cell $and $and$ls180.v:8764$2741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8764$2741_Y + end + attribute \src "ls180.v:8765.8-8765.85" + cell $and $and$ls180.v:8765$2742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8765$2742_Y + end + attribute \src "ls180.v:8773.8-8773.85" + cell $and $and$ls180.v:8773$2743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8773$2743_Y + end + attribute \src "ls180.v:8829.7-8829.88" + cell $and $and$ls180.v:8829$2747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8829$2747_Y + end + attribute \src "ls180.v:8836.8-8836.83" + cell $and $and$ls180.v:8836$2749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8836$2749_Y + end + attribute \src "ls180.v:8836.7-8836.119" + cell $and $and$ls180.v:8836$2751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8836$2749_Y + connect \B $not$ls180.v:8836$2750_Y + connect \Y $and$ls180.v:8836$2751_Y + end + attribute \src "ls180.v:8842.8-8842.83" + cell $and $and$ls180.v:8842$2754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8842$2754_Y + end + attribute \src "ls180.v:8842.7-8842.119" + cell $and $and$ls180.v:8842$2756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8842$2754_Y + connect \B $not$ls180.v:8842$2755_Y + connect \Y $and$ls180.v:8842$2756_Y + end + attribute \src "ls180.v:2885.30-2885.76" + cell $eq $eq$ls180.v:2885$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2885$30_Y + end + attribute \src "ls180.v:2892.11-2892.42" + cell $eq $eq$ls180.v:2892$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2892$35_Y + end + attribute \src "ls180.v:2945.30-2945.76" + cell $eq $eq$ls180.v:2945$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2945$41_Y + end + attribute \src "ls180.v:2952.11-2952.42" + cell $eq $eq$ls180.v:2952$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2952$46_Y + end + attribute \src "ls180.v:3005.33-3005.58" + cell $eq $eq$ls180.v:3005$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_sel + connect \B 1'0 + connect \Y $eq$ls180.v:3005$52_Y + end + attribute \src "ls180.v:3012.11-3012.45" + cell $eq $eq$ls180.v:3012$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_counter + connect \B 1'1 + connect \Y $eq$ls180.v:3012$57_Y + end + attribute \src "ls180.v:3216.34-3216.65" + cell $eq $eq$ls180.v:3216$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3216$122_Y + end + attribute \src "ls180.v:3220.68-3220.102" + cell $eq $eq$ls180.v:3220$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3220$125_Y + end + attribute \src "ls180.v:3264.43-3264.134" + cell $eq $eq$ls180.v:3264$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3264$130_Y + end + attribute \src "ls180.v:3281.47-3281.88" + cell $eq $eq$ls180.v:3281$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3281$143_Y + end + attribute \src "ls180.v:3421.43-3421.134" + cell $eq $eq$ls180.v:3421$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3421$160_Y + end + attribute \src "ls180.v:3438.47-3438.88" + cell $eq $eq$ls180.v:3438$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3438$173_Y + end + attribute \src "ls180.v:3578.43-3578.134" + cell $eq $eq$ls180.v:3578$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3578$190_Y + end + attribute \src "ls180.v:3595.47-3595.88" + cell $eq $eq$ls180.v:3595$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3595$203_Y + end + attribute \src "ls180.v:3735.43-3735.134" + cell $eq $eq$ls180.v:3735$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3735$220_Y + end + attribute \src "ls180.v:3752.47-3752.88" + cell $eq $eq$ls180.v:3752$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3752$233_Y + end + attribute \src "ls180.v:3889.32-3889.56" + cell $eq $eq$ls180.v:3889$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3889$280_Y + end + attribute \src "ls180.v:3890.32-3890.56" + cell $eq $eq$ls180.v:3890$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3890$281_Y + end + attribute \src "ls180.v:3901.339-3901.418" + cell $eq $eq$ls180.v:3901$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3901$295_Y + end + attribute \src "ls180.v:3901.423-3901.504" + cell $eq $eq$ls180.v:3901$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3901$296_Y + end + attribute \src "ls180.v:3902.339-3902.418" + cell $eq $eq$ls180.v:3902$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3902$308_Y + end + attribute \src "ls180.v:3902.423-3902.504" + cell $eq $eq$ls180.v:3902$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3902$309_Y + end + attribute \src "ls180.v:3903.339-3903.418" + cell $eq $eq$ls180.v:3903$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3903$321_Y + end + attribute \src "ls180.v:3903.423-3903.504" + cell $eq $eq$ls180.v:3903$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3903$322_Y + end + attribute \src "ls180.v:3904.339-3904.418" + cell $eq $eq$ls180.v:3904$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3904$334_Y + end + attribute \src "ls180.v:3904.423-3904.504" + cell $eq $eq$ls180.v:3904$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3904$335_Y + end + attribute \src "ls180.v:3934.339-3934.418" + cell $eq $eq$ls180.v:3934$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3934$353_Y + end + attribute \src "ls180.v:3934.423-3934.504" + cell $eq $eq$ls180.v:3934$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3934$354_Y + end + attribute \src "ls180.v:3935.339-3935.418" + cell $eq $eq$ls180.v:3935$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3935$366_Y + end + attribute \src "ls180.v:3935.423-3935.504" + cell $eq $eq$ls180.v:3935$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3935$367_Y + end + attribute \src "ls180.v:3936.339-3936.418" + cell $eq $eq$ls180.v:3936$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3936$379_Y + end + attribute \src "ls180.v:3936.423-3936.504" + cell $eq $eq$ls180.v:3936$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3936$380_Y + end + attribute \src "ls180.v:3937.339-3937.418" + cell $eq $eq$ls180.v:3937$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3937$392_Y + end + attribute \src "ls180.v:3937.423-3937.504" + cell $eq $eq$ls180.v:3937$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3937$393_Y + end + attribute \src "ls180.v:3966.78-3966.113" + cell $eq $eq$ls180.v:3966$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3966$402_Y + end + attribute \src "ls180.v:3969.78-3969.113" + cell $eq $eq$ls180.v:3969$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3969$405_Y + end + attribute \src "ls180.v:3975.78-3975.113" + cell $eq $eq$ls180.v:3975$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3975$409_Y + end + attribute \src "ls180.v:3978.78-3978.113" + cell $eq $eq$ls180.v:3978$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3978$412_Y + end + attribute \src "ls180.v:3984.78-3984.113" + cell $eq $eq$ls180.v:3984$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3984$416_Y + end + attribute \src "ls180.v:3987.78-3987.113" + cell $eq $eq$ls180.v:3987$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3987$419_Y + end + attribute \src "ls180.v:3993.78-3993.113" + cell $eq $eq$ls180.v:3993$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3993$423_Y + end + attribute \src "ls180.v:3996.78-3996.113" + cell $eq $eq$ls180.v:3996$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3996$426_Y + end + attribute \src "ls180.v:4077.42-4077.82" + cell $eq $eq$ls180.v:4077$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4077$449_Y + end + attribute \src "ls180.v:4077.145-4077.178" + cell $eq $eq$ls180.v:4077$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4077$450_Y + end + attribute \src "ls180.v:4077.220-4077.253" + cell $eq $eq$ls180.v:4077$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4077$453_Y + end + attribute \src "ls180.v:4077.295-4077.328" + cell $eq $eq$ls180.v:4077$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4077$456_Y + end + attribute \src "ls180.v:4082.42-4082.82" + cell $eq $eq$ls180.v:4082$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4082$465_Y + end + attribute \src "ls180.v:4082.145-4082.178" + cell $eq $eq$ls180.v:4082$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4082$466_Y + end + attribute \src "ls180.v:4082.220-4082.253" + cell $eq $eq$ls180.v:4082$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4082$469_Y + end + attribute \src "ls180.v:4082.295-4082.328" + cell $eq $eq$ls180.v:4082$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4082$472_Y + end + attribute \src "ls180.v:4087.42-4087.82" + cell $eq $eq$ls180.v:4087$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4087$481_Y + end + attribute \src "ls180.v:4087.145-4087.178" + cell $eq $eq$ls180.v:4087$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4087$482_Y + end + attribute \src "ls180.v:4087.220-4087.253" + cell $eq $eq$ls180.v:4087$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4087$485_Y + end + attribute \src "ls180.v:4087.295-4087.328" + cell $eq $eq$ls180.v:4087$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4087$488_Y + end + attribute \src "ls180.v:4092.42-4092.82" + cell $eq $eq$ls180.v:4092$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4092$497_Y + end + attribute \src "ls180.v:4092.145-4092.178" + cell $eq $eq$ls180.v:4092$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4092$498_Y + end + attribute \src "ls180.v:4092.220-4092.253" + cell $eq $eq$ls180.v:4092$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4092$501_Y + end + attribute \src "ls180.v:4092.295-4092.328" + cell $eq $eq$ls180.v:4092$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4092$504_Y + end + attribute \src "ls180.v:4097.44-4097.77" + cell $eq $eq$ls180.v:4097$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$513_Y + end + attribute \src "ls180.v:4097.83-4097.123" + cell $eq $eq$ls180.v:4097$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4097$514_Y + end + attribute \src "ls180.v:4097.186-4097.219" + cell $eq $eq$ls180.v:4097$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$515_Y + end + attribute \src "ls180.v:4097.261-4097.294" + cell $eq $eq$ls180.v:4097$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$518_Y + end + attribute \src "ls180.v:4097.336-4097.369" + cell $eq $eq$ls180.v:4097$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$521_Y + end + attribute \src "ls180.v:4097.418-4097.451" + cell $eq $eq$ls180.v:4097$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$529_Y + end + attribute \src "ls180.v:4097.457-4097.497" + cell $eq $eq$ls180.v:4097$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4097$530_Y + end + attribute \src "ls180.v:4097.560-4097.593" + cell $eq $eq$ls180.v:4097$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$531_Y + end + attribute \src "ls180.v:4097.635-4097.668" + cell $eq $eq$ls180.v:4097$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$534_Y + end + attribute \src "ls180.v:4097.710-4097.743" + cell $eq $eq$ls180.v:4097$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$537_Y + end + attribute \src "ls180.v:4097.792-4097.825" + cell $eq $eq$ls180.v:4097$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$545_Y + end + attribute \src "ls180.v:4097.831-4097.871" + cell $eq $eq$ls180.v:4097$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4097$546_Y + end + attribute \src "ls180.v:4097.934-4097.967" + cell $eq $eq$ls180.v:4097$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$547_Y + end + attribute \src "ls180.v:4097.1009-4097.1042" + cell $eq $eq$ls180.v:4097$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$550_Y + end + attribute \src "ls180.v:4097.1084-4097.1117" + cell $eq $eq$ls180.v:4097$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$553_Y + end + attribute \src "ls180.v:4097.1166-4097.1199" + cell $eq $eq$ls180.v:4097$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$561_Y + end + attribute \src "ls180.v:4097.1205-4097.1245" + cell $eq $eq$ls180.v:4097$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4097$562_Y + end + attribute \src "ls180.v:4097.1308-4097.1341" + cell $eq $eq$ls180.v:4097$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$563_Y + end + attribute \src "ls180.v:4097.1383-4097.1416" + cell $eq $eq$ls180.v:4097$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$566_Y + end + attribute \src "ls180.v:4097.1458-4097.1491" + cell $eq $eq$ls180.v:4097$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4097$569_Y + end + attribute \src "ls180.v:4156.29-4156.57" + cell $eq $eq$ls180.v:4156$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4156$582_Y + end + attribute \src "ls180.v:4163.11-4163.41" + cell $eq $eq$ls180.v:4163$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4163$587_Y + end + attribute \src "ls180.v:4331.37-4331.111" + cell $eq $eq$ls180.v:4331$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4331$653_Y + connect \Y $eq$ls180.v:4331$654_Y + end + attribute \src "ls180.v:4332.37-4332.105" + cell $eq $eq$ls180.v:4332$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4332$655_Y + connect \Y $eq$ls180.v:4332$656_Y + end + attribute \src "ls180.v:4359.10-4359.67" + cell $eq $eq$ls180.v:4359$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spimaster27_count + connect \B $sub$ls180.v:4359$659_Y + connect \Y $eq$ls180.v:4359$660_Y + end + attribute \src "ls180.v:4389.35-4389.108" + cell $eq $eq$ls180.v:4389$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4389$661_Y + connect \Y $eq$ls180.v:4389$662_Y + end + attribute \src "ls180.v:4390.35-4390.102" + cell $eq $eq$ls180.v:4390$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4390$663_Y + connect \Y $eq$ls180.v:4390$664_Y + end + attribute \src "ls180.v:4418.10-4418.65" + cell $eq $eq$ls180.v:4418$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_count + connect \B $sub$ls180.v:4418$667_Y + connect \Y $eq$ls180.v:4418$668_Y + end + attribute \src "ls180.v:4522.10-4522.40" + cell $eq $eq$ls180.v:4522$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4522$695_Y + end + attribute \src "ls180.v:4579.10-4579.39" + cell $eq $eq$ls180.v:4579$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4579$698_Y + end + attribute \src "ls180.v:4596.10-4596.39" + cell $eq $eq$ls180.v:4596$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4596$700_Y + end + attribute \src "ls180.v:4624.38-4624.88" + cell $eq $eq$ls180.v:4624$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4624$702_Y + end + attribute \src "ls180.v:4674.9-4674.40" + cell $eq $eq$ls180.v:4674$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4674$712_Y + end + attribute \src "ls180.v:4683.36-4683.105" + cell $eq $eq$ls180.v:4683$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4683$713_Y + connect \Y $eq$ls180.v:4683$714_Y + end + attribute \src "ls180.v:4702.9-4702.40" + cell $eq $eq$ls180.v:4702$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4702$718_Y + end + attribute \src "ls180.v:4714.10-4714.39" + cell $eq $eq$ls180.v:4714$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4714$720_Y + end + attribute \src "ls180.v:4751.39-4751.94" + cell $eq $eq$ls180.v:4751$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4751$724_Y + end + attribute \src "ls180.v:4788.32-4788.89" + cell $eq $eq$ls180.v:4788$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4788$733_Y + end + attribute \src "ls180.v:4836.10-4836.40" + cell $eq $eq$ls180.v:4836$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4836$737_Y + end + attribute \src "ls180.v:4885.40-4885.98" + cell $eq $eq$ls180.v:4885$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4885$739_Y + end + attribute \src "ls180.v:4936.9-4936.41" + cell $eq $eq$ls180.v:4936$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4936$749_Y + end + attribute \src "ls180.v:4945.37-4945.123" + cell $eq $eq$ls180.v:4945$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:4945$751_Y + connect \Y $eq$ls180.v:4945$752_Y + end + attribute \src "ls180.v:4968.9-4968.41" + cell $eq $eq$ls180.v:4968$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4968$755_Y + end + attribute \src "ls180.v:4978.10-4978.41" + cell $eq $eq$ls180.v:4978$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:4978$757_Y + end + attribute \src "ls180.v:5147.9-5147.47" + cell $eq $eq$ls180.v:5147$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5147$939_Y + end + attribute \src "ls180.v:5177.10-5177.48" + cell $eq $eq$ls180.v:5177$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5177$940_Y + end + attribute \src "ls180.v:5208.10-5208.78" + cell $eq $eq$ls180.v:5208$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:5208$945_Y + end + attribute \src "ls180.v:5208.83-5208.151" + cell $eq $eq$ls180.v:5208$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:5208$946_Y + end + attribute \src "ls180.v:5208.157-5208.225" + cell $eq $eq$ls180.v:5208$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:5208$948_Y + end + attribute \src "ls180.v:5208.231-5208.299" + cell $eq $eq$ls180.v:5208$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:5208$950_Y + end + attribute \src "ls180.v:5216.7-5216.44" + cell $eq $eq$ls180.v:5216$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5216$954_Y + end + attribute \src "ls180.v:5226.7-5226.44" + cell $eq $eq$ls180.v:5226$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5226$957_Y + end + attribute \src "ls180.v:5236.7-5236.44" + cell $eq $eq$ls180.v:5236$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5236$960_Y + end + attribute \src "ls180.v:5246.7-5246.44" + cell $eq $eq$ls180.v:5246$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5246$963_Y + end + attribute \src "ls180.v:5370.36-5370.64" + cell $eq $eq$ls180.v:5370$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5370$1014_Y + end + attribute \src "ls180.v:5376.10-5376.39" + cell $eq $eq$ls180.v:5376$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5376$1017_Y + end + attribute \src "ls180.v:5377.11-5377.39" + cell $eq $eq$ls180.v:5377$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5377$1018_Y + end + attribute \src "ls180.v:5389.34-5389.63" + cell $eq $eq$ls180.v:5389$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5389$1019_Y + end + attribute \src "ls180.v:5390.9-5390.37" + cell $eq $eq$ls180.v:5390$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5390$1020_Y + end + attribute \src "ls180.v:5397.10-5397.55" + cell $eq $eq$ls180.v:5397$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5397$1021_Y + end + attribute \src "ls180.v:5403.12-5403.41" + cell $eq $eq$ls180.v:5403$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5403$1022_Y + end + attribute \src "ls180.v:5406.13-5406.42" + cell $eq $eq$ls180.v:5406$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5406$1023_Y + end + attribute \src "ls180.v:5428.10-5428.76" + cell $eq $eq$ls180.v:5428$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5428$1027_Y + connect \Y $eq$ls180.v:5428$1028_Y + end + attribute \src "ls180.v:5443.35-5443.101" + cell $eq $eq$ls180.v:5443$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5443$1030_Y + connect \Y $eq$ls180.v:5443$1031_Y + end + attribute \src "ls180.v:5445.10-5445.56" + cell $eq $eq$ls180.v:5445$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5445$1032_Y + end + attribute \src "ls180.v:5454.12-5454.78" + cell $eq $eq$ls180.v:5454$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5454$1035_Y + connect \Y $eq$ls180.v:5454$1036_Y + end + attribute \src "ls180.v:5461.11-5461.57" + cell $eq $eq$ls180.v:5461$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5461$1037_Y + end + attribute \src "ls180.v:5578.10-5578.105" + cell $eq $eq$ls180.v:5578$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5578$1053_Y + connect \Y $eq$ls180.v:5578$1054_Y + end + attribute \src "ls180.v:5668.39-5668.106" + cell $eq $eq$ls180.v:5668$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5668$1059_Y + connect \Y $eq$ls180.v:5668$1060_Y + end + attribute \src "ls180.v:5698.44-5698.82" + cell $eq $eq$ls180.v:5698$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5698$1063_Y + end + attribute \src "ls180.v:5699.43-5699.81" + cell $eq $eq$ls180.v:5699$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 3'111 + connect \Y $eq$ls180.v:5699$1064_Y + end + attribute \src "ls180.v:5811.68-5811.89" + cell $eq $eq$ls180.v:5811$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5811$1080_Y + end + attribute \src "ls180.v:5812.68-5812.89" + cell $eq $eq$ls180.v:5812$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5812$1082_Y + end + attribute \src "ls180.v:5813.71-5813.92" + cell $eq $eq$ls180.v:5813$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5813$1084_Y + end + attribute \src "ls180.v:5814.57-5814.78" + cell $eq $eq$ls180.v:5814$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5814$1086_Y + end + attribute \src "ls180.v:5815.57-5815.78" + cell $eq $eq$ls180.v:5815$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5815$1088_Y + end + attribute \src "ls180.v:5816.68-5816.89" + cell $eq $eq$ls180.v:5816$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5816$1090_Y + end + attribute \src "ls180.v:5817.68-5817.89" + cell $eq $eq$ls180.v:5817$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5817$1092_Y + end + attribute \src "ls180.v:5818.71-5818.92" + cell $eq $eq$ls180.v:5818$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5818$1094_Y + end + attribute \src "ls180.v:5819.57-5819.78" + cell $eq $eq$ls180.v:5819$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5819$1096_Y + end + attribute \src "ls180.v:5820.57-5820.78" + cell $eq $eq$ls180.v:5820$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5820$1098_Y + end + attribute \src "ls180.v:5824.27-5824.59" + cell $eq $eq$ls180.v:5824$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 26 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:4] + connect \B 1'0 + connect \Y $eq$ls180.v:5824$1101_Y + end + attribute \src "ls180.v:5825.27-5825.60" + cell $eq $eq$ls180.v:5825$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 26 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:4] + connect \B 4'1110 + connect \Y $eq$ls180.v:5825$1102_Y + end + attribute \src "ls180.v:5826.27-5826.68" + cell $eq $eq$ls180.v:5826$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 28 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:2] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5826$1103_Y + end + attribute \src "ls180.v:5827.27-5827.65" + cell $eq $eq$ls180.v:5827$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5827$1104_Y + end + attribute \src "ls180.v:5828.27-5828.59" + cell $eq $eq$ls180.v:5828$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 1'1 + connect \Y $eq$ls180.v:5828$1105_Y + end + attribute \src "ls180.v:5829.27-5829.59" + cell $eq $eq$ls180.v:5829$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'10 + connect \Y $eq$ls180.v:5829$1106_Y + end + attribute \src "ls180.v:5830.27-5830.59" + cell $eq $eq$ls180.v:5830$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'11 + connect \Y $eq$ls180.v:5830$1107_Y + end + attribute \src "ls180.v:5831.27-5831.59" + cell $eq $eq$ls180.v:5831$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 3'100 + connect \Y $eq$ls180.v:5831$1108_Y + end + attribute \src "ls180.v:5832.27-5832.61" + cell $eq $eq$ls180.v:5832$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:22] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5832$1109_Y + end + attribute \src "ls180.v:5833.27-5833.65" + cell $eq $eq$ls180.v:5833$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:13] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5833$1110_Y + end + attribute \src "ls180.v:5929.24-5929.45" + cell $eq $eq$ls180.v:5929$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:5929$1162_Y + end + attribute \src "ls180.v:5930.32-5930.77" + cell $eq $eq$ls180.v:5930$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:8] + connect \B 1'0 + connect \Y $eq$ls180.v:5930$1163_Y + end + attribute \src "ls180.v:5932.97-5932.141" + cell $eq $eq$ls180.v:5932$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5932$1165_Y + end + attribute \src "ls180.v:5933.100-5933.144" + cell $eq $eq$ls180.v:5933$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5933$1169_Y + end + attribute \src "ls180.v:5935.99-5935.143" + cell $eq $eq$ls180.v:5935$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5935$1172_Y + end + attribute \src "ls180.v:5936.102-5936.146" + cell $eq $eq$ls180.v:5936$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5936$1176_Y + end + attribute \src "ls180.v:5938.99-5938.143" + cell $eq $eq$ls180.v:5938$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5938$1179_Y + end + attribute \src "ls180.v:5939.102-5939.146" + cell $eq $eq$ls180.v:5939$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5939$1183_Y + end + attribute \src "ls180.v:5941.99-5941.143" + cell $eq $eq$ls180.v:5941$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5941$1186_Y + end + attribute \src "ls180.v:5942.102-5942.146" + cell $eq $eq$ls180.v:5942$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5942$1190_Y + end + attribute \src "ls180.v:5944.99-5944.143" + cell $eq $eq$ls180.v:5944$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5944$1193_Y + end + attribute \src "ls180.v:5945.102-5945.146" + cell $eq $eq$ls180.v:5945$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5945$1197_Y + end + attribute \src "ls180.v:5947.102-5947.146" + cell $eq $eq$ls180.v:5947$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5947$1200_Y + end + attribute \src "ls180.v:5948.105-5948.149" + cell $eq $eq$ls180.v:5948$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5948$1204_Y + end + attribute \src "ls180.v:5950.102-5950.146" + cell $eq $eq$ls180.v:5950$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5950$1207_Y + end + attribute \src "ls180.v:5951.105-5951.149" + cell $eq $eq$ls180.v:5951$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5951$1211_Y + end + attribute \src "ls180.v:5953.102-5953.146" + cell $eq $eq$ls180.v:5953$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5953$1214_Y + end + attribute \src "ls180.v:5954.105-5954.149" + cell $eq $eq$ls180.v:5954$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5954$1218_Y + end + attribute \src "ls180.v:5956.102-5956.146" + cell $eq $eq$ls180.v:5956$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5956$1221_Y + end + attribute \src "ls180.v:5957.105-5957.149" + cell $eq $eq$ls180.v:5957$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5957$1225_Y + end + attribute \src "ls180.v:5968.32-5968.77" + cell $eq $eq$ls180.v:5968$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:8] + connect \B 3'110 + connect \Y $eq$ls180.v:5968$1227_Y + end + attribute \src "ls180.v:5970.94-5970.138" + cell $eq $eq$ls180.v:5970$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5970$1229_Y + end + attribute \src "ls180.v:5971.97-5971.141" + cell $eq $eq$ls180.v:5971$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5971$1233_Y + end + attribute \src "ls180.v:5973.94-5973.138" + cell $eq $eq$ls180.v:5973$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5973$1236_Y + end + attribute \src "ls180.v:5974.97-5974.141" + cell $eq $eq$ls180.v:5974$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5974$1240_Y + end + attribute \src "ls180.v:5976.94-5976.138" + cell $eq $eq$ls180.v:5976$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5976$1243_Y + end + attribute \src "ls180.v:5977.97-5977.141" + cell $eq $eq$ls180.v:5977$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5977$1247_Y + end + attribute \src "ls180.v:5979.94-5979.138" + cell $eq $eq$ls180.v:5979$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5979$1250_Y + end + attribute \src "ls180.v:5980.97-5980.141" + cell $eq $eq$ls180.v:5980$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5980$1254_Y + end + attribute \src "ls180.v:5982.95-5982.139" + cell $eq $eq$ls180.v:5982$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5982$1257_Y + end + attribute \src "ls180.v:5983.98-5983.142" + cell $eq $eq$ls180.v:5983$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5983$1261_Y + end + attribute \src "ls180.v:5985.95-5985.139" + cell $eq $eq$ls180.v:5985$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5985$1264_Y + end + attribute \src "ls180.v:5986.98-5986.142" + cell $eq $eq$ls180.v:5986$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5986$1268_Y + end + attribute \src "ls180.v:5994.32-5994.78" + cell $eq $eq$ls180.v:5994$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:8] + connect \B 4'1100 + connect \Y $eq$ls180.v:5994$1270_Y + end + attribute \src "ls180.v:5996.93-5996.135" + cell $eq $eq$ls180.v:5996$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5996$1272_Y + end + attribute \src "ls180.v:5997.96-5997.138" + cell $eq $eq$ls180.v:5997$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5997$1276_Y + end + attribute \src "ls180.v:5999.92-5999.134" + cell $eq $eq$ls180.v:5999$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5999$1279_Y + end + attribute \src "ls180.v:6000.95-6000.137" + cell $eq $eq$ls180.v:6000$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:6000$1283_Y + end + attribute \src "ls180.v:6008.32-6008.78" + cell $eq $eq$ls180.v:6008$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:8] + connect \B 4'1010 + connect \Y $eq$ls180.v:6008$1285_Y + end + attribute \src "ls180.v:6010.98-6010.142" + cell $eq $eq$ls180.v:6010$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6010$1287_Y + end + attribute \src "ls180.v:6011.101-6011.145" + cell $eq $eq$ls180.v:6011$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6011$1291_Y + end + attribute \src "ls180.v:6013.97-6013.141" + cell $eq $eq$ls180.v:6013$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6013$1294_Y + end + attribute \src "ls180.v:6014.100-6014.144" + cell $eq $eq$ls180.v:6014$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6014$1298_Y + end + attribute \src "ls180.v:6016.97-6016.141" + cell $eq $eq$ls180.v:6016$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6016$1301_Y + end + attribute \src "ls180.v:6017.100-6017.144" + cell $eq $eq$ls180.v:6017$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6017$1305_Y + end + attribute \src "ls180.v:6019.97-6019.141" + cell $eq $eq$ls180.v:6019$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6019$1308_Y + end + attribute \src "ls180.v:6020.100-6020.144" + cell $eq $eq$ls180.v:6020$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6020$1312_Y + end + attribute \src "ls180.v:6022.97-6022.141" + cell $eq $eq$ls180.v:6022$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6022$1315_Y + end + attribute \src "ls180.v:6023.100-6023.144" + cell $eq $eq$ls180.v:6023$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6023$1319_Y + end + attribute \src "ls180.v:6025.98-6025.142" + cell $eq $eq$ls180.v:6025$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6025$1322_Y + end + attribute \src "ls180.v:6026.101-6026.145" + cell $eq $eq$ls180.v:6026$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6026$1326_Y + end + attribute \src "ls180.v:6028.98-6028.142" + cell $eq $eq$ls180.v:6028$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6028$1329_Y + end + attribute \src "ls180.v:6029.101-6029.145" + cell $eq $eq$ls180.v:6029$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6029$1333_Y + end + attribute \src "ls180.v:6031.98-6031.142" + cell $eq $eq$ls180.v:6031$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6031$1336_Y + end + attribute \src "ls180.v:6032.101-6032.145" + cell $eq $eq$ls180.v:6032$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6032$1340_Y + end + attribute \src "ls180.v:6034.98-6034.142" + cell $eq $eq$ls180.v:6034$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6034$1343_Y + end + attribute \src "ls180.v:6035.101-6035.145" + cell $eq $eq$ls180.v:6035$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6035$1347_Y + end + attribute \src "ls180.v:6045.32-6045.78" + cell $eq $eq$ls180.v:6045$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:8] + connect \B 4'1011 + connect \Y $eq$ls180.v:6045$1349_Y + end + attribute \src "ls180.v:6047.98-6047.142" + cell $eq $eq$ls180.v:6047$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6047$1351_Y + end + attribute \src "ls180.v:6048.101-6048.145" + cell $eq $eq$ls180.v:6048$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6048$1355_Y + end + attribute \src "ls180.v:6050.97-6050.141" + cell $eq $eq$ls180.v:6050$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6050$1358_Y + end + attribute \src "ls180.v:6051.100-6051.144" + cell $eq $eq$ls180.v:6051$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6051$1362_Y + end + attribute \src "ls180.v:6053.97-6053.141" + cell $eq $eq$ls180.v:6053$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6053$1365_Y + end + attribute \src "ls180.v:6054.100-6054.144" + cell $eq $eq$ls180.v:6054$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6054$1369_Y + end + attribute \src "ls180.v:6056.97-6056.141" + cell $eq $eq$ls180.v:6056$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6056$1372_Y + end + attribute \src "ls180.v:6057.100-6057.144" + cell $eq $eq$ls180.v:6057$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6057$1376_Y + end + attribute \src "ls180.v:6059.97-6059.141" + cell $eq $eq$ls180.v:6059$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6059$1379_Y + end + attribute \src "ls180.v:6060.100-6060.144" + cell $eq $eq$ls180.v:6060$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6060$1383_Y + end + attribute \src "ls180.v:6062.98-6062.142" + cell $eq $eq$ls180.v:6062$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6062$1386_Y + end + attribute \src "ls180.v:6063.101-6063.145" + cell $eq $eq$ls180.v:6063$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6063$1390_Y + end + attribute \src "ls180.v:6065.98-6065.142" + cell $eq $eq$ls180.v:6065$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6065$1393_Y + end + attribute \src "ls180.v:6066.101-6066.145" + cell $eq $eq$ls180.v:6066$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6066$1397_Y + end + attribute \src "ls180.v:6068.98-6068.142" + cell $eq $eq$ls180.v:6068$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6068$1400_Y + end + attribute \src "ls180.v:6069.101-6069.145" + cell $eq $eq$ls180.v:6069$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6069$1404_Y + end + attribute \src "ls180.v:6071.98-6071.142" + cell $eq $eq$ls180.v:6071$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6071$1407_Y + end + attribute \src "ls180.v:6072.101-6072.145" + cell $eq $eq$ls180.v:6072$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6072$1411_Y + end + attribute \src "ls180.v:6082.32-6082.78" + cell $eq $eq$ls180.v:6082$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:8] + connect \B 4'1111 + connect \Y $eq$ls180.v:6082$1413_Y + end + attribute \src "ls180.v:6084.100-6084.144" + cell $eq $eq$ls180.v:6084$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6084$1415_Y + end + attribute \src "ls180.v:6085.103-6085.147" + cell $eq $eq$ls180.v:6085$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6085$1419_Y + end + attribute \src "ls180.v:6087.100-6087.144" + cell $eq $eq$ls180.v:6087$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6087$1422_Y + end + attribute \src "ls180.v:6088.103-6088.147" + cell $eq $eq$ls180.v:6088$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6088$1426_Y + end + attribute \src "ls180.v:6090.100-6090.144" + cell $eq $eq$ls180.v:6090$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6090$1429_Y + end + attribute \src "ls180.v:6091.103-6091.147" + cell $eq $eq$ls180.v:6091$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6091$1433_Y + end + attribute \src "ls180.v:6093.100-6093.144" + cell $eq $eq$ls180.v:6093$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6093$1436_Y + end + attribute \src "ls180.v:6094.103-6094.147" + cell $eq $eq$ls180.v:6094$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6094$1440_Y + end + attribute \src "ls180.v:6096.100-6096.144" + cell $eq $eq$ls180.v:6096$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6096$1443_Y + end + attribute \src "ls180.v:6097.103-6097.147" + cell $eq $eq$ls180.v:6097$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6097$1447_Y + end + attribute \src "ls180.v:6099.100-6099.144" + cell $eq $eq$ls180.v:6099$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6099$1450_Y + end + attribute \src "ls180.v:6100.103-6100.147" + cell $eq $eq$ls180.v:6100$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6100$1454_Y + end + attribute \src "ls180.v:6102.100-6102.144" + cell $eq $eq$ls180.v:6102$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6102$1457_Y + end + attribute \src "ls180.v:6103.103-6103.147" + cell $eq $eq$ls180.v:6103$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6103$1461_Y + end + attribute \src "ls180.v:6105.100-6105.144" + cell $eq $eq$ls180.v:6105$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6105$1464_Y + end + attribute \src "ls180.v:6106.103-6106.147" + cell $eq $eq$ls180.v:6106$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6106$1468_Y + end + attribute \src "ls180.v:6108.102-6108.146" + cell $eq $eq$ls180.v:6108$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6108$1471_Y + end + attribute \src "ls180.v:6109.105-6109.149" + cell $eq $eq$ls180.v:6109$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6109$1475_Y + end + attribute \src "ls180.v:6111.102-6111.146" + cell $eq $eq$ls180.v:6111$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6111$1478_Y + end + attribute \src "ls180.v:6112.105-6112.149" + cell $eq $eq$ls180.v:6112$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6112$1482_Y + end + attribute \src "ls180.v:6114.102-6114.147" + cell $eq $eq$ls180.v:6114$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6114$1485_Y + end + attribute \src "ls180.v:6115.105-6115.150" + cell $eq $eq$ls180.v:6115$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6115$1489_Y + end + attribute \src "ls180.v:6117.102-6117.147" + cell $eq $eq$ls180.v:6117$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6117$1492_Y + end + attribute \src "ls180.v:6118.105-6118.150" + cell $eq $eq$ls180.v:6118$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6118$1496_Y + end + attribute \src "ls180.v:6120.102-6120.147" + cell $eq $eq$ls180.v:6120$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6120$1499_Y + end + attribute \src "ls180.v:6121.105-6121.150" + cell $eq $eq$ls180.v:6121$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6121$1503_Y + end + attribute \src "ls180.v:6123.99-6123.144" + cell $eq $eq$ls180.v:6123$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6123$1506_Y + end + attribute \src "ls180.v:6124.102-6124.147" + cell $eq $eq$ls180.v:6124$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6124$1510_Y + end + attribute \src "ls180.v:6126.100-6126.145" + cell $eq $eq$ls180.v:6126$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6126$1513_Y + end + attribute \src "ls180.v:6127.103-6127.148" + cell $eq $eq$ls180.v:6127$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6127$1517_Y + end + attribute \src "ls180.v:6144.32-6144.78" + cell $eq $eq$ls180.v:6144$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:8] + connect \B 4'1110 + connect \Y $eq$ls180.v:6144$1519_Y + end + attribute \src "ls180.v:6146.104-6146.148" + cell $eq $eq$ls180.v:6146$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6146$1521_Y + end + attribute \src "ls180.v:6147.107-6147.151" + cell $eq $eq$ls180.v:6147$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6147$1525_Y + end + attribute \src "ls180.v:6149.104-6149.148" + cell $eq $eq$ls180.v:6149$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6149$1528_Y + end + attribute \src "ls180.v:6150.107-6150.151" + cell $eq $eq$ls180.v:6150$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6150$1532_Y + end + attribute \src "ls180.v:6152.104-6152.148" + cell $eq $eq$ls180.v:6152$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6152$1535_Y + end + attribute \src "ls180.v:6153.107-6153.151" + cell $eq $eq$ls180.v:6153$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6153$1539_Y + end + attribute \src "ls180.v:6155.104-6155.148" + cell $eq $eq$ls180.v:6155$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6155$1542_Y + end + attribute \src "ls180.v:6156.107-6156.151" + cell $eq $eq$ls180.v:6156$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6156$1546_Y + end + attribute \src "ls180.v:6158.103-6158.147" + cell $eq $eq$ls180.v:6158$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6158$1549_Y + end + attribute \src "ls180.v:6159.106-6159.150" + cell $eq $eq$ls180.v:6159$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6159$1553_Y + end + attribute \src "ls180.v:6161.103-6161.147" + cell $eq $eq$ls180.v:6161$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6161$1556_Y + end + attribute \src "ls180.v:6162.106-6162.150" + cell $eq $eq$ls180.v:6162$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6162$1560_Y + end + attribute \src "ls180.v:6164.103-6164.147" + cell $eq $eq$ls180.v:6164$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6164$1563_Y + end + attribute \src "ls180.v:6165.106-6165.150" + cell $eq $eq$ls180.v:6165$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6165$1567_Y + end + attribute \src "ls180.v:6167.103-6167.147" + cell $eq $eq$ls180.v:6167$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6167$1570_Y + end + attribute \src "ls180.v:6168.106-6168.150" + cell $eq $eq$ls180.v:6168$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6168$1574_Y + end + attribute \src "ls180.v:6170.94-6170.138" + cell $eq $eq$ls180.v:6170$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6170$1577_Y + end + attribute \src "ls180.v:6171.97-6171.141" + cell $eq $eq$ls180.v:6171$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6171$1581_Y + end + attribute \src "ls180.v:6173.105-6173.149" + cell $eq $eq$ls180.v:6173$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6173$1584_Y + end + attribute \src "ls180.v:6174.108-6174.152" + cell $eq $eq$ls180.v:6174$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6174$1588_Y + end + attribute \src "ls180.v:6176.105-6176.150" + cell $eq $eq$ls180.v:6176$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6176$1591_Y + end + attribute \src "ls180.v:6177.108-6177.153" + cell $eq $eq$ls180.v:6177$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6177$1595_Y + end + attribute \src "ls180.v:6179.105-6179.150" + cell $eq $eq$ls180.v:6179$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6179$1598_Y + end + attribute \src "ls180.v:6180.108-6180.153" + cell $eq $eq$ls180.v:6180$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6180$1602_Y + end + attribute \src "ls180.v:6182.105-6182.150" + cell $eq $eq$ls180.v:6182$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6182$1605_Y + end + attribute \src "ls180.v:6183.108-6183.153" + cell $eq $eq$ls180.v:6183$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6183$1609_Y + end + attribute \src "ls180.v:6185.105-6185.150" + cell $eq $eq$ls180.v:6185$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6185$1612_Y + end + attribute \src "ls180.v:6186.108-6186.153" + cell $eq $eq$ls180.v:6186$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6186$1616_Y + end + attribute \src "ls180.v:6188.105-6188.150" + cell $eq $eq$ls180.v:6188$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6188$1619_Y + end + attribute \src "ls180.v:6189.108-6189.153" + cell $eq $eq$ls180.v:6189$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6189$1623_Y + end + attribute \src "ls180.v:6191.104-6191.149" + cell $eq $eq$ls180.v:6191$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6191$1626_Y + end + attribute \src "ls180.v:6192.107-6192.152" + cell $eq $eq$ls180.v:6192$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6192$1630_Y + end + attribute \src "ls180.v:6194.104-6194.149" + cell $eq $eq$ls180.v:6194$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6194$1633_Y + end + attribute \src "ls180.v:6195.107-6195.152" + cell $eq $eq$ls180.v:6195$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6195$1637_Y + end + attribute \src "ls180.v:6197.104-6197.149" + cell $eq $eq$ls180.v:6197$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6197$1640_Y + end + attribute \src "ls180.v:6198.107-6198.152" + cell $eq $eq$ls180.v:6198$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6198$1644_Y + end + attribute \src "ls180.v:6200.104-6200.149" + cell $eq $eq$ls180.v:6200$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6200$1647_Y + end + attribute \src "ls180.v:6201.107-6201.152" + cell $eq $eq$ls180.v:6201$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6201$1651_Y + end + attribute \src "ls180.v:6203.104-6203.149" + cell $eq $eq$ls180.v:6203$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6203$1654_Y + end + attribute \src "ls180.v:6204.107-6204.152" + cell $eq $eq$ls180.v:6204$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6204$1658_Y + end + attribute \src "ls180.v:6206.104-6206.149" + cell $eq $eq$ls180.v:6206$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6206$1661_Y + end + attribute \src "ls180.v:6207.107-6207.152" + cell $eq $eq$ls180.v:6207$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6207$1665_Y + end + attribute \src "ls180.v:6209.104-6209.149" + cell $eq $eq$ls180.v:6209$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6209$1668_Y + end + attribute \src "ls180.v:6210.107-6210.152" + cell $eq $eq$ls180.v:6210$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6210$1672_Y + end + attribute \src "ls180.v:6212.104-6212.149" + cell $eq $eq$ls180.v:6212$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6212$1675_Y + end + attribute \src "ls180.v:6213.107-6213.152" + cell $eq $eq$ls180.v:6213$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6213$1679_Y + end + attribute \src "ls180.v:6215.104-6215.149" + cell $eq $eq$ls180.v:6215$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6215$1682_Y + end + attribute \src "ls180.v:6216.107-6216.152" + cell $eq $eq$ls180.v:6216$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6216$1686_Y + end + attribute \src "ls180.v:6218.104-6218.149" + cell $eq $eq$ls180.v:6218$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6218$1689_Y + end + attribute \src "ls180.v:6219.107-6219.152" + cell $eq $eq$ls180.v:6219$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6219$1693_Y + end + attribute \src "ls180.v:6221.100-6221.145" + cell $eq $eq$ls180.v:6221$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6221$1696_Y + end + attribute \src "ls180.v:6222.103-6222.148" + cell $eq $eq$ls180.v:6222$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6222$1700_Y + end + attribute \src "ls180.v:6224.101-6224.146" + cell $eq $eq$ls180.v:6224$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6224$1703_Y + end + attribute \src "ls180.v:6225.104-6225.149" + cell $eq $eq$ls180.v:6225$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6225$1707_Y + end + attribute \src "ls180.v:6227.104-6227.149" + cell $eq $eq$ls180.v:6227$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6227$1710_Y + end + attribute \src "ls180.v:6228.107-6228.152" + cell $eq $eq$ls180.v:6228$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6228$1714_Y + end + attribute \src "ls180.v:6230.104-6230.149" + cell $eq $eq$ls180.v:6230$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6230$1717_Y + end + attribute \src "ls180.v:6231.107-6231.152" + cell $eq $eq$ls180.v:6231$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6231$1721_Y + end + attribute \src "ls180.v:6233.103-6233.148" + cell $eq $eq$ls180.v:6233$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6233$1724_Y + end + attribute \src "ls180.v:6234.106-6234.151" + cell $eq $eq$ls180.v:6234$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6234$1728_Y + end + attribute \src "ls180.v:6236.103-6236.148" + cell $eq $eq$ls180.v:6236$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6236$1731_Y + end + attribute \src "ls180.v:6237.106-6237.151" + cell $eq $eq$ls180.v:6237$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6237$1735_Y + end + attribute \src "ls180.v:6239.103-6239.148" + cell $eq $eq$ls180.v:6239$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6239$1738_Y + end + attribute \src "ls180.v:6240.106-6240.151" + cell $eq $eq$ls180.v:6240$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6240$1742_Y + end + attribute \src "ls180.v:6242.103-6242.148" + cell $eq $eq$ls180.v:6242$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6242$1745_Y + end + attribute \src "ls180.v:6243.106-6243.151" + cell $eq $eq$ls180.v:6243$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6243$1749_Y + end + attribute \src "ls180.v:6279.32-6279.78" + cell $eq $eq$ls180.v:6279$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:8] + connect \B 5'10000 + connect \Y $eq$ls180.v:6279$1751_Y + end + attribute \src "ls180.v:6281.100-6281.144" + cell $eq $eq$ls180.v:6281$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6281$1753_Y + end + attribute \src "ls180.v:6282.103-6282.147" + cell $eq $eq$ls180.v:6282$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6282$1757_Y + end + attribute \src "ls180.v:6284.100-6284.144" + cell $eq $eq$ls180.v:6284$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6284$1760_Y + end + attribute \src "ls180.v:6285.103-6285.147" + cell $eq $eq$ls180.v:6285$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6285$1764_Y + end + attribute \src "ls180.v:6287.100-6287.144" + cell $eq $eq$ls180.v:6287$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6287$1767_Y + end + attribute \src "ls180.v:6288.103-6288.147" + cell $eq $eq$ls180.v:6288$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6288$1771_Y + end + attribute \src "ls180.v:6290.100-6290.144" + cell $eq $eq$ls180.v:6290$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6290$1774_Y + end + attribute \src "ls180.v:6291.103-6291.147" + cell $eq $eq$ls180.v:6291$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6291$1778_Y + end + attribute \src "ls180.v:6293.100-6293.144" + cell $eq $eq$ls180.v:6293$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6293$1781_Y + end + attribute \src "ls180.v:6294.103-6294.147" + cell $eq $eq$ls180.v:6294$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6294$1785_Y + end + attribute \src "ls180.v:6296.100-6296.144" + cell $eq $eq$ls180.v:6296$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6296$1788_Y + end + attribute \src "ls180.v:6297.103-6297.147" + cell $eq $eq$ls180.v:6297$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6297$1792_Y + end + attribute \src "ls180.v:6299.100-6299.144" + cell $eq $eq$ls180.v:6299$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6299$1795_Y + end + attribute \src "ls180.v:6300.103-6300.147" + cell $eq $eq$ls180.v:6300$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6300$1799_Y + end + attribute \src "ls180.v:6302.100-6302.144" + cell $eq $eq$ls180.v:6302$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6302$1802_Y + end + attribute \src "ls180.v:6303.103-6303.147" + cell $eq $eq$ls180.v:6303$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6303$1806_Y + end + attribute \src "ls180.v:6305.102-6305.146" + cell $eq $eq$ls180.v:6305$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6305$1809_Y + end + attribute \src "ls180.v:6306.105-6306.149" + cell $eq $eq$ls180.v:6306$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6306$1813_Y + end + attribute \src "ls180.v:6308.102-6308.146" + cell $eq $eq$ls180.v:6308$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6308$1816_Y + end + attribute \src "ls180.v:6309.105-6309.149" + cell $eq $eq$ls180.v:6309$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6309$1820_Y + end + attribute \src "ls180.v:6311.102-6311.147" + cell $eq $eq$ls180.v:6311$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6311$1823_Y + end + attribute \src "ls180.v:6312.105-6312.150" + cell $eq $eq$ls180.v:6312$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6312$1827_Y + end + attribute \src "ls180.v:6314.102-6314.147" + cell $eq $eq$ls180.v:6314$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6314$1830_Y + end + attribute \src "ls180.v:6315.105-6315.150" + cell $eq $eq$ls180.v:6315$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6315$1834_Y + end + attribute \src "ls180.v:6317.102-6317.147" + cell $eq $eq$ls180.v:6317$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6317$1837_Y + end + attribute \src "ls180.v:6318.105-6318.150" + cell $eq $eq$ls180.v:6318$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6318$1841_Y + end + attribute \src "ls180.v:6320.99-6320.144" + cell $eq $eq$ls180.v:6320$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6320$1844_Y + end + attribute \src "ls180.v:6321.102-6321.147" + cell $eq $eq$ls180.v:6321$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6321$1848_Y + end + attribute \src "ls180.v:6323.100-6323.145" + cell $eq $eq$ls180.v:6323$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6323$1851_Y + end + attribute \src "ls180.v:6324.103-6324.148" + cell $eq $eq$ls180.v:6324$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6324$1855_Y + end + attribute \src "ls180.v:6326.102-6326.147" + cell $eq $eq$ls180.v:6326$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6326$1858_Y + end + attribute \src "ls180.v:6327.105-6327.150" + cell $eq $eq$ls180.v:6327$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6327$1862_Y + end + attribute \src "ls180.v:6329.102-6329.147" + cell $eq $eq$ls180.v:6329$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6329$1865_Y + end + attribute \src "ls180.v:6330.105-6330.150" + cell $eq $eq$ls180.v:6330$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6330$1869_Y + end + attribute \src "ls180.v:6332.102-6332.147" + cell $eq $eq$ls180.v:6332$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6332$1872_Y + end + attribute \src "ls180.v:6333.105-6333.150" + cell $eq $eq$ls180.v:6333$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6333$1876_Y + end + attribute \src "ls180.v:6335.102-6335.147" + cell $eq $eq$ls180.v:6335$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6335$1879_Y + end + attribute \src "ls180.v:6336.105-6336.150" + cell $eq $eq$ls180.v:6336$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6336$1883_Y + end + attribute \src "ls180.v:6358.32-6358.78" + cell $eq $eq$ls180.v:6358$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:8] + connect \B 4'1101 + connect \Y $eq$ls180.v:6358$1885_Y + end + attribute \src "ls180.v:6360.102-6360.146" + cell $eq $eq$ls180.v:6360$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6360$1887_Y + end + attribute \src "ls180.v:6361.105-6361.149" + cell $eq $eq$ls180.v:6361$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6361$1891_Y + end + attribute \src "ls180.v:6363.107-6363.151" + cell $eq $eq$ls180.v:6363$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6363$1894_Y + end + attribute \src "ls180.v:6364.110-6364.154" + cell $eq $eq$ls180.v:6364$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6364$1898_Y + end + attribute \src "ls180.v:6366.107-6366.151" + cell $eq $eq$ls180.v:6366$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6366$1901_Y + end + attribute \src "ls180.v:6367.110-6367.154" + cell $eq $eq$ls180.v:6367$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6367$1905_Y + end + attribute \src "ls180.v:6369.100-6369.144" + cell $eq $eq$ls180.v:6369$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6369$1908_Y + end + attribute \src "ls180.v:6370.103-6370.147" + cell $eq $eq$ls180.v:6370$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6370$1912_Y + end + attribute \src "ls180.v:6375.32-6375.77" + cell $eq $eq$ls180.v:6375$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:8] + connect \B 2'11 + connect \Y $eq$ls180.v:6375$1914_Y + end + attribute \src "ls180.v:6377.104-6377.148" + cell $eq $eq$ls180.v:6377$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6377$1916_Y + end + attribute \src "ls180.v:6378.107-6378.151" + cell $eq $eq$ls180.v:6378$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6378$1920_Y + end + attribute \src "ls180.v:6380.108-6380.152" + cell $eq $eq$ls180.v:6380$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6380$1923_Y + end + attribute \src "ls180.v:6381.111-6381.155" + cell $eq $eq$ls180.v:6381$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6381$1927_Y + end + attribute \src "ls180.v:6383.98-6383.142" + cell $eq $eq$ls180.v:6383$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6383$1930_Y + end + attribute \src "ls180.v:6384.101-6384.145" + cell $eq $eq$ls180.v:6384$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6384$1934_Y + end + attribute \src "ls180.v:6386.108-6386.152" + cell $eq $eq$ls180.v:6386$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6386$1937_Y + end + attribute \src "ls180.v:6387.111-6387.155" + cell $eq $eq$ls180.v:6387$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6387$1941_Y + end + attribute \src "ls180.v:6389.108-6389.152" + cell $eq $eq$ls180.v:6389$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6389$1944_Y + end + attribute \src "ls180.v:6390.111-6390.155" + cell $eq $eq$ls180.v:6390$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6390$1948_Y + end + attribute \src "ls180.v:6392.109-6392.153" + cell $eq $eq$ls180.v:6392$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6392$1951_Y + end + attribute \src "ls180.v:6393.112-6393.156" + cell $eq $eq$ls180.v:6393$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6393$1955_Y + end + attribute \src "ls180.v:6395.107-6395.151" + cell $eq $eq$ls180.v:6395$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6395$1958_Y + end + attribute \src "ls180.v:6396.110-6396.154" + cell $eq $eq$ls180.v:6396$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6396$1962_Y + end + attribute \src "ls180.v:6398.107-6398.151" + cell $eq $eq$ls180.v:6398$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6398$1965_Y + end + attribute \src "ls180.v:6399.110-6399.154" + cell $eq $eq$ls180.v:6399$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6399$1969_Y + end + attribute \src "ls180.v:6401.107-6401.151" + cell $eq $eq$ls180.v:6401$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6401$1972_Y + end + attribute \src "ls180.v:6402.110-6402.154" + cell $eq $eq$ls180.v:6402$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6402$1976_Y + end + attribute \src "ls180.v:6404.107-6404.151" + cell $eq $eq$ls180.v:6404$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6404$1979_Y + end + attribute \src "ls180.v:6405.110-6405.154" + cell $eq $eq$ls180.v:6405$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6405$1983_Y + end + attribute \src "ls180.v:6420.33-6420.79" + cell $eq $eq$ls180.v:6420$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:8] + connect \B 4'1000 + connect \Y $eq$ls180.v:6420$1985_Y + end + attribute \src "ls180.v:6422.102-6422.147" + cell $eq $eq$ls180.v:6422$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6422$1987_Y + end + attribute \src "ls180.v:6423.105-6423.150" + cell $eq $eq$ls180.v:6423$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6423$1991_Y + end + attribute \src "ls180.v:6425.102-6425.147" + cell $eq $eq$ls180.v:6425$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6425$1994_Y + end + attribute \src "ls180.v:6426.105-6426.150" + cell $eq $eq$ls180.v:6426$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6426$1998_Y + end + attribute \src "ls180.v:6428.100-6428.145" + cell $eq $eq$ls180.v:6428$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6428$2001_Y + end + attribute \src "ls180.v:6429.103-6429.148" + cell $eq $eq$ls180.v:6429$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6429$2005_Y + end + attribute \src "ls180.v:6431.99-6431.144" + cell $eq $eq$ls180.v:6431$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6431$2008_Y + end + attribute \src "ls180.v:6432.102-6432.147" + cell $eq $eq$ls180.v:6432$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6432$2012_Y + end + attribute \src "ls180.v:6434.98-6434.143" + cell $eq $eq$ls180.v:6434$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6434$2015_Y + end + attribute \src "ls180.v:6435.101-6435.146" + cell $eq $eq$ls180.v:6435$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6435$2019_Y + end + attribute \src "ls180.v:6437.97-6437.142" + cell $eq $eq$ls180.v:6437$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6437$2022_Y + end + attribute \src "ls180.v:6438.100-6438.145" + cell $eq $eq$ls180.v:6438$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6438$2026_Y + end + attribute \src "ls180.v:6440.103-6440.148" + cell $eq $eq$ls180.v:6440$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6440$2029_Y + end + attribute \src "ls180.v:6441.106-6441.151" + cell $eq $eq$ls180.v:6441$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6441$2033_Y + end + attribute \src "ls180.v:6460.33-6460.79" + cell $eq $eq$ls180.v:6460$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:8] + connect \B 4'1001 + connect \Y $eq$ls180.v:6460$2036_Y + end + attribute \src "ls180.v:6462.102-6462.147" + cell $eq $eq$ls180.v:6462$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6462$2038_Y + end + attribute \src "ls180.v:6463.105-6463.150" + cell $eq $eq$ls180.v:6463$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6463$2042_Y + end + attribute \src "ls180.v:6465.102-6465.147" + cell $eq $eq$ls180.v:6465$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6465$2045_Y + end + attribute \src "ls180.v:6466.105-6466.150" + cell $eq $eq$ls180.v:6466$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6466$2049_Y + end + attribute \src "ls180.v:6468.100-6468.145" + cell $eq $eq$ls180.v:6468$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6468$2052_Y + end + attribute \src "ls180.v:6469.103-6469.148" + cell $eq $eq$ls180.v:6469$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6469$2056_Y + end + attribute \src "ls180.v:6471.99-6471.144" + cell $eq $eq$ls180.v:6471$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6471$2059_Y + end + attribute \src "ls180.v:6472.102-6472.147" + cell $eq $eq$ls180.v:6472$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6472$2063_Y + end + attribute \src "ls180.v:6474.98-6474.143" + cell $eq $eq$ls180.v:6474$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6474$2066_Y + end + attribute \src "ls180.v:6475.101-6475.146" + cell $eq $eq$ls180.v:6475$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6475$2070_Y + end + attribute \src "ls180.v:6477.97-6477.142" + cell $eq $eq$ls180.v:6477$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6477$2073_Y + end + attribute \src "ls180.v:6478.100-6478.145" + cell $eq $eq$ls180.v:6478$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6478$2077_Y + end + attribute \src "ls180.v:6480.103-6480.148" + cell $eq $eq$ls180.v:6480$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6480$2080_Y + end + attribute \src "ls180.v:6481.106-6481.151" + cell $eq $eq$ls180.v:6481$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6481$2084_Y + end + attribute \src "ls180.v:6483.106-6483.151" + cell $eq $eq$ls180.v:6483$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6483$2087_Y + end + attribute \src "ls180.v:6484.109-6484.154" + cell $eq $eq$ls180.v:6484$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6484$2091_Y + end + attribute \src "ls180.v:6486.106-6486.151" + cell $eq $eq$ls180.v:6486$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6486$2094_Y + end + attribute \src "ls180.v:6487.109-6487.154" + cell $eq $eq$ls180.v:6487$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6487$2098_Y + end + attribute \src "ls180.v:6508.33-6508.79" + cell $eq $eq$ls180.v:6508$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:8] + connect \B 2'10 + connect \Y $eq$ls180.v:6508$2101_Y + end + attribute \src "ls180.v:6510.99-6510.144" + cell $eq $eq$ls180.v:6510$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6510$2103_Y + end + attribute \src "ls180.v:6511.102-6511.147" + cell $eq $eq$ls180.v:6511$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6511$2107_Y + end + attribute \src "ls180.v:6513.99-6513.144" + cell $eq $eq$ls180.v:6513$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6513$2110_Y + end + attribute \src "ls180.v:6514.102-6514.147" + cell $eq $eq$ls180.v:6514$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6514$2114_Y + end + attribute \src "ls180.v:6516.99-6516.144" + cell $eq $eq$ls180.v:6516$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6516$2117_Y + end + attribute \src "ls180.v:6517.102-6517.147" + cell $eq $eq$ls180.v:6517$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6517$2121_Y + end + attribute \src "ls180.v:6519.99-6519.144" + cell $eq $eq$ls180.v:6519$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6519$2124_Y + end + attribute \src "ls180.v:6520.102-6520.147" + cell $eq $eq$ls180.v:6520$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6520$2128_Y + end + attribute \src "ls180.v:6522.101-6522.146" + cell $eq $eq$ls180.v:6522$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6522$2131_Y + end + attribute \src "ls180.v:6523.104-6523.149" + cell $eq $eq$ls180.v:6523$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6523$2135_Y + end + attribute \src "ls180.v:6525.101-6525.146" + cell $eq $eq$ls180.v:6525$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6525$2138_Y + end + attribute \src "ls180.v:6526.104-6526.149" + cell $eq $eq$ls180.v:6526$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6526$2142_Y + end + attribute \src "ls180.v:6528.101-6528.146" + cell $eq $eq$ls180.v:6528$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6528$2145_Y + end + attribute \src "ls180.v:6529.104-6529.149" + cell $eq $eq$ls180.v:6529$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6529$2149_Y + end + attribute \src "ls180.v:6531.101-6531.146" + cell $eq $eq$ls180.v:6531$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6531$2152_Y + end + attribute \src "ls180.v:6532.104-6532.149" + cell $eq $eq$ls180.v:6532$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6532$2156_Y + end + attribute \src "ls180.v:6534.97-6534.142" + cell $eq $eq$ls180.v:6534$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6534$2159_Y + end + attribute \src "ls180.v:6535.100-6535.145" + cell $eq $eq$ls180.v:6535$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6535$2163_Y + end + attribute \src "ls180.v:6537.107-6537.152" + cell $eq $eq$ls180.v:6537$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6537$2166_Y + end + attribute \src "ls180.v:6538.110-6538.155" + cell $eq $eq$ls180.v:6538$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6538$2170_Y + end + attribute \src "ls180.v:6540.100-6540.146" + cell $eq $eq$ls180.v:6540$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6540$2173_Y + end + attribute \src "ls180.v:6541.103-6541.149" + cell $eq $eq$ls180.v:6541$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6541$2177_Y + end + attribute \src "ls180.v:6543.100-6543.146" + cell $eq $eq$ls180.v:6543$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6543$2180_Y + end + attribute \src "ls180.v:6544.103-6544.149" + cell $eq $eq$ls180.v:6544$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6544$2184_Y + end + attribute \src "ls180.v:6546.100-6546.146" + cell $eq $eq$ls180.v:6546$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6546$2187_Y + end + attribute \src "ls180.v:6547.103-6547.149" + cell $eq $eq$ls180.v:6547$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6547$2191_Y + end + attribute \src "ls180.v:6549.100-6549.146" + cell $eq $eq$ls180.v:6549$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6549$2194_Y + end + attribute \src "ls180.v:6550.103-6550.149" + cell $eq $eq$ls180.v:6550$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6550$2198_Y + end + attribute \src "ls180.v:6552.112-6552.158" + cell $eq $eq$ls180.v:6552$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6552$2201_Y + end + attribute \src "ls180.v:6553.115-6553.161" + cell $eq $eq$ls180.v:6553$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6553$2205_Y + end + attribute \src "ls180.v:6555.113-6555.159" + cell $eq $eq$ls180.v:6555$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6555$2208_Y + end + attribute \src "ls180.v:6556.116-6556.162" + cell $eq $eq$ls180.v:6556$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6556$2212_Y + end + attribute \src "ls180.v:6558.104-6558.150" + cell $eq $eq$ls180.v:6558$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6558$2215_Y + end + attribute \src "ls180.v:6559.107-6559.153" + cell $eq $eq$ls180.v:6559$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6559$2219_Y + end + attribute \src "ls180.v:6576.33-6576.79" + cell $eq $eq$ls180.v:6576$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:8] + connect \B 3'101 + connect \Y $eq$ls180.v:6576$2221_Y + end + attribute \src "ls180.v:6578.90-6578.135" + cell $eq $eq$ls180.v:6578$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6578$2223_Y + end + attribute \src "ls180.v:6579.93-6579.138" + cell $eq $eq$ls180.v:6579$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6579$2227_Y + end + attribute \src "ls180.v:6581.100-6581.145" + cell $eq $eq$ls180.v:6581$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6581$2230_Y + end + attribute \src "ls180.v:6582.103-6582.148" + cell $eq $eq$ls180.v:6582$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6582$2234_Y + end + attribute \src "ls180.v:6584.101-6584.146" + cell $eq $eq$ls180.v:6584$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6584$2237_Y + end + attribute \src "ls180.v:6585.104-6585.149" + cell $eq $eq$ls180.v:6585$2241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6585$2241_Y + end + attribute \src "ls180.v:6587.105-6587.150" + cell $eq $eq$ls180.v:6587$2244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6587$2244_Y + end + attribute \src "ls180.v:6588.108-6588.153" + cell $eq $eq$ls180.v:6588$2248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6588$2248_Y + end + attribute \src "ls180.v:6590.106-6590.151" + cell $eq $eq$ls180.v:6590$2251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6590$2251_Y + end + attribute \src "ls180.v:6591.109-6591.154" + cell $eq $eq$ls180.v:6591$2255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6591$2255_Y + end + attribute \src "ls180.v:6593.104-6593.149" + cell $eq $eq$ls180.v:6593$2258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6593$2258_Y + end + attribute \src "ls180.v:6594.107-6594.152" + cell $eq $eq$ls180.v:6594$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6594$2262_Y + end + attribute \src "ls180.v:6596.101-6596.146" + cell $eq $eq$ls180.v:6596$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6596$2265_Y + end + attribute \src "ls180.v:6597.104-6597.149" + cell $eq $eq$ls180.v:6597$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6597$2269_Y + end + attribute \src "ls180.v:6599.100-6599.145" + cell $eq $eq$ls180.v:6599$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6599$2272_Y + end + attribute \src "ls180.v:6600.103-6600.148" + cell $eq $eq$ls180.v:6600$2276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6600$2276_Y + end + attribute \src "ls180.v:6610.33-6610.79" + cell $eq $eq$ls180.v:6610$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [13:8] + connect \B 3'100 + connect \Y $eq$ls180.v:6610$2278_Y + end + attribute \src "ls180.v:6612.106-6612.151" + cell $eq $eq$ls180.v:6612$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6612$2280_Y + end + attribute \src "ls180.v:6613.109-6613.154" + cell $eq $eq$ls180.v:6613$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6613$2284_Y + end + attribute \src "ls180.v:6615.106-6615.151" + cell $eq $eq$ls180.v:6615$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6615$2287_Y + end + attribute \src "ls180.v:6616.109-6616.154" + cell $eq $eq$ls180.v:6616$2291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6616$2291_Y + end + attribute \src "ls180.v:6618.106-6618.151" + cell $eq $eq$ls180.v:6618$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6618$2294_Y + end + attribute \src "ls180.v:6619.109-6619.154" + cell $eq $eq$ls180.v:6619$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6619$2298_Y + end + attribute \src "ls180.v:6621.106-6621.151" + cell $eq $eq$ls180.v:6621$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6621$2301_Y + end + attribute \src "ls180.v:6622.109-6622.154" + cell $eq $eq$ls180.v:6622$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6622$2305_Y + end + attribute \src "ls180.v:7003.41-7003.81" + cell $eq $eq$ls180.v:7003$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:7003$2342_Y + end + attribute \src "ls180.v:7003.144-7003.177" + cell $eq $eq$ls180.v:7003$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7003$2343_Y + end + attribute \src "ls180.v:7003.219-7003.252" + cell $eq $eq$ls180.v:7003$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7003$2346_Y + end + attribute \src "ls180.v:7003.294-7003.327" + cell $eq $eq$ls180.v:7003$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7003$2349_Y + end + attribute \src "ls180.v:7027.41-7027.81" + cell $eq $eq$ls180.v:7027$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:7027$2358_Y + end + attribute \src "ls180.v:7027.144-7027.177" + cell $eq $eq$ls180.v:7027$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7027$2359_Y + end + attribute \src "ls180.v:7027.219-7027.252" + cell $eq $eq$ls180.v:7027$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7027$2362_Y + end + attribute \src "ls180.v:7027.294-7027.327" + cell $eq $eq$ls180.v:7027$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7027$2365_Y + end + attribute \src "ls180.v:7051.41-7051.81" + cell $eq $eq$ls180.v:7051$2374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:7051$2374_Y + end + attribute \src "ls180.v:7051.144-7051.177" + cell $eq $eq$ls180.v:7051$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7051$2375_Y + end + attribute \src "ls180.v:7051.219-7051.252" + cell $eq $eq$ls180.v:7051$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7051$2378_Y + end + attribute \src "ls180.v:7051.294-7051.327" + cell $eq $eq$ls180.v:7051$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7051$2381_Y + end + attribute \src "ls180.v:7075.41-7075.81" + cell $eq $eq$ls180.v:7075$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:7075$2390_Y + end + attribute \src "ls180.v:7075.144-7075.177" + cell $eq $eq$ls180.v:7075$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7075$2391_Y + end + attribute \src "ls180.v:7075.219-7075.252" + cell $eq $eq$ls180.v:7075$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7075$2394_Y + end + attribute \src "ls180.v:7075.294-7075.327" + cell $eq $eq$ls180.v:7075$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7075$2397_Y + end + attribute \src "ls180.v:7659.8-7659.38" + cell $eq $eq$ls180.v:7659$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7659$2491_Y + end + attribute \src "ls180.v:7694.8-7694.42" + cell $eq $eq$ls180.v:7694$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7694$2502_Y + end + attribute \src "ls180.v:7714.38-7714.74" + cell $eq $eq$ls180.v:7714$2505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7714$2505_Y + end + attribute \src "ls180.v:7721.7-7721.43" + cell $eq $eq$ls180.v:7721$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7721$2507_Y + end + attribute \src "ls180.v:7728.7-7728.43" + cell $eq $eq$ls180.v:7728$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7728$2508_Y + end + attribute \src "ls180.v:7736.7-7736.43" + cell $eq $eq$ls180.v:7736$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7736$2509_Y + end + attribute \src "ls180.v:7788.9-7788.54" + cell $eq $eq$ls180.v:7788$2527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7788$2527_Y + end + attribute \src "ls180.v:7834.9-7834.54" + cell $eq $eq$ls180.v:7834$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7834$2543_Y + end + attribute \src "ls180.v:7880.9-7880.54" + cell $eq $eq$ls180.v:7880$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7880$2559_Y + end + attribute \src "ls180.v:7926.9-7926.54" + cell $eq $eq$ls180.v:7926$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7926$2575_Y + end + attribute \src "ls180.v:8076.9-8076.41" + cell $eq $eq$ls180.v:8076$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8076$2587_Y + end + attribute \src "ls180.v:8091.9-8091.41" + cell $eq $eq$ls180.v:8091$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8091$2590_Y + end + attribute \src "ls180.v:8097.49-8097.82" + cell $eq $eq$ls180.v:8097$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8097$2591_Y + end + attribute \src "ls180.v:8097.131-8097.164" + cell $eq $eq$ls180.v:8097$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8097$2594_Y + end + attribute \src "ls180.v:8097.213-8097.246" + cell $eq $eq$ls180.v:8097$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8097$2597_Y + end + attribute \src "ls180.v:8097.295-8097.328" + cell $eq $eq$ls180.v:8097$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8097$2600_Y + end + attribute \src "ls180.v:8098.50-8098.83" + cell $eq $eq$ls180.v:8098$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8098$2603_Y + end + attribute \src "ls180.v:8098.132-8098.165" + cell $eq $eq$ls180.v:8098$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8098$2606_Y + end + attribute \src "ls180.v:8098.214-8098.247" + cell $eq $eq$ls180.v:8098$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8098$2609_Y + end + attribute \src "ls180.v:8098.296-8098.329" + cell $eq $eq$ls180.v:8098$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8098$2612_Y + end + attribute \src "ls180.v:8133.9-8133.42" + cell $eq $eq$ls180.v:8133$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:8133$2624_Y + end + attribute \src "ls180.v:8136.10-8136.43" + cell $eq $eq$ls180.v:8136$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8136$2625_Y + end + attribute \src "ls180.v:8162.9-8162.42" + cell $eq $eq$ls180.v:8162$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:8162$2631_Y + end + attribute \src "ls180.v:8167.10-8167.43" + cell $eq $eq$ls180.v:8167$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8167$2632_Y + end + attribute \src "ls180.v:8374.9-8374.53" + cell $eq $eq$ls180.v:8374$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8374$2681_Y + end + attribute \src "ls180.v:8455.9-8455.54" + cell $eq $eq$ls180.v:8455$2693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8455$2693_Y + end + attribute \src "ls180.v:8534.9-8534.55" + cell $eq $eq$ls180.v:8534$2705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8534$2705_Y + end + attribute \src "ls180.v:8757.9-8757.49" + cell $eq $eq$ls180.v:8757$2738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8757$2738_Y + end + attribute \src "ls180.v:8333.8-8333.54" + cell $ge $ge$ls180.v:8333$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8333$2672_Y + connect \Y $ge$ls180.v:8333$2673_Y + end + attribute \src "ls180.v:8347.8-8347.54" + cell $ge $ge$ls180.v:8347$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8347$2676_Y + connect \Y $ge$ls180.v:8347$2677_Y + end + attribute \src "ls180.v:5255.47-5255.83" + cell $gt $gt$ls180.v:5255$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5255$965_Y + end + attribute \src "ls180.v:5261.7-5261.43" + cell $lt $lt$ls180.v:5261$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5261$968_Y + end + attribute \src "ls180.v:8328.8-8328.43" + cell $lt $lt$ls180.v:8328$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8328$2671_Y + end + attribute \src "ls180.v:8342.8-8342.43" + cell $lt $lt$ls180.v:8342$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8342$2675_Y + end + attribute \src "ls180.v:10244.33-10244.36" + cell $memrd $memrd$\mem$ls180.v:10244$2792 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:10244$2792_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10272.25-10272.30" + cell $memrd $memrd$\mem_1$ls180.v:10272$2818 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_1 + connect \CLK 1'x + connect \DATA $memrd$\mem_1$ls180.v:10272$2818_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10283.12-10283.19" + cell $memrd $memrd$\storage$ls180.v:10283$2823 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10283$2823_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10290.68-10290.75" + cell $memrd $memrd$\storage$ls180.v:10290$2825 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10290$2825_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10297.14-10297.23" + cell $memrd $memrd$\storage_1$ls180.v:10297$2830 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10297$2830_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10304.68-10304.77" + cell $memrd $memrd$\storage_1$ls180.v:10304$2832 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10304$2832_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10311.14-10311.23" + cell $memrd $memrd$\storage_2$ls180.v:10311$2837 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10311$2837_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10318.68-10318.77" + cell $memrd $memrd$\storage_2$ls180.v:10318$2839 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10318$2839_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10325.14-10325.23" + cell $memrd $memrd$\storage_3$ls180.v:10325$2844 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10325$2844_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10332.68-10332.77" + cell $memrd $memrd$\storage_3$ls180.v:10332$2846 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10332$2846_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10340.14-10340.23" + cell $memrd $memrd$\storage_4$ls180.v:10340$2851 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10340$2851_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10345.15-10345.24" + cell $memrd $memrd$\storage_4$ls180.v:10345$2853 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10345$2853_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10357.14-10357.23" + cell $memrd $memrd$\storage_5$ls180.v:10357$2858 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10357$2858_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10362.15-10362.24" + cell $memrd $memrd$\storage_5$ls180.v:10362$2860 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10362$2860_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10373.14-10373.23" + cell $memrd $memrd$\storage_6$ls180.v:10373$2865 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10373$2865_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10380.45-10380.54" + cell $memrd $memrd$\storage_6$ls180.v:10380$2867 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10380$2867_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10387.14-10387.23" + cell $memrd $memrd$\storage_7$ls180.v:10387$2872 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10387$2872_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10394.45-10394.54" + cell $memrd $memrd$\storage_7$ls180.v:10394$2874 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10394$2874_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2876 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2876 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10226$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10226$1_DATA + connect \EN $memwr$\mem$ls180.v:10226$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2877 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2877 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10228$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10228$2_DATA + connect \EN $memwr$\mem$ls180.v:10228$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2878 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2878 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10230$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10230$3_DATA + connect \EN $memwr$\mem$ls180.v:10230$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2879 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2879 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10232$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10232$4_DATA + connect \EN $memwr$\mem$ls180.v:10232$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2880 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2880 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10234$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10234$5_DATA + connect \EN $memwr$\mem$ls180.v:10234$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2881 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2881 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10236$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10236$6_DATA + connect \EN $memwr$\mem$ls180.v:10236$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2882 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2882 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10238$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10238$7_DATA + connect \EN $memwr$\mem$ls180.v:10238$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2883 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2883 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10240$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10240$8_DATA + connect \EN $memwr$\mem$ls180.v:10240$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2884 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2884 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10254$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10254$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10254$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2885 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2885 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10256$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10256$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10256$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2886 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2886 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10258$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10258$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10258$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2887 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2887 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10260$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10260$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10260$12_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2888 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2888 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10262$13_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10262$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10262$13_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2889 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2889 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10264$14_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10264$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10264$14_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2890 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2890 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10266$15_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10266$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10266$15_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2891 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2891 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10268$16_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10268$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10268$16_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$2892 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2892 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10282$17_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10282$17_DATA + connect \EN $memwr$\storage$ls180.v:10282$17_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$2893 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2893 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10296$18_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10296$18_DATA + connect \EN $memwr$\storage_1$ls180.v:10296$18_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$2894 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2894 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10310$19_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10310$19_DATA + connect \EN $memwr$\storage_2$ls180.v:10310$19_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$2895 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2895 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10324$20_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10324$20_DATA + connect \EN $memwr$\storage_3$ls180.v:10324$20_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$2896 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2896 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10339$21_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10339$21_DATA + connect \EN $memwr$\storage_4$ls180.v:10339$21_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$2897 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2897 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10356$22_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10356$22_DATA + connect \EN $memwr$\storage_5$ls180.v:10356$22_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$2898 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2898 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10372$23_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10372$23_DATA + connect \EN $memwr$\storage_6$ls180.v:10372$23_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$2899 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2899 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10386$24_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10386$24_DATA + connect \EN $memwr$\storage_7$ls180.v:10386$24_EN + end + attribute \src "ls180.v:3044.41-3044.71" + cell $ne $ne$ls180.v:3044$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:3044$84_Y + end + attribute \src "ls180.v:3219.70-3219.104" + cell $ne $ne$ls180.v:3219$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3219$123_Y + end + attribute \src "ls180.v:3280.8-3280.142" + cell $ne $ne$ls180.v:3280$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3280$142_Y + end + attribute \src "ls180.v:3312.75-3312.133" + cell $ne $ne$ls180.v:3312$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3312$149_Y + end + attribute \src "ls180.v:3313.75-3313.133" + cell $ne $ne$ls180.v:3313$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3313$150_Y + end + attribute \src "ls180.v:3437.8-3437.142" + cell $ne $ne$ls180.v:3437$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3437$172_Y + end + attribute \src "ls180.v:3469.75-3469.133" + cell $ne $ne$ls180.v:3469$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3469$179_Y + end + attribute \src "ls180.v:3470.75-3470.133" + cell $ne $ne$ls180.v:3470$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3470$180_Y + end + attribute \src "ls180.v:3594.8-3594.142" + cell $ne $ne$ls180.v:3594$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3594$202_Y + end + attribute \src "ls180.v:3626.75-3626.133" + cell $ne $ne$ls180.v:3626$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3626$209_Y + end + attribute \src "ls180.v:3627.75-3627.133" + cell $ne $ne$ls180.v:3627$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3627$210_Y + end + attribute \src "ls180.v:3751.8-3751.142" + cell $ne $ne$ls180.v:3751$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3751$232_Y + end + attribute \src "ls180.v:3783.75-3783.133" + cell $ne $ne$ls180.v:3783$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3783$239_Y + end + attribute \src "ls180.v:3784.75-3784.133" + cell $ne $ne$ls180.v:3784$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3784$240_Y + end + attribute \src "ls180.v:4276.47-4276.80" + cell $ne $ne$ls180.v:4276$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4276$638_Y + end + attribute \src "ls180.v:4277.47-4277.79" + cell $ne $ne$ls180.v:4277$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4277$639_Y + end + attribute \src "ls180.v:4306.47-4306.80" + cell $ne $ne$ls180.v:4306$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4306$649_Y + end + attribute \src "ls180.v:4307.47-4307.79" + cell $ne $ne$ls180.v:4307$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4307$650_Y + end + attribute \src "ls180.v:4787.32-4787.89" + cell $ne $ne$ls180.v:4787$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4787$732_Y + end + attribute \src "ls180.v:5434.10-5434.56" + cell $ne $ne$ls180.v:5434$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5434$1029_Y + end + attribute \src "ls180.v:5539.51-5539.87" + cell $ne $ne$ls180.v:5539$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5539$1043_Y + end + attribute \src "ls180.v:5540.51-5540.86" + cell $ne $ne$ls180.v:5540$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5540$1044_Y + end + attribute \src "ls180.v:5759.51-5759.87" + cell $ne $ne$ls180.v:5759$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5759$1074_Y + end + attribute \src "ls180.v:5760.51-5760.86" + cell $ne $ne$ls180.v:5760$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5760$1075_Y + end + attribute \src "ls180.v:5791.79-5791.119" + cell $ne $ne$ls180.v:5791$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5791$1078_Y + end + attribute \src "ls180.v:7649.7-7649.52" + cell $ne $ne$ls180.v:7649$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7649$2486_Y + end + attribute \src "ls180.v:7703.9-7703.43" + cell $ne $ne$ls180.v:7703$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7703$2503_Y + end + attribute \src "ls180.v:7739.8-7739.44" + cell $ne $ne$ls180.v:7739$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7739$2510_Y + end + attribute \src "ls180.v:8677.9-8677.47" + cell $ne $ne$ls180.v:8677$2725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8677$2725_Y + end + attribute \src "ls180.v:2848.33-2848.73" + cell $not $not$ls180.v:2848$26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_cyc + connect \Y $not$ls180.v:2848$26_Y + end + attribute \src "ls180.v:2887.48-2887.69" + cell $not $not$ls180.v:2887$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2887$31_Y + end + attribute \src "ls180.v:2888.48-2888.69" + cell $not $not$ls180.v:2888$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2888$32_Y + end + attribute \src "ls180.v:2908.33-2908.73" + cell $not $not$ls180.v:2908$37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_cyc + connect \Y $not$ls180.v:2908$37_Y + end + attribute \src "ls180.v:2947.48-2947.69" + cell $not $not$ls180.v:2947$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2947$42_Y + end + attribute \src "ls180.v:2948.48-2948.69" + cell $not $not$ls180.v:2948$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2948$43_Y + end + attribute \src "ls180.v:2968.36-2968.79" + cell $not $not$ls180.v:2968$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:2968$48_Y + end + attribute \src "ls180.v:3007.27-3007.51" + cell $not $not$ls180.v:3007$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3007$53_Y + end + attribute \src "ls180.v:3008.27-3008.51" + cell $not $not$ls180.v:3008$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3008$54_Y + end + attribute \src "ls180.v:3168.34-3168.64" + cell $not $not$ls180.v:3168$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3168$115_Y + end + attribute \src "ls180.v:3169.31-3169.61" + cell $not $not$ls180.v:3169$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3169$116_Y + end + attribute \src "ls180.v:3170.32-3170.62" + cell $not $not$ls180.v:3170$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3170$117_Y + end + attribute \src "ls180.v:3171.32-3171.62" + cell $not $not$ls180.v:3171$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3171$118_Y + end + attribute \src "ls180.v:3213.33-3213.56" + cell $not $not$ls180.v:3213$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3213$121_Y + end + attribute \src "ls180.v:3314.58-3314.106" + cell $not $not$ls180.v:3314$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3314$151_Y + end + attribute \src "ls180.v:3368.9-3368.45" + cell $not $not$ls180.v:3368$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3368$156_Y + end + attribute \src "ls180.v:3471.58-3471.106" + cell $not $not$ls180.v:3471$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3471$181_Y + end + attribute \src "ls180.v:3525.9-3525.45" + cell $not $not$ls180.v:3525$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3525$186_Y + end + attribute \src "ls180.v:3628.58-3628.106" + cell $not $not$ls180.v:3628$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3628$211_Y + end + attribute \src "ls180.v:3682.9-3682.45" + cell $not $not$ls180.v:3682$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3682$216_Y + end + attribute \src "ls180.v:3785.58-3785.106" + cell $not $not$ls180.v:3785$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3785$241_Y + end + attribute \src "ls180.v:3839.9-3839.45" + cell $not $not$ls180.v:3839$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3839$246_Y + end + attribute \src "ls180.v:3881.149-3881.187" + cell $not $not$ls180.v:3881$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3881$249_Y + end + attribute \src "ls180.v:3881.193-3881.230" + cell $not $not$ls180.v:3881$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3881$251_Y + end + attribute \src "ls180.v:3882.149-3882.187" + cell $not $not$ls180.v:3882$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3882$255_Y + end + attribute \src "ls180.v:3882.193-3882.230" + cell $not $not$ls180.v:3882$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3882$257_Y + end + attribute \src "ls180.v:3898.43-3898.73" + cell $not $not$ls180.v:3898$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3898$285_Y + end + attribute \src "ls180.v:3901.205-3901.245" + cell $not $not$ls180.v:3901$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3901$288_Y + end + attribute \src "ls180.v:3901.251-3901.290" + cell $not $not$ls180.v:3901$290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3901$290_Y + end + attribute \src "ls180.v:3901.159-3901.292" + cell $not $not$ls180.v:3901$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3901$291_Y + connect \Y $not$ls180.v:3901$292_Y + end + attribute \src "ls180.v:3902.205-3902.245" + cell $not $not$ls180.v:3902$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3902$301_Y + end + attribute \src "ls180.v:3902.251-3902.290" + cell $not $not$ls180.v:3902$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3902$303_Y + end + attribute \src "ls180.v:3902.159-3902.292" + cell $not $not$ls180.v:3902$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3902$304_Y + connect \Y $not$ls180.v:3902$305_Y + end + attribute \src "ls180.v:3903.205-3903.245" + cell $not $not$ls180.v:3903$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3903$314_Y + end + attribute \src "ls180.v:3903.251-3903.290" + cell $not $not$ls180.v:3903$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3903$316_Y + end + attribute \src "ls180.v:3903.159-3903.292" + cell $not $not$ls180.v:3903$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3903$317_Y + connect \Y $not$ls180.v:3903$318_Y + end + attribute \src "ls180.v:3904.205-3904.245" + cell $not $not$ls180.v:3904$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3904$327_Y + end + attribute \src "ls180.v:3904.251-3904.290" + cell $not $not$ls180.v:3904$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3904$329_Y + end + attribute \src "ls180.v:3904.159-3904.292" + cell $not $not$ls180.v:3904$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3904$330_Y + connect \Y $not$ls180.v:3904$331_Y + end + attribute \src "ls180.v:3931.71-3931.103" + cell $not $not$ls180.v:3931$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:3931$342_Y + end + attribute \src "ls180.v:3934.205-3934.245" + cell $not $not$ls180.v:3934$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3934$346_Y + end + attribute \src "ls180.v:3934.251-3934.290" + cell $not $not$ls180.v:3934$348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3934$348_Y + end + attribute \src "ls180.v:3934.159-3934.292" + cell $not $not$ls180.v:3934$350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3934$349_Y + connect \Y $not$ls180.v:3934$350_Y + end + attribute \src "ls180.v:3935.205-3935.245" + cell $not $not$ls180.v:3935$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3935$359_Y + end + attribute \src "ls180.v:3935.251-3935.290" + cell $not $not$ls180.v:3935$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3935$361_Y + end + attribute \src "ls180.v:3935.159-3935.292" + cell $not $not$ls180.v:3935$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3935$362_Y + connect \Y $not$ls180.v:3935$363_Y + end + attribute \src "ls180.v:3936.205-3936.245" + cell $not $not$ls180.v:3936$372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3936$372_Y + end + attribute \src "ls180.v:3936.251-3936.290" + cell $not $not$ls180.v:3936$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3936$374_Y + end + attribute \src "ls180.v:3936.159-3936.292" + cell $not $not$ls180.v:3936$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3936$375_Y + connect \Y $not$ls180.v:3936$376_Y + end + attribute \src "ls180.v:3937.205-3937.245" + cell $not $not$ls180.v:3937$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3937$385_Y + end + attribute \src "ls180.v:3937.251-3937.290" + cell $not $not$ls180.v:3937$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3937$387_Y + end + attribute \src "ls180.v:3937.159-3937.292" + cell $not $not$ls180.v:3937$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3937$388_Y + connect \Y $not$ls180.v:3937$389_Y + end + attribute \src "ls180.v:4000.71-4000.103" + cell $not $not$ls180.v:4000$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:4000$428_Y + end + attribute \src "ls180.v:4021.112-4021.150" + cell $not $not$ls180.v:4021$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:4021$431_Y + end + attribute \src "ls180.v:4021.156-4021.193" + cell $not $not$ls180.v:4021$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:4021$433_Y + end + attribute \src "ls180.v:4021.68-4021.195" + cell $not $not$ls180.v:4021$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$434_Y + connect \Y $not$ls180.v:4021$435_Y + end + attribute \src "ls180.v:4029.11-4029.38" + cell $not $not$ls180.v:4029$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:4029$438_Y + end + attribute \src "ls180.v:4059.112-4059.150" + cell $not $not$ls180.v:4059$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:4059$440_Y + end + attribute \src "ls180.v:4059.156-4059.193" + cell $not $not$ls180.v:4059$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:4059$442_Y + end + attribute \src "ls180.v:4059.68-4059.195" + cell $not $not$ls180.v:4059$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4059$443_Y + connect \Y $not$ls180.v:4059$444_Y + end + attribute \src "ls180.v:4067.11-4067.37" + cell $not $not$ls180.v:4067$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:4067$447_Y + end + attribute \src "ls180.v:4077.87-4077.331" + cell $not $not$ls180.v:4077$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4077$458_Y + connect \Y $not$ls180.v:4077$459_Y + end + attribute \src "ls180.v:4078.35-4078.68" + cell $not $not$ls180.v:4078$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:4078$462_Y + end + attribute \src "ls180.v:4078.73-4078.105" + cell $not $not$ls180.v:4078$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:4078$463_Y + end + attribute \src "ls180.v:4082.87-4082.331" + cell $not $not$ls180.v:4082$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4082$474_Y + connect \Y $not$ls180.v:4082$475_Y + end + attribute \src "ls180.v:4083.35-4083.68" + cell $not $not$ls180.v:4083$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:4083$478_Y + end + attribute \src "ls180.v:4083.73-4083.105" + cell $not $not$ls180.v:4083$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:4083$479_Y + end + attribute \src "ls180.v:4087.87-4087.331" + cell $not $not$ls180.v:4087$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4087$490_Y + connect \Y $not$ls180.v:4087$491_Y + end + attribute \src "ls180.v:4088.35-4088.68" + cell $not $not$ls180.v:4088$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:4088$494_Y + end + attribute \src "ls180.v:4088.73-4088.105" + cell $not $not$ls180.v:4088$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:4088$495_Y + end + attribute \src "ls180.v:4092.87-4092.331" + cell $not $not$ls180.v:4092$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4092$506_Y + connect \Y $not$ls180.v:4092$507_Y + end + attribute \src "ls180.v:4093.35-4093.68" + cell $not $not$ls180.v:4093$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:4093$510_Y + end + attribute \src "ls180.v:4093.73-4093.105" + cell $not $not$ls180.v:4093$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:4093$511_Y + end + attribute \src "ls180.v:4097.128-4097.372" + cell $not $not$ls180.v:4097$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$523_Y + connect \Y $not$ls180.v:4097$524_Y + end + attribute \src "ls180.v:4097.502-4097.746" + cell $not $not$ls180.v:4097$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$539_Y + connect \Y $not$ls180.v:4097$540_Y + end + attribute \src "ls180.v:4097.876-4097.1120" + cell $not $not$ls180.v:4097$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$555_Y + connect \Y $not$ls180.v:4097$556_Y + end + attribute \src "ls180.v:4097.1250-4097.1494" + cell $not $not$ls180.v:4097$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$571_Y + connect \Y $not$ls180.v:4097$572_Y + end + attribute \src "ls180.v:4119.32-4119.50" + cell $not $not$ls180.v:4119$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:4119$578_Y + end + attribute \src "ls180.v:4158.30-4158.50" + cell $not $not$ls180.v:4158$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4158$583_Y + end + attribute \src "ls180.v:4159.30-4159.50" + cell $not $not$ls180.v:4159$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4159$584_Y + end + attribute \src "ls180.v:4184.27-4184.48" + cell $not $not$ls180.v:4184$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4184$590_Y + end + attribute \src "ls180.v:4185.30-4185.50" + cell $not $not$ls180.v:4185$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4185$591_Y + end + attribute \src "ls180.v:4186.80-4186.98" + cell $not $not$ls180.v:4186$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4186$593_Y + end + attribute \src "ls180.v:4187.107-4187.127" + cell $not $not$ls180.v:4187$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4187$597_Y + end + attribute \src "ls180.v:4188.78-4188.103" + cell $not $not$ls180.v:4188$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4188$600_Y + end + attribute \src "ls180.v:4189.91-4189.111" + cell $not $not$ls180.v:4189$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4189$603_Y + end + attribute \src "ls180.v:4205.35-4205.64" + cell $not $not$ls180.v:4205$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4205$612_Y + end + attribute \src "ls180.v:4206.36-4206.67" + cell $not $not$ls180.v:4206$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4206$613_Y + end + attribute \src "ls180.v:4212.32-4212.61" + cell $not $not$ls180.v:4212$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4212$614_Y + end + attribute \src "ls180.v:4218.36-4218.67" + cell $not $not$ls180.v:4218$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4218$615_Y + end + attribute \src "ls180.v:4219.35-4219.64" + cell $not $not$ls180.v:4219$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4219$616_Y + end + attribute \src "ls180.v:4222.32-4222.63" + cell $not $not$ls180.v:4222$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4222$619_Y + end + attribute \src "ls180.v:4260.81-4260.108" + cell $not $not$ls180.v:4260$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4260$629_Y + end + attribute \src "ls180.v:4290.81-4290.108" + cell $not $not$ls180.v:4290$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4290$640_Y + end + attribute \src "ls180.v:4501.60-4501.85" + cell $not $not$ls180.v:4501$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4501$691_Y + end + attribute \src "ls180.v:4642.54-4642.96" + cell $not $not$ls180.v:4642$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4642$705_Y + end + attribute \src "ls180.v:4645.48-4645.86" + cell $not $not$ls180.v:4645$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4645$708_Y + end + attribute \src "ls180.v:4769.55-4769.98" + cell $not $not$ls180.v:4769$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4769$726_Y + end + attribute \src "ls180.v:4772.49-4772.88" + cell $not $not$ls180.v:4772$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4772$729_Y + end + attribute \src "ls180.v:4822.30-4822.58" + cell $not $not$ls180.v:4822$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4822$735_Y + end + attribute \src "ls180.v:4903.56-4903.100" + cell $not $not$ls180.v:4903$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4903$741_Y + end + attribute \src "ls180.v:4906.50-4906.90" + cell $not $not$ls180.v:4906$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4906$744_Y + end + attribute \src "ls180.v:5022.42-5022.74" + cell $not $not$ls180.v:5022$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:5022$760_Y + end + attribute \src "ls180.v:5546.50-5546.88" + cell $not $not$ls180.v:5546$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5546$1045_Y + end + attribute \src "ls180.v:5558.52-5558.102" + cell $not $not$ls180.v:5558$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5558$1048_Y + end + attribute \src "ls180.v:5617.38-5617.74" + cell $not $not$ls180.v:5617$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5617$1055_Y + end + attribute \src "ls180.v:5916.69-5916.88" + cell $not $not$ls180.v:5916$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:5916$1131_Y + end + attribute \src "ls180.v:5933.63-5933.94" + cell $not $not$ls180.v:5933$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5933$1167_Y + end + attribute \src "ls180.v:5936.65-5936.96" + cell $not $not$ls180.v:5936$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5936$1174_Y + end + attribute \src "ls180.v:5939.65-5939.96" + cell $not $not$ls180.v:5939$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5939$1181_Y + end + attribute \src "ls180.v:5942.65-5942.96" + cell $not $not$ls180.v:5942$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5942$1188_Y + end + attribute \src "ls180.v:5945.65-5945.96" + cell $not $not$ls180.v:5945$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5945$1195_Y + end + attribute \src "ls180.v:5948.68-5948.99" + cell $not $not$ls180.v:5948$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5948$1202_Y + end + attribute \src "ls180.v:5951.68-5951.99" + cell $not $not$ls180.v:5951$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5951$1209_Y + end + attribute \src "ls180.v:5954.68-5954.99" + cell $not $not$ls180.v:5954$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5954$1216_Y + end + attribute \src "ls180.v:5957.68-5957.99" + cell $not $not$ls180.v:5957$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5957$1223_Y + end + attribute \src "ls180.v:5971.60-5971.91" + cell $not $not$ls180.v:5971$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5971$1231_Y + end + attribute \src "ls180.v:5974.60-5974.91" + cell $not $not$ls180.v:5974$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5974$1238_Y + end + attribute \src "ls180.v:5977.60-5977.91" + cell $not $not$ls180.v:5977$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5977$1245_Y + end + attribute \src "ls180.v:5980.60-5980.91" + cell $not $not$ls180.v:5980$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5980$1252_Y + end + attribute \src "ls180.v:5983.61-5983.92" + cell $not $not$ls180.v:5983$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5983$1259_Y + end + attribute \src "ls180.v:5986.61-5986.92" + cell $not $not$ls180.v:5986$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5986$1266_Y + end + attribute \src "ls180.v:5997.59-5997.90" + cell $not $not$ls180.v:5997$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5997$1274_Y + end + attribute \src "ls180.v:6000.58-6000.89" + cell $not $not$ls180.v:6000$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:6000$1281_Y + end + attribute \src "ls180.v:6011.64-6011.95" + cell $not $not$ls180.v:6011$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6011$1289_Y + end + attribute \src "ls180.v:6014.63-6014.94" + cell $not $not$ls180.v:6014$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6014$1296_Y + end + attribute \src "ls180.v:6017.63-6017.94" + cell $not $not$ls180.v:6017$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6017$1303_Y + end + attribute \src "ls180.v:6020.63-6020.94" + cell $not $not$ls180.v:6020$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6020$1310_Y + end + attribute \src "ls180.v:6023.63-6023.94" + cell $not $not$ls180.v:6023$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6023$1317_Y + end + attribute \src "ls180.v:6026.64-6026.95" + cell $not $not$ls180.v:6026$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6026$1324_Y + end + attribute \src "ls180.v:6029.64-6029.95" + cell $not $not$ls180.v:6029$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6029$1331_Y + end + attribute \src "ls180.v:6032.64-6032.95" + cell $not $not$ls180.v:6032$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6032$1338_Y + end + attribute \src "ls180.v:6035.64-6035.95" + cell $not $not$ls180.v:6035$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6035$1345_Y + end + attribute \src "ls180.v:6048.64-6048.95" + cell $not $not$ls180.v:6048$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6048$1353_Y + end + attribute \src "ls180.v:6051.63-6051.94" + cell $not $not$ls180.v:6051$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6051$1360_Y + end + attribute \src "ls180.v:6054.63-6054.94" + cell $not $not$ls180.v:6054$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6054$1367_Y + end + attribute \src "ls180.v:6057.63-6057.94" + cell $not $not$ls180.v:6057$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6057$1374_Y + end + attribute \src "ls180.v:6060.63-6060.94" + cell $not $not$ls180.v:6060$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6060$1381_Y + end + attribute \src "ls180.v:6063.64-6063.95" + cell $not $not$ls180.v:6063$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6063$1388_Y + end + attribute \src "ls180.v:6066.64-6066.95" + cell $not $not$ls180.v:6066$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6066$1395_Y + end + attribute \src "ls180.v:6069.64-6069.95" + cell $not $not$ls180.v:6069$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6069$1402_Y + end + attribute \src "ls180.v:6072.64-6072.95" + cell $not $not$ls180.v:6072$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6072$1409_Y + end + attribute \src "ls180.v:6085.66-6085.97" + cell $not $not$ls180.v:6085$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6085$1417_Y + end + attribute \src "ls180.v:6088.66-6088.97" + cell $not $not$ls180.v:6088$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6088$1424_Y + end + attribute \src "ls180.v:6091.66-6091.97" + cell $not $not$ls180.v:6091$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6091$1431_Y + end + attribute \src "ls180.v:6094.66-6094.97" + cell $not $not$ls180.v:6094$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6094$1438_Y + end + attribute \src "ls180.v:6097.66-6097.97" + cell $not $not$ls180.v:6097$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6097$1445_Y + end + attribute \src "ls180.v:6100.66-6100.97" + cell $not $not$ls180.v:6100$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6100$1452_Y + end + attribute \src "ls180.v:6103.66-6103.97" + cell $not $not$ls180.v:6103$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6103$1459_Y + end + attribute \src "ls180.v:6106.66-6106.97" + cell $not $not$ls180.v:6106$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6106$1466_Y + end + attribute \src "ls180.v:6109.68-6109.99" + cell $not $not$ls180.v:6109$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6109$1473_Y + end + attribute \src "ls180.v:6112.68-6112.99" + cell $not $not$ls180.v:6112$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6112$1480_Y + end + attribute \src "ls180.v:6115.68-6115.99" + cell $not $not$ls180.v:6115$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6115$1487_Y + end + attribute \src "ls180.v:6118.68-6118.99" + cell $not $not$ls180.v:6118$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6118$1494_Y + end + attribute \src "ls180.v:6121.68-6121.99" + cell $not $not$ls180.v:6121$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6121$1501_Y + end + attribute \src "ls180.v:6124.65-6124.96" + cell $not $not$ls180.v:6124$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6124$1508_Y + end + attribute \src "ls180.v:6127.66-6127.97" + cell $not $not$ls180.v:6127$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6127$1515_Y + end + attribute \src "ls180.v:6147.70-6147.101" + cell $not $not$ls180.v:6147$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6147$1523_Y + end + attribute \src "ls180.v:6150.70-6150.101" + cell $not $not$ls180.v:6150$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6150$1530_Y + end + attribute \src "ls180.v:6153.70-6153.101" + cell $not $not$ls180.v:6153$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6153$1537_Y + end + attribute \src "ls180.v:6156.70-6156.101" + cell $not $not$ls180.v:6156$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6156$1544_Y + end + attribute \src "ls180.v:6159.69-6159.100" + cell $not $not$ls180.v:6159$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6159$1551_Y + end + attribute \src "ls180.v:6162.69-6162.100" + cell $not $not$ls180.v:6162$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6162$1558_Y + end + attribute \src "ls180.v:6165.69-6165.100" + cell $not $not$ls180.v:6165$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6165$1565_Y + end + attribute \src "ls180.v:6168.69-6168.100" + cell $not $not$ls180.v:6168$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6168$1572_Y + end + attribute \src "ls180.v:6171.60-6171.91" + cell $not $not$ls180.v:6171$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6171$1579_Y + end + attribute \src "ls180.v:6174.71-6174.102" + cell $not $not$ls180.v:6174$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6174$1586_Y + end + attribute \src "ls180.v:6177.71-6177.102" + cell $not $not$ls180.v:6177$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6177$1593_Y + end + attribute \src "ls180.v:6180.71-6180.102" + cell $not $not$ls180.v:6180$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6180$1600_Y + end + attribute \src "ls180.v:6183.71-6183.102" + cell $not $not$ls180.v:6183$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6183$1607_Y + end + attribute \src "ls180.v:6186.71-6186.102" + cell $not $not$ls180.v:6186$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6186$1614_Y + end + attribute \src "ls180.v:6189.71-6189.102" + cell $not $not$ls180.v:6189$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6189$1621_Y + end + attribute \src "ls180.v:6192.70-6192.101" + cell $not $not$ls180.v:6192$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6192$1628_Y + end + attribute \src "ls180.v:6195.70-6195.101" + cell $not $not$ls180.v:6195$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6195$1635_Y + end + attribute \src "ls180.v:6198.70-6198.101" + cell $not $not$ls180.v:6198$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6198$1642_Y + end + attribute \src "ls180.v:6201.70-6201.101" + cell $not $not$ls180.v:6201$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6201$1649_Y + end + attribute \src "ls180.v:6204.70-6204.101" + cell $not $not$ls180.v:6204$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6204$1656_Y + end + attribute \src "ls180.v:6207.70-6207.101" + cell $not $not$ls180.v:6207$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6207$1663_Y + end + attribute \src "ls180.v:6210.70-6210.101" + cell $not $not$ls180.v:6210$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6210$1670_Y + end + attribute \src "ls180.v:6213.70-6213.101" + cell $not $not$ls180.v:6213$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6213$1677_Y + end + attribute \src "ls180.v:6216.70-6216.101" + cell $not $not$ls180.v:6216$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6216$1684_Y + end + attribute \src "ls180.v:6219.70-6219.101" + cell $not $not$ls180.v:6219$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6219$1691_Y + end + attribute \src "ls180.v:6222.66-6222.97" + cell $not $not$ls180.v:6222$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6222$1698_Y + end + attribute \src "ls180.v:6225.67-6225.98" + cell $not $not$ls180.v:6225$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6225$1705_Y + end + attribute \src "ls180.v:6228.70-6228.101" + cell $not $not$ls180.v:6228$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6228$1712_Y + end + attribute \src "ls180.v:6231.70-6231.101" + cell $not $not$ls180.v:6231$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6231$1719_Y + end + attribute \src "ls180.v:6234.69-6234.100" + cell $not $not$ls180.v:6234$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6234$1726_Y + end + attribute \src "ls180.v:6237.69-6237.100" + cell $not $not$ls180.v:6237$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6237$1733_Y + end + attribute \src "ls180.v:6240.69-6240.100" + cell $not $not$ls180.v:6240$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6240$1740_Y + end + attribute \src "ls180.v:6243.69-6243.100" + cell $not $not$ls180.v:6243$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6243$1747_Y + end + attribute \src "ls180.v:6282.66-6282.97" + cell $not $not$ls180.v:6282$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6282$1755_Y + end + attribute \src "ls180.v:6285.66-6285.97" + cell $not $not$ls180.v:6285$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6285$1762_Y + end + attribute \src "ls180.v:6288.66-6288.97" + cell $not $not$ls180.v:6288$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6288$1769_Y + end + attribute \src "ls180.v:6291.66-6291.97" + cell $not $not$ls180.v:6291$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6291$1776_Y + end + attribute \src "ls180.v:6294.66-6294.97" + cell $not $not$ls180.v:6294$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6294$1783_Y + end + attribute \src "ls180.v:6297.66-6297.97" + cell $not $not$ls180.v:6297$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6297$1790_Y + end + attribute \src "ls180.v:6300.66-6300.97" + cell $not $not$ls180.v:6300$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6300$1797_Y + end + attribute \src "ls180.v:6303.66-6303.97" + cell $not $not$ls180.v:6303$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6303$1804_Y + end + attribute \src "ls180.v:6306.68-6306.99" + cell $not $not$ls180.v:6306$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6306$1811_Y + end + attribute \src "ls180.v:6309.68-6309.99" + cell $not $not$ls180.v:6309$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6309$1818_Y + end + attribute \src "ls180.v:6312.68-6312.99" + cell $not $not$ls180.v:6312$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6312$1825_Y + end + attribute \src "ls180.v:6315.68-6315.99" + cell $not $not$ls180.v:6315$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6315$1832_Y + end + attribute \src "ls180.v:6318.68-6318.99" + cell $not $not$ls180.v:6318$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6318$1839_Y + end + attribute \src "ls180.v:6321.65-6321.96" + cell $not $not$ls180.v:6321$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6321$1846_Y + end + attribute \src "ls180.v:6324.66-6324.97" + cell $not $not$ls180.v:6324$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6324$1853_Y + end + attribute \src "ls180.v:6327.68-6327.99" + cell $not $not$ls180.v:6327$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6327$1860_Y + end + attribute \src "ls180.v:6330.68-6330.99" + cell $not $not$ls180.v:6330$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6330$1867_Y + end + attribute \src "ls180.v:6333.68-6333.99" + cell $not $not$ls180.v:6333$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6333$1874_Y + end + attribute \src "ls180.v:6336.68-6336.99" + cell $not $not$ls180.v:6336$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6336$1881_Y + end + attribute \src "ls180.v:6361.68-6361.99" + cell $not $not$ls180.v:6361$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6361$1889_Y + end + attribute \src "ls180.v:6364.73-6364.104" + cell $not $not$ls180.v:6364$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6364$1896_Y + end + attribute \src "ls180.v:6367.73-6367.104" + cell $not $not$ls180.v:6367$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6367$1903_Y + end + attribute \src "ls180.v:6370.66-6370.97" + cell $not $not$ls180.v:6370$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6370$1910_Y + end + attribute \src "ls180.v:6378.70-6378.101" + cell $not $not$ls180.v:6378$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6378$1918_Y + end + attribute \src "ls180.v:6381.74-6381.105" + cell $not $not$ls180.v:6381$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6381$1925_Y + end + attribute \src "ls180.v:6384.64-6384.95" + cell $not $not$ls180.v:6384$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6384$1932_Y + end + attribute \src "ls180.v:6387.74-6387.105" + cell $not $not$ls180.v:6387$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6387$1939_Y + end + attribute \src "ls180.v:6390.74-6390.105" + cell $not $not$ls180.v:6390$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6390$1946_Y + end + attribute \src "ls180.v:6393.75-6393.106" + cell $not $not$ls180.v:6393$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6393$1953_Y + end + attribute \src "ls180.v:6396.73-6396.104" + cell $not $not$ls180.v:6396$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6396$1960_Y + end + attribute \src "ls180.v:6399.73-6399.104" + cell $not $not$ls180.v:6399$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6399$1967_Y + end + attribute \src "ls180.v:6402.73-6402.104" + cell $not $not$ls180.v:6402$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6402$1974_Y + end + attribute \src "ls180.v:6405.73-6405.104" + cell $not $not$ls180.v:6405$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6405$1981_Y + end + attribute \src "ls180.v:6423.67-6423.99" + cell $not $not$ls180.v:6423$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6423$1989_Y + end + attribute \src "ls180.v:6426.67-6426.99" + cell $not $not$ls180.v:6426$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6426$1996_Y + end + attribute \src "ls180.v:6429.65-6429.97" + cell $not $not$ls180.v:6429$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6429$2003_Y + end + attribute \src "ls180.v:6432.64-6432.96" + cell $not $not$ls180.v:6432$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6432$2010_Y + end + attribute \src "ls180.v:6435.63-6435.95" + cell $not $not$ls180.v:6435$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6435$2017_Y + end + attribute \src "ls180.v:6438.62-6438.94" + cell $not $not$ls180.v:6438$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6438$2024_Y + end + attribute \src "ls180.v:6441.68-6441.100" + cell $not $not$ls180.v:6441$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6441$2031_Y + end + attribute \src "ls180.v:6463.67-6463.99" + cell $not $not$ls180.v:6463$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6463$2040_Y + end + attribute \src "ls180.v:6466.67-6466.99" + cell $not $not$ls180.v:6466$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6466$2047_Y + end + attribute \src "ls180.v:6469.65-6469.97" + cell $not $not$ls180.v:6469$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6469$2054_Y + end + attribute \src "ls180.v:6472.64-6472.96" + cell $not $not$ls180.v:6472$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6472$2061_Y + end + attribute \src "ls180.v:6475.63-6475.95" + cell $not $not$ls180.v:6475$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6475$2068_Y + end + attribute \src "ls180.v:6478.62-6478.94" + cell $not $not$ls180.v:6478$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6478$2075_Y + end + attribute \src "ls180.v:6481.68-6481.100" + cell $not $not$ls180.v:6481$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6481$2082_Y + end + attribute \src "ls180.v:6484.71-6484.103" + cell $not $not$ls180.v:6484$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6484$2089_Y + end + attribute \src "ls180.v:6487.71-6487.103" + cell $not $not$ls180.v:6487$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6487$2096_Y + end + attribute \src "ls180.v:6511.64-6511.96" + cell $not $not$ls180.v:6511$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6511$2105_Y + end + attribute \src "ls180.v:6514.64-6514.96" + cell $not $not$ls180.v:6514$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6514$2112_Y + end + attribute \src "ls180.v:6517.64-6517.96" + cell $not $not$ls180.v:6517$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6517$2119_Y + end + attribute \src "ls180.v:6520.64-6520.96" + cell $not $not$ls180.v:6520$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6520$2126_Y + end + attribute \src "ls180.v:6523.66-6523.98" + cell $not $not$ls180.v:6523$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6523$2133_Y + end + attribute \src "ls180.v:6526.66-6526.98" + cell $not $not$ls180.v:6526$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6526$2140_Y + end + attribute \src "ls180.v:6529.66-6529.98" + cell $not $not$ls180.v:6529$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6529$2147_Y + end + attribute \src "ls180.v:6532.66-6532.98" + cell $not $not$ls180.v:6532$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6532$2154_Y + end + attribute \src "ls180.v:6535.62-6535.94" + cell $not $not$ls180.v:6535$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6535$2161_Y + end + attribute \src "ls180.v:6538.72-6538.104" + cell $not $not$ls180.v:6538$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6538$2168_Y + end + attribute \src "ls180.v:6541.65-6541.97" + cell $not $not$ls180.v:6541$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6541$2175_Y + end + attribute \src "ls180.v:6544.65-6544.97" + cell $not $not$ls180.v:6544$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6544$2182_Y + end + attribute \src "ls180.v:6547.65-6547.97" + cell $not $not$ls180.v:6547$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6547$2189_Y + end + attribute \src "ls180.v:6550.65-6550.97" + cell $not $not$ls180.v:6550$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6550$2196_Y + end + attribute \src "ls180.v:6553.77-6553.109" + cell $not $not$ls180.v:6553$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6553$2203_Y + end + attribute \src "ls180.v:6556.78-6556.110" + cell $not $not$ls180.v:6556$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6556$2210_Y + end + attribute \src "ls180.v:6559.69-6559.101" + cell $not $not$ls180.v:6559$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6559$2217_Y + end + attribute \src "ls180.v:6579.55-6579.87" + cell $not $not$ls180.v:6579$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6579$2225_Y + end + attribute \src "ls180.v:6582.65-6582.97" + cell $not $not$ls180.v:6582$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6582$2232_Y + end + attribute \src "ls180.v:6585.66-6585.98" + cell $not $not$ls180.v:6585$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6585$2239_Y + end + attribute \src "ls180.v:6588.70-6588.102" + cell $not $not$ls180.v:6588$2246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6588$2246_Y + end + attribute \src "ls180.v:6591.71-6591.103" + cell $not $not$ls180.v:6591$2253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6591$2253_Y + end + attribute \src "ls180.v:6594.69-6594.101" + cell $not $not$ls180.v:6594$2260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6594$2260_Y + end + attribute \src "ls180.v:6597.66-6597.98" + cell $not $not$ls180.v:6597$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6597$2267_Y + end + attribute \src "ls180.v:6600.65-6600.97" + cell $not $not$ls180.v:6600$2274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6600$2274_Y + end + attribute \src "ls180.v:6613.71-6613.103" + cell $not $not$ls180.v:6613$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6613$2282_Y + end + attribute \src "ls180.v:6616.71-6616.103" + cell $not $not$ls180.v:6616$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6616$2289_Y + end + attribute \src "ls180.v:6619.71-6619.103" + cell $not $not$ls180.v:6619$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6619$2296_Y + end + attribute \src "ls180.v:6622.71-6622.103" + cell $not $not$ls180.v:6622$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6622$2303_Y + end + attribute \src "ls180.v:7003.86-7003.330" + cell $not $not$ls180.v:7003$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7003$2351_Y + connect \Y $not$ls180.v:7003$2352_Y + end + attribute \src "ls180.v:7027.86-7027.330" + cell $not $not$ls180.v:7027$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7027$2367_Y + connect \Y $not$ls180.v:7027$2368_Y + end + attribute \src "ls180.v:7051.86-7051.330" + cell $not $not$ls180.v:7051$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7051$2383_Y + connect \Y $not$ls180.v:7051$2384_Y + end + attribute \src "ls180.v:7075.86-7075.330" + cell $not $not$ls180.v:7075$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7075$2399_Y + connect \Y $not$ls180.v:7075$2400_Y + end + attribute \src "ls180.v:7576.18-7576.42" + cell $not $not$ls180.v:7576$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7576$2456_Y + end + attribute \src "ls180.v:7655.72-7655.101" + cell $not $not$ls180.v:7655$2489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7655$2489_Y + end + attribute \src "ls180.v:7674.8-7674.38" + cell $not $not$ls180.v:7674$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7674$2493_Y + end + attribute \src "ls180.v:7678.64-7678.89" + cell $not $not$ls180.v:7678$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ram_bus_ram_bus_ack + connect \Y $not$ls180.v:7678$2496_Y + end + attribute \src "ls180.v:7686.32-7686.55" + cell $not $not$ls180.v:7686$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7686$2498_Y + end + attribute \src "ls180.v:7756.136-7756.189" + cell $not $not$ls180.v:7756$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7756$2513_Y + end + attribute \src "ls180.v:7762.136-7762.189" + cell $not $not$ls180.v:7762$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7762$2518_Y + end + attribute \src "ls180.v:7763.8-7763.61" + cell $not $not$ls180.v:7763$2520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7763$2520_Y + end + attribute \src "ls180.v:7771.8-7771.56" + cell $not $not$ls180.v:7771$2523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7771$2523_Y + end + attribute \src "ls180.v:7786.8-7786.46" + cell $not $not$ls180.v:7786$2525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7786$2525_Y + end + attribute \src "ls180.v:7802.136-7802.189" + cell $not $not$ls180.v:7802$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7802$2529_Y + end + attribute \src "ls180.v:7808.136-7808.189" + cell $not $not$ls180.v:7808$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7808$2534_Y + end + attribute \src "ls180.v:7809.8-7809.61" + cell $not $not$ls180.v:7809$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7809$2536_Y + end + attribute \src "ls180.v:7817.8-7817.56" + cell $not $not$ls180.v:7817$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7817$2539_Y + end + attribute \src "ls180.v:7832.8-7832.46" + cell $not $not$ls180.v:7832$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7832$2541_Y + end + attribute \src "ls180.v:7848.136-7848.189" + cell $not $not$ls180.v:7848$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7848$2545_Y + end + attribute \src "ls180.v:7854.136-7854.189" + cell $not $not$ls180.v:7854$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7854$2550_Y + end + attribute \src "ls180.v:7855.8-7855.61" + cell $not $not$ls180.v:7855$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7855$2552_Y + end + attribute \src "ls180.v:7863.8-7863.56" + cell $not $not$ls180.v:7863$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7863$2555_Y + end + attribute \src "ls180.v:7878.8-7878.46" + cell $not $not$ls180.v:7878$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:7878$2557_Y + end + attribute \src "ls180.v:7894.136-7894.189" + cell $not $not$ls180.v:7894$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7894$2561_Y + end + attribute \src "ls180.v:7900.136-7900.189" + cell $not $not$ls180.v:7900$2566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7900$2566_Y + end + attribute \src "ls180.v:7901.8-7901.61" + cell $not $not$ls180.v:7901$2568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7901$2568_Y + end + attribute \src "ls180.v:7909.8-7909.56" + cell $not $not$ls180.v:7909$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:7909$2571_Y + end + attribute \src "ls180.v:7924.8-7924.46" + cell $not $not$ls180.v:7924$2573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:7924$2573_Y + end + attribute \src "ls180.v:7932.7-7932.22" + cell $not $not$ls180.v:7932$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:7932$2576_Y + end + attribute \src "ls180.v:7935.8-7935.29" + cell $not $not$ls180.v:7935$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:7935$2577_Y + end + attribute \src "ls180.v:7939.7-7939.22" + cell $not $not$ls180.v:7939$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:7939$2579_Y + end + attribute \src "ls180.v:7942.8-7942.29" + cell $not $not$ls180.v:7942$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:7942$2580_Y + end + attribute \src "ls180.v:8061.30-8061.60" + cell $not $not$ls180.v:8061$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:8061$2582_Y + end + attribute \src "ls180.v:8062.30-8062.60" + cell $not $not$ls180.v:8062$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:8062$2583_Y + end + attribute \src "ls180.v:8063.29-8063.59" + cell $not $not$ls180.v:8063$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:8063$2584_Y + end + attribute \src "ls180.v:8074.8-8074.33" + cell $not $not$ls180.v:8074$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:8074$2585_Y + end + attribute \src "ls180.v:8089.8-8089.33" + cell $not $not$ls180.v:8089$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:8089$2588_Y + end + attribute \src "ls180.v:8125.36-8125.58" + cell $not $not$ls180.v:8125$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:8125$2618_Y + end + attribute \src "ls180.v:8125.64-8125.89" + cell $not $not$ls180.v:8125$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:8125$2620_Y + end + attribute \src "ls180.v:8154.7-8154.29" + cell $not $not$ls180.v:8154$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:8154$2627_Y + end + attribute \src "ls180.v:8155.9-8155.26" + cell $not $not$ls180.v:8155$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:8155$2628_Y + end + attribute \src "ls180.v:8188.8-8188.29" + cell $not $not$ls180.v:8188$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:8188$2634_Y + end + attribute \src "ls180.v:8195.8-8195.29" + cell $not $not$ls180.v:8195$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:8195$2636_Y + end + attribute \src "ls180.v:8205.80-8205.106" + cell $not $not$ls180.v:8205$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8205$2639_Y + end + attribute \src "ls180.v:8211.80-8211.106" + cell $not $not$ls180.v:8211$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8211$2644_Y + end + attribute \src "ls180.v:8212.8-8212.34" + cell $not $not$ls180.v:8212$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:8212$2646_Y + end + attribute \src "ls180.v:8227.80-8227.106" + cell $not $not$ls180.v:8227$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8227$2650_Y + end + attribute \src "ls180.v:8233.80-8233.106" + cell $not $not$ls180.v:8233$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8233$2655_Y + end + attribute \src "ls180.v:8234.8-8234.34" + cell $not $not$ls180.v:8234$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8234$2657_Y + end + attribute \src "ls180.v:8265.22-8265.41" + cell $not $not$ls180.v:8265$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster6_cs + connect \Y $not$ls180.v:8265$2661_Y + end + attribute \src "ls180.v:8265.46-8265.73" + cell $not $not$ls180.v:8265$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster26_cs_enable + connect \Y $not$ls180.v:8265$2662_Y + end + attribute \src "ls180.v:8300.22-8300.40" + cell $not $not$ls180.v:8300$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs + connect \Y $not$ls180.v:8300$2666_Y + end + attribute \src "ls180.v:8300.45-8300.70" + cell $not $not$ls180.v:8300$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs_enable + connect \Y $not$ls180.v:8300$2667_Y + end + attribute \src "ls180.v:8354.7-8354.31" + cell $not $not$ls180.v:8354$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8354$2678_Y + end + attribute \src "ls180.v:8426.8-8426.46" + cell $not $not$ls180.v:8426$2690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8426$2690_Y + end + attribute \src "ls180.v:8507.8-8507.47" + cell $not $not$ls180.v:8507$2702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8507$2702_Y + end + attribute \src "ls180.v:8568.8-8568.48" + cell $not $not$ls180.v:8568$2714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8568$2714_Y + end + attribute \src "ls180.v:8738.88-8738.118" + cell $not $not$ls180.v:8738$2728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8738$2728_Y + end + attribute \src "ls180.v:8744.88-8744.118" + cell $not $not$ls180.v:8744$2733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8744$2733_Y + end + attribute \src "ls180.v:8745.8-8745.38" + cell $not $not$ls180.v:8745$2735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8745$2735_Y + end + attribute \src "ls180.v:8836.88-8836.118" + cell $not $not$ls180.v:8836$2750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8836$2750_Y + end + attribute \src "ls180.v:8842.88-8842.118" + cell $not $not$ls180.v:8842$2755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8842$2755_Y + end + attribute \src "ls180.v:8843.8-8843.38" + cell $not $not$ls180.v:8843$2757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8843$2757_Y + end + attribute \src "ls180.v:8863.9-8863.28" + cell $not $not$ls180.v:8863$2760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8863$2760_Y + end + attribute \src "ls180.v:8882.9-8882.28" + cell $not $not$ls180.v:8882$2761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:8882$2761_Y + end + attribute \src "ls180.v:8901.9-8901.28" + cell $not $not$ls180.v:8901$2762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:8901$2762_Y + end + attribute \src "ls180.v:8920.9-8920.28" + cell $not $not$ls180.v:8920$2763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:8920$2763_Y + end + attribute \src "ls180.v:8939.9-8939.28" + cell $not $not$ls180.v:8939$2764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:8939$2764_Y + end + attribute \src "ls180.v:8960.8-8960.21" + cell $not $not$ls180.v:8960$2765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:8960$2765_Y + end + attribute \src "ls180.v:10496.8-10496.51" + cell $or $or$ls180.v:10496$2875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10496$2875_Y + end + attribute \src "ls180.v:2889.10-2889.71" + cell $or $or$ls180.v:2889$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:2889$33_Y + end + attribute \src "ls180.v:2949.10-2949.71" + cell $or $or$ls180.v:2949$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:2949$44_Y + end + attribute \src "ls180.v:3009.10-3009.53" + cell $or $or$ls180.v:3009$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:3009$55_Y + end + attribute \src "ls180.v:3219.39-3219.105" + cell $or $or$ls180.v:3219$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3219$123_Y + connect \Y $or$ls180.v:3219$124_Y + end + attribute \src "ls180.v:3262.59-3262.140" + cell $or $or$ls180.v:3262$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3262$128_Y + end + attribute \src "ls180.v:3263.44-3263.151" + cell $or $or$ls180.v:3263$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3263$129_Y + end + attribute \src "ls180.v:3271.45-3271.170" + cell $or $or$ls180.v:3271$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3271$132_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3271$133_Y + end + attribute \src "ls180.v:3308.127-3308.245" + cell $or $or$ls180.v:3308$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3308$146_Y + end + attribute \src "ls180.v:3314.57-3314.157" + cell $or $or$ls180.v:3314$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3314$151_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3314$152_Y + end + attribute \src "ls180.v:3419.59-3419.140" + cell $or $or$ls180.v:3419$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3419$158_Y + end + attribute \src "ls180.v:3420.44-3420.151" + cell $or $or$ls180.v:3420$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3420$159_Y + end + attribute \src "ls180.v:3428.45-3428.170" + cell $or $or$ls180.v:3428$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3428$162_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3428$163_Y + end + attribute \src "ls180.v:3465.127-3465.245" + cell $or $or$ls180.v:3465$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3465$176_Y + end + attribute \src "ls180.v:3471.57-3471.157" + cell $or $or$ls180.v:3471$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3471$181_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3471$182_Y + end + attribute \src "ls180.v:3576.59-3576.140" + cell $or $or$ls180.v:3576$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3576$188_Y + end + attribute \src "ls180.v:3577.44-3577.151" + cell $or $or$ls180.v:3577$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3577$189_Y + end + attribute \src "ls180.v:3585.45-3585.170" + cell $or $or$ls180.v:3585$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3585$192_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3585$193_Y + end + attribute \src "ls180.v:3622.127-3622.245" + cell $or $or$ls180.v:3622$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3622$206_Y + end + attribute \src "ls180.v:3628.57-3628.157" + cell $or $or$ls180.v:3628$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3628$211_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3628$212_Y + end + attribute \src "ls180.v:3733.59-3733.140" + cell $or $or$ls180.v:3733$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3733$218_Y + end + attribute \src "ls180.v:3734.44-3734.151" + cell $or $or$ls180.v:3734$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3734$219_Y + end + attribute \src "ls180.v:3742.45-3742.170" + cell $or $or$ls180.v:3742$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3742$222_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3742$223_Y + end + attribute \src "ls180.v:3779.127-3779.245" + cell $or $or$ls180.v:3779$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3779$236_Y + end + attribute \src "ls180.v:3785.57-3785.157" + cell $or $or$ls180.v:3785$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3785$241_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3785$242_Y + end + attribute \src "ls180.v:3884.107-3884.193" + cell $or $or$ls180.v:3884$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3884$262_Y + end + attribute \src "ls180.v:3887.39-3887.204" + cell $or $or$ls180.v:3887$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3887$266_Y + connect \B $and$ls180.v:3887$267_Y + connect \Y $or$ls180.v:3887$268_Y + end + attribute \src "ls180.v:3887.38-3887.289" + cell $or $or$ls180.v:3887$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3887$268_Y + connect \B $and$ls180.v:3887$269_Y + connect \Y $or$ls180.v:3887$270_Y + end + attribute \src "ls180.v:3887.37-3887.374" + cell $or $or$ls180.v:3887$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3887$270_Y + connect \B $and$ls180.v:3887$271_Y + connect \Y $or$ls180.v:3887$272_Y + end + attribute \src "ls180.v:3888.40-3888.207" + cell $or $or$ls180.v:3888$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3888$273_Y + connect \B $and$ls180.v:3888$274_Y + connect \Y $or$ls180.v:3888$275_Y + end + attribute \src "ls180.v:3888.39-3888.293" + cell $or $or$ls180.v:3888$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3888$275_Y + connect \B $and$ls180.v:3888$276_Y + connect \Y $or$ls180.v:3888$277_Y + end + attribute \src "ls180.v:3888.38-3888.379" + cell $or $or$ls180.v:3888$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3888$277_Y + connect \B $and$ls180.v:3888$278_Y + connect \Y $or$ls180.v:3888$279_Y + end + attribute \src "ls180.v:3901.158-3901.332" + cell $or $or$ls180.v:3901$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3901$292_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3901$293_Y + end + attribute \src "ls180.v:3901.75-3901.506" + cell $or $or$ls180.v:3901$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3901$294_Y + connect \B $and$ls180.v:3901$297_Y + connect \Y $or$ls180.v:3901$298_Y + end + attribute \src "ls180.v:3902.158-3902.332" + cell $or $or$ls180.v:3902$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3902$305_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3902$306_Y + end + attribute \src "ls180.v:3902.75-3902.506" + cell $or $or$ls180.v:3902$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3902$307_Y + connect \B $and$ls180.v:3902$310_Y + connect \Y $or$ls180.v:3902$311_Y + end + attribute \src "ls180.v:3903.158-3903.332" + cell $or $or$ls180.v:3903$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3903$318_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3903$319_Y + end + attribute \src "ls180.v:3903.75-3903.506" + cell $or $or$ls180.v:3903$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3903$320_Y + connect \B $and$ls180.v:3903$323_Y + connect \Y $or$ls180.v:3903$324_Y + end + attribute \src "ls180.v:3904.158-3904.332" + cell $or $or$ls180.v:3904$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3904$331_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3904$332_Y + end + attribute \src "ls180.v:3904.75-3904.506" + cell $or $or$ls180.v:3904$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3904$333_Y + connect \B $and$ls180.v:3904$336_Y + connect \Y $or$ls180.v:3904$337_Y + end + attribute \src "ls180.v:3931.36-3931.104" + cell $or $or$ls180.v:3931$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:3931$342_Y + connect \Y $or$ls180.v:3931$343_Y + end + attribute \src "ls180.v:3934.158-3934.332" + cell $or $or$ls180.v:3934$351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3934$350_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3934$351_Y + end + attribute \src "ls180.v:3934.75-3934.506" + cell $or $or$ls180.v:3934$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3934$352_Y + connect \B $and$ls180.v:3934$355_Y + connect \Y $or$ls180.v:3934$356_Y + end + attribute \src "ls180.v:3935.158-3935.332" + cell $or $or$ls180.v:3935$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3935$363_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3935$364_Y + end + attribute \src "ls180.v:3935.75-3935.506" + cell $or $or$ls180.v:3935$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3935$365_Y + connect \B $and$ls180.v:3935$368_Y + connect \Y $or$ls180.v:3935$369_Y + end + attribute \src "ls180.v:3936.158-3936.332" + cell $or $or$ls180.v:3936$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3936$376_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3936$377_Y + end + attribute \src "ls180.v:3936.75-3936.506" + cell $or $or$ls180.v:3936$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3936$378_Y + connect \B $and$ls180.v:3936$381_Y + connect \Y $or$ls180.v:3936$382_Y + end + attribute \src "ls180.v:3937.158-3937.332" + cell $or $or$ls180.v:3937$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3937$389_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3937$390_Y + end + attribute \src "ls180.v:3937.75-3937.506" + cell $or $or$ls180.v:3937$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3937$391_Y + connect \B $and$ls180.v:3937$394_Y + connect \Y $or$ls180.v:3937$395_Y + end + attribute \src "ls180.v:4000.36-4000.104" + cell $or $or$ls180.v:4000$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:4000$428_Y + connect \Y $or$ls180.v:4000$429_Y + end + attribute \src "ls180.v:4021.67-4021.221" + cell $or $or$ls180.v:4021$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4021$435_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:4021$436_Y + end + attribute \src "ls180.v:4029.10-4029.62" + cell $or $or$ls180.v:4029$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4029$438_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:4029$439_Y + end + attribute \src "ls180.v:4059.67-4059.221" + cell $or $or$ls180.v:4059$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4059$444_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:4059$445_Y + end + attribute \src "ls180.v:4067.10-4067.61" + cell $or $or$ls180.v:4067$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4067$447_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:4067$448_Y + end + attribute \src "ls180.v:4077.91-4077.180" + cell $or $or$ls180.v:4077$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4077$451_Y + connect \Y $or$ls180.v:4077$452_Y + end + attribute \src "ls180.v:4077.90-4077.255" + cell $or $or$ls180.v:4077$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4077$452_Y + connect \B $and$ls180.v:4077$454_Y + connect \Y $or$ls180.v:4077$455_Y + end + attribute \src "ls180.v:4077.89-4077.330" + cell $or $or$ls180.v:4077$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4077$455_Y + connect \B $and$ls180.v:4077$457_Y + connect \Y $or$ls180.v:4077$458_Y + end + attribute \src "ls180.v:4082.91-4082.180" + cell $or $or$ls180.v:4082$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4082$467_Y + connect \Y $or$ls180.v:4082$468_Y + end + attribute \src "ls180.v:4082.90-4082.255" + cell $or $or$ls180.v:4082$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4082$468_Y + connect \B $and$ls180.v:4082$470_Y + connect \Y $or$ls180.v:4082$471_Y + end + attribute \src "ls180.v:4082.89-4082.330" + cell $or $or$ls180.v:4082$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4082$471_Y + connect \B $and$ls180.v:4082$473_Y + connect \Y $or$ls180.v:4082$474_Y + end + attribute \src "ls180.v:4087.91-4087.180" + cell $or $or$ls180.v:4087$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4087$483_Y + connect \Y $or$ls180.v:4087$484_Y + end + attribute \src "ls180.v:4087.90-4087.255" + cell $or $or$ls180.v:4087$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4087$484_Y + connect \B $and$ls180.v:4087$486_Y + connect \Y $or$ls180.v:4087$487_Y + end + attribute \src "ls180.v:4087.89-4087.330" + cell $or $or$ls180.v:4087$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4087$487_Y + connect \B $and$ls180.v:4087$489_Y + connect \Y $or$ls180.v:4087$490_Y + end + attribute \src "ls180.v:4092.91-4092.180" + cell $or $or$ls180.v:4092$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4092$499_Y + connect \Y $or$ls180.v:4092$500_Y + end + attribute \src "ls180.v:4092.90-4092.255" + cell $or $or$ls180.v:4092$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4092$500_Y + connect \B $and$ls180.v:4092$502_Y + connect \Y $or$ls180.v:4092$503_Y + end + attribute \src "ls180.v:4092.89-4092.330" + cell $or $or$ls180.v:4092$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4092$503_Y + connect \B $and$ls180.v:4092$505_Y + connect \Y $or$ls180.v:4092$506_Y + end + attribute \src "ls180.v:4097.132-4097.221" + cell $or $or$ls180.v:4097$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4097$516_Y + connect \Y $or$ls180.v:4097$517_Y + end + attribute \src "ls180.v:4097.131-4097.296" + cell $or $or$ls180.v:4097$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$517_Y + connect \B $and$ls180.v:4097$519_Y + connect \Y $or$ls180.v:4097$520_Y + end + attribute \src "ls180.v:4097.130-4097.371" + cell $or $or$ls180.v:4097$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$520_Y + connect \B $and$ls180.v:4097$522_Y + connect \Y $or$ls180.v:4097$523_Y + end + attribute \src "ls180.v:4097.34-4097.411" + cell $or $or$ls180.v:4097$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:4097$527_Y + connect \Y $or$ls180.v:4097$528_Y + end + attribute \src "ls180.v:4097.506-4097.595" + cell $or $or$ls180.v:4097$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4097$532_Y + connect \Y $or$ls180.v:4097$533_Y + end + attribute \src "ls180.v:4097.505-4097.670" + cell $or $or$ls180.v:4097$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$533_Y + connect \B $and$ls180.v:4097$535_Y + connect \Y $or$ls180.v:4097$536_Y + end + attribute \src "ls180.v:4097.504-4097.745" + cell $or $or$ls180.v:4097$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$536_Y + connect \B $and$ls180.v:4097$538_Y + connect \Y $or$ls180.v:4097$539_Y + end + attribute \src "ls180.v:4097.33-4097.785" + cell $or $or$ls180.v:4097$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$528_Y + connect \B $and$ls180.v:4097$543_Y + connect \Y $or$ls180.v:4097$544_Y + end + attribute \src "ls180.v:4097.880-4097.969" + cell $or $or$ls180.v:4097$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4097$548_Y + connect \Y $or$ls180.v:4097$549_Y + end + attribute \src "ls180.v:4097.879-4097.1044" + cell $or $or$ls180.v:4097$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$549_Y + connect \B $and$ls180.v:4097$551_Y + connect \Y $or$ls180.v:4097$552_Y + end + attribute \src "ls180.v:4097.878-4097.1119" + cell $or $or$ls180.v:4097$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$552_Y + connect \B $and$ls180.v:4097$554_Y + connect \Y $or$ls180.v:4097$555_Y + end + attribute \src "ls180.v:4097.32-4097.1159" + cell $or $or$ls180.v:4097$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$544_Y + connect \B $and$ls180.v:4097$559_Y + connect \Y $or$ls180.v:4097$560_Y + end + attribute \src "ls180.v:4097.1254-4097.1343" + cell $or $or$ls180.v:4097$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4097$564_Y + connect \Y $or$ls180.v:4097$565_Y + end + attribute \src "ls180.v:4097.1253-4097.1418" + cell $or $or$ls180.v:4097$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$565_Y + connect \B $and$ls180.v:4097$567_Y + connect \Y $or$ls180.v:4097$568_Y + end + attribute \src "ls180.v:4097.1252-4097.1493" + cell $or $or$ls180.v:4097$571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$568_Y + connect \B $and$ls180.v:4097$570_Y + connect \Y $or$ls180.v:4097$571_Y + end + attribute \src "ls180.v:4097.31-4097.1533" + cell $or $or$ls180.v:4097$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4097$560_Y + connect \B $and$ls180.v:4097$575_Y + connect \Y $or$ls180.v:4097$576_Y + end + attribute \src "ls180.v:4160.10-4160.52" + cell $or $or$ls180.v:4160$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4160$585_Y + end + attribute \src "ls180.v:4187.35-4187.74" + cell $or $or$ls180.v:4187$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4187$595_Y + end + attribute \src "ls180.v:4188.34-4188.73" + cell $or $or$ls180.v:4188$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4188$599_Y + end + attribute \src "ls180.v:4189.48-4189.130" + cell $or $or$ls180.v:4189$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4189$602_Y + connect \B $and$ls180.v:4189$604_Y + connect \Y $or$ls180.v:4189$605_Y + end + attribute \src "ls180.v:4190.24-4190.87" + cell $or $or$ls180.v:4190$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4190$607_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4190$608_Y + end + attribute \src "ls180.v:4191.26-4191.95" + cell $or $or$ls180.v:4191$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4191$609_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4191$610_Y + end + attribute \src "ls180.v:4221.42-4221.89" + cell $or $or$ls180.v:4221$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4221$617_Y + connect \Y $or$ls180.v:4221$618_Y + end + attribute \src "ls180.v:4245.25-4245.174" + cell $or $or$ls180.v:4245$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4245$626_Y + connect \B $and$ls180.v:4245$627_Y + connect \Y $or$ls180.v:4245$628_Y + end + attribute \src "ls180.v:4260.80-4260.132" + cell $or $or$ls180.v:4260$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4260$629_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4260$630_Y + end + attribute \src "ls180.v:4271.72-4271.135" + cell $or $or$ls180.v:4271$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4271$635_Y + end + attribute \src "ls180.v:4290.80-4290.132" + cell $or $or$ls180.v:4290$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4290$640_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4290$641_Y + end + attribute \src "ls180.v:4301.72-4301.135" + cell $or $or$ls180.v:4301$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4301$646_Y + end + attribute \src "ls180.v:4446.36-4446.111" + cell $or $or$ls180.v:4446$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4446$669_Y + end + attribute \src "ls180.v:4446.35-4446.151" + cell $or $or$ls180.v:4446$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4446$669_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4446$670_Y + end + attribute \src "ls180.v:4446.34-4446.192" + cell $or $or$ls180.v:4446$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4446$670_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4446$671_Y + end + attribute \src "ls180.v:4446.33-4446.233" + cell $or $or$ls180.v:4446$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4446$671_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4446$672_Y + end + attribute \src "ls180.v:4447.39-4447.120" + cell $or $or$ls180.v:4447$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4447$673_Y + end + attribute \src "ls180.v:4447.38-4447.163" + cell $or $or$ls180.v:4447$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4447$673_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4447$674_Y + end + attribute \src "ls180.v:4447.37-4447.207" + cell $or $or$ls180.v:4447$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4447$674_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4447$675_Y + end + attribute \src "ls180.v:4447.36-4447.251" + cell $or $or$ls180.v:4447$676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4447$675_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4447$676_Y + end + attribute \src "ls180.v:4448.38-4448.117" + cell $or $or$ls180.v:4448$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4448$677_Y + end + attribute \src "ls180.v:4448.37-4448.159" + cell $or $or$ls180.v:4448$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4448$677_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4448$678_Y + end + attribute \src "ls180.v:4448.36-4448.202" + cell $or $or$ls180.v:4448$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4448$678_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4448$679_Y + end + attribute \src "ls180.v:4448.35-4448.245" + cell $or $or$ls180.v:4448$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4448$679_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4448$680_Y + end + attribute \src "ls180.v:4449.40-4449.123" + cell $or $or$ls180.v:4449$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4449$681_Y + end + attribute \src "ls180.v:4449.39-4449.167" + cell $or $or$ls180.v:4449$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4449$681_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4449$682_Y + end + attribute \src "ls180.v:4449.38-4449.212" + cell $or $or$ls180.v:4449$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4449$682_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4449$683_Y + end + attribute \src "ls180.v:4449.37-4449.257" + cell $or $or$ls180.v:4449$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4449$683_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4449$684_Y + end + attribute \src "ls180.v:4450.39-4450.120" + cell $or $or$ls180.v:4450$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4450$685_Y + end + attribute \src "ls180.v:4450.38-4450.163" + cell $or $or$ls180.v:4450$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4450$685_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4450$686_Y + end + attribute \src "ls180.v:4450.37-4450.207" + cell $or $or$ls180.v:4450$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4450$686_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4450$687_Y + end + attribute \src "ls180.v:4450.36-4450.251" + cell $or $or$ls180.v:4450$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4450$687_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4450$688_Y + end + attribute \src "ls180.v:4471.35-4471.80" + cell $or $or$ls180.v:4471$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4471$689_Y + end + attribute \src "ls180.v:4625.91-4625.144" + cell $or $or$ls180.v:4625$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4625$703_Y + end + attribute \src "ls180.v:4642.53-4642.143" + cell $or $or$ls180.v:4642$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4642$705_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4642$706_Y + end + attribute \src "ls180.v:4645.47-4645.127" + cell $or $or$ls180.v:4645$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4645$708_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4645$709_Y + end + attribute \src "ls180.v:4769.54-4769.146" + cell $or $or$ls180.v:4769$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4769$726_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4769$727_Y + end + attribute \src "ls180.v:4772.48-4772.130" + cell $or $or$ls180.v:4772$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4772$729_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4772$730_Y + end + attribute \src "ls180.v:4903.55-4903.149" + cell $or $or$ls180.v:4903$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4903$741_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4903$742_Y + end + attribute \src "ls180.v:4906.49-4906.133" + cell $or $or$ls180.v:4906$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4906$744_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4906$745_Y + end + attribute \src "ls180.v:5535.80-5535.151" + cell $or $or$ls180.v:5535$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5535$1040_Y + end + attribute \src "ls180.v:5546.49-5546.131" + cell $or $or$ls180.v:5546$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5546$1045_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5546$1046_Y + end + attribute \src "ls180.v:5755.80-5755.151" + cell $or $or$ls180.v:5755$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5755$1071_Y + end + attribute \src "ls180.v:5915.38-5915.93" + cell $or $or$ls180.v:5915$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_ram_bus_ram_bus_err + connect \Y $or$ls180.v:5915$1121_Y + end + attribute \src "ls180.v:5915.37-5915.136" + cell $or $or$ls180.v:5915$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1121_Y + connect \B \main_interface0_converted_interface_err + connect \Y $or$ls180.v:5915$1122_Y + end + attribute \src "ls180.v:5915.36-5915.179" + cell $or $or$ls180.v:5915$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1122_Y + connect \B \main_interface1_converted_interface_err + connect \Y $or$ls180.v:5915$1123_Y + end + attribute \src "ls180.v:5915.35-5915.223" + cell $or $or$ls180.v:5915$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1123_Y + connect \B \main_libresocsim_libresoc_interface0_err + connect \Y $or$ls180.v:5915$1124_Y + end + attribute \src "ls180.v:5915.34-5915.267" + cell $or $or$ls180.v:5915$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1124_Y + connect \B \main_libresocsim_libresoc_interface1_err + connect \Y $or$ls180.v:5915$1125_Y + end + attribute \src "ls180.v:5915.33-5915.311" + cell $or $or$ls180.v:5915$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1125_Y + connect \B \main_libresocsim_libresoc_interface2_err + connect \Y $or$ls180.v:5915$1126_Y + end + attribute \src "ls180.v:5915.32-5915.355" + cell $or $or$ls180.v:5915$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1126_Y + connect \B \main_libresocsim_libresoc_interface3_err + connect \Y $or$ls180.v:5915$1127_Y + end + attribute \src "ls180.v:5915.31-5915.401" + cell $or $or$ls180.v:5915$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1127_Y + connect \B \main_socbushandler_converted_interface_err + connect \Y $or$ls180.v:5915$1128_Y + end + attribute \src "ls180.v:5915.30-5915.448" + cell $or $or$ls180.v:5915$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5915$1128_Y + connect \B \builder_libresocsim_converted_interface_err + connect \Y $or$ls180.v:5915$1129_Y + end + attribute \src "ls180.v:5921.33-5921.88" + cell $or $or$ls180.v:5921$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_ram_bus_ram_bus_ack + connect \Y $or$ls180.v:5921$1134_Y + end + attribute \src "ls180.v:5921.32-5921.131" + cell $or $or$ls180.v:5921$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1134_Y + connect \B \main_interface0_converted_interface_ack + connect \Y $or$ls180.v:5921$1135_Y + end + attribute \src "ls180.v:5921.31-5921.174" + cell $or $or$ls180.v:5921$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1135_Y + connect \B \main_interface1_converted_interface_ack + connect \Y $or$ls180.v:5921$1136_Y + end + attribute \src "ls180.v:5921.30-5921.218" + cell $or $or$ls180.v:5921$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1136_Y + connect \B \main_libresocsim_libresoc_interface0_ack + connect \Y $or$ls180.v:5921$1137_Y + end + attribute \src "ls180.v:5921.29-5921.262" + cell $or $or$ls180.v:5921$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1137_Y + connect \B \main_libresocsim_libresoc_interface1_ack + connect \Y $or$ls180.v:5921$1138_Y + end + attribute \src "ls180.v:5921.28-5921.306" + cell $or $or$ls180.v:5921$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1138_Y + connect \B \main_libresocsim_libresoc_interface2_ack + connect \Y $or$ls180.v:5921$1139_Y + end + attribute \src "ls180.v:5921.27-5921.350" + cell $or $or$ls180.v:5921$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1139_Y + connect \B \main_libresocsim_libresoc_interface3_ack + connect \Y $or$ls180.v:5921$1140_Y + end + attribute \src "ls180.v:5921.26-5921.396" + cell $or $or$ls180.v:5921$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1140_Y + connect \B \main_socbushandler_converted_interface_ack + connect \Y $or$ls180.v:5921$1141_Y + end + attribute \src "ls180.v:5921.25-5921.443" + cell $or $or$ls180.v:5921$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5921$1141_Y + connect \B \builder_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:5921$1142_Y + end + attribute \src "ls180.v:5922.35-5922.160" + cell $or $or$ls180.v:5922$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:5922$1143_Y + connect \B $and$ls180.v:5922$1144_Y + connect \Y $or$ls180.v:5922$1145_Y + end + attribute \src "ls180.v:5922.34-5922.238" + cell $or $or$ls180.v:5922$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1145_Y + connect \B $and$ls180.v:5922$1146_Y + connect \Y $or$ls180.v:5922$1147_Y + end + attribute \src "ls180.v:5922.33-5922.316" + cell $or $or$ls180.v:5922$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1147_Y + connect \B $and$ls180.v:5922$1148_Y + connect \Y $or$ls180.v:5922$1149_Y + end + attribute \src "ls180.v:5922.32-5922.395" + cell $or $or$ls180.v:5922$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1149_Y + connect \B $and$ls180.v:5922$1150_Y + connect \Y $or$ls180.v:5922$1151_Y + end + attribute \src "ls180.v:5922.31-5922.474" + cell $or $or$ls180.v:5922$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1151_Y + connect \B $and$ls180.v:5922$1152_Y + connect \Y $or$ls180.v:5922$1153_Y + end + attribute \src "ls180.v:5922.30-5922.553" + cell $or $or$ls180.v:5922$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1153_Y + connect \B $and$ls180.v:5922$1154_Y + connect \Y $or$ls180.v:5922$1155_Y + end + attribute \src "ls180.v:5922.29-5922.632" + cell $or $or$ls180.v:5922$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1155_Y + connect \B $and$ls180.v:5922$1156_Y + connect \Y $or$ls180.v:5922$1157_Y + end + attribute \src "ls180.v:5922.28-5922.713" + cell $or $or$ls180.v:5922$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1157_Y + connect \B $and$ls180.v:5922$1158_Y + connect \Y $or$ls180.v:5922$1159_Y + end + attribute \src "ls180.v:5922.27-5922.795" + cell $or $or$ls180.v:5922$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5922$1159_Y + connect \B $and$ls180.v:5922$1160_Y + connect \Y $or$ls180.v:5922$1161_Y + end + attribute \src "ls180.v:6676.55-6676.124" + cell $or $or$ls180.v:6676$2307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2307_Y + end + attribute \src "ls180.v:6676.54-6676.161" + cell $or $or$ls180.v:6676$2308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2307_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2308_Y + end + attribute \src "ls180.v:6676.53-6676.198" + cell $or $or$ls180.v:6676$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2308_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2309_Y + end + attribute \src "ls180.v:6676.52-6676.235" + cell $or $or$ls180.v:6676$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2309_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2310_Y + end + attribute \src "ls180.v:6676.51-6676.272" + cell $or $or$ls180.v:6676$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2310_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2311_Y + end + attribute \src "ls180.v:6676.50-6676.309" + cell $or $or$ls180.v:6676$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2311_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2312_Y + end + attribute \src "ls180.v:6676.49-6676.346" + cell $or $or$ls180.v:6676$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2312_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2313_Y + end + attribute \src "ls180.v:6676.48-6676.383" + cell $or $or$ls180.v:6676$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2313_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2314_Y + end + attribute \src "ls180.v:6676.47-6676.420" + cell $or $or$ls180.v:6676$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2314_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2315_Y + end + attribute \src "ls180.v:6676.46-6676.458" + cell $or $or$ls180.v:6676$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2315_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2316_Y + end + attribute \src "ls180.v:6676.45-6676.496" + cell $or $or$ls180.v:6676$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2316_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2317_Y + end + attribute \src "ls180.v:6676.44-6676.534" + cell $or $or$ls180.v:6676$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2317_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2318_Y + end + attribute \src "ls180.v:6676.43-6676.572" + cell $or $or$ls180.v:6676$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2318_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2319_Y + end + attribute \src "ls180.v:6676.42-6676.610" + cell $or $or$ls180.v:6676$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6676$2319_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6676$2320_Y + end + attribute \src "ls180.v:7003.90-7003.179" + cell $or $or$ls180.v:7003$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:7003$2344_Y + connect \Y $or$ls180.v:7003$2345_Y + end + attribute \src "ls180.v:7003.89-7003.254" + cell $or $or$ls180.v:7003$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7003$2345_Y + connect \B $and$ls180.v:7003$2347_Y + connect \Y $or$ls180.v:7003$2348_Y + end + attribute \src "ls180.v:7003.88-7003.329" + cell $or $or$ls180.v:7003$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7003$2348_Y + connect \B $and$ls180.v:7003$2350_Y + connect \Y $or$ls180.v:7003$2351_Y + end + attribute \src "ls180.v:7027.90-7027.179" + cell $or $or$ls180.v:7027$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:7027$2360_Y + connect \Y $or$ls180.v:7027$2361_Y + end + attribute \src "ls180.v:7027.89-7027.254" + cell $or $or$ls180.v:7027$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7027$2361_Y + connect \B $and$ls180.v:7027$2363_Y + connect \Y $or$ls180.v:7027$2364_Y + end + attribute \src "ls180.v:7027.88-7027.329" + cell $or $or$ls180.v:7027$2367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7027$2364_Y + connect \B $and$ls180.v:7027$2366_Y + connect \Y $or$ls180.v:7027$2367_Y + end + attribute \src "ls180.v:7051.90-7051.179" + cell $or $or$ls180.v:7051$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:7051$2376_Y + connect \Y $or$ls180.v:7051$2377_Y + end + attribute \src "ls180.v:7051.89-7051.254" + cell $or $or$ls180.v:7051$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7051$2377_Y + connect \B $and$ls180.v:7051$2379_Y + connect \Y $or$ls180.v:7051$2380_Y + end + attribute \src "ls180.v:7051.88-7051.329" + cell $or $or$ls180.v:7051$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7051$2380_Y + connect \B $and$ls180.v:7051$2382_Y + connect \Y $or$ls180.v:7051$2383_Y + end + attribute \src "ls180.v:7075.90-7075.179" + cell $or $or$ls180.v:7075$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:7075$2392_Y + connect \Y $or$ls180.v:7075$2393_Y + end + attribute \src "ls180.v:7075.89-7075.254" + cell $or $or$ls180.v:7075$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7075$2393_Y + connect \B $and$ls180.v:7075$2395_Y + connect \Y $or$ls180.v:7075$2396_Y + end + attribute \src "ls180.v:7075.88-7075.329" + cell $or $or$ls180.v:7075$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7075$2396_Y + connect \B $and$ls180.v:7075$2398_Y + connect \Y $or$ls180.v:7075$2399_Y + end + attribute \src "ls180.v:7592.20-7592.71" + cell $or $or$ls180.v:7592$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7592$2459_Y + end + attribute \src "ls180.v:7593.20-7593.71" + cell $or $or$ls180.v:7593$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7593$2460_Y + end + attribute \src "ls180.v:7594.20-7594.71" + cell $or $or$ls180.v:7594$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7594$2461_Y + end + attribute \src "ls180.v:7595.20-7595.71" + cell $or $or$ls180.v:7595$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7595$2462_Y + end + attribute \src "ls180.v:7596.20-7596.71" + cell $or $or$ls180.v:7596$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7596$2463_Y + end + attribute \src "ls180.v:7597.20-7597.71" + cell $or $or$ls180.v:7597$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7597$2464_Y + end + attribute \src "ls180.v:7598.20-7598.71" + cell $or $or$ls180.v:7598$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7598$2465_Y + end + attribute \src "ls180.v:7599.20-7599.71" + cell $or $or$ls180.v:7599$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7599$2466_Y + end + attribute \src "ls180.v:7600.20-7600.71" + cell $or $or$ls180.v:7600$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7600$2467_Y + end + attribute \src "ls180.v:7601.20-7601.71" + cell $or $or$ls180.v:7601$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7601$2468_Y + end + attribute \src "ls180.v:7602.21-7602.73" + cell $or $or$ls180.v:7602$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7602$2469_Y + end + attribute \src "ls180.v:7603.21-7603.73" + cell $or $or$ls180.v:7603$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7603$2470_Y + end + attribute \src "ls180.v:7604.21-7604.73" + cell $or $or$ls180.v:7604$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7604$2471_Y + end + attribute \src "ls180.v:7605.21-7605.73" + cell $or $or$ls180.v:7605$2472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7605$2472_Y + end + attribute \src "ls180.v:7606.21-7606.73" + cell $or $or$ls180.v:7606$2473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7606$2473_Y + end + attribute \src "ls180.v:7607.21-7607.73" + cell $or $or$ls180.v:7607$2474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7607$2474_Y + end + attribute \src "ls180.v:7608.21-7608.73" + cell $or $or$ls180.v:7608$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7608$2475_Y + end + attribute \src "ls180.v:7609.21-7609.73" + cell $or $or$ls180.v:7609$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7609$2476_Y + end + attribute \src "ls180.v:7610.21-7610.73" + cell $or $or$ls180.v:7610$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7610$2477_Y + end + attribute \src "ls180.v:7611.21-7611.73" + cell $or $or$ls180.v:7611$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7611$2478_Y + end + attribute \src "ls180.v:7612.21-7612.73" + cell $or $or$ls180.v:7612$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7612$2479_Y + end + attribute \src "ls180.v:7613.21-7613.73" + cell $or $or$ls180.v:7613$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7613$2480_Y + end + attribute \src "ls180.v:7614.21-7614.73" + cell $or $or$ls180.v:7614$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7614$2481_Y + end + attribute \src "ls180.v:7615.21-7615.73" + cell $or $or$ls180.v:7615$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7615$2482_Y + end + attribute \src "ls180.v:7616.7-7616.68" + cell $or $or$ls180.v:7616$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:7616$2483_Y + end + attribute \src "ls180.v:7627.7-7627.68" + cell $or $or$ls180.v:7627$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:7627$2484_Y + end + attribute \src "ls180.v:7638.7-7638.50" + cell $or $or$ls180.v:7638$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:7638$2485_Y + end + attribute \src "ls180.v:7771.7-7771.107" + cell $or $or$ls180.v:7771$2524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7771$2523_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7771$2524_Y + end + attribute \src "ls180.v:7817.7-7817.107" + cell $or $or$ls180.v:7817$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7817$2539_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7817$2540_Y + end + attribute \src "ls180.v:7863.7-7863.107" + cell $or $or$ls180.v:7863$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7863$2555_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7863$2556_Y + end + attribute \src "ls180.v:7909.7-7909.107" + cell $or $or$ls180.v:7909$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7909$2571_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:7909$2572_Y + end + attribute \src "ls180.v:8097.40-8097.125" + cell $or $or$ls180.v:8097$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:8097$2592_Y + connect \Y $or$ls180.v:8097$2593_Y + end + attribute \src "ls180.v:8097.39-8097.207" + cell $or $or$ls180.v:8097$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8097$2593_Y + connect \B $and$ls180.v:8097$2595_Y + connect \Y $or$ls180.v:8097$2596_Y + end + attribute \src "ls180.v:8097.38-8097.289" + cell $or $or$ls180.v:8097$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8097$2596_Y + connect \B $and$ls180.v:8097$2598_Y + connect \Y $or$ls180.v:8097$2599_Y + end + attribute \src "ls180.v:8097.37-8097.371" + cell $or $or$ls180.v:8097$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8097$2599_Y + connect \B $and$ls180.v:8097$2601_Y + connect \Y $or$ls180.v:8097$2602_Y + end + attribute \src "ls180.v:8098.41-8098.126" + cell $or $or$ls180.v:8098$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:8098$2604_Y + connect \Y $or$ls180.v:8098$2605_Y + end + attribute \src "ls180.v:8098.40-8098.208" + cell $or $or$ls180.v:8098$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8098$2605_Y + connect \B $and$ls180.v:8098$2607_Y + connect \Y $or$ls180.v:8098$2608_Y + end + attribute \src "ls180.v:8098.39-8098.290" + cell $or $or$ls180.v:8098$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8098$2608_Y + connect \B $and$ls180.v:8098$2610_Y + connect \Y $or$ls180.v:8098$2611_Y + end + attribute \src "ls180.v:8098.38-8098.372" + cell $or $or$ls180.v:8098$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8098$2611_Y + connect \B $and$ls180.v:8098$2613_Y + connect \Y $or$ls180.v:8098$2614_Y + end + attribute \src "ls180.v:8102.7-8102.49" + cell $or $or$ls180.v:8102$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:8102$2615_Y + end + attribute \src "ls180.v:8265.21-8265.74" + cell $or $or$ls180.v:8265$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8265$2661_Y + connect \B $not$ls180.v:8265$2662_Y + connect \Y $or$ls180.v:8265$2663_Y + end + attribute \src "ls180.v:8300.21-8300.71" + cell $or $or$ls180.v:8300$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8300$2666_Y + connect \B $not$ls180.v:8300$2667_Y + connect \Y $or$ls180.v:8300$2668_Y + end + attribute \src "ls180.v:8368.32-8368.85" + cell $or $or$ls180.v:8368$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8368$2680_Y + end + attribute \src "ls180.v:8374.8-8374.97" + cell $or $or$ls180.v:8374$2682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8374$2681_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8374$2682_Y + end + attribute \src "ls180.v:8391.52-8391.139" + cell $or $or$ls180.v:8391$2687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8391$2687_Y + end + attribute \src "ls180.v:8392.51-8392.136" + cell $or $or$ls180.v:8392$2688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8392$2688_Y + end + attribute \src "ls180.v:8426.7-8426.87" + cell $or $or$ls180.v:8426$2691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8426$2690_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8426$2691_Y + end + attribute \src "ls180.v:8449.33-8449.88" + cell $or $or$ls180.v:8449$2692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8449$2692_Y + end + attribute \src "ls180.v:8455.8-8455.99" + cell $or $or$ls180.v:8455$2694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8455$2693_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8455$2694_Y + end + attribute \src "ls180.v:8472.53-8472.142" + cell $or $or$ls180.v:8472$2699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8472$2699_Y + end + attribute \src "ls180.v:8473.52-8473.139" + cell $or $or$ls180.v:8473$2700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8473$2700_Y + end + attribute \src "ls180.v:8507.7-8507.89" + cell $or $or$ls180.v:8507$2703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8507$2702_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8507$2703_Y + end + attribute \src "ls180.v:8528.34-8528.91" + cell $or $or$ls180.v:8528$2704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8528$2704_Y + end + attribute \src "ls180.v:8534.8-8534.101" + cell $or $or$ls180.v:8534$2706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8534$2705_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8534$2706_Y + end + attribute \src "ls180.v:8551.54-8551.145" + cell $or $or$ls180.v:8551$2711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8551$2711_Y + end + attribute \src "ls180.v:8552.53-8552.142" + cell $or $or$ls180.v:8552$2712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8552$2712_Y + end + attribute \src "ls180.v:8568.7-8568.91" + cell $or $or$ls180.v:8568$2715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8568$2714_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8568$2715_Y + end + attribute \src "ls180.v:8757.8-8757.89" + cell $or $or$ls180.v:8757$2739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8757$2738_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8757$2739_Y + end + attribute \src "ls180.v:8774.48-8774.127" + cell $or $or$ls180.v:8774$2744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8774$2744_Y + end + attribute \src "ls180.v:8775.47-8775.124" + cell $or $or$ls180.v:8775$2745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8775$2745_Y + end + attribute \src "ls180.v:3271.46-3271.94" + cell $sshl $sshl$ls180.v:3271$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3271$132_Y + end + attribute \src "ls180.v:3428.46-3428.94" + cell $sshl $sshl$ls180.v:3428$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3428$162_Y + end + attribute \src "ls180.v:3585.46-3585.94" + cell $sshl $sshl$ls180.v:3585$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3585$192_Y + end + attribute \src "ls180.v:3742.46-3742.94" + cell $sshl $sshl$ls180.v:3742$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3742$222_Y + end + attribute \src "ls180.v:3302.63-3302.122" + cell $sub $sub$ls180.v:3302$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3302$145_Y + end + attribute \src "ls180.v:3459.63-3459.122" + cell $sub $sub$ls180.v:3459$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3459$175_Y + end + attribute \src "ls180.v:3616.63-3616.122" + cell $sub $sub$ls180.v:3616$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3616$205_Y + end + attribute \src "ls180.v:3773.63-3773.122" + cell $sub $sub$ls180.v:3773$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3773$235_Y + end + attribute \src "ls180.v:4179.38-4179.75" + cell $sub $sub$ls180.v:4179$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4179$589_Y + end + attribute \src "ls180.v:4265.36-4265.68" + cell $sub $sub$ls180.v:4265$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4265$634_Y + end + attribute \src "ls180.v:4295.36-4295.68" + cell $sub $sub$ls180.v:4295$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4295$645_Y + end + attribute \src "ls180.v:4331.70-4331.110" + cell $sub $sub$ls180.v:4331$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4331$653_Y + end + attribute \src "ls180.v:4332.70-4332.104" + cell $sub $sub$ls180.v:4332$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider + connect \B 1'1 + connect \Y $sub$ls180.v:4332$655_Y + end + attribute \src "ls180.v:4359.37-4359.66" + cell $sub $sub$ls180.v:4359$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spimaster1_length + connect \B 1'1 + connect \Y $sub$ls180.v:4359$659_Y + end + attribute \src "ls180.v:4389.67-4389.107" + cell $sub $sub$ls180.v:4389$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4389$661_Y + end + attribute \src "ls180.v:4390.67-4390.101" + cell $sub $sub$ls180.v:4390$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4390$663_Y + end + attribute \src "ls180.v:4418.35-4418.64" + cell $sub $sub$ls180.v:4418$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spisdcard_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4418$667_Y + end + attribute \src "ls180.v:4672.60-4672.90" + cell $sub $sub$ls180.v:4672$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4672$711_Y + end + attribute \src "ls180.v:4683.62-4683.104" + cell $sub $sub$ls180.v:4683$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4683$713_Y + end + attribute \src "ls180.v:4700.60-4700.90" + cell $sub $sub$ls180.v:4700$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4700$717_Y + end + attribute \src "ls180.v:4929.62-4929.93" + cell $sub $sub$ls180.v:4929$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4929$747_Y + end + attribute \src "ls180.v:4934.62-4934.93" + cell $sub $sub$ls180.v:4934$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4934$748_Y + end + attribute \src "ls180.v:4945.64-4945.122" + cell $sub $sub$ls180.v:4945$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:4945$750_Y + connect \B 1'1 + connect \Y $sub$ls180.v:4945$751_Y + end + attribute \src "ls180.v:4966.62-4966.93" + cell $sub $sub$ls180.v:4966$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4966$754_Y + end + attribute \src "ls180.v:5428.37-5428.75" + cell $sub $sub$ls180.v:5428$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5428$1027_Y + end + attribute \src "ls180.v:5443.62-5443.100" + cell $sub $sub$ls180.v:5443$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5443$1030_Y + end + attribute \src "ls180.v:5454.39-5454.77" + cell $sub $sub$ls180.v:5454$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5454$1035_Y + end + attribute \src "ls180.v:5529.40-5529.76" + cell $sub $sub$ls180.v:5529$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5529$1039_Y + end + attribute \src "ls180.v:5578.56-5578.104" + cell $sub $sub$ls180.v:5578$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5578$1053_Y + end + attribute \src "ls180.v:5668.71-5668.105" + cell $sub $sub$ls180.v:5668$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5668$1059_Y + end + attribute \src "ls180.v:5749.40-5749.76" + cell $sub $sub$ls180.v:5749$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5749$1070_Y + end + attribute \src "ls180.v:7662.31-7662.60" + cell $sub $sub$ls180.v:7662$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7662$2492_Y + end + attribute \src "ls180.v:7687.31-7687.61" + cell $sub $sub$ls180.v:7687$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7687$2500_Y + end + attribute \src "ls180.v:7693.34-7693.67" + cell $sub $sub$ls180.v:7693$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7693$2501_Y + end + attribute \src "ls180.v:7704.36-7704.69" + cell $sub $sub$ls180.v:7704$2504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7704$2504_Y + end + attribute \src "ls180.v:7768.59-7768.116" + cell $sub $sub$ls180.v:7768$2522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7768$2522_Y + end + attribute \src "ls180.v:7787.46-7787.90" + cell $sub $sub$ls180.v:7787$2526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7787$2526_Y + end + attribute \src "ls180.v:7814.59-7814.116" + cell $sub $sub$ls180.v:7814$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7814$2538_Y + end + attribute \src "ls180.v:7833.46-7833.90" + cell $sub $sub$ls180.v:7833$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7833$2542_Y + end + attribute \src "ls180.v:7860.59-7860.116" + cell $sub $sub$ls180.v:7860$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7860$2554_Y + end + attribute \src "ls180.v:7879.46-7879.90" + cell $sub $sub$ls180.v:7879$2558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7879$2558_Y + end + attribute \src "ls180.v:7906.59-7906.116" + cell $sub $sub$ls180.v:7906$2570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7906$2570_Y + end + attribute \src "ls180.v:7925.46-7925.90" + cell $sub $sub$ls180.v:7925$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7925$2574_Y + end + attribute \src "ls180.v:7936.25-7936.48" + cell $sub $sub$ls180.v:7936$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:7936$2578_Y + end + attribute \src "ls180.v:7943.25-7943.48" + cell $sub $sub$ls180.v:7943$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:7943$2581_Y + end + attribute \src "ls180.v:8075.33-8075.64" + cell $sub $sub$ls180.v:8075$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8075$2586_Y + end + attribute \src "ls180.v:8090.33-8090.64" + cell $sub $sub$ls180.v:8090$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8090$2589_Y + end + attribute \src "ls180.v:8217.33-8217.64" + cell $sub $sub$ls180.v:8217$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8217$2648_Y + end + attribute \src "ls180.v:8239.33-8239.64" + cell $sub $sub$ls180.v:8239$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8239$2659_Y + end + attribute \src "ls180.v:8274.34-8274.66" + cell $sub $sub$ls180.v:8274$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster34_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8274$2664_Y + end + attribute \src "ls180.v:8309.32-8309.62" + cell $sub $sub$ls180.v:8309$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8309$2669_Y + end + attribute \src "ls180.v:8333.30-8333.53" + cell $sub $sub$ls180.v:8333$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8333$2672_Y + end + attribute \src "ls180.v:8347.30-8347.53" + cell $sub $sub$ls180.v:8347$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8347$2676_Y + end + attribute \src "ls180.v:8750.36-8750.70" + cell $sub $sub$ls180.v:8750$2737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8750$2737_Y + end + attribute \src "ls180.v:8848.36-8848.70" + cell $sub $sub$ls180.v:8848$2759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8848$2759_Y + end + attribute \src "ls180.v:8961.22-8961.42" + cell $sub $sub$ls180.v:8961$2766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:8961$2766_Y + end + attribute \src "ls180.v:5026.353-5026.425" + cell $xor $xor$ls180.v:5026$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:5026$761_Y + end + attribute \src "ls180.v:5026.200-5026.272" + cell $xor $xor$ls180.v:5026$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:5026$762_Y + end + attribute \src "ls180.v:5026.160-5026.273" + cell $xor $xor$ls180.v:5026$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:5026$762_Y + connect \Y $xor$ls180.v:5026$763_Y + end + attribute \src "ls180.v:5027.353-5027.425" + cell $xor $xor$ls180.v:5027$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:5027$764_Y + end + attribute \src "ls180.v:5027.200-5027.272" + cell $xor $xor$ls180.v:5027$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:5027$765_Y + end + attribute \src "ls180.v:5027.160-5027.273" + cell $xor $xor$ls180.v:5027$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:5027$765_Y + connect \Y $xor$ls180.v:5027$766_Y + end + attribute \src "ls180.v:5028.353-5028.425" + cell $xor $xor$ls180.v:5028$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:5028$767_Y + end + attribute \src "ls180.v:5028.200-5028.272" + cell $xor $xor$ls180.v:5028$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:5028$768_Y + end + attribute \src "ls180.v:5028.160-5028.273" + cell $xor $xor$ls180.v:5028$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:5028$768_Y + connect \Y $xor$ls180.v:5028$769_Y + end + attribute \src "ls180.v:5029.353-5029.425" + cell $xor $xor$ls180.v:5029$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:5029$770_Y + end + attribute \src "ls180.v:5029.200-5029.272" + cell $xor $xor$ls180.v:5029$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:5029$771_Y + end + attribute \src "ls180.v:5029.160-5029.273" + cell $xor $xor$ls180.v:5029$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:5029$771_Y + connect \Y $xor$ls180.v:5029$772_Y + end + attribute \src "ls180.v:5030.353-5030.425" + cell $xor $xor$ls180.v:5030$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:5030$773_Y + end + attribute \src "ls180.v:5030.200-5030.272" + cell $xor $xor$ls180.v:5030$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:5030$774_Y + end + attribute \src "ls180.v:5030.160-5030.273" + cell $xor $xor$ls180.v:5030$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:5030$774_Y + connect \Y $xor$ls180.v:5030$775_Y + end + attribute \src "ls180.v:5031.353-5031.425" + cell $xor $xor$ls180.v:5031$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:5031$776_Y + end + attribute \src "ls180.v:5031.200-5031.272" + cell $xor $xor$ls180.v:5031$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:5031$777_Y + end + attribute \src "ls180.v:5031.160-5031.273" + cell $xor $xor$ls180.v:5031$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:5031$777_Y + connect \Y $xor$ls180.v:5031$778_Y + end + attribute \src "ls180.v:5032.353-5032.425" + cell $xor $xor$ls180.v:5032$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:5032$779_Y + end + attribute \src "ls180.v:5032.200-5032.272" + cell $xor $xor$ls180.v:5032$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:5032$780_Y + end + attribute \src "ls180.v:5032.160-5032.273" + cell $xor $xor$ls180.v:5032$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:5032$780_Y + connect \Y $xor$ls180.v:5032$781_Y + end + attribute \src "ls180.v:5033.353-5033.425" + cell $xor $xor$ls180.v:5033$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:5033$782_Y + end + attribute \src "ls180.v:5033.200-5033.272" + cell $xor $xor$ls180.v:5033$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:5033$783_Y + end + attribute \src "ls180.v:5033.160-5033.273" + cell $xor $xor$ls180.v:5033$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:5033$783_Y + connect \Y $xor$ls180.v:5033$784_Y + end + attribute \src "ls180.v:5034.353-5034.425" + cell $xor $xor$ls180.v:5034$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:5034$785_Y + end + attribute \src "ls180.v:5034.200-5034.272" + cell $xor $xor$ls180.v:5034$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:5034$786_Y + end + attribute \src "ls180.v:5034.160-5034.273" + cell $xor $xor$ls180.v:5034$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:5034$786_Y + connect \Y $xor$ls180.v:5034$787_Y + end + attribute \src "ls180.v:5035.354-5035.426" + cell $xor $xor$ls180.v:5035$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:5035$788_Y + end + attribute \src "ls180.v:5035.201-5035.273" + cell $xor $xor$ls180.v:5035$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:5035$789_Y + end + attribute \src "ls180.v:5035.161-5035.274" + cell $xor $xor$ls180.v:5035$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:5035$789_Y + connect \Y $xor$ls180.v:5035$790_Y + end + attribute \src "ls180.v:5036.361-5036.434" + cell $xor $xor$ls180.v:5036$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:5036$791_Y + end + attribute \src "ls180.v:5036.205-5036.278" + cell $xor $xor$ls180.v:5036$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:5036$792_Y + end + attribute \src "ls180.v:5036.164-5036.279" + cell $xor $xor$ls180.v:5036$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:5036$792_Y + connect \Y $xor$ls180.v:5036$793_Y + end + attribute \src "ls180.v:5037.361-5037.434" + cell $xor $xor$ls180.v:5037$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:5037$794_Y + end + attribute \src "ls180.v:5037.205-5037.278" + cell $xor $xor$ls180.v:5037$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:5037$795_Y + end + attribute \src "ls180.v:5037.164-5037.279" + cell $xor $xor$ls180.v:5037$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:5037$795_Y + connect \Y $xor$ls180.v:5037$796_Y + end + attribute \src "ls180.v:5038.361-5038.434" + cell $xor $xor$ls180.v:5038$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:5038$797_Y + end + attribute \src "ls180.v:5038.205-5038.278" + cell $xor $xor$ls180.v:5038$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:5038$798_Y + end + attribute \src "ls180.v:5038.164-5038.279" + cell $xor $xor$ls180.v:5038$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:5038$798_Y + connect \Y $xor$ls180.v:5038$799_Y + end + attribute \src "ls180.v:5039.361-5039.434" + cell $xor $xor$ls180.v:5039$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:5039$800_Y + end + attribute \src "ls180.v:5039.205-5039.278" + cell $xor $xor$ls180.v:5039$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:5039$801_Y + end + attribute \src "ls180.v:5039.164-5039.279" + cell $xor $xor$ls180.v:5039$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:5039$801_Y + connect \Y $xor$ls180.v:5039$802_Y + end + attribute \src "ls180.v:5040.361-5040.434" + cell $xor $xor$ls180.v:5040$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:5040$803_Y + end + attribute \src "ls180.v:5040.205-5040.278" + cell $xor $xor$ls180.v:5040$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:5040$804_Y + end + attribute \src "ls180.v:5040.164-5040.279" + cell $xor $xor$ls180.v:5040$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:5040$804_Y + connect \Y $xor$ls180.v:5040$805_Y + end + attribute \src "ls180.v:5041.361-5041.434" + cell $xor $xor$ls180.v:5041$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:5041$806_Y + end + attribute \src "ls180.v:5041.205-5041.278" + cell $xor $xor$ls180.v:5041$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:5041$807_Y + end + attribute \src "ls180.v:5041.164-5041.279" + cell $xor $xor$ls180.v:5041$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:5041$807_Y + connect \Y $xor$ls180.v:5041$808_Y + end + attribute \src "ls180.v:5042.361-5042.434" + cell $xor $xor$ls180.v:5042$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:5042$809_Y + end + attribute \src "ls180.v:5042.205-5042.278" + cell $xor $xor$ls180.v:5042$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:5042$810_Y + end + attribute \src "ls180.v:5042.164-5042.279" + cell $xor $xor$ls180.v:5042$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:5042$810_Y + connect \Y $xor$ls180.v:5042$811_Y + end + attribute \src "ls180.v:5043.361-5043.434" + cell $xor $xor$ls180.v:5043$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:5043$812_Y + end + attribute \src "ls180.v:5043.205-5043.278" + cell $xor $xor$ls180.v:5043$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:5043$813_Y + end + attribute \src "ls180.v:5043.164-5043.279" + cell $xor $xor$ls180.v:5043$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:5043$813_Y + connect \Y $xor$ls180.v:5043$814_Y + end + attribute \src "ls180.v:5044.361-5044.434" + cell $xor $xor$ls180.v:5044$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:5044$815_Y + end + attribute \src "ls180.v:5044.205-5044.278" + cell $xor $xor$ls180.v:5044$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:5044$816_Y + end + attribute \src "ls180.v:5044.164-5044.279" + cell $xor $xor$ls180.v:5044$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:5044$816_Y + connect \Y $xor$ls180.v:5044$817_Y + end + attribute \src "ls180.v:5045.361-5045.434" + cell $xor $xor$ls180.v:5045$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:5045$818_Y + end + attribute \src "ls180.v:5045.205-5045.278" + cell $xor $xor$ls180.v:5045$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:5045$819_Y + end + attribute \src "ls180.v:5045.164-5045.279" + cell $xor $xor$ls180.v:5045$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:5045$819_Y + connect \Y $xor$ls180.v:5045$820_Y + end + attribute \src "ls180.v:5046.361-5046.434" + cell $xor $xor$ls180.v:5046$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:5046$821_Y + end + attribute \src "ls180.v:5046.205-5046.278" + cell $xor $xor$ls180.v:5046$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:5046$822_Y + end + attribute \src "ls180.v:5046.164-5046.279" + cell $xor $xor$ls180.v:5046$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:5046$822_Y + connect \Y $xor$ls180.v:5046$823_Y + end + attribute \src "ls180.v:5047.361-5047.434" + cell $xor $xor$ls180.v:5047$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:5047$824_Y + end + attribute \src "ls180.v:5047.205-5047.278" + cell $xor $xor$ls180.v:5047$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:5047$825_Y + end + attribute \src "ls180.v:5047.164-5047.279" + cell $xor $xor$ls180.v:5047$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:5047$825_Y + connect \Y $xor$ls180.v:5047$826_Y + end + attribute \src "ls180.v:5048.361-5048.434" + cell $xor $xor$ls180.v:5048$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:5048$827_Y + end + attribute \src "ls180.v:5048.205-5048.278" + cell $xor $xor$ls180.v:5048$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:5048$828_Y + end + attribute \src "ls180.v:5048.164-5048.279" + cell $xor $xor$ls180.v:5048$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:5048$828_Y + connect \Y $xor$ls180.v:5048$829_Y + end + attribute \src "ls180.v:5049.361-5049.434" + cell $xor $xor$ls180.v:5049$830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:5049$830_Y + end + attribute \src "ls180.v:5049.205-5049.278" + cell $xor $xor$ls180.v:5049$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:5049$831_Y + end + attribute \src "ls180.v:5049.164-5049.279" + cell $xor $xor$ls180.v:5049$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:5049$831_Y + connect \Y $xor$ls180.v:5049$832_Y + end + attribute \src "ls180.v:5050.361-5050.434" + cell $xor $xor$ls180.v:5050$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:5050$833_Y + end + attribute \src "ls180.v:5050.205-5050.278" + cell $xor $xor$ls180.v:5050$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:5050$834_Y + end + attribute \src "ls180.v:5050.164-5050.279" + cell $xor $xor$ls180.v:5050$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:5050$834_Y + connect \Y $xor$ls180.v:5050$835_Y + end + attribute \src "ls180.v:5051.361-5051.434" + cell $xor $xor$ls180.v:5051$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:5051$836_Y + end + attribute \src "ls180.v:5051.205-5051.278" + cell $xor $xor$ls180.v:5051$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:5051$837_Y + end + attribute \src "ls180.v:5051.164-5051.279" + cell $xor $xor$ls180.v:5051$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:5051$837_Y + connect \Y $xor$ls180.v:5051$838_Y + end + attribute \src "ls180.v:5052.361-5052.434" + cell $xor $xor$ls180.v:5052$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:5052$839_Y + end + attribute \src "ls180.v:5052.205-5052.278" + cell $xor $xor$ls180.v:5052$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:5052$840_Y + end + attribute \src "ls180.v:5052.164-5052.279" + cell $xor $xor$ls180.v:5052$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:5052$840_Y + connect \Y $xor$ls180.v:5052$841_Y + end + attribute \src "ls180.v:5053.361-5053.434" + cell $xor $xor$ls180.v:5053$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:5053$842_Y + end + attribute \src "ls180.v:5053.205-5053.278" + cell $xor $xor$ls180.v:5053$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:5053$843_Y + end + attribute \src "ls180.v:5053.164-5053.279" + cell $xor $xor$ls180.v:5053$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:5053$843_Y + connect \Y $xor$ls180.v:5053$844_Y + end + attribute \src "ls180.v:5054.361-5054.434" + cell $xor $xor$ls180.v:5054$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:5054$845_Y + end + attribute \src "ls180.v:5054.205-5054.278" + cell $xor $xor$ls180.v:5054$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:5054$846_Y + end + attribute \src "ls180.v:5054.164-5054.279" + cell $xor $xor$ls180.v:5054$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:5054$846_Y + connect \Y $xor$ls180.v:5054$847_Y + end + attribute \src "ls180.v:5055.361-5055.434" + cell $xor $xor$ls180.v:5055$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:5055$848_Y + end + attribute \src "ls180.v:5055.205-5055.278" + cell $xor $xor$ls180.v:5055$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:5055$849_Y + end + attribute \src "ls180.v:5055.164-5055.279" + cell $xor $xor$ls180.v:5055$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:5055$849_Y + connect \Y $xor$ls180.v:5055$850_Y + end + attribute \src "ls180.v:5056.360-5056.432" + cell $xor $xor$ls180.v:5056$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:5056$851_Y + end + attribute \src "ls180.v:5056.205-5056.277" + cell $xor $xor$ls180.v:5056$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:5056$852_Y + end + attribute \src "ls180.v:5056.164-5056.278" + cell $xor $xor$ls180.v:5056$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:5056$852_Y + connect \Y $xor$ls180.v:5056$853_Y + end + attribute \src "ls180.v:5057.360-5057.432" + cell $xor $xor$ls180.v:5057$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:5057$854_Y + end + attribute \src "ls180.v:5057.205-5057.277" + cell $xor $xor$ls180.v:5057$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:5057$855_Y + end + attribute \src "ls180.v:5057.164-5057.278" + cell $xor $xor$ls180.v:5057$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:5057$855_Y + connect \Y $xor$ls180.v:5057$856_Y + end + attribute \src "ls180.v:5058.360-5058.432" + cell $xor $xor$ls180.v:5058$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:5058$857_Y + end + attribute \src "ls180.v:5058.205-5058.277" + cell $xor $xor$ls180.v:5058$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:5058$858_Y + end + attribute \src "ls180.v:5058.164-5058.278" + cell $xor $xor$ls180.v:5058$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:5058$858_Y + connect \Y $xor$ls180.v:5058$859_Y + end + attribute \src "ls180.v:5059.360-5059.432" + cell $xor $xor$ls180.v:5059$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:5059$860_Y + end + attribute \src "ls180.v:5059.205-5059.277" + cell $xor $xor$ls180.v:5059$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:5059$861_Y + end + attribute \src "ls180.v:5059.164-5059.278" + cell $xor $xor$ls180.v:5059$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:5059$861_Y + connect \Y $xor$ls180.v:5059$862_Y + end + attribute \src "ls180.v:5060.360-5060.432" + cell $xor $xor$ls180.v:5060$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:5060$863_Y + end + attribute \src "ls180.v:5060.205-5060.277" + cell $xor $xor$ls180.v:5060$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:5060$864_Y + end + attribute \src "ls180.v:5060.164-5060.278" + cell $xor $xor$ls180.v:5060$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:5060$864_Y + connect \Y $xor$ls180.v:5060$865_Y + end + attribute \src "ls180.v:5061.360-5061.432" + cell $xor $xor$ls180.v:5061$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:5061$866_Y + end + attribute \src "ls180.v:5061.205-5061.277" + cell $xor $xor$ls180.v:5061$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:5061$867_Y + end + attribute \src "ls180.v:5061.164-5061.278" + cell $xor $xor$ls180.v:5061$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:5061$867_Y + connect \Y $xor$ls180.v:5061$868_Y + end + attribute \src "ls180.v:5062.360-5062.432" + cell $xor $xor$ls180.v:5062$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:5062$869_Y + end + attribute \src "ls180.v:5062.205-5062.277" + cell $xor $xor$ls180.v:5062$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:5062$870_Y + end + attribute \src "ls180.v:5062.164-5062.278" + cell $xor $xor$ls180.v:5062$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:5062$870_Y + connect \Y $xor$ls180.v:5062$871_Y + end + attribute \src "ls180.v:5063.360-5063.432" + cell $xor $xor$ls180.v:5063$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:5063$872_Y + end + attribute \src "ls180.v:5063.205-5063.277" + cell $xor $xor$ls180.v:5063$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:5063$873_Y + end + attribute \src "ls180.v:5063.164-5063.278" + cell $xor $xor$ls180.v:5063$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:5063$873_Y + connect \Y $xor$ls180.v:5063$874_Y + end + attribute \src "ls180.v:5064.360-5064.432" + cell $xor $xor$ls180.v:5064$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:5064$875_Y + end + attribute \src "ls180.v:5064.205-5064.277" + cell $xor $xor$ls180.v:5064$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:5064$876_Y + end + attribute \src "ls180.v:5064.164-5064.278" + cell $xor $xor$ls180.v:5064$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:5064$876_Y + connect \Y $xor$ls180.v:5064$877_Y + end + attribute \src "ls180.v:5065.360-5065.432" + cell $xor $xor$ls180.v:5065$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:5065$878_Y + end + attribute \src "ls180.v:5065.205-5065.277" + cell $xor $xor$ls180.v:5065$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:5065$879_Y + end + attribute \src "ls180.v:5065.164-5065.278" + cell $xor $xor$ls180.v:5065$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:5065$879_Y + connect \Y $xor$ls180.v:5065$880_Y + end + attribute \src "ls180.v:5086.899-5086.983" + cell $xor $xor$ls180.v:5086$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5086$894_Y + end + attribute \src "ls180.v:5086.634-5086.718" + cell $xor $xor$ls180.v:5086$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5086$895_Y + end + attribute \src "ls180.v:5086.588-5086.719" + cell $xor $xor$ls180.v:5086$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5086$895_Y + connect \Y $xor$ls180.v:5086$896_Y + end + attribute \src "ls180.v:5086.234-5086.318" + cell $xor $xor$ls180.v:5086$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5086$897_Y + end + attribute \src "ls180.v:5086.187-5086.319" + cell $xor $xor$ls180.v:5086$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5086$897_Y + connect \Y $xor$ls180.v:5086$898_Y + end + attribute \src "ls180.v:5087.899-5087.983" + cell $xor $xor$ls180.v:5087$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5087$899_Y + end + attribute \src "ls180.v:5087.634-5087.718" + cell $xor $xor$ls180.v:5087$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5087$900_Y + end + attribute \src "ls180.v:5087.588-5087.719" + cell $xor $xor$ls180.v:5087$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5087$900_Y + connect \Y $xor$ls180.v:5087$901_Y + end + attribute \src "ls180.v:5087.234-5087.318" + cell $xor $xor$ls180.v:5087$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5087$902_Y + end + attribute \src "ls180.v:5087.187-5087.319" + cell $xor $xor$ls180.v:5087$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5087$902_Y + connect \Y $xor$ls180.v:5087$903_Y + end + attribute \src "ls180.v:5096.899-5096.983" + cell $xor $xor$ls180.v:5096$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5096$905_Y + end + attribute \src "ls180.v:5096.634-5096.718" + cell $xor $xor$ls180.v:5096$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5096$906_Y + end + attribute \src "ls180.v:5096.588-5096.719" + cell $xor $xor$ls180.v:5096$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5096$906_Y + connect \Y $xor$ls180.v:5096$907_Y + end + attribute \src "ls180.v:5096.234-5096.318" + cell $xor $xor$ls180.v:5096$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5096$908_Y + end + attribute \src "ls180.v:5096.187-5096.319" + cell $xor $xor$ls180.v:5096$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5096$908_Y + connect \Y $xor$ls180.v:5096$909_Y + end + attribute \src "ls180.v:5097.899-5097.983" + cell $xor $xor$ls180.v:5097$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5097$910_Y + end + attribute \src "ls180.v:5097.634-5097.718" + cell $xor $xor$ls180.v:5097$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5097$911_Y + end + attribute \src "ls180.v:5097.588-5097.719" + cell $xor $xor$ls180.v:5097$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5097$911_Y + connect \Y $xor$ls180.v:5097$912_Y + end + attribute \src "ls180.v:5097.234-5097.318" + cell $xor $xor$ls180.v:5097$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5097$913_Y + end + attribute \src "ls180.v:5097.187-5097.319" + cell $xor $xor$ls180.v:5097$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5097$913_Y + connect \Y $xor$ls180.v:5097$914_Y + end + attribute \src "ls180.v:5106.899-5106.983" + cell $xor $xor$ls180.v:5106$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5106$916_Y + end + attribute \src "ls180.v:5106.634-5106.718" + cell $xor $xor$ls180.v:5106$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5106$917_Y + end + attribute \src "ls180.v:5106.588-5106.719" + cell $xor $xor$ls180.v:5106$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5106$917_Y + connect \Y $xor$ls180.v:5106$918_Y + end + attribute \src "ls180.v:5106.234-5106.318" + cell $xor $xor$ls180.v:5106$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5106$919_Y + end + attribute \src "ls180.v:5106.187-5106.319" + cell $xor $xor$ls180.v:5106$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5106$919_Y + connect \Y $xor$ls180.v:5106$920_Y + end + attribute \src "ls180.v:5107.899-5107.983" + cell $xor $xor$ls180.v:5107$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5107$921_Y + end + attribute \src "ls180.v:5107.634-5107.718" + cell $xor $xor$ls180.v:5107$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5107$922_Y + end + attribute \src "ls180.v:5107.588-5107.719" + cell $xor $xor$ls180.v:5107$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5107$922_Y + connect \Y $xor$ls180.v:5107$923_Y + end + attribute \src "ls180.v:5107.234-5107.318" + cell $xor $xor$ls180.v:5107$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5107$924_Y + end + attribute \src "ls180.v:5107.187-5107.319" + cell $xor $xor$ls180.v:5107$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5107$924_Y + connect \Y $xor$ls180.v:5107$925_Y + end + attribute \src "ls180.v:5116.899-5116.983" + cell $xor $xor$ls180.v:5116$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5116$927_Y + end + attribute \src "ls180.v:5116.634-5116.718" + cell $xor $xor$ls180.v:5116$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5116$928_Y + end + attribute \src "ls180.v:5116.588-5116.719" + cell $xor $xor$ls180.v:5116$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5116$928_Y + connect \Y $xor$ls180.v:5116$929_Y + end + attribute \src "ls180.v:5116.234-5116.318" + cell $xor $xor$ls180.v:5116$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5116$930_Y + end + attribute \src "ls180.v:5116.187-5116.319" + cell $xor $xor$ls180.v:5116$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5116$930_Y + connect \Y $xor$ls180.v:5116$931_Y + end + attribute \src "ls180.v:5117.899-5117.983" + cell $xor $xor$ls180.v:5117$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5117$932_Y + end + attribute \src "ls180.v:5117.634-5117.718" + cell $xor $xor$ls180.v:5117$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5117$933_Y + end + attribute \src "ls180.v:5117.588-5117.719" + cell $xor $xor$ls180.v:5117$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5117$933_Y + connect \Y $xor$ls180.v:5117$934_Y + end + attribute \src "ls180.v:5117.234-5117.318" + cell $xor $xor$ls180.v:5117$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5117$935_Y + end + attribute \src "ls180.v:5117.187-5117.319" + cell $xor $xor$ls180.v:5117$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5117$935_Y + connect \Y $xor$ls180.v:5117$936_Y + end + attribute \src "ls180.v:5268.879-5268.961" + cell $xor $xor$ls180.v:5268$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5268$969_Y + end + attribute \src "ls180.v:5268.620-5268.702" + cell $xor $xor$ls180.v:5268$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5268$970_Y + end + attribute \src "ls180.v:5268.575-5268.703" + cell $xor $xor$ls180.v:5268$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5268$970_Y + connect \Y $xor$ls180.v:5268$971_Y + end + attribute \src "ls180.v:5268.229-5268.311" + cell $xor $xor$ls180.v:5268$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5268$972_Y + end + attribute \src "ls180.v:5268.183-5268.312" + cell $xor $xor$ls180.v:5268$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5268$972_Y + connect \Y $xor$ls180.v:5268$973_Y + end + attribute \src "ls180.v:5269.879-5269.961" + cell $xor $xor$ls180.v:5269$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5269$974_Y + end + attribute \src "ls180.v:5269.620-5269.702" + cell $xor $xor$ls180.v:5269$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5269$975_Y + end + attribute \src "ls180.v:5269.575-5269.703" + cell $xor $xor$ls180.v:5269$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5269$975_Y + connect \Y $xor$ls180.v:5269$976_Y + end + attribute \src "ls180.v:5269.229-5269.311" + cell $xor $xor$ls180.v:5269$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5269$977_Y + end + attribute \src "ls180.v:5269.183-5269.312" + cell $xor $xor$ls180.v:5269$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5269$977_Y + connect \Y $xor$ls180.v:5269$978_Y + end + attribute \src "ls180.v:5278.879-5278.961" + cell $xor $xor$ls180.v:5278$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5278$980_Y + end + attribute \src "ls180.v:5278.620-5278.702" + cell $xor $xor$ls180.v:5278$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5278$981_Y + end + attribute \src "ls180.v:5278.575-5278.703" + cell $xor $xor$ls180.v:5278$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5278$981_Y + connect \Y $xor$ls180.v:5278$982_Y + end + attribute \src "ls180.v:5278.229-5278.311" + cell $xor $xor$ls180.v:5278$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5278$983_Y + end + attribute \src "ls180.v:5278.183-5278.312" + cell $xor $xor$ls180.v:5278$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5278$983_Y + connect \Y $xor$ls180.v:5278$984_Y + end + attribute \src "ls180.v:5279.879-5279.961" + cell $xor $xor$ls180.v:5279$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5279$985_Y + end + attribute \src "ls180.v:5279.620-5279.702" + cell $xor $xor$ls180.v:5279$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5279$986_Y + end + attribute \src "ls180.v:5279.575-5279.703" + cell $xor $xor$ls180.v:5279$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5279$986_Y + connect \Y $xor$ls180.v:5279$987_Y + end + attribute \src "ls180.v:5279.229-5279.311" + cell $xor $xor$ls180.v:5279$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5279$988_Y + end + attribute \src "ls180.v:5279.183-5279.312" + cell $xor $xor$ls180.v:5279$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5279$988_Y + connect \Y $xor$ls180.v:5279$989_Y + end + attribute \src "ls180.v:5288.879-5288.961" + cell $xor $xor$ls180.v:5288$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5288$991_Y + end + attribute \src "ls180.v:5288.620-5288.702" + cell $xor $xor$ls180.v:5288$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5288$992_Y + end + attribute \src "ls180.v:5288.575-5288.703" + cell $xor $xor$ls180.v:5288$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5288$992_Y + connect \Y $xor$ls180.v:5288$993_Y + end + attribute \src "ls180.v:5288.229-5288.311" + cell $xor $xor$ls180.v:5288$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5288$994_Y + end + attribute \src "ls180.v:5288.183-5288.312" + cell $xor $xor$ls180.v:5288$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5288$994_Y + connect \Y $xor$ls180.v:5288$995_Y + end + attribute \src "ls180.v:5289.183-5289.312" + cell $xor $xor$ls180.v:5289$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5289$999_Y + connect \Y $xor$ls180.v:5289$1000_Y + end + attribute \src "ls180.v:5289.879-5289.961" + cell $xor $xor$ls180.v:5289$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5289$996_Y + end + attribute \src "ls180.v:5289.620-5289.702" + cell $xor $xor$ls180.v:5289$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5289$997_Y + end + attribute \src "ls180.v:5289.575-5289.703" + cell $xor $xor$ls180.v:5289$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5289$997_Y + connect \Y $xor$ls180.v:5289$998_Y + end + attribute \src "ls180.v:5289.229-5289.311" + cell $xor $xor$ls180.v:5289$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5289$999_Y + end + attribute \src "ls180.v:5298.879-5298.961" + cell $xor $xor$ls180.v:5298$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5298$1002_Y + end + attribute \src "ls180.v:5298.620-5298.702" + cell $xor $xor$ls180.v:5298$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5298$1003_Y + end + attribute \src "ls180.v:5298.575-5298.703" + cell $xor $xor$ls180.v:5298$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5298$1003_Y + connect \Y $xor$ls180.v:5298$1004_Y + end + attribute \src "ls180.v:5298.229-5298.311" + cell $xor $xor$ls180.v:5298$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5298$1005_Y + end + attribute \src "ls180.v:5298.183-5298.312" + cell $xor $xor$ls180.v:5298$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5298$1005_Y + connect \Y $xor$ls180.v:5298$1006_Y + end + attribute \src "ls180.v:5299.879-5299.961" + cell $xor $xor$ls180.v:5299$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5299$1007_Y + end + attribute \src "ls180.v:5299.620-5299.702" + cell $xor $xor$ls180.v:5299$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5299$1008_Y + end + attribute \src "ls180.v:5299.575-5299.703" + cell $xor $xor$ls180.v:5299$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5299$1008_Y + connect \Y $xor$ls180.v:5299$1009_Y + end + attribute \src "ls180.v:5299.229-5299.311" + cell $xor $xor$ls180.v:5299$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5299$1010_Y + end + attribute \src "ls180.v:5299.183-5299.312" + cell $xor $xor$ls180.v:5299$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5299$1010_Y + connect \Y $xor$ls180.v:5299$1011_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10396.13-10802.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte 1'0 + connect \dbus__cti 1'0 + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \gpio_i [10] + connect \gpio_e10__core__o \gpio_o [10] + connect \gpio_e10__core__oe \gpio_oe [10] + connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e11__core__i \gpio_i [11] + connect \gpio_e11__core__o \gpio_o [11] + connect \gpio_e11__core__oe \gpio_oe [11] + connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e12__core__i \gpio_i [12] + connect \gpio_e12__core__o \gpio_o [12] + connect \gpio_e12__core__oe \gpio_oe [12] + connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e13__core__i \gpio_i [13] + connect \gpio_e13__core__o \gpio_o [13] + connect \gpio_e13__core__oe \gpio_oe [13] + connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e14__core__i \gpio_i [14] + connect \gpio_e14__core__o \gpio_o [14] + connect \gpio_e14__core__oe \gpio_oe [14] + connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e15__core__i \gpio_i [15] + connect \gpio_e15__core__o \gpio_o [15] + connect \gpio_e15__core__oe \gpio_oe [15] + connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e8__core__i \gpio_i [8] + connect \gpio_e8__core__o \gpio_o [8] + connect \gpio_e8__core__oe \gpio_oe [8] + connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e9__core__i \gpio_i [9] + connect \gpio_e9__core__o \gpio_o [9] + connect \gpio_e9__core__oe \gpio_oe [9] + connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_s0__core__i \gpio_i [0] + connect \gpio_s0__core__o \gpio_o [0] + connect \gpio_s0__core__oe \gpio_oe [0] + connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s1__core__i \gpio_i [1] + connect \gpio_s1__core__o \gpio_o [1] + connect \gpio_s1__core__oe \gpio_oe [1] + connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s2__core__i \gpio_i [2] + connect \gpio_s2__core__o \gpio_o [2] + connect \gpio_s2__core__oe \gpio_oe [2] + connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s3__core__i \gpio_i [3] + connect \gpio_s3__core__o \gpio_o [3] + connect \gpio_s3__core__oe \gpio_oe [3] + connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s4__core__i \gpio_i [4] + connect \gpio_s4__core__o \gpio_o [4] + connect \gpio_s4__core__oe \gpio_oe [4] + connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s5__core__i \gpio_i [5] + connect \gpio_s5__core__o \gpio_o [5] + connect \gpio_s5__core__oe \gpio_oe [5] + connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s6__core__i \gpio_i [6] + connect \gpio_s6__core__o \gpio_o [6] + connect \gpio_s6__core__oe \gpio_oe [6] + connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s7__core__i \gpio_i [7] + connect \gpio_s7__core__o \gpio_o [7] + connect \gpio_s7__core__oe \gpio_oe [7] + connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte 1'0 + connect \ibus__cti 1'0 + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \mspi0_clk__core__o \spimaster_clk + connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_cs_n__core__o \spimaster_cs_n + connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_miso__core__i \spimaster_miso + connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_mosi__core__o \spimaster_mosi + connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi1_clk__core__o \spisdcard_clk + connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + connect \mspi1_cs_n__core__o \spisdcard_cs_n + connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + connect \mspi1_miso__core__i \spisdcard_miso + connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + connect \mspi1_mosi__core__o \spisdcard_mosi + connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + connect \mtwi_scl__core__o \i2c_scl + connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_sda__core__i \i2c_sda_i + connect \mtwi_sda__core__o \i2c_sda_o + connect \mtwi_sda__core__oe \i2c_sda_oe + connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \pwm_0__core__o \pwm [0] + connect \pwm_0__pad__o \pwm_1 [0] + connect \pwm_1__core__o \pwm [1] + connect \pwm_1__pad__o \pwm_1 [1] + connect \rst $or$ls180.v:10496$2875_Y + connect \sd0_clk__core__o \sdcard_clk + connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + connect \sd0_cmd__core__i \sdcard_cmd_i + connect \sd0_cmd__core__o \sdcard_cmd_o + connect \sd0_cmd__core__oe \sdcard_cmd_oe + connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_data_i [0] + connect \sd0_data0__core__o \sdcard_data_o [0] + connect \sd0_data0__core__oe \sdcard_data_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [0] + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [0] + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data1__core__i \sdcard_data_i [1] + connect \sd0_data1__core__o \sdcard_data_o [1] + connect \sd0_data1__core__oe \sdcard_data_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [1] + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [1] + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data2__core__i \sdcard_data_i [2] + connect \sd0_data2__core__o \sdcard_data_o [2] + connect \sd0_data2__core__oe \sdcard_data_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [2] + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [2] + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data3__core__i \sdcard_data_i [3] + connect \sd0_data3__core__o \sdcard_data_o [3] + connect \sd0_data3__core__oe \sdcard_data_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [3] + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [3] + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sdr_a_0__core__o \sdram_a [0] + connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_10__core__o \sdram_a [10] + connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_11__core__o \sdram_a [11] + connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_12__core__o \sdram_a [12] + connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_1__core__o \sdram_a [1] + connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_2__core__o \sdram_a [2] + connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_3__core__o \sdram_a [3] + connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_4__core__o \sdram_a [4] + connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_5__core__o \sdram_a [5] + connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_6__core__o \sdram_a [6] + connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_7__core__o \sdram_a [7] + connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_8__core__o \sdram_a [8] + connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_9__core__o \sdram_a [9] + connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_ba_0__core__o \sdram_ba [0] + connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_1__core__o \sdram_ba [1] + connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_cas_n__core__o \sdram_cas_n + connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cke__core__o \sdram_cke + connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \sdram_cs_n + connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_dm_0__core__o \sdram_dm [0] + connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_1__core__o \sdram_dm [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [1] + connect \sdr_dq_0__core__i \sdram_dq_i [0] + connect \sdr_dq_0__core__o \sdram_dq_o [0] + connect \sdr_dq_0__core__oe \sdram_dq_oe + connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__core__i \sdram_dq_i [10] + connect \sdr_dq_10__core__o \sdram_dq_o [10] + connect \sdr_dq_10__core__oe \sdram_dq_oe + connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__core__i \sdram_dq_i [11] + connect \sdr_dq_11__core__o \sdram_dq_o [11] + connect \sdr_dq_11__core__oe \sdram_dq_oe + connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__core__i \sdram_dq_i [12] + connect \sdr_dq_12__core__o \sdram_dq_o [12] + connect \sdr_dq_12__core__oe \sdram_dq_oe + connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__core__i \sdram_dq_i [13] + connect \sdr_dq_13__core__o \sdram_dq_o [13] + connect \sdr_dq_13__core__oe \sdram_dq_oe + connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__core__i \sdram_dq_i [14] + connect \sdr_dq_14__core__o \sdram_dq_o [14] + connect \sdr_dq_14__core__oe \sdram_dq_oe + connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__core__i \sdram_dq_i [15] + connect \sdr_dq_15__core__o \sdram_dq_o [15] + connect \sdr_dq_15__core__oe \sdram_dq_oe + connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__core__i \sdram_dq_i [1] + connect \sdr_dq_1__core__o \sdram_dq_o [1] + connect \sdr_dq_1__core__oe \sdram_dq_oe + connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__core__i \sdram_dq_i [2] + connect \sdr_dq_2__core__o \sdram_dq_o [2] + connect \sdr_dq_2__core__oe \sdram_dq_oe + connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__core__i \sdram_dq_i [3] + connect \sdr_dq_3__core__o \sdram_dq_o [3] + connect \sdr_dq_3__core__oe \sdram_dq_oe + connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__core__i \sdram_dq_i [4] + connect \sdr_dq_4__core__o \sdram_dq_o [4] + connect \sdr_dq_4__core__oe \sdram_dq_oe + connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__core__i \sdram_dq_i [5] + connect \sdr_dq_5__core__o \sdram_dq_o [5] + connect \sdr_dq_5__core__oe \sdram_dq_oe + connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__core__i \sdram_dq_i [6] + connect \sdr_dq_6__core__o \sdram_dq_o [6] + connect \sdr_dq_6__core__oe \sdram_dq_oe + connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__core__i \sdram_dq_i [7] + connect \sdr_dq_7__core__o \sdram_dq_o [7] + connect \sdr_dq_7__core__oe \sdram_dq_oe + connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__core__i \sdram_dq_i [8] + connect \sdr_dq_8__core__o \sdram_dq_o [8] + connect \sdr_dq_8__core__oe \sdram_dq_oe + connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__core__i \sdram_dq_i [9] + connect \sdr_dq_9__core__o \sdram_dq_o [9] + connect \sdr_dq_9__core__oe \sdram_dq_oe + connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_ras_n__core__o \sdram_ras_n + connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_we_n__core__o \sdram_we_n + connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack + connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr + connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc + connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r + connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w + connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err + connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel + connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb + connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we + connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack + connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr + connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc + connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r + connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w + connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err + connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel + connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb + connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we + connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack + connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr + connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc + connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r + connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w + connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err + connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel + connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb + connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we + connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack + connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr + connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc + connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r + connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w + connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err + connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel + connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb + connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3856 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3857 + sync always + sync init + end + attribute \src "ls180.v:100.11-100.56" + process $proc$ls180.v:100$2918 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + end + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$2919 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + end + attribute \src "ls180.v:1013.5-1013.38" + process $proc$ls180.v:1013$3256 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$2920 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + end + attribute \src "ls180.v:1020.11-1020.42" + process $proc$ls180.v:1020$3257 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:1021.5-1021.37" + process $proc$ls180.v:1021$3258 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1022.11-1022.43" + process $proc$ls180.v:1022$3259 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:10224.1-10242.4" + process $proc$ls180.v:10224$2767 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10240$8_ADDR[3:0]$2789 4'xxxx + assign $0$memwr$\mem$ls180.v:10240$8_DATA[63:0]$2790 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10240$8_EN[63:0]$2791 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10238$7_ADDR[3:0]$2786 4'xxxx + assign $0$memwr$\mem$ls180.v:10238$7_DATA[63:0]$2787 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10238$7_EN[63:0]$2788 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10236$6_ADDR[3:0]$2783 4'xxxx + assign $0$memwr$\mem$ls180.v:10236$6_DATA[63:0]$2784 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10236$6_EN[63:0]$2785 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10234$5_ADDR[3:0]$2780 4'xxxx + assign $0$memwr$\mem$ls180.v:10234$5_DATA[63:0]$2781 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10234$5_EN[63:0]$2782 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10232$4_ADDR[3:0]$2777 4'xxxx + assign $0$memwr$\mem$ls180.v:10232$4_DATA[63:0]$2778 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10232$4_EN[63:0]$2779 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10230$3_ADDR[3:0]$2774 4'xxxx + assign $0$memwr$\mem$ls180.v:10230$3_DATA[63:0]$2775 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10230$3_EN[63:0]$2776 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10228$2_ADDR[3:0]$2771 4'xxxx + assign $0$memwr$\mem$ls180.v:10228$2_DATA[63:0]$2772 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10228$2_EN[63:0]$2773 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10226$1_ADDR[3:0]$2768 4'xxxx + assign $0$memwr$\mem$ls180.v:10226$1_DATA[63:0]$2769 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10226$1_EN[63:0]$2770 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[3:0] \main_libresocsim_adr + attribute \src "ls180.v:10225.2-10226.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10225.6-10225.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10226$1_ADDR[3:0]$2768 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10226$1_DATA[63:0]$2769 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10226$1_EN[63:0]$2770 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10227.2-10228.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10227.6-10227.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10228$2_ADDR[3:0]$2771 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10228$2_DATA[63:0]$2772 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10228$2_EN[63:0]$2773 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10229.2-10230.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10229.6-10229.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10230$3_ADDR[3:0]$2774 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10230$3_DATA[63:0]$2775 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10230$3_EN[63:0]$2776 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10231.2-10232.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10231.6-10231.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10232$4_ADDR[3:0]$2777 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10232$4_DATA[63:0]$2778 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10232$4_EN[63:0]$2779 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10233.2-10234.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10233.6-10233.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10234$5_ADDR[3:0]$2780 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10234$5_DATA[63:0]$2781 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10234$5_EN[63:0]$2782 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10235.2-10236.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10235.6-10235.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10236$6_ADDR[3:0]$2783 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10236$6_DATA[63:0]$2784 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10236$6_EN[63:0]$2785 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10237.2-10238.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10237.6-10237.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10238$7_ADDR[3:0]$2786 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10238$7_DATA[63:0]$2787 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10238$7_EN[63:0]$2788 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10239.2-10240.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10239.6-10239.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10240$8_ADDR[3:0]$2789 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10240$8_DATA[63:0]$2790 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10240$8_EN[63:0]$2791 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[3:0] + update $memwr$\mem$ls180.v:10226$1_ADDR $0$memwr$\mem$ls180.v:10226$1_ADDR[3:0]$2768 + update $memwr$\mem$ls180.v:10226$1_DATA $0$memwr$\mem$ls180.v:10226$1_DATA[63:0]$2769 + update $memwr$\mem$ls180.v:10226$1_EN $0$memwr$\mem$ls180.v:10226$1_EN[63:0]$2770 + update $memwr$\mem$ls180.v:10228$2_ADDR $0$memwr$\mem$ls180.v:10228$2_ADDR[3:0]$2771 + update $memwr$\mem$ls180.v:10228$2_DATA $0$memwr$\mem$ls180.v:10228$2_DATA[63:0]$2772 + update $memwr$\mem$ls180.v:10228$2_EN $0$memwr$\mem$ls180.v:10228$2_EN[63:0]$2773 + update $memwr$\mem$ls180.v:10230$3_ADDR $0$memwr$\mem$ls180.v:10230$3_ADDR[3:0]$2774 + update $memwr$\mem$ls180.v:10230$3_DATA $0$memwr$\mem$ls180.v:10230$3_DATA[63:0]$2775 + update $memwr$\mem$ls180.v:10230$3_EN $0$memwr$\mem$ls180.v:10230$3_EN[63:0]$2776 + update $memwr$\mem$ls180.v:10232$4_ADDR $0$memwr$\mem$ls180.v:10232$4_ADDR[3:0]$2777 + update $memwr$\mem$ls180.v:10232$4_DATA $0$memwr$\mem$ls180.v:10232$4_DATA[63:0]$2778 + update $memwr$\mem$ls180.v:10232$4_EN $0$memwr$\mem$ls180.v:10232$4_EN[63:0]$2779 + update $memwr$\mem$ls180.v:10234$5_ADDR $0$memwr$\mem$ls180.v:10234$5_ADDR[3:0]$2780 + update $memwr$\mem$ls180.v:10234$5_DATA $0$memwr$\mem$ls180.v:10234$5_DATA[63:0]$2781 + update $memwr$\mem$ls180.v:10234$5_EN $0$memwr$\mem$ls180.v:10234$5_EN[63:0]$2782 + update $memwr$\mem$ls180.v:10236$6_ADDR $0$memwr$\mem$ls180.v:10236$6_ADDR[3:0]$2783 + update $memwr$\mem$ls180.v:10236$6_DATA $0$memwr$\mem$ls180.v:10236$6_DATA[63:0]$2784 + update $memwr$\mem$ls180.v:10236$6_EN $0$memwr$\mem$ls180.v:10236$6_EN[63:0]$2785 + update $memwr$\mem$ls180.v:10238$7_ADDR $0$memwr$\mem$ls180.v:10238$7_ADDR[3:0]$2786 + update $memwr$\mem$ls180.v:10238$7_DATA $0$memwr$\mem$ls180.v:10238$7_DATA[63:0]$2787 + update $memwr$\mem$ls180.v:10238$7_EN $0$memwr$\mem$ls180.v:10238$7_EN[63:0]$2788 + update $memwr$\mem$ls180.v:10240$8_ADDR $0$memwr$\mem$ls180.v:10240$8_ADDR[3:0]$2789 + update $memwr$\mem$ls180.v:10240$8_DATA $0$memwr$\mem$ls180.v:10240$8_DATA[63:0]$2790 + update $memwr$\mem$ls180.v:10240$8_EN $0$memwr$\mem$ls180.v:10240$8_EN[63:0]$2791 + end + attribute \src "ls180.v:1023.11-1023.43" + process $proc$ls180.v:1023$3260 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:1024.11-1024.46" + process $proc$ls180.v:1024$3261 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:10252.1-10270.4" + process $proc$ls180.v:10252$2793 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:10268$16_ADDR[3:0]$2815 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10268$16_DATA[63:0]$2816 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10268$16_EN[63:0]$2817 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10266$15_ADDR[3:0]$2812 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10266$15_DATA[63:0]$2813 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10266$15_EN[63:0]$2814 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10264$14_ADDR[3:0]$2809 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10264$14_DATA[63:0]$2810 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10264$14_EN[63:0]$2811 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10262$13_ADDR[3:0]$2806 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10262$13_DATA[63:0]$2807 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10262$13_EN[63:0]$2808 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10260$12_ADDR[3:0]$2803 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10260$12_DATA[63:0]$2804 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10260$12_EN[63:0]$2805 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10258$11_ADDR[3:0]$2800 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10258$11_DATA[63:0]$2801 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10258$11_EN[63:0]$2802 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10256$10_ADDR[3:0]$2797 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10256$10_DATA[63:0]$2798 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10256$10_EN[63:0]$2799 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10254$9_ADDR[3:0]$2794 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10254$9_DATA[63:0]$2795 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10254$9_EN[63:0]$2796 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[3:0] \main_ram_adr + attribute \src "ls180.v:10253.2-10254.51" + switch \main_ram_we [0] + attribute \src "ls180.v:10253.6-10253.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10254$9_ADDR[3:0]$2794 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10254$9_DATA[63:0]$2795 { 56'00000000000000000000000000000000000000000000000000000000 \main_ram_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10254$9_EN[63:0]$2796 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10255.2-10256.53" + switch \main_ram_we [1] + attribute \src "ls180.v:10255.6-10255.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10256$10_ADDR[3:0]$2797 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10256$10_DATA[63:0]$2798 { 48'000000000000000000000000000000000000000000000000 \main_ram_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10256$10_EN[63:0]$2799 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10257.2-10258.55" + switch \main_ram_we [2] + attribute \src "ls180.v:10257.6-10257.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10258$11_ADDR[3:0]$2800 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10258$11_DATA[63:0]$2801 { 40'0000000000000000000000000000000000000000 \main_ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10258$11_EN[63:0]$2802 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10259.2-10260.55" + switch \main_ram_we [3] + attribute \src "ls180.v:10259.6-10259.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10260$12_ADDR[3:0]$2803 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10260$12_DATA[63:0]$2804 { 32'00000000000000000000000000000000 \main_ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10260$12_EN[63:0]$2805 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10261.2-10262.55" + switch \main_ram_we [4] + attribute \src "ls180.v:10261.6-10261.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10262$13_ADDR[3:0]$2806 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10262$13_DATA[63:0]$2807 { 24'000000000000000000000000 \main_ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10262$13_EN[63:0]$2808 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10263.2-10264.55" + switch \main_ram_we [5] + attribute \src "ls180.v:10263.6-10263.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10264$14_ADDR[3:0]$2809 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10264$14_DATA[63:0]$2810 { 16'0000000000000000 \main_ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10264$14_EN[63:0]$2811 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10265.2-10266.55" + switch \main_ram_we [6] + attribute \src "ls180.v:10265.6-10265.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10266$15_ADDR[3:0]$2812 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10266$15_DATA[63:0]$2813 { 8'00000000 \main_ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10266$15_EN[63:0]$2814 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10267.2-10268.55" + switch \main_ram_we [7] + attribute \src "ls180.v:10267.6-10267.20" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10268$16_ADDR[3:0]$2815 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10268$16_DATA[63:0]$2816 { \main_ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10268$16_EN[63:0]$2817 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_1 $0\memadr_1[3:0] + update $memwr$\mem_1$ls180.v:10254$9_ADDR $0$memwr$\mem_1$ls180.v:10254$9_ADDR[3:0]$2794 + update $memwr$\mem_1$ls180.v:10254$9_DATA $0$memwr$\mem_1$ls180.v:10254$9_DATA[63:0]$2795 + update $memwr$\mem_1$ls180.v:10254$9_EN $0$memwr$\mem_1$ls180.v:10254$9_EN[63:0]$2796 + update $memwr$\mem_1$ls180.v:10256$10_ADDR $0$memwr$\mem_1$ls180.v:10256$10_ADDR[3:0]$2797 + update $memwr$\mem_1$ls180.v:10256$10_DATA $0$memwr$\mem_1$ls180.v:10256$10_DATA[63:0]$2798 + update $memwr$\mem_1$ls180.v:10256$10_EN $0$memwr$\mem_1$ls180.v:10256$10_EN[63:0]$2799 + update $memwr$\mem_1$ls180.v:10258$11_ADDR $0$memwr$\mem_1$ls180.v:10258$11_ADDR[3:0]$2800 + update $memwr$\mem_1$ls180.v:10258$11_DATA $0$memwr$\mem_1$ls180.v:10258$11_DATA[63:0]$2801 + update $memwr$\mem_1$ls180.v:10258$11_EN $0$memwr$\mem_1$ls180.v:10258$11_EN[63:0]$2802 + update $memwr$\mem_1$ls180.v:10260$12_ADDR $0$memwr$\mem_1$ls180.v:10260$12_ADDR[3:0]$2803 + update $memwr$\mem_1$ls180.v:10260$12_DATA $0$memwr$\mem_1$ls180.v:10260$12_DATA[63:0]$2804 + update $memwr$\mem_1$ls180.v:10260$12_EN $0$memwr$\mem_1$ls180.v:10260$12_EN[63:0]$2805 + update $memwr$\mem_1$ls180.v:10262$13_ADDR $0$memwr$\mem_1$ls180.v:10262$13_ADDR[3:0]$2806 + update $memwr$\mem_1$ls180.v:10262$13_DATA $0$memwr$\mem_1$ls180.v:10262$13_DATA[63:0]$2807 + update $memwr$\mem_1$ls180.v:10262$13_EN $0$memwr$\mem_1$ls180.v:10262$13_EN[63:0]$2808 + update $memwr$\mem_1$ls180.v:10264$14_ADDR $0$memwr$\mem_1$ls180.v:10264$14_ADDR[3:0]$2809 + update $memwr$\mem_1$ls180.v:10264$14_DATA $0$memwr$\mem_1$ls180.v:10264$14_DATA[63:0]$2810 + update $memwr$\mem_1$ls180.v:10264$14_EN $0$memwr$\mem_1$ls180.v:10264$14_EN[63:0]$2811 + update $memwr$\mem_1$ls180.v:10266$15_ADDR $0$memwr$\mem_1$ls180.v:10266$15_ADDR[3:0]$2812 + update $memwr$\mem_1$ls180.v:10266$15_DATA $0$memwr$\mem_1$ls180.v:10266$15_DATA[63:0]$2813 + update $memwr$\mem_1$ls180.v:10266$15_EN $0$memwr$\mem_1$ls180.v:10266$15_EN[63:0]$2814 + update $memwr$\mem_1$ls180.v:10268$16_ADDR $0$memwr$\mem_1$ls180.v:10268$16_ADDR[3:0]$2815 + update $memwr$\mem_1$ls180.v:10268$16_DATA $0$memwr$\mem_1$ls180.v:10268$16_DATA[63:0]$2816 + update $memwr$\mem_1$ls180.v:10268$16_EN $0$memwr$\mem_1$ls180.v:10268$16_EN[63:0]$2817 + end + attribute \src "ls180.v:10280.1-10284.4" + process $proc$ls180.v:10280$2819 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10282$17_ADDR[2:0]$2820 3'xxx + assign $0$memwr$\storage$ls180.v:10282$17_DATA[24:0]$2821 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10282$17_EN[24:0]$2822 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10283$2823_DATA + attribute \src "ls180.v:10281.2-10282.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10281.6-10281.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10282$17_ADDR[2:0]$2820 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10282$17_DATA[24:0]$2821 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10282$17_EN[24:0]$2822 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10282$17_ADDR $0$memwr$\storage$ls180.v:10282$17_ADDR[2:0]$2820 + update $memwr$\storage$ls180.v:10282$17_DATA $0$memwr$\storage$ls180.v:10282$17_DATA[24:0]$2821 + update $memwr$\storage$ls180.v:10282$17_EN $0$memwr$\storage$ls180.v:10282$17_EN[24:0]$2822 + end + attribute \src "ls180.v:10286.1-10287.4" + process $proc$ls180.v:10286$2824 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10294.1-10298.4" + process $proc$ls180.v:10294$2826 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10296$18_ADDR[2:0]$2827 3'xxx + assign $0$memwr$\storage_1$ls180.v:10296$18_DATA[24:0]$2828 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10296$18_EN[24:0]$2829 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10297$2830_DATA + attribute \src "ls180.v:10295.2-10296.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10295.6-10295.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10296$18_ADDR[2:0]$2827 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10296$18_DATA[24:0]$2828 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10296$18_EN[24:0]$2829 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10296$18_ADDR $0$memwr$\storage_1$ls180.v:10296$18_ADDR[2:0]$2827 + update $memwr$\storage_1$ls180.v:10296$18_DATA $0$memwr$\storage_1$ls180.v:10296$18_DATA[24:0]$2828 + update $memwr$\storage_1$ls180.v:10296$18_EN $0$memwr$\storage_1$ls180.v:10296$18_EN[24:0]$2829 + end + attribute \src "ls180.v:10300.1-10301.4" + process $proc$ls180.v:10300$2831 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10308.1-10312.4" + process $proc$ls180.v:10308$2833 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10310$19_ADDR[2:0]$2834 3'xxx + assign $0$memwr$\storage_2$ls180.v:10310$19_DATA[24:0]$2835 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10310$19_EN[24:0]$2836 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10311$2837_DATA + attribute \src "ls180.v:10309.2-10310.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10309.6-10309.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10310$19_ADDR[2:0]$2834 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10310$19_DATA[24:0]$2835 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10310$19_EN[24:0]$2836 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10310$19_ADDR $0$memwr$\storage_2$ls180.v:10310$19_ADDR[2:0]$2834 + update $memwr$\storage_2$ls180.v:10310$19_DATA $0$memwr$\storage_2$ls180.v:10310$19_DATA[24:0]$2835 + update $memwr$\storage_2$ls180.v:10310$19_EN $0$memwr$\storage_2$ls180.v:10310$19_EN[24:0]$2836 + end + attribute \src "ls180.v:10314.1-10315.4" + process $proc$ls180.v:10314$2838 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10322.1-10326.4" + process $proc$ls180.v:10322$2840 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10324$20_ADDR[2:0]$2841 3'xxx + assign $0$memwr$\storage_3$ls180.v:10324$20_DATA[24:0]$2842 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10324$20_EN[24:0]$2843 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10325$2844_DATA + attribute \src "ls180.v:10323.2-10324.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10323.6-10323.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10324$20_ADDR[2:0]$2841 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10324$20_DATA[24:0]$2842 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10324$20_EN[24:0]$2843 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10324$20_ADDR $0$memwr$\storage_3$ls180.v:10324$20_ADDR[2:0]$2841 + update $memwr$\storage_3$ls180.v:10324$20_DATA $0$memwr$\storage_3$ls180.v:10324$20_DATA[24:0]$2842 + update $memwr$\storage_3$ls180.v:10324$20_EN $0$memwr$\storage_3$ls180.v:10324$20_EN[24:0]$2843 + end + attribute \src "ls180.v:10328.1-10329.4" + process $proc$ls180.v:10328$2845 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10337.1-10341.4" + process $proc$ls180.v:10337$2847 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10339$21_ADDR[3:0]$2848 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10339$21_DATA[9:0]$2849 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10339$21_EN[9:0]$2850 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10340$2851_DATA + attribute \src "ls180.v:10338.2-10339.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10338.6-10338.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10339$21_ADDR[3:0]$2848 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10339$21_DATA[9:0]$2849 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10339$21_EN[9:0]$2850 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10339$21_ADDR $0$memwr$\storage_4$ls180.v:10339$21_ADDR[3:0]$2848 + update $memwr$\storage_4$ls180.v:10339$21_DATA $0$memwr$\storage_4$ls180.v:10339$21_DATA[9:0]$2849 + update $memwr$\storage_4$ls180.v:10339$21_EN $0$memwr$\storage_4$ls180.v:10339$21_EN[9:0]$2850 + end + attribute \src "ls180.v:10343.1-10346.4" + process $proc$ls180.v:10343$2852 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10344.2-10345.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10344.6-10344.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10345$2853_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:10354.1-10358.4" + process $proc$ls180.v:10354$2854 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10356$22_ADDR[3:0]$2855 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10356$22_DATA[9:0]$2856 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10356$22_EN[9:0]$2857 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10357$2858_DATA + attribute \src "ls180.v:10355.2-10356.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10355.6-10355.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10356$22_ADDR[3:0]$2855 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10356$22_DATA[9:0]$2856 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10356$22_EN[9:0]$2857 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10356$22_ADDR $0$memwr$\storage_5$ls180.v:10356$22_ADDR[3:0]$2855 + update $memwr$\storage_5$ls180.v:10356$22_DATA $0$memwr$\storage_5$ls180.v:10356$22_DATA[9:0]$2856 + update $memwr$\storage_5$ls180.v:10356$22_EN $0$memwr$\storage_5$ls180.v:10356$22_EN[9:0]$2857 + end + attribute \src "ls180.v:10360.1-10363.4" + process $proc$ls180.v:10360$2859 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10361.2-10362.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10361.6-10361.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10362$2860_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:10370.1-10374.4" + process $proc$ls180.v:10370$2861 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10372$23_ADDR[4:0]$2862 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10372$23_DATA[9:0]$2863 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10372$23_EN[9:0]$2864 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10373$2865_DATA + attribute \src "ls180.v:10371.2-10372.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10371.6-10371.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10372$23_ADDR[4:0]$2862 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10372$23_DATA[9:0]$2863 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10372$23_EN[9:0]$2864 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10372$23_ADDR $0$memwr$\storage_6$ls180.v:10372$23_ADDR[4:0]$2862 + update $memwr$\storage_6$ls180.v:10372$23_DATA $0$memwr$\storage_6$ls180.v:10372$23_DATA[9:0]$2863 + update $memwr$\storage_6$ls180.v:10372$23_EN $0$memwr$\storage_6$ls180.v:10372$23_EN[9:0]$2864 + end + attribute \src "ls180.v:10376.1-10377.4" + process $proc$ls180.v:10376$2866 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10384.1-10388.4" + process $proc$ls180.v:10384$2868 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10386$24_ADDR[4:0]$2869 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10386$24_DATA[9:0]$2870 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10386$24_EN[9:0]$2871 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10387$2872_DATA + attribute \src "ls180.v:10385.2-10386.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10385.6-10385.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10386$24_ADDR[4:0]$2869 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10386$24_DATA[9:0]$2870 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10386$24_EN[9:0]$2871 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10386$24_ADDR $0$memwr$\storage_7$ls180.v:10386$24_ADDR[4:0]$2869 + update $memwr$\storage_7$ls180.v:10386$24_DATA $0$memwr$\storage_7$ls180.v:10386$24_DATA[9:0]$2870 + update $memwr$\storage_7$ls180.v:10386$24_EN $0$memwr$\storage_7$ls180.v:10386$24_EN[9:0]$2871 + end + attribute \src "ls180.v:1039.5-1039.27" + process $proc$ls180.v:1039$3262 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:10390.1-10391.4" + process $proc$ls180.v:10390$2873 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$2921 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] + end + attribute \src "ls180.v:1040.12-1040.53" + process $proc$ls180.v:1040$3263 + assign { } { } + assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] + sync init + end + attribute \src "ls180.v:1041.12-1041.49" + process $proc$ls180.v:1041$3264 + assign { } { } + assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:1042.12-1042.54" + process $proc$ls180.v:1042$3265 + assign { } { } + assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] + sync init + end + attribute \src "ls180.v:1046.12-1046.53" + process $proc$ls180.v:1046$3266 + assign { } { } + assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] + end + attribute \src "ls180.v:1047.5-1047.40" + process $proc$ls180.v:1047$3267 + assign { } { } + assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] + end + attribute \src "ls180.v:1048.12-1048.49" + process $proc$ls180.v:1048$3268 + assign { } { } + assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:1050.12-1050.54" + process $proc$ls180.v:1050$3269 + assign { } { } + assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] + end + attribute \src "ls180.v:1051.5-1051.41" + process $proc$ls180.v:1051$3270 + assign { } { } + assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] + end + attribute \src "ls180.v:1057.5-1057.32" + process $proc$ls180.v:1057$3271 + assign { } { } + assign $1\main_spimaster2_done[0:0] 1'0 + sync always + sync init + update \main_spimaster2_done $1\main_spimaster2_done[0:0] + end + attribute \src "ls180.v:1058.5-1058.31" + process $proc$ls180.v:1058$3272 + assign { } { } + assign $1\main_spimaster3_irq[0:0] 1'0 + sync always + sync init + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] + end + attribute \src "ls180.v:1060.11-1060.38" + process $proc$ls180.v:1060$3273 + assign { } { } + assign $1\main_spimaster5_miso[7:0] 8'00000000 + sync always + sync init + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] + end + attribute \src "ls180.v:1063.12-1063.47" + process $proc$ls180.v:1063$3274 + assign { } { } + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] + sync init + end + attribute \src "ls180.v:1064.5-1064.33" + process $proc$ls180.v:1064$3275 + assign { } { } + assign $1\main_spimaster9_start[0:0] 1'0 + sync always + sync init + update \main_spimaster9_start $1\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:1066.12-1066.44" + process $proc$ls180.v:1066$3276 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + end + attribute \src "ls180.v:1067.5-1067.31" + process $proc$ls180.v:1067$3277 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] + end + attribute \src "ls180.v:1071.11-1071.42" + process $proc$ls180.v:1071$3278 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:1072.5-1072.31" + process $proc$ls180.v:1072$3279 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:1076.5-1076.36" + process $proc$ls180.v:1076$3280 + assign { } { } + assign $1\main_spimaster21_storage[0:0] 1'1 + sync always + sync init + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + end + attribute \src "ls180.v:1077.5-1077.31" + process $proc$ls180.v:1077$3281 + assign { } { } + assign $1\main_spimaster22_re[0:0] 1'0 + sync always + sync init + update \main_spimaster22_re $1\main_spimaster22_re[0:0] + end + attribute \src "ls180.v:1078.5-1078.36" + process $proc$ls180.v:1078$3282 + assign { } { } + assign $1\main_spimaster23_storage[0:0] 1'0 + sync always + sync init + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] + end + attribute \src "ls180.v:1079.5-1079.31" + process $proc$ls180.v:1079$3283 + assign { } { } + assign $1\main_spimaster24_re[0:0] 1'0 + sync always + sync init + update \main_spimaster24_re $1\main_spimaster24_re[0:0] + end + attribute \src "ls180.v:1080.5-1080.39" + process $proc$ls180.v:1080$3284 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:1081.5-1081.38" + process $proc$ls180.v:1081$3285 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:1082.11-1082.40" + process $proc$ls180.v:1082$3286 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:1083.5-1083.39" + process $proc$ls180.v:1083$3287 + assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:1084.5-1084.39" + process $proc$ls180.v:1084$3288 + assign { } { } + assign $1\main_spimaster29_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] + end + attribute \src "ls180.v:1085.12-1085.48" + process $proc$ls180.v:1085$3289 + assign { } { } + assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] + end + attribute \src "ls180.v:1088.11-1088.44" + process $proc$ls180.v:1088$3290 + assign { } { } + assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] + end + attribute \src "ls180.v:1089.11-1089.43" + process $proc$ls180.v:1089$3291 + assign { } { } + assign $1\main_spimaster34_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] + end + attribute \src "ls180.v:1090.11-1090.44" + process $proc$ls180.v:1090$3292 + assign { } { } + assign $1\main_spimaster35_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] + end + attribute \src "ls180.v:1093.5-1093.32" + process $proc$ls180.v:1093$3293 + assign { } { } + assign $1\main_spisdcard_done0[0:0] 1'0 + sync always + sync init + update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] + end + attribute \src "ls180.v:1094.5-1094.30" + process $proc$ls180.v:1094$3294 + assign { } { } + assign $1\main_spisdcard_irq[0:0] 1'0 + sync always + sync init + update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] + end + attribute \src "ls180.v:1096.11-1096.37" + process $proc$ls180.v:1096$3295 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:1100.5-1100.33" + process $proc$ls180.v:1100$3296 + assign { } { } + assign $1\main_spisdcard_start1[0:0] 1'0 + sync always + sync init + update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:1102.12-1102.50" + process $proc$ls180.v:1102$3297 + assign { } { } + assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] + end + attribute \src "ls180.v:1103.5-1103.37" + process $proc$ls180.v:1103$3298 + assign { } { } + assign $1\main_spisdcard_control_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] + end + attribute \src "ls180.v:1107.11-1107.45" + process $proc$ls180.v:1107$3299 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:1108.5-1108.34" + process $proc$ls180.v:1108$3300 + assign { } { } + assign $1\main_spisdcard_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] + end + attribute \src "ls180.v:1112.5-1112.37" + process $proc$ls180.v:1112$3301 + assign { } { } + assign $1\main_spisdcard_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] + end + attribute \src "ls180.v:1113.5-1113.32" + process $proc$ls180.v:1113$3302 + assign { } { } + assign $1\main_spisdcard_cs_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] + end + attribute \src "ls180.v:1114.5-1114.43" + process $proc$ls180.v:1114$3303 + assign { } { } + assign $1\main_spisdcard_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] + end + attribute \src "ls180.v:1115.5-1115.38" + process $proc$ls180.v:1115$3304 + assign { } { } + assign $1\main_spisdcard_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] + end + attribute \src "ls180.v:1116.5-1116.37" + process $proc$ls180.v:1116$3305 + assign { } { } + assign $1\main_spisdcard_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] + end + attribute \src "ls180.v:1117.5-1117.36" + process $proc$ls180.v:1117$3306 + assign { } { } + assign $1\main_spisdcard_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] + end + attribute \src "ls180.v:1118.11-1118.38" + process $proc$ls180.v:1118$3307 + assign { } { } + assign $1\main_spisdcard_count[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count $1\main_spisdcard_count[2:0] + end + attribute \src "ls180.v:1119.5-1119.37" + process $proc$ls180.v:1119$3308 + assign { } { } + assign $1\main_spisdcard_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] + end + attribute \src "ls180.v:1120.5-1120.37" + process $proc$ls180.v:1120$3309 + assign { } { } + assign $1\main_spisdcard_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] + end + attribute \src "ls180.v:1121.12-1121.47" + process $proc$ls180.v:1121$3310 + assign { } { } + assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] + end + attribute \src "ls180.v:1124.11-1124.42" + process $proc$ls180.v:1124$3311 + assign { } { } + assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] + end + attribute \src "ls180.v:1125.11-1125.41" + process $proc$ls180.v:1125$3312 + assign { } { } + assign $1\main_spisdcard_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] + end + attribute \src "ls180.v:1126.11-1126.42" + process $proc$ls180.v:1126$3313 + assign { } { } + assign $1\main_spisdcard_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] + end + attribute \src "ls180.v:1127.12-1127.45" + process $proc$ls180.v:1127$3314 + assign { } { } + assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 + sync always + sync init + update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] + end + attribute \src "ls180.v:1128.5-1128.30" + process $proc$ls180.v:1128$3315 + assign { } { } + assign $1\main_spimaster1_re[0:0] 1'0 + sync always + sync init + update \main_spimaster1_re $1\main_spimaster1_re[0:0] + end + attribute \src "ls180.v:1130.12-1130.30" + process $proc$ls180.v:1130$3316 + assign { } { } + assign $1\main_dummy[23:0] 24'000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[23:0] + end + attribute \src "ls180.v:1134.12-1134.37" + process $proc$ls180.v:1134$3317 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:1135.5-1135.36" + process $proc$ls180.v:1135$3318 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:1136.5-1136.31" + process $proc$ls180.v:1136$3319 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:1137.12-1137.43" + process $proc$ls180.v:1137$3320 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:1138.5-1138.30" + process $proc$ls180.v:1138$3321 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:1139.12-1139.44" + process $proc$ls180.v:1139$3322 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$2922 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + sync init + end + attribute \src "ls180.v:1140.5-1140.31" + process $proc$ls180.v:1140$3323 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:1144.12-1144.37" + process $proc$ls180.v:1144$3324 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1145.5-1145.36" + process $proc$ls180.v:1145$3325 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1146.5-1146.31" + process $proc$ls180.v:1146$3326 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1147.12-1147.43" + process $proc$ls180.v:1147$3327 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1148.5-1148.30" + process $proc$ls180.v:1148$3328 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1149.12-1149.44" + process $proc$ls180.v:1149$3329 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$2923 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1150.5-1150.31" + process $proc$ls180.v:1150$3330 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1154.11-1154.34" + process $proc$ls180.v:1154$3331 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1155.5-1155.23" + process $proc$ls180.v:1155$3332 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1161.11-1161.46" + process $proc$ls180.v:1161$3333 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1162.5-1162.33" + process $proc$ls180.v:1162$3334 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1164.5-1164.35" + process $proc$ls180.v:1164$3335 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1166.11-1166.41" + process $proc$ls180.v:1166$3336 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1167.5-1167.35" + process $proc$ls180.v:1167$3337 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1168.5-1168.36" + process $proc$ls180.v:1168$3338 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1172.5-1172.40" + process $proc$ls180.v:1172$3339 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1177.5-1177.48" + process $proc$ls180.v:1177$3340 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1178.5-1178.50" + process $proc$ls180.v:1178$3341 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1179.5-1179.51" + process $proc$ls180.v:1179$3342 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1180.11-1180.57" + process $proc$ls180.v:1180$3343 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1181.5-1181.52" + process $proc$ls180.v:1181$3344 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1182.11-1182.39" + process $proc$ls180.v:1182$3345 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1187.5-1187.48" + process $proc$ls180.v:1187$3346 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1188.5-1188.50" + process $proc$ls180.v:1188$3347 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1189.5-1189.51" + process $proc$ls180.v:1189$3348 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1190.11-1190.57" + process $proc$ls180.v:1190$3349 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1191.5-1191.52" + process $proc$ls180.v:1191$3350 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1192.5-1192.38" + process $proc$ls180.v:1192$3351 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1193.5-1193.38" + process $proc$ls180.v:1193$3352 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1194.5-1194.37" + process $proc$ls180.v:1194$3353 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1195.11-1195.51" + process $proc$ls180.v:1195$3354 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1196.5-1196.32" + process $proc$ls180.v:1196$3355 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1197.11-1197.39" + process $proc$ls180.v:1197$3356 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1200.5-1200.49" + process $proc$ls180.v:1200$3357 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1201.5-1201.48" + process $proc$ls180.v:1201$3358 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1202.5-1202.55" + process $proc$ls180.v:1202$3359 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1204.5-1204.57" + process $proc$ls180.v:1204$3360 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1205.5-1205.58" + process $proc$ls180.v:1205$3361 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1207.11-1207.64" + process $proc$ls180.v:1207$3362 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1208.5-1208.59" + process $proc$ls180.v:1208$3363 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1210.5-1210.48" + process $proc$ls180.v:1210$3364 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1211.5-1211.50" + process $proc$ls180.v:1211$3365 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1212.5-1212.51" + process $proc$ls180.v:1212$3366 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1213.11-1213.57" + process $proc$ls180.v:1213$3367 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1214.5-1214.52" + process $proc$ls180.v:1214$3368 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1215.5-1215.38" + process $proc$ls180.v:1215$3369 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1216.5-1216.38" + process $proc$ls180.v:1216$3370 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1217.5-1217.37" + process $proc$ls180.v:1217$3371 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1218.11-1218.53" + process $proc$ls180.v:1218$3372 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1219.5-1219.40" + process $proc$ls180.v:1219$3373 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1220.5-1220.40" + process $proc$ls180.v:1220$3374 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1221.5-1221.39" + process $proc$ls180.v:1221$3375 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1222.11-1222.53" + process $proc$ls180.v:1222$3376 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1223.11-1223.55" + process $proc$ls180.v:1223$3377 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1224.12-1224.48" + process $proc$ls180.v:1224$3378 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1225.11-1225.39" + process $proc$ls180.v:1225$3379 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1227.5-1227.46" + process $proc$ls180.v:1227$3380 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1238.5-1238.53" + process $proc$ls180.v:1238$3381 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1243.5-1243.36" + process $proc$ls180.v:1243$3382 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1246.5-1246.53" + process $proc$ls180.v:1246$3383 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1247.5-1247.52" + process $proc$ls180.v:1247$3384 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1251.5-1251.55" + process $proc$ls180.v:1251$3385 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1252.5-1252.54" + process $proc$ls180.v:1252$3386 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1253.11-1253.68" + process $proc$ls180.v:1253$3387 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1254.11-1254.81" + process $proc$ls180.v:1254$3388 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1255.11-1255.54" + process $proc$ls180.v:1255$3389 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1257.5-1257.53" + process $proc$ls180.v:1257$3390 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1268.5-1268.49" + process $proc$ls180.v:1268$3391 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1270.5-1270.49" + process $proc$ls180.v:1270$3392 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1271.5-1271.48" + process $proc$ls180.v:1271$3393 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1272.11-1272.62" + process $proc$ls180.v:1272$3394 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1273.5-1273.38" + process $proc$ls180.v:1273$3395 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1278.5-1278.49" + process $proc$ls180.v:1278$3396 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1279.5-1279.51" + process $proc$ls180.v:1279$3397 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1280.5-1280.52" + process $proc$ls180.v:1280$3398 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1281.11-1281.58" + process $proc$ls180.v:1281$3399 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1282.5-1282.53" + process $proc$ls180.v:1282$3400 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1283.5-1283.39" + process $proc$ls180.v:1283$3401 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1284.5-1284.39" + process $proc$ls180.v:1284$3402 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1285.5-1285.39" + process $proc$ls180.v:1285$3403 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1286.5-1286.38" + process $proc$ls180.v:1286$3404 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1287.11-1287.52" + process $proc$ls180.v:1287$3405 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1288.5-1288.33" + process $proc$ls180.v:1288$3406 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1289.11-1289.40" + process $proc$ls180.v:1289$3407 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1290.5-1290.50" + process $proc$ls180.v:1290$3408 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1292.5-1292.50" + process $proc$ls180.v:1292$3409 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1293.5-1293.49" + process $proc$ls180.v:1293$3410 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1294.5-1294.56" + process $proc$ls180.v:1294$3411 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1295.5-1295.58" + process $proc$ls180.v:1295$3412 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1296.5-1296.58" + process $proc$ls180.v:1296$3413 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1297.5-1297.59" + process $proc$ls180.v:1297$3414 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1298.11-1298.65" + process $proc$ls180.v:1298$3415 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1299.11-1299.65" + process $proc$ls180.v:1299$3416 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1300.5-1300.60" + process $proc$ls180.v:1300$3417 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1301.5-1301.34" + process $proc$ls180.v:1301$3418 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1302.5-1302.34" + process $proc$ls180.v:1302$3419 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1303.5-1303.34" + process $proc$ls180.v:1303$3420 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1305.5-1305.47" + process $proc$ls180.v:1305$3421 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1316.5-1316.54" + process $proc$ls180.v:1316$3422 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1321.5-1321.37" + process $proc$ls180.v:1321$3423 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1324.5-1324.54" + process $proc$ls180.v:1324$3424 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1325.5-1325.53" + process $proc$ls180.v:1325$3425 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1329.5-1329.56" + process $proc$ls180.v:1329$3426 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1330.5-1330.55" + process $proc$ls180.v:1330$3427 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1331.11-1331.69" + process $proc$ls180.v:1331$3428 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1332.11-1332.82" + process $proc$ls180.v:1332$3429 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1333.11-1333.55" + process $proc$ls180.v:1333$3430 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1335.5-1335.54" + process $proc$ls180.v:1335$3431 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1346.5-1346.50" + process $proc$ls180.v:1346$3432 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1348.5-1348.50" + process $proc$ls180.v:1348$3433 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1349.5-1349.49" + process $proc$ls180.v:1349$3434 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1350.11-1350.63" + process $proc$ls180.v:1350$3435 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1351.5-1351.39" + process $proc$ls180.v:1351$3436 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1354.5-1354.50" + process $proc$ls180.v:1354$3437 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1355.5-1355.49" + process $proc$ls180.v:1355$3438 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1356.5-1356.56" + process $proc$ls180.v:1356$3439 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1358.5-1358.58" + process $proc$ls180.v:1358$3440 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1359.5-1359.59" + process $proc$ls180.v:1359$3441 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1361.11-1361.65" + process $proc$ls180.v:1361$3442 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1362.5-1362.60" + process $proc$ls180.v:1362$3443 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1364.5-1364.49" + process $proc$ls180.v:1364$3444 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1365.5-1365.51" + process $proc$ls180.v:1365$3445 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1366.5-1366.52" + process $proc$ls180.v:1366$3446 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1367.11-1367.58" + process $proc$ls180.v:1367$3447 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1368.5-1368.53" + process $proc$ls180.v:1368$3448 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1369.5-1369.39" + process $proc$ls180.v:1369$3449 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1370.5-1370.39" + process $proc$ls180.v:1370$3450 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1371.5-1371.38" + process $proc$ls180.v:1371$3451 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1372.11-1372.61" + process $proc$ls180.v:1372$3452 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1373.5-1373.41" + process $proc$ls180.v:1373$3453 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1374.5-1374.41" + process $proc$ls180.v:1374$3454 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1375.5-1375.41" + process $proc$ls180.v:1375$3455 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1376.5-1376.40" + process $proc$ls180.v:1376$3456 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1377.11-1377.54" + process $proc$ls180.v:1377$3457 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1378.11-1378.56" + process $proc$ls180.v:1378$3458 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1379.5-1379.33" + process $proc$ls180.v:1379$3459 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1380.12-1380.49" + process $proc$ls180.v:1380$3460 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1381.11-1381.41" + process $proc$ls180.v:1381$3461 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1383.5-1383.48" + process $proc$ls180.v:1383$3462 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1394.5-1394.55" + process $proc$ls180.v:1394$3463 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1399.5-1399.38" + process $proc$ls180.v:1399$3464 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1402.5-1402.55" + process $proc$ls180.v:1402$3465 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1403.5-1403.54" + process $proc$ls180.v:1403$3466 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1407.5-1407.57" + process $proc$ls180.v:1407$3467 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1408.5-1408.56" + process $proc$ls180.v:1408$3468 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1409.11-1409.70" + process $proc$ls180.v:1409$3469 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1410.11-1410.83" + process $proc$ls180.v:1410$3470 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1411.5-1411.50" + process $proc$ls180.v:1411$3471 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1413.5-1413.55" + process $proc$ls180.v:1413$3472 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1424.5-1424.51" + process $proc$ls180.v:1424$3473 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1426.5-1426.51" + process $proc$ls180.v:1426$3474 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1427.5-1427.50" + process $proc$ls180.v:1427$3475 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1428.11-1428.64" + process $proc$ls180.v:1428$3476 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1429.5-1429.40" + process $proc$ls180.v:1429$3477 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1431.5-1431.35" + process $proc$ls180.v:1431$3478 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1434.11-1434.42" + process $proc$ls180.v:1434$3479 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:1447.12-1447.52" + process $proc$ls180.v:1447$3480 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1448.5-1448.39" + process $proc$ls180.v:1448$3481 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1449.12-1449.51" + process $proc$ls180.v:1449$3482 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1450.5-1450.38" + process $proc$ls180.v:1450$3483 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1454.5-1454.34" + process $proc$ls180.v:1454$3484 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1455.13-1455.53" + process $proc$ls180.v:1455$3485 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1461.11-1461.51" + process $proc$ls180.v:1461$3486 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1462.5-1462.39" + process $proc$ls180.v:1462$3487 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1463.12-1463.51" + process $proc$ls180.v:1463$3488 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1464.5-1464.38" + process $proc$ls180.v:1464$3489 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1465.11-1465.51" + process $proc$ls180.v:1465$3490 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:1507.11-1507.47" + process $proc$ls180.v:1507$3491 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:1511.5-1511.49" + process $proc$ls180.v:1511$3492 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:1515.5-1515.51" + process $proc$ls180.v:1515$3493 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1516.5-1516.51" + process $proc$ls180.v:1516$3494 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1517.5-1517.51" + process $proc$ls180.v:1517$3495 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1518.5-1518.50" + process $proc$ls180.v:1518$3496 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1519.11-1519.64" + process $proc$ls180.v:1519$3497 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1520.11-1520.48" + process $proc$ls180.v:1520$3498 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1521.12-1521.59" + process $proc$ls180.v:1521$3499 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1525.12-1525.55" + process $proc$ls180.v:1525$3500 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1528.12-1528.59" + process $proc$ls180.v:1528$3501 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1532.12-1532.55" + process $proc$ls180.v:1532$3502 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:1535.12-1535.59" + process $proc$ls180.v:1535$3503 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1539.12-1539.55" + process $proc$ls180.v:1539$3504 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1542.12-1542.59" + process $proc$ls180.v:1542$3505 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1546.12-1546.55" + process $proc$ls180.v:1546$3506 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1549.12-1549.54" + process $proc$ls180.v:1549$3507 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1550.12-1550.54" + process $proc$ls180.v:1550$3508 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1551.12-1551.54" + process $proc$ls180.v:1551$3509 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1552.12-1552.54" + process $proc$ls180.v:1552$3510 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1553.5-1553.48" + process $proc$ls180.v:1553$3511 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1554.5-1554.48" + process $proc$ls180.v:1554$3512 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1555.5-1555.48" + process $proc$ls180.v:1555$3513 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1556.5-1556.47" + process $proc$ls180.v:1556$3514 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1557.11-1557.61" + process $proc$ls180.v:1557$3515 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1558.5-1558.50" + process $proc$ls180.v:1558$3516 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1560.5-1560.50" + process $proc$ls180.v:1560$3517 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1563.11-1563.47" + process $proc$ls180.v:1563$3518 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1564.11-1564.47" + process $proc$ls180.v:1564$3519 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1565.12-1565.58" + process $proc$ls180.v:1565$3520 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1569.12-1569.54" + process $proc$ls180.v:1569$3521 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1570.5-1570.46" + process $proc$ls180.v:1570$3522 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1572.12-1572.58" + process $proc$ls180.v:1572$3523 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1576.12-1576.54" + process $proc$ls180.v:1576$3524 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1577.5-1577.46" + process $proc$ls180.v:1577$3525 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1579.12-1579.58" + process $proc$ls180.v:1579$3526 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1583.12-1583.54" + process $proc$ls180.v:1583$3527 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1584.5-1584.46" + process $proc$ls180.v:1584$3528 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1586.12-1586.58" + process $proc$ls180.v:1586$3529 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1590.12-1590.54" + process $proc$ls180.v:1590$3530 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1591.5-1591.46" + process $proc$ls180.v:1591$3531 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1593.12-1593.53" + process $proc$ls180.v:1593$3532 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1594.12-1594.53" + process $proc$ls180.v:1594$3533 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1595.12-1595.53" + process $proc$ls180.v:1595$3534 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1596.12-1596.53" + process $proc$ls180.v:1596$3535 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1597.5-1597.43" + process $proc$ls180.v:1597$3536 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1598.12-1598.51" + process $proc$ls180.v:1598$3537 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1599.12-1599.51" + process $proc$ls180.v:1599$3538 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1600.12-1600.51" + process $proc$ls180.v:1600$3539 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1601.12-1601.51" + process $proc$ls180.v:1601$3540 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1603.11-1603.39" + process $proc$ls180.v:1603$3541 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1604.5-1604.32" + process $proc$ls180.v:1604$3542 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1605.5-1605.33" + process $proc$ls180.v:1605$3543 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1606.5-1606.35" + process $proc$ls180.v:1606$3544 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1608.12-1608.42" + process $proc$ls180.v:1608$3545 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1609.5-1609.33" + process $proc$ls180.v:1609$3546 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1610.5-1610.34" + process $proc$ls180.v:1610$3547 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1611.5-1611.36" + process $proc$ls180.v:1611$3548 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:1620.11-1620.41" + process $proc$ls180.v:1620$3549 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1621.11-1621.41" + process $proc$ls180.v:1621$3550 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1644.11-1644.45" + process $proc$ls180.v:1644$3551 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1645.5-1645.41" + process $proc$ls180.v:1645$3552 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1646.11-1646.47" + process $proc$ls180.v:1646$3553 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1647.11-1647.47" + process $proc$ls180.v:1647$3554 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1648.11-1648.50" + process $proc$ls180.v:1648$3555 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:1668.5-1668.51" + process $proc$ls180.v:1668$3556 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1669.5-1669.50" + process $proc$ls180.v:1669$3557 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1670.12-1670.66" + process $proc$ls180.v:1670$3558 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] + end + attribute \src "ls180.v:1671.11-1671.77" + process $proc$ls180.v:1671$3559 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1672.11-1672.50" + process $proc$ls180.v:1672$3560 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] + end + attribute \src "ls180.v:1674.5-1674.49" + process $proc$ls180.v:1674$3561 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1680.5-1680.45" + process $proc$ls180.v:1680$3562 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1682.12-1682.62" + process $proc$ls180.v:1682$3563 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1683.12-1683.60" + process $proc$ls180.v:1683$3564 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + end + attribute \src "ls180.v:1685.5-1685.57" + process $proc$ls180.v:1685$3565 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1689.12-1689.67" + process $proc$ls180.v:1689$3566 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1690.5-1690.54" + process $proc$ls180.v:1690$3567 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1691.12-1691.69" + process $proc$ls180.v:1691$3568 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1692.5-1692.56" + process $proc$ls180.v:1692$3569 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1693.5-1693.61" + process $proc$ls180.v:1693$3570 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1694.5-1694.56" + process $proc$ls180.v:1694$3571 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1695.5-1695.53" + process $proc$ls180.v:1695$3572 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1697.5-1697.59" + process $proc$ls180.v:1697$3573 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1698.5-1698.54" + process $proc$ls180.v:1698$3574 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1700.12-1700.61" + process $proc$ls180.v:1700$3575 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1703.12-1703.43" + process $proc$ls180.v:1703$3576 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1704.12-1704.45" + process $proc$ls180.v:1704$3577 + assign { } { } + assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] + sync init + end + attribute \src "ls180.v:1706.11-1706.41" + process $proc$ls180.v:1706$3578 + assign { } { } + assign $1\main_interface1_bus_sel[7:0] 8'00000000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] + end + attribute \src "ls180.v:1707.5-1707.35" + process $proc$ls180.v:1707$3579 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1708.5-1708.35" + process $proc$ls180.v:1708$3580 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1710.5-1710.34" + process $proc$ls180.v:1710$3581 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1711.11-1711.41" + process $proc$ls180.v:1711$3582 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1712.11-1712.41" + process $proc$ls180.v:1712$3583 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1719.5-1719.43" + process $proc$ls180.v:1719$3584 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1720.5-1720.43" + process $proc$ls180.v:1720$3585 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1721.5-1721.42" + process $proc$ls180.v:1721$3586 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1722.12-1722.61" + process $proc$ls180.v:1722$3587 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1723.5-1723.45" + process $proc$ls180.v:1723$3588 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1725.5-1725.45" + process $proc$ls180.v:1725$3589 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1726.5-1726.44" + process $proc$ls180.v:1726$3590 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1727.12-1727.60" + process $proc$ls180.v:1727$3591 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] + end + attribute \src "ls180.v:1728.12-1728.45" + process $proc$ls180.v:1728$3592 + assign { } { } + assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] + end + attribute \src "ls180.v:1729.12-1729.53" + process $proc$ls180.v:1729$3593 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:173.12-173.78" + process $proc$ls180.v:173$2924 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end + attribute \src "ls180.v:1730.5-1730.40" + process $proc$ls180.v:1730$3594 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1731.12-1731.55" + process $proc$ls180.v:1731$3595 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1732.5-1732.42" + process $proc$ls180.v:1732$3596 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1733.5-1733.47" + process $proc$ls180.v:1733$3597 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1734.5-1734.42" + process $proc$ls180.v:1734$3598 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1735.5-1735.44" + process $proc$ls180.v:1735$3599 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1737.5-1737.45" + process $proc$ls180.v:1737$3600 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1738.5-1738.40" + process $proc$ls180.v:1738$3601 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:1742.12-1742.47" + process $proc$ls180.v:1742$3602 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:1754.11-1754.64" + process $proc$ls180.v:1754$3603 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1756.11-1756.48" + process $proc$ls180.v:1756$3604 + assign { } { } + assign $1\main_sdmem2block_converter_mux[2:0] 3'000 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] + end + attribute \src "ls180.v:1780.11-1780.45" + process $proc$ls180.v:1780$3605 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1781.5-1781.41" + process $proc$ls180.v:1781$3606 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1782.11-1782.47" + process $proc$ls180.v:1782$3607 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1783.11-1783.47" + process $proc$ls180.v:1783$3608 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1784.11-1784.50" + process $proc$ls180.v:1784$3609 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:1797.5-1797.36" + process $proc$ls180.v:1797$3610 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1798.5-1798.41" + process $proc$ls180.v:1798$3611 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1799.5-1799.57" + process $proc$ls180.v:1799$3612 + assign { } { } + assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1800.5-1800.60" + process $proc$ls180.v:1800$3613 + assign { } { } + assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1801.5-1801.36" + process $proc$ls180.v:1801$3614 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1802.5-1802.41" + process $proc$ls180.v:1802$3615 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1803.5-1803.57" + process $proc$ls180.v:1803$3616 + assign { } { } + assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1804.5-1804.60" + process $proc$ls180.v:1804$3617 + assign { } { } + assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1805.5-1805.36" + process $proc$ls180.v:1805$3618 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1806.5-1806.41" + process $proc$ls180.v:1806$3619 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:1807.5-1807.60" + process $proc$ls180.v:1807$3620 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1808.5-1808.63" + process $proc$ls180.v:1808$3621 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1809.11-1809.41" + process $proc$ls180.v:1809$3622 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1810.11-1810.46" + process $proc$ls180.v:1810$3623 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1811.11-1811.44" + process $proc$ls180.v:1811$3624 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1812.11-1812.49" + process $proc$ls180.v:1812$3625 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1813.11-1813.44" + process $proc$ls180.v:1813$3626 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1814.11-1814.49" + process $proc$ls180.v:1814$3627 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1815.11-1815.44" + process $proc$ls180.v:1815$3628 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1816.11-1816.49" + process $proc$ls180.v:1816$3629 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1817.11-1817.44" + process $proc$ls180.v:1817$3630 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1818.11-1818.49" + process $proc$ls180.v:1818$3631 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1819.11-1819.43" + process $proc$ls180.v:1819$3632 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1820.11-1820.48" + process $proc$ls180.v:1820$3633 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:1833.5-1833.27" + process $proc$ls180.v:1833$3634 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1834.5-1834.27" + process $proc$ls180.v:1834$3635 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1835.5-1835.27" + process $proc$ls180.v:1835$3636 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1836.5-1836.27" + process $proc$ls180.v:1836$3637 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:1837.5-1837.42" + process $proc$ls180.v:1837$3638 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1838.5-1838.43" + process $proc$ls180.v:1838$3639 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1839.5-1839.43" + process $proc$ls180.v:1839$3640 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1840.5-1840.43" + process $proc$ls180.v:1840$3641 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1841.5-1841.43" + process $proc$ls180.v:1841$3642 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1842.5-1842.35" + process $proc$ls180.v:1842$3643 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:1843.5-1843.40" + process $proc$ls180.v:1843$3644 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1844.5-1844.55" + process $proc$ls180.v:1844$3645 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1845.5-1845.58" + process $proc$ls180.v:1845$3646 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1846.11-1846.42" + process $proc$ls180.v:1846$3647 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:1847.11-1847.47" + process $proc$ls180.v:1847$3648 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1848.11-1848.62" + process $proc$ls180.v:1848$3649 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1849.5-1849.59" + process $proc$ls180.v:1849$3650 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:185.5-185.72" + process $proc$ls180.v:185$2925 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1850.11-1850.42" + process $proc$ls180.v:1850$3651 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1851.11-1851.47" + process $proc$ls180.v:1851$3652 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1852.11-1852.60" + process $proc$ls180.v:1852$3653 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1853.5-1853.57" + process $proc$ls180.v:1853$3654 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1854.5-1854.41" + process $proc$ls180.v:1854$3655 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1855.5-1855.46" + process $proc$ls180.v:1855$3656 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1856.11-1856.66" + process $proc$ls180.v:1856$3657 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1857.5-1857.63" + process $proc$ls180.v:1857$3658 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1858.11-1858.47" + process $proc$ls180.v:1858$3659 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1859.11-1859.52" + process $proc$ls180.v:1859$3660 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1860.11-1860.66" + process $proc$ls180.v:1860$3661 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1861.5-1861.63" + process $proc$ls180.v:1861$3662 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1862.11-1862.47" + process $proc$ls180.v:1862$3663 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1863.11-1863.52" + process $proc$ls180.v:1863$3664 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1864.11-1864.67" + process $proc$ls180.v:1864$3665 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1865.5-1865.64" + process $proc$ls180.v:1865$3666 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1866.12-1866.71" + process $proc$ls180.v:1866$3667 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1867.5-1867.66" + process $proc$ls180.v:1867$3668 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1868.5-1868.66" + process $proc$ls180.v:1868$3669 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1869.5-1869.69" + process $proc$ls180.v:1869$3670 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1870.5-1870.41" + process $proc$ls180.v:1870$3671 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1871.5-1871.46" + process $proc$ls180.v:1871$3672 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1872.5-1872.66" + process $proc$ls180.v:1872$3673 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1873.5-1873.69" + process $proc$ls180.v:1873$3674 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1874.11-1874.41" + process $proc$ls180.v:1874$3675 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1875.11-1875.46" + process $proc$ls180.v:1875$3676 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1876.11-1876.61" + process $proc$ls180.v:1876$3677 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1877.5-1877.58" + process $proc$ls180.v:1877$3678 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1878.11-1878.48" + process $proc$ls180.v:1878$3679 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1879.11-1879.53" + process $proc$ls180.v:1879$3680 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:188.11-188.79" + process $proc$ls180.v:188$2926 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + sync init + end + attribute \src "ls180.v:1880.11-1880.70" + process $proc$ls180.v:1880$3681 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1881.5-1881.66" + process $proc$ls180.v:1881$3682 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1882.12-1882.73" + process $proc$ls180.v:1882$3683 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1883.5-1883.68" + process $proc$ls180.v:1883$3684 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1884.5-1884.69" + process $proc$ls180.v:1884$3685 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1885.5-1885.72" + process $proc$ls180.v:1885$3686 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1886.5-1886.52" + process $proc$ls180.v:1886$3687 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1887.5-1887.57" + process $proc$ls180.v:1887$3688 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1888.12-1888.93" + process $proc$ls180.v:1888$3689 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1889.5-1889.88" + process $proc$ls180.v:1889$3690 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1890.12-1890.93" + process $proc$ls180.v:1890$3691 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1891.5-1891.88" + process $proc$ls180.v:1891$3692 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1892.12-1892.93" + process $proc$ls180.v:1892$3693 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1893.5-1893.88" + process $proc$ls180.v:1893$3694 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1894.12-1894.93" + process $proc$ls180.v:1894$3695 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1895.5-1895.88" + process $proc$ls180.v:1895$3696 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1896.11-1896.87" + process $proc$ls180.v:1896$3697 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1897.5-1897.84" + process $proc$ls180.v:1897$3698 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1898.11-1898.42" + process $proc$ls180.v:1898$3699 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1899.11-1899.47" + process $proc$ls180.v:1899$3700 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1900.5-1900.55" + process $proc$ls180.v:1900$3701 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1901.5-1901.58" + process $proc$ls180.v:1901$3702 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1902.5-1902.56" + process $proc$ls180.v:1902$3703 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1903.5-1903.59" + process $proc$ls180.v:1903$3704 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1904.11-1904.62" + process $proc$ls180.v:1904$3705 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1905.5-1905.59" + process $proc$ls180.v:1905$3706 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1906.12-1906.65" + process $proc$ls180.v:1906$3707 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1907.5-1907.60" + process $proc$ls180.v:1907$3708 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1908.5-1908.56" + process $proc$ls180.v:1908$3709 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1909.5-1909.59" + process $proc$ls180.v:1909$3710 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1910.5-1910.58" + process $proc$ls180.v:1910$3711 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1911.5-1911.61" + process $proc$ls180.v:1911$3712 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1912.5-1912.57" + process $proc$ls180.v:1912$3713 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1913.5-1913.60" + process $proc$ls180.v:1913$3714 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1914.5-1914.59" + process $proc$ls180.v:1914$3715 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1915.5-1915.62" + process $proc$ls180.v:1915$3716 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1916.13-1916.76" + process $proc$ls180.v:1916$3717 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:1917.5-1917.69" + process $proc$ls180.v:1917$3718 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1918.11-1918.46" + process $proc$ls180.v:1918$3719 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1919.11-1919.51" + process $proc$ls180.v:1919$3720 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1920.12-1920.87" + process $proc$ls180.v:1920$3721 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1921.5-1921.82" + process $proc$ls180.v:1921$3722 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1922.5-1922.44" + process $proc$ls180.v:1922$3723 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1923.5-1923.49" + process $proc$ls180.v:1923$3724 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1924.12-1924.75" + process $proc$ls180.v:1924$3725 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + end + attribute \src "ls180.v:1925.5-1925.70" + process $proc$ls180.v:1925$3726 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1926.11-1926.60" + process $proc$ls180.v:1926$3727 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1927.11-1927.65" + process $proc$ls180.v:1927$3728 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1928.12-1928.87" + process $proc$ls180.v:1928$3729 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1929.5-1929.82" + process $proc$ls180.v:1929$3730 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1930.12-1930.43" + process $proc$ls180.v:1930$3731 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1931.5-1931.34" + process $proc$ls180.v:1931$3732 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1932.11-1932.43" + process $proc$ls180.v:1932$3733 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1934.12-1934.52" + process $proc$ls180.v:1934$3734 + assign { } { } + assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 + sync always + update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] + sync init + end + attribute \src "ls180.v:1935.12-1935.54" + process $proc$ls180.v:1935$3735 + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 + sync always + update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1936.12-1936.54" + process $proc$ls180.v:1936$3736 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1937.11-1937.50" + process $proc$ls180.v:1937$3737 + assign { } { } + assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 + sync always + update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] + sync init + end + attribute \src "ls180.v:1938.5-1938.44" + process $proc$ls180.v:1938$3738 + assign { } { } + assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] + sync init + end + attribute \src "ls180.v:1939.5-1939.44" + process $proc$ls180.v:1939$3739 + assign { } { } + assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] + sync init + end + attribute \src "ls180.v:1940.5-1940.44" + process $proc$ls180.v:1940$3740 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1941.5-1941.43" + process $proc$ls180.v:1941$3741 + assign { } { } + assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] + sync init + end + attribute \src "ls180.v:1944.12-1944.65" + process $proc$ls180.v:1944$3742 + assign { } { } + assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] + sync init + end + attribute \src "ls180.v:1948.5-1948.55" + process $proc$ls180.v:1948$3743 + assign { } { } + assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 + sync always + update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] + sync init + end + attribute \src "ls180.v:1952.5-1952.55" + process $proc$ls180.v:1952$3744 + assign { } { } + assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 + sync always + update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:1955.12-1955.40" + process $proc$ls180.v:1955$3745 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1959.5-1959.30" + process $proc$ls180.v:1959$3746 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:196.12-196.74" + process $proc$ls180.v:196$2927 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end + attribute \src "ls180.v:1965.11-1965.31" + process $proc$ls180.v:1965$3747 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:1966.11-1966.36" + process $proc$ls180.v:1966$3748 + assign { } { } + assign $1\builder_slave_sel[9:0] 10'0000000000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[9:0] + end + attribute \src "ls180.v:1967.11-1967.38" + process $proc$ls180.v:1967$3749 + assign { } { } + assign $1\builder_slave_sel_r[9:0] 10'0000000000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[9:0] + end + attribute \src "ls180.v:1968.5-1968.25" + process $proc$ls180.v:1968$3750 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:1971.12-1971.39" + process $proc$ls180.v:1971$3751 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:1975.11-1975.51" + process $proc$ls180.v:1975$3752 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:200.5-200.69" + process $proc$ls180.v:200$2928 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end + attribute \src "ls180.v:2016.11-2016.51" + process $proc$ls180.v:2016$3753 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2045.11-2045.51" + process $proc$ls180.v:2045$3754 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2058.11-2058.51" + process $proc$ls180.v:2058$3755 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2099.11-2099.51" + process $proc$ls180.v:2099$3756 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:213.5-213.40" + process $proc$ls180.v:213$2929 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2140.11-2140.51" + process $proc$ls180.v:2140$3757 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:217.5-217.40" + process $proc$ls180.v:217$2930 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:220.11-220.37" + process $proc$ls180.v:220$2931 + assign { } { } + assign $1\main_libresocsim_we[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:2205.11-2205.51" + process $proc$ls180.v:2205$3758 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:222.12-222.49" + process $proc$ls180.v:222$2932 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:223.5-223.36" + process $proc$ls180.v:223$2933 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:224.12-224.51" + process $proc$ls180.v:224$2934 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:225.5-225.38" + process $proc$ls180.v:225$2935 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:226.5-226.39" + process $proc$ls180.v:226$2936 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:227.5-227.34" + process $proc$ls180.v:227$2937 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:228.5-228.49" + process $proc$ls180.v:228$2938 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:229.5-229.44" + process $proc$ls180.v:229$2939 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:230.12-230.49" + process $proc$ls180.v:230$2940 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:2338.11-2338.51" + process $proc$ls180.v:2338$3759 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:234.5-234.41" + process $proc$ls180.v:234$2941 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:236.5-236.39" + process $proc$ls180.v:236$2942 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:237.5-237.45" + process $proc$ls180.v:237$2943 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2419.11-2419.51" + process $proc$ls180.v:2419$3760 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2436.11-2436.51" + process $proc$ls180.v:2436$3761 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:246.5-246.49" + process $proc$ls180.v:246$2944 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:247.5-247.44" + process $proc$ls180.v:247$2945 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:2477.11-2477.52" + process $proc$ls180.v:2477$3762 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:248.12-248.42" + process $proc$ls180.v:248$2946 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:2510.11-2510.52" + process $proc$ls180.v:2510$3763 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:255.5-255.36" + process $proc$ls180.v:255$2947 + assign { } { } + assign $1\main_ram_bus_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_ram_bus_ram_bus_ack $1\main_ram_bus_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2551.11-2551.52" + process $proc$ls180.v:2551$3764 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:259.5-259.36" + process $proc$ls180.v:259$2948 + assign { } { } + assign $0\main_ram_bus_ram_bus_err[0:0] 1'0 + sync always + update \main_ram_bus_ram_bus_err $0\main_ram_bus_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2616.11-2616.52" + process $proc$ls180.v:2616$3765 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:262.11-262.29" + process $proc$ls180.v:262$2949 + assign { } { } + assign $1\main_ram_we[7:0] 8'00000000 + sync always + sync init + update \main_ram_we $1\main_ram_we[7:0] + end + attribute \src "ls180.v:2641.11-2641.52" + process $proc$ls180.v:2641$3766 + assign { } { } + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2663.11-2663.31" + process $proc$ls180.v:2663$3767 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2664.11-2664.36" + process $proc$ls180.v:2664$3768 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2665.11-2665.55" + process $proc$ls180.v:2665$3769 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2666.5-2666.52" + process $proc$ls180.v:2666$3770 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2667.12-2667.55" + process $proc$ls180.v:2667$3771 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:2668.5-2668.50" + process $proc$ls180.v:2668$3772 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2669.5-2669.46" + process $proc$ls180.v:2669$3773 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2670.5-2670.49" + process $proc$ls180.v:2670$3774 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2671.5-2671.41" + process $proc$ls180.v:2671$3775 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2672.12-2672.49" + process $proc$ls180.v:2672$3776 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2673.11-2673.47" + process $proc$ls180.v:2673$3777 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2674.5-2674.41" + process $proc$ls180.v:2674$3778 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2675.5-2675.41" + process $proc$ls180.v:2675$3779 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2676.5-2676.41" + process $proc$ls180.v:2676$3780 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2677.5-2677.39" + process $proc$ls180.v:2677$3781 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2678.5-2678.39" + process $proc$ls180.v:2678$3782 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2679.5-2679.39" + process $proc$ls180.v:2679$3783 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2680.5-2680.41" + process $proc$ls180.v:2680$3784 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2681.12-2681.49" + process $proc$ls180.v:2681$3785 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2682.11-2682.47" + process $proc$ls180.v:2682$3786 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2683.5-2683.41" + process $proc$ls180.v:2683$3787 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2684.5-2684.42" + process $proc$ls180.v:2684$3788 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2685.5-2685.42" + process $proc$ls180.v:2685$3789 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2686.5-2686.39" + process $proc$ls180.v:2686$3790 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2687.5-2687.39" + process $proc$ls180.v:2687$3791 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2688.5-2688.39" + process $proc$ls180.v:2688$3792 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2689.12-2689.50" + process $proc$ls180.v:2689$3793 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2690.5-2690.42" + process $proc$ls180.v:2690$3794 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2691.5-2691.42" + process $proc$ls180.v:2691$3795 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2692.12-2692.50" + process $proc$ls180.v:2692$3796 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2693.5-2693.42" + process $proc$ls180.v:2693$3797 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2694.5-2694.42" + process $proc$ls180.v:2694$3798 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2695.12-2695.50" + process $proc$ls180.v:2695$3799 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2696.5-2696.42" + process $proc$ls180.v:2696$3800 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2697.5-2697.42" + process $proc$ls180.v:2697$3801 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:2698.12-2698.50" + process $proc$ls180.v:2698$3802 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2699.5-2699.42" + process $proc$ls180.v:2699$3803 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:270.5-270.51" + process $proc$ls180.v:270$2950 + assign { } { } + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] + end + attribute \src "ls180.v:2700.5-2700.42" + process $proc$ls180.v:2700$3804 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2701.12-2701.50" + process $proc$ls180.v:2701$3805 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2702.12-2702.50" + process $proc$ls180.v:2702$3806 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] + end + attribute \src "ls180.v:2703.11-2703.48" + process $proc$ls180.v:2703$3807 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] + end + attribute \src "ls180.v:2704.5-2704.42" + process $proc$ls180.v:2704$3808 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:2705.5-2705.42" + process $proc$ls180.v:2705$3809 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2706.5-2706.42" + process $proc$ls180.v:2706$3810 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2707.11-2707.48" + process $proc$ls180.v:2707$3811 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2708.11-2708.48" + process $proc$ls180.v:2708$3812 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2709.11-2709.47" + process $proc$ls180.v:2709$3813 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2710.12-2710.49" + process $proc$ls180.v:2710$3814 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2711.5-2711.41" + process $proc$ls180.v:2711$3815 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2712.5-2712.41" + process $proc$ls180.v:2712$3816 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2713.5-2713.41" + process $proc$ls180.v:2713$3817 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2714.5-2714.41" + process $proc$ls180.v:2714$3818 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2715.5-2715.41" + process $proc$ls180.v:2715$3819 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2716.5-2716.39" + process $proc$ls180.v:2716$3820 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2717.5-2717.39" + process $proc$ls180.v:2717$3821 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:274.5-274.51" + process $proc$ls180.v:274$2951 + assign { } { } + assign $0\main_interface0_converted_interface_err[0:0] 1'0 + sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:275.5-275.32" + process $proc$ls180.v:275$2952 + assign { } { } + assign $1\main_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_converter0_skip $1\main_converter0_skip[0:0] + end + attribute \src "ls180.v:276.5-276.35" + process $proc$ls180.v:276$2953 + assign { } { } + assign $1\main_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_converter0_counter $1\main_converter0_counter[0:0] + end + attribute \src "ls180.v:2774.32-2774.66" + process $proc$ls180.v:2774$3822 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2775.32-2775.66" + process $proc$ls180.v:2775$3823 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2776.32-2776.66" + process $proc$ls180.v:2776$3824 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2777.32-2777.66" + process $proc$ls180.v:2777$3825 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:2778.32-2778.66" + process $proc$ls180.v:2778$3826 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2779.32-2779.66" + process $proc$ls180.v:2779$3827 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:278.12-278.41" + process $proc$ls180.v:278$2954 + assign { } { } + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] + end + attribute \src "ls180.v:2780.32-2780.66" + process $proc$ls180.v:2780$3828 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2781.32-2781.66" + process $proc$ls180.v:2781$3829 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2782.32-2782.66" + process $proc$ls180.v:2782$3830 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2783.32-2783.66" + process $proc$ls180.v:2783$3831 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2784.32-2784.66" + process $proc$ls180.v:2784$3832 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2785.32-2785.66" + process $proc$ls180.v:2785$3833 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2786.32-2786.66" + process $proc$ls180.v:2786$3834 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2787.32-2787.66" + process $proc$ls180.v:2787$3835 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2788.32-2788.66" + process $proc$ls180.v:2788$3836 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2789.32-2789.66" + process $proc$ls180.v:2789$3837 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2790.32-2790.66" + process $proc$ls180.v:2790$3838 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2791.32-2791.66" + process $proc$ls180.v:2791$3839 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2792.32-2792.66" + process $proc$ls180.v:2792$3840 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2793.32-2793.66" + process $proc$ls180.v:2793$3841 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2794.32-2794.67" + process $proc$ls180.v:2794$3842 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2795.32-2795.67" + process $proc$ls180.v:2795$3843 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2796.32-2796.67" + process $proc$ls180.v:2796$3844 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2797.32-2797.67" + process $proc$ls180.v:2797$3845 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2798.32-2798.67" + process $proc$ls180.v:2798$3846 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2799.32-2799.67" + process $proc$ls180.v:2799$3847 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2800.32-2800.67" + process $proc$ls180.v:2800$3848 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:2801.32-2801.67" + process $proc$ls180.v:2801$3849 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2802.32-2802.67" + process $proc$ls180.v:2802$3850 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2803.32-2803.67" + process $proc$ls180.v:2803$3851 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:2804.32-2804.67" + process $proc$ls180.v:2804$3852 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2805.32-2805.67" + process $proc$ls180.v:2805$3853 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2806.32-2806.67" + process $proc$ls180.v:2806$3854 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2807.32-2807.67" + process $proc$ls180.v:2807$3855 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:2842.1-2847.4" + process $proc$ls180.v:2842$25 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:2849.1-2859.4" + process $proc$ls180.v:2849$27 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:2851.2-2858.9" + switch \main_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] + case + end + sync always + update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:285.5-285.51" + process $proc$ls180.v:285$2955 + assign { } { } + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] + end + attribute \src "ls180.v:2861.1-2907.4" + process $proc$ls180.v:2861$28 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign { } { } + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2873.2-2906.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } + attribute \src "ls180.v:2876.4-2883.11" + switch \main_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:2884.4-2897.7" + switch $and$ls180.v:2884$29_Y + attribute \src "ls180.v:2884.8-2884.91" + case 1'1 + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2885$30_Y + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2887$31_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2888$32_Y + attribute \src "ls180.v:2889.5-2896.8" + switch $or$ls180.v:2889$33_Y + attribute \src "ls180.v:2889.9-2889.72" + case 1'1 + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2890$34_Y + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2892.6-2895.9" + switch $eq$ls180.v:2892$35_Y + attribute \src "ls180.v:2892.10-2892.43" + case 1'1 + assign $0\main_interface0_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2902.4-2904.7" + switch $and$ls180.v:2902$36_Y + attribute \src "ls180.v:2902.8-2902.91" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] + update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] + update \main_converter0_skip $0\main_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:289.5-289.51" + process $proc$ls180.v:289$2956 + assign { } { } + assign $0\main_interface1_converted_interface_err[0:0] 1'0 + sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:290.5-290.32" + process $proc$ls180.v:290$2957 + assign { } { } + assign $1\main_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_converter1_skip $1\main_converter1_skip[0:0] + end + attribute \src "ls180.v:2909.1-2919.4" + process $proc$ls180.v:2909$38 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:2911.2-2918.9" + switch \main_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] + case + end + sync always + update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:291.5-291.35" + process $proc$ls180.v:291$2958 + assign { } { } + assign $1\main_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_converter1_counter $1\main_converter1_counter[0:0] + end + attribute \src "ls180.v:2921.1-2967.4" + process $proc$ls180.v:2921$39 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign { } { } + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2933.2-2966.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } + attribute \src "ls180.v:2936.4-2943.11" + switch \main_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:2944.4-2957.7" + switch $and$ls180.v:2944$40_Y + attribute \src "ls180.v:2944.8-2944.91" + case 1'1 + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2945$41_Y + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2947$42_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2948$43_Y + attribute \src "ls180.v:2949.5-2956.8" + switch $or$ls180.v:2949$44_Y + attribute \src "ls180.v:2949.9-2949.72" + case 1'1 + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2950$45_Y + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2952.6-2955.9" + switch $eq$ls180.v:2952$46_Y + attribute \src "ls180.v:2952.10-2952.43" + case 1'1 + assign $0\main_interface1_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2962.4-2964.7" + switch $and$ls180.v:2962$47_Y + attribute \src "ls180.v:2962.8-2962.91" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] + update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] + update \main_converter1_skip $0\main_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:293.12-293.41" + process $proc$ls180.v:293$2959 + assign { } { } + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + end + attribute \src "ls180.v:2969.1-2979.4" + process $proc$ls180.v:2969$49 + assign { } { } + assign $0\main_wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:2971.2-2978.9" + switch \main_socbushandler_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] + case + end + sync always + update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:297.5-297.24" + process $proc$ls180.v:297$2960 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:2981.1-3027.4" + process $proc$ls180.v:2981$50 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\main_wb_sdram_sel[3:0] 4'0000 + assign $0\main_wb_sdram_cyc[0:0] 1'0 + assign $0\main_wb_sdram_stb[0:0] 1'0 + assign $0\main_socbushandler_skip[0:0] 1'0 + assign { } { } + assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:2993.2-3026.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } + attribute \src "ls180.v:2996.4-3003.11" + switch \main_socbushandler_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:3004.4-3017.7" + switch $and$ls180.v:3004$51_Y + attribute \src "ls180.v:3004.8-3004.97" + case 1'1 + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3005$52_Y + assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3007$53_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3008$54_Y + attribute \src "ls180.v:3009.5-3016.8" + switch $or$ls180.v:3009$55_Y + attribute \src "ls180.v:3009.9-3009.54" + case 1'1 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3010$56_Y + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3012.6-3015.9" + switch $eq$ls180.v:3012$57_Y + attribute \src "ls180.v:3012.10-3012.46" + case 1'1 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3022.4-3024.7" + switch $and$ls180.v:3022$58_Y + attribute \src "ls180.v:3022.8-3022.97" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] + update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] + update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] + update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] + update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] + update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] + update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:3030.1-3040.4" + process $proc$ls180.v:3030$59 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3032$62_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3033$65_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3034$68_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3035$71_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3036$74_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3037$77_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3038$80_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3039$83_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:3046.1-3051.4" + process $proc$ls180.v:3046$85 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:3048.2-3050.5" + switch $and$ls180.v:3048$86_Y + attribute \src "ls180.v:3048.6-3048.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:3055.1-3065.4" + process $proc$ls180.v:3055$88 + assign { } { } + assign { } { } + assign $0\main_ram_we[7:0] [0] $and$ls180.v:3057$91_Y + assign $0\main_ram_we[7:0] [1] $and$ls180.v:3058$94_Y + assign $0\main_ram_we[7:0] [2] $and$ls180.v:3059$97_Y + assign $0\main_ram_we[7:0] [3] $and$ls180.v:3060$100_Y + assign $0\main_ram_we[7:0] [4] $and$ls180.v:3061$103_Y + assign $0\main_ram_we[7:0] [5] $and$ls180.v:3062$106_Y + assign $0\main_ram_we[7:0] [6] $and$ls180.v:3063$109_Y + assign $0\main_ram_we[7:0] [7] $and$ls180.v:3064$112_Y + sync always + update \main_ram_we $0\main_ram_we[7:0] + end + attribute \src "ls180.v:3104.1-3158.4" + process $proc$ls180.v:3104$113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + attribute \src "ls180.v:3123.2-3157.5" + switch \main_sdram_sel + attribute \src "ls180.v:3123.6-3123.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3140.6-3140.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:312.12-312.38" + process $proc$ls180.v:312$2961 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:313.5-313.36" + process $proc$ls180.v:313$2962 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:314.11-314.32" + process $proc$ls180.v:314$2963 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:3162.1-3178.4" + process $proc$ls180.v:3162$114 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + attribute \src "ls180.v:3167.2-3177.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3167.6-3167.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3168$115_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3169$116_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3170$117_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3171$118_Y + attribute \src "ls180.v:3172.6-3172.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:317.5-317.36" + process $proc$ls180.v:317$2964 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:318.5-318.35" + process $proc$ls180.v:318$2965 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:319.5-319.36" + process $proc$ls180.v:319$2966 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:320.5-320.35" + process $proc$ls180.v:320$2967 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:3221.1-3251.4" + process $proc$ls180.v:3221$127 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3227.2-3250.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3230.4-3233.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3230.8-3230.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3237.4-3241.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3237.8-3237.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3244.4-3248.7" + switch 1'1 + attribute \src "ls180.v:3244.8-3244.12" + case 1'1 + attribute \src "ls180.v:3245.5-3247.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3245.9-3245.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:324.5-324.36" + process $proc$ls180.v:324$2968 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:3266.1-3273.4" + process $proc$ls180.v:3266$131 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3268.2-3272.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3268.6-3268.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3270.6-3270.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3271$133_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3277.1-3284.4" + process $proc$ls180.v:3277$140 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3279.2-3283.5" + switch $and$ls180.v:3279$141_Y + attribute \src "ls180.v:3279.6-3279.115" + case 1'1 + attribute \src "ls180.v:3280.3-3282.6" + switch $ne$ls180.v:3280$142_Y + attribute \src "ls180.v:3280.7-3280.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3281$143_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:329.12-329.45" + process $proc$ls180.v:329$2969 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:3299.1-3306.4" + process $proc$ls180.v:3299$144 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3301.2-3305.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3301.6-3301.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3302$145_Y + attribute \src "ls180.v:3303.6-3303.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:330.5-330.43" + process $proc$ls180.v:330$2970 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:3315.1-3408.4" + process $proc$ls180.v:3315$153 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3331.2-3407.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3333.4-3341.7" + switch $and$ls180.v:3333$154_Y + attribute \src "ls180.v:3333.8-3333.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3335.5-3337.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3335.9-3335.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3345.4-3347.7" + switch $and$ls180.v:3345$155_Y + attribute \src "ls180.v:3345.8-3345.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3351.4-3360.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3351.8-3351.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3356.5-3358.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3356.9-3356.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3363.4-3365.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3363.8-3363.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3368.4-3370.7" + switch $not$ls180.v:3368$156_Y + attribute \src "ls180.v:3368.8-3368.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3379.4-3405.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3379.8-3379.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3381.8-3381.12" + case + attribute \src "ls180.v:3382.5-3404.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3382.9-3382.56" + case 1'1 + attribute \src "ls180.v:3383.6-3403.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3383.10-3383.44" + case 1'1 + attribute \src "ls180.v:3384.7-3400.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3384.11-3384.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3386.8-3393.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3386.12-3386.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3390.12-3390.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3395.8-3397.11" + switch $and$ls180.v:3395$157_Y + attribute \src "ls180.v:3395.12-3395.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3398.11-3398.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3401.10-3401.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:3423.1-3430.4" + process $proc$ls180.v:3423$161 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3425.2-3429.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3425.6-3425.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3427.6-3427.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3428$163_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3434.1-3441.4" + process $proc$ls180.v:3434$170 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3436.2-3440.5" + switch $and$ls180.v:3436$171_Y + attribute \src "ls180.v:3436.6-3436.115" + case 1'1 + attribute \src "ls180.v:3437.3-3439.6" + switch $ne$ls180.v:3437$172_Y + attribute \src "ls180.v:3437.7-3437.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3438$173_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:345.12-345.46" + process $proc$ls180.v:345$2971 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:3456.1-3463.4" + process $proc$ls180.v:3456$174 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3458.2-3462.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3458.6-3458.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3459$175_Y + attribute \src "ls180.v:3460.6-3460.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:346.5-346.44" + process $proc$ls180.v:346$2972 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:347.12-347.48" + process $proc$ls180.v:347$2973 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:3472.1-3565.4" + process $proc$ls180.v:3472$183 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign { } { } + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3488.2-3564.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3490.4-3498.7" + switch $and$ls180.v:3490$184_Y + attribute \src "ls180.v:3490.8-3490.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3492.5-3494.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3492.9-3492.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3502.4-3504.7" + switch $and$ls180.v:3502$185_Y + attribute \src "ls180.v:3502.8-3502.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3508.4-3517.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3508.8-3508.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3513.5-3515.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3513.9-3513.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3520.4-3522.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3520.8-3520.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3525.4-3527.7" + switch $not$ls180.v:3525$186_Y + attribute \src "ls180.v:3525.8-3525.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3536.4-3562.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3536.8-3536.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3538.8-3538.12" + case + attribute \src "ls180.v:3539.5-3561.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3539.9-3539.56" + case 1'1 + attribute \src "ls180.v:3540.6-3560.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3540.10-3540.44" + case 1'1 + attribute \src "ls180.v:3541.7-3557.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3541.11-3541.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3543.8-3550.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3543.12-3543.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3547.12-3547.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3552.8-3554.11" + switch $and$ls180.v:3552$187_Y + attribute \src "ls180.v:3552.12-3552.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3555.11-3555.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3558.10-3558.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:348.11-348.43" + process $proc$ls180.v:348$2974 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:349.5-349.38" + process $proc$ls180.v:349$2975 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:350.5-350.37" + process $proc$ls180.v:350$2976 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:351.5-351.38" + process $proc$ls180.v:351$2977 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:352.5-352.37" + process $proc$ls180.v:352$2978 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:353.5-353.36" + process $proc$ls180.v:353$2979 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:354.5-354.36" + process $proc$ls180.v:354$2980 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:355.5-355.40" + process $proc$ls180.v:355$2981 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:356.5-356.38" + process $proc$ls180.v:356$2982 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:357.12-357.47" + process $proc$ls180.v:357$2983 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:358.5-358.42" + process $proc$ls180.v:358$2984 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:3580.1-3587.4" + process $proc$ls180.v:3580$191 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3582.2-3586.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3582.6-3582.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3584.6-3584.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3585$193_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:359.11-359.50" + process $proc$ls180.v:359$2985 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:3591.1-3598.4" + process $proc$ls180.v:3591$200 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3593.2-3597.5" + switch $and$ls180.v:3593$201_Y + attribute \src "ls180.v:3593.6-3593.115" + case 1'1 + attribute \src "ls180.v:3594.3-3596.6" + switch $ne$ls180.v:3594$202_Y + attribute \src "ls180.v:3594.7-3594.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3595$203_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:360.5-360.42" + process $proc$ls180.v:360$2986 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3613.1-3620.4" + process $proc$ls180.v:3613$204 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3615.2-3619.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3615.6-3615.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3616$205_Y + attribute \src "ls180.v:3617.6-3617.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3629.1-3722.4" + process $proc$ls180.v:3629$213 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3645.2-3721.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3647.4-3655.7" + switch $and$ls180.v:3647$214_Y + attribute \src "ls180.v:3647.8-3647.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3649.5-3651.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3649.9-3649.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3659.4-3661.7" + switch $and$ls180.v:3659$215_Y + attribute \src "ls180.v:3659.8-3659.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3665.4-3674.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3665.8-3665.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3670.5-3672.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3670.9-3670.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3677.4-3679.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3677.8-3677.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3682.4-3684.7" + switch $not$ls180.v:3682$216_Y + attribute \src "ls180.v:3682.8-3682.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3693.4-3719.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3693.8-3693.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3695.8-3695.12" + case + attribute \src "ls180.v:3696.5-3718.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3696.9-3696.56" + case 1'1 + attribute \src "ls180.v:3697.6-3717.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3697.10-3697.44" + case 1'1 + attribute \src "ls180.v:3698.7-3714.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3698.11-3698.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3700.8-3707.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3700.12-3700.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3704.12-3704.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3709.8-3711.11" + switch $and$ls180.v:3709$217_Y + attribute \src "ls180.v:3709.12-3709.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3712.11-3712.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3715.10-3715.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:367.11-367.36" + process $proc$ls180.v:367$2987 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:368.5-368.25" + process $proc$ls180.v:368$2988 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:369.11-369.44" + process $proc$ls180.v:369$2989 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:370.5-370.33" + process $proc$ls180.v:370$2990 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:3737.1-3744.4" + process $proc$ls180.v:3737$221 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3739.2-3743.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3739.6-3739.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3741.6-3741.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3742$223_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:374.5-374.38" + process $proc$ls180.v:374$2991 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:3748.1-3755.4" + process $proc$ls180.v:3748$230 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3750.2-3754.5" + switch $and$ls180.v:3750$231_Y + attribute \src "ls180.v:3750.6-3750.115" + case 1'1 + attribute \src "ls180.v:3751.3-3753.6" + switch $ne$ls180.v:3751$232_Y + attribute \src "ls180.v:3751.7-3751.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3752$233_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:375.12-375.46" + process $proc$ls180.v:375$2992 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:376.5-376.33" + process $proc$ls180.v:376$2993 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:377.11-377.45" + process $proc$ls180.v:377$2994 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:3770.1-3777.4" + process $proc$ls180.v:3770$234 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3772.2-3776.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3772.6-3772.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3773$235_Y + attribute \src "ls180.v:3774.6-3774.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:378.5-378.34" + process $proc$ls180.v:378$2995 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:3786.1-3879.4" + process $proc$ls180.v:3786$243 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3802.2-3878.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3804.4-3812.7" + switch $and$ls180.v:3804$244_Y + attribute \src "ls180.v:3804.8-3804.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3806.5-3808.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3806.9-3806.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3816.4-3818.7" + switch $and$ls180.v:3816$245_Y + attribute \src "ls180.v:3816.8-3816.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3822.4-3831.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3822.8-3822.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3827.5-3829.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3827.9-3827.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3834.4-3836.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3834.8-3834.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3839.4-3841.7" + switch $not$ls180.v:3839$246_Y + attribute \src "ls180.v:3839.8-3839.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3850.4-3876.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3850.8-3850.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3852.8-3852.12" + case + attribute \src "ls180.v:3853.5-3875.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3853.9-3853.56" + case 1'1 + attribute \src "ls180.v:3854.6-3874.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3854.10-3854.44" + case 1'1 + attribute \src "ls180.v:3855.7-3871.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3855.11-3855.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3857.8-3864.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3857.12-3857.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3861.12-3861.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3866.8-3868.11" + switch $and$ls180.v:3866$247_Y + attribute \src "ls180.v:3866.12-3866.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3869.11-3869.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3872.10-3872.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:379.12-379.45" + process $proc$ls180.v:379$2996 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:380.5-380.32" + process $proc$ls180.v:380$2997 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:381.12-381.37" + process $proc$ls180.v:381$2998 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3899.1-3905.4" + process $proc$ls180.v:3899$286 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3901$299_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3902$312_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3903$325_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3904$338_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:3913.1-3918.4" + process $proc$ls180.v:3913$339 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3915.2-3917.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3915.6-3915.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3919.1-3924.4" + process $proc$ls180.v:3919$340 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3921.2-3923.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3921.6-3921.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3925.1-3930.4" + process $proc$ls180.v:3925$341 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3927.2-3929.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3927.6-3927.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3932.1-3938.4" + process $proc$ls180.v:3932$344 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3934$357_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3935$370_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3936$383_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3937$396_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:3946.1-3951.4" + process $proc$ls180.v:3946$397 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3948.2-3950.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3948.6-3948.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3952.1-3957.4" + process $proc$ls180.v:3952$398 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3954.2-3956.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3954.6-3954.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3958.1-3963.4" + process $proc$ls180.v:3958$399 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3960.2-3962.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3960.6-3960.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3964.1-3972.4" + process $proc$ls180.v:3964$400 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3966.2-3968.5" + switch $and$ls180.v:3966$403_Y + attribute \src "ls180.v:3966.6-3966.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3969.2-3971.5" + switch $and$ls180.v:3969$406_Y + attribute \src "ls180.v:3969.6-3969.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:3973.1-3981.4" + process $proc$ls180.v:3973$407 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3975.2-3977.5" + switch $and$ls180.v:3975$410_Y + attribute \src "ls180.v:3975.6-3975.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3978.2-3980.5" + switch $and$ls180.v:3978$413_Y + attribute \src "ls180.v:3978.6-3978.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:3982.1-3990.4" + process $proc$ls180.v:3982$414 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3984.2-3986.5" + switch $and$ls180.v:3984$417_Y + attribute \src "ls180.v:3984.6-3984.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3987.2-3989.5" + switch $and$ls180.v:3987$420_Y + attribute \src "ls180.v:3987.6-3987.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:3991.1-3999.4" + process $proc$ls180.v:3991$421 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3993.2-3995.5" + switch $and$ls180.v:3993$424_Y + attribute \src "ls180.v:3993.6-3993.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3996.2-3998.5" + switch $and$ls180.v:3996$427_Y + attribute \src "ls180.v:3996.6-3996.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:4004.1-4076.4" + process $proc$ls180.v:4004$430 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:4016.2-4075.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:4020.4-4026.7" + switch 1'1 + attribute \src "ls180.v:4020.8-4020.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4021$437_Y + case + end + attribute \src "ls180.v:4028.4-4032.7" + switch \main_sdram_read_available + attribute \src "ls180.v:4028.8-4028.33" + case 1'1 + attribute \src "ls180.v:4029.5-4031.8" + switch $or$ls180.v:4029$439_Y + attribute \src "ls180.v:4029.9-4029.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:4033.4-4035.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:4033.8-4033.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:4040.4-4042.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:4040.8-4040.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:4045.4-4047.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:4045.8-4045.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:4058.4-4064.7" + switch 1'1 + attribute \src "ls180.v:4058.8-4058.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4059$446_Y + case + end + attribute \src "ls180.v:4066.4-4070.7" + switch \main_sdram_write_available + attribute \src "ls180.v:4066.8-4066.34" + case 1'1 + attribute \src "ls180.v:4067.5-4069.8" + switch $or$ls180.v:4067$448_Y + attribute \src "ls180.v:4067.9-4067.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:4071.4-4073.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:4071.8-4071.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:4100.1-4113.4" + process $proc$ls180.v:4100$577 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:4103.2-4112.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:411.12-411.46" + process $proc$ls180.v:411$2999 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:412.11-412.47" + process $proc$ls180.v:412$3000 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:4120.1-4130.4" + process $proc$ls180.v:4120$579 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:4122.2-4129.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:4132.1-4178.4" + process $proc$ls180.v:4132$580 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign { } { } + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4144.2-4177.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4147.4-4154.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4155.4-4168.7" + switch $and$ls180.v:4155$581_Y + attribute \src "ls180.v:4155.8-4155.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4156$582_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4158$583_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4159$584_Y + attribute \src "ls180.v:4160.5-4167.8" + switch $or$ls180.v:4160$585_Y + attribute \src "ls180.v:4160.9-4160.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4161$586_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4163.6-4166.9" + switch $eq$ls180.v:4163$587_Y + attribute \src "ls180.v:4163.10-4163.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4173.4-4175.7" + switch $and$ls180.v:4173$588_Y + attribute \src "ls180.v:4173.8-4173.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:414.12-414.45" + process $proc$ls180.v:414$3001 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:415.11-415.40" + process $proc$ls180.v:415$3002 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:416.5-416.35" + process $proc$ls180.v:416$3003 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:417.5-417.34" + process $proc$ls180.v:417$3004 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:418.5-418.35" + process $proc$ls180.v:418$3005 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:419.5-419.34" + process $proc$ls180.v:419$3006 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:4223.1-4228.4" + process $proc$ls180.v:4223$620 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4225.2-4227.5" + switch $and$ls180.v:4225$621_Y + attribute \src "ls180.v:4225.6-4225.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4229.1-4233.4" + process $proc$ls180.v:4229$622 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:423.5-423.35" + process $proc$ls180.v:423$3007 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:4234.1-4239.4" + process $proc$ls180.v:4234$623 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4236.2-4238.5" + switch $and$ls180.v:4236$624_Y + attribute \src "ls180.v:4236.6-4236.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:4240.1-4244.4" + process $proc$ls180.v:4240$625 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:425.5-425.39" + process $proc$ls180.v:425$3008 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:4262.1-4269.4" + process $proc$ls180.v:4262$633 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4264.2-4268.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4264.6-4264.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4265$634_Y + attribute \src "ls180.v:4266.6-4266.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:427.5-427.39" + process $proc$ls180.v:427$3009 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4292.1-4299.4" + process $proc$ls180.v:4292$644 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4294.2-4298.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4294.6-4294.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4295$645_Y + attribute \src "ls180.v:4296.6-4296.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:430.5-430.32" + process $proc$ls180.v:430$3010 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:431.5-431.32" + process $proc$ls180.v:431$3011 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:4312.1-4316.4" + process $proc$ls180.v:4312$651 + assign { } { } + assign { } { } + assign { } { } + assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o + sync always + update \gpio_o $0\gpio_o[15:0] + end + attribute \src "ls180.v:4317.1-4321.4" + process $proc$ls180.v:4317$652 + assign { } { } + assign { } { } + assign { } { } + assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe + sync always + update \gpio_oe $0\gpio_oe[15:0] + end + attribute \src "ls180.v:432.5-432.31" + process $proc$ls180.v:432$3012 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:433.12-433.44" + process $proc$ls180.v:433$3013 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:4333.1-4381.4" + process $proc$ls180.v:4333$657 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4344.2-4380.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4348.4-4351.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4348.8-4348.33" + case 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spimaster25_clk_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4356.4-4362.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4356.8-4356.33" + case 1'1 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4357$658_Y + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4359.5-4361.8" + switch $eq$ls180.v:4359$660_Y + attribute \src "ls180.v:4359.9-4359.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4366.4-4370.7" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:4366.8-4366.33" + case 1'1 + assign $0\main_spimaster29_miso_latch[0:0] 1'1 + assign $0\main_spimaster3_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spimaster2_done[0:0] 1'1 + attribute \src "ls180.v:4374.4-4378.7" + switch \main_spimaster0_start + attribute \src "ls180.v:4374.8-4374.29" + case 1'1 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spimaster2_done $0\main_spimaster2_done[0:0] + update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] + update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] + update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] + update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] + update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:434.11-434.43" + process $proc$ls180.v:434$3014 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:435.5-435.38" + process $proc$ls180.v:435$3015 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:436.5-436.38" + process $proc$ls180.v:436$3016 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:437.5-437.37" + process $proc$ls180.v:437$3017 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:438.5-438.42" + process $proc$ls180.v:438$3018 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:439.5-439.43" + process $proc$ls180.v:439$3019 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:4392.1-4440.4" + process $proc$ls180.v:4392$665 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spisdcard_mosi_latch[0:0] 1'0 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_miso_latch[0:0] 1'0 + assign $0\main_spisdcard_irq[0:0] 1'0 + assign { } { } + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:4403.2-4439.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4407.4-4410.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4407.8-4407.31" + case 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spisdcard_clk_enable[0:0] 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4415.4-4421.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4415.8-4415.31" + case 1'1 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4416$666_Y + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4418.5-4420.8" + switch $eq$ls180.v:4418$668_Y + attribute \src "ls180.v:4418.9-4418.66" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4425.4-4429.7" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:4425.8-4425.31" + case 1'1 + assign $0\main_spisdcard_miso_latch[0:0] 1'1 + assign $0\main_spisdcard_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spisdcard_done0[0:0] 1'1 + attribute \src "ls180.v:4433.4-4437.7" + switch \main_spisdcard_start0 + attribute \src "ls180.v:4433.8-4433.29" + case 1'1 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] + update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] + update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] + update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] + update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] + update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] + update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:445.11-445.44" + process $proc$ls180.v:445$3020 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:447.5-447.38" + process $proc$ls180.v:447$3021 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:4472.1-4500.4" + process $proc$ls180.v:4472$690 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4474.2-4499.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:448.5-448.38" + process $proc$ls180.v:448$3022 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:449.5-449.39" + process $proc$ls180.v:449$3023 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:4502.1-4535.4" + process $proc$ls180.v:4502$693 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4512.2-4534.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4519.4-4525.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4519.8-4519.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4520$694_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4522.5-4524.8" + switch $eq$ls180.v:4522$695_Y + attribute \src "ls180.v:4522.9-4522.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4530.4-4532.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4530.8-4530.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:452.5-452.38" + process $proc$ls180.v:452$3024 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:453.11-453.46" + process $proc$ls180.v:453$3025 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:4536.1-4612.4" + process $proc$ls180.v:4536$696 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4546.2-4611.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4550.4-4575.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4576.4-4587.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4576.8-4576.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4577$697_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4579.5-4586.8" + switch $eq$ls180.v:4579$698_Y + attribute \src "ls180.v:4579.9-4579.40" + case 1'1 + attribute \src "ls180.v:4580.6-4585.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4580.10-4580.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4582.10-4582.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4593.4-4600.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4593.8-4593.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4594$699_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4596.5-4599.8" + switch $eq$ls180.v:4596$700_Y + attribute \src "ls180.v:4596.9-4596.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4605.4-4609.7" + switch $and$ls180.v:4605$701_Y + attribute \src "ls180.v:4605.8-4605.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4607.8-4607.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:454.5-454.38" + process $proc$ls180.v:454$3026 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:460.5-460.51" + process $proc$ls180.v:460$3027 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:461.5-461.51" + process $proc$ls180.v:461$3028 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:463.5-463.47" + process $proc$ls180.v:463$3029 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:464.5-464.45" + process $proc$ls180.v:464$3030 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:4646.1-4739.4" + process $proc$ls180.v:4646$710 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4664.2-4738.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4672$711_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4669.4-4671.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4669.8-4669.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4674.4-4677.7" + switch $eq$ls180.v:4674$712_Y + attribute \src "ls180.v:4674.8-4674.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4683$714_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4700$717_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4685.4-4699.7" + switch $and$ls180.v:4685$715_Y + attribute \src "ls180.v:4685.8-4685.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4687$716_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4689.5-4698.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4689.9-4689.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4691.6-4697.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4691.10-4691.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4695.10-4695.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4702.4-4705.7" + switch $eq$ls180.v:4702$718_Y + attribute \src "ls180.v:4702.8-4702.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4711.4-4717.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4711.8-4711.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4712$719_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4714.5-4716.8" + switch $eq$ls180.v:4714$720_Y + attribute \src "ls180.v:4714.9-4714.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4723.4-4725.7" + switch $and$ls180.v:4723$721_Y + attribute \src "ls180.v:4723.8-4723.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4732.4-4736.7" + switch $and$ls180.v:4732$723_Y + attribute \src "ls180.v:4732.8-4732.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:465.5-465.45" + process $proc$ls180.v:465$3031 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:466.12-466.57" + process $proc$ls180.v:466$3032 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:468.5-468.51" + process $proc$ls180.v:468$3033 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:469.5-469.51" + process $proc$ls180.v:469$3034 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:470.5-470.50" + process $proc$ls180.v:470$3035 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:471.5-471.54" + process $proc$ls180.v:471$3036 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:472.5-472.55" + process $proc$ls180.v:472$3037 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:473.5-473.56" + process $proc$ls180.v:473$3038 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:474.5-474.50" + process $proc$ls180.v:474$3039 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:477.5-477.67" + process $proc$ls180.v:477$3040 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:4773.1-4800.4" + process $proc$ls180.v:4773$731 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4781.2-4799.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4786.4-4790.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4786.8-4786.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4787$732_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4788$733_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4793.4-4797.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4793.8-4793.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:478.5-478.66" + process $proc$ls180.v:478$3041 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4801.1-4873.4" + process $proc$ls180.v:4801$734 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4812.2-4872.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4817.4-4819.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4817.8-4817.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4822$735_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4825.4-4832.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4833.4-4845.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4833.8-4833.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4834$736_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4836.5-4844.8" + switch $eq$ls180.v:4836$737_Y + attribute \src "ls180.v:4836.9-4836.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4839.6-4843.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4839.10-4839.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4841.10-4841.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4851.4-4854.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4851.8-4851.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4858.4-4863.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4858.8-4858.39" + case 1'1 + attribute \src "ls180.v:4859.5-4862.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4859.9-4859.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4868.4-4870.7" + switch $and$ls180.v:4868$738_Y + attribute \src "ls180.v:4868.8-4868.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:4907.1-5008.4" + process $proc$ls180.v:4907$746 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:4924.2-5007.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4934$748_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4931.4-4933.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:4931.8-4931.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4936.4-4939.7" + switch $eq$ls180.v:4936$749_Y + attribute \src "ls180.v:4936.8-4936.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4945$752_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4966$754_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4947.4-4965.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:4947.8-4947.37" + case 1'1 + attribute \src "ls180.v:4948.5-4964.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:4948.9-4948.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4950$753_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4952.6-4961.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:4952.10-4952.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4954.7-4960.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:4954.11-4954.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:4958.11-4958.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:4962.9-4962.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:4968.4-4971.7" + switch $eq$ls180.v:4968$755_Y + attribute \src "ls180.v:4968.8-4968.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4975.4-4981.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4975.8-4975.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4976$756_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4978.5-4980.8" + switch $eq$ls180.v:4978$757_Y + attribute \src "ls180.v:4978.9-4978.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:4987.4-4989.7" + switch $and$ls180.v:4987$758_Y + attribute \src "ls180.v:4987.8-4987.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4994.4-5005.7" + switch $and$ls180.v:4994$759_Y + attribute \src "ls180.v:4994.8-4994.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4996.5-5004.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4996.9-4996.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:493.11-493.68" + process $proc$ls180.v:493$3042 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:494.5-494.64" + process $proc$ls180.v:494$3043 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:495.11-495.70" + process $proc$ls180.v:495$3044 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:496.11-496.70" + process $proc$ls180.v:496$3045 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:497.11-497.73" + process $proc$ls180.v:497$3046 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5066.1-5073.4" + process $proc$ls180.v:5066$881 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:5068.2-5072.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:5068.6-5068.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:5070.6-5070.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:5088.1-5095.4" + process $proc$ls180.v:5088$904 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5090.2-5094.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:5090.6-5090.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:5092.6-5092.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:5098.1-5105.4" + process $proc$ls180.v:5098$915 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5100.2-5104.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:5100.6-5100.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:5102.6-5102.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:5108.1-5115.4" + process $proc$ls180.v:5108$926 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5110.2-5114.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:5110.6-5110.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:5112.6-5112.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:5118.1-5125.4" + process $proc$ls180.v:5118$937 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5120.2-5124.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:5120.6-5120.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:5122.6-5122.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:5126.1-5205.4" + process $proc$ls180.v:5126$938 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:5143.2-5204.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:5147.4-5149.7" + switch $eq$ls180.v:5147$939_Y + attribute \src "ls180.v:5147.8-5147.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:5150.4-5175.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:5176.4-5183.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:5176.8-5176.47" + case 1'1 + attribute \src "ls180.v:5177.5-5182.8" + switch $eq$ls180.v:5177$940_Y + attribute \src "ls180.v:5177.9-5177.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:5179.9-5179.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5180$941_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5198.4-5202.7" + switch $and$ls180.v:5198$943_Y + attribute \src "ls180.v:5198.8-5198.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:518.5-518.59" + process $proc$ls180.v:518$3047 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:520.5-520.59" + process $proc$ls180.v:520$3048 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:5206.1-5211.4" + process $proc$ls180.v:5206$944 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5208.2-5210.5" + switch $and$ls180.v:5208$951_Y + attribute \src "ls180.v:5208.6-5208.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:521.5-521.58" + process $proc$ls180.v:521$3049 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:5214.1-5221.4" + process $proc$ls180.v:5214$953 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5216.2-5220.5" + switch $eq$ls180.v:5216$954_Y + attribute \src "ls180.v:5216.6-5216.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5218.6-5218.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:522.5-522.64" + process $proc$ls180.v:522$3050 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:5224.1-5231.4" + process $proc$ls180.v:5224$956 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5226.2-5230.5" + switch $eq$ls180.v:5226$957_Y + attribute \src "ls180.v:5226.6-5226.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5228.6-5228.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:523.12-523.74" + process $proc$ls180.v:523$3051 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:5234.1-5241.4" + process $proc$ls180.v:5234$959 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5236.2-5240.5" + switch $eq$ls180.v:5236$960_Y + attribute \src "ls180.v:5236.6-5236.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5238.6-5238.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:524.12-524.47" + process $proc$ls180.v:524$3052 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:5244.1-5251.4" + process $proc$ls180.v:5244$962 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5246.2-5250.5" + switch $eq$ls180.v:5246$963_Y + attribute \src "ls180.v:5246.6-5246.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5248.6-5248.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:525.5-525.46" + process $proc$ls180.v:525$3053 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:5253.1-5258.4" + process $proc$ls180.v:5253$964 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5255.2-5257.5" + switch $and$ls180.v:5255$966_Y + attribute \src "ls180.v:5255.6-5255.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:5259.1-5266.4" + process $proc$ls180.v:5259$967 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5261.2-5265.5" + switch $lt$ls180.v:5261$968_Y + attribute \src "ls180.v:5261.6-5261.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5263.6-5263.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:527.5-527.44" + process $proc$ls180.v:527$3054 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:5270.1-5277.4" + process $proc$ls180.v:5270$979 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5272.2-5276.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5272.6-5272.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5274.6-5274.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:528.5-528.45" + process $proc$ls180.v:528$3055 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:5280.1-5287.4" + process $proc$ls180.v:5280$990 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5282.2-5286.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5282.6-5282.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5284.6-5284.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:529.5-529.54" + process $proc$ls180.v:529$3056 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5290.1-5297.4" + process $proc$ls180.v:5290$1001 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5292.2-5296.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5292.6-5292.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5294.6-5294.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:5300.1-5307.4" + process $proc$ls180.v:5300$1012 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5302.2-5306.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5302.6-5302.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5304.6-5304.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:5308.1-5498.4" + process $proc$ls180.v:5308$1013 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5349.2-5497.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5352.4-5372.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5370$1014_Y + case + end + attribute \src "ls180.v:5373.4-5385.7" + switch $and$ls180.v:5373$1015_Y + attribute \src "ls180.v:5373.8-5373.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5374$1016_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5376.5-5384.8" + switch $eq$ls180.v:5376$1017_Y + attribute \src "ls180.v:5376.9-5376.40" + case 1'1 + attribute \src "ls180.v:5377.6-5383.9" + switch $eq$ls180.v:5377$1018_Y + attribute \src "ls180.v:5377.10-5377.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5381.10-5381.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5389$1019_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5390.4-5394.7" + switch $eq$ls180.v:5390$1020_Y + attribute \src "ls180.v:5390.8-5390.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5392.8-5392.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5396.4-5417.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5396.8-5396.36" + case 1'1 + attribute \src "ls180.v:5397.5-5416.8" + switch $eq$ls180.v:5397$1021_Y + attribute \src "ls180.v:5397.9-5397.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5401.9-5401.13" + case + attribute \src "ls180.v:5402.6-5415.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5402.10-5402.37" + case 1'1 + attribute \src "ls180.v:5403.7-5411.10" + switch $eq$ls180.v:5403$1022_Y + attribute \src "ls180.v:5403.11-5403.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5405.11-5405.15" + case + attribute \src "ls180.v:5406.8-5410.11" + switch $eq$ls180.v:5406$1023_Y + attribute \src "ls180.v:5406.12-5406.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5408.12-5408.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5412.10-5412.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5425.4-5431.7" + switch $and$ls180.v:5425$1025_Y + attribute \src "ls180.v:5425.8-5425.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5426$1026_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5428.5-5430.8" + switch $eq$ls180.v:5428$1028_Y + attribute \src "ls180.v:5428.9-5428.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5433.4-5438.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5433.8-5433.37" + case 1'1 + attribute \src "ls180.v:5434.5-5437.8" + switch $ne$ls180.v:5434$1029_Y + attribute \src "ls180.v:5434.9-5434.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5443$1031_Y + attribute \src "ls180.v:5444.4-5470.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5444.8-5444.37" + case 1'1 + attribute \src "ls180.v:5445.5-5469.8" + switch $eq$ls180.v:5445$1032_Y + attribute \src "ls180.v:5445.9-5445.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5451.6-5459.9" + switch $and$ls180.v:5451$1033_Y + attribute \src "ls180.v:5451.10-5451.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5452$1034_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5454.7-5458.10" + switch $eq$ls180.v:5454$1036_Y + attribute \src "ls180.v:5454.11-5454.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5456.11-5456.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5460.9-5460.13" + case + attribute \src "ls180.v:5461.6-5468.9" + switch $eq$ls180.v:5461$1037_Y + attribute \src "ls180.v:5461.10-5461.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5481.4-5495.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5481.8-5481.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:531.32-531.76" + process $proc$ls180.v:531$3057 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:532.11-532.55" + process $proc$ls180.v:532$3058 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:534.32-534.75" + process $proc$ls180.v:534$3059 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:536.32-536.76" + process $proc$ls180.v:536$3060 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:542.5-542.51" + process $proc$ls180.v:542$3061 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:543.5-543.51" + process $proc$ls180.v:543$3062 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:545.5-545.47" + process $proc$ls180.v:545$3063 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:546.5-546.45" + process $proc$ls180.v:546$3064 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:547.5-547.45" + process $proc$ls180.v:547$3065 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:548.12-548.57" + process $proc$ls180.v:548$3066 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$2900 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:550.5-550.51" + process $proc$ls180.v:550$3067 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:551.5-551.51" + process $proc$ls180.v:551$3068 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:552.5-552.50" + process $proc$ls180.v:552$3069 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:5526.1-5533.4" + process $proc$ls180.v:5526$1038 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5528.2-5532.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5528.6-5528.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5529$1039_Y + attribute \src "ls180.v:5530.6-5530.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:553.5-553.54" + process $proc$ls180.v:553$3070 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:554.5-554.55" + process $proc$ls180.v:554$3071 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:555.5-555.56" + process $proc$ls180.v:555$3072 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:5559.1-5598.4" + process $proc$ls180.v:5559$1049 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5569.2-5597.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5573$1050_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5575.4-5586.7" + switch $and$ls180.v:5575$1051_Y + attribute \src "ls180.v:5575.8-5575.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5576$1052_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5578.5-5585.8" + switch $eq$ls180.v:5578$1054_Y + attribute \src "ls180.v:5578.9-5578.106" + case 1'1 + attribute \src "ls180.v:5579.6-5584.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5579.10-5579.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5582.10-5582.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:556.5-556.50" + process $proc$ls180.v:556$3073 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:559.5-559.67" + process $proc$ls180.v:559$3074 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$2901 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.5-560.66" + process $proc$ls180.v:560$3075 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5618.1-5655.4" + process $proc$ls180.v:5618$1056 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_adr[31:0] 0 + assign { } { } + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_sel[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5632.2-5654.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5637.4-5640.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5637.8-5637.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[7:0] 8'11111111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5648.4-5652.7" + switch $and$ls180.v:5648$1057_Y + attribute \src "ls180.v:5648.8-5648.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:5656.1-5692.4" + process $proc$ls180.v:5656$1058 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5665.2-5691.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5668$1060_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5669$1061_Y + attribute \src "ls180.v:5670.4-5681.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5670.8-5670.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5671$1062_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5673.5-5680.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5673.9-5673.39" + case 1'1 + attribute \src "ls180.v:5674.6-5679.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5674.10-5674.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5677.10-5677.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$2902 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:5704.1-5732.4" + process $proc$ls180.v:5704$1068 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5706.2-5731.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:5746.1-5753.4" + process $proc$ls180.v:5746$1069 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5748.2-5752.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5748.6-5748.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5749$1070_Y + attribute \src "ls180.v:5750.6-5750.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:575.11-575.68" + process $proc$ls180.v:575$3076 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:576.5-576.64" + process $proc$ls180.v:576$3077 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:5761.1-5797.4" + process $proc$ls180.v:5761$1076 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5772.2-5796.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5788.4-5794.7" + switch $and$ls180.v:5788$1077_Y + attribute \src "ls180.v:5788.8-5788.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5791$1079_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:577.11-577.70" + process $proc$ls180.v:577$3078 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:578.11-578.70" + process $proc$ls180.v:578$3079 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:579.11-579.73" + process $proc$ls180.v:579$3080 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$2903 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:5822.1-5834.4" + process $proc$ls180.v:5822$1100 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[9:0] [0] $eq$ls180.v:5824$1101_Y + assign $0\builder_slave_sel[9:0] [1] $eq$ls180.v:5825$1102_Y + assign $0\builder_slave_sel[9:0] [2] $eq$ls180.v:5826$1103_Y + assign $0\builder_slave_sel[9:0] [3] $eq$ls180.v:5827$1104_Y + assign $0\builder_slave_sel[9:0] [4] $eq$ls180.v:5828$1105_Y + assign $0\builder_slave_sel[9:0] [5] $eq$ls180.v:5829$1106_Y + assign $0\builder_slave_sel[9:0] [6] $eq$ls180.v:5830$1107_Y + assign $0\builder_slave_sel[9:0] [7] $eq$ls180.v:5831$1108_Y + assign $0\builder_slave_sel[9:0] [8] $eq$ls180.v:5832$1109_Y + assign $0\builder_slave_sel[9:0] [9] $eq$ls180.v:5833$1110_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[9:0] + end + attribute \src "ls180.v:5917.1-5928.4" + process $proc$ls180.v:5917$1133 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign { } { } + assign $0\builder_shared_ack[0:0] $or$ls180.v:5921$1142_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5922$1161_Y [31:0] + attribute \src "ls180.v:5923.2-5927.5" + switch \builder_done + attribute \src "ls180.v:5923.6-5923.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:600.5-600.59" + process $proc$ls180.v:600$3081 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:602.5-602.59" + process $proc$ls180.v:602$3082 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:603.5-603.58" + process $proc$ls180.v:603$3083 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:604.5-604.64" + process $proc$ls180.v:604$3084 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:605.12-605.74" + process $proc$ls180.v:605$3085 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:606.12-606.47" + process $proc$ls180.v:606$3086 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:607.5-607.46" + process $proc$ls180.v:607$3087 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:609.5-609.44" + process $proc$ls180.v:609$3088 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:610.5-610.45" + process $proc$ls180.v:610$3089 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:611.5-611.54" + process $proc$ls180.v:611$3090 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:613.32-613.76" + process $proc$ls180.v:613$3091 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:614.11-614.55" + process $proc$ls180.v:614$3092 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:616.32-616.75" + process $proc$ls180.v:616$3093 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:618.32-618.76" + process $proc$ls180.v:618$3094 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:624.5-624.51" + process $proc$ls180.v:624$3095 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:625.5-625.51" + process $proc$ls180.v:625$3096 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:627.5-627.47" + process $proc$ls180.v:627$3097 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:628.5-628.45" + process $proc$ls180.v:628$3098 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:629.5-629.45" + process $proc$ls180.v:629$3099 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$2904 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:630.12-630.57" + process $proc$ls180.v:630$3100 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:632.5-632.51" + process $proc$ls180.v:632$3101 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:633.5-633.51" + process $proc$ls180.v:633$3102 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:634.5-634.50" + process $proc$ls180.v:634$3103 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:635.5-635.54" + process $proc$ls180.v:635$3104 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:636.5-636.55" + process $proc$ls180.v:636$3105 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:637.5-637.56" + process $proc$ls180.v:637$3106 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:638.5-638.50" + process $proc$ls180.v:638$3107 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:641.5-641.67" + process $proc$ls180.v:641$3108 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:642.5-642.66" + process $proc$ls180.v:642$3109 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6442.1-6447.4" + process $proc$ls180.v:6442$2035 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6444.2-6446.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6444.6-6444.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:6488.1-6493.4" + process $proc$ls180.v:6488$2100 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6490.2-6492.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6490.6-6490.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$2905 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:657.11-657.68" + process $proc$ls180.v:657$3110 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:658.5-658.64" + process $proc$ls180.v:658$3111 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:659.11-659.70" + process $proc$ls180.v:659$3112 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:660.11-660.70" + process $proc$ls180.v:660$3113 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:661.11-661.73" + process $proc$ls180.v:661$3114 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6677.1-6693.4" + process $proc$ls180.v:6677$2321 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6679.2-6692.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:6694.1-6710.4" + process $proc$ls180.v:6694$2322 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6696.2-6709.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:6711.1-6727.4" + process $proc$ls180.v:6711$2323 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6713.2-6726.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:6728.1-6744.4" + process $proc$ls180.v:6728$2324 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6730.2-6743.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:6745.1-6761.4" + process $proc$ls180.v:6745$2325 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6747.2-6760.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:6762.1-6778.4" + process $proc$ls180.v:6762$2326 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6764.2-6777.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:6779.1-6795.4" + process $proc$ls180.v:6779$2327 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6781.2-6794.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:6796.1-6812.4" + process $proc$ls180.v:6796$2328 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6798.2-6811.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:6813.1-6829.4" + process $proc$ls180.v:6813$2329 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6815.2-6828.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:682.5-682.59" + process $proc$ls180.v:682$3115 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:6830.1-6846.4" + process $proc$ls180.v:6830$2330 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6832.2-6845.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:684.5-684.59" + process $proc$ls180.v:684$3116 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:6847.1-6863.4" + process $proc$ls180.v:6847$2331 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6849.2-6862.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:685.5-685.58" + process $proc$ls180.v:685$3117 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:686.5-686.64" + process $proc$ls180.v:686$3118 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:6864.1-6880.4" + process $proc$ls180.v:6864$2332 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6866.2-6879.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:687.12-687.74" + process $proc$ls180.v:687$3119 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:688.12-688.47" + process $proc$ls180.v:688$3120 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:6881.1-6897.4" + process $proc$ls180.v:6881$2333 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6883.2-6896.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:689.5-689.46" + process $proc$ls180.v:689$3121 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:6898.1-6914.4" + process $proc$ls180.v:6898$2334 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:6900.2-6913.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:691.5-691.44" + process $proc$ls180.v:691$3122 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:6915.1-6931.4" + process $proc$ls180.v:6915$2335 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:6917.2-6930.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:692.5-692.45" + process $proc$ls180.v:692$3123 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:693.5-693.54" + process $proc$ls180.v:693$3124 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:6932.1-6948.4" + process $proc$ls180.v:6932$2336 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6934.2-6947.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:6949.1-6965.4" + process $proc$ls180.v:6949$2337 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6951.2-6964.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:695.32-695.76" + process $proc$ls180.v:695$3125 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:696.11-696.55" + process $proc$ls180.v:696$3126 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:6966.1-6982.4" + process $proc$ls180.v:6966$2338 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6968.2-6981.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:698.32-698.75" + process $proc$ls180.v:698$3127 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:6983.1-6990.4" + process $proc$ls180.v:6983$2339 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6985.2-6989.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:6991.1-6998.4" + process $proc$ls180.v:6991$2340 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:6993.2-6997.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:6999.1-7006.4" + process $proc$ls180.v:6999$2341 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:7001.2-7005.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7003$2354_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:700.32-700.76" + process $proc$ls180.v:700$3128 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7007.1-7014.4" + process $proc$ls180.v:7007$2355 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7009.2-7013.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:7015.1-7022.4" + process $proc$ls180.v:7015$2356 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:7017.2-7021.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:7023.1-7030.4" + process $proc$ls180.v:7023$2357 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:7025.2-7029.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7027$2370_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:7031.1-7038.4" + process $proc$ls180.v:7031$2371 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7033.2-7037.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:7039.1-7046.4" + process $proc$ls180.v:7039$2372 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:7041.2-7045.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:7047.1-7054.4" + process $proc$ls180.v:7047$2373 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:7049.2-7053.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7051$2386_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:7055.1-7062.4" + process $proc$ls180.v:7055$2387 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7057.2-7061.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:706.5-706.51" + process $proc$ls180.v:706$3129 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:7063.1-7070.4" + process $proc$ls180.v:7063$2388 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:7065.2-7069.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:707.5-707.51" + process $proc$ls180.v:707$3130 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:7071.1-7078.4" + process $proc$ls180.v:7071$2389 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:7073.2-7077.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7075$2402_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:7079.1-7098.4" + process $proc$ls180.v:7079$2403 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:7081.2-7097.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:709.5-709.47" + process $proc$ls180.v:709$3131 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:7099.1-7118.4" + process $proc$ls180.v:7099$2404 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:7101.2-7117.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] + end + attribute \src "ls180.v:710.5-710.45" + process $proc$ls180.v:710$3132 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:711.5-711.45" + process $proc$ls180.v:711$3133 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:7119.1-7138.4" + process $proc$ls180.v:7119$2405 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:7121.2-7137.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] + end + attribute \src "ls180.v:712.12-712.57" + process $proc$ls180.v:712$3134 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:7139.1-7158.4" + process $proc$ls180.v:7139$2406 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:7141.2-7157.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:714.5-714.51" + process $proc$ls180.v:714$3135 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:715.5-715.51" + process $proc$ls180.v:715$3136 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:7159.1-7178.4" + process $proc$ls180.v:7159$2407 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:7161.2-7177.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:716.5-716.50" + process $proc$ls180.v:716$3137 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:717.5-717.54" + process $proc$ls180.v:717$3138 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:7179.1-7198.4" + process $proc$ls180.v:7179$2408 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:7181.2-7197.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:718.5-718.55" + process $proc$ls180.v:718$3139 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:719.5-719.56" + process $proc$ls180.v:719$3140 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:7199.1-7218.4" + process $proc$ls180.v:7199$2409 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:7201.2-7217.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:720.5-720.50" + process $proc$ls180.v:720$3141 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:7219.1-7238.4" + process $proc$ls180.v:7219$2410 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:7221.2-7237.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:723.5-723.67" + process $proc$ls180.v:723$3142 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:7239.1-7255.4" + process $proc$ls180.v:7239$2411 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7241.2-7254.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:724.5-724.66" + process $proc$ls180.v:724$3143 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:7256.1-7272.4" + process $proc$ls180.v:7256$2412 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7258.2-7271.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:7273.1-7289.4" + process $proc$ls180.v:7273$2413 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7275.2-7288.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7280$2415_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7283$2417_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7286$2419_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:7290.1-7306.4" + process $proc$ls180.v:7290$2420 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7292.2-7305.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7297$2422_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7300$2424_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7303$2426_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:7307.1-7323.4" + process $proc$ls180.v:7307$2427 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7309.2-7322.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7314$2429_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7317$2431_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7320$2433_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:7324.1-7340.4" + process $proc$ls180.v:7324$2434 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7326.2-7339.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7331$2436_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7334$2438_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7337$2440_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:7341.1-7357.4" + process $proc$ls180.v:7341$2441 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7343.2-7356.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7348$2443_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7351$2445_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7354$2447_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:7358.1-7386.4" + process $proc$ls180.v:7358$2448 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7360.2-7385.9" + switch \main_spimaster34_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:7387.1-7415.4" + process $proc$ls180.v:7387$2449 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7389.2-7414.9" + switch \main_spisdcard_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:739.11-739.68" + process $proc$ls180.v:739$3144 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$2906 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] + sync init + end + attribute \src "ls180.v:740.5-740.64" + process $proc$ls180.v:740$3145 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:741.11-741.70" + process $proc$ls180.v:741$3146 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:742.11-742.70" + process $proc$ls180.v:742$3147 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:743.11-743.73" + process $proc$ls180.v:743$3148 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:7473.1-7483.4" + process $proc$ls180.v:7473$2450 + assign { } { } + assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 + assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 + sync always + update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:7484.1-7494.4" + process $proc$ls180.v:7484$2451 + assign { } { } + assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 + assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$2907 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] + sync init + end + attribute \src "ls180.v:7515.1-7517.4" + process $proc$ls180.v:7515$2452 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] + end + attribute \src "ls180.v:7519.1-7589.4" + process $proc$ls180.v:7519$2453 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] $and$ls180.v:7573$2454_Y + assign $0\sdram_dm[1:0] [1] $and$ls180.v:7574$2455_Y + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7576$2457_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:7591.1-10220.4" + process $proc$ls180.v:7591$2458 + assign $0\pwm[1:0] \pwm + assign $0\uart_tx[0:0] \uart_tx + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign $0\main_converter0_counter[0:0] \main_converter0_counter + assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r + assign $0\main_converter1_counter[0:0] \main_converter1_counter + assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage + assign { } { } + assign { } { } + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy + assign { } { } + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx + assign { } { } + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage + assign { } { } + assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage + assign { } { } + assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso + assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage + assign { } { } + assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage + assign { } { } + assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage + assign { } { } + assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage + assign { } { } + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count + assign { } { } + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data + assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel + assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso + assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage + assign { } { } + assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage + assign { } { } + assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage + assign { } { } + assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage + assign { } { } + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count + assign { } { } + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data + assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel + assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data + assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage + assign { } { } + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[23:0] [0] $or$ls180.v:7592$2459_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7593$2460_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7594$2461_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7595$2462_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7596$2463_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7597$2464_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7598$2465_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7599$2466_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7600$2467_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7601$2468_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7602$2469_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7603$2470_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7604$2471_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7605$2472_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7606$2473_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7607$2474_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7608$2475_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7609$2476_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7610$2477_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7611$2478_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7612$2479_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7613$2480_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7614$2481_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7615$2482_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_ram_bus_ram_bus_ack[0:0] 1'0 + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8061$2582_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8062$2583_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8063$2584_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8097$2602_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8098$2614_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8256$2660_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8265$2663_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8291$2665_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8300$2668_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[9:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re + assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7616.2-7618.5" + switch $or$ls180.v:7616$2483_Y + attribute \src "ls180.v:7616.6-7616.69" + case 1'1 + assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r + case + end + attribute \src "ls180.v:7620.2-7622.5" + switch \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7620.6-7620.54" + case 1'1 + assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7623.2-7626.5" + switch \main_converter0_reset + attribute \src "ls180.v:7623.6-7623.27" + case 1'1 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7627.2-7629.5" + switch $or$ls180.v:7627$2484_Y + attribute \src "ls180.v:7627.6-7627.69" + case 1'1 + assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r + case + end + attribute \src "ls180.v:7631.2-7633.5" + switch \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7631.6-7631.54" + case 1'1 + assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7634.2-7637.5" + switch \main_converter1_reset + attribute \src "ls180.v:7634.6-7634.27" + case 1'1 + assign $0\main_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7638.2-7640.5" + switch $or$ls180.v:7638$2485_Y + attribute \src "ls180.v:7638.6-7638.51" + case 1'1 + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r + case + end + attribute \src "ls180.v:7642.2-7644.5" + switch \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:7642.6-7642.57" + case 1'1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value + case + end + attribute \src "ls180.v:7645.2-7648.5" + switch \main_socbushandler_reset + attribute \src "ls180.v:7645.6-7645.30" + case 1'1 + assign $0\main_socbushandler_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7649.2-7653.5" + switch $ne$ls180.v:7649$2486_Y + attribute \src "ls180.v:7649.6-7649.53" + case 1'1 + attribute \src "ls180.v:7650.3-7652.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7650.7-7650.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7651$2487_Y + case + end + case + end + attribute \src "ls180.v:7655.2-7657.5" + switch $and$ls180.v:7655$2490_Y + attribute \src "ls180.v:7655.6-7655.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7658.2-7666.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7658.6-7658.33" + case 1'1 + attribute \src "ls180.v:7659.3-7663.6" + switch $eq$ls180.v:7659$2491_Y + attribute \src "ls180.v:7659.7-7659.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7661.7-7661.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7662$2492_Y + end + attribute \src "ls180.v:7664.6-7664.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7667.2-7669.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7667.6-7667.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7670.2-7672.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7670.6-7670.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7674.2-7676.5" + switch $and$ls180.v:7674$2494_Y + attribute \src "ls180.v:7674.6-7674.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7678.2-7680.5" + switch $and$ls180.v:7678$2497_Y + attribute \src "ls180.v:7678.6-7678.91" + case 1'1 + assign $0\main_ram_bus_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7683.2-7685.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7683.6-7683.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7686.2-7690.5" + switch $and$ls180.v:7686$2499_Y + attribute \src "ls180.v:7686.6-7686.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7687$2500_Y + attribute \src "ls180.v:7688.6-7688.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7692.2-7698.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7692.6-7692.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7693$2501_Y + attribute \src "ls180.v:7694.3-7697.6" + switch $eq$ls180.v:7694$2502_Y + attribute \src "ls180.v:7694.7-7694.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7699.2-7707.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7699.6-7699.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7701.6-7701.10" + case + attribute \src "ls180.v:7702.3-7706.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7702.7-7702.33" + case 1'1 + attribute \src "ls180.v:7703.4-7705.7" + switch $ne$ls180.v:7703$2503_Y + attribute \src "ls180.v:7703.8-7703.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7704$2504_Y + case + end + case + end + end + attribute \src "ls180.v:7714.2-7720.5" + switch $and$ls180.v:7714$2506_Y + attribute \src "ls180.v:7714.6-7714.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7721.2-7727.5" + switch $eq$ls180.v:7721$2507_Y + attribute \src "ls180.v:7721.6-7721.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7728.2-7735.5" + switch $eq$ls180.v:7728$2508_Y + attribute \src "ls180.v:7728.6-7728.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7736.2-7746.5" + switch $eq$ls180.v:7736$2509_Y + attribute \src "ls180.v:7736.6-7736.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7738.6-7738.10" + case + attribute \src "ls180.v:7739.3-7745.6" + switch $ne$ls180.v:7739$2510_Y + attribute \src "ls180.v:7739.7-7739.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7740$2511_Y + attribute \src "ls180.v:7741.7-7741.11" + case + attribute \src "ls180.v:7742.4-7744.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7742.8-7742.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7748.2-7755.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7748.6-7748.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7750.6-7750.10" + case + attribute \src "ls180.v:7751.3-7754.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7751.7-7751.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7756.2-7758.5" + switch $and$ls180.v:7756$2514_Y + attribute \src "ls180.v:7756.6-7756.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7757$2515_Y + case + end + attribute \src "ls180.v:7759.2-7761.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7759.6-7759.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7760$2516_Y + case + end + attribute \src "ls180.v:7762.2-7770.5" + switch $and$ls180.v:7762$2519_Y + attribute \src "ls180.v:7762.6-7762.191" + case 1'1 + attribute \src "ls180.v:7763.3-7765.6" + switch $not$ls180.v:7763$2520_Y + attribute \src "ls180.v:7763.7-7763.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7764$2521_Y + case + end + attribute \src "ls180.v:7766.6-7766.10" + case + attribute \src "ls180.v:7767.3-7769.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7767.7-7767.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7768$2522_Y + case + end + end + attribute \src "ls180.v:7771.2-7777.5" + switch $or$ls180.v:7771$2524_Y + attribute \src "ls180.v:7771.6-7771.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7778.2-7792.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7778.6-7778.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7780.3-7784.6" + switch 1'0 + attribute \src "ls180.v:7782.7-7782.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7785.6-7785.10" + case + attribute \src "ls180.v:7786.3-7791.6" + switch $not$ls180.v:7786$2525_Y + attribute \src "ls180.v:7786.7-7786.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7787$2526_Y + attribute \src "ls180.v:7788.4-7790.7" + switch $eq$ls180.v:7788$2527_Y + attribute \src "ls180.v:7788.8-7788.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7794.2-7801.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7794.6-7794.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7796.6-7796.10" + case + attribute \src "ls180.v:7797.3-7800.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7797.7-7797.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7802.2-7804.5" + switch $and$ls180.v:7802$2530_Y + attribute \src "ls180.v:7802.6-7802.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7803$2531_Y + case + end + attribute \src "ls180.v:7805.2-7807.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7805.6-7805.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7806$2532_Y + case + end + attribute \src "ls180.v:7808.2-7816.5" + switch $and$ls180.v:7808$2535_Y + attribute \src "ls180.v:7808.6-7808.191" + case 1'1 + attribute \src "ls180.v:7809.3-7811.6" + switch $not$ls180.v:7809$2536_Y + attribute \src "ls180.v:7809.7-7809.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7810$2537_Y + case + end + attribute \src "ls180.v:7812.6-7812.10" + case + attribute \src "ls180.v:7813.3-7815.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7813.7-7813.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7814$2538_Y + case + end + end + attribute \src "ls180.v:7817.2-7823.5" + switch $or$ls180.v:7817$2540_Y + attribute \src "ls180.v:7817.6-7817.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7824.2-7838.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7824.6-7824.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7826.3-7830.6" + switch 1'0 + attribute \src "ls180.v:7828.7-7828.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7831.6-7831.10" + case + attribute \src "ls180.v:7832.3-7837.6" + switch $not$ls180.v:7832$2541_Y + attribute \src "ls180.v:7832.7-7832.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7833$2542_Y + attribute \src "ls180.v:7834.4-7836.7" + switch $eq$ls180.v:7834$2543_Y + attribute \src "ls180.v:7834.8-7834.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7840.2-7847.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7840.6-7840.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7842.6-7842.10" + case + attribute \src "ls180.v:7843.3-7846.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7843.7-7843.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7848.2-7850.5" + switch $and$ls180.v:7848$2546_Y + attribute \src "ls180.v:7848.6-7848.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7849$2547_Y + case + end + attribute \src "ls180.v:7851.2-7853.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7851.6-7851.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7852$2548_Y + case + end + attribute \src "ls180.v:7854.2-7862.5" + switch $and$ls180.v:7854$2551_Y + attribute \src "ls180.v:7854.6-7854.191" + case 1'1 + attribute \src "ls180.v:7855.3-7857.6" + switch $not$ls180.v:7855$2552_Y + attribute \src "ls180.v:7855.7-7855.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7856$2553_Y + case + end + attribute \src "ls180.v:7858.6-7858.10" + case + attribute \src "ls180.v:7859.3-7861.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7859.7-7859.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7860$2554_Y + case + end + end + attribute \src "ls180.v:7863.2-7869.5" + switch $or$ls180.v:7863$2556_Y + attribute \src "ls180.v:7863.6-7863.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7870.2-7884.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7870.6-7870.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7872.3-7876.6" + switch 1'0 + attribute \src "ls180.v:7874.7-7874.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7877.6-7877.10" + case + attribute \src "ls180.v:7878.3-7883.6" + switch $not$ls180.v:7878$2557_Y + attribute \src "ls180.v:7878.7-7878.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7879$2558_Y + attribute \src "ls180.v:7880.4-7882.7" + switch $eq$ls180.v:7880$2559_Y + attribute \src "ls180.v:7880.8-7880.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7886.2-7893.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:7886.6-7886.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:7888.6-7888.10" + case + attribute \src "ls180.v:7889.3-7892.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:7889.7-7889.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7894.2-7896.5" + switch $and$ls180.v:7894$2562_Y + attribute \src "ls180.v:7894.6-7894.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7895$2563_Y + case + end + attribute \src "ls180.v:7897.2-7899.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7897.6-7897.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7898$2564_Y + case + end + attribute \src "ls180.v:7900.2-7908.5" + switch $and$ls180.v:7900$2567_Y + attribute \src "ls180.v:7900.6-7900.191" + case 1'1 + attribute \src "ls180.v:7901.3-7903.6" + switch $not$ls180.v:7901$2568_Y + attribute \src "ls180.v:7901.7-7901.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7902$2569_Y + case + end + attribute \src "ls180.v:7904.6-7904.10" + case + attribute \src "ls180.v:7905.3-7907.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7905.7-7905.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7906$2570_Y + case + end + end + attribute \src "ls180.v:7909.2-7915.5" + switch $or$ls180.v:7909$2572_Y + attribute \src "ls180.v:7909.6-7909.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7916.2-7930.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:7916.6-7916.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7918.3-7922.6" + switch 1'0 + attribute \src "ls180.v:7920.7-7920.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7923.6-7923.10" + case + attribute \src "ls180.v:7924.3-7929.6" + switch $not$ls180.v:7924$2573_Y + attribute \src "ls180.v:7924.7-7924.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7925$2574_Y + attribute \src "ls180.v:7926.4-7928.7" + switch $eq$ls180.v:7926$2575_Y + attribute \src "ls180.v:7926.8-7926.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7932.2-7938.5" + switch $not$ls180.v:7932$2576_Y + attribute \src "ls180.v:7932.6-7932.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:7934.6-7934.10" + case + attribute \src "ls180.v:7935.3-7937.6" + switch $not$ls180.v:7935$2577_Y + attribute \src "ls180.v:7935.7-7935.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7936$2578_Y + case + end + end + attribute \src "ls180.v:7939.2-7945.5" + switch $not$ls180.v:7939$2579_Y + attribute \src "ls180.v:7939.6-7939.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:7941.6-7941.10" + case + attribute \src "ls180.v:7942.3-7944.6" + switch $not$ls180.v:7942$2580_Y + attribute \src "ls180.v:7942.7-7942.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7943$2581_Y + case + end + end + attribute \src "ls180.v:7946.2-8001.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:7946.6-7946.30" + case 1'1 + attribute \src "ls180.v:7947.3-8000.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7949.5-7959.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7949.9-7949.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7951.9-7951.13" + case + attribute \src "ls180.v:7952.6-7958.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7952.10-7952.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7954.10-7954.14" + case + attribute \src "ls180.v:7955.7-7957.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7955.11-7955.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7962.5-7972.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7962.9-7962.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7964.9-7964.13" + case + attribute \src "ls180.v:7965.6-7971.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7965.10-7965.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7967.10-7967.14" + case + attribute \src "ls180.v:7968.7-7970.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7968.11-7968.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7975.5-7985.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7975.9-7975.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7977.9-7977.13" + case + attribute \src "ls180.v:7978.6-7984.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7978.10-7978.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7980.10-7980.14" + case + attribute \src "ls180.v:7981.7-7983.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7981.11-7981.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7988.5-7998.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7988.9-7988.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7990.9-7990.13" + case + attribute \src "ls180.v:7991.6-7997.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7991.10-7991.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7993.10-7993.14" + case + attribute \src "ls180.v:7994.7-7996.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7994.11-7994.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:8002.2-8057.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:8002.6-8002.30" + case 1'1 + attribute \src "ls180.v:8003.3-8056.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:8005.5-8015.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8005.9-8005.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:8007.9-8007.13" + case + attribute \src "ls180.v:8008.6-8014.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8008.10-8008.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:8010.10-8010.14" + case + attribute \src "ls180.v:8011.7-8013.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8011.11-8011.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:8018.5-8028.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8018.9-8018.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:8020.9-8020.13" + case + attribute \src "ls180.v:8021.6-8027.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8021.10-8021.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:8023.10-8023.14" + case + attribute \src "ls180.v:8024.7-8026.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8024.11-8024.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:8031.5-8041.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8031.9-8031.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:8033.9-8033.13" + case + attribute \src "ls180.v:8034.6-8040.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8034.10-8034.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:8036.10-8036.14" + case + attribute \src "ls180.v:8037.7-8039.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8037.11-8037.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:8044.5-8054.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8044.9-8044.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:8046.9-8046.13" + case + attribute \src "ls180.v:8047.6-8053.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8047.10-8047.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:8049.10-8049.14" + case + attribute \src "ls180.v:8050.7-8052.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8050.11-8050.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:8066.2-8080.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:8066.6-8066.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:8068.3-8072.6" + switch 1'1 + attribute \src "ls180.v:8068.7-8068.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:8073.6-8073.10" + case + attribute \src "ls180.v:8074.3-8079.6" + switch $not$ls180.v:8074$2585_Y + attribute \src "ls180.v:8074.7-8074.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8075$2586_Y + attribute \src "ls180.v:8076.4-8078.7" + switch $eq$ls180.v:8076$2587_Y + attribute \src "ls180.v:8076.8-8076.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8081.2-8095.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:8081.6-8081.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:8083.3-8087.6" + switch 1'0 + attribute \src "ls180.v:8085.7-8085.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8088.6-8088.10" + case + attribute \src "ls180.v:8089.3-8094.6" + switch $not$ls180.v:8089$2588_Y + attribute \src "ls180.v:8089.7-8089.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8090$2589_Y + attribute \src "ls180.v:8091.4-8093.7" + switch $eq$ls180.v:8091$2590_Y + attribute \src "ls180.v:8091.8-8091.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8102.2-8104.5" + switch $or$ls180.v:8102$2615_Y + attribute \src "ls180.v:8102.6-8102.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:8106.2-8108.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:8106.6-8106.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:8109.2-8112.5" + switch \main_converter_reset + attribute \src "ls180.v:8109.6-8109.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:8113.2-8123.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:8113.6-8113.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:8116.6-8116.10" + case + attribute \src "ls180.v:8117.3-8119.6" + switch $and$ls180.v:8117$2616_Y + attribute \src "ls180.v:8117.7-8117.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:8120.3-8122.6" + switch $and$ls180.v:8120$2617_Y + attribute \src "ls180.v:8120.7-8120.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:8125.2-8146.5" + switch $and$ls180.v:8125$2621_Y + attribute \src "ls180.v:8125.6-8125.91" + case 1'1 + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\uart_tx[0:0] 1'0 + attribute \src "ls180.v:8130.6-8130.10" + case + attribute \src "ls180.v:8131.3-8145.6" + switch $and$ls180.v:8131$2622_Y + attribute \src "ls180.v:8131.7-8131.60" + case 1'1 + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8132$2623_Y + attribute \src "ls180.v:8133.4-8144.7" + switch $eq$ls180.v:8133$2624_Y + attribute \src "ls180.v:8133.8-8133.43" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + attribute \src "ls180.v:8135.8-8135.12" + case + attribute \src "ls180.v:8136.5-8143.8" + switch $eq$ls180.v:8136$2625_Y + attribute \src "ls180.v:8136.9-8136.44" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:8140.9-8140.13" + case + assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8147.2-8151.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:8147.6-8147.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8148$2626_Y + attribute \src "ls180.v:8149.6-8149.10" + case + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + end + attribute \src "ls180.v:8154.2-8178.5" + switch $not$ls180.v:8154$2627_Y + attribute \src "ls180.v:8154.6-8154.30" + case 1'1 + attribute \src "ls180.v:8155.3-8158.6" + switch $and$ls180.v:8155$2629_Y + attribute \src "ls180.v:8155.7-8155.49" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:8159.6-8159.10" + case + attribute \src "ls180.v:8160.3-8177.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:8160.7-8160.34" + case 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8161$2630_Y + attribute \src "ls180.v:8162.4-8176.7" + switch $eq$ls180.v:8162$2631_Y + attribute \src "ls180.v:8162.8-8162.43" + case 1'1 + attribute \src "ls180.v:8163.5-8165.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:8163.9-8163.25" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:8166.8-8166.12" + case + attribute \src "ls180.v:8167.5-8175.8" + switch $eq$ls180.v:8167$2632_Y + attribute \src "ls180.v:8167.9-8167.44" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:8169.6-8172.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:8169.10-8169.26" + case 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:8173.9-8173.13" + case + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8179.2-8183.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8179.6-8179.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8180$2633_Y + attribute \src "ls180.v:8181.6-8181.10" + case + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:8184.2-8186.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:8184.6-8184.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8188.2-8190.5" + switch $and$ls180.v:8188$2635_Y + attribute \src "ls180.v:8188.6-8188.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8191.2-8193.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:8191.6-8191.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8195.2-8197.5" + switch $and$ls180.v:8195$2637_Y + attribute \src "ls180.v:8195.6-8195.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8198.2-8204.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:8198.6-8198.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8200.6-8200.10" + case + attribute \src "ls180.v:8201.3-8203.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:8201.7-8201.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8205.2-8207.5" + switch $and$ls180.v:8205$2640_Y + attribute \src "ls180.v:8205.6-8205.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8206$2641_Y + case + end + attribute \src "ls180.v:8208.2-8210.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8208.6-8208.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8209$2642_Y + case + end + attribute \src "ls180.v:8211.2-8219.5" + switch $and$ls180.v:8211$2645_Y + attribute \src "ls180.v:8211.6-8211.108" + case 1'1 + attribute \src "ls180.v:8212.3-8214.6" + switch $not$ls180.v:8212$2646_Y + attribute \src "ls180.v:8212.7-8212.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8213$2647_Y + case + end + attribute \src "ls180.v:8215.6-8215.10" + case + attribute \src "ls180.v:8216.3-8218.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8216.7-8216.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8217$2648_Y + case + end + end + attribute \src "ls180.v:8220.2-8226.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8220.6-8220.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8222.6-8222.10" + case + attribute \src "ls180.v:8223.3-8225.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8223.7-8223.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8227.2-8229.5" + switch $and$ls180.v:8227$2651_Y + attribute \src "ls180.v:8227.6-8227.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8228$2652_Y + case + end + attribute \src "ls180.v:8230.2-8232.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8230.6-8230.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8231$2653_Y + case + end + attribute \src "ls180.v:8233.2-8241.5" + switch $and$ls180.v:8233$2656_Y + attribute \src "ls180.v:8233.6-8233.108" + case 1'1 + attribute \src "ls180.v:8234.3-8236.6" + switch $not$ls180.v:8234$2657_Y + attribute \src "ls180.v:8234.7-8234.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8235$2658_Y + case + end + attribute \src "ls180.v:8237.6-8237.10" + case + attribute \src "ls180.v:8238.3-8240.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8238.7-8238.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8239$2659_Y + case + end + end + attribute \src "ls180.v:8242.2-8255.5" + switch \main_uart_reset + attribute \src "ls180.v:8242.6-8242.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8257.2-8264.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8257.6-8257.31" + case 1'1 + assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable + attribute \src "ls180.v:8259.6-8259.10" + case + attribute \src "ls180.v:8260.3-8263.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8260.7-8260.32" + case 1'1 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8266.2-8276.5" + switch \main_spimaster28_mosi_latch + attribute \src "ls180.v:8266.6-8266.33" + case 1'1 + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi + assign $0\main_spimaster34_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8269.6-8269.10" + case + attribute \src "ls180.v:8270.3-8275.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8270.7-8270.32" + case 1'1 + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8274$2664_Y + attribute \src "ls180.v:8271.4-8273.7" + switch \main_spimaster26_cs_enable + attribute \src "ls180.v:8271.8-8271.34" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8277.2-8283.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8277.6-8277.31" + case 1'1 + attribute \src "ls180.v:8278.3-8282.6" + switch \main_spimaster7_loopback + attribute \src "ls180.v:8278.7-8278.31" + case 1'1 + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8280.7-8280.11" + case + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8284.2-8286.5" + switch \main_spimaster29_miso_latch + attribute \src "ls180.v:8284.6-8284.33" + case 1'1 + assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data + case + end + attribute \src "ls180.v:8288.2-8290.5" + switch \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:8288.6-8288.53" + case 1'1 + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8292.2-8299.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8292.6-8292.29" + case 1'1 + assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable + attribute \src "ls180.v:8294.6-8294.10" + case + attribute \src "ls180.v:8295.3-8298.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8295.7-8295.30" + case 1'1 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\spimaster_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8301.2-8311.5" + switch \main_spisdcard_mosi_latch + attribute \src "ls180.v:8301.6-8301.31" + case 1'1 + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi + assign $0\main_spisdcard_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8304.6-8304.10" + case + attribute \src "ls180.v:8305.3-8310.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8305.7-8305.30" + case 1'1 + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8309$2669_Y + attribute \src "ls180.v:8306.4-8308.7" + switch \main_spisdcard_cs_enable + attribute \src "ls180.v:8306.8-8306.32" + case 1'1 + assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8312.2-8318.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8312.6-8312.29" + case 1'1 + attribute \src "ls180.v:8313.3-8317.6" + switch \main_spisdcard_loopback + attribute \src "ls180.v:8313.7-8313.30" + case 1'1 + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } + attribute \src "ls180.v:8315.7-8315.11" + case + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } + end + case + end + attribute \src "ls180.v:8319.2-8321.5" + switch \main_spisdcard_miso_latch + attribute \src "ls180.v:8319.6-8319.31" + case 1'1 + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data + case + end + attribute \src "ls180.v:8323.2-8325.5" + switch \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:8323.6-8323.51" + case 1'1 + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8326.2-8339.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8326.6-8326.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8327$2670_Y + attribute \src "ls180.v:8328.3-8332.6" + switch $lt$ls180.v:8328$2671_Y + attribute \src "ls180.v:8328.7-8328.44" + case 1'1 + assign $0\pwm[1:0] [0] 1'1 + attribute \src "ls180.v:8330.7-8330.11" + case + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8333.3-8335.6" + switch $ge$ls180.v:8333$2673_Y + attribute \src "ls180.v:8333.7-8333.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8336.6-8336.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8340.2-8353.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8340.6-8340.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8341$2674_Y + attribute \src "ls180.v:8342.3-8346.6" + switch $lt$ls180.v:8342$2675_Y + attribute \src "ls180.v:8342.7-8342.44" + case 1'1 + assign $0\pwm[1:0] [1] 1'1 + attribute \src "ls180.v:8344.7-8344.11" + case + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8347.3-8349.6" + switch $ge$ls180.v:8347$2677_Y + attribute \src "ls180.v:8347.7-8347.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8350.6-8350.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8354.2-8356.5" + switch $not$ls180.v:8354$2678_Y + attribute \src "ls180.v:8354.6-8354.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8355$2679_Y + case + end + attribute \src "ls180.v:8360.2-8362.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8360.6-8360.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8364.2-8366.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8364.6-8364.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8367.2-8369.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8367.6-8367.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8368$2680_Y + case + end + attribute \src "ls180.v:8370.2-8372.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8370.6-8370.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8373.2-8380.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8373.6-8373.46" + case 1'1 + attribute \src "ls180.v:8374.3-8379.6" + switch $or$ls180.v:8374$2682_Y + attribute \src "ls180.v:8374.7-8374.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8377.7-8377.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8378$2683_Y + end + case + end + attribute \src "ls180.v:8381.2-8394.5" + switch $and$ls180.v:8381$2684_Y + attribute \src "ls180.v:8381.6-8381.97" + case 1'1 + attribute \src "ls180.v:8382.3-8388.6" + switch $and$ls180.v:8382$2685_Y + attribute \src "ls180.v:8382.7-8382.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8385.7-8385.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8389.6-8389.10" + case + attribute \src "ls180.v:8390.3-8393.6" + switch $and$ls180.v:8390$2686_Y + attribute \src "ls180.v:8390.7-8390.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8391$2687_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8392$2688_Y + case + end + end + attribute \src "ls180.v:8395.2-8422.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8395.6-8395.46" + case 1'1 + attribute \src "ls180.v:8396.3-8421.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8423.2-8425.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8423.6-8423.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8424$2689_Y + case + end + attribute \src "ls180.v:8426.2-8431.5" + switch $or$ls180.v:8426$2691_Y + attribute \src "ls180.v:8426.6-8426.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8432.2-8437.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8432.6-8432.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8439.2-8441.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8439.6-8439.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8442.2-8444.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8442.6-8442.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8445.2-8447.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8445.6-8445.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8448.2-8450.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8448.6-8448.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8449$2692_Y + case + end + attribute \src "ls180.v:8451.2-8453.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8451.6-8451.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8454.2-8461.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8454.6-8454.47" + case 1'1 + attribute \src "ls180.v:8455.3-8460.6" + switch $or$ls180.v:8455$2694_Y + attribute \src "ls180.v:8455.7-8455.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8458.7-8458.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8459$2695_Y + end + case + end + attribute \src "ls180.v:8462.2-8475.5" + switch $and$ls180.v:8462$2696_Y + attribute \src "ls180.v:8462.6-8462.99" + case 1'1 + attribute \src "ls180.v:8463.3-8469.6" + switch $and$ls180.v:8463$2697_Y + attribute \src "ls180.v:8463.7-8463.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8466.7-8466.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8470.6-8470.10" + case + attribute \src "ls180.v:8471.3-8474.6" + switch $and$ls180.v:8471$2698_Y + attribute \src "ls180.v:8471.7-8471.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8472$2699_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8473$2700_Y + case + end + end + attribute \src "ls180.v:8476.2-8503.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8476.6-8476.47" + case 1'1 + attribute \src "ls180.v:8477.3-8502.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8504.2-8506.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8504.6-8504.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8505$2701_Y + case + end + attribute \src "ls180.v:8507.2-8512.5" + switch $or$ls180.v:8507$2703_Y + attribute \src "ls180.v:8507.6-8507.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8513.2-8518.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8513.6-8513.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8520.2-8522.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8520.6-8520.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8524.2-8526.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8524.6-8524.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8527.2-8529.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8527.6-8527.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8528$2704_Y + case + end + attribute \src "ls180.v:8530.2-8532.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8530.6-8530.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8533.2-8540.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8533.6-8533.48" + case 1'1 + attribute \src "ls180.v:8534.3-8539.6" + switch $or$ls180.v:8534$2706_Y + attribute \src "ls180.v:8534.7-8534.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8537.7-8537.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8538$2707_Y + end + case + end + attribute \src "ls180.v:8541.2-8554.5" + switch $and$ls180.v:8541$2708_Y + attribute \src "ls180.v:8541.6-8541.101" + case 1'1 + attribute \src "ls180.v:8542.3-8548.6" + switch $and$ls180.v:8542$2709_Y + attribute \src "ls180.v:8542.7-8542.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8545.7-8545.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8549.6-8549.10" + case + attribute \src "ls180.v:8550.3-8553.6" + switch $and$ls180.v:8550$2710_Y + attribute \src "ls180.v:8550.7-8550.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8551$2711_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8552$2712_Y + case + end + end + attribute \src "ls180.v:8555.2-8564.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8555.6-8555.48" + case 1'1 + attribute \src "ls180.v:8556.3-8563.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8565.2-8567.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8565.6-8565.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8566$2713_Y + case + end + attribute \src "ls180.v:8568.2-8573.5" + switch $or$ls180.v:8568$2715_Y + attribute \src "ls180.v:8568.6-8568.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8574.2-8579.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8574.6-8574.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8581.2-8583.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8581.6-8581.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8584.2-8586.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8584.6-8584.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8587.2-8589.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8587.6-8587.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8590.2-8596.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8590.6-8590.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8592.6-8592.10" + case + attribute \src "ls180.v:8593.3-8595.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8593.7-8593.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8597.2-8603.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8597.6-8597.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8599.6-8599.10" + case + attribute \src "ls180.v:8600.3-8602.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8600.7-8600.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8604.2-8610.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8604.6-8604.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8606.6-8606.10" + case + attribute \src "ls180.v:8607.3-8609.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8607.7-8607.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8611.2-8617.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8611.6-8611.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8613.6-8613.10" + case + attribute \src "ls180.v:8614.3-8616.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8614.7-8614.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8618.2-8624.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8618.6-8618.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8620.6-8620.10" + case + attribute \src "ls180.v:8621.3-8623.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8621.7-8621.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8626.2-8628.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8626.6-8626.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8629.2-8631.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8629.6-8629.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8632.2-8634.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8632.6-8632.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8635.2-8637.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8635.6-8635.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8638.2-8640.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8638.6-8638.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8641.2-8643.5" + switch $and$ls180.v:8641$2716_Y + attribute \src "ls180.v:8641.6-8641.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8644.2-8646.5" + switch $and$ls180.v:8644$2717_Y + attribute \src "ls180.v:8644.6-8644.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8647.2-8649.5" + switch $and$ls180.v:8647$2718_Y + attribute \src "ls180.v:8647.6-8647.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8650.2-8652.5" + switch $and$ls180.v:8650$2719_Y + attribute \src "ls180.v:8650.6-8650.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8653.2-8657.5" + switch $and$ls180.v:8653$2720_Y + attribute \src "ls180.v:8653.6-8653.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8658.2-8662.5" + switch $and$ls180.v:8658$2721_Y + attribute \src "ls180.v:8658.6-8658.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8663.2-8667.5" + switch $and$ls180.v:8663$2722_Y + attribute \src "ls180.v:8663.6-8663.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8668.2-8672.5" + switch $and$ls180.v:8668$2723_Y + attribute \src "ls180.v:8668.6-8668.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8673.2-8681.5" + switch $and$ls180.v:8673$2724_Y + attribute \src "ls180.v:8673.6-8673.83" + case 1'1 + attribute \src "ls180.v:8674.3-8680.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8674.7-8674.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8676.7-8676.11" + case + attribute \src "ls180.v:8677.4-8679.7" + switch $ne$ls180.v:8677$2725_Y + attribute \src "ls180.v:8677.8-8677.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8678$2726_Y + case + end + end + case + end + attribute \src "ls180.v:8682.2-8688.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8682.6-8682.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8684.6-8684.10" + case + attribute \src "ls180.v:8685.3-8687.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8685.7-8685.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8689.2-8695.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8689.6-8689.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8691.6-8691.10" + case + attribute \src "ls180.v:8692.3-8694.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8692.7-8692.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8696.2-8702.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8696.6-8696.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8698.6-8698.10" + case + attribute \src "ls180.v:8699.3-8701.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8699.7-8699.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8703.2-8709.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8703.6-8703.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8705.6-8705.10" + case + attribute \src "ls180.v:8706.3-8708.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8706.7-8706.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8711.2-8713.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8711.6-8711.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8714.2-8716.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8714.6-8714.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8717.2-8719.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8717.6-8717.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8720.2-8722.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8720.6-8720.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8723.2-8725.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8723.6-8723.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8726.2-8728.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8726.6-8726.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8729.2-8731.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8729.6-8729.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8732.2-8734.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8732.6-8732.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8735.2-8737.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8735.6-8735.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8738.2-8740.5" + switch $and$ls180.v:8738$2729_Y + attribute \src "ls180.v:8738.6-8738.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8739$2730_Y + case + end + attribute \src "ls180.v:8741.2-8743.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8741.6-8741.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8742$2731_Y + case + end + attribute \src "ls180.v:8744.2-8752.5" + switch $and$ls180.v:8744$2734_Y + attribute \src "ls180.v:8744.6-8744.120" + case 1'1 + attribute \src "ls180.v:8745.3-8747.6" + switch $not$ls180.v:8745$2735_Y + attribute \src "ls180.v:8745.7-8745.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8746$2736_Y + case + end + attribute \src "ls180.v:8748.6-8748.10" + case + attribute \src "ls180.v:8749.3-8751.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8749.7-8749.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8750$2737_Y + case + end + end + attribute \src "ls180.v:8753.2-8755.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8753.6-8753.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8756.2-8763.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8756.6-8756.42" + case 1'1 + attribute \src "ls180.v:8757.3-8762.6" + switch $or$ls180.v:8757$2739_Y + attribute \src "ls180.v:8757.7-8757.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8760.7-8760.11" + case + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8761$2740_Y + end + case + end + attribute \src "ls180.v:8764.2-8777.5" + switch $and$ls180.v:8764$2741_Y + attribute \src "ls180.v:8764.6-8764.89" + case 1'1 + attribute \src "ls180.v:8765.3-8771.6" + switch $and$ls180.v:8765$2742_Y + attribute \src "ls180.v:8765.7-8765.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8768.7-8768.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8772.6-8772.10" + case + attribute \src "ls180.v:8773.3-8776.6" + switch $and$ls180.v:8773$2743_Y + attribute \src "ls180.v:8773.7-8773.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8774$2744_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8775$2745_Y + case + end + end + attribute \src "ls180.v:8778.2-8805.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8778.6-8778.42" + case 1'1 + attribute \src "ls180.v:8779.3-8804.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8806.2-8808.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8806.6-8806.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8807$2746_Y + case + end + attribute \src "ls180.v:8810.2-8812.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8810.6-8810.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8813.2-8816.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8813.6-8813.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8818.2-8820.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8818.6-8818.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8822.2-8824.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8822.6-8822.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8825.2-8828.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8825.6-8825.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8829.2-8835.5" + switch $and$ls180.v:8829$2747_Y + attribute \src "ls180.v:8829.6-8829.89" + case 1'1 + attribute \src "ls180.v:8830.3-8834.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8830.7-8830.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + attribute \src "ls180.v:8832.7-8832.11" + case + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8833$2748_Y + end + case + end + attribute \src "ls180.v:8836.2-8838.5" + switch $and$ls180.v:8836$2751_Y + attribute \src "ls180.v:8836.6-8836.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8837$2752_Y + case + end + attribute \src "ls180.v:8839.2-8841.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8839.6-8839.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8840$2753_Y + case + end + attribute \src "ls180.v:8842.2-8850.5" + switch $and$ls180.v:8842$2756_Y + attribute \src "ls180.v:8842.6-8842.120" + case 1'1 + attribute \src "ls180.v:8843.3-8845.6" + switch $not$ls180.v:8843$2757_Y + attribute \src "ls180.v:8843.7-8843.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8844$2758_Y + case + end + attribute \src "ls180.v:8846.6-8846.10" + case + attribute \src "ls180.v:8847.3-8849.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8847.7-8847.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8848$2759_Y + case + end + end + attribute \src "ls180.v:8852.2-8854.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8852.6-8852.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8855.2-8857.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8855.6-8855.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8858.2-8860.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8858.6-8858.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8861.2-8957.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8863.4-8879.7" + switch $not$ls180.v:8863$2760_Y + attribute \src "ls180.v:8863.8-8863.29" + case 1'1 + attribute \src "ls180.v:8864.5-8878.8" + switch \builder_request [1] + attribute \src "ls180.v:8864.9-8864.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8866.9-8866.13" + case + attribute \src "ls180.v:8867.6-8877.9" + switch \builder_request [2] + attribute \src "ls180.v:8867.10-8867.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8869.10-8869.14" + case + attribute \src "ls180.v:8870.7-8876.10" + switch \builder_request [3] + attribute \src "ls180.v:8870.11-8870.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8872.11-8872.15" + case + attribute \src "ls180.v:8873.8-8875.11" + switch \builder_request [4] + attribute \src "ls180.v:8873.12-8873.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:8882.4-8898.7" + switch $not$ls180.v:8882$2761_Y + attribute \src "ls180.v:8882.8-8882.29" + case 1'1 + attribute \src "ls180.v:8883.5-8897.8" + switch \builder_request [2] + attribute \src "ls180.v:8883.9-8883.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8885.9-8885.13" + case + attribute \src "ls180.v:8886.6-8896.9" + switch \builder_request [3] + attribute \src "ls180.v:8886.10-8886.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8888.10-8888.14" + case + attribute \src "ls180.v:8889.7-8895.10" + switch \builder_request [4] + attribute \src "ls180.v:8889.11-8889.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8891.11-8891.15" + case + attribute \src "ls180.v:8892.8-8894.11" + switch \builder_request [0] + attribute \src "ls180.v:8892.12-8892.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:8901.4-8917.7" + switch $not$ls180.v:8901$2762_Y + attribute \src "ls180.v:8901.8-8901.29" + case 1'1 + attribute \src "ls180.v:8902.5-8916.8" + switch \builder_request [3] + attribute \src "ls180.v:8902.9-8902.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8904.9-8904.13" + case + attribute \src "ls180.v:8905.6-8915.9" + switch \builder_request [4] + attribute \src "ls180.v:8905.10-8905.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8907.10-8907.14" + case + attribute \src "ls180.v:8908.7-8914.10" + switch \builder_request [0] + attribute \src "ls180.v:8908.11-8908.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8910.11-8910.15" + case + attribute \src "ls180.v:8911.8-8913.11" + switch \builder_request [1] + attribute \src "ls180.v:8911.12-8911.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:8920.4-8936.7" + switch $not$ls180.v:8920$2763_Y + attribute \src "ls180.v:8920.8-8920.29" + case 1'1 + attribute \src "ls180.v:8921.5-8935.8" + switch \builder_request [4] + attribute \src "ls180.v:8921.9-8921.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8923.9-8923.13" + case + attribute \src "ls180.v:8924.6-8934.9" + switch \builder_request [0] + attribute \src "ls180.v:8924.10-8924.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8926.10-8926.14" + case + attribute \src "ls180.v:8927.7-8933.10" + switch \builder_request [1] + attribute \src "ls180.v:8927.11-8927.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8929.11-8929.15" + case + attribute \src "ls180.v:8930.8-8932.11" + switch \builder_request [2] + attribute \src "ls180.v:8930.12-8930.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:8939.4-8955.7" + switch $not$ls180.v:8939$2764_Y + attribute \src "ls180.v:8939.8-8939.29" + case 1'1 + attribute \src "ls180.v:8940.5-8954.8" + switch \builder_request [0] + attribute \src "ls180.v:8940.9-8940.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8942.9-8942.13" + case + attribute \src "ls180.v:8943.6-8953.9" + switch \builder_request [1] + attribute \src "ls180.v:8943.10-8943.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8945.10-8945.14" + case + attribute \src "ls180.v:8946.7-8952.10" + switch \builder_request [2] + attribute \src "ls180.v:8946.11-8946.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8948.11-8948.15" + case + attribute \src "ls180.v:8949.8-8951.11" + switch \builder_request [3] + attribute \src "ls180.v:8949.12-8949.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:8959.2-8965.5" + switch \builder_wait + attribute \src "ls180.v:8959.6-8959.18" + case 1'1 + attribute \src "ls180.v:8960.3-8962.6" + switch $not$ls180.v:8960$2765_Y + attribute \src "ls180.v:8960.7-8960.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:8961$2766_Y + case + end + attribute \src "ls180.v:8963.6-8963.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:8967.2-8997.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:8967.6-8967.26" + case 1'1 + attribute \src "ls180.v:8968.3-8996.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:8998.2-9000.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:8998.6-8998.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:9002.2-9004.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:9002.6-9002.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:9005.2-9007.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:9005.6-9005.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:9008.2-9010.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:9008.6-9008.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:9011.2-9013.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:9011.6-9011.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:9016.2-9037.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:9016.6-9016.26" + case 1'1 + attribute \src "ls180.v:9017.3-9036.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:9038.2-9040.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:9038.6-9038.29" + case 1'1 + assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:9041.2-9043.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:9041.6-9041.29" + case 1'1 + assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:9045.2-9047.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:9045.6-9045.30" + case 1'1 + assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:9048.2-9050.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:9048.6-9048.30" + case 1'1 + assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:9053.2-9062.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:9053.6-9053.26" + case 1'1 + attribute \src "ls180.v:9054.3-9061.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:9063.2-9065.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:9063.6-9063.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:9068.2-9098.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:9068.6-9068.26" + case 1'1 + attribute \src "ls180.v:9069.3-9097.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:9099.2-9101.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:9099.6-9099.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:9103.2-9105.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:9103.6-9103.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:9106.2-9108.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:9106.6-9106.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:9109.2-9111.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:9109.6-9109.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:9112.2-9114.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:9112.6-9112.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:9116.2-9118.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:9116.6-9116.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:9119.2-9121.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:9119.6-9119.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:9122.2-9124.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:9122.6-9122.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:9125.2-9127.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:9125.6-9125.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:9130.2-9160.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:9130.6-9130.26" + case 1'1 + attribute \src "ls180.v:9131.3-9159.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + case + end + case + end + attribute \src "ls180.v:9161.2-9163.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:9161.6-9161.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r + case + end + attribute \src "ls180.v:9165.2-9167.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:9165.6-9165.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r + case + end + attribute \src "ls180.v:9168.2-9170.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:9168.6-9168.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r + case + end + attribute \src "ls180.v:9171.2-9173.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:9171.6-9171.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r + case + end + attribute \src "ls180.v:9174.2-9176.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:9174.6-9174.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r + case + end + attribute \src "ls180.v:9178.2-9180.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:9178.6-9178.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r + case + end + attribute \src "ls180.v:9181.2-9183.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:9181.6-9181.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r + case + end + attribute \src "ls180.v:9184.2-9186.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9184.6-9184.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r + case + end + attribute \src "ls180.v:9187.2-9189.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9187.6-9187.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r + case + end + attribute \src "ls180.v:9192.2-9240.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9192.6-9192.26" + case 1'1 + attribute \src "ls180.v:9193.3-9239.10" + switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:9241.2-9243.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9241.6-9241.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "ls180.v:9244.2-9246.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9244.6-9244.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "ls180.v:9247.2-9249.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9247.6-9247.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "ls180.v:9250.2-9252.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9250.6-9250.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "ls180.v:9253.2-9255.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9253.6-9253.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "ls180.v:9256.2-9258.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9256.6-9256.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "ls180.v:9259.2-9261.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9259.6-9259.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "ls180.v:9262.2-9264.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9262.6-9262.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "ls180.v:9266.2-9268.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9266.6-9266.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "ls180.v:9269.2-9271.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9269.6-9269.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "ls180.v:9272.2-9274.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9272.6-9272.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "ls180.v:9275.2-9277.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9275.6-9275.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "ls180.v:9279.2-9281.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9279.6-9279.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "ls180.v:9283.2-9285.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9283.6-9283.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "ls180.v:9288.2-9390.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9288.6-9288.26" + case 1'1 + attribute \src "ls180.v:9289.3-9389.10" + switch \builder_interface6_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w + case + end + case + end + attribute \src "ls180.v:9391.2-9393.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9391.6-9391.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r + case + end + attribute \src "ls180.v:9394.2-9396.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9394.6-9394.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r + case + end + attribute \src "ls180.v:9397.2-9399.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9397.6-9397.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r + case + end + attribute \src "ls180.v:9400.2-9402.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9400.6-9400.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r + case + end + attribute \src "ls180.v:9404.2-9406.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9404.6-9404.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r + case + end + attribute \src "ls180.v:9407.2-9409.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9407.6-9407.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r + case + end + attribute \src "ls180.v:9410.2-9412.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9410.6-9410.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r + case + end + attribute \src "ls180.v:9413.2-9415.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9413.6-9413.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r + case + end + attribute \src "ls180.v:9417.2-9419.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9417.6-9417.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r + case + end + attribute \src "ls180.v:9420.2-9422.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9420.6-9420.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r + case + end + attribute \src "ls180.v:9424.2-9426.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9424.6-9424.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r + case + end + attribute \src "ls180.v:9427.2-9429.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9427.6-9427.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r + case + end + attribute \src "ls180.v:9430.2-9432.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9430.6-9430.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r + case + end + attribute \src "ls180.v:9433.2-9435.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9433.6-9433.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r + case + end + attribute \src "ls180.v:9438.2-9498.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9438.6-9438.26" + case 1'1 + attribute \src "ls180.v:9439.3-9497.10" + switch \builder_interface7_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9499.2-9501.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9499.6-9499.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r + case + end + attribute \src "ls180.v:9502.2-9504.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9502.6-9502.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r + case + end + attribute \src "ls180.v:9505.2-9507.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9505.6-9505.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r + case + end + attribute \src "ls180.v:9508.2-9510.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9508.6-9508.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r + case + end + attribute \src "ls180.v:9511.2-9513.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9511.6-9511.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + case + end + attribute \src "ls180.v:9514.2-9516.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9514.6-9514.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + case + end + attribute \src "ls180.v:9517.2-9519.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9517.6-9517.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + case + end + attribute \src "ls180.v:9520.2-9522.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9520.6-9520.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + case + end + attribute \src "ls180.v:9524.2-9526.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9524.6-9524.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + case + end + attribute \src "ls180.v:9527.2-9529.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9527.6-9527.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + case + end + attribute \src "ls180.v:9530.2-9532.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9530.6-9530.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + case + end + attribute \src "ls180.v:9533.2-9535.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9533.6-9533.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + case + end + attribute \src "ls180.v:9537.2-9539.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9537.6-9537.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + case + end + attribute \src "ls180.v:9541.2-9543.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9541.6-9541.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + case + end + attribute \src "ls180.v:9546.2-9561.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9546.6-9546.26" + case 1'1 + attribute \src "ls180.v:9547.3-9560.10" + switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9562.2-9564.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9562.6-9562.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + case + end + attribute \src "ls180.v:9565.2-9567.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9565.6-9565.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + case + end + attribute \src "ls180.v:9570.2-9603.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9570.6-9570.26" + case 1'1 + attribute \src "ls180.v:9571.3-9602.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9604.2-9606.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9604.6-9604.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + case + end + attribute \src "ls180.v:9608.2-9610.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9608.6-9608.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9612.2-9614.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9612.6-9612.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9615.2-9617.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9615.6-9615.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9619.2-9621.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9619.6-9619.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9623.2-9625.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9623.6-9623.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9626.2-9628.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9626.6-9626.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9631.2-9655.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9631.6-9631.27" + case 1'1 + attribute \src "ls180.v:9632.3-9654.10" + switch \builder_interface10_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9656.2-9658.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9656.6-9656.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9659.2-9661.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9659.6-9659.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9663.2-9665.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9663.6-9663.32" + case 1'1 + assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9667.2-9669.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9667.6-9667.30" + case 1'1 + assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9671.2-9673.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9671.6-9671.36" + case 1'1 + assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9676.2-9706.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9676.6-9676.27" + case 1'1 + attribute \src "ls180.v:9677.3-9705.10" + switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9707.2-9709.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9707.6-9707.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + case + end + attribute \src "ls180.v:9710.2-9712.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9710.6-9710.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + case + end + attribute \src "ls180.v:9714.2-9716.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9714.6-9714.32" + case 1'1 + assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + case + end + attribute \src "ls180.v:9718.2-9720.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9718.6-9718.30" + case 1'1 + assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + case + end + attribute \src "ls180.v:9722.2-9724.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9722.6-9722.36" + case 1'1 + assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + case + end + attribute \src "ls180.v:9726.2-9728.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9726.6-9726.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + case + end + attribute \src "ls180.v:9729.2-9731.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9729.6-9729.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + case + end + attribute \src "ls180.v:9734.2-9788.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9734.6-9734.27" + case 1'1 + attribute \src "ls180.v:9735.3-9787.10" + switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9789.2-9791.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9789.6-9789.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + case + end + attribute \src "ls180.v:9792.2-9794.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9792.6-9792.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + case + end + attribute \src "ls180.v:9795.2-9797.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9795.6-9795.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + case + end + attribute \src "ls180.v:9798.2-9800.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9798.6-9798.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + case + end + attribute \src "ls180.v:9802.2-9804.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9802.6-9802.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + case + end + attribute \src "ls180.v:9805.2-9807.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9805.6-9805.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + case + end + attribute \src "ls180.v:9808.2-9810.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9808.6-9808.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + case + end + attribute \src "ls180.v:9811.2-9813.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9811.6-9811.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + case + end + attribute \src "ls180.v:9815.2-9817.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9815.6-9815.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + case + end + attribute \src "ls180.v:9819.2-9821.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9819.6-9819.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + case + end + attribute \src "ls180.v:9823.2-9825.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9823.6-9823.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9828.2-9855.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9828.6-9828.27" + case 1'1 + attribute \src "ls180.v:9829.3-9854.10" + switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9856.2-9858.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9856.6-9856.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + case + end + attribute \src "ls180.v:9861.2-9876.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9861.6-9861.27" + case 1'1 + attribute \src "ls180.v:9862.3-9875.10" + switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:9877.2-9879.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:9877.6-9877.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + case + end + attribute \src "ls180.v:9880.2-9882.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:9880.6-9880.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + case + end + attribute \src "ls180.v:9883.2-9885.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:9883.6-9883.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + case + end + attribute \src "ls180.v:9886.2-9888.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:9886.6-9886.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + case + end + attribute \src "ls180.v:9890.2-10185.5" + switch \sys_rst_1 + attribute \src "ls180.v:9890.6-9890.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\pwm[1:0] 2'00 + assign $0\uart_tx[0:0] 1'1 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_ram_bus_ram_bus_ack[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_socbushandler_counter[0:0] 1'0 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 + assign $0\main_spimaster5_miso[7:0] 8'00000000 + assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $0\main_spimaster12_re[0:0] 1'0 + assign $0\main_spimaster17_re[0:0] 1'0 + assign $0\main_spimaster21_storage[0:0] 1'1 + assign $0\main_spimaster22_re[0:0] 1'0 + assign $0\main_spimaster23_storage[0:0] 1'0 + assign $0\main_spimaster24_re[0:0] 1'0 + assign $0\main_spimaster27_count[2:0] 3'000 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 + assign $0\main_spimaster34_mosi_sel[2:0] 3'000 + assign $0\main_spimaster35_miso_data[7:0] 8'00000000 + assign $0\main_spisdcard_miso[7:0] 8'00000000 + assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 + assign $0\main_spisdcard_control_re[0:0] 1'0 + assign $0\main_spisdcard_mosi_re[0:0] 1'0 + assign $0\main_spisdcard_cs_storage[0:0] 1'1 + assign $0\main_spisdcard_cs_re[0:0] 1'0 + assign $0\main_spisdcard_loopback_storage[0:0] 1'0 + assign $0\main_spisdcard_loopback_re[0:0] 1'0 + assign $0\main_spisdcard_count[2:0] 3'000 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 + assign $0\main_spisdcard_mosi_sel[2:0] 3'000 + assign $0\main_spisdcard_miso_data[7:0] 8'00000000 + assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 + assign $0\main_spimaster1_re[0:0] 1'0 + assign $0\main_dummy[23:0] 24'000000000000000000000000 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[9:0] 10'0000000000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \pwm $0\pwm[1:0] + update \uart_tx $0\uart_tx[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_ram_bus_ram_bus_ack $0\main_ram_bus_ram_bus_ack[0:0] + update \main_converter0_counter $0\main_converter0_counter[0:0] + update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] + update \main_converter1_counter $0\main_converter1_counter[0:0] + update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] + update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] + update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] + update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] + update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] + update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] + update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] + update \main_spimaster12_re $0\main_spimaster12_re[0:0] + update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] + update \main_spimaster17_re $0\main_spimaster17_re[0:0] + update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] + update \main_spimaster22_re $0\main_spimaster22_re[0:0] + update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] + update \main_spimaster24_re $0\main_spimaster24_re[0:0] + update \main_spimaster27_count $0\main_spimaster27_count[2:0] + update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] + update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] + update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] + update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] + update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] + update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] + update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] + update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] + update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] + update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] + update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] + update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] + update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] + update \main_spisdcard_count $0\main_spisdcard_count[2:0] + update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] + update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] + update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] + update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] + update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] + update \main_spimaster1_re $0\main_spimaster1_re[0:0] + update \main_dummy $0\main_dummy[23:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[9:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:764.5-764.59" + process $proc$ls180.v:764$3149 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:766.5-766.59" + process $proc$ls180.v:766$3150 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:767.5-767.58" + process $proc$ls180.v:767$3151 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:768.5-768.64" + process $proc$ls180.v:768$3152 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:769.12-769.74" + process $proc$ls180.v:769$3153 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:770.12-770.47" + process $proc$ls180.v:770$3154 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:771.5-771.46" + process $proc$ls180.v:771$3155 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:773.5-773.44" + process $proc$ls180.v:773$3156 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:774.5-774.45" + process $proc$ls180.v:774$3157 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:775.5-775.54" + process $proc$ls180.v:775$3158 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:777.32-777.76" + process $proc$ls180.v:777$3159 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:778.11-778.55" + process $proc$ls180.v:778$3160 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:780.32-780.75" + process $proc$ls180.v:780$3161 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:782.32-782.76" + process $proc$ls180.v:782$3162 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:785.5-785.44" + process $proc$ls180.v:785$3163 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:786.5-786.45" + process $proc$ls180.v:786$3164 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:787.5-787.43" + process $proc$ls180.v:787$3165 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:788.5-788.48" + process $proc$ls180.v:788$3166 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:790.5-790.43" + process $proc$ls180.v:790$3167 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:793.5-793.49" + process $proc$ls180.v:793$3168 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:794.5-794.49" + process $proc$ls180.v:794$3169 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:795.5-795.48" + process $proc$ls180.v:795$3170 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:799.11-799.46" + process $proc$ls180.v:799$3171 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:801.11-801.45" + process $proc$ls180.v:801$3172 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:803.5-803.44" + process $proc$ls180.v:803$3173 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:804.5-804.45" + process $proc$ls180.v:804$3174 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:806.5-806.48" + process $proc$ls180.v:806$3175 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:808.5-808.43" + process $proc$ls180.v:808$3176 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:811.5-811.49" + process $proc$ls180.v:811$3177 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:812.5-812.49" + process $proc$ls180.v:812$3178 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:813.5-813.48" + process $proc$ls180.v:813$3179 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:817.11-817.46" + process $proc$ls180.v:817$3180 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:819.11-819.45" + process $proc$ls180.v:819$3181 + assign { } { } + assign $1\main_sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:821.12-821.36" + process $proc$ls180.v:821$3182 + assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:822.11-822.35" + process $proc$ls180.v:822$3183 + assign { } { } + assign $0\main_sdram_nop_ba[1:0] 2'00 + sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:823.11-823.40" + process $proc$ls180.v:823$3184 + assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:824.5-824.31" + process $proc$ls180.v:824$3185 + assign { } { } + assign $0\main_sdram_steerer0[0:0] 1'1 + sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:825.5-825.31" + process $proc$ls180.v:825$3186 + assign { } { } + assign $0\main_sdram_steerer1[0:0] 1'1 + sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:827.32-827.63" + process $proc$ls180.v:827$3187 + assign { } { } + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:829.32-829.63" + process $proc$ls180.v:829$3188 + assign { } { } + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:831.32-831.63" + process $proc$ls180.v:831$3189 + assign { } { } + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:832.5-832.36" + process $proc$ls180.v:832$3190 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:834.32-834.63" + process $proc$ls180.v:834$3191 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + end + attribute \src "ls180.v:835.11-835.42" + process $proc$ls180.v:835$3192 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:838.5-838.26" + process $proc$ls180.v:838$3193 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] + end + attribute \src "ls180.v:840.11-840.34" + process $proc$ls180.v:840$3194 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] + end + attribute \src "ls180.v:841.5-841.26" + process $proc$ls180.v:841$3195 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] + end + attribute \src "ls180.v:843.11-843.34" + process $proc$ls180.v:843$3196 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] + end + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$2908 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:858.12-858.37" + process $proc$ls180.v:858$3197 + assign { } { } + assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] + end + attribute \src "ls180.v:859.12-859.39" + process $proc$ls180.v:859$3198 + assign { } { } + assign $1\main_wb_sdram_dat_w[31:0] 0 + sync always + sync init + update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$2909 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] + sync init + end + attribute \src "ls180.v:861.11-861.35" + process $proc$ls180.v:861$3199 + assign { } { } + assign $1\main_wb_sdram_sel[3:0] 4'0000 + sync always + sync init + update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + end + attribute \src "ls180.v:862.5-862.29" + process $proc$ls180.v:862$3200 + assign { } { } + assign $1\main_wb_sdram_cyc[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + end + attribute \src "ls180.v:863.5-863.29" + process $proc$ls180.v:863$3201 + assign { } { } + assign $1\main_wb_sdram_stb[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + end + attribute \src "ls180.v:864.5-864.29" + process $proc$ls180.v:864$3202 + assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "ls180.v:865.5-865.28" + process $proc$ls180.v:865$3203 + assign { } { } + assign $1\main_wb_sdram_we[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + end + attribute \src "ls180.v:872.5-872.54" + process $proc$ls180.v:872$3204 + assign { } { } + assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + end + attribute \src "ls180.v:876.5-876.54" + process $proc$ls180.v:876$3205 + assign { } { } + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:877.5-877.35" + process $proc$ls180.v:877$3206 + assign { } { } + assign $1\main_socbushandler_skip[0:0] 1'0 + sync always + sync init + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + end + attribute \src "ls180.v:878.5-878.38" + process $proc$ls180.v:878$3207 + assign { } { } + assign $1\main_socbushandler_counter[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + end + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$2910 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + end + attribute \src "ls180.v:880.12-880.44" + process $proc$ls180.v:880$3208 + assign { } { } + assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] + end + attribute \src "ls180.v:881.12-881.40" + process $proc$ls180.v:881$3209 + assign { } { } + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + end + attribute \src "ls180.v:882.12-882.42" + process $proc$ls180.v:882$3210 + assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:884.11-884.38" + process $proc$ls180.v:884$3211 + assign { } { } + assign $1\main_litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + end + attribute \src "ls180.v:885.5-885.32" + process $proc$ls180.v:885$3212 + assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:886.5-886.32" + process $proc$ls180.v:886$3213 + assign { } { } + assign $1\main_litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + end + attribute \src "ls180.v:888.5-888.31" + process $proc$ls180.v:888$3214 + assign { } { } + assign $1\main_litedram_wb_we[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + end + attribute \src "ls180.v:889.5-889.31" + process $proc$ls180.v:889$3215 + assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$2911 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:890.5-890.34" + process $proc$ls180.v:890$3216 + assign { } { } + assign $1\main_converter_counter[0:0] 1'0 + sync always + sync init + update \main_converter_counter $1\main_converter_counter[0:0] + end + attribute \src "ls180.v:892.12-892.40" + process $proc$ls180.v:892$3217 + assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "ls180.v:893.5-893.29" + process $proc$ls180.v:893$3218 + assign { } { } + assign $1\main_cmd_consumed[0:0] 1'0 + sync always + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] + end + attribute \src "ls180.v:894.5-894.31" + process $proc$ls180.v:894$3219 + assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "ls180.v:898.12-898.47" + process $proc$ls180.v:898$3220 + assign { } { } + assign $1\main_uart_phy_storage[31:0] 9895604 + sync always + sync init + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] + end + attribute \src "ls180.v:899.5-899.28" + process $proc$ls180.v:899$3221 + assign { } { } + assign $1\main_uart_phy_re[0:0] 1'0 + sync always + sync init + update \main_uart_phy_re $1\main_uart_phy_re[0:0] + end + attribute \src "ls180.v:901.5-901.36" + process $proc$ls180.v:901$3222 + assign { } { } + assign $1\main_uart_phy_sink_ready[0:0] 1'0 + sync always + sync init + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] + end + attribute \src "ls180.v:905.5-905.39" + process $proc$ls180.v:905$3223 + assign { } { } + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + end + attribute \src "ls180.v:906.12-906.54" + process $proc$ls180.v:906$3224 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] + end + attribute \src "ls180.v:907.11-907.38" + process $proc$ls180.v:907$3225 + assign { } { } + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + end + attribute \src "ls180.v:908.11-908.43" + process $proc$ls180.v:908$3226 + assign { } { } + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + end + attribute \src "ls180.v:909.5-909.33" + process $proc$ls180.v:909$3227 + assign { } { } + assign $1\main_uart_phy_tx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] + end + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$2912 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:910.5-910.38" + process $proc$ls180.v:910$3228 + assign { } { } + assign $1\main_uart_phy_source_valid[0:0] 1'0 + sync always + sync init + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + end + attribute \src "ls180.v:912.5-912.38" + process $proc$ls180.v:912$3229 + assign { } { } + assign $0\main_uart_phy_source_first[0:0] 1'0 + sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] + sync init + end + attribute \src "ls180.v:913.5-913.37" + process $proc$ls180.v:913$3230 + assign { } { } + assign $0\main_uart_phy_source_last[0:0] 1'0 + sync always + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] + sync init + end + attribute \src "ls180.v:914.11-914.51" + process $proc$ls180.v:914$3231 + assign { } { } + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + end + attribute \src "ls180.v:915.5-915.39" + process $proc$ls180.v:915$3232 + assign { } { } + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + end + attribute \src "ls180.v:916.12-916.54" + process $proc$ls180.v:916$3233 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] + end + attribute \src "ls180.v:918.5-918.30" + process $proc$ls180.v:918$3234 + assign { } { } + assign $1\main_uart_phy_rx_r[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + end + attribute \src "ls180.v:919.11-919.38" + process $proc$ls180.v:919$3235 + assign { } { } + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] + end + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$2913 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:920.11-920.43" + process $proc$ls180.v:920$3236 + assign { } { } + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] + end + attribute \src "ls180.v:921.5-921.33" + process $proc$ls180.v:921$3237 + assign { } { } + assign $1\main_uart_phy_rx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + end + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$2914 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:932.5-932.32" + process $proc$ls180.v:932$3238 + assign { } { } + assign $1\main_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] + end + attribute \src "ls180.v:934.5-934.30" + process $proc$ls180.v:934$3239 + assign { } { } + assign $1\main_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:935.5-935.36" + process $proc$ls180.v:935$3240 + assign { } { } + assign $1\main_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + end + attribute \src "ls180.v:937.5-937.32" + process $proc$ls180.v:937$3241 + assign { } { } + assign $1\main_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + end + attribute \src "ls180.v:939.5-939.30" + process $proc$ls180.v:939$3242 + assign { } { } + assign $1\main_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:940.5-940.36" + process $proc$ls180.v:940$3243 + assign { } { } + assign $1\main_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + end + attribute \src "ls180.v:944.11-944.49" + process $proc$ls180.v:944$3244 + assign { } { } + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:948.11-948.50" + process $proc$ls180.v:948$3245 + assign { } { } + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:949.11-949.48" + process $proc$ls180.v:949$3246 + assign { } { } + assign $1\main_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + end + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$2915 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:950.5-950.37" + process $proc$ls180.v:950$3247 + assign { } { } + assign $1\main_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + end + attribute \src "ls180.v:967.5-967.40" + process $proc$ls180.v:967$3248 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:968.5-968.39" + process $proc$ls180.v:968$3249 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$2916 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + end + attribute \src "ls180.v:976.5-976.38" + process $proc$ls180.v:976$3250 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$2917 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:983.11-983.42" + process $proc$ls180.v:983$3251 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:984.5-984.37" + process $proc$ls180.v:984$3252 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:985.11-985.43" + process $proc$ls180.v:985$3253 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:986.11-986.43" + process $proc$ls180.v:986$3254 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:987.11-987.46" + process $proc$ls180.v:987$3255 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_converter0_reset $not$ls180.v:2848$26_Y + connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } + connect \main_converter1_reset $not$ls180.v:2908$37_Y + connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } + connect \main_socbushandler_reset $not$ls180.v:2968$48_Y + connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [3:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:3044$84_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:3053$87_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \main_ram_adr \main_ram_bus_ram_bus_adr [3:0] + connect \main_ram_bus_ram_bus_dat_r \main_ram_dat_r + connect \main_ram_dat_w \main_ram_bus_ram_bus_dat_w + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3181$119_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3182$120_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3213$121_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3216$122_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3219$124_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3220$126_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3262$128_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3263$129_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3264$130_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3274$135_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3275$137_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3276$139_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3308$147_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3309$148_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3312$149_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3313$150_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3314$152_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3419$158_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3420$159_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3421$160_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3431$165_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3432$167_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3433$169_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3465$177_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3466$178_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3469$179_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3470$180_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3471$182_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3576$188_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3577$189_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3578$190_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3588$195_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3589$197_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3590$199_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3622$207_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3623$208_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3626$209_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3627$210_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3628$212_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3733$218_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3734$219_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3735$220_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3745$225_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3746$227_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3747$229_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3779$237_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3780$238_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3783$239_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3784$240_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3785$242_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3881$253_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3882$259_Y + connect \main_sdram_ras_allowed $and$ls180.v:3883$260_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3884$263_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3886$265_Y + connect \main_sdram_read_available $or$ls180.v:3887$272_Y + connect \main_sdram_write_available $or$ls180.v:3888$279_Y + connect \main_sdram_max_time0 $eq$ls180.v:3889$280_Y + connect \main_sdram_max_time1 $eq$ls180.v:3890$281_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3895$284_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3898$285_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:3931$343_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:4000$429_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:4077$461_Y + connect \builder_roundrobin0_ce $and$ls180.v:4078$464_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:4082$477_Y + connect \builder_roundrobin1_ce $and$ls180.v:4083$480_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:4087$493_Y + connect \builder_roundrobin2_ce $and$ls180.v:4088$496_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:4092$509_Y + connect \builder_roundrobin3_ce $and$ls180.v:4093$512_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:4097$576_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:4119$578_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4179$589_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4184$590_Y + connect \main_port_cmd_last $not$ls180.v:4185$591_Y + connect \main_port_cmd_valid $and$ls180.v:4186$594_Y + connect \main_port_wdata_valid $and$ls180.v:4187$598_Y + connect \main_port_rdata_ready $and$ls180.v:4188$601_Y + connect \main_litedram_wb_ack $and$ls180.v:4189$606_Y + connect \main_ack_cmd $or$ls180.v:4190$608_Y + connect \main_ack_wdata $or$ls180.v:4191$610_Y + connect \main_ack_rdata $and$ls180.v:4192$611_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4205$612_Y + connect \main_uart_txempty_status $not$ls180.v:4206$613_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4212$614_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4218$615_Y + connect \main_uart_rxfull_status $not$ls180.v:4219$616_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4221$618_Y + connect \main_uart_rx_trigger $not$ls180.v:4222$619_Y + connect \main_uart_irq $or$ls180.v:4245$628_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4260$631_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4261$632_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4271$636_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4272$637_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4276$638_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4277$639_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4290$642_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4291$643_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4301$647_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4302$648_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4306$649_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4307$650_Y + connect \main_gpiotristateasic0_pads_i \gpio_i + connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage + connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage + connect \main_gpiotristateasic1_pads_i \gpio_i + connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage + connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage + connect \main_spimaster0_start \main_spimaster9_start + connect \main_spimaster1_length \main_spimaster10_length + connect \main_spimaster4_mosi \main_spimaster16_storage + connect \main_spimaster13_done \main_spimaster2_done + connect \main_spimaster18_status \main_spimaster5_miso + connect \main_spimaster6_cs \main_spimaster21_storage + connect \main_spimaster7_loopback \main_spimaster23_storage + connect \main_spimaster31_clk_rise $eq$ls180.v:4331$654_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4332$656_Y + connect \main_spisdcard_start0 \main_spisdcard_start1 + connect \main_spisdcard_length0 \main_spisdcard_length1 + connect \main_spisdcard_mosi \main_spisdcard_mosi_storage + connect \main_spisdcard_done1 \main_spisdcard_done0 + connect \main_spisdcard_miso_status \main_spisdcard_miso + connect \main_spisdcard_cs \main_spisdcard_cs_storage + connect \main_spisdcard_loopback \main_spisdcard_loopback_storage + connect \main_spisdcard_clk_rise $eq$ls180.v:4389$662_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4390$664_Y + connect \main_spisdcard_clk_divider0 \main_spimaster1_storage + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4446$672_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4447$676_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4448$680_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4449$684_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4450$688_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4471$689_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4501$692_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4624$702_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4625$704_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4642$706_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4644$707_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4645$709_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4751$724_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4752$725_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4769$727_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4771$728_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4772$730_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4885$739_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4886$740_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4903$742_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4905$743_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4906$745_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5022$760_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5026$763_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5026$761_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5027$766_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5027$764_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5028$769_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5028$767_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5029$772_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5029$770_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5030$775_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5030$773_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5031$778_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5031$776_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5032$781_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5032$779_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5033$784_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5033$782_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5034$787_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5034$785_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5035$790_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5035$788_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5036$793_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5036$791_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5037$796_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5037$794_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5038$799_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5038$797_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5039$802_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5039$800_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5040$805_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5040$803_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5041$808_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5041$806_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5042$811_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5042$809_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5043$814_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5043$812_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5044$817_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5044$815_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5045$820_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5045$818_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5046$823_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5046$821_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5047$826_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5047$824_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5048$829_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5048$827_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5049$832_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5049$830_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5050$835_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5050$833_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5051$838_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5051$836_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5052$841_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5052$839_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5053$844_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5053$842_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5054$847_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5054$845_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5055$850_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5055$848_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5056$853_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5056$851_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5057$856_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5057$854_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5058$859_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5058$857_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5059$862_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5059$860_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5060$865_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5060$863_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5061$868_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5061$866_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5062$871_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5062$869_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5063$874_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5063$872_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5064$877_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5064$875_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5065$880_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5065$878_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5075$883_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5076$884_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5078$886_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5079$887_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5081$889_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5082$890_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5084$892_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5085$893_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5086$898_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5086$896_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5086$894_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5087$903_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5087$901_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5087$899_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5096$909_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5096$907_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5096$905_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5097$914_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5097$912_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5097$910_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5106$920_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5106$918_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5106$916_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5107$925_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5107$923_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5107$921_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5116$931_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5116$929_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5116$927_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5117$936_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5117$934_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5117$932_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5213$952_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5223$955_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5233$958_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5243$961_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5268$973_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5268$971_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5268$969_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5269$978_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5269$976_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5269$974_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5278$984_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5278$982_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5278$980_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5279$989_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5279$987_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5279$985_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5288$995_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5288$993_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5288$991_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5289$1000_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5289$998_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5289$996_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5298$1006_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5298$1004_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5298$1002_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5299$1011_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5299$1009_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5299$1007_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5535$1041_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5536$1042_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5539$1043_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5540$1044_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5546$1046_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5548$1047_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 8'11111111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] + connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5558$1048_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] + connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5617$1055_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5698$1063_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5699$1064_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5701$1065_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5702$1066_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5703$1067_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5755$1072_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5756$1073_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5759$1074_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5760$1075_Y + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5811$1081_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5812$1083_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5813$1085_Y + connect \main_interface0_bus_ack $and$ls180.v:5814$1087_Y + connect \main_interface1_bus_ack $and$ls180.v:5815$1089_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5816$1091_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5817$1093_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5818$1095_Y + connect \main_interface0_bus_err $and$ls180.v:5819$1097_Y + connect \main_interface1_bus_err $and$ls180.v:5820$1099_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_ram_bus_ram_bus_adr \builder_shared_adr + connect \main_ram_bus_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_ram_bus_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_ram_bus_ram_bus_stb \builder_shared_stb + connect \main_ram_bus_ram_bus_we \builder_shared_we + connect \main_ram_bus_ram_bus_cti \builder_shared_cti + connect \main_ram_bus_ram_bus_bte \builder_shared_bte + connect \main_interface0_converted_interface_adr \builder_shared_adr + connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_converted_interface_stb \builder_shared_stb + connect \main_interface0_converted_interface_we \builder_shared_we + connect \main_interface0_converted_interface_cti \builder_shared_cti + connect \main_interface0_converted_interface_bte \builder_shared_bte + connect \main_interface1_converted_interface_adr \builder_shared_adr + connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_converted_interface_stb \builder_shared_stb + connect \main_interface1_converted_interface_we \builder_shared_we + connect \main_interface1_converted_interface_cti \builder_shared_cti + connect \main_interface1_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface0_we \builder_shared_we + connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface1_we \builder_shared_we + connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface2_we \builder_shared_we + connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface3_we \builder_shared_we + connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte + connect \main_socbushandler_converted_interface_adr \builder_shared_adr + connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_socbushandler_converted_interface_stb \builder_shared_stb + connect \main_socbushandler_converted_interface_we \builder_shared_we + connect \main_socbushandler_converted_interface_cti \builder_shared_cti + connect \main_socbushandler_converted_interface_bte \builder_shared_bte + connect \builder_libresocsim_converted_interface_adr \builder_shared_adr + connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \builder_libresocsim_converted_interface_stb \builder_shared_stb + connect \builder_libresocsim_converted_interface_we \builder_shared_we + connect \builder_libresocsim_converted_interface_cti \builder_shared_cti + connect \builder_libresocsim_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5905$1111_Y + connect \main_ram_bus_ram_bus_cyc $and$ls180.v:5906$1112_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:5907$1113_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:5908$1114_Y + connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:5909$1115_Y + connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:5910$1116_Y + connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:5911$1117_Y + connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:5912$1118_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:5913$1119_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:5914$1120_Y + connect \builder_shared_err $or$ls180.v:5915$1129_Y + connect \builder_wait $and$ls180.v:5916$1132_Y + connect \builder_done $eq$ls180.v:5929$1162_Y + connect \builder_csrbank0_sel $eq$ls180.v:5930$1163_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:5932$1166_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5933$1170_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:5935$1173_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5936$1177_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:5938$1180_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5939$1184_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:5941$1187_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5942$1191_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:5944$1194_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5945$1198_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5947$1201_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5948$1205_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5950$1208_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5951$1212_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5953$1215_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5954$1219_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5956$1222_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5957$1226_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:5968$1227_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:5970$1230_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5971$1234_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:5973$1237_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5974$1241_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:5976$1244_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5977$1248_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:5979$1251_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5980$1255_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:5982$1258_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5983$1262_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:5985$1265_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5986$1269_Y + connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] + connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] + connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5994$1270_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:5996$1273_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5997$1277_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:5999$1280_Y + connect \builder_csrbank2_r_we $and$ls180.v:6000$1284_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:6008$1285_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:6010$1288_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:6011$1292_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:6013$1295_Y + connect \builder_csrbank3_width3_we $and$ls180.v:6014$1299_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:6016$1302_Y + connect \builder_csrbank3_width2_we $and$ls180.v:6017$1306_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:6019$1309_Y + connect \builder_csrbank3_width1_we $and$ls180.v:6020$1313_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:6022$1316_Y + connect \builder_csrbank3_width0_we $and$ls180.v:6023$1320_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:6025$1323_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6026$1327_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:6028$1330_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6029$1334_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:6031$1337_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6032$1341_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:6034$1344_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6035$1348_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:6045$1349_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:6047$1352_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6048$1356_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:6050$1359_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6051$1363_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:6053$1366_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6054$1370_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:6056$1373_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6057$1377_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:6059$1380_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6060$1384_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:6062$1387_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6063$1391_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:6065$1394_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6066$1398_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:6068$1401_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6069$1405_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:6071$1408_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6072$1412_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:6082$1413_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6084$1416_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6085$1420_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6087$1423_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6088$1427_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6090$1430_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6091$1434_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6093$1437_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6094$1441_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6096$1444_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6097$1448_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6099$1451_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6100$1455_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6102$1458_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6103$1462_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6105$1465_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6106$1469_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6108$1472_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6109$1476_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6111$1479_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6112$1483_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6114$1486_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6115$1490_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6117$1493_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6118$1497_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6120$1500_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6121$1504_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:6123$1507_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6124$1511_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6126$1514_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6127$1518_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:6144$1519_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6146$1522_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6147$1526_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6149$1529_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6150$1533_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6152$1536_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6153$1540_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6155$1543_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6156$1547_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6158$1550_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6159$1554_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6161$1557_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6162$1561_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6164$1564_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6165$1568_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6167$1571_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6168$1575_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:6170$1578_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6171$1582_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6173$1585_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6174$1589_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6176$1592_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6177$1596_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6179$1599_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6180$1603_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6182$1606_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6183$1610_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6185$1613_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6186$1617_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6188$1620_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6189$1624_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6191$1627_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6192$1631_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6194$1634_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6195$1638_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6197$1641_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6198$1645_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6200$1648_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6201$1652_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6203$1655_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6204$1659_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6206$1662_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6207$1666_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6209$1669_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6210$1673_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6212$1676_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6213$1680_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6215$1683_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6216$1687_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6218$1690_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6219$1694_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6221$1697_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6222$1701_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6224$1704_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6225$1708_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6227$1711_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6228$1715_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6230$1718_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6231$1722_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6233$1725_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6234$1729_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6236$1732_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6237$1736_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6239$1739_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6240$1743_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6242$1746_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6243$1750_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6279$1751_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6281$1754_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6282$1758_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6284$1761_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6285$1765_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6287$1768_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6288$1772_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6290$1775_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6291$1779_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6293$1782_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6294$1786_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6296$1789_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6297$1793_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6299$1796_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6300$1800_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6302$1803_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6303$1807_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6305$1810_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6306$1814_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6308$1817_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6309$1821_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6311$1824_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6312$1828_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6314$1831_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6315$1835_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6317$1838_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6318$1842_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6320$1845_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6321$1849_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6323$1852_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6324$1856_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6326$1859_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6327$1863_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6329$1866_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6330$1870_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6332$1873_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6333$1877_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6335$1880_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6336$1884_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6358$1885_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6360$1888_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6361$1892_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6363$1895_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6364$1899_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6366$1902_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6367$1906_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6369$1909_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6370$1913_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6375$1914_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6377$1917_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6378$1921_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6380$1924_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6381$1928_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6383$1931_Y + connect \main_sdram_command_issue_we $and$ls180.v:6384$1935_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6386$1938_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6387$1942_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6389$1945_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6390$1949_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6392$1952_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6393$1956_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6395$1959_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6396$1963_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6398$1966_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6399$1970_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6401$1973_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6402$1977_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6404$1980_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6405$1984_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6420$1985_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6422$1988_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6423$1992_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6425$1995_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6426$1999_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6428$2002_Y + connect \builder_csrbank10_status_we $and$ls180.v:6429$2006_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6431$2009_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6432$2013_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6434$2016_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6435$2020_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6437$2023_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6438$2027_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6440$2030_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6441$2034_Y + connect \main_spimaster10_length \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] + connect \main_spimaster14_status \main_spimaster13_done + connect \builder_csrbank10_status_w \main_spimaster14_status + connect \main_spimaster15_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spimaster16_storage + connect \builder_csrbank10_miso_w \main_spimaster18_status + connect \main_spimaster19_we \builder_csrbank10_miso_we + connect \main_spimaster20_sel \main_spimaster21_storage + connect \builder_csrbank10_cs0_w \main_spimaster21_storage + connect \builder_csrbank10_loopback0_w \main_spimaster23_storage + connect \builder_csrbank11_sel $eq$ls180.v:6460$2036_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6462$2039_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6463$2043_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6465$2046_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6466$2050_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6468$2053_Y + connect \builder_csrbank11_status_we $and$ls180.v:6469$2057_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6471$2060_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6472$2064_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6474$2067_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6475$2071_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6477$2074_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6478$2078_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6480$2081_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6481$2085_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6483$2088_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6484$2092_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6486$2095_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6487$2099_Y + connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] + connect \main_spisdcard_status_status \main_spisdcard_done1 + connect \builder_csrbank11_status_w \main_spisdcard_status_status + connect \main_spisdcard_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage + connect \builder_csrbank11_miso_w \main_spisdcard_miso_status + connect \main_spisdcard_miso_we \builder_csrbank11_miso_we + connect \main_spisdcard_sel \main_spisdcard_cs_storage + connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage + connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage + connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6508$2101_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6510$2104_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6511$2108_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6513$2111_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6514$2115_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6516$2118_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6517$2122_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6519$2125_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6520$2129_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6522$2132_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6523$2136_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6525$2139_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6526$2143_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6528$2146_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6529$2150_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6531$2153_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6532$2157_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6534$2160_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6535$2164_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6537$2167_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6538$2171_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6540$2174_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6541$2178_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6543$2181_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6544$2185_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6546$2188_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6547$2192_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6549$2195_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6550$2199_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6552$2202_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6553$2206_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6555$2209_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6556$2213_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6558$2216_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6559$2220_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6576$2221_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6578$2224_Y + connect \main_uart_rxtx_we $and$ls180.v:6579$2228_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6581$2231_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6582$2235_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6584$2238_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6585$2242_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6587$2245_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6588$2249_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6590$2252_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6591$2256_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6593$2259_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6594$2263_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6596$2266_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6597$2270_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6599$2273_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6600$2277_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6610$2278_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6612$2281_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6613$2285_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6615$2288_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6616$2292_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6618$2295_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6619$2299_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6621$2302_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6622$2306_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6676$2320_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10244$2792_DATA + connect \main_ram_dat_r $memrd$\mem_1$ls180.v:10272$2818_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10290$2825_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10304$2832_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10318$2839_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10332$2846_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10380$2867_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10394$2874_DATA +end +attribute \src "libresoc.v:146562.1-146620.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" +attribute \generator "nMigen" +module \lsd_l + attribute \src "libresoc.v:146563.7-146563.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146608.3-146616.6" + wire $0\q_int$next[0:0]$7149 + attribute \src "libresoc.v:146606.3-146607.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:146608.3-146616.6" + wire $1\q_int$next[0:0]$7150 + attribute \src "libresoc.v:146585.7-146585.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:146598.17-146598.96" + wire $and$libresoc.v:146598$7139_Y + attribute \src "libresoc.v:146603.17-146603.96" + wire $and$libresoc.v:146603$7144_Y + attribute \src "libresoc.v:146600.18-146600.93" + wire $not$libresoc.v:146600$7141_Y + attribute \src "libresoc.v:146602.17-146602.92" + wire $not$libresoc.v:146602$7143_Y + attribute \src "libresoc.v:146605.17-146605.92" + wire $not$libresoc.v:146605$7146_Y + attribute \src "libresoc.v:146599.18-146599.98" + wire $or$libresoc.v:146599$7140_Y + attribute \src "libresoc.v:146601.18-146601.99" + wire $or$libresoc.v:146601$7142_Y + attribute \src "libresoc.v:146604.17-146604.97" + wire $or$libresoc.v:146604$7145_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:146563.7-146563.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:146598$7139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:146598$7139_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:146603$7144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:146603$7144_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 13 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 18 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 \dbus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 12 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 17 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 20 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 \dbus__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 14 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 16 \dbus__sel + attribute \src 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$and$libresoc.v:146808$7157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \x_valid_i + connect \Y $and$libresoc.v:146808$7157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:146811$7160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \$19 + connect \Y $and$libresoc.v:146811$7160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:146816$7165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \x_valid_i + connect \Y $and$libresoc.v:146816$7165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:146825$7174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:146825$7174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:146828$7177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:146828$7177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:146831$7180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:146831$7180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:146833$7182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:146833$7182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:146837$7186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:146837$7186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:146841$7190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:146841$7190_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:146845$7194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:146845$7194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" + cell $not $not$libresoc.v:146846$7195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__we + connect \Y $not$libresoc.v:146846$7195_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:146848$7197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:146848$7197_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:146850$7199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:146850$7199_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146804$7153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:146804$7153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146806$7155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:146806$7155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146807$7156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146807$7156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146809$7158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146809$7158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146812$7161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:146812$7161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146814$7163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:146814$7163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146815$7164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146815$7164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146819$7168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:146819$7168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146822$7171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:146822$7171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146823$7172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146823$7172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146827$7176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:146827$7176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:146829$7178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:146829$7178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146830$7179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146830$7179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146835$7184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146835$7184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:146839$7188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:146839$7188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + cell $or $or$libresoc.v:146851$7200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $or$libresoc.v:146851$7200_Y + end + attribute \src "libresoc.v:146625.7-146625.20" + process $proc$libresoc.v:146625$7267 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146730.14-146730.42" + process $proc$libresoc.v:146730$7268 + assign { } { } + assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__adr $1\dbus__adr[44:0] + end + attribute \src "libresoc.v:146735.7-146735.23" + process $proc$libresoc.v:146735$7269 + assign { } { } + assign $1\dbus__cyc[0:0] 1'0 + sync always + sync init + update \dbus__cyc $1\dbus__cyc[0:0] + end + attribute \src "libresoc.v:146742.14-146742.48" + process $proc$libresoc.v:146742$7270 + assign { } { } + assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__dat_w $1\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:146749.13-146749.30" + process $proc$libresoc.v:146749$7271 + assign { } { } + assign $1\dbus__sel[7:0] 8'00000000 + sync always + sync init + update \dbus__sel $1\dbus__sel[7:0] + end + attribute \src "libresoc.v:146754.7-146754.23" + process $proc$libresoc.v:146754$7272 + assign { } { } + assign $1\dbus__stb[0:0] 1'0 + sync always + sync init + update \dbus__stb $1\dbus__stb[0:0] + end + attribute \src "libresoc.v:146759.7-146759.22" + process $proc$libresoc.v:146759$7273 + assign { } { } + assign $1\dbus__we[0:0] 1'0 + sync always + sync init + update \dbus__we $1\dbus__we[0:0] + end + attribute \src "libresoc.v:146763.14-146763.44" + process $proc$libresoc.v:146763$7274 + assign { } { } + assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \m_badaddr_o $1\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:146770.14-146770.48" + process $proc$libresoc.v:146770$7275 + assign { } { } + assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \m_ld_data_o $1\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:146774.7-146774.26" + process $proc$libresoc.v:146774$7276 + assign { } { } + assign $1\m_load_err_o[0:0] 1'0 + sync always + sync init + update \m_load_err_o $1\m_load_err_o[0:0] + end + attribute \src "libresoc.v:146780.7-146780.27" + process $proc$libresoc.v:146780$7277 + assign { } { } + assign $1\m_store_err_o[0:0] 1'0 + sync always + sync init + update \m_store_err_o $1\m_store_err_o[0:0] + end + attribute \src "libresoc.v:146852.3-146853.39" + process $proc$libresoc.v:146852$7201 + assign { } { } + assign $0\m_badaddr_o[44:0] \m_badaddr_o$next + sync posedge \coresync_clk + update \m_badaddr_o $0\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:146854.3-146855.43" + process $proc$libresoc.v:146854$7202 + assign { } { } + assign $0\m_store_err_o[0:0] \m_store_err_o$next + sync posedge \coresync_clk + update \m_store_err_o $0\m_store_err_o[0:0] + end + attribute \src "libresoc.v:146856.3-146857.41" + process $proc$libresoc.v:146856$7203 + assign { } { } + assign $0\m_load_err_o[0:0] \m_load_err_o$next + sync posedge \coresync_clk + update \m_load_err_o $0\m_load_err_o[0:0] + end + attribute \src "libresoc.v:146858.3-146859.39" + process $proc$libresoc.v:146858$7204 + assign { } { } + assign $0\dbus__dat_w[63:0] \dbus__dat_w$next + sync posedge \coresync_clk + update \dbus__dat_w $0\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:146860.3-146861.33" + process $proc$libresoc.v:146860$7205 + assign { } { } + assign $0\dbus__we[0:0] \dbus__we$next + sync posedge \coresync_clk + update \dbus__we $0\dbus__we[0:0] + end + attribute \src "libresoc.v:146862.3-146863.35" + process $proc$libresoc.v:146862$7206 + assign { } { } + assign $0\dbus__adr[44:0] \dbus__adr$next + sync posedge \coresync_clk + update \dbus__adr $0\dbus__adr[44:0] + end + attribute \src "libresoc.v:146864.3-146865.39" + process $proc$libresoc.v:146864$7207 + assign { } { } + assign $0\m_ld_data_o[63:0] \m_ld_data_o$next + sync posedge \coresync_clk + update \m_ld_data_o $0\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:146866.3-146867.35" + process $proc$libresoc.v:146866$7208 + assign { } { } + assign $0\dbus__sel[7:0] \dbus__sel$next + sync posedge \coresync_clk + update \dbus__sel $0\dbus__sel[7:0] + end + attribute \src "libresoc.v:146868.3-146869.35" + process $proc$libresoc.v:146868$7209 + assign { } { } + assign $0\dbus__stb[0:0] \dbus__stb$next + sync posedge \coresync_clk + update \dbus__stb $0\dbus__stb[0:0] + end + attribute \src "libresoc.v:146870.3-146871.35" + process $proc$libresoc.v:146870$7210 + assign { } { } + assign $0\dbus__cyc[0:0] \dbus__cyc$next + sync posedge \coresync_clk + update \dbus__cyc $0\dbus__cyc[0:0] + end + attribute \src "libresoc.v:146872.3-146899.6" + process $proc$libresoc.v:146872$7211 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__cyc$next[0:0]$7212 $4\dbus__cyc$next[0:0]$7216 + attribute \src "libresoc.v:146873.5-146873.29" + switch \initial + attribute \src "libresoc.v:146873.9-146873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__cyc$next[0:0]$7213 $2\dbus__cyc$next[0:0]$7214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$7 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$7214 $3\dbus__cyc$next[0:0]$7215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$7215 1'0 + case + assign $3\dbus__cyc$next[0:0]$7215 \dbus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__cyc$next[0:0]$7214 1'1 + case + assign $2\dbus__cyc$next[0:0]$7214 \dbus__cyc + end + case + assign $1\dbus__cyc$next[0:0]$7213 \dbus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__cyc$next[0:0]$7216 1'0 + case + assign $4\dbus__cyc$next[0:0]$7216 $1\dbus__cyc$next[0:0]$7213 + end + sync always + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7212 + end + attribute \src "libresoc.v:146900.3-146927.6" + process $proc$libresoc.v:146900$7217 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__stb$next[0:0]$7218 $4\dbus__stb$next[0:0]$7222 + attribute \src "libresoc.v:146901.5-146901.29" + switch \initial + attribute \src "libresoc.v:146901.9-146901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__stb$next[0:0]$7219 $2\dbus__stb$next[0:0]$7220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$21 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__stb$next[0:0]$7220 $3\dbus__stb$next[0:0]$7221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$7221 1'0 + case + assign $3\dbus__stb$next[0:0]$7221 \dbus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__stb$next[0:0]$7220 1'1 + case + assign $2\dbus__stb$next[0:0]$7220 \dbus__stb + end + case + assign $1\dbus__stb$next[0:0]$7219 \dbus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__stb$next[0:0]$7222 1'0 + case + assign $4\dbus__stb$next[0:0]$7222 $1\dbus__stb$next[0:0]$7219 + end + sync always + update \dbus__stb$next $0\dbus__stb$next[0:0]$7218 + end + attribute \src "libresoc.v:146928.3-146937.6" + process $proc$libresoc.v:146928$7223 + assign { } { } + assign { } { } + assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] + attribute \src "libresoc.v:146929.5-146929.29" + switch \initial + attribute \src "libresoc.v:146929.9-146929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_busy_o[0:0] \dbus__cyc + case + assign $1\x_busy_o[0:0] 1'0 + end + sync always + update \x_busy_o $0\x_busy_o[0:0] + end + attribute \src "libresoc.v:146938.3-146955.6" + process $proc$libresoc.v:146938$7224 + assign { } { } + assign { } { } + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "libresoc.v:146939.5-146939.29" + switch \initial + attribute \src "libresoc.v:146939.9-146939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\m_busy_o[0:0] \dbus__cyc + end + case + assign $1\m_busy_o[0:0] 1'0 + end + sync always + update \m_busy_o $0\m_busy_o[0:0] + end + attribute \src "libresoc.v:146956.3-146986.6" + process $proc$libresoc.v:146956$7225 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__sel$next[7:0]$7226 $4\dbus__sel$next[7:0]$7230 + attribute \src "libresoc.v:146957.5-146957.29" + switch \initial + attribute \src "libresoc.v:146957.9-146957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__sel$next[7:0]$7227 $2\dbus__sel$next[7:0]$7228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$35 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__sel$next[7:0]$7228 $3\dbus__sel$next[7:0]$7229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$7229 8'00000000 + case + assign $3\dbus__sel$next[7:0]$7229 \dbus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__sel$next[7:0]$7228 \x_mask_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__sel$next[7:0]$7228 8'00000000 + end + case + assign $1\dbus__sel$next[7:0]$7227 \dbus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__sel$next[7:0]$7230 8'00000000 + case + assign $4\dbus__sel$next[7:0]$7230 $1\dbus__sel$next[7:0]$7227 + end + sync always + update \dbus__sel$next $0\dbus__sel$next[7:0]$7226 + end + attribute \src "libresoc.v:146987.3-147011.6" + process $proc$libresoc.v:146987$7231 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_ld_data_o$next[63:0]$7232 $4\m_ld_data_o$next[63:0]$7236 + attribute \src "libresoc.v:146988.5-146988.29" + switch \initial + attribute \src "libresoc.v:146988.9-146988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_ld_data_o$next[63:0]$7233 $2\m_ld_data_o$next[63:0]$7234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$49 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_ld_data_o$next[63:0]$7234 $3\m_ld_data_o$next[63:0]$7235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$7235 \dbus__dat_r + case + assign $3\m_ld_data_o$next[63:0]$7235 \m_ld_data_o + end + case + assign $2\m_ld_data_o$next[63:0]$7234 \m_ld_data_o + end + case + assign $1\m_ld_data_o$next[63:0]$7233 \m_ld_data_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\m_ld_data_o$next[63:0]$7236 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\m_ld_data_o$next[63:0]$7236 $1\m_ld_data_o$next[63:0]$7233 + end + sync always + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7232 + end + attribute \src "libresoc.v:147012.3-147037.6" + process $proc$libresoc.v:147012$7237 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__adr$next[44:0]$7238 $3\dbus__adr$next[44:0]$7241 + attribute \src "libresoc.v:147013.5-147013.29" + switch \initial + attribute \src "libresoc.v:147013.9-147013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__adr$next[44:0]$7239 $2\dbus__adr$next[44:0]$7240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$63 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__adr$next[44:0]$7240 \dbus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__adr$next[44:0]$7240 \x_addr_i [47:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__adr$next[44:0]$7240 45'000000000000000000000000000000000000000000000 + end + case + assign $1\dbus__adr$next[44:0]$7239 \dbus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__adr$next[44:0]$7241 45'000000000000000000000000000000000000000000000 + case + assign $3\dbus__adr$next[44:0]$7241 $1\dbus__adr$next[44:0]$7239 + end + sync always + update \dbus__adr$next $0\dbus__adr$next[44:0]$7238 + end + attribute \src "libresoc.v:147038.3-147063.6" + process $proc$libresoc.v:147038$7242 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__we$next[0:0]$7243 $3\dbus__we$next[0:0]$7246 + attribute \src "libresoc.v:147039.5-147039.29" + switch \initial + attribute \src "libresoc.v:147039.9-147039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__we$next[0:0]$7244 $2\dbus__we$next[0:0]$7245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$71 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__we$next[0:0]$7245 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__we$next[0:0]$7245 \x_st_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__we$next[0:0]$7245 1'0 + end + case + assign $1\dbus__we$next[0:0]$7244 \dbus__we + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__we$next[0:0]$7246 1'0 + case + assign $3\dbus__we$next[0:0]$7246 $1\dbus__we$next[0:0]$7244 + end + sync always + update \dbus__we$next $0\dbus__we$next[0:0]$7243 + end + attribute \src "libresoc.v:147064.3-147089.6" + process $proc$libresoc.v:147064$7247 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__dat_w$next[63:0]$7248 $3\dbus__dat_w$next[63:0]$7251 + attribute \src "libresoc.v:147065.5-147065.29" + switch \initial + attribute \src "libresoc.v:147065.9-147065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__dat_w$next[63:0]$7249 $2\dbus__dat_w$next[63:0]$7250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$79 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__dat_w$next[63:0]$7250 \dbus__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__dat_w$next[63:0]$7250 \x_st_data_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__dat_w$next[63:0]$7250 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\dbus__dat_w$next[63:0]$7249 \dbus__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__dat_w$next[63:0]$7251 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dbus__dat_w$next[63:0]$7251 $1\dbus__dat_w$next[63:0]$7249 + end + sync always + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7248 + end + attribute \src "libresoc.v:147090.3-147112.6" + process $proc$libresoc.v:147090$7252 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_load_err_o$next[0:0]$7253 $3\m_load_err_o$next[0:0]$7256 + attribute \src "libresoc.v:147091.5-147091.29" + switch \initial + attribute \src "libresoc.v:147091.9-147091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_load_err_o$next[0:0]$7254 $2\m_load_err_o$next[0:0]$7255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$7255 \$85 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_load_err_o$next[0:0]$7255 1'0 + case + assign $2\m_load_err_o$next[0:0]$7255 \m_load_err_o + end + case + assign $1\m_load_err_o$next[0:0]$7254 \m_load_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_load_err_o$next[0:0]$7256 1'0 + case + assign $3\m_load_err_o$next[0:0]$7256 $1\m_load_err_o$next[0:0]$7254 + end + sync always + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7253 + end + attribute \src "libresoc.v:147113.3-147135.6" + process $proc$libresoc.v:147113$7257 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_store_err_o$next[0:0]$7258 $3\m_store_err_o$next[0:0]$7261 + attribute \src "libresoc.v:147114.5-147114.29" + switch \initial + attribute \src "libresoc.v:147114.9-147114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_store_err_o$next[0:0]$7259 $2\m_store_err_o$next[0:0]$7260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$89 \$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$7260 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_store_err_o$next[0:0]$7260 1'0 + case + assign $2\m_store_err_o$next[0:0]$7260 \m_store_err_o + end + case + assign $1\m_store_err_o$next[0:0]$7259 \m_store_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_store_err_o$next[0:0]$7261 1'0 + case + assign $3\m_store_err_o$next[0:0]$7261 $1\m_store_err_o$next[0:0]$7259 + end + sync always + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7258 + end + attribute \src "libresoc.v:147136.3-147155.6" + process $proc$libresoc.v:147136$7262 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_badaddr_o$next[44:0]$7263 $3\m_badaddr_o$next[44:0]$7266 + attribute \src "libresoc.v:147137.5-147137.29" + switch \initial + attribute \src "libresoc.v:147137.9-147137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_badaddr_o$next[44:0]$7264 $2\m_badaddr_o$next[44:0]$7265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$93 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$7265 \dbus__adr + case + assign $2\m_badaddr_o$next[44:0]$7265 \m_badaddr_o + end + case + assign $1\m_badaddr_o$next[44:0]$7264 \m_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_badaddr_o$next[44:0]$7266 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7266 $1\m_badaddr_o$next[44:0]$7264 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7263 + end + connect \$9 $or$libresoc.v:146804$7153_Y + connect \$11 $not$libresoc.v:146805$7154_Y + connect \$13 $or$libresoc.v:146806$7155_Y + connect \$15 $or$libresoc.v:146807$7156_Y + connect \$17 $and$libresoc.v:146808$7157_Y + connect \$1 $or$libresoc.v:146809$7158_Y + connect \$19 $not$libresoc.v:146810$7159_Y + connect \$21 $and$libresoc.v:146811$7160_Y + connect \$23 $or$libresoc.v:146812$7161_Y + connect \$25 $not$libresoc.v:146813$7162_Y + connect \$27 $or$libresoc.v:146814$7163_Y + connect \$29 $or$libresoc.v:146815$7164_Y + connect \$31 $and$libresoc.v:146816$7165_Y + connect \$33 $not$libresoc.v:146817$7166_Y + connect \$35 $and$libresoc.v:146818$7167_Y + connect \$37 $or$libresoc.v:146819$7168_Y + connect \$3 $and$libresoc.v:146820$7169_Y + connect \$39 $not$libresoc.v:146821$7170_Y + connect \$41 $or$libresoc.v:146822$7171_Y + connect \$43 $or$libresoc.v:146823$7172_Y + connect \$45 $and$libresoc.v:146824$7173_Y + connect \$47 $not$libresoc.v:146825$7174_Y + connect \$49 $and$libresoc.v:146826$7175_Y + connect \$51 $or$libresoc.v:146827$7176_Y + connect \$53 $not$libresoc.v:146828$7177_Y + connect \$55 $or$libresoc.v:146829$7178_Y + connect \$57 $or$libresoc.v:146830$7179_Y + connect \$5 $not$libresoc.v:146831$7180_Y + connect \$59 $and$libresoc.v:146832$7181_Y + connect \$61 $not$libresoc.v:146833$7182_Y + connect \$63 $and$libresoc.v:146834$7183_Y + connect \$65 $or$libresoc.v:146835$7184_Y + connect \$67 $and$libresoc.v:146836$7185_Y + connect \$69 $not$libresoc.v:146837$7186_Y + connect \$71 $and$libresoc.v:146838$7187_Y + connect \$73 $or$libresoc.v:146839$7188_Y + connect \$75 $and$libresoc.v:146840$7189_Y + connect \$77 $not$libresoc.v:146841$7190_Y + connect \$7 $and$libresoc.v:146842$7191_Y + connect \$79 $and$libresoc.v:146843$7192_Y + connect \$81 $and$libresoc.v:146844$7193_Y + connect \$83 $not$libresoc.v:146845$7194_Y + connect \$85 $not$libresoc.v:146846$7195_Y + connect \$87 $and$libresoc.v:146847$7196_Y + connect \$89 $not$libresoc.v:146848$7197_Y + connect \$91 $and$libresoc.v:146849$7198_Y + connect \$93 $not$libresoc.v:146850$7199_Y + connect \$95 $or$libresoc.v:146851$7200_Y + connect \x_stall_i 1'0 + connect \m_stall_i 1'0 +end +attribute \src "libresoc.v:147162.1-148123.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" +attribute \generator "nMigen" +module \main + attribute \src "libresoc.v:147695.3-147717.6" + wire width 64 $0\a_i[63:0] + attribute \src "libresoc.v:147794.3-147820.6" + wire $0\a_lt[0:0] + attribute \src "libresoc.v:148075.3-148085.6" + wire width 64 $0\a_n[63:0] + attribute \src "libresoc.v:148045.3-148054.6" + wire width 66 $0\add_a[65:0] + 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\enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire \carry_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 8 \eqs + attribute \src "libresoc.v:147163.7-147163.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" + wire \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire \msb_b + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" + wire width 2 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + wire width 8 \src1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire width 5 \tval + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" + wire \zerohi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" + wire \zerolo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" + cell $add $add$libresoc.v:147660$7314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 67 + connect \A \add_a + connect \B \add_b + connect \Y $add$libresoc.v:147660$7314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:147634$7288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$113 + connect \B \$115 + connect \Y $and$libresoc.v:147634$7288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:147638$7292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$121 + connect \B \$123 + connect \Y $and$libresoc.v:147638$7292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:147671$7325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$69 + connect \Y $and$libresoc.v:147671$7325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:147676$7330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$79 + connect \Y $and$libresoc.v:147676$7330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:147679$7333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$85 + connect \Y $and$libresoc.v:147679$7333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:147682$7336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$91 + connect \Y $and$libresoc.v:147682$7336_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $eq$libresoc.v:147625$7279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:147625$7279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + cell $eq $eq$libresoc.v:147626$7280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 2'10 + connect \Y $eq$libresoc.v:147626$7280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + cell $eq $eq$libresoc.v:147627$7281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:147627$7281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:147639$7293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:147639$7293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:147640$7294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:147640$7294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:147641$7295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:147641$7295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:147642$7296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [31:24] + connect \Y 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"/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $reduce_or $reduce_or$libresoc.v:147665$7319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \Y $reduce_or$libresoc.v:147665$7319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $reduce_or $reduce_or$libresoc.v:147668$7322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \Y $reduce_or$libresoc.v:147668$7322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" + cell $mux $ternary$libresoc.v:147677$7331 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:147677$7331_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + cell $mux $ternary$libresoc.v:147680$7334 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:147680$7334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" + cell $mux $ternary$libresoc.v:147684$7338 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:147684$7338_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:147629$7283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $xor$libresoc.v:147629$7283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:147630$7284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \$109 + connect \Y $xor$libresoc.v:147630$7284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:147631$7285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $xor$libresoc.v:147631$7285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:147632$7286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $xor$libresoc.v:147632$7286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:147635$7289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $xor$libresoc.v:147635$7289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:147636$7290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $xor$libresoc.v:147636$7290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:147662$7316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $xor$libresoc.v:147662$7316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:147663$7317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \rb [32] + connect \Y $xor$libresoc.v:147663$7317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $xor $xor$libresoc.v:147664$7318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $xor$libresoc.v:147664$7318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $xor $xor$libresoc.v:147667$7321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $xor$libresoc.v:147667$7321_Y + end + attribute \src "libresoc.v:147163.7-147163.20" + process $proc$libresoc.v:147163$7368 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:147685.3-147694.6" + process $proc$libresoc.v:147685$7339 + assign { } { } + assign { } { } + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + attribute \src "libresoc.v:147686.5-147686.29" + switch \initial + attribute \src "libresoc.v:147686.9-147686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\is_32bit[0:0] \$24 + case + assign $1\is_32bit[0:0] 1'0 + end + sync always + update \is_32bit $0\is_32bit[0:0] + end + attribute \src "libresoc.v:147695.3-147717.6" + process $proc$libresoc.v:147695$7340 + assign { } { } + assign $0\a_i[63:0] $1\a_i[63:0] + attribute \src "libresoc.v:147696.5-147696.29" + switch \initial + attribute \src "libresoc.v:147696.9-147696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$26 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\a_i[63:0] \ra + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\a_i[63:0] $2\a_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_i[63:0] \ra + end + sync always + update \a_i $0\a_i[63:0] + end + attribute \src "libresoc.v:147718.3-147728.6" + process $proc$libresoc.v:147718$7341 + assign { } { } + assign { } { } + assign $0\zerohi[0:0] $1\zerohi[0:0] + attribute \src "libresoc.v:147719.5-147719.29" + switch \initial + attribute \src "libresoc.v:147719.9-147719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerohi[0:0] \$63 + case + assign $1\zerohi[0:0] 1'0 + end + sync always + update \zerohi $0\zerohi[0:0] + end + attribute \src "libresoc.v:147729.3-147755.6" + process $proc$libresoc.v:147729$7342 + assign { } { } + assign { } { } + assign $0\tval[4:0] $1\tval[4:0] + attribute \src "libresoc.v:147730.5-147730.29" + switch \initial + attribute \src "libresoc.v:147730.9-147730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\tval[4:0] $2\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 + assign $2\tval[4:0] [2] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tval[4:0] $3\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + end + end + case + assign $1\tval[4:0] 5'00000 + end + sync always + update \tval $0\tval[4:0] + end + attribute \src "libresoc.v:147756.3-147774.6" + process $proc$libresoc.v:147756$7343 + assign { } { } + assign { } { } + assign $0\msb_a[0:0] $1\msb_a[0:0] + attribute \src "libresoc.v:147757.5-147757.29" + switch \initial + attribute \src "libresoc.v:147757.9-147757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_a[0:0] $2\msb_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_a[0:0] \$83 + end + case + assign $1\msb_a[0:0] 1'0 + end + sync always + update \msb_a $0\msb_a[0:0] + end + attribute \src "libresoc.v:147775.3-147793.6" + process $proc$libresoc.v:147775$7344 + assign { } { } + assign { } { } + assign $0\msb_b[0:0] $1\msb_b[0:0] + attribute \src "libresoc.v:147776.5-147776.29" + switch \initial + attribute \src "libresoc.v:147776.9-147776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_b[0:0] $2\msb_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_b[0:0] \$89 + end + case + assign $1\msb_b[0:0] 1'0 + end + sync always + update \msb_b $0\msb_b[0:0] + end + attribute \src "libresoc.v:147794.3-147820.6" + process $proc$libresoc.v:147794$7345 + assign { } { } + assign { } { } + assign $0\a_lt[0:0] $1\a_lt[0:0] + attribute \src "libresoc.v:147795.5-147795.29" + switch \initial + attribute \src "libresoc.v:147795.9-147795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_lt[0:0] $2\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_lt[0:0] $3\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\a_lt[0:0] \$97 + end + end + case + assign $1\a_lt[0:0] 1'0 + end + sync always + update \a_lt $0\a_lt[0:0] + end + attribute \src "libresoc.v:147821.3-147846.6" + process $proc$libresoc.v:147821$7346 + assign { } { } + assign { } { } + assign $0\cr_a[3:0] $1\cr_a[3:0] + attribute \src "libresoc.v:147822.5-147822.29" + switch \initial + attribute \src "libresoc.v:147822.9-147822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } + assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a[3:2] \tval [4:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_a[3:2] \tval [1:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a[3:0] { 1'0 \$99 2'00 } + case + assign $1\cr_a[3:0] 4'0000 + end + sync always + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:147847.3-147861.6" + process $proc$libresoc.v:147847$7347 + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + attribute \src "libresoc.v:147848.5-147848.29" + switch \initial + attribute \src "libresoc.v:147848.9-147848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + case + assign $1\cr_a_ok[0:0] 1'0 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:147862.3-147899.6" + process $proc$libresoc.v:147862$7348 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:147863.5-147863.29" + switch \initial + attribute \src "libresoc.v:147863.9-147863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o[63:0] \add_o [64:1] + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign { } { } + assign { } { } + assign $1\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } + case + assign $3\o[63:0] $2\o[63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + case + assign $4\o[63:0] $3\o[63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] [0] \$107 + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:147900.3-147918.6" + process $proc$libresoc.v:147900$7349 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:147901.5-147901.29" + switch \initial + attribute \src "libresoc.v:147901.9-147901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\o_ok[0:0] 1'0 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:147919.3-147932.6" + process $proc$libresoc.v:147919$7350 + assign { } { } + assign { } { } + assign $0\ca[1:0] $1\ca[1:0] + attribute \src "libresoc.v:147920.5-147920.29" + switch \initial + attribute \src "libresoc.v:147920.9-147920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ca[1:0] [0] \add_o [65] + assign $1\ca[1:0] [1] \$111 + case + assign $1\ca[1:0] 2'00 + end + sync always + update \ca $0\ca[1:0] + end + attribute \src "libresoc.v:147933.3-147955.6" + process $proc$libresoc.v:147933$7351 + assign { } { } + assign $0\b_i[63:0] $1\b_i[63:0] + attribute \src "libresoc.v:147934.5-147934.29" + switch \initial + attribute \src "libresoc.v:147934.9-147934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$28 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\b_i[63:0] \rb + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\b_i[63:0] $2\b_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_i[63:0] \rb + end + sync always + update \b_i $0\b_i[63:0] + end + attribute \src "libresoc.v:147956.3-147966.6" + process $proc$libresoc.v:147956$7352 + assign { } { } + assign { } { } + assign $0\xer_ca$20[1:0]$7353 $1\xer_ca$20[1:0]$7354 + attribute \src "libresoc.v:147957.5-147957.29" + switch \initial + attribute \src "libresoc.v:147957.9-147957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca$20[1:0]$7354 \ca + case + assign $1\xer_ca$20[1:0]$7354 2'00 + end + sync always + update \xer_ca$20 $0\xer_ca$20[1:0]$7353 + end + attribute \src "libresoc.v:147967.3-147977.6" + process $proc$libresoc.v:147967$7355 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:147968.5-147968.29" + switch \initial + attribute \src "libresoc.v:147968.9-147968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'1 + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:147978.3-147991.6" + process $proc$libresoc.v:147978$7356 + assign { } { } + assign { } { } + assign $0\ov[1:0] $1\ov[1:0] + attribute \src "libresoc.v:147979.5-147979.29" + switch \initial + attribute \src "libresoc.v:147979.9-147979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ov[1:0] [0] \$119 + assign $1\ov[1:0] [1] \$127 + case + assign $1\ov[1:0] 2'00 + end + sync always + update \ov $0\ov[1:0] + end + attribute \src "libresoc.v:147992.3-148002.6" + process $proc$libresoc.v:147992$7357 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:147993.5-147993.29" + switch \initial + attribute \src "libresoc.v:147993.9-147993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov[1:0] \ov + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:148003.3-148013.6" + process $proc$libresoc.v:148003$7358 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:148004.5-148004.29" + switch \initial + attribute \src "libresoc.v:148004.9-148004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:148014.3-148024.6" + process $proc$libresoc.v:148014$7359 + assign { } { } + assign { } { } + assign $0\src1[7:0] $1\src1[7:0] + attribute \src "libresoc.v:148015.5-148015.29" + switch \initial + attribute \src "libresoc.v:148015.9-148015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\src1[7:0] \ra [7:0] + case + assign $1\src1[7:0] 8'00000000 + end + sync always + update \src1 $0\src1[7:0] + end + attribute \src "libresoc.v:148025.3-148044.6" + process $proc$libresoc.v:148025$7360 + assign { } { } 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 39 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" + wire width 64 \br_imm_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 1 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 13 \br_op__cia$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 15 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \br_op__insn$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire \br_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \fast2_ok + attribute \src "libresoc.v:148546.7-148546.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 27 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $add$libresoc.v:148851$7374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $add$libresoc.v:148851$7374_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + cell $add $add$libresoc.v:148866$7390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:148866$7390_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $and $and$libresoc.v:148858$7381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \$29 + connect \Y $and$libresoc.v:148858$7381_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + cell $and $and$libresoc.v:148859$7382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $and$libresoc.v:148859$7382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $and $and$libresoc.v:148865$7389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [10] + connect \B \$44 + connect \Y $and$libresoc.v:148865$7389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $eq$libresoc.v:148849$7372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $eq$libresoc.v:148849$7372_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $eq $eq$libresoc.v:148852$7375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B \bo [3] + connect \Y $eq$libresoc.v:148852$7375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $eq$libresoc.v:148854$7377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'0 + connect \Y $eq$libresoc.v:148854$7377_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + cell $eq $eq$libresoc.v:148855$7378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'1 + connect \Y $eq$libresoc.v:148855$7378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + cell $eq $eq$libresoc.v:148856$7379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:148856$7379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:148861$7384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $extend$libresoc.v:148861$7384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $not $not$libresoc.v:148857$7380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $not$libresoc.v:148857$7380_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $not $not$libresoc.v:148864$7388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [6] + connect \Y $not$libresoc.v:148864$7388_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $or$libresoc.v:148850$7373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [1] + connect \B \$12 + connect \Y $or$libresoc.v:148850$7373_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $or $or$libresoc.v:148853$7376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \bo [4] + connect \Y $or$libresoc.v:148853$7376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:148861$7385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148861$7384_Y + connect \Y $pos$libresoc.v:148861$7385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $reduce_or $reduce_or$libresoc.v:148862$7386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_n + connect \Y $reduce_or$libresoc.v:148862$7386_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + cell $sub $sub$libresoc.v:148860$7383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $sub$libresoc.v:148860$7383_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $xor $xor$libresoc.v:148863$7387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [1] + connect \B \$40 + connect \Y $xor$libresoc.v:148863$7387_Y + end + attribute \src "libresoc.v:148546.7-148546.20" + process $proc$libresoc.v:148546$7408 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:148867.3-148878.6" + process $proc$libresoc.v:148867$7391 + assign { } { } + assign $0\br_addr[63:0] $1\br_addr[63:0] + attribute \src "libresoc.v:148868.5-148868.29" + switch \initial + attribute \src "libresoc.v:148868.9-148868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\br_addr[63:0] \br_imm_addr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\br_addr[63:0] \$16 [63:0] + end + sync always + update \br_addr $0\br_addr[63:0] + end + attribute \src "libresoc.v:148879.3-148905.6" + process $proc$libresoc.v:148879$7392 + assign { } { } + assign { } { } + assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] + attribute \src "libresoc.v:148880.5-148880.29" + switch \initial + attribute \src "libresoc.v:148880.9-148880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } + end + case + assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \br_imm_addr $0\br_imm_addr[63:0] + end + attribute \src "libresoc.v:148906.3-148924.6" + process $proc$libresoc.v:148906$7393 + assign { } { } + assign { } { } + assign $0\br_taken[0:0] $1\br_taken[0:0] + attribute \src "libresoc.v:148907.5-148907.29" + switch \initial + attribute \src "libresoc.v:148907.9-148907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_taken[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + case + assign $1\br_taken[0:0] 1'0 + end + sync always + update \br_taken $0\br_taken[0:0] + end + attribute \src "libresoc.v:148925.3-148939.6" + process $proc$libresoc.v:148925$7394 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:148926.5-148926.29" + switch \initial + attribute \src "libresoc.v:148926.9-148926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:148940.3-148949.6" + process $proc$libresoc.v:148940$7395 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$7396 $1\fast2$11[63:0]$7397 + attribute \src "libresoc.v:148941.5-148941.29" + switch \initial + attribute \src "libresoc.v:148941.9-148941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2$11[63:0]$7397 \$48 [63:0] + case + assign $1\fast2$11[63:0]$7397 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$7396 + end + attribute \src "libresoc.v:148950.3-148959.6" + process $proc$libresoc.v:148950$7398 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:148951.5-148951.29" + switch \initial + attribute \src "libresoc.v:148951.9-148951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:148960.3-148974.6" + process $proc$libresoc.v:148960$7399 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:148961.5-148961.29" + switch \initial + attribute \src "libresoc.v:148961.9-148961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" + switch \bi + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $1\cr_bit[0:0] \cr_a [0] + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:148975.3-148987.6" + process $proc$libresoc.v:148975$7400 + assign { } { } + assign { } { } + assign $0\ctr_write[0:0] $1\ctr_write[0:0] + attribute \src "libresoc.v:148976.5-148976.29" + switch \initial + attribute \src "libresoc.v:148976.9-148976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_write[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_write[0:0] 1'1 + end + sync always + update \ctr_write $0\ctr_write[0:0] + end + attribute \src "libresoc.v:148988.3-149011.6" + process $proc$libresoc.v:148988$7401 + assign { } { } + assign { } { } + assign $0\bc_taken[0:0] $1\bc_taken[0:0] + attribute \src "libresoc.v:148989.5-148989.29" + switch \initial + attribute \src "libresoc.v:148989.9-148989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\bc_taken[0:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\bc_taken[0:0] $2\bc_taken[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + switch { \$27 \$25 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\bc_taken[0:0] \$31 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\bc_taken[0:0] \$33 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\bc_taken[0:0] \ctr_zero_bo1 + case + assign $2\bc_taken[0:0] 1'0 + end + end + sync always + update \bc_taken $0\bc_taken[0:0] + end + attribute \src "libresoc.v:149012.3-149024.6" + process $proc$libresoc.v:149012$7402 + assign { } { } + assign { } { } + assign $0\ctr_n[63:0] $1\ctr_n[63:0] + attribute \src "libresoc.v:149013.5-149013.29" + switch \initial + attribute \src "libresoc.v:149013.9-149013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_n[63:0] \$35 [63:0] + end + sync always + update \ctr_n $0\ctr_n[63:0] + end + attribute \src "libresoc.v:149025.3-149037.6" + process $proc$libresoc.v:149025$7403 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$7404 $1\fast1$10[63:0]$7405 + attribute \src "libresoc.v:149026.5-149026.29" + switch \initial + attribute \src "libresoc.v:149026.9-149026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\fast1$10[63:0]$7405 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\fast1$10[63:0]$7405 \ctr_n + end + sync always + update \fast1$10 $0\fast1$10[63:0]$7404 + end + attribute \src "libresoc.v:149038.3-149058.6" + process $proc$libresoc.v:149038$7406 + assign { } { } + assign { } { } + assign $0\ctr_m[63:0] $1\ctr_m[63:0] + attribute \src "libresoc.v:149039.5-149039.29" + switch \initial + attribute \src "libresoc.v:149039.9-149039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_m[63:0] $2\ctr_m[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" + switch \br_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ctr_m[63:0] \$38 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ctr_m[63:0] \fast1 + end + end + sync always + update \ctr_m $0\ctr_m[63:0] + end + attribute \src "libresoc.v:149059.3-149071.6" + process $proc$libresoc.v:149059$7407 + assign { } { } + assign { } { } + assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:149060.5-149060.29" + switch \initial + attribute \src "libresoc.v:149060.9-149060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_zero_bo1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_zero_bo1[0:0] \$42 + end + sync always + update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] + end + connect \$12 $eq$libresoc.v:148849$7372_Y + connect \$14 $or$libresoc.v:148850$7373_Y + connect \$17 $add$libresoc.v:148851$7374_Y + connect \$19 $eq$libresoc.v:148852$7375_Y + connect \$21 $or$libresoc.v:148853$7376_Y + connect \$23 $eq$libresoc.v:148854$7377_Y + connect \$25 $eq$libresoc.v:148855$7378_Y + connect \$27 $eq$libresoc.v:148856$7379_Y + connect \$29 $not$libresoc.v:148857$7380_Y + connect \$31 $and$libresoc.v:148858$7381_Y + connect \$33 $and$libresoc.v:148859$7382_Y + connect \$36 $sub$libresoc.v:148860$7383_Y + connect \$38 $pos$libresoc.v:148861$7385_Y + connect \$40 $reduce_or$libresoc.v:148862$7386_Y + connect \$42 $xor$libresoc.v:148863$7387_Y + connect \$44 $not$libresoc.v:148864$7388_Y + connect \$46 $and$libresoc.v:148865$7389_Y + connect \$49 $add$libresoc.v:148866$7390_Y + connect \$16 \$17 + connect \$35 \$36 + connect \$48 \$49 + connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \muxid$1 \muxid + connect \nia_ok \br_taken + connect \nia \br_addr + connect \bi \br_op__insn [17:16] + connect \bo \br_op__insn [25:21] +end +attribute \src "libresoc.v:149085.1-150035.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" +attribute \generator "nMigen" +module \main$38 + attribute \src "libresoc.v:150000.3-150011.6" + wire width 64 $0\a[63:0] + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 16 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \trap_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 15 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 9 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 23 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" + cell $add $add$libresoc.v:149474$7425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:149474$7425_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $and $and$libresoc.v:149468$7418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $and$libresoc.v:149468$7418_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + cell $and $and$libresoc.v:149476$7427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $and$libresoc.v:149476$7427_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + cell $and $and$libresoc.v:149478$7429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $and$libresoc.v:149478$7429_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + cell $and $and$libresoc.v:149480$7431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $and$libresoc.v:149480$7431_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:149482$7433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:149482$7433_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + cell $and $and$libresoc.v:149484$7435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 8'10000000 + connect \Y $and$libresoc.v:149484$7435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:149486$7437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:149486$7437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $and $and$libresoc.v:149492$7444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:149492$7444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $and $and$libresoc.v:149497$7449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:149497$7449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" + cell $eq $eq$libresoc.v:149467$7417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $eq$libresoc.v:149467$7417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + cell $eq $eq$libresoc.v:149475$7426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $eq$libresoc.v:149475$7426_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + cell $eq $eq$libresoc.v:149489$7441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $eq$libresoc.v:149489$7441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" + cell $eq $eq$libresoc.v:149490$7442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:149490$7442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $eq $eq$libresoc.v:149491$7443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:149491$7443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + cell $eq $eq$libresoc.v:149495$7447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:149495$7447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $eq $eq$libresoc.v:149496$7448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:149496$7448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:149461$7409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $extend$libresoc.v:149461$7409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:149462$7411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $extend$libresoc.v:149462$7411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $extend$libresoc.v:149473$7423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A \$36 + connect \Y $extend$libresoc.v:149473$7423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:149488$7439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $extend$libresoc.v:149488$7439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $gt $gt$libresoc.v:149464$7414 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $gt$libresoc.v:149464$7414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $gt $gt$libresoc.v:149466$7416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $gt$libresoc.v:149466$7416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $lt $lt$libresoc.v:149463$7413 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $lt$libresoc.v:149463$7413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $lt $lt$libresoc.v:149465$7415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $lt$libresoc.v:149465$7415_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + cell $not $not$libresoc.v:149493$7445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $not$libresoc.v:149493$7445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + cell $not $not$libresoc.v:149494$7446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $not$libresoc.v:149494$7446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $or $or$libresoc.v:149471$7421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$31 + connect \Y $or$libresoc.v:149471$7421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:149461$7410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:149461$7409_Y + connect \Y $pos$libresoc.v:149461$7410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:149462$7412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:149462$7411_Y + connect \Y $pos$libresoc.v:149462$7412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $pos$libresoc.v:149473$7424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:149473$7423_Y + connect \Y $pos$libresoc.v:149473$7424_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:149488$7440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:149488$7439_Y + connect \Y $pos$libresoc.v:149488$7440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:149469$7419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $reduce_or$libresoc.v:149469$7419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:149470$7420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $reduce_or$libresoc.v:149470$7420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:149477$7428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \Y $reduce_or$libresoc.v:149477$7428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:149479$7430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \Y $reduce_or$libresoc.v:149479$7430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:149481$7432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \Y $reduce_or$libresoc.v:149481$7432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:149483$7434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \Y $reduce_or$libresoc.v:149483$7434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:149485$7436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $reduce_or$libresoc.v:149485$7436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:149487$7438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$72 + connect \Y $reduce_or$libresoc.v:149487$7438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $sshl $sshl$libresoc.v:149472$7422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $sshl$libresoc.v:149472$7422_Y + end + attribute \src "libresoc.v:149086.7-149086.20" + process $proc$libresoc.v:149086$7510 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:149498.3-149509.6" + process $proc$libresoc.v:149498$7450 + assign { } { } + assign $0\a_s[63:0] $1\a_s[63:0] + attribute \src "libresoc.v:149499.5-149499.29" + switch \initial + attribute \src "libresoc.v:149499.9-149499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_s[63:0] \ra + end + sync always + update \a_s $0\a_s[63:0] + end + attribute \src "libresoc.v:149510.3-149541.6" + process $proc$libresoc.v:149510$7451 + assign { } { } + assign { } { } + assign $0\nia[63:0] $1\nia[63:0] + attribute \src "libresoc.v:149511.5-149511.29" + switch \initial + attribute \src "libresoc.v:149511.9-149511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia[63:0] $2\nia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia[63:0] \$35 + case + assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + case + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:149542.3-149573.6" + process $proc$libresoc.v:149542$7452 + assign { } { } + assign { } { } + assign $0\nia_ok[0:0] $1\nia_ok[0:0] + attribute \src "libresoc.v:149543.5-149543.29" + switch \initial + attribute \src "libresoc.v:149543.9-149543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia_ok[0:0] $2\nia_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok[0:0] 1'1 + case + assign $2\nia_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + case + assign $1\nia_ok[0:0] 1'0 + end + sync always + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:149574.3-149605.6" + process $proc$libresoc.v:149574$7453 + assign { } { } + assign { } { } + assign $0\fast1$11[63:0]$7454 $1\fast1$11[63:0]$7455 + attribute \src "libresoc.v:149575.5-149575.29" + switch \initial + attribute \src "libresoc.v:149575.9-149575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1$11[63:0]$7455 $2\fast1$11[63:0]$7456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1$11[63:0]$7456 \trap_op__cia + case + assign $2\fast1$11[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1$11[63:0]$7455 \$39 [63:0] + case + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$11 $0\fast1$11[63:0]$7454 + end + attribute \src "libresoc.v:149606.3-149637.6" + process $proc$libresoc.v:149606$7457 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:149607.5-149607.29" + switch \initial + attribute \src "libresoc.v:149607.9-149607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1_ok[0:0] 1'1 + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:149638.3-149720.6" + process $proc$libresoc.v:149638$7458 + assign { } { } + assign { } { } + assign $0\fast2$12[63:0]$7459 $1\fast2$12[63:0]$7460 + attribute \src "libresoc.v:149639.5-149639.29" + switch \initial + attribute \src "libresoc.v:149639.9-149639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2$12[63:0]$7460 $2\fast2$12[63:0]$7461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { $2\fast2$12[63:0]$7461 [29] $2\fast2$12[63:0]$7461 [27] $2\fast2$12[63:0]$7461 [21] } 3'000 + assign $2\fast2$12[63:0]$7461 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7461 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7461 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7461 [17] $3\fast2$12[17:17]$7462 + assign { } { } + assign $2\fast2$12[63:0]$7461 [20] $5\fast2$12[20:20]$7464 + assign $2\fast2$12[63:0]$7461 [16] $6\fast2$12[16:16]$7465 + assign $2\fast2$12[63:0]$7461 [18] $7\fast2$12[19:18]$7466 [0] + assign $2\fast2$12[63:0]$7461 [28] $8\fast2$12[28:28]$7467 + assign $2\fast2$12[63:0]$7461 [30] $9\fast2$12[30:30]$7468 + assign $2\fast2$12[63:0]$7461 [19] $10\fast2$12[19:19]$7469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fast2$12[17:17]$7462 1'1 + case + assign $3\fast2$12[17:17]$7462 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fast2$12[18:18]$7463 1'1 + case + assign $4\fast2$12[18:18]$7463 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fast2$12[20:20]$7464 1'1 + case + assign $5\fast2$12[20:20]$7464 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fast2$12[16:16]$7465 1'1 + case + assign $6\fast2$12[16:16]$7465 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$56 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $9\fast2$12[30:30]$7468 \trapexc_$signal + assign $8\fast2$12[28:28]$7467 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7466 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7466 [0] \trapexc_$signal$62 + case + assign $7\fast2$12[19:18]$7466 { 1'0 $4\fast2$12[18:18]$7463 } + assign $8\fast2$12[28:28]$7467 1'0 + assign $9\fast2$12[30:30]$7468 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fast2$12[19:19]$7469 1'1 + case + assign $10\fast2$12[19:19]$7469 $7\fast2$12[19:18]$7466 [1] + end + case + assign $2\fast2$12[63:0]$7461 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { $1\fast2$12[63:0]$7460 [30:27] $1\fast2$12[63:0]$7460 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7460 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7460 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7460 [63:31] \trap_op__msr [63:31] + case + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$12 $0\fast2$12[63:0]$7459 + end + attribute \src "libresoc.v:149721.3-149752.6" + process $proc$libresoc.v:149721$7470 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:149722.5-149722.29" + switch \initial + attribute \src "libresoc.v:149722.9-149722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:149753.3-149780.6" + process $proc$libresoc.v:149753$7471 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trapexc_$signal[0:0]$7472 $1\trapexc_$signal[0:0]$7480 + assign $0\trapexc_$signal$60[0:0]$7473 $1\trapexc_$signal$60[0:0]$7481 + assign $0\trapexc_$signal$61[0:0]$7474 $1\trapexc_$signal$61[0:0]$7482 + assign $0\trapexc_$signal$62[0:0]$7475 $1\trapexc_$signal$62[0:0]$7483 + assign $0\trapexc_$signal$67[0:0]$7476 $1\trapexc_$signal$67[0:0]$7484 + assign $0\trapexc_$signal$68[0:0]$7477 $1\trapexc_$signal$68[0:0]$7485 + assign $0\trapexc_$signal$69[0:0]$7478 $1\trapexc_$signal$69[0:0]$7486 + assign $0\trapexc_$signal$70[0:0]$7479 $1\trapexc_$signal$70[0:0]$7487 + attribute \src "libresoc.v:149754.5-149754.29" + switch \initial + attribute \src "libresoc.v:149754.9-149754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\trapexc_$signal[0:0]$7480 $2\trapexc_$signal[0:0]$7488 + assign $1\trapexc_$signal$60[0:0]$7481 $2\trapexc_$signal$60[0:0]$7489 + assign $1\trapexc_$signal$61[0:0]$7482 $2\trapexc_$signal$61[0:0]$7490 + assign $1\trapexc_$signal$62[0:0]$7483 $2\trapexc_$signal$62[0:0]$7491 + assign $1\trapexc_$signal$67[0:0]$7484 $2\trapexc_$signal$67[0:0]$7492 + assign $1\trapexc_$signal$68[0:0]$7485 $2\trapexc_$signal$68[0:0]$7493 + assign $1\trapexc_$signal$69[0:0]$7486 $2\trapexc_$signal$69[0:0]$7494 + assign $1\trapexc_$signal$70[0:0]$7487 $2\trapexc_$signal$70[0:0]$7495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\trapexc_$signal[0:0]$7488 $3\trapexc_$signal[0:0]$7496 + assign $2\trapexc_$signal$60[0:0]$7489 $3\trapexc_$signal$60[0:0]$7497 + assign $2\trapexc_$signal$61[0:0]$7490 $3\trapexc_$signal$61[0:0]$7498 + assign $2\trapexc_$signal$62[0:0]$7491 $3\trapexc_$signal$62[0:0]$7499 + assign $2\trapexc_$signal$67[0:0]$7492 $3\trapexc_$signal$67[0:0]$7500 + assign $2\trapexc_$signal$68[0:0]$7493 $3\trapexc_$signal$68[0:0]$7501 + assign $2\trapexc_$signal$69[0:0]$7494 $3\trapexc_$signal$69[0:0]$7502 + assign $2\trapexc_$signal$70[0:0]$7495 $3\trapexc_$signal$70[0:0]$7503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\trapexc_$signal$70[0:0]$7503 $3\trapexc_$signal$62[0:0]$7499 $3\trapexc_$signal$60[0:0]$7497 $3\trapexc_$signal$61[0:0]$7498 $3\trapexc_$signal[0:0]$7496 $3\trapexc_$signal$69[0:0]$7502 $3\trapexc_$signal$68[0:0]$7501 $3\trapexc_$signal$67[0:0]$7500 } \trap_op__ldst_exc + case + assign $3\trapexc_$signal[0:0]$7496 1'0 + assign $3\trapexc_$signal$60[0:0]$7497 1'0 + assign $3\trapexc_$signal$61[0:0]$7498 1'0 + assign $3\trapexc_$signal$62[0:0]$7499 1'0 + assign $3\trapexc_$signal$67[0:0]$7500 1'0 + assign $3\trapexc_$signal$68[0:0]$7501 1'0 + assign $3\trapexc_$signal$69[0:0]$7502 1'0 + assign $3\trapexc_$signal$70[0:0]$7503 1'0 + end + case + assign $2\trapexc_$signal[0:0]$7488 1'0 + assign $2\trapexc_$signal$60[0:0]$7489 1'0 + assign $2\trapexc_$signal$61[0:0]$7490 1'0 + assign $2\trapexc_$signal$62[0:0]$7491 1'0 + assign $2\trapexc_$signal$67[0:0]$7492 1'0 + assign $2\trapexc_$signal$68[0:0]$7493 1'0 + assign $2\trapexc_$signal$69[0:0]$7494 1'0 + assign $2\trapexc_$signal$70[0:0]$7495 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7480 1'0 + assign $1\trapexc_$signal$60[0:0]$7481 1'0 + assign $1\trapexc_$signal$61[0:0]$7482 1'0 + assign $1\trapexc_$signal$62[0:0]$7483 1'0 + assign $1\trapexc_$signal$67[0:0]$7484 1'0 + assign $1\trapexc_$signal$68[0:0]$7485 1'0 + assign $1\trapexc_$signal$69[0:0]$7486 1'0 + assign $1\trapexc_$signal$70[0:0]$7487 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7472 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7473 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7474 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7475 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7476 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7477 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7478 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7479 + end + attribute \src "libresoc.v:149781.3-149792.6" + process $proc$libresoc.v:149781$7504 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "libresoc.v:149782.5-149782.29" + switch \initial + attribute \src "libresoc.v:149782.9-149782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_s[63:0] \rb + end + sync always + update \b_s $0\b_s[63:0] + end + attribute \src "libresoc.v:149793.3-149961.6" + process $proc$libresoc.v:149793$7505 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr[63:0] $1\msr[63:0] + assign $0\msr_ok[0:0] $1\msr_ok[0:0] + attribute \src "libresoc.v:149794.5-149794.29" + switch \initial + attribute \src "libresoc.v:149794.9-149794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign $1\msr[63:0] $2\msr[63:0] + assign $1\msr_ok[0:0] $2\msr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $2\msr[63:0] [63] 1'1 + assign $2\msr[63:0] [15] 1'0 + assign $2\msr[63:0] [14] 1'0 + assign $2\msr[63:0] [5] 1'0 + assign $2\msr[63:0] [4] 1'0 + assign $2\msr[63:0] [1] 1'0 + assign $2\msr[63:0] [0] 1'1 + assign $2\msr[63:0] [11] 1'0 + assign $2\msr[63:0] [8] 1'0 + assign $2\msr[63:0] [23] 1'0 + assign $2\msr[63:0] [32] 1'0 + assign $2\msr[63:0] [25] 1'0 + assign $2\msr[63:0] [13] 1'0 + assign $2\msr[63:0] [3] 1'0 + assign $2\msr[63:0] [10] 1'0 + assign $2\msr[63:0] [9] 1'0 + assign $2\msr[63:0] [58] 1'0 + assign $2\msr_ok[0:0] 1'1 + case + assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign { } { } + assign { } { } + assign $1\msr[63:0] [0] \$75 [0] + assign $1\msr[63:0] [11:1] $3\msr[11:1] + assign $1\msr[63:0] [59:13] $4\msr[59:13] + assign $1\msr[63:0] [63:61] $5\msr[63:61] + assign $1\msr[63:0] [12] $12\msr[12:12] + assign $1\msr[63:0] [60] $13\msr[60:60] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" + switch \trap_op__insn [21] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\msr[11:1] [10:1] \$75 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } + assign $5\msr[63:61] \$75 [63:61] + assign $3\msr[11:1] [0] \ra [1] + assign $4\msr[59:13] [2] \ra [15] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } + assign $5\msr[63:61] $8\msr[63:61] + assign $3\msr[11:1] [4:3] $10\msr[5:4] + assign $4\msr[59:13] [2] $11\msr[15:15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $6\msr[11:1] \ra [11:1] + assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } + assign $8\msr[63:61] \ra [63:61] + assign $7\msr[59:13] [21:19] $9\msr[34:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\msr[34:32] \trap_op__msr [34:32] + case + assign $9\msr[34:32] \ra [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\msr[59:13] [46:19] \$75 [59:32] + assign $8\msr[63:61] \$75 [63:61] + assign $6\msr[11:1] \ra [11:1] + assign $7\msr[59:13] [18:0] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch $7\msr[59:13] [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $11\msr[15:15] 1'1 + assign $10\msr[5:4] [1] 1'1 + assign $10\msr[5:4] [0] 1'1 + case + assign $10\msr[5:4] $6\msr[11:1] [4:3] + assign $11\msr[15:15] $7\msr[59:13] [2] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $13\msr[60:60] \trap_op__msr [60] + assign $12\msr[12:12] \trap_op__msr [12] + case + assign $12\msr[12:12] \$75 [12] + assign $13\msr[60:60] \$75 [60] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 + assign { } { } + assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } + assign $1\msr[63:0] [26:22] \fast2 [26:22] + assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } + assign $1\msr[63:0] [12] $14\msr[12:12] + assign $1\msr[63:0] [5:4] $16\msr[5:4] + assign $1\msr[63:0] [15] $17\msr[15:15] + assign $1\msr[63:0] [34:32] $18\msr[34:32] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\msr[12:12] $15\msr[12:12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" + switch \trap_op__msr [60] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\msr[12:12] \fast2 [12] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $15\msr[12:12] \trap_op__msr [12] + end + case + assign $14\msr[12:12] \fast2 [12] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch \fast2 [14] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $17\msr[15:15] 1'1 + assign $16\msr[5:4] [1] 1'1 + assign $16\msr[5:4] [0] 1'1 + case + assign $16\msr[5:4] \fast2 [5:4] + assign $17\msr[15:15] \fast2 [15] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\msr[34:32] \trap_op__msr [34:32] + case + assign $18\msr[34:32] \fast2 [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { } { } + assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $1\msr[63:0] [63] 1'1 + assign $1\msr[63:0] [15] 1'0 + assign $1\msr[63:0] [14] 1'0 + assign $1\msr[63:0] [5] 1'0 + assign $1\msr[63:0] [4] 1'0 + assign $1\msr[63:0] [1] 1'0 + assign $1\msr[63:0] [0] 1'1 + assign $1\msr[63:0] [11] 1'0 + assign $1\msr[63:0] [8] 1'0 + assign $1\msr[63:0] [23] 1'0 + assign $1\msr[63:0] [32] 1'0 + assign $1\msr[63:0] [25] 1'0 + assign $1\msr[63:0] [13] 1'0 + assign $1\msr[63:0] [3] 1'0 + assign $1\msr[63:0] [10] 1'0 + assign $1\msr[63:0] [9] 1'0 + assign $1\msr[63:0] [58] 1'0 + assign $1\msr_ok[0:0] 1'1 + case + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + end + sync always + update \msr $0\msr[63:0] + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:149962.3-149980.6" + process $proc$libresoc.v:149962$7506 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:149963.5-149963.29" + switch \initial + attribute \src "libresoc.v:149963.9-149963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o[63:0] \trap_op__msr + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:149981.3-149999.6" + process $proc$libresoc.v:149981$7507 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:149982.5-149982.29" + switch \initial + attribute \src "libresoc.v:149982.9-149982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:150000.3-150011.6" + process $proc$libresoc.v:150000$7508 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:150001.5-150001.29" + switch \initial + attribute \src "libresoc.v:150001.9-150001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$13 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:150012.3-150023.6" + process $proc$libresoc.v:150012$7509 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:150013.5-150013.29" + switch \initial + attribute \src "libresoc.v:150013.9-150013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$15 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$13 $pos$libresoc.v:149461$7410_Y + connect \$15 $pos$libresoc.v:149462$7412_Y + connect \$17 $lt$libresoc.v:149463$7413_Y + connect \$19 $gt$libresoc.v:149464$7414_Y + connect \$21 $lt$libresoc.v:149465$7415_Y + connect \$23 $gt$libresoc.v:149466$7416_Y + connect \$25 $eq$libresoc.v:149467$7417_Y + connect \$28 $and$libresoc.v:149468$7418_Y + connect \$27 $reduce_or$libresoc.v:149469$7419_Y + connect \$31 $reduce_or$libresoc.v:149470$7420_Y + connect \$33 $or$libresoc.v:149471$7421_Y + connect \$36 $sshl$libresoc.v:149472$7422_Y + connect \$35 $pos$libresoc.v:149473$7424_Y + connect \$40 $add$libresoc.v:149474$7425_Y + connect \$42 $eq$libresoc.v:149475$7426_Y + connect \$45 $and$libresoc.v:149476$7427_Y + connect \$44 $reduce_or$libresoc.v:149477$7428_Y + connect \$49 $and$libresoc.v:149478$7429_Y + connect \$48 $reduce_or$libresoc.v:149479$7430_Y + connect \$53 $and$libresoc.v:149480$7431_Y + connect \$52 $reduce_or$libresoc.v:149481$7432_Y + connect \$57 $and$libresoc.v:149482$7433_Y + connect \$56 $reduce_or$libresoc.v:149483$7434_Y + connect \$64 $and$libresoc.v:149484$7435_Y + connect \$63 $reduce_or$libresoc.v:149485$7436_Y + connect \$72 $and$libresoc.v:149486$7437_Y + connect \$71 $reduce_or$libresoc.v:149487$7438_Y + connect \$75 $pos$libresoc.v:149488$7440_Y + connect \$77 $eq$libresoc.v:149489$7441_Y + connect \$79 $eq$libresoc.v:149490$7442_Y + connect \$81 $eq$libresoc.v:149491$7443_Y + connect \$83 $and$libresoc.v:149492$7444_Y + connect \$85 $not$libresoc.v:149493$7445_Y + connect \$87 $not$libresoc.v:149494$7446_Y + connect \$89 $eq$libresoc.v:149495$7447_Y + connect \$91 $eq$libresoc.v:149496$7448_Y + connect \$93 $and$libresoc.v:149497$7449_Y + connect \$39 \$40 + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid + connect \should_trap \$33 + connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } + connect \equal \$25 + connect \gt_u \$23 + connect \lt_u \$21 + connect \gt_s \$19 + connect \lt_s \$17 + connect \to \trap_op__insn [25:21] +end +attribute \src "libresoc.v:150039.1-150788.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" +attribute \generator "nMigen" +module \main$51 + attribute \src "libresoc.v:150755.3-150765.6" + wire width 32 $0\a32[31:0] + attribute \src "libresoc.v:150700.3-150710.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:150678.3-150688.6" + wire width 64 $0\bpermd_rb[63:0] + attribute \src "libresoc.v:150667.3-150677.6" + wire width 64 $0\bpermd_rs[63:0] + attribute \src "libresoc.v:150656.3-150666.6" + wire width 64 $0\clz_sig_in[63:0] + attribute \src "libresoc.v:150766.3-150784.6" + wire width 64 $0\cntz_i[63:0] + attribute \src "libresoc.v:150744.3-150754.6" + wire $0\count_right[0:0] + attribute \src "libresoc.v:150040.7-150040.20" + wire $0\initial[0:0] + attribute \src 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\enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute 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"OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 41 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $and$libresoc.v:150548$7557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $and$libresoc.v:150548$7557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150507$7511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150507$7511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150508$7512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150508$7512_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150509$7513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150509$7513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150510$7514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150510$7514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150511$7515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150511$7515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150512$7516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150512$7516_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150513$7517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150513$7517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150514$7518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150514$7518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150515$7519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150515$7519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150516$7520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150516$7520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150517$7521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150517$7521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150518$7522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:150518$7522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150519$7523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150519$7523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150520$7524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150520$7524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150521$7525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150521$7525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150522$7526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150522$7526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150523$7527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150523$7527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150524$7528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150524$7528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150525$7529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150525$7529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150526$7530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:150526$7530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150527$7531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150527$7531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150528$7532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150528$7532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150529$7533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150529$7533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150530$7534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150530$7534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150531$7535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150531$7535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150532$7536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150532$7536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150533$7537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150533$7537_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150534$7538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:150534$7538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + cell $eq $eq$libresoc.v:150535$7539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__data_len [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:150535$7539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150551$7560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150551$7560_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150552$7561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150552$7561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150553$7562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150553$7562_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150554$7563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150554$7563_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150555$7564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150555$7564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150556$7565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150556$7565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150557$7566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150557$7566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150558$7567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:150558$7567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150559$7568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150559$7568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150560$7569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150560$7569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150561$7570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150561$7570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150562$7571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150562$7571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150563$7572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150563$7572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150564$7573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150564$7573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150565$7574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150565$7574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150566$7575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:150566$7575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150567$7576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150567$7576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150568$7577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150568$7577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150569$7578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150569$7578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150570$7579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150570$7579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150571$7580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150571$7580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150572$7581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150572$7581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150573$7582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150573$7582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150574$7583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:150574$7583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150575$7584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150575$7584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150576$7585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150576$7585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150577$7586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150577$7586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150578$7587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150578$7587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150579$7588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150579$7588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150580$7589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150580$7589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150581$7590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150581$7590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150582$7591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:150582$7591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150583$7592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150583$7592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150584$7593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150584$7593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150585$7594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150585$7594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:150586$7595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:150586$7595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $extend$libresoc.v:150537$7541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A \$158 + connect \Y $extend$libresoc.v:150537$7541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $extend$libresoc.v:150539$7544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $extend$libresoc.v:150539$7544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $extend$libresoc.v:150541$7547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \$166 + connect \Y $extend$libresoc.v:150541$7547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:150542$7549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $extend$libresoc.v:150542$7549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $extend$libresoc.v:150546$7554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$176 + connect \Y $extend$libresoc.v:150546$7554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $or$libresoc.v:150549$7558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $or$libresoc.v:150549$7558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $pos$libresoc.v:150537$7542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:150537$7541_Y + connect \Y $pos$libresoc.v:150537$7542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $pos$libresoc.v:150539$7545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:150539$7544_Y + connect \Y $pos$libresoc.v:150539$7545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $pos$libresoc.v:150541$7548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:150541$7547_Y + connect \Y $pos$libresoc.v:150541$7548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:150542$7550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:150542$7549_Y + connect \Y $pos$libresoc.v:150542$7550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $pos$libresoc.v:150546$7555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:150546$7554_Y + connect \Y $pos$libresoc.v:150546$7555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $reduce_xor$libresoc.v:150543$7551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $reduce_xor$libresoc.v:150543$7551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $reduce_xor$libresoc.v:150544$7552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $reduce_xor$libresoc.v:150544$7552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $sub$libresoc.v:150538$7543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $sub$libresoc.v:150538$7543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $ternary$libresoc.v:150540$7546 + parameter \WIDTH 8 + connect \A \$164 + connect \B \$162 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:150540$7546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $ternary$libresoc.v:150545$7553 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $ternary$libresoc.v:150545$7553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $ternary$libresoc.v:150547$7556 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $ternary$libresoc.v:150547$7556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $xor$libresoc.v:150536$7540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $xor$libresoc.v:150536$7540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $xor$libresoc.v:150550$7559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $xor$libresoc.v:150550$7559_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150587.10-150591.4" + cell \bpermd \bpermd + connect \ra \bpermd_ra + connect \rb \bpermd_rb + connect \rs \bpermd_rs + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150592.7-150595.4" + cell \clz \clz + connect \lz \clz_lz + connect \sig_in \clz_sig_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150596.12-150600.4" + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o + end + attribute \src "libresoc.v:150040.7-150040.20" + process $proc$libresoc.v:150040$7608 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:150601.3-150655.6" + process $proc$libresoc.v:150601$7596 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:150602.5-150602.29" + switch \initial + attribute \src "libresoc.v:150602.9-150602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$25 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \popcount_o + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch \$155 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] \$157 + attribute \src "libresoc.v:0.0-0.0" + case + assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 + assign $2\o[63:0] [0] \par0 + assign $2\o[63:0] [32] \par1 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$161 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \bpermd_ra + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:150656.3-150666.6" + process $proc$libresoc.v:150656$7597 + assign { } { } + assign { } { } + assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] + attribute \src "libresoc.v:150657.5-150657.29" + switch \initial + attribute \src "libresoc.v:150657.9-150657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\clz_sig_in[63:0] \cntz_i + case + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \clz_sig_in $0\clz_sig_in[63:0] + end + attribute \src "libresoc.v:150667.3-150677.6" + process $proc$libresoc.v:150667$7598 + assign { } { } + assign { } { } + assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] + attribute \src "libresoc.v:150668.5-150668.29" + switch \initial + attribute \src "libresoc.v:150668.9-150668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rs[63:0] \ra + case + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rs $0\bpermd_rs[63:0] + end + attribute \src "libresoc.v:150678.3-150688.6" + process $proc$libresoc.v:150678$7599 + assign { } { } + assign { } { } + assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] + attribute \src "libresoc.v:150679.5-150679.29" + switch \initial + attribute \src "libresoc.v:150679.9-150679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rb[63:0] \rb + case + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rb $0\bpermd_rb[63:0] + end + attribute \src "libresoc.v:150689.3-150699.6" + process $proc$libresoc.v:150689$7600 + assign { } { } + assign { } { } + assign $0\popcount_a[63:0] $1\popcount_a[63:0] + attribute \src "libresoc.v:150690.5-150690.29" + switch \initial + attribute \src "libresoc.v:150690.9-150690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_a[63:0] \ra + case + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_a $0\popcount_a[63:0] + end + attribute \src "libresoc.v:150700.3-150710.6" + process $proc$libresoc.v:150700$7601 + assign { } { } + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:150701.5-150701.29" + switch \initial + attribute \src "libresoc.v:150701.9-150701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\b[63:0] \rb + case + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \b $0\b[63:0] + end + attribute \src "libresoc.v:150711.3-150721.6" + process $proc$libresoc.v:150711$7602 + assign { } { } + assign { } { } + assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] + attribute \src "libresoc.v:150712.5-150712.29" + switch \initial + attribute \src "libresoc.v:150712.9-150712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_data_len[63:0] \$169 + case + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_data_len $0\popcount_data_len[63:0] + end + attribute \src "libresoc.v:150722.3-150732.6" + process $proc$libresoc.v:150722$7603 + assign { } { } + assign { } { } + assign $0\par0[0:0] $1\par0[0:0] + attribute \src "libresoc.v:150723.5-150723.29" + switch \initial + attribute \src "libresoc.v:150723.9-150723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par0[0:0] \$171 + case + assign $1\par0[0:0] 1'0 + end + sync always + update \par0 $0\par0[0:0] + end + attribute \src "libresoc.v:150733.3-150743.6" + process $proc$libresoc.v:150733$7604 + assign { } { } + assign { } { } + assign $0\par1[0:0] $1\par1[0:0] + attribute \src "libresoc.v:150734.5-150734.29" + switch \initial + attribute \src "libresoc.v:150734.9-150734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par1[0:0] \$173 + case + assign $1\par1[0:0] 1'0 + end + sync always + update \par1 $0\par1[0:0] + end + attribute \src "libresoc.v:150744.3-150754.6" + process $proc$libresoc.v:150744$7605 + assign { } { } + assign { } { } + assign $0\count_right[0:0] $1\count_right[0:0] + attribute \src "libresoc.v:150745.5-150745.29" + switch \initial + attribute \src "libresoc.v:150745.9-150745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\count_right[0:0] \logical_op__insn [10] + case + assign $1\count_right[0:0] 1'0 + end + sync always + update \count_right $0\count_right[0:0] + end + attribute \src "libresoc.v:150755.3-150765.6" + process $proc$libresoc.v:150755$7606 + assign { } { } + assign { } { } + assign $0\a32[31:0] $1\a32[31:0] + attribute \src "libresoc.v:150756.5-150756.29" + switch \initial + attribute \src "libresoc.v:150756.9-150756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\a32[31:0] \ra [31:0] + case + assign $1\a32[31:0] 0 + end + sync always + update \a32 $0\a32[31:0] + end + attribute \src "libresoc.v:150766.3-150784.6" + process $proc$libresoc.v:150766$7607 + assign { } { } + assign { } { } + assign $0\cntz_i[63:0] $1\cntz_i[63:0] + attribute \src "libresoc.v:150767.5-150767.29" + switch \initial + attribute \src "libresoc.v:150767.9-150767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\cntz_i[63:0] $2\cntz_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cntz_i[63:0] \$175 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cntz_i[63:0] \$179 + end + case + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cntz_i $0\cntz_i[63:0] + end + connect \$99 $eq$libresoc.v:150507$7511_Y + connect \$101 $eq$libresoc.v:150508$7512_Y + connect \$103 $eq$libresoc.v:150509$7513_Y + connect \$105 $eq$libresoc.v:150510$7514_Y + connect \$107 $eq$libresoc.v:150511$7515_Y + connect \$109 $eq$libresoc.v:150512$7516_Y + connect \$111 $eq$libresoc.v:150513$7517_Y + connect \$113 $eq$libresoc.v:150514$7518_Y + connect \$115 $eq$libresoc.v:150515$7519_Y + connect \$117 $eq$libresoc.v:150516$7520_Y + connect \$119 $eq$libresoc.v:150517$7521_Y + connect \$121 $eq$libresoc.v:150518$7522_Y + connect \$123 $eq$libresoc.v:150519$7523_Y + connect \$125 $eq$libresoc.v:150520$7524_Y + connect \$127 $eq$libresoc.v:150521$7525_Y + connect \$129 $eq$libresoc.v:150522$7526_Y + connect \$131 $eq$libresoc.v:150523$7527_Y + connect \$133 $eq$libresoc.v:150524$7528_Y + connect \$135 $eq$libresoc.v:150525$7529_Y + connect \$137 $eq$libresoc.v:150526$7530_Y + connect \$139 $eq$libresoc.v:150527$7531_Y + connect \$141 $eq$libresoc.v:150528$7532_Y + connect \$143 $eq$libresoc.v:150529$7533_Y + connect \$145 $eq$libresoc.v:150530$7534_Y + connect \$147 $eq$libresoc.v:150531$7535_Y + connect \$149 $eq$libresoc.v:150532$7536_Y + connect \$151 $eq$libresoc.v:150533$7537_Y + connect \$153 $eq$libresoc.v:150534$7538_Y + connect \$155 $eq$libresoc.v:150535$7539_Y + connect \$158 $xor$libresoc.v:150536$7540_Y + connect \$157 $pos$libresoc.v:150537$7542_Y + connect \$162 $sub$libresoc.v:150538$7543_Y + connect \$164 $pos$libresoc.v:150539$7545_Y + connect \$166 $ternary$libresoc.v:150540$7546_Y + connect \$161 $pos$libresoc.v:150541$7548_Y + connect \$169 $pos$libresoc.v:150542$7550_Y + connect \$171 $reduce_xor$libresoc.v:150543$7551_Y + connect \$173 $reduce_xor$libresoc.v:150544$7552_Y + connect \$176 $ternary$libresoc.v:150545$7553_Y + connect \$175 $pos$libresoc.v:150546$7555_Y + connect \$179 $ternary$libresoc.v:150547$7556_Y + connect \$21 $and$libresoc.v:150548$7557_Y + connect \$23 $or$libresoc.v:150549$7558_Y + connect \$25 $xor$libresoc.v:150550$7559_Y + connect \$27 $eq$libresoc.v:150551$7560_Y + connect \$29 $eq$libresoc.v:150552$7561_Y + connect \$31 $eq$libresoc.v:150553$7562_Y + connect \$33 $eq$libresoc.v:150554$7563_Y + connect \$35 $eq$libresoc.v:150555$7564_Y + connect \$37 $eq$libresoc.v:150556$7565_Y + connect \$39 $eq$libresoc.v:150557$7566_Y + connect \$41 $eq$libresoc.v:150558$7567_Y + connect \$43 $eq$libresoc.v:150559$7568_Y + connect \$45 $eq$libresoc.v:150560$7569_Y + connect \$47 $eq$libresoc.v:150561$7570_Y + connect \$49 $eq$libresoc.v:150562$7571_Y + connect \$51 $eq$libresoc.v:150563$7572_Y + connect \$53 $eq$libresoc.v:150564$7573_Y + connect \$55 $eq$libresoc.v:150565$7574_Y + connect \$57 $eq$libresoc.v:150566$7575_Y + connect \$59 $eq$libresoc.v:150567$7576_Y + connect \$61 $eq$libresoc.v:150568$7577_Y + connect \$63 $eq$libresoc.v:150569$7578_Y + connect \$65 $eq$libresoc.v:150570$7579_Y + connect \$67 $eq$libresoc.v:150571$7580_Y + connect \$69 $eq$libresoc.v:150572$7581_Y + connect \$71 $eq$libresoc.v:150573$7582_Y + connect \$73 $eq$libresoc.v:150574$7583_Y + connect \$75 $eq$libresoc.v:150575$7584_Y + connect \$77 $eq$libresoc.v:150576$7585_Y + connect \$79 $eq$libresoc.v:150577$7586_Y + connect \$81 $eq$libresoc.v:150578$7587_Y + connect \$83 $eq$libresoc.v:150579$7588_Y + connect \$85 $eq$libresoc.v:150580$7589_Y + connect \$87 $eq$libresoc.v:150581$7590_Y + connect \$89 $eq$libresoc.v:150582$7591_Y + connect \$91 $eq$libresoc.v:150583$7592_Y + connect \$93 $eq$libresoc.v:150584$7593_Y + connect \$95 $eq$libresoc.v:150585$7594_Y + connect \$97 $eq$libresoc.v:150586$7595_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so +end +attribute \src "libresoc.v:150792.1-151307.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" +attribute \generator "nMigen" +module \main$9 + attribute \src "libresoc.v:151162.3-151172.6" + wire width 2 $0\BC[1:0] + attribute \src "libresoc.v:151216.3-151226.6" + wire width 2 $0\ba[1:0] + attribute \src "libresoc.v:151227.3-151237.6" + wire width 2 $0\bb[1:0] + attribute \src "libresoc.v:151238.3-151258.6" + wire $0\bit_a[0:0] + attribute \src "libresoc.v:151259.3-151279.6" + wire $0\bit_b[0:0] + attribute \src "libresoc.v:151280.3-151290.6" + wire $0\bit_o[0:0] + attribute \src "libresoc.v:151205.3-151215.6" + wire width 2 $0\bt[1:0] + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $0\cr_a$6[3:0]$7623 + attribute \src "libresoc.v:151074.3-151108.6" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:151173.3-151193.6" + wire $0\cr_bit[0:0] + attribute \src "libresoc.v:151291.3-151301.6" + wire width 32 $0\full_cr$5[31:0]$7638 + attribute \src "libresoc.v:151109.3-151119.6" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:150793.7-150793.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:151194.3-151204.6" + wire width 4 $0\lut[3:0] + attribute \src "libresoc.v:151120.3-151161.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:151120.3-151161.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:151162.3-151172.6" + wire width 2 $1\BC[1:0] + attribute \src "libresoc.v:151216.3-151226.6" + wire width 2 $1\ba[1:0] + attribute \src "libresoc.v:151227.3-151237.6" + wire width 2 $1\bb[1:0] + attribute \src "libresoc.v:151238.3-151258.6" + wire $1\bit_a[0:0] + attribute \src "libresoc.v:151259.3-151279.6" + wire $1\bit_b[0:0] + attribute \src "libresoc.v:151280.3-151290.6" + wire $1\bit_o[0:0] + attribute \src "libresoc.v:151205.3-151215.6" + wire width 2 $1\bt[1:0] + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $1\cr_a$6[3:0]$7624 + attribute \src "libresoc.v:151074.3-151108.6" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:151173.3-151193.6" + wire $1\cr_bit[0:0] + attribute \src "libresoc.v:151291.3-151301.6" + wire width 32 $1\full_cr$5[31:0]$7639 + attribute \src "libresoc.v:151109.3-151119.6" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:151194.3-151204.6" + wire width 4 $1\lut[3:0] + attribute \src "libresoc.v:151120.3-151161.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:151120.3-151161.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:151238.3-151258.6" + wire $2\bit_a[0:0] + attribute \src "libresoc.v:151259.3-151279.6" + wire $2\bit_b[0:0] + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $2\cr_a$6[3:0]$7625 + attribute \src "libresoc.v:151173.3-151193.6" + wire $2\cr_bit[0:0] + attribute \src "libresoc.v:151120.3-151161.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:151070.18-151070.96" + wire width 64 $extend$libresoc.v:151070$7615_Y + attribute \src "libresoc.v:151072.18-151072.98" + wire width 65 $extend$libresoc.v:151072$7618_Y + attribute \src "libresoc.v:151073.17-151073.92" + wire width 5 $extend$libresoc.v:151073$7620_Y + attribute \src "libresoc.v:151070.18-151070.96" + wire width 64 $pos$libresoc.v:151070$7616_Y + attribute \src "libresoc.v:151072.18-151072.98" + wire width 65 $pos$libresoc.v:151072$7619_Y + attribute \src "libresoc.v:151073.17-151073.92" + wire width 5 $pos$libresoc.v:151073$7621_Y + attribute \src "libresoc.v:151064.18-151064.116" + wire width 3 $sub$libresoc.v:151064$7609_Y + attribute \src "libresoc.v:151065.18-151065.116" + wire width 3 $sub$libresoc.v:151065$7610_Y + attribute \src "libresoc.v:151066.18-151066.116" + wire width 3 $sub$libresoc.v:151066$7611_Y + attribute \src "libresoc.v:151067.18-151067.114" + wire $ternary$libresoc.v:151067$7612_Y + attribute \src "libresoc.v:151068.18-151068.115" + wire $ternary$libresoc.v:151068$7613_Y + attribute \src "libresoc.v:151069.18-151069.112" + wire $ternary$libresoc.v:151069$7614_Y + attribute \src "libresoc.v:151071.18-151071.108" + wire width 64 $ternary$libresoc.v:151071$7617_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 65 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 64 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" + wire width 2 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" + wire width 2 \ba + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" + wire width 2 \bb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" + wire \bit_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" + wire \bit_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" + wire \bit_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" + wire width 2 \bt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 7 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 18 \cr_a$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 8 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 9 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 12 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \cr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 11 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 6 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 16 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \full_cr_ok + attribute \src "libresoc.v:150793.7-150793.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + wire width 4 \lut + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 20 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 10 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:151070$7615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_cr + connect \Y $extend$libresoc.v:151070$7615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $extend$libresoc.v:151072$7618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$27 + connect \Y $extend$libresoc.v:151072$7618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:151073$7620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $extend$libresoc.v:151073$7620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:151070$7616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:151070$7615_Y + connect \Y $pos$libresoc.v:151070$7616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $pos$libresoc.v:151072$7619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:151072$7618_Y + connect \Y $pos$libresoc.v:151072$7619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:151073$7621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $extend$libresoc.v:151073$7620_Y + connect \Y $pos$libresoc.v:151073$7621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $sub$libresoc.v:151064$7609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [22:21] + connect \Y $sub$libresoc.v:151064$7609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $sub$libresoc.v:151065$7610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [17:16] + connect \Y $sub$libresoc.v:151065$7610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $sub$libresoc.v:151066$7611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [12:11] + connect \Y $sub$libresoc.v:151066$7611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $ternary$libresoc.v:151067$7612 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $ternary$libresoc.v:151067$7612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:151068$7613 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $ternary$libresoc.v:151068$7613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:151069$7614 + parameter \WIDTH 1 + connect \A \$20 + connect \B \$18 + connect \S \bit_b + connect \Y $ternary$libresoc.v:151069$7614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $ternary$libresoc.v:151071$7617 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $ternary$libresoc.v:151071$7617_Y + end + attribute \src "libresoc.v:150793.7-150793.20" + process $proc$libresoc.v:150793$7640 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:151074.3-151108.6" + process $proc$libresoc.v:151074$7622 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + assign $0\cr_a$6[3:0]$7623 $1\cr_a$6[3:0]$7624 + attribute \src "libresoc.v:151075.5-151075.29" + switch \initial + attribute \src "libresoc.v:151075.9-151075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7624 \$7 [3:0] + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7624 $2\cr_a$6[3:0]$7625 + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" + switch \bt + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $2\cr_a$6[3:0]$7625 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7625 [0] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { $2\cr_a$6[3:0]$7625 [3:2] $2\cr_a$6[3:0]$7625 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7625 [1] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { $2\cr_a$6[3:0]$7625 [3] $2\cr_a$6[3:0]$7625 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7625 [2] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign $2\cr_a$6[3:0]$7625 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7625 [3] \bit_o + case + assign $2\cr_a$6[3:0]$7625 \cr_c + end + case + assign $1\cr_a_ok[0:0] 1'0 + assign $1\cr_a$6[3:0]$7624 4'0000 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$7623 + end + attribute \src "libresoc.v:151109.3-151119.6" + process $proc$libresoc.v:151109$7626 + assign { } { } + assign { } { } + assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] + attribute \src "libresoc.v:151110.5-151110.29" + switch \initial + attribute \src "libresoc.v:151110.9-151110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr_ok[0:0] 1'1 + case + assign $1\full_cr_ok[0:0] 1'0 + end + sync always + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:151120.3-151161.6" + process $proc$libresoc.v:151120$7627 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:151121.5-151121.29" + switch \initial + attribute \src "libresoc.v:151121.9-151121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign { } { } + assign { } { } + assign $1\o[63:0] \$24 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign { } { } + assign $1\o[63:0] \$26 [63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111011 + assign { } { } + assign { } { } + assign $1\o[63:0] $2\o[63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" + switch { \cr_a [2] \cr_a [3] } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:151162.3-151172.6" + process $proc$libresoc.v:151162$7628 + assign { } { } + assign { } { } + assign $0\BC[1:0] $1\BC[1:0] + attribute \src "libresoc.v:151163.5-151163.29" + switch \initial + attribute \src "libresoc.v:151163.9-151163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\BC[1:0] \cr_op__insn [7:6] + case + assign $1\BC[1:0] 2'00 + end + sync always + update \BC $0\BC[1:0] + end + attribute \src "libresoc.v:151173.3-151193.6" + process $proc$libresoc.v:151173$7629 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:151174.5-151174.29" + switch \initial + attribute \src "libresoc.v:151174.9-151174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\cr_bit[0:0] $2\cr_bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\cr_bit[0:0] \cr_a [0] + case + assign $2\cr_bit[0:0] 1'0 + end + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:151194.3-151204.6" + process $proc$libresoc.v:151194$7630 + assign { } { } + assign { } { } + assign $0\lut[3:0] $1\lut[3:0] + attribute \src "libresoc.v:151195.5-151195.29" + switch \initial + attribute \src "libresoc.v:151195.9-151195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\lut[3:0] \cr_op__insn [9:6] + case + assign $1\lut[3:0] 4'0000 + end + sync always + update \lut $0\lut[3:0] + end + attribute \src "libresoc.v:151205.3-151215.6" + process $proc$libresoc.v:151205$7631 + assign { } { } + assign { } { } + assign $0\bt[1:0] $1\bt[1:0] + attribute \src "libresoc.v:151206.5-151206.29" + switch \initial + attribute \src "libresoc.v:151206.9-151206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bt[1:0] \$9 [1:0] + case + assign $1\bt[1:0] 2'00 + end + sync always + update \bt $0\bt[1:0] + end + attribute \src "libresoc.v:151216.3-151226.6" + process $proc$libresoc.v:151216$7632 + assign { } { } + assign { } { } + assign $0\ba[1:0] $1\ba[1:0] + attribute \src "libresoc.v:151217.5-151217.29" + switch \initial + attribute \src "libresoc.v:151217.9-151217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\ba[1:0] \$12 [1:0] + case + assign $1\ba[1:0] 2'00 + end + sync always + update \ba $0\ba[1:0] + end + attribute \src "libresoc.v:151227.3-151237.6" + process $proc$libresoc.v:151227$7633 + assign { } { } + assign { } { } + assign $0\bb[1:0] $1\bb[1:0] + attribute \src "libresoc.v:151228.5-151228.29" + switch \initial + attribute \src "libresoc.v:151228.9-151228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bb[1:0] \$15 [1:0] + case + assign $1\bb[1:0] 2'00 + end + sync always + update \bb $0\bb[1:0] + end + attribute \src "libresoc.v:151238.3-151258.6" + process $proc$libresoc.v:151238$7634 + assign { } { } + assign { } { } + assign $0\bit_a[0:0] $1\bit_a[0:0] + attribute \src "libresoc.v:151239.5-151239.29" + switch \initial + attribute \src "libresoc.v:151239.9-151239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_a[0:0] $2\bit_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + switch \ba + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_a[0:0] \cr_a [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_a[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_a[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_a[0:0] \cr_a [3] + case + assign $2\bit_a[0:0] 1'0 + end + case + assign $1\bit_a[0:0] 1'0 + end + sync always + update \bit_a $0\bit_a[0:0] + end + attribute \src "libresoc.v:151259.3-151279.6" + process $proc$libresoc.v:151259$7635 + assign { } { } + assign { } { } + assign $0\bit_b[0:0] $1\bit_b[0:0] + attribute \src "libresoc.v:151260.5-151260.29" + switch \initial + attribute \src "libresoc.v:151260.9-151260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_b[0:0] $2\bit_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + switch \bb + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_b[0:0] \cr_b [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_b[0:0] \cr_b [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_b[0:0] \cr_b [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_b[0:0] \cr_b [3] + case + assign $2\bit_b[0:0] 1'0 + end + case + assign $1\bit_b[0:0] 1'0 + end + sync always + update \bit_b $0\bit_b[0:0] + end + attribute \src "libresoc.v:151280.3-151290.6" + process $proc$libresoc.v:151280$7636 + assign { } { } + assign { } { } + assign $0\bit_o[0:0] $1\bit_o[0:0] + attribute \src "libresoc.v:151281.5-151281.29" + switch \initial + attribute \src "libresoc.v:151281.9-151281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_o[0:0] \$22 + case + assign $1\bit_o[0:0] 1'0 + end + sync always + update \bit_o $0\bit_o[0:0] + end + attribute \src "libresoc.v:151291.3-151301.6" + process $proc$libresoc.v:151291$7637 + assign { } { } + assign { } { } + assign $0\full_cr$5[31:0]$7638 $1\full_cr$5[31:0]$7639 + attribute \src "libresoc.v:151292.5-151292.29" + switch \initial + attribute \src "libresoc.v:151292.9-151292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr$5[31:0]$7639 \ra [31:0] + case + assign $1\full_cr$5[31:0]$7639 0 + end + sync always + update \full_cr$5 $0\full_cr$5[31:0]$7638 + end + connect \$10 $sub$libresoc.v:151064$7609_Y + connect \$13 $sub$libresoc.v:151065$7610_Y + connect \$16 $sub$libresoc.v:151066$7611_Y + connect \$18 $ternary$libresoc.v:151067$7612_Y + connect \$20 $ternary$libresoc.v:151068$7613_Y + connect \$22 $ternary$libresoc.v:151069$7614_Y + connect \$24 $pos$libresoc.v:151070$7616_Y + connect \$27 $ternary$libresoc.v:151071$7617_Y + connect \$26 $pos$libresoc.v:151072$7619_Y + connect \$7 $pos$libresoc.v:151073$7621_Y + connect \$9 \$10 + connect \$12 \$13 + connect \$15 \$16 + connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:151311.1-152472.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" +attribute \generator "nMigen" +module \mul0 + attribute \src "libresoc.v:152043.3-152044.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:152041.3-152042.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:152384.3-152392.6" + wire $0\alu_l_r_alu$next[0:0]$7846 + attribute \src "libresoc.v:151969.3-151970.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 + attribute \src "libresoc.v:151997.3-151998.65" + wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 + attribute \src "libresoc.v:151999.3-152000.79" + wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 + attribute \src "libresoc.v:152001.3-152002.75" + wire $0\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7774 + attribute \src "libresoc.v:152017.3-152018.59" + wire width 32 $0\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 + attribute \src "libresoc.v:151995.3-151996.69" + wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 + attribute \src "libresoc.v:152013.3-152014.67" + wire $0\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 + attribute \src "libresoc.v:152015.3-152016.69" + wire $0\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + attribute \src "libresoc.v:152007.3-152008.63" + wire $0\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + attribute \src "libresoc.v:152009.3-152010.63" + wire $0\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + attribute \src "libresoc.v:152005.3-152006.63" + wire $0\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + attribute \src "libresoc.v:152003.3-152004.63" + wire $0\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 + attribute \src "libresoc.v:152011.3-152012.69" + wire $0\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:152375.3-152383.6" + wire $0\alui_l_r_alui$next[0:0]$7843 + attribute \src "libresoc.v:151971.3-151972.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $0\data_r0__o$next[63:0]$7802 + attribute \src "libresoc.v:151991.3-151992.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:152257.3-152278.6" + wire $0\data_r0__o_ok$next[0:0]$7803 + attribute \src "libresoc.v:151993.3-151994.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7810 + attribute \src "libresoc.v:151987.3-151988.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:152279.3-152300.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7811 + attribute \src "libresoc.v:151989.3-151990.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7818 + attribute \src "libresoc.v:151983.3-151984.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:152301.3-152322.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7819 + attribute \src "libresoc.v:151985.3-151986.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:152323.3-152344.6" + wire $0\data_r3__xer_so$next[0:0]$7826 + attribute \src "libresoc.v:151979.3-151980.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:152323.3-152344.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7827 + attribute \src "libresoc.v:151981.3-151982.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:152393.3-152402.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:152403.3-152412.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:152413.3-152422.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:152423.3-152432.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:151312.7-151312.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:152179.3-152187.6" + wire $0\opc_l_r_opc$next[0:0]$7756 + attribute \src "libresoc.v:152027.3-152028.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:152170.3-152178.6" + wire $0\opc_l_s_opc$next[0:0]$7753 + attribute \src "libresoc.v:152029.3-152030.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:152433.3-152441.6" + wire width 4 $0\prev_wr_go$next[3:0]$7853 + attribute \src "libresoc.v:152039.3-152040.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:152124.3-152133.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:152215.3-152223.6" + wire width 4 $0\req_l_r_req$next[3:0]$7768 + attribute \src "libresoc.v:152019.3-152020.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:152206.3-152214.6" + wire width 4 $0\req_l_s_req$next[3:0]$7765 + attribute \src "libresoc.v:152021.3-152022.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:152143.3-152151.6" + wire $0\rok_l_r_rdok$next[0:0]$7744 + attribute \src "libresoc.v:152035.3-152036.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:152134.3-152142.6" + wire $0\rok_l_s_rdok$next[0:0]$7741 + attribute \src "libresoc.v:152037.3-152038.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:152161.3-152169.6" + wire $0\rst_l_r_rst$next[0:0]$7750 + attribute \src "libresoc.v:152031.3-152032.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:152152.3-152160.6" + wire $0\rst_l_s_rst$next[0:0]$7747 + attribute \src "libresoc.v:152033.3-152034.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:152197.3-152205.6" + wire width 3 $0\src_l_r_src$next[2:0]$7762 + attribute \src "libresoc.v:152023.3-152024.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:152188.3-152196.6" + wire width 3 $0\src_l_s_src$next[2:0]$7759 + attribute \src "libresoc.v:152025.3-152026.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:152345.3-152354.6" + wire width 64 $0\src_r0$next[63:0]$7834 + attribute \src "libresoc.v:151977.3-151978.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:152355.3-152364.6" + wire width 64 $0\src_r1$next[63:0]$7837 + attribute \src "libresoc.v:151975.3-151976.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:152365.3-152374.6" + wire $0\src_r2$next[0:0]$7840 + attribute \src "libresoc.v:151973.3-151974.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:151436.7-151436.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:151446.7-151446.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:152384.3-152392.6" + wire $1\alu_l_r_alu$next[0:0]$7847 + attribute \src "libresoc.v:151454.7-151454.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 + attribute \src "libresoc.v:151477.14-151477.49" + wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 + attribute \src "libresoc.v:151481.14-151481.68" + wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 + attribute \src "libresoc.v:151485.7-151485.43" + wire $1\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7786 + attribute \src "libresoc.v:151489.14-151489.43" + wire width 32 $1\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 + attribute \src "libresoc.v:151568.13-151568.47" + wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 + attribute \src "libresoc.v:151572.7-151572.39" + wire $1\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 + attribute \src "libresoc.v:151576.7-151576.40" + wire $1\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 + attribute \src "libresoc.v:151580.7-151580.37" + wire $1\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 + attribute \src "libresoc.v:151584.7-151584.37" + wire $1\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 + attribute \src "libresoc.v:151588.7-151588.37" + wire $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 + attribute \src "libresoc.v:151592.7-151592.37" + wire $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 + attribute \src "libresoc.v:151596.7-151596.40" + wire $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:152375.3-152383.6" + wire $1\alui_l_r_alui$next[0:0]$7844 + attribute \src "libresoc.v:151626.7-151626.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $1\data_r0__o$next[63:0]$7804 + attribute \src "libresoc.v:151660.14-151660.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:152257.3-152278.6" + wire $1\data_r0__o_ok$next[0:0]$7805 + attribute \src "libresoc.v:151664.7-151664.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7812 + attribute \src "libresoc.v:151668.13-151668.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:152279.3-152300.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7813 + attribute \src "libresoc.v:151672.7-151672.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7820 + attribute \src "libresoc.v:151676.13-151676.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:152301.3-152322.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7821 + attribute \src "libresoc.v:151680.7-151680.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:152323.3-152344.6" + wire $1\data_r3__xer_so$next[0:0]$7828 + attribute \src "libresoc.v:151684.7-151684.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:152323.3-152344.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7829 + attribute \src "libresoc.v:151688.7-151688.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:152393.3-152402.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:152403.3-152412.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:152413.3-152422.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:152423.3-152432.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:152179.3-152187.6" + wire $1\opc_l_r_opc$next[0:0]$7757 + attribute \src "libresoc.v:151708.7-151708.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:152170.3-152178.6" + wire $1\opc_l_s_opc$next[0:0]$7754 + attribute \src "libresoc.v:151712.7-151712.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:152433.3-152441.6" + wire width 4 $1\prev_wr_go$next[3:0]$7854 + attribute \src "libresoc.v:151830.13-151830.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:152124.3-152133.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:152215.3-152223.6" + wire width 4 $1\req_l_r_req$next[3:0]$7769 + attribute \src "libresoc.v:151838.13-151838.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:152206.3-152214.6" + wire width 4 $1\req_l_s_req$next[3:0]$7766 + attribute \src "libresoc.v:151842.13-151842.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:152143.3-152151.6" + wire $1\rok_l_r_rdok$next[0:0]$7745 + attribute \src "libresoc.v:151854.7-151854.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:152134.3-152142.6" + wire $1\rok_l_s_rdok$next[0:0]$7742 + attribute \src "libresoc.v:151858.7-151858.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:152161.3-152169.6" + wire $1\rst_l_r_rst$next[0:0]$7751 + attribute \src "libresoc.v:151862.7-151862.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:152152.3-152160.6" + wire $1\rst_l_s_rst$next[0:0]$7748 + attribute \src "libresoc.v:151866.7-151866.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:152197.3-152205.6" + wire width 3 $1\src_l_r_src$next[2:0]$7763 + attribute \src "libresoc.v:151880.13-151880.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:152188.3-152196.6" + wire width 3 $1\src_l_s_src$next[2:0]$7760 + attribute \src "libresoc.v:151884.13-151884.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:152345.3-152354.6" + wire width 64 $1\src_r0$next[63:0]$7835 + attribute \src "libresoc.v:151890.14-151890.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:152355.3-152364.6" + wire width 64 $1\src_r1$next[63:0]$7838 + attribute \src "libresoc.v:151894.14-151894.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:152365.3-152374.6" + wire $1\src_r2$next[0:0]$7841 + attribute \src "libresoc.v:151898.7-151898.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 + attribute \src "libresoc.v:152224.3-152256.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 + attribute \src "libresoc.v:152224.3-152256.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 + attribute \src "libresoc.v:152224.3-152256.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 + attribute \src "libresoc.v:152224.3-152256.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 + attribute \src "libresoc.v:152224.3-152256.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $2\data_r0__o$next[63:0]$7806 + attribute \src "libresoc.v:152257.3-152278.6" + wire $2\data_r0__o_ok$next[0:0]$7807 + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7814 + attribute \src "libresoc.v:152279.3-152300.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7815 + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7822 + attribute \src "libresoc.v:152301.3-152322.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7823 + attribute \src "libresoc.v:152323.3-152344.6" + wire $2\data_r3__xer_so$next[0:0]$7830 + attribute \src "libresoc.v:152323.3-152344.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7831 + attribute \src "libresoc.v:152257.3-152278.6" + wire $3\data_r0__o_ok$next[0:0]$7808 + attribute \src "libresoc.v:152279.3-152300.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7816 + attribute \src "libresoc.v:152301.3-152322.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7824 + attribute \src "libresoc.v:152323.3-152344.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7832 + attribute \src "libresoc.v:151909.19-151909.113" + wire width 3 $and$libresoc.v:151909$7641_Y + attribute \src "libresoc.v:151910.19-151910.125" + wire $and$libresoc.v:151910$7642_Y + attribute \src "libresoc.v:151911.19-151911.125" + wire $and$libresoc.v:151911$7643_Y + attribute \src "libresoc.v:151912.19-151912.125" + wire $and$libresoc.v:151912$7644_Y + attribute \src "libresoc.v:151913.19-151913.125" + wire $and$libresoc.v:151913$7645_Y + attribute \src "libresoc.v:151914.18-151914.110" + wire $and$libresoc.v:151914$7646_Y + attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_mul0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_mul0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_mul0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 19 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 20 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 21 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 \src_l_q_src + attribute \src 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0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:151910$7642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:151911$7643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:151911$7643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:151912$7644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:151912$7644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:151913$7645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:151913$7645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:151914$7646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $and$libresoc.v:151914$7646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:151915$7647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { \$102 \$104 \$106 \$108 } + connect \Y $and$libresoc.v:151915$7647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:151916$7648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$110 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:151916$7648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:151917$7649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151917$7649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:151918$7650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151918$7650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:151919$7651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151919$7651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:151920$7652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151920$7652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:151922$7654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:151922$7654_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:151924$7656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:151924$7656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:151925$7657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:151925$7657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:151927$7659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B \$24 + connect \Y $and$libresoc.v:151927$7659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:151930$7662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:151930$7662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:151931$7663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$libresoc.v:151931$7663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:151936$7668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$libresoc.v:151936$7668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:151937$7669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:151937$7669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:151939$7671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:151939$7671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:151941$7673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + 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parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151949$7681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:151950$7682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:151950$7682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:151952$7684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151952$7684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:151953$7685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151953$7685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:151954$7686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151954$7686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:151955$7687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:151955$7687_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:151962$7694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:151962$7694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:151964$7696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:151964$7696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:151965$7697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:151965$7697_Y + end + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:151921$7653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:151921$7653_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:151923$7655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:151923$7655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:151926$7658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:151926$7658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:151929$7661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:151929$7661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:151935$7667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_ready_i + connect \Y $not$libresoc.v:151935$7667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:151946$7678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:151946$7678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:151966$7698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_mul_op__imm_data__ok + connect \Y $not$libresoc.v:151966$7698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:151968$7700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:151968$7700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:151934$7666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:151934$7666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:151944$7676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:151944$7676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:151945$7677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:151945$7677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:151947$7679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:151947$7679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:151948$7680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:151948$7680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:151951$7683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:151951$7683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:151957$7689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:151957$7689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:151963$7695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:151963$7695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:151928$7660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:151928$7660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:151932$7664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:151932$7664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:151933$7665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:151933$7665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:151956$7688 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:151956$7688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:151958$7690 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:151958$7690_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:151959$7691 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:151959$7691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:151960$7692 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:151960$7692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:151961$7693 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:151961$7693_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152045.15-152051.4" + cell \alu_l$107 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152052.12-152082.4" + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_mul0_cr_a + connect \cr_a_ok \cr_a_ok + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \n_ready_i \alu_mul0_n_ready_i + connect \n_valid_o \alu_mul0_n_valid_o + connect \o \alu_mul0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_mul0_p_ready_o + connect \p_valid_i \alu_mul0_p_valid_i + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_ov \alu_mul0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_mul0_xer_so + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152083.16-152089.4" + cell \alui_l$106 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152090.15-152096.4" + cell \opc_l$102 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152097.15-152103.4" + cell \req_l$103 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152104.15-152110.4" + cell \rok_l$105 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152111.15-152116.4" + cell \rst_l$104 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152117.15-152123.4" + cell \src_l$101 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:151312.7-151312.20" + process $proc$libresoc.v:151312$7855 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:151436.7-151436.24" + process $proc$libresoc.v:151436$7856 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:151446.7-151446.26" + process $proc$libresoc.v:151446$7857 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:151454.7-151454.25" + process $proc$libresoc.v:151454$7858 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:151477.14-151477.49" + process $proc$libresoc.v:151477$7859 + assign { } { } + assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] + end + attribute \src "libresoc.v:151481.14-151481.68" + process $proc$libresoc.v:151481$7860 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:151485.7-151485.43" + process $proc$libresoc.v:151485$7861 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:151489.14-151489.43" + process $proc$libresoc.v:151489$7862 + assign { } { } + assign $1\alu_mul0_mul_op__insn[31:0] 0 + sync always + sync init + update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:151568.13-151568.47" + process $proc$libresoc.v:151568$7863 + assign { } { } + assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:151572.7-151572.39" + process $proc$libresoc.v:151572$7864 + assign { } { } + assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:151576.7-151576.40" + process $proc$libresoc.v:151576$7865 + assign { } { } + assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:151580.7-151580.37" + process $proc$libresoc.v:151580$7866 + assign { } { } + assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:151584.7-151584.37" + process $proc$libresoc.v:151584$7867 + assign { } { } + assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:151588.7-151588.37" + process $proc$libresoc.v:151588$7868 + assign { } { } + assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:151592.7-151592.37" + process $proc$libresoc.v:151592$7869 + assign { } { } + assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:151596.7-151596.40" + process $proc$libresoc.v:151596$7870 + assign { } { } + assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:151626.7-151626.27" + process $proc$libresoc.v:151626$7871 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:151660.14-151660.47" + process $proc$libresoc.v:151660$7872 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:151664.7-151664.27" + process $proc$libresoc.v:151664$7873 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:151668.13-151668.33" + process $proc$libresoc.v:151668$7874 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:151672.7-151672.30" + process $proc$libresoc.v:151672$7875 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:151676.13-151676.35" + process $proc$libresoc.v:151676$7876 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:151680.7-151680.32" + process $proc$libresoc.v:151680$7877 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:151684.7-151684.29" + process $proc$libresoc.v:151684$7878 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:151688.7-151688.32" + process $proc$libresoc.v:151688$7879 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:151708.7-151708.25" + process $proc$libresoc.v:151708$7880 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:151712.7-151712.25" + process $proc$libresoc.v:151712$7881 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:151830.13-151830.30" + process $proc$libresoc.v:151830$7882 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:151838.13-151838.31" + process $proc$libresoc.v:151838$7883 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:151842.13-151842.31" + process $proc$libresoc.v:151842$7884 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:151854.7-151854.26" + process $proc$libresoc.v:151854$7885 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:151858.7-151858.26" + process $proc$libresoc.v:151858$7886 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:151862.7-151862.25" + process $proc$libresoc.v:151862$7887 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:151866.7-151866.25" + process $proc$libresoc.v:151866$7888 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:151880.13-151880.31" + process $proc$libresoc.v:151880$7889 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:151884.13-151884.31" + process $proc$libresoc.v:151884$7890 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:151890.14-151890.43" + process $proc$libresoc.v:151890$7891 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:151894.14-151894.43" + process $proc$libresoc.v:151894$7892 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:151898.7-151898.20" + process $proc$libresoc.v:151898$7893 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:151969.3-151970.39" + process $proc$libresoc.v:151969$7701 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:151971.3-151972.43" + process $proc$libresoc.v:151971$7702 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:151973.3-151974.29" + process $proc$libresoc.v:151973$7703 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:151975.3-151976.29" + process $proc$libresoc.v:151975$7704 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:151977.3-151978.29" + process $proc$libresoc.v:151977$7705 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:151979.3-151980.47" + process $proc$libresoc.v:151979$7706 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:151981.3-151982.53" + process $proc$libresoc.v:151981$7707 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:151983.3-151984.47" + process $proc$libresoc.v:151983$7708 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:151985.3-151986.53" + process $proc$libresoc.v:151985$7709 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:151987.3-151988.43" + process $proc$libresoc.v:151987$7710 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:151989.3-151990.49" + process $proc$libresoc.v:151989$7711 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:151991.3-151992.37" + process $proc$libresoc.v:151991$7712 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:151993.3-151994.43" + process $proc$libresoc.v:151993$7713 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:151995.3-151996.69" + process $proc$libresoc.v:151995$7714 + assign { } { } + assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:151997.3-151998.65" + process $proc$libresoc.v:151997$7715 + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] + end + attribute \src "libresoc.v:151999.3-152000.79" + process $proc$libresoc.v:151999$7716 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:152001.3-152002.75" + process $proc$libresoc.v:152001$7717 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:152003.3-152004.63" + process $proc$libresoc.v:152003$7718 + assign { } { } + assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:152005.3-152006.63" + process $proc$libresoc.v:152005$7719 + assign { } { } + assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:152007.3-152008.63" + process $proc$libresoc.v:152007$7720 + assign { } { } + assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:152009.3-152010.63" + process $proc$libresoc.v:152009$7721 + assign { } { } + assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:152011.3-152012.69" + process $proc$libresoc.v:152011$7722 + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:152013.3-152014.67" + process $proc$libresoc.v:152013$7723 + assign { } { } + assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:152015.3-152016.69" + process $proc$libresoc.v:152015$7724 + assign { } { } + assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:152017.3-152018.59" + process $proc$libresoc.v:152017$7725 + assign { } { } + assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:152019.3-152020.39" + process $proc$libresoc.v:152019$7726 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:152021.3-152022.39" + process $proc$libresoc.v:152021$7727 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:152023.3-152024.39" + process $proc$libresoc.v:152023$7728 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:152025.3-152026.39" + process $proc$libresoc.v:152025$7729 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:152027.3-152028.39" + process $proc$libresoc.v:152027$7730 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:152029.3-152030.39" + process $proc$libresoc.v:152029$7731 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:152031.3-152032.39" + process $proc$libresoc.v:152031$7732 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:152033.3-152034.39" + process $proc$libresoc.v:152033$7733 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:152035.3-152036.41" + process $proc$libresoc.v:152035$7734 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:152037.3-152038.41" + process $proc$libresoc.v:152037$7735 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:152039.3-152040.37" + process $proc$libresoc.v:152039$7736 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:152041.3-152042.40" + process $proc$libresoc.v:152041$7737 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:152043.3-152044.25" + process $proc$libresoc.v:152043$7738 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:152124.3-152133.6" + process $proc$libresoc.v:152124$7739 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:152125.5-152125.29" + switch \initial + attribute \src "libresoc.v:152125.9-152125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:152134.3-152142.6" + process $proc$libresoc.v:152134$7740 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$7741 $1\rok_l_s_rdok$next[0:0]$7742 + attribute \src "libresoc.v:152135.5-152135.29" + switch \initial + attribute \src "libresoc.v:152135.9-152135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$7742 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$7742 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7741 + end + attribute \src "libresoc.v:152143.3-152151.6" + process $proc$libresoc.v:152143$7743 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$7744 $1\rok_l_r_rdok$next[0:0]$7745 + attribute \src "libresoc.v:152144.5-152144.29" + switch \initial + attribute \src "libresoc.v:152144.9-152144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$7745 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$7745 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7744 + end + attribute \src "libresoc.v:152152.3-152160.6" + process $proc$libresoc.v:152152$7746 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$7747 $1\rst_l_s_rst$next[0:0]$7748 + attribute \src "libresoc.v:152153.5-152153.29" + switch \initial + attribute \src "libresoc.v:152153.9-152153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$7748 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$7748 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7747 + end + attribute \src "libresoc.v:152161.3-152169.6" + process $proc$libresoc.v:152161$7749 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$7750 $1\rst_l_r_rst$next[0:0]$7751 + attribute \src "libresoc.v:152162.5-152162.29" + switch \initial + attribute \src "libresoc.v:152162.9-152162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$7751 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$7751 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7750 + end + attribute \src "libresoc.v:152170.3-152178.6" + process $proc$libresoc.v:152170$7752 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$7753 $1\opc_l_s_opc$next[0:0]$7754 + attribute \src "libresoc.v:152171.5-152171.29" + switch \initial + attribute \src "libresoc.v:152171.9-152171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$7754 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$7754 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7753 + end + attribute \src "libresoc.v:152179.3-152187.6" + process $proc$libresoc.v:152179$7755 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$7756 $1\opc_l_r_opc$next[0:0]$7757 + attribute \src "libresoc.v:152180.5-152180.29" + switch \initial + attribute \src "libresoc.v:152180.9-152180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$7757 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$7757 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7756 + end + attribute \src "libresoc.v:152188.3-152196.6" + process $proc$libresoc.v:152188$7758 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$7759 $1\src_l_s_src$next[2:0]$7760 + attribute \src "libresoc.v:152189.5-152189.29" + switch \initial + attribute \src "libresoc.v:152189.9-152189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$7760 3'000 + case + assign $1\src_l_s_src$next[2:0]$7760 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7759 + end + attribute \src "libresoc.v:152197.3-152205.6" + process $proc$libresoc.v:152197$7761 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$7762 $1\src_l_r_src$next[2:0]$7763 + attribute \src "libresoc.v:152198.5-152198.29" + switch \initial + attribute \src "libresoc.v:152198.9-152198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$7763 3'111 + case + assign $1\src_l_r_src$next[2:0]$7763 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7762 + end + attribute \src "libresoc.v:152206.3-152214.6" + process $proc$libresoc.v:152206$7764 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$7765 $1\req_l_s_req$next[3:0]$7766 + attribute \src "libresoc.v:152207.5-152207.29" + switch \initial + attribute \src "libresoc.v:152207.9-152207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$7766 4'0000 + case + assign $1\req_l_s_req$next[3:0]$7766 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7765 + end + attribute \src "libresoc.v:152215.3-152223.6" + process $proc$libresoc.v:152215$7767 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$7768 $1\req_l_r_req$next[3:0]$7769 + attribute \src "libresoc.v:152216.5-152216.29" + switch \initial + attribute \src "libresoc.v:152216.9-152216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$7769 4'1111 + case + assign $1\req_l_r_req$next[3:0]$7769 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7768 + end + attribute \src "libresoc.v:152224.3-152256.6" + process $proc$libresoc.v:152224$7770 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__insn$next[31:0]$7774 $1\alu_mul0_mul_op__insn$next[31:0]$7786 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 + attribute \src "libresoc.v:152225.5-152225.29" + switch \initial + attribute \src "libresoc.v:152225.9-152225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7786 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + case + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7786 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 \alu_mul0_mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 1'0 + case + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 + end + sync always + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7774 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 + end + attribute \src "libresoc.v:152257.3-152278.6" + process $proc$libresoc.v:152257$7801 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$7802 $2\data_r0__o$next[63:0]$7806 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$7803 $3\data_r0__o_ok$next[0:0]$7808 + attribute \src "libresoc.v:152258.5-152258.29" + switch \initial + attribute \src "libresoc.v:152258.9-152258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$7805 $1\data_r0__o$next[63:0]$7804 } { \o_ok \alu_mul0_o } + case + assign $1\data_r0__o$next[63:0]$7804 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7805 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$7807 $2\data_r0__o$next[63:0]$7806 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$7806 $1\data_r0__o$next[63:0]$7804 + assign $2\data_r0__o_ok$next[0:0]$7807 $1\data_r0__o_ok$next[0:0]$7805 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$7808 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$7808 $2\data_r0__o_ok$next[0:0]$7807 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$7802 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7803 + end + attribute \src "libresoc.v:152279.3-152300.6" + process $proc$libresoc.v:152279$7809 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$7810 $2\data_r1__cr_a$next[3:0]$7814 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$7811 $3\data_r1__cr_a_ok$next[0:0]$7816 + attribute \src "libresoc.v:152280.5-152280.29" + switch \initial + attribute \src "libresoc.v:152280.9-152280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$7813 $1\data_r1__cr_a$next[3:0]$7812 } { \cr_a_ok \alu_mul0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$7812 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7813 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$7815 $2\data_r1__cr_a$next[3:0]$7814 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$7814 $1\data_r1__cr_a$next[3:0]$7812 + assign $2\data_r1__cr_a_ok$next[0:0]$7815 $1\data_r1__cr_a_ok$next[0:0]$7813 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$7816 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$7816 $2\data_r1__cr_a_ok$next[0:0]$7815 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7810 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7811 + end + attribute \src "libresoc.v:152301.3-152322.6" + process $proc$libresoc.v:152301$7817 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$7818 $2\data_r2__xer_ov$next[1:0]$7822 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$7819 $3\data_r2__xer_ov_ok$next[0:0]$7824 + attribute \src "libresoc.v:152302.5-152302.29" + switch \initial + attribute \src "libresoc.v:152302.9-152302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7821 $1\data_r2__xer_ov$next[1:0]$7820 } { \xer_ov_ok \alu_mul0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$7820 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7821 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$7823 $2\data_r2__xer_ov$next[1:0]$7822 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$7822 $1\data_r2__xer_ov$next[1:0]$7820 + assign $2\data_r2__xer_ov_ok$next[0:0]$7823 $1\data_r2__xer_ov_ok$next[0:0]$7821 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$7824 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$7824 $2\data_r2__xer_ov_ok$next[0:0]$7823 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7818 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7819 + end + attribute \src "libresoc.v:152323.3-152344.6" + process $proc$libresoc.v:152323$7825 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$7826 $2\data_r3__xer_so$next[0:0]$7830 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$7827 $3\data_r3__xer_so_ok$next[0:0]$7832 + attribute \src "libresoc.v:152324.5-152324.29" + switch \initial + attribute \src "libresoc.v:152324.9-152324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$7829 $1\data_r3__xer_so$next[0:0]$7828 } { \xer_so_ok \alu_mul0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$7828 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7829 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$7831 $2\data_r3__xer_so$next[0:0]$7830 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$7830 $1\data_r3__xer_so$next[0:0]$7828 + assign $2\data_r3__xer_so_ok$next[0:0]$7831 $1\data_r3__xer_so_ok$next[0:0]$7829 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$7832 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$7832 $2\data_r3__xer_so_ok$next[0:0]$7831 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7826 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7827 + end + attribute \src "libresoc.v:152345.3-152354.6" + process $proc$libresoc.v:152345$7833 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$7834 $1\src_r0$next[63:0]$7835 + attribute \src "libresoc.v:152346.5-152346.29" + switch \initial + attribute \src "libresoc.v:152346.9-152346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$7835 \src1_i + case + assign $1\src_r0$next[63:0]$7835 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$7834 + end + attribute \src "libresoc.v:152355.3-152364.6" + process $proc$libresoc.v:152355$7836 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$7837 $1\src_r1$next[63:0]$7838 + attribute \src "libresoc.v:152356.5-152356.29" + switch \initial + attribute \src "libresoc.v:152356.9-152356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$7838 \src_or_imm + case + assign $1\src_r1$next[63:0]$7838 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$7837 + end + attribute \src "libresoc.v:152365.3-152374.6" + process $proc$libresoc.v:152365$7839 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$7840 $1\src_r2$next[0:0]$7841 + attribute \src "libresoc.v:152366.5-152366.29" + switch \initial + attribute \src "libresoc.v:152366.9-152366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$7841 \src3_i + case + assign $1\src_r2$next[0:0]$7841 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$7840 + end + attribute \src "libresoc.v:152375.3-152383.6" + process $proc$libresoc.v:152375$7842 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$7843 $1\alui_l_r_alui$next[0:0]$7844 + attribute \src "libresoc.v:152376.5-152376.29" + switch \initial + attribute \src "libresoc.v:152376.9-152376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$7844 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$7844 \$88 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7843 + end + attribute \src "libresoc.v:152384.3-152392.6" + process $proc$libresoc.v:152384$7845 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$7846 $1\alu_l_r_alu$next[0:0]$7847 + attribute \src "libresoc.v:152385.5-152385.29" + switch \initial + attribute \src "libresoc.v:152385.9-152385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$7847 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$7847 \$90 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7846 + end + 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+ attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 34 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 32 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 33 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" + wire \sign32_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" + wire \sign32_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" + wire \sign_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" + wire \sign_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $and $and$libresoc.v:152776$7895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:152776$7895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $and $and$libresoc.v:152778$7897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:152778$7897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + cell $and $and$libresoc.v:152779$7898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ra [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:152779$7898_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + cell $and $and$libresoc.v:152780$7899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rb [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:152780$7899_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $pos $extend$libresoc.v:152783$7902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:152783$7902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:152784$7904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:152784$7904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $pos $extend$libresoc.v:152786$7907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:152786$7907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:152787$7909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:152787$7909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $neg $neg$libresoc.v:152783$7903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:152783$7902_Y + connect \Y $neg$libresoc.v:152783$7903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $neg$libresoc.v:152786$7908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:152786$7907_Y + connect \Y $neg$libresoc.v:152786$7908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:152784$7905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:152784$7904_Y + connect \Y $pos$libresoc.v:152784$7905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:152787$7910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:152787$7909_Y + connect \Y $pos$libresoc.v:152787$7910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $ternary$libresoc.v:152775$7894 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:152775$7894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $ternary$libresoc.v:152777$7896 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:152777$7896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $ternary$libresoc.v:152785$7906 + parameter \WIDTH 65 + connect \A \$36 + connect \B \$34 + connect \S \sign_a + connect \Y $ternary$libresoc.v:152785$7906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $ternary$libresoc.v:152788$7911 + parameter \WIDTH 65 + connect \A \$43 + connect \B \$41 + connect \S \sign_b + connect \Y $ternary$libresoc.v:152788$7911_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:152789$7912 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:152789$7912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:152790$7913 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:152790$7913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $xor$libresoc.v:152781$7900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign_a + connect \B \sign_b + connect \Y $xor$libresoc.v:152781$7900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $xor$libresoc.v:152782$7901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $xor$libresoc.v:152782$7901_Y + end + connect \$17 $ternary$libresoc.v:152775$7894_Y + connect \$19 $and$libresoc.v:152776$7895_Y + connect \$21 $ternary$libresoc.v:152777$7896_Y + connect \$23 $and$libresoc.v:152778$7897_Y + connect \$25 $and$libresoc.v:152779$7898_Y + connect \$27 $and$libresoc.v:152780$7899_Y + connect \$29 $xor$libresoc.v:152781$7900_Y + connect \$31 $xor$libresoc.v:152782$7901_Y + connect \$34 $neg$libresoc.v:152783$7903_Y + connect \$36 $pos$libresoc.v:152784$7905_Y + connect \$38 $ternary$libresoc.v:152785$7906_Y + connect \$41 $neg$libresoc.v:152786$7908_Y + connect \$43 $pos$libresoc.v:152787$7910_Y + connect \$45 $ternary$libresoc.v:152788$7911_Y + connect \$47 $ternary$libresoc.v:152789$7912_Y + connect \$49 $ternary$libresoc.v:152790$7913_Y + connect \$33 \$38 + connect \$40 \$45 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 [63:32] \$49 + connect \rb$15 [31:0] \abs_b [31:0] + connect \ra$14 [63:32] \$47 + connect \ra$14 [31:0] \abs_a [31:0] + connect \abs_b \$45 [63:0] + connect \abs_a \$38 [63:0] + connect \neg_res32 \$31 + connect \neg_res \$29 + connect \sign32_b \$27 + connect \sign32_a \$25 + connect \sign_b \$23 + connect \sign_a \$19 + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:152813.1-153076.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +attribute \generator "nMigen" +module \mul2 + attribute \src "libresoc.v:153069.18-153069.98" + wire width 129 $extend$libresoc.v:153069$7915_Y + attribute \src "libresoc.v:153068.18-153068.99" + wire width 128 $mul$libresoc.v:153068$7914_Y + attribute \src "libresoc.v:153069.18-153069.98" + wire width 129 $pos$libresoc.v:153069$7916_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 \$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 16 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 33 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 17 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 34 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 32 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $extend$libresoc.v:153069$7915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 129 + connect \A \$18 + connect \Y $extend$libresoc.v:153069$7915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $mul $mul$libresoc.v:153068$7914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 128 + connect \A \ra + connect \B \rb + connect \Y $mul$libresoc.v:153068$7914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $pos$libresoc.v:153069$7916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 129 + connect \A $extend$libresoc.v:153069$7915_Y + connect \Y $pos$libresoc.v:153069$7916_Y + end + connect \$18 $mul$libresoc.v:153068$7914_Y + connect \$17 $pos$libresoc.v:153069$7916_Y + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$14 \xer_so + connect \neg_res32$16 \neg_res32 + connect \neg_res$15 \neg_res + connect \o \$17 +end +attribute \src "libresoc.v:153080.1-153465.10" +attribute \cells_not_processed 1 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$2\mul_ov[0:0] + attribute \src "libresoc.v:153374.18-153374.104" + wire $and$libresoc.v:153374$7925_Y + attribute \src "libresoc.v:153378.18-153378.104" + wire $and$libresoc.v:153378$7929_Y + attribute \src "libresoc.v:153368.18-153368.95" + wire width 130 $extend$libresoc.v:153368$7917_Y + attribute \src "libresoc.v:153369.18-153369.90" + wire width 130 $extend$libresoc.v:153369$7919_Y + attribute \src "libresoc.v:153379.18-153379.95" + wire width 2 $extend$libresoc.v:153379$7930_Y + attribute \src "libresoc.v:153368.18-153368.95" + wire width 130 $neg$libresoc.v:153368$7918_Y + attribute \src "libresoc.v:153373.18-153373.98" + wire $not$libresoc.v:153373$7924_Y + attribute \src "libresoc.v:153377.18-153377.98" + wire $not$libresoc.v:153377$7928_Y + attribute \src "libresoc.v:153369.18-153369.90" + wire width 130 $pos$libresoc.v:153369$7920_Y + attribute \src "libresoc.v:153379.18-153379.95" + wire width 2 $pos$libresoc.v:153379$7931_Y + attribute \src "libresoc.v:153372.18-153372.106" + wire $reduce_and$libresoc.v:153372$7923_Y + attribute \src "libresoc.v:153376.18-153376.107" + wire $reduce_and$libresoc.v:153376$7927_Y + attribute \src "libresoc.v:153371.18-153371.106" + wire $reduce_or$libresoc.v:153371$7922_Y + attribute \src "libresoc.v:153375.18-153375.107" + wire $reduce_or$libresoc.v:153375$7926_Y + attribute \src "libresoc.v:153370.18-153370.114" + wire width 130 $ternary$libresoc.v:153370$7921_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \$39 + attribute \src "libresoc.v:153081.7-153081.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" + wire \mul_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $and $and$libresoc.v:153374$7925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $and$libresoc.v:153374$7925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $and $and$libresoc.v:153378$7929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:153378$7929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $pos $extend$libresoc.v:153368$7917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:153368$7917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:153369$7919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:153369$7919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:153379$7930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $extend$libresoc.v:153379$7930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $neg$libresoc.v:153368$7918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:153368$7917_Y + connect \Y $neg$libresoc.v:153368$7918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $not $not$libresoc.v:153373$7924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $not$libresoc.v:153373$7924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $not $not$libresoc.v:153377$7928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$34 + connect \Y $not$libresoc.v:153377$7928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:153369$7920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:153369$7919_Y + connect \Y $pos$libresoc.v:153369$7920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:153379$7931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$libresoc.v:153379$7930_Y + connect \Y $pos$libresoc.v:153379$7931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_and $reduce_and$libresoc.v:153372$7923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_and$libresoc.v:153372$7923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_and $reduce_and$libresoc.v:153376$7927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_and$libresoc.v:153376$7927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_or $reduce_or$libresoc.v:153371$7922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_or$libresoc.v:153371$7922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_or $reduce_or$libresoc.v:153375$7926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_or$libresoc.v:153375$7926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $ternary$libresoc.v:153370$7921 + parameter \WIDTH 130 + connect \A \$19 + connect \B \$17 + connect \S \neg_res + connect \Y $ternary$libresoc.v:153370$7921_Y + end + attribute \src "libresoc.v:153081.7-153081.20" + process $proc$libresoc.v:153081$7939 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:153380.3-153398.6" + process $proc$libresoc.v:153380$7932 + assign { } { } + assign { } { } + assign $0\o$14[63:0]$7933 $1\o$14[63:0]$7934 + attribute \src "libresoc.v:153381.5-153381.29" + switch \initial + attribute \src "libresoc.v:153381.9-153381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o$14[63:0]$7934 { \mul_o [63:32] \mul_o [63:32] } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o$14[63:0]$7934 \mul_o [127:64] + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o$14[63:0]$7934 \mul_o [63:0] + case + assign $1\o$14[63:0]$7934 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o$14 $0\o$14[63:0]$7933 + end + attribute \src "libresoc.v:153399.3-153417.6" + process $proc$libresoc.v:153399$7935 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:153400.5-153400.29" + switch \initial + attribute \src "libresoc.v:153400.9-153400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:153418.3-153436.6" + process $proc$libresoc.v:153418$7936 + assign { } { } + assign { } { } + assign $0\mul_ov[0:0] $1\mul_ov[0:0] + attribute \src "libresoc.v:153419.5-153419.29" + switch \initial + attribute \src "libresoc.v:153419.9-153419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\mul_ov[0:0] $2\mul_ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mul_ov[0:0] \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\mul_ov[0:0] \$37 + end + case + assign $1\mul_ov[0:0] 1'0 + end + sync always + update \mul_ov $0\mul_ov[0:0] + end + attribute \src "libresoc.v:153437.3-153447.6" + process $proc$libresoc.v:153437$7937 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:153438.5-153438.29" + switch \initial + attribute \src "libresoc.v:153438.9-153438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:153448.3-153458.6" + process $proc$libresoc.v:153448$7938 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:153449.5-153449.29" + switch \initial + attribute \src "libresoc.v:153449.9-153449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$17 $neg$libresoc.v:153368$7918_Y + connect \$19 $pos$libresoc.v:153369$7920_Y + connect \$21 $ternary$libresoc.v:153370$7921_Y + connect \$23 $reduce_or$libresoc.v:153371$7922_Y + connect \$26 $reduce_and$libresoc.v:153372$7923_Y + connect \$25 $not$libresoc.v:153373$7924_Y + connect \$29 $and$libresoc.v:153374$7925_Y + connect \$31 $reduce_or$libresoc.v:153375$7926_Y + connect \$34 $reduce_and$libresoc.v:153376$7927_Y + connect \$33 $not$libresoc.v:153377$7928_Y + connect \$37 $and$libresoc.v:153378$7929_Y + connect \$39 $pos$libresoc.v:153379$7931_Y + connect \$16 \$21 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect { \xer_so_ok \xer_so$15 } \$39 + connect \mul_o \$21 [128:0] + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:153469.1-154686.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \generator "nMigen" +module \mul_pipe1 + attribute \src "libresoc.v:153470.7-153470.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7968 + attribute \src "libresoc.v:154428.3-154429.47" + wire width 14 $0\mul_op__fn_unit[13:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7969 + attribute \src "libresoc.v:154430.3-154431.61" + wire width 64 $0\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7970 + attribute \src "libresoc.v:154432.3-154433.57" + wire $0\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 32 $0\mul_op__insn$next[31:0]$7971 + attribute \src "libresoc.v:154448.3-154449.41" + wire width 32 $0\mul_op__insn[31:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7972 + attribute \src "libresoc.v:154426.3-154427.51" + wire width 7 $0\mul_op__insn_type[6:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__is_32bit$next[0:0]$7973 + attribute \src "libresoc.v:154444.3-154445.49" + wire $0\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__is_signed$next[0:0]$7974 + attribute \src "libresoc.v:154446.3-154447.51" + wire $0\mul_op__is_signed[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__oe__oe$next[0:0]$7975 + attribute \src "libresoc.v:154438.3-154439.45" + wire $0\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__oe__ok$next[0:0]$7976 + attribute \src "libresoc.v:154440.3-154441.45" + wire $0\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__rc__ok$next[0:0]$7977 + attribute \src "libresoc.v:154436.3-154437.45" + wire $0\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__rc__rc$next[0:0]$7978 + attribute \src "libresoc.v:154434.3-154435.45" + wire $0\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__write_cr0$next[0:0]$7979 + attribute \src "libresoc.v:154442.3-154443.51" + wire $0\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:154550.3-154562.6" + wire width 2 $0\muxid$next[1:0]$7965 + attribute \src "libresoc.v:154450.3-154451.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:154638.3-154650.6" + wire $0\neg_res$next[0:0]$8008 + attribute \src "libresoc.v:154651.3-154663.6" + wire $0\neg_res32$next[0:0]$8011 + attribute \src "libresoc.v:154416.3-154417.35" + wire $0\neg_res32[0:0] + attribute \src "libresoc.v:154418.3-154419.31" + wire $0\neg_res[0:0] + attribute \src "libresoc.v:154532.3-154549.6" + wire $0\r_busy$next[0:0]$7961 + attribute \src "libresoc.v:154452.3-154453.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:154599.3-154611.6" + wire width 64 $0\ra$next[63:0]$7999 + attribute \src "libresoc.v:154424.3-154425.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:154612.3-154624.6" + wire width 64 $0\rb$next[63:0]$8002 + attribute \src "libresoc.v:154422.3-154423.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:154625.3-154637.6" + wire $0\xer_so$next[0:0]$8005 + attribute \src "libresoc.v:154420.3-154421.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7980 + attribute \src "libresoc.v:153986.14-153986.40" + wire width 14 $1\mul_op__fn_unit[13:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7981 + attribute \src "libresoc.v:154025.14-154025.59" + wire width 64 $1\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7982 + attribute \src "libresoc.v:154034.7-154034.34" + wire $1\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 32 $1\mul_op__insn$next[31:0]$7983 + attribute \src "libresoc.v:154043.14-154043.34" + wire width 32 $1\mul_op__insn[31:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7984 + attribute \src "libresoc.v:154127.13-154127.38" + wire width 7 $1\mul_op__insn_type[6:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__is_32bit$next[0:0]$7985 + attribute \src "libresoc.v:154286.7-154286.30" + wire $1\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__is_signed$next[0:0]$7986 + attribute \src "libresoc.v:154295.7-154295.31" + wire $1\mul_op__is_signed[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__oe__oe$next[0:0]$7987 + attribute \src "libresoc.v:154304.7-154304.28" + wire $1\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__oe__ok$next[0:0]$7988 + attribute \src "libresoc.v:154313.7-154313.28" + wire $1\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__rc__ok$next[0:0]$7989 + attribute \src "libresoc.v:154322.7-154322.28" + wire $1\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__rc__rc$next[0:0]$7990 + attribute \src "libresoc.v:154331.7-154331.28" + wire $1\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__write_cr0$next[0:0]$7991 + attribute \src "libresoc.v:154340.7-154340.31" + wire $1\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:154550.3-154562.6" + wire width 2 $1\muxid$next[1:0]$7966 + attribute \src "libresoc.v:154349.13-154349.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:154638.3-154650.6" + wire $1\neg_res$next[0:0]$8009 + attribute \src "libresoc.v:154651.3-154663.6" + wire $1\neg_res32$next[0:0]$8012 + attribute \src "libresoc.v:154371.7-154371.23" + wire $1\neg_res32[0:0] + attribute \src "libresoc.v:154364.7-154364.21" + wire $1\neg_res[0:0] + attribute \src "libresoc.v:154532.3-154549.6" + wire $1\r_busy$next[0:0]$7962 + attribute \src "libresoc.v:154385.7-154385.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:154599.3-154611.6" + wire width 64 $1\ra$next[63:0]$8000 + attribute \src "libresoc.v:154390.14-154390.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:154612.3-154624.6" + wire width 64 $1\rb$next[63:0]$8003 + attribute \src "libresoc.v:154399.14-154399.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:154625.3-154637.6" + wire $1\xer_so$next[0:0]$8006 + attribute \src "libresoc.v:154408.7-154408.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7992 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7993 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__oe__oe$next[0:0]$7994 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__oe__ok$next[0:0]$7995 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__rc__ok$next[0:0]$7996 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__rc__rc$next[0:0]$7997 + attribute \src "libresoc.v:154532.3-154549.6" + wire $2\r_busy$next[0:0]$7963 + attribute \src "libresoc.v:154415.18-154415.118" + wire $and$libresoc.v:154415$7940_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 40 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:153470.7-153470.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$32 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul1_muxid$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so$48 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 26 \mul_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 39 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:154415$7940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $and$libresoc.v:154415$7940_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154454.14-154487.4" + cell \input$95 \input + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 + connect \mul_op__insn \input_mul_op__insn + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__ok \input_mul_op__oe__ok + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 + connect \mul_op__rc__ok \input_mul_op__rc__ok + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$17 + connect \ra \input_ra + connect \ra$14 \input_ra$30 + connect \rb \input_rb + connect \rb$15 \input_rb$31 + connect \xer_so \input_xer_so + connect \xer_so$16 \input_xer_so$32 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154488.8-154523.4" + cell \mul1 \mul1 + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 + connect \mul_op__insn \mul1_mul_op__insn + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__ok \mul1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 + connect \mul_op__rc__ok \mul1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \muxid \mul1_muxid + connect \muxid$1 \mul1_muxid$33 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + connect \ra \mul1_ra + connect \ra$14 \mul1_ra$46 + connect \rb \mul1_rb + connect \rb$15 \mul1_rb$47 + connect \xer_so \mul1_xer_so + connect \xer_so$16 \mul1_xer_so$48 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154524.10-154527.4" + cell \n$94 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154528.10-154531.4" + cell \p$93 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:153470.7-153470.20" + process $proc$libresoc.v:153470$8013 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:153986.14-153986.40" + process $proc$libresoc.v:153986$8014 + assign { } { } + assign $1\mul_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] + end + attribute \src "libresoc.v:154025.14-154025.59" + process $proc$libresoc.v:154025$8015 + assign { } { } + assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:154034.7-154034.34" + process $proc$libresoc.v:154034$8016 + assign { } { } + assign $1\mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:154043.14-154043.34" + process $proc$libresoc.v:154043$8017 + assign { } { } + assign $1\mul_op__insn[31:0] 0 + sync always + sync init + update \mul_op__insn $1\mul_op__insn[31:0] + end + attribute \src "libresoc.v:154127.13-154127.38" + process $proc$libresoc.v:154127$8018 + assign { } { } + assign $1\mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \mul_op__insn_type $1\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:154286.7-154286.30" + process $proc$libresoc.v:154286$8019 + assign { } { } + assign $1\mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:154295.7-154295.31" + process $proc$libresoc.v:154295$8020 + assign { } { } + assign $1\mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \mul_op__is_signed $1\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:154304.7-154304.28" + process $proc$libresoc.v:154304$8021 + assign { } { } + assign $1\mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:154313.7-154313.28" + process $proc$libresoc.v:154313$8022 + assign { } { } + assign $1\mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:154322.7-154322.28" + process $proc$libresoc.v:154322$8023 + assign { } { } + assign $1\mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:154331.7-154331.28" + process $proc$libresoc.v:154331$8024 + assign { } { } + assign $1\mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:154340.7-154340.31" + process $proc$libresoc.v:154340$8025 + assign { } { } + assign $1\mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:154349.13-154349.25" + process $proc$libresoc.v:154349$8026 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:154364.7-154364.21" + process $proc$libresoc.v:154364$8027 + assign { } { } + assign $1\neg_res[0:0] 1'0 + sync always + sync init + update \neg_res $1\neg_res[0:0] + end + attribute \src "libresoc.v:154371.7-154371.23" + process $proc$libresoc.v:154371$8028 + assign { } { } + assign $1\neg_res32[0:0] 1'0 + sync always + sync init + update \neg_res32 $1\neg_res32[0:0] + end + attribute \src "libresoc.v:154385.7-154385.20" + process $proc$libresoc.v:154385$8029 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:154390.14-154390.39" + process $proc$libresoc.v:154390$8030 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:154399.14-154399.39" + process $proc$libresoc.v:154399$8031 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:154408.7-154408.20" + process $proc$libresoc.v:154408$8032 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:154416.3-154417.35" + process $proc$libresoc.v:154416$7941 + assign { } { } + assign $0\neg_res32[0:0] \neg_res32$next + sync posedge \coresync_clk + update \neg_res32 $0\neg_res32[0:0] + end + attribute \src "libresoc.v:154418.3-154419.31" + process $proc$libresoc.v:154418$7942 + assign { } { } + assign $0\neg_res[0:0] \neg_res$next + sync posedge \coresync_clk + update \neg_res $0\neg_res[0:0] + end + attribute \src "libresoc.v:154420.3-154421.29" + process $proc$libresoc.v:154420$7943 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:154422.3-154423.21" + process $proc$libresoc.v:154422$7944 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:154424.3-154425.21" + process $proc$libresoc.v:154424$7945 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:154426.3-154427.51" + process $proc$libresoc.v:154426$7946 + assign { } { } + assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next + sync posedge \coresync_clk + update \mul_op__insn_type $0\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:154428.3-154429.47" + process $proc$libresoc.v:154428$7947 + assign { } { } + assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next + sync posedge \coresync_clk + update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] + end + attribute \src "libresoc.v:154430.3-154431.61" + process $proc$libresoc.v:154430$7948 + assign { } { } + assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next + sync posedge \coresync_clk + update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:154432.3-154433.57" + process $proc$libresoc.v:154432$7949 + assign { } { } + assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:154434.3-154435.45" + process $proc$libresoc.v:154434$7950 + assign { } { } + assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next + sync posedge \coresync_clk + update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:154436.3-154437.45" + process $proc$libresoc.v:154436$7951 + assign { } { } + assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next + sync posedge \coresync_clk + update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:154438.3-154439.45" + process $proc$libresoc.v:154438$7952 + assign { } { } + assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next + sync posedge \coresync_clk + update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:154440.3-154441.45" + process $proc$libresoc.v:154440$7953 + assign { } { } + assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next + sync posedge \coresync_clk + update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:154442.3-154443.51" + process $proc$libresoc.v:154442$7954 + assign { } { } + assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next + sync posedge \coresync_clk + update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:154444.3-154445.49" + process $proc$libresoc.v:154444$7955 + assign { } { } + assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next + sync posedge \coresync_clk + update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:154446.3-154447.51" + process $proc$libresoc.v:154446$7956 + assign { } { } + assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next + sync posedge \coresync_clk + update \mul_op__is_signed $0\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:154448.3-154449.41" + process $proc$libresoc.v:154448$7957 + assign { } { } + assign $0\mul_op__insn[31:0] \mul_op__insn$next + sync posedge \coresync_clk + update \mul_op__insn $0\mul_op__insn[31:0] + end + attribute \src "libresoc.v:154450.3-154451.27" + process $proc$libresoc.v:154450$7958 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:154452.3-154453.29" + process $proc$libresoc.v:154452$7959 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:154532.3-154549.6" + process $proc$libresoc.v:154532$7960 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7961 $2\r_busy$next[0:0]$7963 + attribute \src "libresoc.v:154533.5-154533.29" + switch \initial + attribute \src "libresoc.v:154533.9-154533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7962 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7962 1'0 + case + assign $1\r_busy$next[0:0]$7962 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7963 1'0 + case + assign $2\r_busy$next[0:0]$7963 $1\r_busy$next[0:0]$7962 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7961 + end + attribute \src "libresoc.v:154550.3-154562.6" + process $proc$libresoc.v:154550$7964 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$7965 $1\muxid$next[1:0]$7966 + attribute \src "libresoc.v:154551.5-154551.29" + switch \initial + attribute \src "libresoc.v:154551.9-154551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$7966 \muxid$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$7966 \muxid$52 + case + assign $1\muxid$next[1:0]$7966 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$7965 + end + attribute \src "libresoc.v:154563.3-154598.6" + process $proc$libresoc.v:154563$7967 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$next[13:0]$7968 $1\mul_op__fn_unit$next[13:0]$7980 + assign { } { } + assign { } { } + assign $0\mul_op__insn$next[31:0]$7971 $1\mul_op__insn$next[31:0]$7983 + assign $0\mul_op__insn_type$next[6:0]$7972 $1\mul_op__insn_type$next[6:0]$7984 + assign $0\mul_op__is_32bit$next[0:0]$7973 $1\mul_op__is_32bit$next[0:0]$7985 + assign $0\mul_op__is_signed$next[0:0]$7974 $1\mul_op__is_signed$next[0:0]$7986 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$next[0:0]$7979 $1\mul_op__write_cr0$next[0:0]$7991 + assign $0\mul_op__imm_data__data$next[63:0]$7969 $2\mul_op__imm_data__data$next[63:0]$7992 + assign $0\mul_op__imm_data__ok$next[0:0]$7970 $2\mul_op__imm_data__ok$next[0:0]$7993 + assign $0\mul_op__oe__oe$next[0:0]$7975 $2\mul_op__oe__oe$next[0:0]$7994 + assign $0\mul_op__oe__ok$next[0:0]$7976 $2\mul_op__oe__ok$next[0:0]$7995 + assign $0\mul_op__rc__ok$next[0:0]$7977 $2\mul_op__rc__ok$next[0:0]$7996 + assign $0\mul_op__rc__rc$next[0:0]$7978 $2\mul_op__rc__rc$next[0:0]$7997 + attribute \src "libresoc.v:154564.5-154564.29" + switch \initial + attribute \src "libresoc.v:154564.9-154564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + case + assign $1\mul_op__fn_unit$next[13:0]$7980 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7981 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7982 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7983 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7984 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7985 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7986 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7987 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7988 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7989 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7990 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7991 \mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$next[63:0]$7992 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7993 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7997 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7996 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7994 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7995 1'0 + case + assign $2\mul_op__imm_data__data$next[63:0]$7992 $1\mul_op__imm_data__data$next[63:0]$7981 + assign $2\mul_op__imm_data__ok$next[0:0]$7993 $1\mul_op__imm_data__ok$next[0:0]$7982 + assign $2\mul_op__oe__oe$next[0:0]$7994 $1\mul_op__oe__oe$next[0:0]$7987 + assign $2\mul_op__oe__ok$next[0:0]$7995 $1\mul_op__oe__ok$next[0:0]$7988 + assign $2\mul_op__rc__ok$next[0:0]$7996 $1\mul_op__rc__ok$next[0:0]$7989 + assign $2\mul_op__rc__rc$next[0:0]$7997 $1\mul_op__rc__rc$next[0:0]$7990 + end + sync always + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7968 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7969 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7970 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7971 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7972 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7973 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7974 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7975 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7976 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7977 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7978 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7979 + end + attribute \src "libresoc.v:154599.3-154611.6" + process $proc$libresoc.v:154599$7998 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$7999 $1\ra$next[63:0]$8000 + attribute \src "libresoc.v:154600.5-154600.29" + switch \initial + attribute \src "libresoc.v:154600.9-154600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$8000 \ra$65 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$8000 \ra$65 + case + assign $1\ra$next[63:0]$8000 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$7999 + end + attribute \src "libresoc.v:154612.3-154624.6" + process $proc$libresoc.v:154612$8001 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$8002 $1\rb$next[63:0]$8003 + attribute \src "libresoc.v:154613.5-154613.29" + switch \initial + attribute \src "libresoc.v:154613.9-154613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$8003 \rb$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$8003 \rb$66 + case + assign $1\rb$next[63:0]$8003 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$8002 + end + attribute \src "libresoc.v:154625.3-154637.6" + process $proc$libresoc.v:154625$8004 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8005 $1\xer_so$next[0:0]$8006 + attribute \src "libresoc.v:154626.5-154626.29" + switch \initial + attribute \src "libresoc.v:154626.9-154626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$8006 \xer_so$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$8006 \xer_so$67 + case + assign $1\xer_so$next[0:0]$8006 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8005 + end + attribute \src "libresoc.v:154638.3-154650.6" + process $proc$libresoc.v:154638$8007 + assign { } { } + assign { } { } + assign $0\neg_res$next[0:0]$8008 $1\neg_res$next[0:0]$8009 + attribute \src "libresoc.v:154639.5-154639.29" + switch \initial + attribute \src "libresoc.v:154639.9-154639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$next[0:0]$8009 \neg_res$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$next[0:0]$8009 \neg_res$68 + case + assign $1\neg_res$next[0:0]$8009 \neg_res + end + sync always + update \neg_res$next $0\neg_res$next[0:0]$8008 + end + attribute \src "libresoc.v:154651.3-154663.6" + process $proc$libresoc.v:154651$8010 + assign { } { } + assign { } { } + assign $0\neg_res32$next[0:0]$8011 $1\neg_res32$next[0:0]$8012 + attribute \src "libresoc.v:154652.5-154652.29" + switch \initial + attribute \src "libresoc.v:154652.9-154652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 + case + assign $1\neg_res32$next[0:0]$8012 \neg_res32 + end + sync always + update \neg_res32$next $0\neg_res32$next[0:0]$8011 + end + connect \$50 $and$libresoc.v:154415$7940_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$69 \mul1_neg_res32 + connect \neg_res$68 \mul1_neg_res + connect \xer_so$67 \mul1_xer_so$48 + connect \rb$66 \mul1_rb$47 + connect \ra$65 \mul1_ra$46 + connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + connect \muxid$52 \mul1_muxid$33 + connect \p_valid_i_p_ready_o \$50 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$49 \p_valid_i + connect \mul1_xer_so \input_xer_so$32 + connect \mul1_rb \input_rb$31 + connect \mul1_ra \input_ra$30 + connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + connect \mul1_muxid \input_muxid$17 + connect \input_xer_so \xer_so$16 + connect \input_rb \rb$15 + connect \input_ra \ra$14 + connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:154690.1-155610.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \generator "nMigen" +module \mul_pipe2 + attribute \src "libresoc.v:154691.7-154691.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:155504.3-155539.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8076 + attribute \src "libresoc.v:155402.3-155403.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8044 + attribute \src "libresoc.v:154982.14-154982.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8120 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8077 + attribute \src "libresoc.v:155404.3-155405.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8046 + attribute \src "libresoc.v:155008.14-155008.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8122 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8078 + attribute \src "libresoc.v:155406.3-155407.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8048 + attribute \src "libresoc.v:155017.7-155017.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8124 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8079 + attribute \src "libresoc.v:155422.3-155423.49" + wire width 32 $0\mul_op__insn$13[31:0]$8064 + attribute \src "libresoc.v:155024.14-155024.39" + wire width 32 $0\mul_op__insn$13[31:0]$8126 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8080 + attribute \src "libresoc.v:155400.3-155401.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8042 + attribute \src "libresoc.v:155183.13-155183.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8128 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8081 + attribute \src "libresoc.v:155418.3-155419.57" + wire $0\mul_op__is_32bit$11[0:0]$8060 + attribute \src "libresoc.v:155267.7-155267.35" + wire $0\mul_op__is_32bit$11[0:0]$8130 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__is_signed$12$next[0:0]$8082 + attribute \src "libresoc.v:155420.3-155421.59" + wire $0\mul_op__is_signed$12[0:0]$8062 + attribute \src "libresoc.v:155276.7-155276.36" + wire $0\mul_op__is_signed$12[0:0]$8132 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8083 + attribute \src "libresoc.v:155412.3-155413.51" + wire $0\mul_op__oe__oe$8[0:0]$8054 + attribute \src "libresoc.v:155287.7-155287.32" + wire $0\mul_op__oe__oe$8[0:0]$8134 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8084 + attribute \src "libresoc.v:155414.3-155415.51" + wire $0\mul_op__oe__ok$9[0:0]$8056 + attribute \src "libresoc.v:155296.7-155296.32" + wire $0\mul_op__oe__ok$9[0:0]$8136 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8085 + attribute \src "libresoc.v:155410.3-155411.51" + wire $0\mul_op__rc__ok$7[0:0]$8052 + attribute \src "libresoc.v:155305.7-155305.32" + wire $0\mul_op__rc__ok$7[0:0]$8138 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8086 + attribute \src "libresoc.v:155408.3-155409.51" + wire $0\mul_op__rc__rc$6[0:0]$8050 + attribute \src "libresoc.v:155314.7-155314.32" + wire $0\mul_op__rc__rc$6[0:0]$8140 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8087 + attribute \src "libresoc.v:155416.3-155417.59" + wire $0\mul_op__write_cr0$10[0:0]$8058 + attribute \src "libresoc.v:155321.7-155321.36" + wire $0\mul_op__write_cr0$10[0:0]$8142 + attribute \src "libresoc.v:155491.3-155503.6" + wire width 2 $0\muxid$1$next[1:0]$8073 + attribute \src "libresoc.v:155424.3-155425.33" + wire width 2 $0\muxid$1[1:0]$8066 + attribute \src "libresoc.v:155330.13-155330.29" + wire width 2 $0\muxid$1[1:0]$8144 + attribute \src "libresoc.v:155566.3-155578.6" + wire $0\neg_res$15$next[0:0]$8113 + attribute \src "libresoc.v:155394.3-155395.39" + wire $0\neg_res$15[0:0]$8037 + attribute \src "libresoc.v:155345.7-155345.26" + wire $0\neg_res$15[0:0]$8146 + attribute \src "libresoc.v:155579.3-155591.6" + wire $0\neg_res32$16$next[0:0]$8116 + attribute \src "libresoc.v:155392.3-155393.43" + wire $0\neg_res32$16[0:0]$8035 + attribute \src "libresoc.v:155354.7-155354.28" + wire $0\neg_res32$16[0:0]$8148 + attribute \src "libresoc.v:155540.3-155552.6" + wire width 129 $0\o$next[128:0]$8107 + attribute \src "libresoc.v:155398.3-155399.19" + wire width 129 $0\o[128:0] + attribute \src "libresoc.v:155473.3-155490.6" + wire $0\r_busy$next[0:0]$8069 + attribute \src "libresoc.v:155426.3-155427.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:155553.3-155565.6" + wire $0\xer_so$14$next[0:0]$8110 + attribute \src "libresoc.v:155396.3-155397.37" + wire $0\xer_so$14[0:0]$8039 + attribute \src "libresoc.v:155386.7-155386.25" + wire $0\xer_so$14[0:0]$8152 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8088 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8089 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8090 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8091 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8092 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8093 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__is_signed$12$next[0:0]$8094 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8095 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8096 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8097 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8098 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8099 + attribute \src "libresoc.v:155491.3-155503.6" + wire width 2 $1\muxid$1$next[1:0]$8074 + attribute \src "libresoc.v:155566.3-155578.6" + wire $1\neg_res$15$next[0:0]$8114 + attribute \src "libresoc.v:155579.3-155591.6" + wire $1\neg_res32$16$next[0:0]$8117 + attribute \src "libresoc.v:155540.3-155552.6" + wire width 129 $1\o$next[128:0]$8108 + attribute \src "libresoc.v:155361.15-155361.57" + wire width 129 $1\o[128:0] + attribute \src "libresoc.v:155473.3-155490.6" + wire $1\r_busy$next[0:0]$8070 + attribute \src "libresoc.v:155375.7-155375.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:155553.3-155565.6" + wire $1\xer_so$14$next[0:0]$8111 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8100 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8101 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8102 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8103 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8104 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8105 + attribute \src "libresoc.v:155473.3-155490.6" + wire $2\r_busy$next[0:0]$8071 + attribute \src "libresoc.v:155391.18-155391.118" + wire $and$libresoc.v:155391$8033_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:154691.7-154691.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul2_neg_res32$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so$30 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:155391$8033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $and$libresoc.v:155391$8033_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155428.8-155464.4" + cell \mul2 \mul2 + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 + connect \mul_op__insn \mul2_mul_op__insn + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__ok \mul2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 + connect \mul_op__rc__ok \mul2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \muxid \mul2_muxid + connect \muxid$1 \mul2_muxid$17 + connect \neg_res \mul2_neg_res + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32 \mul2_neg_res32 + connect \neg_res32$16 \mul2_neg_res32$32 + connect \o \mul2_o + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \xer_so$14 \mul2_xer_so$30 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155465.10-155468.4" + cell \n$97 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155469.10-155472.4" + cell \p$96 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:154691.7-154691.20" + process $proc$libresoc.v:154691$8118 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:154982.14-154982.44" + process $proc$libresoc.v:154982$8119 + assign { } { } + assign $0\mul_op__fn_unit$3[13:0]$8120 14'00000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8120 + end + attribute \src "libresoc.v:155008.14-155008.63" + process $proc$libresoc.v:155008$8121 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8122 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8122 + end + attribute \src "libresoc.v:155017.7-155017.38" + process $proc$libresoc.v:155017$8123 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8124 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8124 + end + attribute \src "libresoc.v:155024.14-155024.39" + process $proc$libresoc.v:155024$8125 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8126 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8126 + end + attribute \src "libresoc.v:155183.13-155183.42" + process $proc$libresoc.v:155183$8127 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8128 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8128 + end + attribute \src "libresoc.v:155267.7-155267.35" + process $proc$libresoc.v:155267$8129 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8130 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8130 + end + attribute \src "libresoc.v:155276.7-155276.36" + process $proc$libresoc.v:155276$8131 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8132 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8132 + end + attribute \src "libresoc.v:155287.7-155287.32" + process $proc$libresoc.v:155287$8133 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8134 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8134 + end + attribute \src "libresoc.v:155296.7-155296.32" + process $proc$libresoc.v:155296$8135 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8136 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8136 + end + attribute \src "libresoc.v:155305.7-155305.32" + process $proc$libresoc.v:155305$8137 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8138 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8138 + end + attribute \src "libresoc.v:155314.7-155314.32" + process $proc$libresoc.v:155314$8139 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8140 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8140 + end + attribute \src "libresoc.v:155321.7-155321.36" + process $proc$libresoc.v:155321$8141 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8142 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8142 + end + attribute \src "libresoc.v:155330.13-155330.29" + process $proc$libresoc.v:155330$8143 + assign { } { } + assign $0\muxid$1[1:0]$8144 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8144 + end + attribute \src "libresoc.v:155345.7-155345.26" + process $proc$libresoc.v:155345$8145 + assign { } { } + assign $0\neg_res$15[0:0]$8146 1'0 + sync always + sync init + update \neg_res$15 $0\neg_res$15[0:0]$8146 + end + attribute \src "libresoc.v:155354.7-155354.28" + process $proc$libresoc.v:155354$8147 + assign { } { } + assign $0\neg_res32$16[0:0]$8148 1'0 + sync always + sync init + update \neg_res32$16 $0\neg_res32$16[0:0]$8148 + end + attribute \src "libresoc.v:155361.15-155361.57" + process $proc$libresoc.v:155361$8149 + assign { } { } + assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[128:0] + end + attribute \src "libresoc.v:155375.7-155375.20" + process $proc$libresoc.v:155375$8150 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:155386.7-155386.25" + process $proc$libresoc.v:155386$8151 + assign { } { } + assign $0\xer_so$14[0:0]$8152 1'0 + sync always + sync init + update \xer_so$14 $0\xer_so$14[0:0]$8152 + end + attribute \src "libresoc.v:155392.3-155393.43" + process $proc$libresoc.v:155392$8034 + assign { } { } + assign $0\neg_res32$16[0:0]$8035 \neg_res32$16$next + sync posedge \coresync_clk + update \neg_res32$16 $0\neg_res32$16[0:0]$8035 + end + attribute \src "libresoc.v:155394.3-155395.39" + process $proc$libresoc.v:155394$8036 + assign { } { } + assign $0\neg_res$15[0:0]$8037 \neg_res$15$next + sync posedge \coresync_clk + update \neg_res$15 $0\neg_res$15[0:0]$8037 + end + attribute \src "libresoc.v:155396.3-155397.37" + process $proc$libresoc.v:155396$8038 + assign { } { } + assign $0\xer_so$14[0:0]$8039 \xer_so$14$next + sync posedge \coresync_clk + update \xer_so$14 $0\xer_so$14[0:0]$8039 + end + attribute \src "libresoc.v:155398.3-155399.19" + process $proc$libresoc.v:155398$8040 + assign { } { } + assign $0\o[128:0] \o$next + sync posedge \coresync_clk + update \o $0\o[128:0] + end + attribute \src "libresoc.v:155400.3-155401.57" + process $proc$libresoc.v:155400$8041 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8042 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8042 + end + attribute \src "libresoc.v:155402.3-155403.53" + process $proc$libresoc.v:155402$8043 + assign { } { } + assign $0\mul_op__fn_unit$3[13:0]$8044 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8044 + end + attribute \src "libresoc.v:155404.3-155405.67" + process $proc$libresoc.v:155404$8045 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8046 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8046 + end + attribute \src "libresoc.v:155406.3-155407.63" + process $proc$libresoc.v:155406$8047 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8048 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8048 + end + attribute \src "libresoc.v:155408.3-155409.51" + process $proc$libresoc.v:155408$8049 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8050 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8050 + end + attribute \src "libresoc.v:155410.3-155411.51" + process $proc$libresoc.v:155410$8051 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8052 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8052 + end + attribute \src "libresoc.v:155412.3-155413.51" + process $proc$libresoc.v:155412$8053 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8054 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8054 + end + attribute \src "libresoc.v:155414.3-155415.51" + process $proc$libresoc.v:155414$8055 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8056 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8056 + end + attribute \src "libresoc.v:155416.3-155417.59" + process $proc$libresoc.v:155416$8057 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8058 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8058 + end + attribute \src "libresoc.v:155418.3-155419.57" + process $proc$libresoc.v:155418$8059 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8060 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8060 + end + attribute \src "libresoc.v:155420.3-155421.59" + process $proc$libresoc.v:155420$8061 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8062 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8062 + end + attribute \src "libresoc.v:155422.3-155423.49" + process $proc$libresoc.v:155422$8063 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8064 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8064 + end + attribute \src "libresoc.v:155424.3-155425.33" + process $proc$libresoc.v:155424$8065 + assign { } { } + assign $0\muxid$1[1:0]$8066 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8066 + end + attribute \src "libresoc.v:155426.3-155427.29" + process $proc$libresoc.v:155426$8067 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:155473.3-155490.6" + process $proc$libresoc.v:155473$8068 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8069 $2\r_busy$next[0:0]$8071 + attribute \src "libresoc.v:155474.5-155474.29" + switch \initial + attribute \src "libresoc.v:155474.9-155474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8070 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8070 1'0 + case + assign $1\r_busy$next[0:0]$8070 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8071 1'0 + case + assign $2\r_busy$next[0:0]$8071 $1\r_busy$next[0:0]$8070 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8069 + end + attribute \src "libresoc.v:155491.3-155503.6" + process $proc$libresoc.v:155491$8072 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8073 $1\muxid$1$next[1:0]$8074 + attribute \src "libresoc.v:155492.5-155492.29" + switch \initial + attribute \src "libresoc.v:155492.9-155492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8074 \muxid$36 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8074 \muxid$36 + case + assign $1\muxid$1$next[1:0]$8074 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8073 + end + attribute \src "libresoc.v:155504.3-155539.6" + process $proc$libresoc.v:155504$8075 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[13:0]$8076 $1\mul_op__fn_unit$3$next[13:0]$8088 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$8079 $1\mul_op__insn$13$next[31:0]$8091 + assign $0\mul_op__insn_type$2$next[6:0]$8080 $1\mul_op__insn_type$2$next[6:0]$8092 + assign $0\mul_op__is_32bit$11$next[0:0]$8081 $1\mul_op__is_32bit$11$next[0:0]$8093 + assign $0\mul_op__is_signed$12$next[0:0]$8082 $1\mul_op__is_signed$12$next[0:0]$8094 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$8087 $1\mul_op__write_cr0$10$next[0:0]$8099 + assign $0\mul_op__imm_data__data$4$next[63:0]$8077 $2\mul_op__imm_data__data$4$next[63:0]$8100 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8078 $2\mul_op__imm_data__ok$5$next[0:0]$8101 + assign $0\mul_op__oe__oe$8$next[0:0]$8083 $2\mul_op__oe__oe$8$next[0:0]$8102 + assign $0\mul_op__oe__ok$9$next[0:0]$8084 $2\mul_op__oe__ok$9$next[0:0]$8103 + assign $0\mul_op__rc__ok$7$next[0:0]$8085 $2\mul_op__rc__ok$7$next[0:0]$8104 + assign $0\mul_op__rc__rc$6$next[0:0]$8086 $2\mul_op__rc__rc$6$next[0:0]$8105 + attribute \src "libresoc.v:155505.5-155505.29" + switch \initial + attribute \src "libresoc.v:155505.9-155505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + case + assign $1\mul_op__fn_unit$3$next[13:0]$8088 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8089 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8090 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8091 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8092 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8093 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8094 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8095 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8096 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8097 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8098 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8099 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$8100 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8105 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8104 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8102 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8103 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$8100 $1\mul_op__imm_data__data$4$next[63:0]$8089 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 $1\mul_op__imm_data__ok$5$next[0:0]$8090 + assign $2\mul_op__oe__oe$8$next[0:0]$8102 $1\mul_op__oe__oe$8$next[0:0]$8095 + assign $2\mul_op__oe__ok$9$next[0:0]$8103 $1\mul_op__oe__ok$9$next[0:0]$8096 + assign $2\mul_op__rc__ok$7$next[0:0]$8104 $1\mul_op__rc__ok$7$next[0:0]$8097 + assign $2\mul_op__rc__rc$6$next[0:0]$8105 $1\mul_op__rc__rc$6$next[0:0]$8098 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8076 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8077 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8078 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8079 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8080 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8081 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8082 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8083 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8084 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8085 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8086 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8087 + end + attribute \src "libresoc.v:155540.3-155552.6" + process $proc$libresoc.v:155540$8106 + assign { } { } + assign { } { } + assign $0\o$next[128:0]$8107 $1\o$next[128:0]$8108 + attribute \src "libresoc.v:155541.5-155541.29" + switch \initial + attribute \src "libresoc.v:155541.9-155541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o$next[128:0]$8108 \o$49 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o$next[128:0]$8108 \o$49 + case + assign $1\o$next[128:0]$8108 \o + end + sync always + update \o$next $0\o$next[128:0]$8107 + end + attribute \src "libresoc.v:155553.3-155565.6" + process $proc$libresoc.v:155553$8109 + assign { } { } + assign { } { } + assign $0\xer_so$14$next[0:0]$8110 $1\xer_so$14$next[0:0]$8111 + attribute \src "libresoc.v:155554.5-155554.29" + switch \initial + attribute \src "libresoc.v:155554.9-155554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 + case + assign $1\xer_so$14$next[0:0]$8111 \xer_so$14 + end + sync always + update \xer_so$14$next $0\xer_so$14$next[0:0]$8110 + end + attribute \src "libresoc.v:155566.3-155578.6" + process $proc$libresoc.v:155566$8112 + assign { } { } + assign { } { } + assign $0\neg_res$15$next[0:0]$8113 $1\neg_res$15$next[0:0]$8114 + attribute \src "libresoc.v:155567.5-155567.29" + switch \initial + attribute \src "libresoc.v:155567.9-155567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 + case + assign $1\neg_res$15$next[0:0]$8114 \neg_res$15 + end + sync always + update \neg_res$15$next $0\neg_res$15$next[0:0]$8113 + end + attribute \src "libresoc.v:155579.3-155591.6" + process $proc$libresoc.v:155579$8115 + assign { } { } + assign { } { } + assign $0\neg_res32$16$next[0:0]$8116 $1\neg_res32$16$next[0:0]$8117 + attribute \src "libresoc.v:155580.5-155580.29" + switch \initial + attribute \src "libresoc.v:155580.9-155580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 + case + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$16 + end + sync always + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8116 + end + connect \$34 $and$libresoc.v:155391$8033_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$52 \mul2_neg_res32$32 + connect \neg_res$51 \mul2_neg_res$31 + connect \xer_so$50 \mul2_xer_so$30 + connect \o$49 \mul2_o + connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + connect \muxid$36 \mul2_muxid$17 + connect \p_valid_i_p_ready_o \$34 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$33 \p_valid_i + connect \mul2_neg_res32 \neg_res32 + connect \mul2_neg_res \neg_res + connect \mul2_xer_so \xer_so + connect \mul2_rb \rb + connect \mul2_ra \ra + connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul2_muxid \muxid +end +attribute \src "libresoc.v:155614.1-156910.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \generator "nMigen" +module \mul_pipe3 + attribute \src "libresoc.v:156828.3-156846.6" + wire width 4 $0\cr_a$next[3:0]$8236 + attribute \src "libresoc.v:156620.3-156621.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:156828.3-156846.6" + wire $0\cr_a_ok$next[0:0]$8237 + attribute \src "libresoc.v:156622.3-156623.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:155615.7-155615.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156773.3-156808.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8199 + attribute \src "libresoc.v:156630.3-156631.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8167 + attribute \src "libresoc.v:155926.14-155926.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8257 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8200 + attribute \src "libresoc.v:156632.3-156633.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8169 + attribute \src "libresoc.v:155950.14-155950.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8259 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8201 + attribute \src "libresoc.v:156634.3-156635.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8171 + attribute \src "libresoc.v:155959.7-155959.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8261 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8202 + attribute \src "libresoc.v:156650.3-156651.49" + wire width 32 $0\mul_op__insn$13[31:0]$8187 + attribute \src "libresoc.v:155968.14-155968.39" + wire width 32 $0\mul_op__insn$13[31:0]$8263 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8203 + attribute \src "libresoc.v:156628.3-156629.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8165 + attribute \src "libresoc.v:156127.13-156127.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8265 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8204 + attribute \src "libresoc.v:156646.3-156647.57" + wire $0\mul_op__is_32bit$11[0:0]$8183 + attribute \src "libresoc.v:156211.7-156211.35" + wire $0\mul_op__is_32bit$11[0:0]$8267 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__is_signed$12$next[0:0]$8205 + attribute \src "libresoc.v:156648.3-156649.59" + wire $0\mul_op__is_signed$12[0:0]$8185 + attribute \src "libresoc.v:156220.7-156220.36" + wire $0\mul_op__is_signed$12[0:0]$8269 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8206 + attribute \src "libresoc.v:156640.3-156641.51" + wire $0\mul_op__oe__oe$8[0:0]$8177 + attribute \src "libresoc.v:156231.7-156231.32" + wire $0\mul_op__oe__oe$8[0:0]$8271 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8207 + attribute \src "libresoc.v:156642.3-156643.51" + wire $0\mul_op__oe__ok$9[0:0]$8179 + attribute \src "libresoc.v:156240.7-156240.32" + wire $0\mul_op__oe__ok$9[0:0]$8273 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8208 + attribute \src "libresoc.v:156638.3-156639.51" + wire $0\mul_op__rc__ok$7[0:0]$8175 + attribute \src "libresoc.v:156249.7-156249.32" + wire $0\mul_op__rc__ok$7[0:0]$8275 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8209 + attribute \src "libresoc.v:156636.3-156637.51" + wire $0\mul_op__rc__rc$6[0:0]$8173 + attribute \src "libresoc.v:156256.7-156256.32" + wire $0\mul_op__rc__rc$6[0:0]$8277 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8210 + attribute \src "libresoc.v:156644.3-156645.59" + wire $0\mul_op__write_cr0$10[0:0]$8181 + attribute \src "libresoc.v:156265.7-156265.36" + wire $0\mul_op__write_cr0$10[0:0]$8279 + attribute \src "libresoc.v:156760.3-156772.6" + wire width 2 $0\muxid$1$next[1:0]$8196 + attribute \src "libresoc.v:156652.3-156653.33" + wire width 2 $0\muxid$1[1:0]$8189 + attribute \src "libresoc.v:156274.13-156274.29" + wire width 2 $0\muxid$1[1:0]$8281 + attribute \src "libresoc.v:156809.3-156827.6" + wire width 64 $0\o$14$next[63:0]$8231 + attribute \src "libresoc.v:156624.3-156625.27" + wire width 64 $0\o$14[63:0]$8162 + attribute \src "libresoc.v:156295.14-156295.43" + wire width 64 $0\o$14[63:0]$8283 + attribute \src "libresoc.v:156809.3-156827.6" + wire $0\o_ok$next[0:0]$8230 + attribute \src "libresoc.v:156626.3-156627.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:156742.3-156759.6" + wire $0\r_busy$next[0:0]$8192 + attribute \src "libresoc.v:156654.3-156655.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:156847.3-156865.6" + wire width 2 $0\xer_ov$next[1:0]$8242 + attribute \src "libresoc.v:156616.3-156617.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:156847.3-156865.6" + wire $0\xer_ov_ok$next[0:0]$8243 + attribute \src "libresoc.v:156618.3-156619.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:156866.3-156884.6" + wire $0\xer_so$15$next[0:0]$8249 + attribute \src "libresoc.v:156612.3-156613.37" + wire $0\xer_so$15[0:0]$8155 + attribute \src "libresoc.v:156597.7-156597.25" + wire $0\xer_so$15[0:0]$8289 + attribute \src "libresoc.v:156866.3-156884.6" + wire $0\xer_so_ok$next[0:0]$8248 + attribute \src "libresoc.v:156614.3-156615.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:156828.3-156846.6" + wire width 4 $1\cr_a$next[3:0]$8238 + attribute \src "libresoc.v:155624.13-155624.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:156828.3-156846.6" + wire $1\cr_a_ok$next[0:0]$8239 + attribute \src "libresoc.v:155633.7-155633.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:156773.3-156808.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8211 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8212 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8213 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8214 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8215 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8216 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__is_signed$12$next[0:0]$8217 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8218 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8219 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8220 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8221 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8222 + attribute \src "libresoc.v:156760.3-156772.6" + wire width 2 $1\muxid$1$next[1:0]$8197 + attribute \src "libresoc.v:156809.3-156827.6" + wire width 64 $1\o$14$next[63:0]$8233 + attribute \src "libresoc.v:156809.3-156827.6" + wire $1\o_ok$next[0:0]$8232 + attribute \src "libresoc.v:156302.7-156302.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:156742.3-156759.6" + wire $1\r_busy$next[0:0]$8193 + attribute \src "libresoc.v:156574.7-156574.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:156847.3-156865.6" + wire width 2 $1\xer_ov$next[1:0]$8244 + attribute \src "libresoc.v:156579.13-156579.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:156847.3-156865.6" + wire $1\xer_ov_ok$next[0:0]$8245 + attribute \src "libresoc.v:156586.7-156586.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:156866.3-156884.6" + wire $1\xer_so$15$next[0:0]$8251 + attribute \src "libresoc.v:156866.3-156884.6" + wire $1\xer_so_ok$next[0:0]$8250 + attribute \src "libresoc.v:156604.7-156604.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:156828.3-156846.6" + wire $2\cr_a_ok$next[0:0]$8240 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8223 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8224 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8225 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8226 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8227 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8228 + attribute \src "libresoc.v:156809.3-156827.6" + wire $2\o_ok$next[0:0]$8234 + attribute \src "libresoc.v:156742.3-156759.6" + wire $2\r_busy$next[0:0]$8194 + attribute \src "libresoc.v:156847.3-156865.6" + wire $2\xer_ov_ok$next[0:0]$8246 + attribute \src "libresoc.v:156866.3-156884.6" + wire $2\xer_so_ok$next[0:0]$8252 + attribute \src "libresoc.v:156611.18-156611.118" + wire $and$libresoc.v:156611$8153_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 44 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 38 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:155615.7-155615.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul3_mul_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul3_muxid$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \mul3_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \mul3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_mul_op__fn_unit$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn$43 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:156611$8153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $and$libresoc.v:156611$8153_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156656.8-156692.4" + cell \mul3 \mul3 + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 + connect \mul_op__insn \mul3_mul_op__insn + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__ok \mul3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 + connect \mul_op__rc__ok \mul3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \muxid \mul3_muxid + connect \muxid$1 \mul3_muxid$16 + connect \neg_res \mul3_neg_res + connect \o \mul3_o + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so \mul3_xer_so + connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156693.10-156696.4" + cell \n$99 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156697.16-156737.4" + cell \output$100 \output + connect \cr_a \output_cr_a + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 + connect \mul_op__insn \output_mul_op__insn + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__ok \output_mul_op__oe__ok + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 + connect \mul_op__rc__ok \output_mul_op__rc__ok + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$31 + connect \o \output_o + connect \o$14 \output_o$44 + connect \o_ok \output_o_ok + connect \o_ok$15 \output_o_ok$45 + connect \xer_ov \output_xer_ov + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156738.10-156741.4" + cell \p$98 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:155615.7-155615.20" + process $proc$libresoc.v:155615$8253 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:155624.13-155624.24" + process $proc$libresoc.v:155624$8254 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:155633.7-155633.21" + process $proc$libresoc.v:155633$8255 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:155926.14-155926.44" + process $proc$libresoc.v:155926$8256 + assign { } { } + assign $0\mul_op__fn_unit$3[13:0]$8257 14'00000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8257 + end + attribute \src "libresoc.v:155950.14-155950.63" + process $proc$libresoc.v:155950$8258 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8259 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8259 + end + attribute \src "libresoc.v:155959.7-155959.38" + process $proc$libresoc.v:155959$8260 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8261 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8261 + end + attribute \src "libresoc.v:155968.14-155968.39" + process $proc$libresoc.v:155968$8262 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8263 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8263 + end + attribute \src "libresoc.v:156127.13-156127.42" + process $proc$libresoc.v:156127$8264 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8265 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8265 + end + attribute \src "libresoc.v:156211.7-156211.35" + process $proc$libresoc.v:156211$8266 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8267 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8267 + end + attribute \src "libresoc.v:156220.7-156220.36" + process $proc$libresoc.v:156220$8268 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8269 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8269 + end + attribute \src "libresoc.v:156231.7-156231.32" + process $proc$libresoc.v:156231$8270 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8271 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8271 + end + attribute \src "libresoc.v:156240.7-156240.32" + process $proc$libresoc.v:156240$8272 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8273 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8273 + end + attribute \src "libresoc.v:156249.7-156249.32" + process $proc$libresoc.v:156249$8274 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8275 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8275 + end + attribute \src "libresoc.v:156256.7-156256.32" + process $proc$libresoc.v:156256$8276 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8277 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8277 + end + attribute \src "libresoc.v:156265.7-156265.36" + process $proc$libresoc.v:156265$8278 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8279 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8279 + end + attribute \src "libresoc.v:156274.13-156274.29" + process $proc$libresoc.v:156274$8280 + assign { } { } + assign $0\muxid$1[1:0]$8281 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8281 + end + attribute \src "libresoc.v:156295.14-156295.43" + process $proc$libresoc.v:156295$8282 + assign { } { } + assign $0\o$14[63:0]$8283 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$14 $0\o$14[63:0]$8283 + end + attribute \src "libresoc.v:156302.7-156302.18" + process $proc$libresoc.v:156302$8284 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:156574.7-156574.20" + process $proc$libresoc.v:156574$8285 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:156579.13-156579.26" + process $proc$libresoc.v:156579$8286 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:156586.7-156586.23" + process $proc$libresoc.v:156586$8287 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:156597.7-156597.25" + process $proc$libresoc.v:156597$8288 + assign { } { } + assign $0\xer_so$15[0:0]$8289 1'0 + sync always + sync init + update \xer_so$15 $0\xer_so$15[0:0]$8289 + end + attribute \src "libresoc.v:156604.7-156604.23" + process $proc$libresoc.v:156604$8290 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:156612.3-156613.37" + process $proc$libresoc.v:156612$8154 + assign { } { } + assign $0\xer_so$15[0:0]$8155 \xer_so$15$next + sync posedge \coresync_clk + update \xer_so$15 $0\xer_so$15[0:0]$8155 + end + attribute \src "libresoc.v:156614.3-156615.35" + process $proc$libresoc.v:156614$8156 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:156616.3-156617.29" + process $proc$libresoc.v:156616$8157 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:156618.3-156619.35" + process $proc$libresoc.v:156618$8158 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:156620.3-156621.25" + process $proc$libresoc.v:156620$8159 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:156622.3-156623.31" + process $proc$libresoc.v:156622$8160 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:156624.3-156625.27" + process $proc$libresoc.v:156624$8161 + assign { } { } + assign $0\o$14[63:0]$8162 \o$14$next + sync posedge \coresync_clk + update \o$14 $0\o$14[63:0]$8162 + end + attribute \src "libresoc.v:156626.3-156627.25" + process $proc$libresoc.v:156626$8163 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:156628.3-156629.57" + process $proc$libresoc.v:156628$8164 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8165 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8165 + end + attribute \src "libresoc.v:156630.3-156631.53" + process $proc$libresoc.v:156630$8166 + assign { } { } + assign $0\mul_op__fn_unit$3[13:0]$8167 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8167 + end + attribute \src "libresoc.v:156632.3-156633.67" + process $proc$libresoc.v:156632$8168 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8169 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8169 + end + attribute \src "libresoc.v:156634.3-156635.63" + process $proc$libresoc.v:156634$8170 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8171 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8171 + end + attribute \src "libresoc.v:156636.3-156637.51" + process $proc$libresoc.v:156636$8172 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8173 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8173 + end + attribute \src "libresoc.v:156638.3-156639.51" + process $proc$libresoc.v:156638$8174 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8175 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8175 + end + attribute \src "libresoc.v:156640.3-156641.51" + process $proc$libresoc.v:156640$8176 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8177 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8177 + end + attribute \src "libresoc.v:156642.3-156643.51" + process $proc$libresoc.v:156642$8178 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8179 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8179 + end + attribute \src "libresoc.v:156644.3-156645.59" + process $proc$libresoc.v:156644$8180 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8181 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8181 + end + attribute \src "libresoc.v:156646.3-156647.57" + process $proc$libresoc.v:156646$8182 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8183 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8183 + end + attribute \src "libresoc.v:156648.3-156649.59" + process $proc$libresoc.v:156648$8184 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8185 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8185 + end + attribute \src "libresoc.v:156650.3-156651.49" + process $proc$libresoc.v:156650$8186 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8187 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8187 + end + attribute \src "libresoc.v:156652.3-156653.33" + process $proc$libresoc.v:156652$8188 + assign { } { } + assign $0\muxid$1[1:0]$8189 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8189 + end + attribute \src "libresoc.v:156654.3-156655.29" + process $proc$libresoc.v:156654$8190 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:156742.3-156759.6" + process $proc$libresoc.v:156742$8191 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8192 $2\r_busy$next[0:0]$8194 + attribute \src "libresoc.v:156743.5-156743.29" + switch \initial + attribute \src "libresoc.v:156743.9-156743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8193 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8193 1'0 + case + assign $1\r_busy$next[0:0]$8193 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8194 1'0 + case + assign $2\r_busy$next[0:0]$8194 $1\r_busy$next[0:0]$8193 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8192 + end + attribute \src "libresoc.v:156760.3-156772.6" + process $proc$libresoc.v:156760$8195 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8196 $1\muxid$1$next[1:0]$8197 + attribute \src "libresoc.v:156761.5-156761.29" + switch \initial + attribute \src "libresoc.v:156761.9-156761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8197 \muxid$58 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8197 \muxid$58 + case + assign $1\muxid$1$next[1:0]$8197 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8196 + end + attribute \src "libresoc.v:156773.3-156808.6" + process $proc$libresoc.v:156773$8198 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[13:0]$8199 $1\mul_op__fn_unit$3$next[13:0]$8211 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$8202 $1\mul_op__insn$13$next[31:0]$8214 + assign $0\mul_op__insn_type$2$next[6:0]$8203 $1\mul_op__insn_type$2$next[6:0]$8215 + assign $0\mul_op__is_32bit$11$next[0:0]$8204 $1\mul_op__is_32bit$11$next[0:0]$8216 + assign $0\mul_op__is_signed$12$next[0:0]$8205 $1\mul_op__is_signed$12$next[0:0]$8217 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$8210 $1\mul_op__write_cr0$10$next[0:0]$8222 + assign $0\mul_op__imm_data__data$4$next[63:0]$8200 $2\mul_op__imm_data__data$4$next[63:0]$8223 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8201 $2\mul_op__imm_data__ok$5$next[0:0]$8224 + assign $0\mul_op__oe__oe$8$next[0:0]$8206 $2\mul_op__oe__oe$8$next[0:0]$8225 + assign $0\mul_op__oe__ok$9$next[0:0]$8207 $2\mul_op__oe__ok$9$next[0:0]$8226 + assign $0\mul_op__rc__ok$7$next[0:0]$8208 $2\mul_op__rc__ok$7$next[0:0]$8227 + assign $0\mul_op__rc__rc$6$next[0:0]$8209 $2\mul_op__rc__rc$6$next[0:0]$8228 + attribute \src "libresoc.v:156774.5-156774.29" + switch \initial + attribute \src "libresoc.v:156774.9-156774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + case + assign $1\mul_op__fn_unit$3$next[13:0]$8211 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8212 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8213 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8214 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8215 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8216 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8217 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8218 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8219 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8220 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8221 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8222 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$8223 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8228 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8227 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8225 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8226 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$8223 $1\mul_op__imm_data__data$4$next[63:0]$8212 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 $1\mul_op__imm_data__ok$5$next[0:0]$8213 + assign $2\mul_op__oe__oe$8$next[0:0]$8225 $1\mul_op__oe__oe$8$next[0:0]$8218 + assign $2\mul_op__oe__ok$9$next[0:0]$8226 $1\mul_op__oe__ok$9$next[0:0]$8219 + assign $2\mul_op__rc__ok$7$next[0:0]$8227 $1\mul_op__rc__ok$7$next[0:0]$8220 + assign $2\mul_op__rc__rc$6$next[0:0]$8228 $1\mul_op__rc__rc$6$next[0:0]$8221 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8199 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8200 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8201 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8202 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8203 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8204 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8205 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8206 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8207 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8208 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8209 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8210 + end + attribute \src "libresoc.v:156809.3-156827.6" + process $proc$libresoc.v:156809$8229 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$14$next[63:0]$8231 $1\o$14$next[63:0]$8233 + assign $0\o_ok$next[0:0]$8230 $2\o_ok$next[0:0]$8234 + attribute \src "libresoc.v:156810.5-156810.29" + switch \initial + attribute \src "libresoc.v:156810.9-156810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } + case + assign $1\o_ok$next[0:0]$8232 \o_ok + assign $1\o$14$next[63:0]$8233 \o$14 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8234 1'0 + case + assign $2\o_ok$next[0:0]$8234 $1\o_ok$next[0:0]$8232 + end + sync always + update \o_ok$next $0\o_ok$next[0:0]$8230 + update \o$14$next $0\o$14$next[63:0]$8231 + end + attribute \src "libresoc.v:156828.3-156846.6" + process $proc$libresoc.v:156828$8235 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8236 $1\cr_a$next[3:0]$8238 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8237 $2\cr_a_ok$next[0:0]$8240 + attribute \src "libresoc.v:156829.5-156829.29" + switch \initial + attribute \src "libresoc.v:156829.9-156829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$next[3:0]$8238 \cr_a + assign $1\cr_a_ok$next[0:0]$8239 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8240 1'0 + case + assign $2\cr_a_ok$next[0:0]$8240 $1\cr_a_ok$next[0:0]$8239 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8236 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8237 + end + attribute \src "libresoc.v:156847.3-156865.6" + process $proc$libresoc.v:156847$8241 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8242 $1\xer_ov$next[1:0]$8244 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8243 $2\xer_ov_ok$next[0:0]$8246 + attribute \src "libresoc.v:156848.5-156848.29" + switch \initial + attribute \src "libresoc.v:156848.9-156848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } + case + assign $1\xer_ov$next[1:0]$8244 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8245 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8246 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8246 $1\xer_ov_ok$next[0:0]$8245 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8242 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8243 + end + attribute \src "libresoc.v:156866.3-156884.6" + process $proc$libresoc.v:156866$8247 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$15$next[0:0]$8249 $1\xer_so$15$next[0:0]$8251 + assign $0\xer_so_ok$next[0:0]$8248 $2\xer_so_ok$next[0:0]$8252 + attribute \src "libresoc.v:156867.5-156867.29" + switch \initial + attribute \src "libresoc.v:156867.9-156867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } + case + assign $1\xer_so_ok$next[0:0]$8250 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8251 \xer_so$15 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8252 1'0 + case + assign $2\xer_so_ok$next[0:0]$8252 $1\xer_so_ok$next[0:0]$8250 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8248 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8249 + end + connect \$56 $and$libresoc.v:156611$8153_Y + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } + connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } + connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } + connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + connect \muxid$58 \output_muxid$31 + connect \p_valid_i_p_ready_o \$56 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$55 \p_valid_i + connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } + connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + connect { \cr_a_ok$50 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + connect \output_muxid \mul3_muxid$16 + connect \neg_res32$49 \neg_res32 + connect \mul3_neg_res \neg_res + connect \mul3_xer_so \xer_so + connect \mul3_o \o + connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul3_muxid \muxid +end +attribute \src "libresoc.v:156914.1-156925.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" +attribute \generator "nMigen" +module \n + attribute \src "libresoc.v:156923.17-156923.111" + wire $and$libresoc.v:156923$8291_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:156923$8291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:156923$8291_Y + end + connect \$1 $and$libresoc.v:156923$8291_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:156929.1-156940.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \generator "nMigen" +module \n$109 + attribute \src "libresoc.v:156938.17-156938.111" + wire $and$libresoc.v:156938$8292_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:156938$8292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:156938$8292_Y + end + connect \$1 $and$libresoc.v:156938$8292_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:156944.1-156955.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +attribute \generator "nMigen" +module \n$112 + attribute \src "libresoc.v:156953.17-156953.111" + wire $and$libresoc.v:156953$8293_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:156953$8293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:156953$8293_Y + end + connect \$1 $and$libresoc.v:156953$8293_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:156959.1-156970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +attribute \generator "nMigen" +module \n$117 + attribute \src "libresoc.v:156968.17-156968.111" + wire $and$libresoc.v:156968$8294_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:156968$8294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:156968$8294_Y + end + connect \$1 $and$libresoc.v:156968$8294_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:156974.1-156985.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" +attribute \generator "nMigen" +module \n$18 + attribute \src "libresoc.v:156983.17-156983.111" + wire $and$libresoc.v:156983$8295_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:156983$8295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:156983$8295_Y + end + connect \$1 $and$libresoc.v:156983$8295_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:156989.1-157000.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" +attribute \generator "nMigen" +module \n$2 + attribute \src "libresoc.v:156998.17-156998.111" + wire $and$libresoc.v:156998$8296_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:156998$8296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:156998$8296_Y + end + connect \$1 $and$libresoc.v:156998$8296_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:157004.1-157015.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" +attribute \generator "nMigen" +module \n$21 + attribute \src "libresoc.v:157013.17-157013.111" + wire $and$libresoc.v:157013$8297_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:157013$8297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y 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parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157408$8337_Y + end + attribute \src "libresoc.v:157367.7-157367.20" + process $proc$libresoc.v:157367$8343 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157389.7-157389.19" + process $proc$libresoc.v:157389$8344 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157410.3-157411.27" + process $proc$libresoc.v:157410$8339 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157412.3-157420.6" + process $proc$libresoc.v:157412$8340 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8341 $1\q_int$next[0:0]$8342 + attribute \src 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"test_issuer.ti.core.fus.cr0.opc_l" +attribute \generator "nMigen" +module \opc_l$11 + attribute \src "libresoc.v:157429.7-157429.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157474.3-157482.6" + wire $0\q_int$next[0:0]$8355 + attribute \src "libresoc.v:157472.3-157473.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:157474.3-157482.6" + wire $1\q_int$next[0:0]$8356 + attribute \src "libresoc.v:157451.7-157451.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:157464.17-157464.96" + wire $and$libresoc.v:157464$8345_Y + attribute \src "libresoc.v:157469.17-157469.96" + wire $and$libresoc.v:157469$8350_Y + attribute \src "libresoc.v:157466.18-157466.93" + wire $not$libresoc.v:157466$8347_Y + attribute \src "libresoc.v:157468.17-157468.92" + wire $not$libresoc.v:157468$8349_Y + attribute \src "libresoc.v:157471.17-157471.92" + wire $not$libresoc.v:157471$8352_Y + attribute \src "libresoc.v:157465.18-157465.98" + wire $or$libresoc.v:157465$8346_Y + attribute \src "libresoc.v:157467.18-157467.99" + wire $or$libresoc.v:157467$8348_Y + attribute \src "libresoc.v:157470.17-157470.97" + wire $or$libresoc.v:157470$8351_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157429.7-157429.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157464$8345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157464$8345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157469$8350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157469$8350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157466$8347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157466$8347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157468$8349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157468$8349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157471$8352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157471$8352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157465$8346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157465$8346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157467$8348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157467$8348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157470$8351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157470$8351_Y + end + attribute \src "libresoc.v:157429.7-157429.20" + process $proc$libresoc.v:157429$8357 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157451.7-157451.19" + process $proc$libresoc.v:157451$8358 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157472.3-157473.27" + process $proc$libresoc.v:157472$8353 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157474.3-157482.6" + process $proc$libresoc.v:157474$8354 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8355 $1\q_int$next[0:0]$8356 + attribute \src "libresoc.v:157475.5-157475.29" + switch \initial + attribute \src "libresoc.v:157475.9-157475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8356 1'0 + case + assign $1\q_int$next[0:0]$8356 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8355 + end + connect \$9 $and$libresoc.v:157464$8345_Y + connect \$11 $or$libresoc.v:157465$8346_Y + connect \$13 $not$libresoc.v:157466$8347_Y + connect \$15 $or$libresoc.v:157467$8348_Y + connect \$1 $not$libresoc.v:157468$8349_Y + connect \$3 $and$libresoc.v:157469$8350_Y + connect \$5 $or$libresoc.v:157470$8351_Y + connect \$7 $not$libresoc.v:157471$8352_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:157490.1-157548.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" +attribute \generator "nMigen" +module \opc_l$120 + attribute \src "libresoc.v:157491.7-157491.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157536.3-157544.6" + wire $0\q_int$next[0:0]$8369 + attribute \src "libresoc.v:157534.3-157535.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:157536.3-157544.6" + wire $1\q_int$next[0:0]$8370 + attribute \src "libresoc.v:157513.7-157513.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:157526.17-157526.96" + wire $and$libresoc.v:157526$8359_Y + attribute \src "libresoc.v:157531.17-157531.96" + wire $and$libresoc.v:157531$8364_Y + attribute \src "libresoc.v:157528.18-157528.93" + wire $not$libresoc.v:157528$8361_Y + attribute \src "libresoc.v:157530.17-157530.92" + wire $not$libresoc.v:157530$8363_Y + attribute \src "libresoc.v:157533.17-157533.92" + wire $not$libresoc.v:157533$8366_Y + attribute \src "libresoc.v:157527.18-157527.98" + wire $or$libresoc.v:157527$8360_Y + attribute \src "libresoc.v:157529.18-157529.99" + wire $or$libresoc.v:157529$8362_Y + attribute \src "libresoc.v:157532.17-157532.97" + wire $or$libresoc.v:157532$8365_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157491.7-157491.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157526$8359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157526$8359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157531$8364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157531$8364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157528$8361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157528$8361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157530$8363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157530$8363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157533$8366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157533$8366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157527$8360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157527$8360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157529$8362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157529$8362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157532$8365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157532$8365_Y + end + attribute \src "libresoc.v:157491.7-157491.20" + process $proc$libresoc.v:157491$8371 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157513.7-157513.19" + process $proc$libresoc.v:157513$8372 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157534.3-157535.27" + process $proc$libresoc.v:157534$8367 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157536.3-157544.6" + process $proc$libresoc.v:157536$8368 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8369 $1\q_int$next[0:0]$8370 + attribute \src "libresoc.v:157537.5-157537.29" + switch \initial + attribute \src "libresoc.v:157537.9-157537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8370 1'0 + case + assign $1\q_int$next[0:0]$8370 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8369 + end + connect \$9 $and$libresoc.v:157526$8359_Y + connect \$11 $or$libresoc.v:157527$8360_Y + connect \$13 $not$libresoc.v:157528$8361_Y + connect \$15 $or$libresoc.v:157529$8362_Y + connect \$1 $not$libresoc.v:157530$8363_Y + connect \$3 $and$libresoc.v:157531$8364_Y + connect \$5 $or$libresoc.v:157532$8365_Y + connect \$7 $not$libresoc.v:157533$8366_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:157552.1-157610.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" +attribute \generator "nMigen" +module \opc_l$126 + attribute \src "libresoc.v:157553.7-157553.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157598.3-157606.6" + wire $0\q_int$next[0:0]$8383 + attribute \src "libresoc.v:157596.3-157597.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:157598.3-157606.6" + wire $1\q_int$next[0:0]$8384 + attribute \src "libresoc.v:157575.7-157575.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:157588.17-157588.96" + wire $and$libresoc.v:157588$8373_Y + attribute \src "libresoc.v:157593.17-157593.96" + wire $and$libresoc.v:157593$8378_Y + attribute \src "libresoc.v:157590.18-157590.93" + wire $not$libresoc.v:157590$8375_Y + attribute \src "libresoc.v:157592.17-157592.92" + wire $not$libresoc.v:157592$8377_Y + attribute \src "libresoc.v:157595.17-157595.92" + wire $not$libresoc.v:157595$8380_Y + attribute \src "libresoc.v:157589.18-157589.98" + wire $or$libresoc.v:157589$8374_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157553.7-157553.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157588$8373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157588$8373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157593$8378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157593$8378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157590$8375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157590$8375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157592$8377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157592$8377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157595$8380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157595$8380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157589$8374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157589$8374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157591$8376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157591$8376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157594$8379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157594$8379_Y + end + attribute \src "libresoc.v:157553.7-157553.20" + process $proc$libresoc.v:157553$8385 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157575.7-157575.19" + process $proc$libresoc.v:157575$8386 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157596.3-157597.27" + process $proc$libresoc.v:157596$8381 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157598.3-157606.6" + process $proc$libresoc.v:157598$8382 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8383 $1\q_int$next[0:0]$8384 + attribute \src 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"libresoc.v:157653.18-157653.99" + wire $or$libresoc.v:157653$8390_Y + attribute \src "libresoc.v:157656.17-157656.97" + wire $or$libresoc.v:157656$8393_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157615.7-157615.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157650$8387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157650$8387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157655$8392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157655$8392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157652$8389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157652$8389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157654$8391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157654$8391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157657$8394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157657$8394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157651$8388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157651$8388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157653$8390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157653$8390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157656$8393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157656$8393_Y + end + attribute \src "libresoc.v:157615.7-157615.20" + process $proc$libresoc.v:157615$8399 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157637.7-157637.19" + process $proc$libresoc.v:157637$8400 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157658.3-157659.27" + process $proc$libresoc.v:157658$8395 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157660.3-157668.6" + process $proc$libresoc.v:157660$8396 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8397 $1\q_int$next[0:0]$8398 + attribute \src "libresoc.v:157661.5-157661.29" + switch \initial + attribute \src "libresoc.v:157661.9-157661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8398 1'0 + case + assign $1\q_int$next[0:0]$8398 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8397 + end + connect \$9 $and$libresoc.v:157650$8387_Y + connect \$11 $or$libresoc.v:157651$8388_Y + connect \$13 $not$libresoc.v:157652$8389_Y + connect \$15 $or$libresoc.v:157653$8390_Y + connect \$1 $not$libresoc.v:157654$8391_Y + connect \$3 $and$libresoc.v:157655$8392_Y + connect \$5 $or$libresoc.v:157656$8393_Y + connect \$7 $not$libresoc.v:157657$8394_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:157676.1-157734.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157677.7-157677.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157712$8401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157712$8401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157717$8406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157717$8406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157714$8403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157714$8403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157716$8405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157716$8405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157719$8408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157719$8408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157713$8402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157713$8402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157715$8404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157715$8404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157718$8407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157718$8407_Y + end + attribute \src "libresoc.v:157677.7-157677.20" + process $proc$libresoc.v:157677$8413 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157699.7-157699.19" + process $proc$libresoc.v:157699$8414 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157720.3-157721.27" + process $proc$libresoc.v:157720$8409 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157722.3-157730.6" + process $proc$libresoc.v:157722$8410 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8411 $1\q_int$next[0:0]$8412 + attribute \src "libresoc.v:157723.5-157723.29" + switch \initial + attribute \src "libresoc.v:157723.9-157723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8412 1'0 + case + assign $1\q_int$next[0:0]$8412 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8411 + end + connect \$9 $and$libresoc.v:157712$8401_Y + connect \$11 $or$libresoc.v:157713$8402_Y + connect \$13 $not$libresoc.v:157714$8403_Y + connect \$15 $or$libresoc.v:157715$8404_Y + connect \$1 $not$libresoc.v:157716$8405_Y + connect \$3 $and$libresoc.v:157717$8406_Y + connect \$5 $or$libresoc.v:157718$8407_Y + connect \$7 $not$libresoc.v:157719$8408_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:157738.1-157796.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" +attribute \generator "nMigen" +module \opc_l$56 + attribute \src "libresoc.v:157739.7-157739.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157784.3-157792.6" + wire $0\q_int$next[0:0]$8425 + attribute \src "libresoc.v:157782.3-157783.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:157784.3-157792.6" + wire $1\q_int$next[0:0]$8426 + attribute \src "libresoc.v:157761.7-157761.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:157774.17-157774.96" + wire $and$libresoc.v:157774$8415_Y + attribute \src "libresoc.v:157779.17-157779.96" + wire $and$libresoc.v:157779$8420_Y + attribute \src "libresoc.v:157776.18-157776.93" + wire $not$libresoc.v:157776$8417_Y + attribute \src "libresoc.v:157778.17-157778.92" + wire $not$libresoc.v:157778$8419_Y + attribute \src "libresoc.v:157781.17-157781.92" + wire $not$libresoc.v:157781$8422_Y + attribute \src "libresoc.v:157775.18-157775.98" + wire $or$libresoc.v:157775$8416_Y + attribute \src "libresoc.v:157777.18-157777.99" + wire $or$libresoc.v:157777$8418_Y + attribute \src "libresoc.v:157780.17-157780.97" + wire $or$libresoc.v:157780$8421_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157739.7-157739.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157774$8415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157774$8415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157779$8420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157779$8420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157776$8417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157776$8417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157778$8419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157778$8419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157781$8422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157781$8422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157775$8416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157775$8416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157777$8418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157777$8418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157780$8421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157780$8421_Y + end + attribute \src "libresoc.v:157739.7-157739.20" + process $proc$libresoc.v:157739$8427 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157761.7-157761.19" + process $proc$libresoc.v:157761$8428 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157782.3-157783.27" + process $proc$libresoc.v:157782$8423 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157784.3-157792.6" + process $proc$libresoc.v:157784$8424 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8425 $1\q_int$next[0:0]$8426 + attribute \src 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"libresoc.v:157839.18-157839.99" + wire $or$libresoc.v:157839$8432_Y + attribute \src "libresoc.v:157842.17-157842.97" + wire $or$libresoc.v:157842$8435_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157801.7-157801.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:157836$8429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:157836$8429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:157841$8434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:157841$8434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:157838$8431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:157838$8431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:157840$8433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157840$8433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:157843$8436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:157843$8436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:157837$8430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:157837$8430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:157839$8432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:157839$8432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:157842$8435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:157842$8435_Y + end + attribute \src "libresoc.v:157801.7-157801.20" + process $proc$libresoc.v:157801$8441 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157823.7-157823.19" + process $proc$libresoc.v:157823$8442 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:157844.3-157845.27" + process $proc$libresoc.v:157844$8437 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:157846.3-157854.6" + process $proc$libresoc.v:157846$8438 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8439 $1\q_int$next[0:0]$8440 + attribute \src "libresoc.v:157847.5-157847.29" + switch \initial + attribute \src "libresoc.v:157847.9-157847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8440 1'0 + case + assign $1\q_int$next[0:0]$8440 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8439 + end + connect \$9 $and$libresoc.v:157836$8429_Y + connect \$11 $or$libresoc.v:157837$8430_Y + connect \$13 $not$libresoc.v:157838$8431_Y + connect \$15 $or$libresoc.v:157839$8432_Y + connect \$1 $not$libresoc.v:157840$8433_Y + connect \$3 $and$libresoc.v:157841$8434_Y + connect \$5 $or$libresoc.v:157842$8435_Y + connect \$7 $not$libresoc.v:157843$8436_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:157862.1-157920.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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\enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 46 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \cr_a_ok + attribute \src "libresoc.v:157925.7-157925.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 54 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 25 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 44 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:158276$8457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:158276$8457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:158284$8467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$41 + connect \Y $and$libresoc.v:158284$8467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:158287$8470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:158287$8470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:158280$8463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:158280$8463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:158281$8464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:158281$8464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:158278$8459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$30 + connect \Y $extend$libresoc.v:158278$8459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:158279$8461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:158279$8461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:158277$8458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:158277$8458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:158283$8466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:158283$8466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:158286$8469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:158286$8469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:158285$8468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:158285$8468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:158288$8471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:158288$8471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:158278$8460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158278$8459_Y + connect \Y $pos$libresoc.v:158278$8460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:158279$8462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158279$8461_Y + connect \Y $pos$libresoc.v:158279$8462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:158282$8465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:158282$8465_Y + end + attribute \src "libresoc.v:157925.7-157925.20" + process $proc$libresoc.v:157925$8485 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:158289.3-158300.6" + process $proc$libresoc.v:158289$8472 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:158290.5-158290.29" + switch \initial + attribute \src "libresoc.v:158290.9-158290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$25 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:158301.3-158312.6" + process $proc$libresoc.v:158301$8473 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:158302.5-158302.29" + switch \initial + attribute \src "libresoc.v:158302.9-158302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:158313.3-158324.6" + process $proc$libresoc.v:158313$8474 + assign { } { } + assign $0\o$28[64:0]$8475 $1\o$28[64:0]$8476 + attribute \src "libresoc.v:158314.5-158314.29" + switch \initial + attribute \src "libresoc.v:158314.9-158314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \alu_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$28[64:0]$8476 \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$28[64:0]$8476 \$33 + end + sync always + update \o$28 $0\o$28[64:0]$8475 + end + attribute \src "libresoc.v:158325.3-158334.6" + process $proc$libresoc.v:158325$8477 + assign { } { } + assign { } { } + assign $0\xer_so$25[0:0]$8478 $1\xer_so$25[0:0]$8479 + attribute \src "libresoc.v:158326.5-158326.29" + switch \initial + attribute \src "libresoc.v:158326.9-158326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$25[0:0]$8479 \$52 + case + assign $1\xer_so$25[0:0]$8479 1'0 + end + sync always + update \xer_so$25 $0\xer_so$25[0:0]$8478 + end + attribute \src "libresoc.v:158335.3-158344.6" + process $proc$libresoc.v:158335$8480 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:158336.5-158336.29" + switch \initial + attribute \src "libresoc.v:158336.9-158336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:158345.3-158354.6" + process $proc$libresoc.v:158345$8481 + assign { } { } + assign { } { } + assign $0\xer_ov$24[1:0]$8482 $1\xer_ov$24[1:0]$8483 + attribute \src "libresoc.v:158346.5-158346.29" + switch \initial + attribute \src "libresoc.v:158346.9-158346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$24[1:0]$8483 \xer_ov + case + assign $1\xer_ov$24[1:0]$8483 2'00 + end + sync always + update \xer_ov$24 $0\xer_ov$24[1:0]$8482 + end + attribute \src "libresoc.v:158355.3-158364.6" + process $proc$libresoc.v:158355$8484 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:158356.5-158356.29" + switch \initial + attribute \src "libresoc.v:158356.9-158356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$26 $and$libresoc.v:158276$8457_Y + connect \$30 $not$libresoc.v:158277$8458_Y + connect \$29 $pos$libresoc.v:158278$8460_Y + connect \$33 $pos$libresoc.v:158279$8462_Y + connect \$35 $eq$libresoc.v:158280$8463_Y + connect \$37 $eq$libresoc.v:158281$8464_Y + connect \$39 $reduce_or$libresoc.v:158282$8465_Y + connect \$41 $not$libresoc.v:158283$8466_Y + connect \$43 $and$libresoc.v:158284$8467_Y + connect \$45 $or$libresoc.v:158285$8468_Y + connect \$47 $not$libresoc.v:158286$8469_Y + connect \$50 $and$libresoc.v:158287$8470_Y + connect \$52 $or$libresoc.v:158288$8471_Y + connect \oe$49 \$50 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \alu_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$28 [63:0] + connect \is_positive \$43 + connect \is_negative \msb_test + connect \is_nzero \$39 + connect \msb_test \target [63] + connect \is_cmpeqb \$37 + connect \is_cmp \$35 + connect \xer_ca_ok \alu_op__output_carry + connect \xer_ca$23 \xer_ca + connect \target \o$28 [63:0] + connect \oe \$26 +end +attribute \src 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+ wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:158731.3-158740.6" + wire $1\xer_so$18[0:0]$8502 + attribute \src "libresoc.v:158741.3-158750.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:158696.18-158696.128" + wire $and$libresoc.v:158696$8486_Y + attribute \src "libresoc.v:158702.18-158702.112" + wire $and$libresoc.v:158702$8493_Y + attribute \src "libresoc.v:158705.18-158705.125" + wire $and$libresoc.v:158705$8496_Y + attribute \src "libresoc.v:158698.18-158698.123" + wire $eq$libresoc.v:158698$8489_Y + attribute \src "libresoc.v:158699.18-158699.123" + wire $eq$libresoc.v:158699$8490_Y + attribute \src "libresoc.v:158697.18-158697.101" + wire width 65 $extend$libresoc.v:158697$8487_Y + attribute \src "libresoc.v:158701.18-158701.107" + wire $not$libresoc.v:158701$8492_Y + attribute \src "libresoc.v:158704.18-158704.107" + wire $not$libresoc.v:158704$8495_Y + attribute \src "libresoc.v:158703.18-158703.115" + wire $or$libresoc.v:158703$8494_Y + attribute \src "libresoc.v:158706.18-158706.112" + wire $or$libresoc.v:158706$8497_Y + attribute \src "libresoc.v:158697.18-158697.101" + wire width 65 $pos$libresoc.v:158697$8488_Y + attribute \src "libresoc.v:158700.18-158700.105" + wire $reduce_or$libresoc.v:158700$8491_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 65 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 33 \cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \cr_a_ok + attribute \src "libresoc.v:158387.7-158387.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:158696$8486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:158696$8486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:158702$8493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$libresoc.v:158702$8493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:158705$8496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:158705$8496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:158698$8489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:158698$8489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:158699$8490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:158699$8490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:158697$8487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:158697$8487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:158701$8492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:158701$8492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:158704$8495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:158704$8495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:158703$8494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:158703$8494_Y + end + attribute \src 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attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$17[1:0]$8506 \xer_ov + case + assign $1\xer_ov$17[1:0]$8506 2'00 + end + sync always + update \xer_ov$17 $0\xer_ov$17[1:0]$8505 + end + attribute \src "libresoc.v:158761.3-158770.6" + process $proc$libresoc.v:158761$8507 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:158762.5-158762.29" + switch \initial + attribute \src "libresoc.v:158762.9-158762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$19 $and$libresoc.v:158696$8486_Y + connect \$22 $pos$libresoc.v:158697$8488_Y + connect \$24 $eq$libresoc.v:158698$8489_Y + connect \$26 $eq$libresoc.v:158699$8490_Y + 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$extend$libresoc.v:159109$8509_Y + attribute \src "libresoc.v:159113.18-159113.107" + wire $not$libresoc.v:159113$8514_Y + attribute \src "libresoc.v:159116.18-159116.107" + wire $not$libresoc.v:159116$8517_Y + attribute \src "libresoc.v:159115.18-159115.115" + wire $or$libresoc.v:159115$8516_Y + attribute \src "libresoc.v:159109.18-159109.101" + wire width 65 $pos$libresoc.v:159109$8510_Y + attribute \src "libresoc.v:159112.18-159112.105" + wire $reduce_or$libresoc.v:159112$8513_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 65 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 43 \cr_a$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \cr_a_ok + attribute \src "libresoc.v:158792.7-158792.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute 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"Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 22 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:159476$8529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$36 + connect \Y $and$libresoc.v:159476$8529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:159472$8525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:159472$8525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:159473$8526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:159473$8526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:159470$8521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$25 + connect \Y $extend$libresoc.v:159470$8521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:159471$8523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:159471$8523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:159469$8520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:159469$8520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:159475$8528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:159475$8528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:159478$8531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:159478$8531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:159477$8530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:159477$8530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:159470$8522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:159470$8521_Y + connect \Y $pos$libresoc.v:159470$8522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:159471$8524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:159471$8523_Y + connect \Y $pos$libresoc.v:159471$8524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:159474$8527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:159474$8527_Y + end + attribute \src "libresoc.v:159150.7-159150.20" + process $proc$libresoc.v:159150$8536 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:159479.3-159490.6" + process $proc$libresoc.v:159479$8532 + assign { } { } + assign $0\o$23[64:0]$8533 $1\o$23[64:0]$8534 + attribute \src "libresoc.v:159480.5-159480.29" + switch \initial + attribute \src "libresoc.v:159480.9-159480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$23[64:0]$8534 \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$23[64:0]$8534 \$28 + end + sync always + update \o$23 $0\o$23[64:0]$8533 + end + attribute \src "libresoc.v:159491.3-159502.6" + process $proc$libresoc.v:159491$8535 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:159492.5-159492.29" + switch \initial + attribute \src "libresoc.v:159492.9-159492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$42 \xer_so } + end + sync always + update \cr0 $0\cr0[3:0] + end + connect \$25 $not$libresoc.v:159469$8520_Y + connect \$24 $pos$libresoc.v:159470$8522_Y + connect \$28 $pos$libresoc.v:159471$8524_Y + connect \$30 $eq$libresoc.v:159472$8525_Y + connect \$32 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attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + 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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__write_cr0$14 + attribute \src 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$and$libresoc.v:159877$8550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:159877$8550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:159870$8543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:159870$8543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:159871$8544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:159871$8544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:159868$8539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$29 + connect \Y $extend$libresoc.v:159868$8539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:159869$8541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:159869$8541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:159867$8538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:159867$8538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:159873$8546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + 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$0\o$27[64:0]$8555 + end + attribute \src "libresoc.v:159915.3-159924.6" + process $proc$libresoc.v:159915$8557 + assign { } { } + assign { } { } + assign $0\xer_so$24[0:0]$8558 $1\xer_so$24[0:0]$8559 + attribute \src "libresoc.v:159916.5-159916.29" + switch \initial + attribute \src "libresoc.v:159916.9-159916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$24[0:0]$8559 \$51 + case + assign $1\xer_so$24[0:0]$8559 1'0 + end + sync always + update \xer_so$24 $0\xer_so$24[0:0]$8558 + end + attribute \src "libresoc.v:159925.3-159934.6" + process $proc$libresoc.v:159925$8560 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:159926.5-159926.29" + switch \initial + attribute \src "libresoc.v:159926.9-159926.17" + case 1'1 + case + end + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + wire width 64 \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + wire width 64 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 24 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 22 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 23 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 21 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 20 \divisor_neg + attribute \src "libresoc.v:159975.7-159975.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 44 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 29 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 30 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 45 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 28 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 27 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire \remainder_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 32 \remainder_s32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + wire width 64 \remainder_s32_as_s64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $and$libresoc.v:160328$8579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B \$38 + connect \Y $and$libresoc.v:160328$8579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $pos $extend$libresoc.v:160320$8567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:160320$8567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $extend$libresoc.v:160321$8569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:160321$8569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $extend$libresoc.v:160323$8572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:160323$8572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:160324$8574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:160324$8574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $extend$libresoc.v:160332$8583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:160332$8583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $extend$libresoc.v:160333$8585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:160333$8585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $extend$libresoc.v:160334$8587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:160334$8587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $extend$libresoc.v:160335$8589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:160335$8589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $extend$libresoc.v:160336$8591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $extend$libresoc.v:160336$8591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $ne$libresoc.v:160329$8580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $ne$libresoc.v:160329$8580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $neg$libresoc.v:160320$8568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:160320$8567_Y + connect \Y $neg$libresoc.v:160320$8568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $neg$libresoc.v:160323$8573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:160323$8572_Y + connect \Y $neg$libresoc.v:160323$8573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $not$libresoc.v:160326$8577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $not$libresoc.v:160326$8577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $not $not$libresoc.v:160331$8582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $not$libresoc.v:160331$8582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $pos$libresoc.v:160321$8570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:160321$8569_Y + connect \Y $pos$libresoc.v:160321$8570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:160324$8575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:160324$8574_Y + connect \Y $pos$libresoc.v:160324$8575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + cell $pos $pos$libresoc.v:160330$8581 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } + connect \Y $pos$libresoc.v:160330$8581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $pos$libresoc.v:160332$8584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:160332$8583_Y + connect \Y $pos$libresoc.v:160332$8584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $pos$libresoc.v:160333$8586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:160333$8585_Y + connect \Y $pos$libresoc.v:160333$8586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $pos$libresoc.v:160334$8588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:160334$8587_Y + connect \Y $pos$libresoc.v:160334$8588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $pos$libresoc.v:160335$8590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:160335$8589_Y + connect \Y $pos$libresoc.v:160335$8590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $pos$libresoc.v:160336$8592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:160336$8591_Y + connect \Y $pos$libresoc.v:160336$8592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $ternary$libresoc.v:160322$8571 + parameter \WIDTH 65 + connect \A \$25 + connect \B \$23 + connect \S \quotient_neg + connect \Y $ternary$libresoc.v:160322$8571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $ternary$libresoc.v:160325$8576 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \remainder_neg + connect \Y $ternary$libresoc.v:160325$8576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $xor$libresoc.v:160319$8566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $xor$libresoc.v:160319$8566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $xor$libresoc.v:160327$8578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $xor$libresoc.v:160327$8578_Y + end + attribute \src "libresoc.v:159975.7-159975.20" + process $proc$libresoc.v:159975$8595 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160337.3-160408.6" + process $proc$libresoc.v:160337$8593 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:160338.5-160338.29" + switch \initial + attribute \src "libresoc.v:160338.9-160338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $2\o[63:0] $3\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] \$48 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\o[63:0] \$50 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 + assign { } { } + assign $2\o[63:0] $5\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\o[63:0] $6\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\o[63:0] \$52 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\o[63:0] \$54 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101111 + assign { } { } + assign $2\o[63:0] $7\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\o[63:0] $8\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\o[63:0] \remainder_s32_as_s64 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\o[63:0] \$56 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\o[63:0] \remainder_64 + end + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:160409.3-160442.6" + process $proc$libresoc.v:160409$8594 + assign { } { } + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "libresoc.v:160410.5-160410.29" + switch \initial + attribute \src "libresoc.v:160410.9-160410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ov[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign { } { } + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 + end + sync always + update \ov $0\ov[0:0] + end + connect \$21 $xor$libresoc.v:160319$8566_Y + connect \$23 $neg$libresoc.v:160320$8568_Y + connect \$25 $pos$libresoc.v:160321$8570_Y + connect \$27 $ternary$libresoc.v:160322$8571_Y + connect \$30 $neg$libresoc.v:160323$8573_Y + connect \$32 $pos$libresoc.v:160324$8575_Y + connect \$34 $ternary$libresoc.v:160325$8576_Y + connect \$36 $not$libresoc.v:160326$8577_Y + connect \$38 $xor$libresoc.v:160327$8578_Y + connect \$40 $and$libresoc.v:160328$8579_Y + connect \$42 $ne$libresoc.v:160329$8580_Y + connect \$44 $pos$libresoc.v:160330$8581_Y + connect \$46 $not$libresoc.v:160331$8582_Y + connect \$48 $pos$libresoc.v:160332$8584_Y + connect \$50 $pos$libresoc.v:160333$8586_Y + connect \$52 $pos$libresoc.v:160334$8588_Y + connect \$54 $pos$libresoc.v:160335$8590_Y + connect \$56 $pos$libresoc.v:160336$8592_Y + connect \$29 \$34 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \remainder_s32_as_s64 \$44 + connect \remainder_s32 \remainder_64 [31:0] + connect \o_ok 1'1 + connect \xer_ov { \ov \ov } + connect \xer_ov_ok 1'1 + connect \remainder_64 \$34 [63:0] + connect \quotient_65 \$27 + connect \remainder_neg \dividend_neg + connect \quotient_neg \$21 +end +attribute \src "libresoc.v:160460.1-160471.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" +attribute \generator "nMigen" +module \p + attribute \src "libresoc.v:160469.17-160469.111" + wire $and$libresoc.v:160469$8596_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:160469$8596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:160469$8596_Y + end + connect \$1 $and$libresoc.v:160469$8596_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:160475.1-160486.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" +attribute \generator "nMigen" +module \p$1 + attribute \src "libresoc.v:160484.17-160484.111" + wire $and$libresoc.v:160484$8597_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:160484$8597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:160484$8597_Y + end + connect \$1 $and$libresoc.v:160484$8597_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:160490.1-160501.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" +attribute \generator "nMigen" +module \p$108 + attribute \src "libresoc.v:160499.17-160499.111" + wire $and$libresoc.v:160499$8598_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:160499$8598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:160499$8598_Y + end + connect \$1 $and$libresoc.v:160499$8598_Y + connect \trigger \$1 +end +attribute \src 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1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \B \$9 + connect \Y $and$libresoc.v:161124$8626_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:161126$8628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds + connect \B \$13 + connect \Y $and$libresoc.v:161126$8628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:161128$8630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:161128$8630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:161129$8631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts + connect \B \$17 + connect \Y $and$libresoc.v:161129$8631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:161132$8636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:161132$8636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:161133$8637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:161133$8637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:161134$8638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:161134$8638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:161135$8639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:161135$8639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:161136$8640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:161136$8640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" + cell $and $and$libresoc.v:161141$8645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 176 + parameter \Y_WIDTH 176 + connect \A \m_ld_data_o + connect \B \lenexp_rexp_o + connect \Y $and$libresoc.v:161141$8645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:161144$8648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:161144$8648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:161145$8649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:161145$8649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:161147$8651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:161147$8651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:161151$8655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:161151$8655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$libresoc.v:161153$8657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \valid_l_q_valid + connect \Y $and$libresoc.v:161153$8657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$libresoc.v:161155$8659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \valid_l_q_valid + connect \Y $and$libresoc.v:161155$8659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $and $and$libresoc.v:161159$8663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$libresoc.v:161159$8663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:161160$8664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:161160$8664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:161163$8667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active + connect \B \$81 + connect \Y $and$libresoc.v:161163$8667_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:161130$8632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$libresoc.v:161130$8632_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:161131$8634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$libresoc.v:161131$8634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $mul $mul$libresoc.v:161142$8646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:161142$8646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $mul $mul$libresoc.v:161148$8652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:161148$8652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $not $not$libresoc.v:161123$8625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:161123$8625_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:161125$8627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $not$libresoc.v:161125$8627_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:161127$8629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $not$libresoc.v:161127$8629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:161137$8641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:161137$8641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $not$libresoc.v:161140$8644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \Y $not$libresoc.v:161140$8644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:161146$8650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:161146$8650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" + cell $not $not$libresoc.v:161149$8653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:161149$8653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + cell $not $not$libresoc.v:161156$8660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:161156$8660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:161157$8661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_st_i + connect \Y $not$libresoc.v:161157$8661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:161158$8662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:161158$8662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $not$libresoc.v:161161$8665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:161161$8665_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:161162$8666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $not$libresoc.v:161162$8666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $or$libresoc.v:161138$8642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $or$libresoc.v:161138$8642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + cell $or $or$libresoc.v:161139$8643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:161139$8643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:161152$8656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:161152$8656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:161154$8658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:161154$8658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:161130$8633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:161130$8632_Y + connect \Y $pos$libresoc.v:161130$8633_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:161131$8635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:161131$8634_Y + connect \Y $pos$libresoc.v:161131$8635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $sshl $sshl$libresoc.v:161150$8654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B \$57 + connect \Y $sshl$libresoc.v:161150$8654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $sshr $sshr$libresoc.v:161143$8647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A \$42 + connect \B \$44 + connect \Y $sshr$libresoc.v:161143$8647_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161180.11-161187.4" + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_addr_acked \adrok_l_q_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \s_addr_acked \adrok_l_s_addr_acked + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161188.10-161194.4" + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_busy \busy_l_q_busy + connect \r_busy \busy_l_r_busy + connect \s_busy \busy_l_s_busy + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161195.9-161201.4" + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_cyc \cyc_l_q_cyc + connect \r_cyc \cyc_l_r_cyc + connect \s_cyc \cyc_l_s_cyc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161202.13-161208.4" + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_ld_active \ld_active_q_ld_active + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161209.10-161214.4" + cell \lenexp \lenexp + connect \addr_i \lenexp_addr_i + connect \len_i \lenexp_len_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161215.11-161221.4" + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161222.13-161228.4" + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_active \st_active_q_st_active + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161229.11-161235.4" + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_done \st_done_q_st_done + connect \r_st_done \st_done_r_st_done + connect \s_st_done \st_done_s_st_done + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161236.11-161242.4" + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid + end + attribute \src "libresoc.v:160878.7-160878.20" + process $proc$libresoc.v:160878$8722 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160972.7-160972.34" + process $proc$libresoc.v:160972$8723 + assign { } { } + assign $1\adrok_l_s_addr_acked[0:0] 1'0 + sync always + sync init + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:160976.7-160976.24" + process $proc$libresoc.v:160976$8724 + assign { } { } + assign $1\busy_delay[0:0] 1'0 + sync always + sync init + update \busy_delay $1\busy_delay[0:0] + end + attribute \src "libresoc.v:160998.13-160998.29" + process $proc$libresoc.v:160998$8725 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:161012.7-161012.21" + process $proc$libresoc.v:161012$8726 + assign { } { } + assign $1\lds_dly[0:0] 1'0 + sync always + sync init + update \lds_dly $1\lds_dly[0:0] + end + attribute \src "libresoc.v:161055.7-161055.29" + process $proc$libresoc.v:161055$8727 + assign { } { } + assign $1\lsui_active_dly[0:0] 1'0 + sync always + sync init + update \lsui_active_dly $1\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:161067.7-161067.25" + process $proc$libresoc.v:161067$8728 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:161087.7-161087.31" + process $proc$libresoc.v:161087$8729 + assign { } { } + assign $1\st_done_s_st_done[0:0] 1'0 + sync always + sync init + update \st_done_s_st_done $1\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:161095.7-161095.21" + process $proc$libresoc.v:161095$8730 + assign { } { } + assign $1\sts_dly[0:0] 1'0 + sync always + sync init + update \sts_dly $1\sts_dly[0:0] + end + attribute \src "libresoc.v:161164.3-161165.47" + process $proc$libresoc.v:161164$8668 + assign { } { } + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:161166.3-161167.35" + process $proc$libresoc.v:161166$8669 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:161168.3-161169.36" + process $proc$libresoc.v:161168$8670 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:161170.3-161171.35" + process $proc$libresoc.v:161170$8671 + assign { } { } + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] + end + attribute \src "libresoc.v:161172.3-161173.35" + process $proc$libresoc.v:161172$8672 + assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "libresoc.v:161174.3-161175.37" + process $proc$libresoc.v:161174$8673 + assign { } { } + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] + end + attribute \src "libresoc.v:161176.3-161177.57" + process $proc$libresoc.v:161176$8674 + assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:161178.3-161179.51" + process $proc$libresoc.v:161178$8675 + assign { } { } + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:161243.3-161257.6" + process $proc$libresoc.v:161243$8676 + assign { } { } + assign { } { } + assign { } { } + assign $0\st_done_s_st_done$next[0:0]$8677 $2\st_done_s_st_done$next[0:0]$8679 + attribute \src "libresoc.v:161244.5-161244.29" + switch \initial + attribute \src "libresoc.v:161244.9-161244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_s_st_done$next[0:0]$8678 1'1 + case + assign $1\st_done_s_st_done$next[0:0]$8678 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\st_done_s_st_done$next[0:0]$8679 1'0 + case + assign $2\st_done_s_st_done$next[0:0]$8679 $1\st_done_s_st_done$next[0:0]$8678 + end + sync always + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8677 + end + attribute \src "libresoc.v:161258.3-161267.6" + process $proc$libresoc.v:161258$8680 + assign { } { } + assign { } { } + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:161259.5-161259.29" + switch \initial + attribute \src "libresoc.v:161259.9-161259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_r_st_done[0:0] 1'1 + case + assign $1\st_done_r_st_done[0:0] 1'0 + end + sync always + update \st_done_r_st_done $0\st_done_r_st_done[0:0] + end + attribute \src "libresoc.v:161268.3-161276.6" + process $proc$libresoc.v:161268$8681 + assign { } { } + assign { } { } + assign $0\busy_delay$next[0:0]$8682 $1\busy_delay$next[0:0]$8683 + attribute \src "libresoc.v:161269.5-161269.29" + switch \initial + attribute \src "libresoc.v:161269.9-161269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_delay$next[0:0]$8683 1'0 + case + assign $1\busy_delay$next[0:0]$8683 \ldst_port0_busy_o + end + sync always + update \busy_delay$next $0\busy_delay$next[0:0]$8682 + end + attribute \src "libresoc.v:161277.3-161286.6" + process $proc$libresoc.v:161277$8684 + assign { } { } + assign { } { } + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:161278.5-161278.29" + switch \initial + attribute \src "libresoc.v:161278.9-161278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_active_r_st_active[0:0] 1'1 + case + assign $1\st_active_r_st_active[0:0] 1'0 + end + sync always + update \st_active_r_st_active $0\st_active_r_st_active[0:0] + end + attribute \src "libresoc.v:161287.3-161302.6" + process $proc$libresoc.v:161287$8685 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:161288.5-161288.29" + switch \initial + attribute \src "libresoc.v:161288.9-161288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $1\lenexp_len_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] + end + sync always + update \lenexp_len_i $0\lenexp_len_i[3:0] + end + attribute \src "libresoc.v:161303.3-161318.6" + process $proc$libresoc.v:161303$8686 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:161304.5-161304.29" + switch \initial + attribute \src "libresoc.v:161304.9-161304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_addr_i[3:0] \$23 + case + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + end + sync always + update \lenexp_addr_i $0\lenexp_addr_i[3:0] + end + attribute \src "libresoc.v:161319.3-161344.6" + process $proc$libresoc.v:161319$8687 + assign { } { } + assign { } { } + assign { } { } + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:161320.5-161320.29" + switch \initial + attribute \src "libresoc.v:161320.9-161320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + case + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + sync always + update \valid_l_s_valid $0\valid_l_s_valid[0:0] + end + attribute \src "libresoc.v:161345.3-161370.6" + process $proc$libresoc.v:161345$8688 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "libresoc.v:161346.5-161346.29" + switch \initial + attribute \src "libresoc.v:161346.9-161346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end + case + assign $1\x_mask_i[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end + case + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + end + sync always + update \x_mask_i $0\x_mask_i[7:0] + end + attribute \src "libresoc.v:161371.3-161396.6" + process $proc$libresoc.v:161371$8689 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "libresoc.v:161372.5-161372.29" + switch \initial + attribute \src "libresoc.v:161372.9-161372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end + case + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + end + sync always + update \x_addr_i $0\x_addr_i[47:0] + end + attribute \src "libresoc.v:161397.3-161427.6" + process $proc$libresoc.v:161397$8690 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:161398.5-161398.29" + switch \initial + attribute \src "libresoc.v:161398.9-161398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:161428.3-161443.6" + process $proc$libresoc.v:161428$8691 + assign { } { } + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:161429.5-161429.29" + switch \initial + attribute \src "libresoc.v:161429.9-161429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" + switch \st_done_q_st_done + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:161444.3-161453.6" + process $proc$libresoc.v:161444$8692 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:161445.5-161445.29" + switch \initial + attribute \src "libresoc.v:161445.9-161445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:161454.3-161463.6" + process $proc$libresoc.v:161454$8693 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:161455.5-161455.29" + switch \initial + attribute \src "libresoc.v:161455.9-161455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + end + attribute \src "libresoc.v:161464.3-161473.6" + process $proc$libresoc.v:161464$8694 + assign { } { } + assign { } { } + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:161465.5-161465.29" + switch \initial + attribute \src "libresoc.v:161465.9-161465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end + sync always + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + end + attribute \src "libresoc.v:161474.3-161483.6" + process $proc$libresoc.v:161474$8695 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:161475.5-161475.29" + switch \initial + attribute \src "libresoc.v:161475.9-161475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:161484.3-161493.6" + process $proc$libresoc.v:161484$8696 + assign { } { } + assign { } { } + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "libresoc.v:161485.5-161485.29" + switch \initial + attribute \src "libresoc.v:161485.9-161485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata[63:0] \$56 [63:0] + case + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata $0\stdata[63:0] + end + attribute \src "libresoc.v:161494.3-161503.6" + process $proc$libresoc.v:161494$8697 + assign { } { } + assign { } { } + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "libresoc.v:161495.5-161495.29" + switch \initial + attribute \src "libresoc.v:161495.9-161495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_st_data_i[63:0] \stdata + case + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \x_st_data_i $0\x_st_data_i[63:0] + end + attribute \src "libresoc.v:161504.3-161523.6" + process $proc$libresoc.v:161504$8698 + assign { } { } + assign { } { } + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "libresoc.v:161505.5-161505.29" + switch \initial + attribute \src "libresoc.v:161505.9-161505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\lsui_busy[0:0] 1'1 + case + assign $1\lsui_busy[0:0] 1'0 + end + sync always + update \lsui_busy $0\lsui_busy[0:0] + end + attribute \src "libresoc.v:161524.3-161562.6" + process $proc$libresoc.v:161524$8699 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$8700 $5\fsm_state$next[1:0]$8705 + attribute \src "libresoc.v:161525.5-161525.29" + switch \initial + attribute \src "libresoc.v:161525.9-161525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$8701 $2\fsm_state$next[1:0]$8702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$8702 2'01 + case + assign $2\fsm_state$next[1:0]$8702 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$8701 $3\fsm_state$next[1:0]$8703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$8703 2'10 + case + assign $3\fsm_state$next[1:0]$8703 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$8701 $4\fsm_state$next[1:0]$8704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$8704 2'00 + case + assign $4\fsm_state$next[1:0]$8704 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$8701 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$8705 2'00 + case + assign $5\fsm_state$next[1:0]$8705 $1\fsm_state$next[1:0]$8701 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$8700 + end + attribute \src "libresoc.v:161563.3-161572.6" + process $proc$libresoc.v:161563$8706 + assign { } { } + assign { } { } + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:161564.5-161564.29" + switch \initial + attribute \src "libresoc.v:161564.9-161564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" + switch \reset_l_s_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_s_cyc[0:0] 1'1 + case + assign $1\cyc_l_s_cyc[0:0] 1'0 + end + sync always + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + end + attribute \src "libresoc.v:161573.3-161581.6" + process $proc$libresoc.v:161573$8707 + assign { } { } + assign { } { } + assign $0\lsui_active_dly$next[0:0]$8708 $1\lsui_active_dly$next[0:0]$8709 + attribute \src "libresoc.v:161574.5-161574.29" + switch \initial + attribute \src "libresoc.v:161574.9-161574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsui_active_dly$next[0:0]$8709 1'0 + case + assign $1\lsui_active_dly$next[0:0]$8709 \lsui_active + end + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8708 + end + attribute \src "libresoc.v:161582.3-161591.6" + process $proc$libresoc.v:161582$8710 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:161583.5-161583.29" + switch \initial + attribute \src "libresoc.v:161583.9-161583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_r_cyc[0:0] 1'1 + case + assign $1\cyc_l_r_cyc[0:0] 1'0 + end + sync always + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + end + attribute \src "libresoc.v:161592.3-161601.6" + process $proc$libresoc.v:161592$8711 + assign { } { } + assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:161593.5-161593.29" + switch \initial + attribute \src "libresoc.v:161593.9-161593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "libresoc.v:161602.3-161617.6" + process $proc$libresoc.v:161602$8712 + assign { } { } + assign { } { } + assign { } { } + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:161603.5-161603.29" + switch \initial + attribute \src "libresoc.v:161603.9-161603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" + switch \ldst_port0_exc_$signal + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_r_busy[0:0] 1'1 + case + assign $1\busy_l_r_busy[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\busy_l_r_busy[0:0] 1'1 + case + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + end + sync always + update \busy_l_r_busy $0\busy_l_r_busy[0:0] + end + attribute \src "libresoc.v:161618.3-161653.6" + process $proc$libresoc.v:161618$8713 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_s_addr_acked$next[0:0]$8714 $6\adrok_l_s_addr_acked$next[0:0]$8720 + attribute \src "libresoc.v:161619.5-161619.29" + switch \initial + attribute \src "libresoc.v:161619.9-161619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_s_addr_acked$next[0:0]$8715 $2\adrok_l_s_addr_acked$next[0:0]$8716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$8715 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $4\adrok_l_s_addr_acked$next[0:0]$8718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $5\adrok_l_s_addr_acked$next[0:0]$8719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$8719 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$8719 $1\adrok_l_s_addr_acked$next[0:0]$8715 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $1\adrok_l_s_addr_acked$next[0:0]$8715 + end + case + assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $1\adrok_l_s_addr_acked$next[0:0]$8715 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\adrok_l_s_addr_acked$next[0:0]$8720 1'0 + case + assign $6\adrok_l_s_addr_acked$next[0:0]$8720 $3\adrok_l_s_addr_acked$next[0:0]$8717 + end + sync always + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8714 + end + attribute \src "libresoc.v:161654.3-161669.6" + process $proc$libresoc.v:161654$8721 + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:161655.5-161655.29" + switch \initial + attribute \src "libresoc.v:161655.9-161655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + switch \reset_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $1\adrok_l_r_addr_acked[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] + end + sync always + update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] + end + connect \$9 $not$libresoc.v:161123$8625_Y + connect \$11 $and$libresoc.v:161124$8626_Y + connect \$13 $not$libresoc.v:161125$8627_Y + connect \$15 $and$libresoc.v:161126$8628_Y + connect \$17 $not$libresoc.v:161127$8629_Y + connect \$1 $and$libresoc.v:161128$8630_Y + connect \$19 $and$libresoc.v:161129$8631_Y + connect \$21 $pos$libresoc.v:161130$8633_Y + connect \$23 $pos$libresoc.v:161131$8635_Y + connect \$25 $and$libresoc.v:161132$8636_Y + connect \$27 $and$libresoc.v:161133$8637_Y + connect \$29 $and$libresoc.v:161134$8638_Y + connect \$31 $and$libresoc.v:161135$8639_Y + connect \$33 $and$libresoc.v:161136$8640_Y + connect \$35 $not$libresoc.v:161137$8641_Y + connect \$38 $or$libresoc.v:161138$8642_Y + connect \$3 $or$libresoc.v:161139$8643_Y + connect \$37 $not$libresoc.v:161140$8644_Y + connect \$42 $and$libresoc.v:161141$8645_Y + connect \$44 $mul$libresoc.v:161142$8646_Y + connect \$46 $sshr$libresoc.v:161143$8647_Y + connect \$48 $and$libresoc.v:161144$8648_Y + connect \$50 $and$libresoc.v:161145$8649_Y + connect \$52 $not$libresoc.v:161146$8650_Y + connect \$54 $and$libresoc.v:161147$8651_Y + connect \$57 $mul$libresoc.v:161148$8652_Y + connect \$5 $not$libresoc.v:161149$8653_Y + connect \$59 $sshl$libresoc.v:161150$8654_Y + connect \$61 $and$libresoc.v:161151$8655_Y + connect \$63 $or$libresoc.v:161152$8656_Y + connect \$65 $and$libresoc.v:161153$8657_Y + connect \$67 $or$libresoc.v:161154$8658_Y + connect \$69 $and$libresoc.v:161155$8659_Y + connect \$71 $not$libresoc.v:161156$8660_Y + connect \$73 $not$libresoc.v:161157$8661_Y + connect \$75 $not$libresoc.v:161158$8662_Y + connect \$77 $and$libresoc.v:161159$8663_Y + connect \$7 $and$libresoc.v:161160$8664_Y + connect \$79 $not$libresoc.v:161161$8665_Y + connect \$81 $not$libresoc.v:161162$8666_Y + connect \$83 $and$libresoc.v:161163$8667_Y + connect \$41 \$46 + connect \$56 \$59 + connect \valid_l_r_valid \lsui_active_rise + connect \lsui_active_rise \$83 + connect \lsui_active \$79 + connect \x_valid_i \valid_l_q_valid + connect \m_valid_i \valid_l_q_valid + connect \x_st_i \ldst_port0_is_st_i + connect \x_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_busy_o \busy_l_q_busy + connect \reset_delay$next \reset_l_q_reset + connect \lddata \$46 [63:0] + connect \st_active_s_st_active \sts_rise + connect \sts_rise \$19 + connect \sts_dly$next \sts + connect \ld_active_s_ld_active \lds_rise + connect \lds_rise \$15 + connect \lds_dly$next \lds + connect \busy_edge \$11 + connect \sts \ldst_port0_is_st_i + connect \lds \ldst_port0_is_ld_i +end +attribute \src "libresoc.v:161695.1-162475.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" +attribute \generator "nMigen" +module \pipe + attribute \src "libresoc.v:162438.3-162456.6" + wire width 4 $0\cr_a$6$next[3:0]$8777 + attribute \src "libresoc.v:162302.3-162303.31" + wire width 4 $0\cr_a$6[3:0]$8733 + attribute \src "libresoc.v:161709.13-161709.28" + wire width 4 $0\cr_a$6[3:0]$8783 + attribute \src "libresoc.v:162438.3-162456.6" + wire $0\cr_a_ok$next[0:0]$8776 + attribute \src "libresoc.v:162304.3-162305.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:162385.3-162399.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8757 + attribute \src "libresoc.v:162316.3-162317.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8743 + attribute \src "libresoc.v:161774.14-161774.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8786 + attribute \src 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"OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute 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\enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 10 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 22 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$next + attribute \src "libresoc.v:161696.7-161696.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_cr_op__fn_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$10 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \main_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \main_full_cr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 14 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:162301$8731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$13 + connect \B \p_ready_o + connect \Y $and$libresoc.v:162301$8731_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:162324.12-162345.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:162346.9-162349.4" + cell \n$8 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:162350.9-162353.4" + cell \p$7 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:161696.7-161696.20" + process $proc$libresoc.v:161696$8781 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:161709.13-161709.28" + process $proc$libresoc.v:161709$8782 + assign { } { } + assign $0\cr_a$6[3:0]$8783 4'0000 + sync always + sync init + update \cr_a$6 $0\cr_a$6[3:0]$8783 + end + attribute \src "libresoc.v:161714.7-161714.21" + process $proc$libresoc.v:161714$8784 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:161774.14-161774.43" + process $proc$libresoc.v:161774$8785 + assign { } { } + assign $0\cr_op__fn_unit$3[13:0]$8786 14'00000000000000 + sync always + sync init + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8786 + end + attribute \src "libresoc.v:161783.14-161783.37" + process $proc$libresoc.v:161783$8787 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8788 0 + sync always + sync init + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8788 + end + attribute \src "libresoc.v:162017.13-162017.41" + process $proc$libresoc.v:162017$8789 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8790 7'0000000 + sync always + sync init + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8790 + end + attribute \src "libresoc.v:162026.14-162026.33" + process $proc$libresoc.v:162026$8791 + assign { } { } + assign $0\full_cr$5[31:0]$8792 0 + sync always + sync init + update \full_cr$5 $0\full_cr$5[31:0]$8792 + end + attribute \src "libresoc.v:162031.7-162031.24" + process $proc$libresoc.v:162031$8793 + assign { } { } + assign $1\full_cr_ok[0:0] 1'0 + sync always + sync init + update \full_cr_ok $1\full_cr_ok[0:0] + end + attribute \src "libresoc.v:162260.13-162260.29" + process $proc$libresoc.v:162260$8794 + assign { } { } + assign $0\muxid$1[1:0]$8795 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8795 + end + attribute \src "libresoc.v:162273.14-162273.38" + process $proc$libresoc.v:162273$8796 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:162280.7-162280.18" + process $proc$libresoc.v:162280$8797 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:162294.7-162294.20" + process $proc$libresoc.v:162294$8798 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:162302.3-162303.31" + process $proc$libresoc.v:162302$8732 + assign { } { } + assign $0\cr_a$6[3:0]$8733 \cr_a$6$next + sync posedge \coresync_clk + update \cr_a$6 $0\cr_a$6[3:0]$8733 + end + attribute \src "libresoc.v:162304.3-162305.31" + process $proc$libresoc.v:162304$8734 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:162306.3-162307.37" + process $proc$libresoc.v:162306$8735 + assign { } { } + assign $0\full_cr$5[31:0]$8736 \full_cr$5$next + sync posedge \coresync_clk + update \full_cr$5 $0\full_cr$5[31:0]$8736 + end + attribute \src "libresoc.v:162308.3-162309.37" + process $proc$libresoc.v:162308$8737 + assign { } { } + assign $0\full_cr_ok[0:0] \full_cr_ok$next + sync posedge \coresync_clk + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:162310.3-162311.19" + process $proc$libresoc.v:162310$8738 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:162312.3-162313.25" + process $proc$libresoc.v:162312$8739 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:162314.3-162315.55" + process $proc$libresoc.v:162314$8740 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8741 \cr_op__insn_type$2$next + sync posedge \coresync_clk + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8741 + end + attribute \src "libresoc.v:162316.3-162317.51" + process $proc$libresoc.v:162316$8742 + assign { } { } + assign $0\cr_op__fn_unit$3[13:0]$8743 \cr_op__fn_unit$3$next + sync posedge \coresync_clk + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8743 + end + attribute \src "libresoc.v:162318.3-162319.45" + process $proc$libresoc.v:162318$8744 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8745 \cr_op__insn$4$next + sync posedge \coresync_clk + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8745 + end + attribute \src "libresoc.v:162320.3-162321.33" + process $proc$libresoc.v:162320$8746 + assign { } { } + assign $0\muxid$1[1:0]$8747 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8747 + end + attribute \src "libresoc.v:162322.3-162323.29" + process $proc$libresoc.v:162322$8748 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:162354.3-162371.6" + process $proc$libresoc.v:162354$8749 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8750 $2\r_busy$next[0:0]$8752 + attribute \src "libresoc.v:162355.5-162355.29" + switch \initial + attribute \src "libresoc.v:162355.9-162355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8751 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8751 1'0 + case + assign $1\r_busy$next[0:0]$8751 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8752 1'0 + case + assign $2\r_busy$next[0:0]$8752 $1\r_busy$next[0:0]$8751 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8750 + end + attribute \src "libresoc.v:162372.3-162384.6" + process $proc$libresoc.v:162372$8753 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8754 $1\muxid$1$next[1:0]$8755 + attribute \src "libresoc.v:162373.5-162373.29" + switch \initial + attribute \src "libresoc.v:162373.9-162373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8755 \muxid$16 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8755 \muxid$16 + case + assign $1\muxid$1$next[1:0]$8755 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8754 + end + attribute \src "libresoc.v:162385.3-162399.6" + process $proc$libresoc.v:162385$8756 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_op__fn_unit$3$next[13:0]$8757 $1\cr_op__fn_unit$3$next[13:0]$8760 + assign $0\cr_op__insn$4$next[31:0]$8758 $1\cr_op__insn$4$next[31:0]$8761 + assign $0\cr_op__insn_type$2$next[6:0]$8759 $1\cr_op__insn_type$2$next[6:0]$8762 + attribute \src "libresoc.v:162386.5-162386.29" + switch \initial + attribute \src "libresoc.v:162386.9-162386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + case + assign $1\cr_op__fn_unit$3$next[13:0]$8760 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8761 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8762 \cr_op__insn_type$2 + end + sync always + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8757 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8758 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8759 + end + attribute \src "libresoc.v:162400.3-162418.6" + process $proc$libresoc.v:162400$8763 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8764 $1\o$next[63:0]$8766 + assign { } { } + assign $0\o_ok$next[0:0]$8765 $2\o_ok$next[0:0]$8768 + attribute \src "libresoc.v:162401.5-162401.29" + switch \initial + attribute \src "libresoc.v:162401.9-162401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } + case + assign $1\o$next[63:0]$8766 \o + assign $1\o_ok$next[0:0]$8767 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8768 1'0 + case + assign $2\o_ok$next[0:0]$8768 $1\o_ok$next[0:0]$8767 + end + sync always + update \o$next $0\o$next[63:0]$8764 + update \o_ok$next $0\o_ok$next[0:0]$8765 + end + attribute \src "libresoc.v:162419.3-162437.6" + process $proc$libresoc.v:162419$8769 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\full_cr$5$next[31:0]$8770 $1\full_cr$5$next[31:0]$8772 + assign { } { } + assign $0\full_cr_ok$next[0:0]$8771 $2\full_cr_ok$next[0:0]$8774 + attribute \src "libresoc.v:162420.5-162420.29" + switch \initial + attribute \src "libresoc.v:162420.9-162420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } + case + assign $1\full_cr$5$next[31:0]$8772 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8773 \full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\full_cr_ok$next[0:0]$8774 1'0 + case + assign $2\full_cr_ok$next[0:0]$8774 $1\full_cr_ok$next[0:0]$8773 + end + sync always + update \full_cr$5$next $0\full_cr$5$next[31:0]$8770 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8771 + end + attribute \src "libresoc.v:162438.3-162456.6" + process $proc$libresoc.v:162438$8775 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$6$next[3:0]$8777 $1\cr_a$6$next[3:0]$8779 + assign $0\cr_a_ok$next[0:0]$8776 $2\cr_a_ok$next[0:0]$8780 + attribute \src "libresoc.v:162439.5-162439.29" + switch \initial + attribute \src "libresoc.v:162439.9-162439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } + case + assign $1\cr_a_ok$next[0:0]$8778 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8779 \cr_a$6 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8780 1'0 + case + assign $2\cr_a_ok$next[0:0]$8780 $1\cr_a_ok$next[0:0]$8778 + end + sync always + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8776 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8777 + end + connect \$14 $and$libresoc.v:162301$8731_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:162479.1-163339.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" +attribute \generator "nMigen" +module \pipe$19 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8835 + attribute \src "libresoc.v:163151.3-163152.43" + wire width 64 $0\br_op__cia$2[63:0]$8809 + attribute \src "libresoc.v:162487.14-162487.51" + wire width 64 $0\br_op__cia$2[63:0]$8873 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 14 $0\br_op__fn_unit$4$next[13:0]$8836 + attribute \src "libresoc.v:163155.3-163156.51" + wire width 14 $0\br_op__fn_unit$4[13:0]$8813 + attribute \src "libresoc.v:162543.14-162543.43" + wire width 14 $0\br_op__fn_unit$4[13:0]$8875 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8837 + attribute \src "libresoc.v:163159.3-163160.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8817 + attribute \src "libresoc.v:162552.14-162552.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8877 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8838 + attribute \src "libresoc.v:163161.3-163162.61" + wire $0\br_op__imm_data__ok$7[0:0]$8819 + attribute \src "libresoc.v:162561.7-162561.37" + wire $0\br_op__imm_data__ok$7[0:0]$8879 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8839 + attribute \src "libresoc.v:163157.3-163158.45" + wire width 32 $0\br_op__insn$5[31:0]$8815 + attribute \src "libresoc.v:162570.14-162570.37" + wire width 32 $0\br_op__insn$5[31:0]$8881 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8840 + attribute \src "libresoc.v:163153.3-163154.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8811 + attribute \src "libresoc.v:162804.13-162804.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8883 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__is_32bit$9$next[0:0]$8841 + attribute \src "libresoc.v:163165.3-163166.53" + wire $0\br_op__is_32bit$9[0:0]$8823 + attribute \src "libresoc.v:162813.7-162813.33" + wire $0\br_op__is_32bit$9[0:0]$8885 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__lk$8$next[0:0]$8842 + attribute \src "libresoc.v:163163.3-163164.41" + wire $0\br_op__lk$8[0:0]$8821 + attribute \src "libresoc.v:162822.7-162822.27" + wire $0\br_op__lk$8[0:0]$8887 + attribute \src "libresoc.v:163267.3-163285.6" + wire width 64 $0\fast1$10$next[63:0]$8854 + attribute \src "libresoc.v:163147.3-163148.35" + wire width 64 $0\fast1$10[63:0]$8806 + attribute \src "libresoc.v:162835.14-162835.47" + wire width 64 $0\fast1$10[63:0]$8889 + attribute \src "libresoc.v:163267.3-163285.6" + wire $0\fast1_ok$next[0:0]$8855 + attribute \src "libresoc.v:163149.3-163150.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:163286.3-163304.6" + wire width 64 $0\fast2$11$next[63:0]$8860 + attribute \src "libresoc.v:163143.3-163144.35" + wire width 64 $0\fast2$11[63:0]$8803 + attribute \src "libresoc.v:162851.14-162851.47" + wire width 64 $0\fast2$11[63:0]$8892 + attribute \src "libresoc.v:163286.3-163304.6" + wire $0\fast2_ok$next[0:0]$8861 + attribute \src "libresoc.v:163145.3-163146.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:162480.7-162480.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:163226.3-163238.6" + wire width 2 $0\muxid$1$next[1:0]$8832 + attribute \src "libresoc.v:163167.3-163168.33" + wire width 2 $0\muxid$1[1:0]$8825 + attribute \src "libresoc.v:163101.13-163101.29" + wire width 2 $0\muxid$1[1:0]$8895 + attribute \src "libresoc.v:163305.3-163323.6" + wire width 64 $0\nia$next[63:0]$8866 + attribute \src "libresoc.v:163139.3-163140.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:163305.3-163323.6" + wire $0\nia_ok$next[0:0]$8867 + attribute \src "libresoc.v:163141.3-163142.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:163208.3-163225.6" + wire $0\r_busy$next[0:0]$8828 + attribute \src "libresoc.v:163169.3-163170.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8843 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8844 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8845 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8846 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8847 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8848 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__is_32bit$9$next[0:0]$8849 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__lk$8$next[0:0]$8850 + attribute \src "libresoc.v:163267.3-163285.6" + wire width 64 $1\fast1$10$next[63:0]$8856 + attribute \src "libresoc.v:163267.3-163285.6" + wire $1\fast1_ok$next[0:0]$8857 + attribute \src "libresoc.v:162842.7-162842.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:163286.3-163304.6" + wire width 64 $1\fast2$11$next[63:0]$8862 + attribute \src "libresoc.v:163286.3-163304.6" + wire $1\fast2_ok$next[0:0]$8863 + attribute \src "libresoc.v:162858.7-162858.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:163226.3-163238.6" + wire width 2 $1\muxid$1$next[1:0]$8833 + attribute \src "libresoc.v:163305.3-163323.6" + wire width 64 $1\nia$next[63:0]$8868 + attribute \src "libresoc.v:163114.14-163114.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:163305.3-163323.6" + wire $1\nia_ok$next[0:0]$8869 + attribute \src "libresoc.v:163121.7-163121.20" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:163208.3-163225.6" + wire $1\r_busy$next[0:0]$8829 + attribute \src "libresoc.v:163135.7-163135.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8851 + attribute \src "libresoc.v:163239.3-163266.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8852 + attribute \src "libresoc.v:163267.3-163285.6" + wire $2\fast1_ok$next[0:0]$8858 + attribute \src "libresoc.v:163286.3-163304.6" + wire $2\fast2_ok$next[0:0]$8864 + attribute \src "libresoc.v:163305.3-163323.6" + wire $2\nia_ok$next[0:0]$8870 + attribute \src "libresoc.v:163208.3-163225.6" + wire $2\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:163138.18-163138.118" + wire $and$libresoc.v:163138$8799_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \br_op__cia$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$27 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$29 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:162480.7-162480.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_br_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:163138$8799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$libresoc.v:163138$8799_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:163171.13-163199.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 + connect \cr_a \main_cr_a + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:163200.10-163203.4" + cell \n$21 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:163204.10-163207.4" + cell \p$20 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:162480.7-162480.20" + process $proc$libresoc.v:162480$8871 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:162487.14-162487.51" + process $proc$libresoc.v:162487$8872 + assign { } { } + assign $0\br_op__cia$2[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8873 + end + attribute \src "libresoc.v:162543.14-162543.43" + process $proc$libresoc.v:162543$8874 + assign { } { } + assign $0\br_op__fn_unit$4[13:0]$8875 14'00000000000000 + sync always + sync init + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8875 + end + attribute \src "libresoc.v:162552.14-162552.62" + process $proc$libresoc.v:162552$8876 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8877 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8877 + end + attribute \src "libresoc.v:162561.7-162561.37" + process $proc$libresoc.v:162561$8878 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8879 1'0 + sync always + sync init + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8879 + end + attribute \src "libresoc.v:162570.14-162570.37" + process $proc$libresoc.v:162570$8880 + assign { } { } + assign $0\br_op__insn$5[31:0]$8881 0 + sync always + sync init + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8881 + end + attribute \src "libresoc.v:162804.13-162804.41" + process $proc$libresoc.v:162804$8882 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8883 7'0000000 + sync always + sync init + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8883 + end + attribute \src "libresoc.v:162813.7-162813.33" + process $proc$libresoc.v:162813$8884 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8885 1'0 + sync always + sync init + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8885 + end + attribute \src "libresoc.v:162822.7-162822.27" + process $proc$libresoc.v:162822$8886 + assign { } { } + assign $0\br_op__lk$8[0:0]$8887 1'0 + sync always + sync init + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8887 + end + attribute \src "libresoc.v:162835.14-162835.47" + process $proc$libresoc.v:162835$8888 + assign { } { } + assign $0\fast1$10[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$8889 + end + attribute \src "libresoc.v:162842.7-162842.22" + process $proc$libresoc.v:162842$8890 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:162851.14-162851.47" + process $proc$libresoc.v:162851$8891 + assign { } { } + assign $0\fast2$11[63:0]$8892 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$8892 + end + attribute \src "libresoc.v:162858.7-162858.22" + process $proc$libresoc.v:162858$8893 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:163101.13-163101.29" + process $proc$libresoc.v:163101$8894 + assign { } { } + assign $0\muxid$1[1:0]$8895 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8895 + end + attribute \src "libresoc.v:163114.14-163114.40" + process $proc$libresoc.v:163114$8896 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:163121.7-163121.20" + process $proc$libresoc.v:163121$8897 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:163135.7-163135.20" + process $proc$libresoc.v:163135$8898 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:163139.3-163140.23" + process $proc$libresoc.v:163139$8800 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:163141.3-163142.29" + process $proc$libresoc.v:163141$8801 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:163143.3-163144.35" + process $proc$libresoc.v:163143$8802 + assign { } { } + assign $0\fast2$11[63:0]$8803 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$8803 + end + attribute \src "libresoc.v:163145.3-163146.33" + process $proc$libresoc.v:163145$8804 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:163147.3-163148.35" + process $proc$libresoc.v:163147$8805 + assign { } { } + assign $0\fast1$10[63:0]$8806 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$8806 + end + attribute \src "libresoc.v:163149.3-163150.33" + process $proc$libresoc.v:163149$8807 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:163151.3-163152.43" + process $proc$libresoc.v:163151$8808 + assign { } { } + assign $0\br_op__cia$2[63:0]$8809 \br_op__cia$2$next + sync posedge \coresync_clk + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8809 + end + attribute \src "libresoc.v:163153.3-163154.55" + process $proc$libresoc.v:163153$8810 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8811 \br_op__insn_type$3$next + sync posedge \coresync_clk + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8811 + end + attribute \src "libresoc.v:163155.3-163156.51" + process $proc$libresoc.v:163155$8812 + assign { } { } + assign $0\br_op__fn_unit$4[13:0]$8813 \br_op__fn_unit$4$next + sync posedge \coresync_clk + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8813 + end + attribute \src "libresoc.v:163157.3-163158.45" + process $proc$libresoc.v:163157$8814 + assign { } { } + assign $0\br_op__insn$5[31:0]$8815 \br_op__insn$5$next + sync posedge \coresync_clk + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8815 + end + attribute \src "libresoc.v:163159.3-163160.65" + process $proc$libresoc.v:163159$8816 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8817 \br_op__imm_data__data$6$next + sync posedge \coresync_clk + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8817 + end + attribute \src "libresoc.v:163161.3-163162.61" + process $proc$libresoc.v:163161$8818 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8819 \br_op__imm_data__ok$7$next + sync posedge \coresync_clk + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8819 + end + attribute \src "libresoc.v:163163.3-163164.41" + process $proc$libresoc.v:163163$8820 + assign { } { } + assign $0\br_op__lk$8[0:0]$8821 \br_op__lk$8$next + sync posedge \coresync_clk + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8821 + end + attribute \src "libresoc.v:163165.3-163166.53" + process $proc$libresoc.v:163165$8822 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8823 \br_op__is_32bit$9$next + sync posedge \coresync_clk + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8823 + end + attribute \src "libresoc.v:163167.3-163168.33" + process $proc$libresoc.v:163167$8824 + assign { } { } + assign $0\muxid$1[1:0]$8825 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8825 + end + attribute \src "libresoc.v:163169.3-163170.29" + process $proc$libresoc.v:163169$8826 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:163208.3-163225.6" + process $proc$libresoc.v:163208$8827 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8828 $2\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:163209.5-163209.29" + switch \initial + attribute \src "libresoc.v:163209.9-163209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8829 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8829 1'0 + case + assign $1\r_busy$next[0:0]$8829 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8830 1'0 + case + assign $2\r_busy$next[0:0]$8830 $1\r_busy$next[0:0]$8829 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8828 + end + attribute \src "libresoc.v:163226.3-163238.6" + process $proc$libresoc.v:163226$8831 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8832 $1\muxid$1$next[1:0]$8833 + attribute \src "libresoc.v:163227.5-163227.29" + switch \initial + attribute \src "libresoc.v:163227.9-163227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8833 \muxid$26 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8833 \muxid$26 + case + assign $1\muxid$1$next[1:0]$8833 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8832 + end + attribute \src "libresoc.v:163239.3-163266.6" + process $proc$libresoc.v:163239$8834 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\br_op__cia$2$next[63:0]$8835 $1\br_op__cia$2$next[63:0]$8843 + assign $0\br_op__fn_unit$4$next[13:0]$8836 $1\br_op__fn_unit$4$next[13:0]$8844 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$8839 $1\br_op__insn$5$next[31:0]$8847 + assign $0\br_op__insn_type$3$next[6:0]$8840 $1\br_op__insn_type$3$next[6:0]$8848 + assign $0\br_op__is_32bit$9$next[0:0]$8841 $1\br_op__is_32bit$9$next[0:0]$8849 + assign $0\br_op__lk$8$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8850 + assign $0\br_op__imm_data__data$6$next[63:0]$8837 $2\br_op__imm_data__data$6$next[63:0]$8851 + assign $0\br_op__imm_data__ok$7$next[0:0]$8838 $2\br_op__imm_data__ok$7$next[0:0]$8852 + attribute \src "libresoc.v:163240.5-163240.29" + switch \initial + attribute \src "libresoc.v:163240.9-163240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + case + assign $1\br_op__cia$2$next[63:0]$8843 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8844 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8845 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8846 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8847 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8848 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8849 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8850 \br_op__lk$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$8851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8852 1'0 + case + assign $2\br_op__imm_data__data$6$next[63:0]$8851 $1\br_op__imm_data__data$6$next[63:0]$8845 + assign $2\br_op__imm_data__ok$7$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8846 + end + sync always + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8835 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8836 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8837 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8838 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8839 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8840 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8841 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8842 + end + attribute \src "libresoc.v:163267.3-163285.6" + process $proc$libresoc.v:163267$8853 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$8854 $1\fast1$10$next[63:0]$8856 + assign { } { } + assign $0\fast1_ok$next[0:0]$8855 $2\fast1_ok$next[0:0]$8858 + attribute \src "libresoc.v:163268.5-163268.29" + switch \initial + attribute \src "libresoc.v:163268.9-163268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } + case + assign $1\fast1$10$next[63:0]$8856 \fast1$10 + assign $1\fast1_ok$next[0:0]$8857 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8858 1'0 + case + assign $2\fast1_ok$next[0:0]$8858 $1\fast1_ok$next[0:0]$8857 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$8854 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8855 + end + attribute \src "libresoc.v:163286.3-163304.6" + process $proc$libresoc.v:163286$8859 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$8860 $1\fast2$11$next[63:0]$8862 + assign { } { } + assign $0\fast2_ok$next[0:0]$8861 $2\fast2_ok$next[0:0]$8864 + attribute \src "libresoc.v:163287.5-163287.29" + switch \initial + attribute \src "libresoc.v:163287.9-163287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } + case + assign $1\fast2$11$next[63:0]$8862 \fast2$11 + assign $1\fast2_ok$next[0:0]$8863 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$8864 1'0 + case + assign $2\fast2_ok$next[0:0]$8864 $1\fast2_ok$next[0:0]$8863 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$8860 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8861 + end + attribute \src "libresoc.v:163305.3-163323.6" + process $proc$libresoc.v:163305$8865 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$8866 $1\nia$next[63:0]$8868 + assign { } { } + assign $0\nia_ok$next[0:0]$8867 $2\nia_ok$next[0:0]$8870 + attribute \src "libresoc.v:163306.5-163306.29" + switch \initial + attribute \src "libresoc.v:163306.9-163306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } + case + assign $1\nia$next[63:0]$8868 \nia + assign $1\nia_ok$next[0:0]$8869 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$8870 1'0 + case + assign $2\nia_ok$next[0:0]$8870 $1\nia_ok$next[0:0]$8869 + end + sync always + update \nia$next $0\nia$next[63:0]$8866 + update \nia_ok$next $0\nia_ok$next[0:0]$8867 + end + connect \$24 $and$libresoc.v:163138$8799_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:163343.1-164273.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" +attribute \generator "nMigen" +module \pipe$64 + attribute \src "libresoc.v:164176.3-164194.6" + wire width 64 $0\fast1$7$next[63:0]$8958 + attribute \src "libresoc.v:164029.3-164030.33" + wire width 64 $0\fast1$7[63:0]$8910 + attribute \src "libresoc.v:163357.14-163357.46" + wire width 64 $0\fast1$7[63:0]$8982 + attribute \src "libresoc.v:164176.3-164194.6" + wire $0\fast1_ok$next[0:0]$8957 + attribute \src "libresoc.v:164031.3-164032.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:163344.7-163344.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:164109.3-164121.6" + wire width 2 $0\muxid$1$next[1:0]$8933 + attribute \src "libresoc.v:164049.3-164050.33" + wire width 2 $0\muxid$1[1:0]$8926 + attribute \src "libresoc.v:163371.13-163371.29" + wire width 2 $0\muxid$1[1:0]$8985 + attribute \src "libresoc.v:164138.3-164156.6" + wire width 64 $0\o$next[63:0]$8945 + attribute \src "libresoc.v:164037.3-164038.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:164138.3-164156.6" + wire $0\o_ok$next[0:0]$8946 + attribute \src "libresoc.v:164039.3-164040.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:164091.3-164108.6" + wire $0\r_busy$next[0:0]$8929 + attribute \src "libresoc.v:164051.3-164052.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:164157.3-164175.6" + wire width 64 $0\spr1$6$next[63:0]$8951 + attribute \src "libresoc.v:164033.3-164034.31" + wire width 64 $0\spr1$6[63:0]$8913 + attribute \src "libresoc.v:163416.14-163416.45" + wire width 64 $0\spr1$6[63:0]$8990 + attribute \src "libresoc.v:164157.3-164175.6" + wire $0\spr1_ok$next[0:0]$8952 + attribute \src "libresoc.v:164035.3-164036.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:164122.3-164137.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8936 + attribute \src "libresoc.v:164043.3-164044.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8920 + attribute \src "libresoc.v:163713.14-163713.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8993 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8937 + attribute \src "libresoc.v:164045.3-164046.47" + wire width 32 $0\spr_op__insn$4[31:0]$8922 + attribute \src "libresoc.v:163722.14-163722.38" + wire width 32 $0\spr_op__insn$4[31:0]$8995 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8938 + attribute \src "libresoc.v:164041.3-164042.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8918 + attribute \src "libresoc.v:163879.13-163879.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8997 + attribute \src "libresoc.v:164122.3-164137.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8939 + attribute \src "libresoc.v:164047.3-164048.55" + wire $0\spr_op__is_32bit$5[0:0]$8924 + attribute \src "libresoc.v:163965.7-163965.34" + wire $0\spr_op__is_32bit$5[0:0]$8999 + attribute \src "libresoc.v:164233.3-164251.6" + wire width 2 $0\xer_ca$10$next[1:0]$8975 + attribute \src "libresoc.v:164017.3-164018.37" + wire width 2 $0\xer_ca$10[1:0]$8901 + attribute \src "libresoc.v:163972.13-163972.31" + wire width 2 $0\xer_ca$10[1:0]$9001 + attribute \src "libresoc.v:164233.3-164251.6" + wire $0\xer_ca_ok$next[0:0]$8976 + attribute \src "libresoc.v:164019.3-164020.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:164214.3-164232.6" + wire width 2 $0\xer_ov$9$next[1:0]$8970 + attribute \src "libresoc.v:164021.3-164022.35" + wire width 2 $0\xer_ov$9[1:0]$8904 + attribute \src "libresoc.v:163990.13-163990.30" + wire width 2 $0\xer_ov$9[1:0]$9004 + attribute \src "libresoc.v:164214.3-164232.6" + wire $0\xer_ov_ok$next[0:0]$8969 + attribute \src "libresoc.v:164023.3-164024.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:164195.3-164213.6" + wire $0\xer_so$8$next[0:0]$8964 + attribute \src "libresoc.v:164025.3-164026.35" + wire $0\xer_so$8[0:0]$8907 + attribute \src "libresoc.v:164006.7-164006.24" + wire $0\xer_so$8[0:0]$9007 + attribute \src "libresoc.v:164195.3-164213.6" + wire $0\xer_so_ok$next[0:0]$8963 + attribute \src "libresoc.v:164027.3-164028.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:164176.3-164194.6" + wire width 64 $1\fast1$7$next[63:0]$8960 + attribute \src "libresoc.v:164176.3-164194.6" + wire $1\fast1_ok$next[0:0]$8959 + attribute \src "libresoc.v:163362.7-163362.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:164109.3-164121.6" + wire width 2 $1\muxid$1$next[1:0]$8934 + attribute \src "libresoc.v:164138.3-164156.6" + wire width 64 $1\o$next[63:0]$8947 + attribute \src "libresoc.v:163384.14-163384.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:164138.3-164156.6" + wire $1\o_ok$next[0:0]$8948 + attribute \src "libresoc.v:163391.7-163391.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:164091.3-164108.6" + wire $1\r_busy$next[0:0]$8930 + attribute \src "libresoc.v:163405.7-163405.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:164157.3-164175.6" + wire width 64 $1\spr1$6$next[63:0]$8953 + attribute \src "libresoc.v:164157.3-164175.6" + wire $1\spr1_ok$next[0:0]$8954 + attribute \src "libresoc.v:163421.7-163421.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:164122.3-164137.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8940 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8941 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8942 + attribute \src "libresoc.v:164122.3-164137.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8943 + attribute \src "libresoc.v:164233.3-164251.6" + wire width 2 $1\xer_ca$10$next[1:0]$8977 + attribute \src "libresoc.v:164233.3-164251.6" + wire $1\xer_ca_ok$next[0:0]$8978 + attribute \src "libresoc.v:163979.7-163979.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:164214.3-164232.6" + wire width 2 $1\xer_ov$9$next[1:0]$8972 + attribute \src "libresoc.v:164214.3-164232.6" + wire $1\xer_ov_ok$next[0:0]$8971 + attribute \src "libresoc.v:163995.7-163995.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:164195.3-164213.6" + wire $1\xer_so$8$next[0:0]$8966 + attribute \src "libresoc.v:164195.3-164213.6" + wire $1\xer_so_ok$next[0:0]$8965 + attribute \src "libresoc.v:164011.7-164011.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:164176.3-164194.6" + wire $2\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:164138.3-164156.6" + wire $2\o_ok$next[0:0]$8949 + attribute \src "libresoc.v:164091.3-164108.6" + wire $2\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:164157.3-164175.6" + wire $2\spr1_ok$next[0:0]$8955 + attribute \src "libresoc.v:164233.3-164251.6" + wire $2\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:164214.3-164232.6" + wire $2\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:164195.3-164213.6" + wire $2\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:164016.18-164016.118" + wire $and$libresoc.v:164016$8899_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "libresoc.v:163344.7-163344.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \spr_main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_main_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_main_spr_op__fn_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_main_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_main_spr_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute 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\enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:164016$8899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$21 + connect \B \p_ready_o + connect \Y $and$libresoc.v:164016$8899_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164053.10-164056.4" + cell \n$66 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164057.10-164060.4" + cell \p$65 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164061.12-164090.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:163344.7-163344.20" + process $proc$libresoc.v:163344$8980 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:163357.14-163357.46" + process $proc$libresoc.v:163357$8981 + assign { } { } + assign $0\fast1$7[63:0]$8982 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$7 $0\fast1$7[63:0]$8982 + end + attribute \src "libresoc.v:163362.7-163362.22" + process $proc$libresoc.v:163362$8983 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:163371.13-163371.29" + process $proc$libresoc.v:163371$8984 + assign { } { } + assign $0\muxid$1[1:0]$8985 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8985 + end + attribute \src "libresoc.v:163384.14-163384.38" + process $proc$libresoc.v:163384$8986 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:163391.7-163391.18" + process $proc$libresoc.v:163391$8987 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:163405.7-163405.20" + process $proc$libresoc.v:163405$8988 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:163416.14-163416.45" + process $proc$libresoc.v:163416$8989 + assign { } { } + assign $0\spr1$6[63:0]$8990 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \spr1$6 $0\spr1$6[63:0]$8990 + end + attribute \src "libresoc.v:163421.7-163421.21" + process $proc$libresoc.v:163421$8991 + assign { } { } + assign $1\spr1_ok[0:0] 1'0 + sync always + sync init + update \spr1_ok $1\spr1_ok[0:0] + end + attribute \src "libresoc.v:163713.14-163713.44" + process $proc$libresoc.v:163713$8992 + assign { } { } + assign $0\spr_op__fn_unit$3[13:0]$8993 14'00000000000000 + sync always + sync init + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8993 + end + attribute \src "libresoc.v:163722.14-163722.38" + process $proc$libresoc.v:163722$8994 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8995 0 + sync always + sync init + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8995 + end + attribute \src "libresoc.v:163879.13-163879.42" + process $proc$libresoc.v:163879$8996 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8997 7'0000000 + sync always + sync init + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8997 + end + attribute \src "libresoc.v:163965.7-163965.34" + process $proc$libresoc.v:163965$8998 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8999 1'0 + sync always + sync init + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8999 + end + attribute \src "libresoc.v:163972.13-163972.31" + process $proc$libresoc.v:163972$9000 + assign { } { } + assign $0\xer_ca$10[1:0]$9001 2'00 + sync always + sync init + update \xer_ca$10 $0\xer_ca$10[1:0]$9001 + end + attribute \src "libresoc.v:163979.7-163979.23" + process $proc$libresoc.v:163979$9002 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:163990.13-163990.30" + process $proc$libresoc.v:163990$9003 + assign { } { } + assign $0\xer_ov$9[1:0]$9004 2'00 + sync always + sync init + update \xer_ov$9 $0\xer_ov$9[1:0]$9004 + end + attribute \src "libresoc.v:163995.7-163995.23" + process $proc$libresoc.v:163995$9005 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:164006.7-164006.24" + process $proc$libresoc.v:164006$9006 + assign { } { } + assign $0\xer_so$8[0:0]$9007 1'0 + sync always + sync init + update \xer_so$8 $0\xer_so$8[0:0]$9007 + end + attribute \src "libresoc.v:164011.7-164011.23" + process $proc$libresoc.v:164011$9008 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:164017.3-164018.37" + process $proc$libresoc.v:164017$8900 + assign { } { } + assign $0\xer_ca$10[1:0]$8901 \xer_ca$10$next + sync posedge \coresync_clk + update \xer_ca$10 $0\xer_ca$10[1:0]$8901 + end + attribute \src "libresoc.v:164019.3-164020.35" + process $proc$libresoc.v:164019$8902 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:164021.3-164022.35" + process $proc$libresoc.v:164021$8903 + assign { } { } + assign $0\xer_ov$9[1:0]$8904 \xer_ov$9$next + sync posedge \coresync_clk + update \xer_ov$9 $0\xer_ov$9[1:0]$8904 + end + attribute \src "libresoc.v:164023.3-164024.35" + process $proc$libresoc.v:164023$8905 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:164025.3-164026.35" + process $proc$libresoc.v:164025$8906 + assign { } { } + assign $0\xer_so$8[0:0]$8907 \xer_so$8$next + sync posedge \coresync_clk + update \xer_so$8 $0\xer_so$8[0:0]$8907 + end + attribute \src "libresoc.v:164027.3-164028.35" + process $proc$libresoc.v:164027$8908 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:164029.3-164030.33" + process $proc$libresoc.v:164029$8909 + assign { } { } + assign $0\fast1$7[63:0]$8910 \fast1$7$next + sync posedge \coresync_clk + update \fast1$7 $0\fast1$7[63:0]$8910 + end + attribute \src "libresoc.v:164031.3-164032.33" + process $proc$libresoc.v:164031$8911 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:164033.3-164034.31" + process $proc$libresoc.v:164033$8912 + assign { } { } + assign $0\spr1$6[63:0]$8913 \spr1$6$next + sync posedge \coresync_clk + update \spr1$6 $0\spr1$6[63:0]$8913 + end + attribute \src "libresoc.v:164035.3-164036.31" + process $proc$libresoc.v:164035$8914 + assign { } { } + assign $0\spr1_ok[0:0] \spr1_ok$next + sync posedge \coresync_clk + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:164037.3-164038.19" + process $proc$libresoc.v:164037$8915 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:164039.3-164040.25" + process $proc$libresoc.v:164039$8916 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:164041.3-164042.57" + process $proc$libresoc.v:164041$8917 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8918 \spr_op__insn_type$2$next + sync posedge \coresync_clk + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8918 + end + attribute \src "libresoc.v:164043.3-164044.53" + process $proc$libresoc.v:164043$8919 + assign { } { } + assign $0\spr_op__fn_unit$3[13:0]$8920 \spr_op__fn_unit$3$next + sync posedge \coresync_clk + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8920 + end + attribute \src "libresoc.v:164045.3-164046.47" + process $proc$libresoc.v:164045$8921 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8922 \spr_op__insn$4$next + sync posedge \coresync_clk + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8922 + end + attribute \src "libresoc.v:164047.3-164048.55" + process $proc$libresoc.v:164047$8923 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8924 \spr_op__is_32bit$5$next + sync posedge \coresync_clk + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8924 + end + attribute \src "libresoc.v:164049.3-164050.33" + process $proc$libresoc.v:164049$8925 + assign { } { } + assign $0\muxid$1[1:0]$8926 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8926 + end + attribute \src "libresoc.v:164051.3-164052.29" + process $proc$libresoc.v:164051$8927 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:164091.3-164108.6" + process $proc$libresoc.v:164091$8928 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8929 $2\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:164092.5-164092.29" + switch \initial + attribute \src "libresoc.v:164092.9-164092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8930 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8930 1'0 + case + assign $1\r_busy$next[0:0]$8930 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8931 1'0 + case + assign $2\r_busy$next[0:0]$8931 $1\r_busy$next[0:0]$8930 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8929 + end + attribute \src "libresoc.v:164109.3-164121.6" + process $proc$libresoc.v:164109$8932 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8933 $1\muxid$1$next[1:0]$8934 + attribute \src "libresoc.v:164110.5-164110.29" + switch \initial + attribute \src "libresoc.v:164110.9-164110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8934 \muxid$24 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8934 \muxid$24 + case + assign $1\muxid$1$next[1:0]$8934 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8933 + end + attribute \src "libresoc.v:164122.3-164137.6" + process $proc$libresoc.v:164122$8935 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_op__fn_unit$3$next[13:0]$8936 $1\spr_op__fn_unit$3$next[13:0]$8940 + assign $0\spr_op__insn$4$next[31:0]$8937 $1\spr_op__insn$4$next[31:0]$8941 + assign $0\spr_op__insn_type$2$next[6:0]$8938 $1\spr_op__insn_type$2$next[6:0]$8942 + assign $0\spr_op__is_32bit$5$next[0:0]$8939 $1\spr_op__is_32bit$5$next[0:0]$8943 + attribute \src "libresoc.v:164123.5-164123.29" + switch \initial + attribute \src "libresoc.v:164123.9-164123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + case + assign $1\spr_op__fn_unit$3$next[13:0]$8940 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8941 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8942 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8943 \spr_op__is_32bit$5 + end + sync always + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8936 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8937 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8938 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8939 + end + attribute \src "libresoc.v:164138.3-164156.6" + process $proc$libresoc.v:164138$8944 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8945 $1\o$next[63:0]$8947 + assign { } { } + assign $0\o_ok$next[0:0]$8946 $2\o_ok$next[0:0]$8949 + attribute \src "libresoc.v:164139.5-164139.29" + switch \initial + attribute \src "libresoc.v:164139.9-164139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8947 \o + assign $1\o_ok$next[0:0]$8948 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8949 1'0 + case + assign $2\o_ok$next[0:0]$8949 $1\o_ok$next[0:0]$8948 + end + sync always + update \o$next $0\o$next[63:0]$8945 + update \o_ok$next $0\o_ok$next[0:0]$8946 + end + attribute \src "libresoc.v:164157.3-164175.6" + process $proc$libresoc.v:164157$8950 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr1$6$next[63:0]$8951 $1\spr1$6$next[63:0]$8953 + assign { } { } + assign $0\spr1_ok$next[0:0]$8952 $2\spr1_ok$next[0:0]$8955 + attribute \src "libresoc.v:164158.5-164158.29" + switch \initial + attribute \src "libresoc.v:164158.9-164158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } + case + assign $1\spr1$6$next[63:0]$8953 \spr1$6 + assign $1\spr1_ok$next[0:0]$8954 \spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\spr1_ok$next[0:0]$8955 1'0 + case + assign $2\spr1_ok$next[0:0]$8955 $1\spr1_ok$next[0:0]$8954 + end + sync always + update \spr1$6$next $0\spr1$6$next[63:0]$8951 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8952 + end + attribute \src "libresoc.v:164176.3-164194.6" + process $proc$libresoc.v:164176$8956 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$7$next[63:0]$8958 $1\fast1$7$next[63:0]$8960 + assign $0\fast1_ok$next[0:0]$8957 $2\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:164177.5-164177.29" + switch \initial + attribute \src "libresoc.v:164177.9-164177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } + case + assign $1\fast1_ok$next[0:0]$8959 \fast1_ok + assign $1\fast1$7$next[63:0]$8960 \fast1$7 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8961 1'0 + case + assign $2\fast1_ok$next[0:0]$8961 $1\fast1_ok$next[0:0]$8959 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$8957 + update \fast1$7$next $0\fast1$7$next[63:0]$8958 + end + attribute \src "libresoc.v:164195.3-164213.6" + process $proc$libresoc.v:164195$8962 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$8$next[0:0]$8964 $1\xer_so$8$next[0:0]$8966 + assign $0\xer_so_ok$next[0:0]$8963 $2\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:164196.5-164196.29" + switch \initial + attribute \src "libresoc.v:164196.9-164196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } + case + assign $1\xer_so_ok$next[0:0]$8965 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8966 \xer_so$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8967 1'0 + case + assign $2\xer_so_ok$next[0:0]$8967 $1\xer_so_ok$next[0:0]$8965 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8963 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8964 + end + attribute \src "libresoc.v:164214.3-164232.6" + process $proc$libresoc.v:164214$8968 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$9$next[1:0]$8970 $1\xer_ov$9$next[1:0]$8972 + assign $0\xer_ov_ok$next[0:0]$8969 $2\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:164215.5-164215.29" + switch \initial + attribute \src "libresoc.v:164215.9-164215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } + case + assign $1\xer_ov_ok$next[0:0]$8971 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8972 \xer_ov$9 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8973 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8973 $1\xer_ov_ok$next[0:0]$8971 + end + sync always + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8969 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8970 + end + attribute \src "libresoc.v:164233.3-164251.6" + process $proc$libresoc.v:164233$8974 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$10$next[1:0]$8975 $1\xer_ca$10$next[1:0]$8977 + assign { } { } + assign $0\xer_ca_ok$next[0:0]$8976 $2\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:164234.5-164234.29" + switch \initial + attribute \src "libresoc.v:164234.9-164234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } + case + assign $1\xer_ca$10$next[1:0]$8977 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8978 \xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8979 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8979 $1\xer_ca_ok$next[0:0]$8978 + end + sync always + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8975 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8976 + end + connect \$22 $and$libresoc.v:164016$8899_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid +end +attribute \src "libresoc.v:164277.1-165769.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" +attribute \generator "nMigen" +module \pipe1 + attribute \src "libresoc.v:165683.3-165724.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9072 + attribute \src "libresoc.v:165459.3-165460.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9073 + attribute \src "libresoc.v:165429.3-165430.47" + wire width 14 $0\alu_op__fn_unit[13:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9074 + attribute \src "libresoc.v:165431.3-165432.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9075 + attribute \src "libresoc.v:165433.3-165434.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9076 + attribute \src "libresoc.v:165451.3-165452.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 32 $0\alu_op__insn$next[31:0]$9077 + attribute \src "libresoc.v:165461.3-165462.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9078 + attribute \src "libresoc.v:165427.3-165428.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__invert_in$next[0:0]$9079 + attribute \src "libresoc.v:165443.3-165444.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__invert_out$next[0:0]$9080 + attribute \src "libresoc.v:165447.3-165448.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__is_32bit$next[0:0]$9081 + attribute \src "libresoc.v:165455.3-165456.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__is_signed$next[0:0]$9082 + attribute \src "libresoc.v:165457.3-165458.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__oe__oe$next[0:0]$9083 + attribute \src "libresoc.v:165439.3-165440.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__oe__ok$next[0:0]$9084 + attribute \src "libresoc.v:165441.3-165442.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__output_carry$next[0:0]$9085 + attribute \src "libresoc.v:165453.3-165454.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__rc__ok$next[0:0]$9086 + attribute \src "libresoc.v:165437.3-165438.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__rc__rc$next[0:0]$9087 + attribute \src "libresoc.v:165435.3-165436.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__write_cr0$next[0:0]$9088 + attribute \src "libresoc.v:165449.3-165450.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__zero_a$next[0:0]$9089 + attribute \src "libresoc.v:165445.3-165446.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:165576.3-165594.6" + wire width 4 $0\cr_a$next[3:0]$9041 + attribute \src "libresoc.v:165419.3-165420.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:165576.3-165594.6" + wire $0\cr_a_ok$next[0:0]$9042 + attribute \src "libresoc.v:165421.3-165422.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:164278.7-164278.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:165670.3-165682.6" + wire width 2 $0\muxid$next[1:0]$9069 + attribute \src "libresoc.v:165463.3-165464.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:165725.3-165743.6" + wire width 64 $0\o$next[63:0]$9115 + attribute \src "libresoc.v:165423.3-165424.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:165725.3-165743.6" + wire $0\o_ok$next[0:0]$9116 + attribute \src "libresoc.v:165425.3-165426.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:165652.3-165669.6" + wire $0\r_busy$next[0:0]$9065 + attribute \src "libresoc.v:165465.3-165466.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:165595.3-165613.6" + wire width 2 $0\xer_ca$next[1:0]$9048 + attribute \src "libresoc.v:165415.3-165416.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:165595.3-165613.6" + wire $0\xer_ca_ok$next[0:0]$9047 + attribute \src "libresoc.v:165417.3-165418.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:165614.3-165632.6" + wire width 2 $0\xer_ov$next[1:0]$9053 + attribute \src "libresoc.v:165411.3-165412.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:165614.3-165632.6" + wire $0\xer_ov_ok$next[0:0]$9054 + attribute \src "libresoc.v:165413.3-165414.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:165633.3-165651.6" + wire $0\xer_so$next[0:0]$9059 + attribute \src "libresoc.v:165407.3-165408.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:165633.3-165651.6" + wire $0\xer_so_ok$next[0:0]$9060 + attribute \src "libresoc.v:165409.3-165410.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9090 + attribute \src "libresoc.v:164283.13-164283.36" + wire width 4 $1\alu_op__data_len[3:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9091 + attribute \src "libresoc.v:164307.14-164307.40" + wire width 14 $1\alu_op__fn_unit[13:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9092 + attribute \src "libresoc.v:164346.14-164346.59" + wire width 64 $1\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9093 + attribute \src "libresoc.v:164355.7-164355.34" + wire $1\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9094 + attribute \src "libresoc.v:164368.13-164368.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 32 $1\alu_op__insn$next[31:0]$9095 + attribute \src "libresoc.v:164385.14-164385.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9096 + attribute \src "libresoc.v:164469.13-164469.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__invert_in$next[0:0]$9097 + attribute \src "libresoc.v:164628.7-164628.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__invert_out$next[0:0]$9098 + attribute \src "libresoc.v:164637.7-164637.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__is_32bit$next[0:0]$9099 + attribute \src "libresoc.v:164646.7-164646.30" + wire $1\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__is_signed$next[0:0]$9100 + attribute \src "libresoc.v:164655.7-164655.31" + wire $1\alu_op__is_signed[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__oe__oe$next[0:0]$9101 + attribute \src "libresoc.v:164664.7-164664.28" + wire $1\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__oe__ok$next[0:0]$9102 + attribute \src "libresoc.v:164673.7-164673.28" + wire $1\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__output_carry$next[0:0]$9103 + attribute \src "libresoc.v:164682.7-164682.34" + wire $1\alu_op__output_carry[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__rc__ok$next[0:0]$9104 + attribute \src "libresoc.v:164691.7-164691.28" + wire $1\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__rc__rc$next[0:0]$9105 + attribute \src "libresoc.v:164700.7-164700.28" + wire $1\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__write_cr0$next[0:0]$9106 + attribute \src "libresoc.v:164709.7-164709.31" + wire $1\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__zero_a$next[0:0]$9107 + attribute \src "libresoc.v:164718.7-164718.28" + wire $1\alu_op__zero_a[0:0] + attribute \src "libresoc.v:165576.3-165594.6" + wire width 4 $1\cr_a$next[3:0]$9043 + attribute \src "libresoc.v:164731.13-164731.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:165576.3-165594.6" + wire $1\cr_a_ok$next[0:0]$9044 + attribute \src "libresoc.v:164738.7-164738.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:165670.3-165682.6" + wire width 2 $1\muxid$next[1:0]$9070 + attribute \src "libresoc.v:165315.13-165315.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:165725.3-165743.6" + wire width 64 $1\o$next[63:0]$9117 + attribute \src "libresoc.v:165330.14-165330.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:165725.3-165743.6" + wire $1\o_ok$next[0:0]$9118 + attribute \src "libresoc.v:165337.7-165337.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:165652.3-165669.6" + wire $1\r_busy$next[0:0]$9066 + attribute \src "libresoc.v:165351.7-165351.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:165595.3-165613.6" + wire width 2 $1\xer_ca$next[1:0]$9050 + attribute \src "libresoc.v:165360.13-165360.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:165595.3-165613.6" + wire $1\xer_ca_ok$next[0:0]$9049 + attribute \src "libresoc.v:165369.7-165369.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:165614.3-165632.6" + wire width 2 $1\xer_ov$next[1:0]$9055 + attribute \src "libresoc.v:165376.13-165376.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:165614.3-165632.6" + wire $1\xer_ov_ok$next[0:0]$9056 + attribute \src "libresoc.v:165383.7-165383.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:165633.3-165651.6" + wire $1\xer_so$next[0:0]$9061 + attribute \src "libresoc.v:165390.7-165390.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:165633.3-165651.6" + wire $1\xer_so_ok$next[0:0]$9062 + attribute \src "libresoc.v:165399.7-165399.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9108 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9109 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__oe__oe$next[0:0]$9110 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__oe__ok$next[0:0]$9111 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__rc__ok$next[0:0]$9112 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__rc__rc$next[0:0]$9113 + attribute \src "libresoc.v:165576.3-165594.6" + wire $2\cr_a_ok$next[0:0]$9045 + attribute \src "libresoc.v:165725.3-165743.6" + wire $2\o_ok$next[0:0]$9119 + attribute \src "libresoc.v:165652.3-165669.6" + wire $2\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:165595.3-165613.6" + wire $2\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:165614.3-165632.6" + wire $2\xer_ov_ok$next[0:0]$9057 + attribute \src "libresoc.v:165633.3-165651.6" + wire $2\xer_so_ok$next[0:0]$9063 + attribute \src "libresoc.v:165406.18-165406.118" + wire $and$libresoc.v:165406$9009_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:164278.7-164278.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:165406$9009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $and$libresoc.v:165406$9009_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165467.11-165514.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165515.8-165567.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165568.9-165571.4" + cell \n$2 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165572.9-165575.4" + cell \p$1 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:164278.7-164278.20" + process $proc$libresoc.v:164278$9120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:164283.13-164283.36" + process $proc$libresoc.v:164283$9121 + assign { } { } + assign $1\alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_op__data_len $1\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:164307.14-164307.40" + process $proc$libresoc.v:164307$9122 + assign { } { } + assign $1\alu_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] + end + attribute \src "libresoc.v:164346.14-164346.59" + process $proc$libresoc.v:164346$9123 + assign { } { } + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:164355.7-164355.34" + process $proc$libresoc.v:164355$9124 + assign { } { } + assign $1\alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:164368.13-164368.39" + process $proc$libresoc.v:164368$9125 + assign { } { } + assign $1\alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_op__input_carry $1\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:164385.14-164385.34" + process $proc$libresoc.v:164385$9126 + assign { } { } + assign $1\alu_op__insn[31:0] 0 + sync always + sync init + update \alu_op__insn $1\alu_op__insn[31:0] + end + attribute \src "libresoc.v:164469.13-164469.38" + process $proc$libresoc.v:164469$9127 + assign { } { } + assign $1\alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_op__insn_type $1\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:164628.7-164628.31" + process $proc$libresoc.v:164628$9128 + assign { } { } + assign $1\alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_op__invert_in $1\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:164637.7-164637.32" + process $proc$libresoc.v:164637$9129 + assign { } { } + assign $1\alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_op__invert_out $1\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:164646.7-164646.30" + process $proc$libresoc.v:164646$9130 + assign { } { } + assign $1\alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:164655.7-164655.31" + process $proc$libresoc.v:164655$9131 + assign { } { } + assign $1\alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_op__is_signed $1\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:164664.7-164664.28" + process $proc$libresoc.v:164664$9132 + assign { } { } + assign $1\alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:164673.7-164673.28" + process $proc$libresoc.v:164673$9133 + assign { } { } + assign $1\alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:164682.7-164682.34" + process $proc$libresoc.v:164682$9134 + assign { } { } + assign $1\alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_op__output_carry $1\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:164691.7-164691.28" + process $proc$libresoc.v:164691$9135 + assign { } { } + assign $1\alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:164700.7-164700.28" + process $proc$libresoc.v:164700$9136 + assign { } { } + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:164709.7-164709.31" + process $proc$libresoc.v:164709$9137 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:164718.7-164718.28" + process $proc$libresoc.v:164718$9138 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:164731.13-164731.24" + process $proc$libresoc.v:164731$9139 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:164738.7-164738.21" + process $proc$libresoc.v:164738$9140 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:165315.13-165315.25" + process $proc$libresoc.v:165315$9141 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:165330.14-165330.38" + process $proc$libresoc.v:165330$9142 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:165337.7-165337.18" + process $proc$libresoc.v:165337$9143 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:165351.7-165351.20" + process $proc$libresoc.v:165351$9144 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:165360.13-165360.26" + process $proc$libresoc.v:165360$9145 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:165369.7-165369.23" + process $proc$libresoc.v:165369$9146 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:165376.13-165376.26" + process $proc$libresoc.v:165376$9147 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:165383.7-165383.23" + process $proc$libresoc.v:165383$9148 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:165390.7-165390.20" + process $proc$libresoc.v:165390$9149 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:165399.7-165399.23" + process $proc$libresoc.v:165399$9150 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:165407.3-165408.29" + process $proc$libresoc.v:165407$9010 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:165409.3-165410.35" + process $proc$libresoc.v:165409$9011 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:165411.3-165412.29" + process $proc$libresoc.v:165411$9012 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:165413.3-165414.35" + process $proc$libresoc.v:165413$9013 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:165415.3-165416.29" + process $proc$libresoc.v:165415$9014 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:165417.3-165418.35" + process $proc$libresoc.v:165417$9015 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:165419.3-165420.25" + process $proc$libresoc.v:165419$9016 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:165421.3-165422.31" + process $proc$libresoc.v:165421$9017 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:165423.3-165424.19" + process $proc$libresoc.v:165423$9018 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:165425.3-165426.25" + process $proc$libresoc.v:165425$9019 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:165427.3-165428.51" + process $proc$libresoc.v:165427$9020 + assign { } { } + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_op__insn_type $0\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:165429.3-165430.47" + process $proc$libresoc.v:165429$9021 + assign { } { } + assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] + end + attribute \src "libresoc.v:165431.3-165432.61" + process $proc$libresoc.v:165431$9022 + assign { } { } + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:165433.3-165434.57" + process $proc$libresoc.v:165433$9023 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:165435.3-165436.45" + process $proc$libresoc.v:165435$9024 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:165437.3-165438.45" + process $proc$libresoc.v:165437$9025 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:165439.3-165440.45" + process $proc$libresoc.v:165439$9026 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:165441.3-165442.45" + process $proc$libresoc.v:165441$9027 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:165443.3-165444.51" + process $proc$libresoc.v:165443$9028 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:165445.3-165446.45" + process $proc$libresoc.v:165445$9029 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:165447.3-165448.53" + process $proc$libresoc.v:165447$9030 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:165449.3-165450.51" + process $proc$libresoc.v:165449$9031 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:165451.3-165452.55" + process $proc$libresoc.v:165451$9032 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:165453.3-165454.57" + process $proc$libresoc.v:165453$9033 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:165455.3-165456.49" + process $proc$libresoc.v:165455$9034 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:165457.3-165458.51" + process $proc$libresoc.v:165457$9035 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:165459.3-165460.49" + process $proc$libresoc.v:165459$9036 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:165461.3-165462.41" + process $proc$libresoc.v:165461$9037 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "libresoc.v:165463.3-165464.27" + process $proc$libresoc.v:165463$9038 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:165465.3-165466.29" + process $proc$libresoc.v:165465$9039 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:165576.3-165594.6" + process $proc$libresoc.v:165576$9040 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9041 $1\cr_a$next[3:0]$9043 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9042 $2\cr_a_ok$next[0:0]$9045 + attribute \src "libresoc.v:165577.5-165577.29" + switch \initial + attribute \src "libresoc.v:165577.9-165577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$9043 \cr_a + assign $1\cr_a_ok$next[0:0]$9044 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9045 1'0 + case + assign $2\cr_a_ok$next[0:0]$9045 $1\cr_a_ok$next[0:0]$9044 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9041 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9042 + end + attribute \src "libresoc.v:165595.3-165613.6" + process $proc$libresoc.v:165595$9046 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$9048 $1\xer_ca$next[1:0]$9050 + assign $0\xer_ca_ok$next[0:0]$9047 $2\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:165596.5-165596.29" + switch \initial + attribute \src "libresoc.v:165596.9-165596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$9049 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9050 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$9051 1'0 + case + assign $2\xer_ca_ok$next[0:0]$9051 $1\xer_ca_ok$next[0:0]$9049 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9047 + update \xer_ca$next $0\xer_ca$next[1:0]$9048 + end + attribute \src "libresoc.v:165614.3-165632.6" + process $proc$libresoc.v:165614$9052 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9053 $1\xer_ov$next[1:0]$9055 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9054 $2\xer_ov_ok$next[0:0]$9057 + attribute \src "libresoc.v:165615.5-165615.29" + switch \initial + attribute \src "libresoc.v:165615.9-165615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$9055 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9056 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9057 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9057 $1\xer_ov_ok$next[0:0]$9056 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9053 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9054 + end + attribute \src "libresoc.v:165633.3-165651.6" + process $proc$libresoc.v:165633$9058 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9059 $1\xer_so$next[0:0]$9061 + assign { } { } + assign $0\xer_so_ok$next[0:0]$9060 $2\xer_so_ok$next[0:0]$9063 + attribute \src "libresoc.v:165634.5-165634.29" + switch \initial + attribute \src "libresoc.v:165634.9-165634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$9061 \xer_so + assign $1\xer_so_ok$next[0:0]$9062 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9063 1'0 + case + assign $2\xer_so_ok$next[0:0]$9063 $1\xer_so_ok$next[0:0]$9062 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9059 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9060 + end + attribute \src "libresoc.v:165652.3-165669.6" + process $proc$libresoc.v:165652$9064 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9065 $2\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:165653.5-165653.29" + switch \initial + attribute \src "libresoc.v:165653.9-165653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9066 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9066 1'0 + case + assign $1\r_busy$next[0:0]$9066 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9067 1'0 + case + assign $2\r_busy$next[0:0]$9067 $1\r_busy$next[0:0]$9066 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9065 + end + attribute \src "libresoc.v:165670.3-165682.6" + process $proc$libresoc.v:165670$9068 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9069 $1\muxid$next[1:0]$9070 + attribute \src "libresoc.v:165671.5-165671.29" + switch \initial + attribute \src "libresoc.v:165671.9-165671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9070 \muxid$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9070 \muxid$69 + case + assign $1\muxid$next[1:0]$9070 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9069 + end + attribute \src "libresoc.v:165683.3-165724.6" + process $proc$libresoc.v:165683$9071 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$9072 $1\alu_op__data_len$next[3:0]$9090 + assign $0\alu_op__fn_unit$next[13:0]$9073 $1\alu_op__fn_unit$next[13:0]$9091 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$9076 $1\alu_op__input_carry$next[1:0]$9094 + assign $0\alu_op__insn$next[31:0]$9077 $1\alu_op__insn$next[31:0]$9095 + assign $0\alu_op__insn_type$next[6:0]$9078 $1\alu_op__insn_type$next[6:0]$9096 + assign $0\alu_op__invert_in$next[0:0]$9079 $1\alu_op__invert_in$next[0:0]$9097 + assign $0\alu_op__invert_out$next[0:0]$9080 $1\alu_op__invert_out$next[0:0]$9098 + assign $0\alu_op__is_32bit$next[0:0]$9081 $1\alu_op__is_32bit$next[0:0]$9099 + assign $0\alu_op__is_signed$next[0:0]$9082 $1\alu_op__is_signed$next[0:0]$9100 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$9085 $1\alu_op__output_carry$next[0:0]$9103 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$9088 $1\alu_op__write_cr0$next[0:0]$9106 + assign $0\alu_op__zero_a$next[0:0]$9089 $1\alu_op__zero_a$next[0:0]$9107 + assign $0\alu_op__imm_data__data$next[63:0]$9074 $2\alu_op__imm_data__data$next[63:0]$9108 + assign $0\alu_op__imm_data__ok$next[0:0]$9075 $2\alu_op__imm_data__ok$next[0:0]$9109 + assign $0\alu_op__oe__oe$next[0:0]$9083 $2\alu_op__oe__oe$next[0:0]$9110 + assign $0\alu_op__oe__ok$next[0:0]$9084 $2\alu_op__oe__ok$next[0:0]$9111 + assign $0\alu_op__rc__ok$next[0:0]$9086 $2\alu_op__rc__ok$next[0:0]$9112 + assign $0\alu_op__rc__rc$next[0:0]$9087 $2\alu_op__rc__rc$next[0:0]$9113 + attribute \src "libresoc.v:165684.5-165684.29" + switch \initial + attribute \src "libresoc.v:165684.9-165684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$9090 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9091 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9092 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9093 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9094 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9095 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9096 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9097 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9098 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9099 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9100 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9101 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9102 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9103 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9104 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9105 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9106 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9107 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$9108 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9109 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9113 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9112 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9110 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9111 1'0 + case + assign $2\alu_op__imm_data__data$next[63:0]$9108 $1\alu_op__imm_data__data$next[63:0]$9092 + assign $2\alu_op__imm_data__ok$next[0:0]$9109 $1\alu_op__imm_data__ok$next[0:0]$9093 + assign $2\alu_op__oe__oe$next[0:0]$9110 $1\alu_op__oe__oe$next[0:0]$9101 + assign $2\alu_op__oe__ok$next[0:0]$9111 $1\alu_op__oe__ok$next[0:0]$9102 + assign $2\alu_op__rc__ok$next[0:0]$9112 $1\alu_op__rc__ok$next[0:0]$9104 + assign $2\alu_op__rc__rc$next[0:0]$9113 $1\alu_op__rc__rc$next[0:0]$9105 + end + sync always + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9072 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9073 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9074 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9075 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9076 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9077 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9078 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9079 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9080 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9081 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9082 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9083 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9084 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9085 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9086 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9087 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9088 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9089 + end + attribute \src "libresoc.v:165725.3-165743.6" + process $proc$libresoc.v:165725$9114 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9115 $1\o$next[63:0]$9117 + assign { } { } + assign $0\o_ok$next[0:0]$9116 $2\o_ok$next[0:0]$9119 + attribute \src "libresoc.v:165726.5-165726.29" + switch \initial + attribute \src "libresoc.v:165726.9-165726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } + case + assign $1\o$next[63:0]$9117 \o + assign $1\o_ok$next[0:0]$9118 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9119 1'0 + case + assign $2\o_ok$next[0:0]$9119 $1\o_ok$next[0:0]$9118 + end + sync always + update \o$next $0\o$next[63:0]$9115 + update \o_ok$next $0\o_ok$next[0:0]$9116 + end + connect \$67 $and$libresoc.v:165406$9009_Y + connect \xer_so_ok$98 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:165773.1-167209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \generator "nMigen" +module \pipe1$110 + attribute \src "libresoc.v:167142.3-167160.6" + wire width 4 $0\cr_a$next[3:0]$9240 + attribute \src "libresoc.v:166884.3-166885.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:167142.3-167160.6" + wire $0\cr_a_ok$next[0:0]$9241 + attribute \src "libresoc.v:166886.3-166887.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:165774.7-165774.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167069.3-167081.6" + wire width 2 $0\muxid$next[1:0]$9190 + attribute \src "libresoc.v:166926.3-166927.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:167123.3-167141.6" + wire width 64 $0\o$next[63:0]$9234 + attribute \src "libresoc.v:166888.3-166889.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:167123.3-167141.6" + wire $0\o_ok$next[0:0]$9235 + attribute \src "libresoc.v:166890.3-166891.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:167051.3-167068.6" + wire $0\r_busy$next[0:0]$9186 + attribute \src "libresoc.v:166928.3-166929.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9193 + attribute \src "libresoc.v:166894.3-166895.45" + wire width 14 $0\sr_op__fn_unit[13:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9194 + attribute \src "libresoc.v:166896.3-166897.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9195 + attribute \src "libresoc.v:166898.3-166899.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9196 + attribute \src "libresoc.v:166912.3-166913.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__input_cr$next[0:0]$9197 + attribute \src "libresoc.v:166916.3-166917.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 32 $0\sr_op__insn$next[31:0]$9198 + attribute \src "libresoc.v:166924.3-166925.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9199 + attribute \src "libresoc.v:166892.3-166893.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__invert_in$next[0:0]$9200 + attribute \src "libresoc.v:166910.3-166911.49" + wire $0\sr_op__invert_in[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__is_32bit$next[0:0]$9201 + attribute \src "libresoc.v:166920.3-166921.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__is_signed$next[0:0]$9202 + attribute \src "libresoc.v:166922.3-166923.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__oe__oe$next[0:0]$9203 + attribute \src "libresoc.v:166904.3-166905.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__oe__ok$next[0:0]$9204 + attribute \src "libresoc.v:166906.3-166907.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__output_carry$next[0:0]$9205 + attribute \src "libresoc.v:166914.3-166915.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__output_cr$next[0:0]$9206 + attribute \src "libresoc.v:166918.3-166919.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__rc__ok$next[0:0]$9207 + attribute \src "libresoc.v:166902.3-166903.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__rc__rc$next[0:0]$9208 + attribute \src "libresoc.v:166900.3-166901.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__write_cr0$next[0:0]$9209 + attribute \src "libresoc.v:166908.3-166909.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:167032.3-167050.6" + wire width 2 $0\xer_ca$next[1:0]$9181 + attribute \src "libresoc.v:166876.3-166877.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:167032.3-167050.6" + wire $0\xer_ca_ok$next[0:0]$9180 + attribute \src "libresoc.v:166878.3-166879.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:167161.3-167179.6" + wire $0\xer_so$next[0:0]$9246 + attribute \src "libresoc.v:166880.3-166881.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:167161.3-167179.6" + wire $0\xer_so_ok$next[0:0]$9247 + attribute \src "libresoc.v:166882.3-166883.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:167142.3-167160.6" + wire width 4 $1\cr_a$next[3:0]$9242 + attribute \src "libresoc.v:165783.13-165783.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:167142.3-167160.6" + wire $1\cr_a_ok$next[0:0]$9243 + attribute \src "libresoc.v:165792.7-165792.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:167069.3-167081.6" + wire width 2 $1\muxid$next[1:0]$9191 + attribute \src "libresoc.v:166357.13-166357.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:167123.3-167141.6" + wire width 64 $1\o$next[63:0]$9236 + attribute \src "libresoc.v:166372.14-166372.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:167123.3-167141.6" + wire $1\o_ok$next[0:0]$9237 + attribute \src "libresoc.v:166379.7-166379.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:167051.3-167068.6" + wire $1\r_busy$next[0:0]$9187 + attribute \src "libresoc.v:166393.7-166393.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9210 + attribute \src "libresoc.v:166419.14-166419.39" + wire width 14 $1\sr_op__fn_unit[13:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9211 + attribute \src "libresoc.v:166458.14-166458.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9212 + attribute \src "libresoc.v:166467.7-166467.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9213 + attribute \src "libresoc.v:166480.13-166480.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__input_cr$next[0:0]$9214 + attribute \src "libresoc.v:166497.7-166497.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 32 $1\sr_op__insn$next[31:0]$9215 + attribute \src "libresoc.v:166506.14-166506.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9216 + attribute \src "libresoc.v:166590.13-166590.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__invert_in$next[0:0]$9217 + attribute \src "libresoc.v:166749.7-166749.30" + wire $1\sr_op__invert_in[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__is_32bit$next[0:0]$9218 + attribute \src "libresoc.v:166758.7-166758.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__is_signed$next[0:0]$9219 + attribute \src "libresoc.v:166767.7-166767.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__oe__oe$next[0:0]$9220 + attribute \src "libresoc.v:166776.7-166776.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__oe__ok$next[0:0]$9221 + attribute \src "libresoc.v:166785.7-166785.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__output_carry$next[0:0]$9222 + attribute \src "libresoc.v:166794.7-166794.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__output_cr$next[0:0]$9223 + attribute \src "libresoc.v:166803.7-166803.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__rc__ok$next[0:0]$9224 + attribute \src "libresoc.v:166812.7-166812.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__rc__rc$next[0:0]$9225 + attribute \src "libresoc.v:166821.7-166821.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__write_cr0$next[0:0]$9226 + attribute \src "libresoc.v:166830.7-166830.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:167032.3-167050.6" + wire width 2 $1\xer_ca$next[1:0]$9183 + attribute \src "libresoc.v:166839.13-166839.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:167032.3-167050.6" + wire $1\xer_ca_ok$next[0:0]$9182 + attribute \src "libresoc.v:166850.7-166850.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:167161.3-167179.6" + wire $1\xer_so$next[0:0]$9248 + attribute \src "libresoc.v:166859.7-166859.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:167161.3-167179.6" + wire $1\xer_so_ok$next[0:0]$9249 + attribute \src "libresoc.v:166868.7-166868.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:167142.3-167160.6" + wire $2\cr_a_ok$next[0:0]$9244 + attribute \src "libresoc.v:167123.3-167141.6" + wire $2\o_ok$next[0:0]$9238 + attribute \src "libresoc.v:167051.3-167068.6" + wire $2\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9227 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9228 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__oe__oe$next[0:0]$9229 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__oe__ok$next[0:0]$9230 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__rc__ok$next[0:0]$9231 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__rc__rc$next[0:0]$9232 + attribute \src "libresoc.v:167032.3-167050.6" + wire $2\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:167161.3-167179.6" + wire $2\xer_so_ok$next[0:0]$9250 + attribute \src "libresoc.v:166875.18-166875.118" + wire $and$libresoc.v:166875$9151_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 55 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:165774.7-165774.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$41 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_sr_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn$38 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute 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\enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" 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\enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src 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\main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 31 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 52 \rc + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 34 \sr_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 43 \sr_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src 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attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute 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attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute 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\enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$68 + attribute \src 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\sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$next + attribute \src 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wire input 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 54 \xer_ca$20 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:166875$9151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$64 + connect \B \p_ready_o + connect \Y $and$libresoc.v:166875$9151_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166930.15-166977.4" + cell \input$113 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$19 \input_ra$39 + connect \rb \input_rb + connect \rb$20 \input_rb$40 + connect \rc \input_rc + connect \rc$21 \input_rc$41 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$18 \input_sr_op__insn$38 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 + connect \sr_op__invert_in \input_sr_op__invert_in + connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166978.14-167023.4" + cell \main$114 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$44 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$18 \main_sr_op__insn$61 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 + connect \sr_op__invert_in \main_sr_op__invert_in + connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$19 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167024.11-167027.4" + cell \n$112 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167028.11-167031.4" + cell \p$111 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:165774.7-165774.20" + process $proc$libresoc.v:165774$9251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:165783.13-165783.24" + process $proc$libresoc.v:165783$9252 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:165792.7-165792.21" + process $proc$libresoc.v:165792$9253 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:166357.13-166357.25" + process $proc$libresoc.v:166357$9254 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:166372.14-166372.38" + process $proc$libresoc.v:166372$9255 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:166379.7-166379.18" + process $proc$libresoc.v:166379$9256 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:166393.7-166393.20" + process $proc$libresoc.v:166393$9257 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:166419.14-166419.39" + process $proc$libresoc.v:166419$9258 + assign { } { } + assign $1\sr_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:166458.14-166458.58" + process $proc$libresoc.v:166458$9259 + assign { } { } + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:166467.7-166467.33" + process $proc$libresoc.v:166467$9260 + assign { } { } + assign $1\sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:166480.13-166480.38" + process $proc$libresoc.v:166480$9261 + assign { } { } + assign $1\sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \sr_op__input_carry $1\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:166497.7-166497.29" + process $proc$libresoc.v:166497$9262 + assign { } { } + assign $1\sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \sr_op__input_cr $1\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:166506.14-166506.33" + process $proc$libresoc.v:166506$9263 + assign { } { } + assign $1\sr_op__insn[31:0] 0 + sync always + sync init + update \sr_op__insn $1\sr_op__insn[31:0] + end + attribute \src "libresoc.v:166590.13-166590.37" + process $proc$libresoc.v:166590$9264 + assign { } { } + assign $1\sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \sr_op__insn_type $1\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:166749.7-166749.30" + process $proc$libresoc.v:166749$9265 + assign { } { } + assign $1\sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \sr_op__invert_in $1\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:166758.7-166758.29" + process $proc$libresoc.v:166758$9266 + assign { } { } + assign $1\sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:166767.7-166767.30" + process $proc$libresoc.v:166767$9267 + assign { } { } + assign $1\sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \sr_op__is_signed $1\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:166776.7-166776.27" + process $proc$libresoc.v:166776$9268 + assign { } { } + assign $1\sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:166785.7-166785.27" + process $proc$libresoc.v:166785$9269 + assign { } { } + assign $1\sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:166794.7-166794.33" + process $proc$libresoc.v:166794$9270 + assign { } { } + assign $1\sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \sr_op__output_carry $1\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:166803.7-166803.30" + process $proc$libresoc.v:166803$9271 + assign { } { } + assign $1\sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \sr_op__output_cr $1\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:166812.7-166812.27" + process $proc$libresoc.v:166812$9272 + assign { } { } + assign $1\sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:166821.7-166821.27" + process $proc$libresoc.v:166821$9273 + assign { } { } + assign $1\sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:166830.7-166830.30" + process $proc$libresoc.v:166830$9274 + assign { } { } + assign $1\sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:166839.13-166839.26" + process $proc$libresoc.v:166839$9275 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:166850.7-166850.23" + process $proc$libresoc.v:166850$9276 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:166859.7-166859.20" + process $proc$libresoc.v:166859$9277 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:166868.7-166868.23" + process $proc$libresoc.v:166868$9278 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:166876.3-166877.29" + process $proc$libresoc.v:166876$9152 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:166878.3-166879.35" + process $proc$libresoc.v:166878$9153 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:166880.3-166881.29" + process $proc$libresoc.v:166880$9154 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:166882.3-166883.35" + process $proc$libresoc.v:166882$9155 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:166884.3-166885.25" + process $proc$libresoc.v:166884$9156 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:166886.3-166887.31" + process $proc$libresoc.v:166886$9157 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:166888.3-166889.19" + process $proc$libresoc.v:166888$9158 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:166890.3-166891.25" + process $proc$libresoc.v:166890$9159 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:166892.3-166893.49" + process $proc$libresoc.v:166892$9160 + assign { } { } + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + sync posedge \coresync_clk + update \sr_op__insn_type $0\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:166894.3-166895.45" + process $proc$libresoc.v:166894$9161 + assign { } { } + assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next + sync posedge \coresync_clk + update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:166896.3-166897.59" + process $proc$libresoc.v:166896$9162 + assign { } { } + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + sync posedge \coresync_clk + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:166898.3-166899.55" + process $proc$libresoc.v:166898$9163 + assign { } { } + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:166900.3-166901.43" + process $proc$libresoc.v:166900$9164 + assign { } { } + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + sync posedge \coresync_clk + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:166902.3-166903.43" + process $proc$libresoc.v:166902$9165 + assign { } { } + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + sync posedge \coresync_clk + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:166904.3-166905.43" + process $proc$libresoc.v:166904$9166 + assign { } { } + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + sync posedge \coresync_clk + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:166906.3-166907.43" + process $proc$libresoc.v:166906$9167 + assign { } { } + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + sync posedge \coresync_clk + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:166908.3-166909.49" + process $proc$libresoc.v:166908$9168 + assign { } { } + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + sync posedge \coresync_clk + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:166910.3-166911.49" + process $proc$libresoc.v:166910$9169 + assign { } { } + assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next + sync posedge \coresync_clk + update \sr_op__invert_in $0\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:166912.3-166913.53" + process $proc$libresoc.v:166912$9170 + assign { } { } + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + sync posedge \coresync_clk + update \sr_op__input_carry $0\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:166914.3-166915.55" + process $proc$libresoc.v:166914$9171 + assign { } { } + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + sync posedge \coresync_clk + update \sr_op__output_carry $0\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:166916.3-166917.47" + process $proc$libresoc.v:166916$9172 + assign { } { } + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + sync posedge \coresync_clk + update \sr_op__input_cr $0\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:166918.3-166919.49" + process $proc$libresoc.v:166918$9173 + assign { } { } + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + sync posedge \coresync_clk + update \sr_op__output_cr $0\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:166920.3-166921.47" + process $proc$libresoc.v:166920$9174 + assign { } { } + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + sync posedge \coresync_clk + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:166922.3-166923.49" + process $proc$libresoc.v:166922$9175 + assign { } { } + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + sync posedge \coresync_clk + update \sr_op__is_signed $0\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:166924.3-166925.39" + process $proc$libresoc.v:166924$9176 + assign { } { } + assign $0\sr_op__insn[31:0] \sr_op__insn$next + sync posedge \coresync_clk + update \sr_op__insn $0\sr_op__insn[31:0] + end + attribute \src "libresoc.v:166926.3-166927.27" + process $proc$libresoc.v:166926$9177 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:166928.3-166929.29" + process $proc$libresoc.v:166928$9178 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:167032.3-167050.6" + process $proc$libresoc.v:167032$9179 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$9181 $1\xer_ca$next[1:0]$9183 + assign $0\xer_ca_ok$next[0:0]$9180 $2\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:167033.5-167033.29" + switch \initial + attribute \src "libresoc.v:167033.9-167033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } + case + assign $1\xer_ca_ok$next[0:0]$9182 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9183 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$9184 1'0 + case + assign $2\xer_ca_ok$next[0:0]$9184 $1\xer_ca_ok$next[0:0]$9182 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9180 + update \xer_ca$next $0\xer_ca$next[1:0]$9181 + end + attribute \src "libresoc.v:167051.3-167068.6" + process $proc$libresoc.v:167051$9185 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9186 $2\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:167052.5-167052.29" + switch \initial + attribute \src "libresoc.v:167052.9-167052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9187 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9187 1'0 + case + assign $1\r_busy$next[0:0]$9187 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9188 1'0 + case + assign $2\r_busy$next[0:0]$9188 $1\r_busy$next[0:0]$9187 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9186 + end + attribute \src "libresoc.v:167069.3-167081.6" + process $proc$libresoc.v:167069$9189 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9190 $1\muxid$next[1:0]$9191 + attribute \src "libresoc.v:167070.5-167070.29" + switch \initial + attribute \src "libresoc.v:167070.9-167070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9191 \muxid$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9191 \muxid$67 + case + assign $1\muxid$next[1:0]$9191 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9190 + end + attribute \src "libresoc.v:167082.3-167122.6" + process $proc$libresoc.v:167082$9192 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$next[13:0]$9193 $1\sr_op__fn_unit$next[13:0]$9210 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$next[1:0]$9196 $1\sr_op__input_carry$next[1:0]$9213 + assign $0\sr_op__input_cr$next[0:0]$9197 $1\sr_op__input_cr$next[0:0]$9214 + assign $0\sr_op__insn$next[31:0]$9198 $1\sr_op__insn$next[31:0]$9215 + assign $0\sr_op__insn_type$next[6:0]$9199 $1\sr_op__insn_type$next[6:0]$9216 + assign $0\sr_op__invert_in$next[0:0]$9200 $1\sr_op__invert_in$next[0:0]$9217 + assign $0\sr_op__is_32bit$next[0:0]$9201 $1\sr_op__is_32bit$next[0:0]$9218 + assign $0\sr_op__is_signed$next[0:0]$9202 $1\sr_op__is_signed$next[0:0]$9219 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$next[0:0]$9205 $1\sr_op__output_carry$next[0:0]$9222 + assign $0\sr_op__output_cr$next[0:0]$9206 $1\sr_op__output_cr$next[0:0]$9223 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$next[0:0]$9209 $1\sr_op__write_cr0$next[0:0]$9226 + assign $0\sr_op__imm_data__data$next[63:0]$9194 $2\sr_op__imm_data__data$next[63:0]$9227 + assign $0\sr_op__imm_data__ok$next[0:0]$9195 $2\sr_op__imm_data__ok$next[0:0]$9228 + assign $0\sr_op__oe__oe$next[0:0]$9203 $2\sr_op__oe__oe$next[0:0]$9229 + assign $0\sr_op__oe__ok$next[0:0]$9204 $2\sr_op__oe__ok$next[0:0]$9230 + assign $0\sr_op__rc__ok$next[0:0]$9207 $2\sr_op__rc__ok$next[0:0]$9231 + assign $0\sr_op__rc__rc$next[0:0]$9208 $2\sr_op__rc__rc$next[0:0]$9232 + attribute \src "libresoc.v:167083.5-167083.29" + switch \initial + attribute \src "libresoc.v:167083.9-167083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + case + assign $1\sr_op__fn_unit$next[13:0]$9210 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9211 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9212 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9213 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9214 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9215 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9216 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9217 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9218 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9219 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9220 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9221 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9222 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9223 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9224 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9225 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9226 \sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$next[63:0]$9227 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9228 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9232 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9231 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9229 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9230 1'0 + case + assign $2\sr_op__imm_data__data$next[63:0]$9227 $1\sr_op__imm_data__data$next[63:0]$9211 + assign $2\sr_op__imm_data__ok$next[0:0]$9228 $1\sr_op__imm_data__ok$next[0:0]$9212 + assign $2\sr_op__oe__oe$next[0:0]$9229 $1\sr_op__oe__oe$next[0:0]$9220 + assign $2\sr_op__oe__ok$next[0:0]$9230 $1\sr_op__oe__ok$next[0:0]$9221 + assign $2\sr_op__rc__ok$next[0:0]$9231 $1\sr_op__rc__ok$next[0:0]$9224 + assign $2\sr_op__rc__rc$next[0:0]$9232 $1\sr_op__rc__rc$next[0:0]$9225 + end + sync always + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9193 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9194 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9195 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9196 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9197 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9198 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9199 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9200 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9201 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9202 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9203 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9204 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9205 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9206 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9207 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9208 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9209 + end + attribute \src "libresoc.v:167123.3-167141.6" + process $proc$libresoc.v:167123$9233 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9234 $1\o$next[63:0]$9236 + assign { } { } + assign $0\o_ok$next[0:0]$9235 $2\o_ok$next[0:0]$9238 + attribute \src "libresoc.v:167124.5-167124.29" + switch \initial + attribute \src "libresoc.v:167124.9-167124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$9236 \o + assign $1\o_ok$next[0:0]$9237 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9238 1'0 + case + assign $2\o_ok$next[0:0]$9238 $1\o_ok$next[0:0]$9237 + end + sync always + update \o$next $0\o$next[63:0]$9234 + update \o_ok$next $0\o_ok$next[0:0]$9235 + end + attribute \src "libresoc.v:167142.3-167160.6" + process $proc$libresoc.v:167142$9239 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9240 $1\cr_a$next[3:0]$9242 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9241 $2\cr_a_ok$next[0:0]$9244 + attribute \src "libresoc.v:167143.5-167143.29" + switch \initial + attribute \src "libresoc.v:167143.9-167143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$9242 \cr_a + assign $1\cr_a_ok$next[0:0]$9243 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9244 1'0 + case + assign $2\cr_a_ok$next[0:0]$9244 $1\cr_a_ok$next[0:0]$9243 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9240 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9241 + end + attribute \src "libresoc.v:167161.3-167179.6" + process $proc$libresoc.v:167161$9245 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9246 $1\xer_so$next[0:0]$9248 + assign { } { } + assign $0\xer_so_ok$next[0:0]$9247 $2\xer_so_ok$next[0:0]$9250 + attribute \src "libresoc.v:167162.5-167162.29" + switch \initial + attribute \src "libresoc.v:167162.9-167162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$9248 \xer_so + assign $1\xer_so_ok$next[0:0]$9249 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9250 1'0 + case + assign $2\xer_so_ok$next[0:0]$9250 $1\xer_so_ok$next[0:0]$9249 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9246 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9247 + end + connect \$65 $and$libresoc.v:166875$9151_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \xer_ca_ok$96 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } + connect \muxid$67 \main_muxid$44 + connect \p_valid_i_p_ready_o \$65 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$64 \p_valid_i + connect \xer_ca$63 \input_xer_ca$43 + connect \main_xer_so \input_xer_so$42 + connect \main_rc \input_rc$41 + connect \main_rb \input_rb$40 + connect \main_ra \input_ra$39 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_ca \xer_ca$20 + connect \input_xer_so \xer_so$19 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:167213.1-168061.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" +attribute \generator "nMigen" +module \pipe1$32 + attribute \src "libresoc.v:168018.3-168030.6" + wire width 64 $0\fast1$next[63:0]$9328 + attribute \src "libresoc.v:167874.3-167875.27" + wire width 64 $0\fast1[63:0] + attribute \src "libresoc.v:168031.3-168043.6" + wire width 64 $0\fast2$next[63:0]$9331 + attribute \src "libresoc.v:167872.3-167873.27" + wire width 64 $0\fast2[63:0] + attribute \src "libresoc.v:167214.7-167214.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167958.3-167970.6" + wire width 2 $0\muxid$next[1:0]$9300 + attribute \src "libresoc.v:167898.3-167899.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:167940.3-167957.6" + wire $0\r_busy$next[0:0]$9296 + attribute \src "libresoc.v:167900.3-167901.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:167992.3-168004.6" + wire width 64 $0\ra$next[63:0]$9322 + attribute \src "libresoc.v:167878.3-167879.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:168005.3-168017.6" + wire width 64 $0\rb$next[63:0]$9325 + attribute \src "libresoc.v:167876.3-167877.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $0\trap_op__cia$next[63:0]$9303 + attribute \src "libresoc.v:167888.3-167889.41" + wire width 64 $0\trap_op__cia[63:0] + attribute \src "libresoc.v:167971.3-167991.6" + wire width 14 $0\trap_op__fn_unit$next[13:0]$9304 + attribute \src "libresoc.v:167882.3-167883.49" + wire width 14 $0\trap_op__fn_unit[13:0] + attribute \src "libresoc.v:167971.3-167991.6" + wire width 32 $0\trap_op__insn$next[31:0]$9305 + attribute \src "libresoc.v:167884.3-167885.43" + wire width 32 $0\trap_op__insn[31:0] + attribute \src "libresoc.v:167971.3-167991.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9306 + attribute \src "libresoc.v:167880.3-167881.53" + wire width 7 $0\trap_op__insn_type[6:0] + attribute \src "libresoc.v:167971.3-167991.6" + wire $0\trap_op__is_32bit$next[0:0]$9307 + attribute \src "libresoc.v:167890.3-167891.51" + wire $0\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9308 + attribute \src "libresoc.v:167896.3-167897.51" + wire width 8 $0\trap_op__ldst_exc[7:0] + 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 22 \trap_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 21 \trap_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 26 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 13 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 29 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 24 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 28 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:167871$9279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$29 + connect \B \p_ready_o + connect \Y $and$libresoc.v:167871$9279_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167902.9-167931.4" + cell \dummy \dummy + connect \fast1 \dummy_fast1 + connect \fast1$13 \dummy_fast1$27 + connect \fast2 \dummy_fast2 + connect \fast2$14 \dummy_fast2$28 + connect \muxid \dummy_muxid + connect \muxid$1 \dummy_muxid$15 + connect \ra \dummy_ra + connect \ra$11 \dummy_ra$25 + connect \rb \dummy_rb + connect \rb$12 \dummy_rb$26 + connect \trap_op__cia \dummy_trap_op__cia + connect \trap_op__cia$6 \dummy_trap_op__cia$20 + connect \trap_op__fn_unit \dummy_trap_op__fn_unit + connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 + connect \trap_op__insn \dummy_trap_op__insn + connect \trap_op__insn$4 \dummy_trap_op__insn$18 + connect \trap_op__insn_type \dummy_trap_op__insn_type + connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 + connect \trap_op__is_32bit \dummy_trap_op__is_32bit + connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 + connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 + connect \trap_op__msr \dummy_trap_op__msr + connect \trap_op__msr$5 \dummy_trap_op__msr$19 + connect \trap_op__trapaddr \dummy_trap_op__trapaddr + connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 + connect \trap_op__traptype \dummy_trap_op__traptype + connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167932.10-167935.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167936.10-167939.4" + cell \p$33 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:167214.7-167214.20" + process $proc$libresoc.v:167214$9333 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167459.14-167459.42" + process $proc$libresoc.v:167459$9334 + assign { } { } + assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1 $1\fast1[63:0] + end + attribute \src "libresoc.v:167468.14-167468.42" + process $proc$libresoc.v:167468$9335 + assign { } { } + assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2 $1\fast2[63:0] + end + attribute \src "libresoc.v:167477.13-167477.25" + process $proc$libresoc.v:167477$9336 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:167499.7-167499.20" + process $proc$libresoc.v:167499$9337 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:167504.14-167504.39" + process $proc$libresoc.v:167504$9338 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:167513.14-167513.39" + process $proc$libresoc.v:167513$9339 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:167522.14-167522.49" + process $proc$libresoc.v:167522$9340 + assign { } { } + assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia $1\trap_op__cia[63:0] + end + attribute \src "libresoc.v:167546.14-167546.41" + process $proc$libresoc.v:167546$9341 + assign { } { } + assign $1\trap_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] + end + attribute \src "libresoc.v:167585.14-167585.35" + process $proc$libresoc.v:167585$9342 + assign { } { } + assign $1\trap_op__insn[31:0] 0 + sync always + sync init + update \trap_op__insn $1\trap_op__insn[31:0] + end + attribute \src "libresoc.v:167669.13-167669.39" + process $proc$libresoc.v:167669$9343 + assign { } { } + assign $1\trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \trap_op__insn_type $1\trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:167828.7-167828.31" + process $proc$libresoc.v:167828$9344 + assign { } { } + assign $1\trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:167837.13-167837.38" + process $proc$libresoc.v:167837$9345 + assign { } { } + assign $1\trap_op__ldst_exc[7:0] 8'00000000 + sync always + sync init + update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:167846.14-167846.49" + process $proc$libresoc.v:167846$9346 + assign { } { } + assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr $1\trap_op__msr[63:0] + end + attribute \src "libresoc.v:167855.14-167855.42" + process $proc$libresoc.v:167855$9347 + assign { } { } + assign $1\trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:167864.13-167864.38" + process $proc$libresoc.v:167864$9348 + assign { } { } + assign $1\trap_op__traptype[7:0] 8'00000000 + sync always + sync init + update \trap_op__traptype $1\trap_op__traptype[7:0] + end + attribute \src "libresoc.v:167872.3-167873.27" + process $proc$libresoc.v:167872$9280 + assign { } { } + assign $0\fast2[63:0] \fast2$next + sync posedge \coresync_clk + update \fast2 $0\fast2[63:0] + end + attribute \src "libresoc.v:167874.3-167875.27" + process $proc$libresoc.v:167874$9281 + assign { } { } + assign $0\fast1[63:0] \fast1$next + sync posedge \coresync_clk + update \fast1 $0\fast1[63:0] + end + attribute \src "libresoc.v:167876.3-167877.21" + process $proc$libresoc.v:167876$9282 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:167878.3-167879.21" + process $proc$libresoc.v:167878$9283 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:167880.3-167881.53" + process $proc$libresoc.v:167880$9284 + assign { } { } + assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next + sync posedge \coresync_clk + update \trap_op__insn_type $0\trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:167882.3-167883.49" + process $proc$libresoc.v:167882$9285 + assign { } { } + assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next + sync posedge \coresync_clk + update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] + end + attribute \src "libresoc.v:167884.3-167885.43" + process $proc$libresoc.v:167884$9286 + assign { } { } + assign $0\trap_op__insn[31:0] \trap_op__insn$next + sync posedge \coresync_clk + update \trap_op__insn $0\trap_op__insn[31:0] + end + attribute \src "libresoc.v:167886.3-167887.41" + process $proc$libresoc.v:167886$9287 + assign { } { } + assign $0\trap_op__msr[63:0] \trap_op__msr$next + sync posedge \coresync_clk + update \trap_op__msr $0\trap_op__msr[63:0] + end + attribute \src "libresoc.v:167888.3-167889.41" + process $proc$libresoc.v:167888$9288 + assign { } { } + assign $0\trap_op__cia[63:0] \trap_op__cia$next + sync posedge \coresync_clk + update \trap_op__cia $0\trap_op__cia[63:0] + end + attribute \src "libresoc.v:167890.3-167891.51" + process $proc$libresoc.v:167890$9289 + assign { } { } + assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next + sync posedge \coresync_clk + update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:167892.3-167893.51" + process $proc$libresoc.v:167892$9290 + assign { } { } + assign $0\trap_op__traptype[7:0] \trap_op__traptype$next + sync posedge \coresync_clk + update \trap_op__traptype $0\trap_op__traptype[7:0] + end + attribute \src "libresoc.v:167894.3-167895.51" + process $proc$libresoc.v:167894$9291 + assign { } { } + assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next + sync posedge \coresync_clk + update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:167896.3-167897.51" + process $proc$libresoc.v:167896$9292 + assign { } { } + assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next + sync posedge \coresync_clk + update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:167898.3-167899.27" + process $proc$libresoc.v:167898$9293 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:167900.3-167901.29" + process $proc$libresoc.v:167900$9294 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:167940.3-167957.6" + process $proc$libresoc.v:167940$9295 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9296 $2\r_busy$next[0:0]$9298 + attribute \src "libresoc.v:167941.5-167941.29" + switch \initial + attribute \src "libresoc.v:167941.9-167941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9297 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9297 1'0 + case + assign $1\r_busy$next[0:0]$9297 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9298 1'0 + case + assign $2\r_busy$next[0:0]$9298 $1\r_busy$next[0:0]$9297 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9296 + end + attribute \src "libresoc.v:167958.3-167970.6" + process $proc$libresoc.v:167958$9299 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9300 $1\muxid$next[1:0]$9301 + attribute \src "libresoc.v:167959.5-167959.29" + switch \initial + attribute \src "libresoc.v:167959.9-167959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9301 \muxid$32 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9301 \muxid$32 + case + assign $1\muxid$next[1:0]$9301 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9300 + end + attribute \src "libresoc.v:167971.3-167991.6" + process $proc$libresoc.v:167971$9302 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$next[63:0]$9303 $1\trap_op__cia$next[63:0]$9312 + assign $0\trap_op__fn_unit$next[13:0]$9304 $1\trap_op__fn_unit$next[13:0]$9313 + assign $0\trap_op__insn$next[31:0]$9305 $1\trap_op__insn$next[31:0]$9314 + assign $0\trap_op__insn_type$next[6:0]$9306 $1\trap_op__insn_type$next[6:0]$9315 + assign $0\trap_op__is_32bit$next[0:0]$9307 $1\trap_op__is_32bit$next[0:0]$9316 + assign $0\trap_op__ldst_exc$next[7:0]$9308 $1\trap_op__ldst_exc$next[7:0]$9317 + assign $0\trap_op__msr$next[63:0]$9309 $1\trap_op__msr$next[63:0]$9318 + assign $0\trap_op__trapaddr$next[12:0]$9310 $1\trap_op__trapaddr$next[12:0]$9319 + assign $0\trap_op__traptype$next[7:0]$9311 $1\trap_op__traptype$next[7:0]$9320 + attribute \src "libresoc.v:167972.5-167972.29" + switch \initial + attribute \src "libresoc.v:167972.9-167972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + case + assign $1\trap_op__cia$next[63:0]$9312 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9313 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9314 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9315 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9316 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9317 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9318 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9319 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9320 \trap_op__traptype + end + sync always + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9303 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9304 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9305 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9306 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9307 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9308 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9309 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9310 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9311 + end + attribute \src "libresoc.v:167992.3-168004.6" + process $proc$libresoc.v:167992$9321 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$9322 $1\ra$next[63:0]$9323 + attribute \src "libresoc.v:167993.5-167993.29" + switch \initial + attribute \src "libresoc.v:167993.9-167993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$9323 \ra$42 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$9323 \ra$42 + case + assign $1\ra$next[63:0]$9323 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$9322 + end + attribute \src "libresoc.v:168005.3-168017.6" + process $proc$libresoc.v:168005$9324 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$9325 $1\rb$next[63:0]$9326 + attribute \src "libresoc.v:168006.5-168006.29" + switch \initial + attribute \src "libresoc.v:168006.9-168006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$9326 \rb$43 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$9326 \rb$43 + case + assign $1\rb$next[63:0]$9326 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$9325 + end + attribute \src "libresoc.v:168018.3-168030.6" + process $proc$libresoc.v:168018$9327 + assign { } { } + assign { } { } + assign $0\fast1$next[63:0]$9328 $1\fast1$next[63:0]$9329 + attribute \src "libresoc.v:168019.5-168019.29" + switch \initial + attribute \src "libresoc.v:168019.9-168019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\fast1$next[63:0]$9329 \fast1$44 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\fast1$next[63:0]$9329 \fast1$44 + case + assign $1\fast1$next[63:0]$9329 \fast1 + end + sync always + update \fast1$next $0\fast1$next[63:0]$9328 + end + attribute \src "libresoc.v:168031.3-168043.6" + process $proc$libresoc.v:168031$9330 + assign { } { } + assign { } { } + assign $0\fast2$next[63:0]$9331 $1\fast2$next[63:0]$9332 + attribute \src "libresoc.v:168032.5-168032.29" + switch \initial + attribute \src "libresoc.v:168032.9-168032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\fast2$next[63:0]$9332 \fast2$45 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\fast2$next[63:0]$9332 \fast2$45 + case + assign $1\fast2$next[63:0]$9332 \fast2 + end + sync always + update \fast2$next $0\fast2$next[63:0]$9331 + end + connect \$30 $and$libresoc.v:167871$9279_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \fast2$45 \dummy_fast2$28 + connect \fast1$44 \dummy_fast1$27 + connect \rb$43 \dummy_rb$26 + connect \ra$42 \dummy_ra$25 + connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } + connect \muxid$32 \dummy_muxid$15 + connect \p_valid_i_p_ready_o \$30 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$29 \p_valid_i + connect \dummy_fast2 \fast2$14 + connect \dummy_fast1 \fast1$13 + connect \dummy_rb \rb$12 + connect \dummy_ra \ra$11 + connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } + connect \dummy_muxid \muxid$1 +end +attribute \src "libresoc.v:168065.1-169250.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" +attribute \generator "nMigen" +module \pipe2 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9417 + attribute \src "libresoc.v:168991.3-168992.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9403 + attribute \src "libresoc.v:168073.13-168073.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9491 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9418 + attribute \src "libresoc.v:168961.3-168962.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9373 + attribute \src "libresoc.v:168112.14-168112.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9493 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9419 + attribute \src "libresoc.v:168963.3-168964.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9375 + attribute \src "libresoc.v:168136.14-168136.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9495 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9420 + attribute \src "libresoc.v:168965.3-168966.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9377 + attribute \src "libresoc.v:168145.7-168145.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9497 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9421 + attribute \src "libresoc.v:168983.3-168984.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9395 + attribute \src "libresoc.v:168162.13-168162.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9499 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9422 + attribute \src "libresoc.v:168993.3-168994.49" + wire width 32 $0\alu_op__insn$19[31:0]$9405 + attribute \src "libresoc.v:168175.14-168175.39" + wire width 32 $0\alu_op__insn$19[31:0]$9501 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9423 + attribute \src "libresoc.v:168959.3-168960.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9371 + attribute \src "libresoc.v:168334.13-168334.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9503 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__invert_in$10$next[0:0]$9424 + attribute \src "libresoc.v:168975.3-168976.59" + wire $0\alu_op__invert_in$10[0:0]$9387 + attribute \src "libresoc.v:168418.7-168418.36" + wire $0\alu_op__invert_in$10[0:0]$9505 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__invert_out$12$next[0:0]$9425 + attribute \src "libresoc.v:168979.3-168980.61" + wire $0\alu_op__invert_out$12[0:0]$9391 + attribute \src "libresoc.v:168427.7-168427.37" + wire $0\alu_op__invert_out$12[0:0]$9507 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9426 + attribute \src "libresoc.v:168987.3-168988.57" + wire $0\alu_op__is_32bit$16[0:0]$9399 + attribute \src "libresoc.v:168436.7-168436.35" + wire $0\alu_op__is_32bit$16[0:0]$9509 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__is_signed$17$next[0:0]$9427 + attribute \src "libresoc.v:168989.3-168990.59" + wire $0\alu_op__is_signed$17[0:0]$9401 + attribute \src "libresoc.v:168445.7-168445.36" + wire $0\alu_op__is_signed$17[0:0]$9511 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9428 + attribute \src "libresoc.v:168971.3-168972.51" + wire $0\alu_op__oe__oe$8[0:0]$9383 + attribute \src "libresoc.v:168456.7-168456.32" + wire $0\alu_op__oe__oe$8[0:0]$9513 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9429 + attribute \src "libresoc.v:168973.3-168974.51" + wire $0\alu_op__oe__ok$9[0:0]$9385 + attribute \src "libresoc.v:168465.7-168465.32" + wire $0\alu_op__oe__ok$9[0:0]$9515 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__output_carry$15$next[0:0]$9430 + attribute \src "libresoc.v:168985.3-168986.65" + wire $0\alu_op__output_carry$15[0:0]$9397 + attribute \src "libresoc.v:168472.7-168472.39" + wire $0\alu_op__output_carry$15[0:0]$9517 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9431 + attribute \src "libresoc.v:168969.3-168970.51" + wire $0\alu_op__rc__ok$7[0:0]$9381 + attribute \src "libresoc.v:168483.7-168483.32" + wire $0\alu_op__rc__ok$7[0:0]$9519 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9432 + attribute \src "libresoc.v:168967.3-168968.51" + wire $0\alu_op__rc__rc$6[0:0]$9379 + attribute \src "libresoc.v:168490.7-168490.32" + wire $0\alu_op__rc__rc$6[0:0]$9521 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9433 + attribute \src "libresoc.v:168981.3-168982.59" + wire $0\alu_op__write_cr0$13[0:0]$9393 + attribute \src "libresoc.v:168499.7-168499.36" + wire $0\alu_op__write_cr0$13[0:0]$9523 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__zero_a$11$next[0:0]$9434 + attribute \src "libresoc.v:168977.3-168978.53" + wire $0\alu_op__zero_a$11[0:0]$9389 + attribute \src "libresoc.v:168508.7-168508.33" + wire $0\alu_op__zero_a$11[0:0]$9525 + attribute \src "libresoc.v:169155.3-169173.6" + wire width 4 $0\cr_a$22$next[3:0]$9466 + attribute \src "libresoc.v:168951.3-168952.33" + wire width 4 $0\cr_a$22[3:0]$9363 + attribute \src "libresoc.v:168521.13-168521.29" + wire width 4 $0\cr_a$22[3:0]$9527 + attribute \src "libresoc.v:169155.3-169173.6" + wire $0\cr_a_ok$23$next[0:0]$9467 + attribute \src "libresoc.v:168953.3-168954.39" + wire $0\cr_a_ok$23[0:0]$9365 + attribute \src "libresoc.v:168530.7-168530.26" + wire $0\cr_a_ok$23[0:0]$9529 + attribute \src "libresoc.v:168066.7-168066.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169081.3-169093.6" + wire width 2 $0\muxid$1$next[1:0]$9414 + attribute \src "libresoc.v:168995.3-168996.33" + wire width 2 $0\muxid$1[1:0]$9407 + attribute \src "libresoc.v:168541.13-168541.29" + wire width 2 $0\muxid$1[1:0]$9531 + attribute \src "libresoc.v:169136.3-169154.6" + wire width 64 $0\o$20$next[63:0]$9460 + attribute \src "libresoc.v:168955.3-168956.27" + wire width 64 $0\o$20[63:0]$9367 + attribute \src "libresoc.v:168556.14-168556.43" + wire width 64 $0\o$20[63:0]$9533 + attribute \src "libresoc.v:169136.3-169154.6" + wire $0\o_ok$21$next[0:0]$9461 + attribute \src "libresoc.v:168957.3-168958.33" + wire $0\o_ok$21[0:0]$9369 + attribute \src "libresoc.v:168565.7-168565.23" + wire $0\o_ok$21[0:0]$9535 + attribute \src "libresoc.v:169063.3-169080.6" + wire $0\r_busy$next[0:0]$9410 + attribute \src "libresoc.v:168997.3-168998.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:169174.3-169192.6" + wire width 2 $0\xer_ca$24$next[1:0]$9472 + attribute \src "libresoc.v:168947.3-168948.37" + wire width 2 $0\xer_ca$24[1:0]$9359 + attribute \src "libresoc.v:168882.13-168882.31" + wire width 2 $0\xer_ca$24[1:0]$9538 + attribute \src "libresoc.v:169174.3-169192.6" + wire $0\xer_ca_ok$25$next[0:0]$9473 + attribute \src "libresoc.v:168949.3-168950.43" + wire $0\xer_ca_ok$25[0:0]$9361 + attribute \src "libresoc.v:168891.7-168891.28" + wire $0\xer_ca_ok$25[0:0]$9540 + attribute \src "libresoc.v:169193.3-169211.6" + wire width 2 $0\xer_ov$26$next[1:0]$9478 + attribute \src "libresoc.v:168943.3-168944.37" + wire width 2 $0\xer_ov$26[1:0]$9355 + attribute \src "libresoc.v:168902.13-168902.31" + wire width 2 $0\xer_ov$26[1:0]$9542 + attribute \src "libresoc.v:169193.3-169211.6" + wire $0\xer_ov_ok$27$next[0:0]$9479 + attribute \src "libresoc.v:168945.3-168946.43" + wire $0\xer_ov_ok$27[0:0]$9357 + attribute \src "libresoc.v:168911.7-168911.28" + wire $0\xer_ov_ok$27[0:0]$9544 + attribute \src "libresoc.v:169212.3-169230.6" + wire $0\xer_so$28$next[0:0]$9484 + attribute \src "libresoc.v:168939.3-168940.37" + wire $0\xer_so$28[0:0]$9351 + attribute \src "libresoc.v:168922.7-168922.25" + wire $0\xer_so$28[0:0]$9546 + attribute \src "libresoc.v:169212.3-169230.6" + wire $0\xer_so_ok$29$next[0:0]$9485 + attribute \src "libresoc.v:168941.3-168942.43" + wire $0\xer_so_ok$29[0:0]$9353 + attribute \src "libresoc.v:168931.7-168931.28" + wire $0\xer_so_ok$29[0:0]$9548 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9435 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9436 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9437 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9438 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9439 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9440 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9441 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__invert_in$10$next[0:0]$9442 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__invert_out$12$next[0:0]$9443 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9444 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__is_signed$17$next[0:0]$9445 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9446 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9447 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__output_carry$15$next[0:0]$9448 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9449 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9450 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9451 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__zero_a$11$next[0:0]$9452 + attribute \src "libresoc.v:169155.3-169173.6" + wire width 4 $1\cr_a$22$next[3:0]$9468 + attribute \src "libresoc.v:169155.3-169173.6" + wire $1\cr_a_ok$23$next[0:0]$9469 + attribute \src "libresoc.v:169081.3-169093.6" + wire width 2 $1\muxid$1$next[1:0]$9415 + attribute \src "libresoc.v:169136.3-169154.6" + wire width 64 $1\o$20$next[63:0]$9462 + attribute \src "libresoc.v:169136.3-169154.6" + wire $1\o_ok$21$next[0:0]$9463 + attribute \src "libresoc.v:169063.3-169080.6" + wire $1\r_busy$next[0:0]$9411 + attribute \src "libresoc.v:168875.7-168875.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:169174.3-169192.6" + wire width 2 $1\xer_ca$24$next[1:0]$9474 + attribute \src "libresoc.v:169174.3-169192.6" + wire $1\xer_ca_ok$25$next[0:0]$9475 + attribute \src "libresoc.v:169193.3-169211.6" + wire width 2 $1\xer_ov$26$next[1:0]$9480 + attribute \src "libresoc.v:169193.3-169211.6" + wire $1\xer_ov_ok$27$next[0:0]$9481 + attribute \src "libresoc.v:169212.3-169230.6" + wire $1\xer_so$28$next[0:0]$9486 + attribute \src "libresoc.v:169212.3-169230.6" + wire $1\xer_so_ok$29$next[0:0]$9487 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9453 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9454 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9455 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9456 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9457 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9458 + attribute \src "libresoc.v:169155.3-169173.6" + wire $2\cr_a_ok$23$next[0:0]$9470 + attribute \src "libresoc.v:169136.3-169154.6" + wire $2\o_ok$21$next[0:0]$9464 + attribute \src "libresoc.v:169063.3-169080.6" + wire $2\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:169174.3-169192.6" + wire $2\xer_ca_ok$25$next[0:0]$9476 + attribute \src "libresoc.v:169193.3-169211.6" + wire $2\xer_ov_ok$27$next[0:0]$9482 + attribute \src "libresoc.v:169212.3-169230.6" + wire $2\xer_so_ok$29$next[0:0]$9488 + attribute \src "libresoc.v:168938.18-168938.118" + wire $and$libresoc.v:168938$9349_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$84 + attribute \src "libresoc.v:168066.7-168066.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:168938$9349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $and$libresoc.v:168938$9349_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168999.9-169002.4" + cell \n$4 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:169003.12-169058.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:169059.9-169062.4" + cell \p$3 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:168066.7-168066.20" + process $proc$libresoc.v:168066$9489 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168073.13-168073.41" + process $proc$libresoc.v:168073$9490 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9491 4'0000 + sync always + sync init + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9491 + end + attribute \src "libresoc.v:168112.14-168112.44" + process $proc$libresoc.v:168112$9492 + assign { } { } + assign $0\alu_op__fn_unit$3[13:0]$9493 14'00000000000000 + sync always + sync init + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9493 + end + attribute \src "libresoc.v:168136.14-168136.63" + process $proc$libresoc.v:168136$9494 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9495 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9495 + end + attribute \src "libresoc.v:168145.7-168145.38" + process $proc$libresoc.v:168145$9496 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9497 1'0 + sync always + sync init + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9497 + end + attribute \src "libresoc.v:168162.13-168162.44" + process $proc$libresoc.v:168162$9498 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$9499 2'00 + sync always + sync init + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9499 + end + attribute \src "libresoc.v:168175.14-168175.39" + process $proc$libresoc.v:168175$9500 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9501 0 + sync always + sync init + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9501 + end + attribute \src "libresoc.v:168334.13-168334.42" + process $proc$libresoc.v:168334$9502 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9503 7'0000000 + sync always + sync init + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9503 + end + attribute \src "libresoc.v:168418.7-168418.36" + process $proc$libresoc.v:168418$9504 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9505 1'0 + sync always + sync init + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9505 + end + attribute \src "libresoc.v:168427.7-168427.37" + process $proc$libresoc.v:168427$9506 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$9507 1'0 + sync always + sync init + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9507 + end + attribute \src "libresoc.v:168436.7-168436.35" + process $proc$libresoc.v:168436$9508 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$9509 1'0 + sync always + sync init + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9509 + end + attribute \src "libresoc.v:168445.7-168445.36" + process $proc$libresoc.v:168445$9510 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9511 1'0 + sync always + sync init + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9511 + end + attribute \src "libresoc.v:168456.7-168456.32" + process $proc$libresoc.v:168456$9512 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9513 1'0 + sync always + sync init + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9513 + end + attribute \src "libresoc.v:168465.7-168465.32" + process $proc$libresoc.v:168465$9514 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9515 1'0 + sync always + sync init + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9515 + end + attribute \src "libresoc.v:168472.7-168472.39" + process $proc$libresoc.v:168472$9516 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$9517 1'0 + sync always + sync init + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9517 + end + attribute \src "libresoc.v:168483.7-168483.32" + process $proc$libresoc.v:168483$9518 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9519 1'0 + sync always + sync init + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9519 + end + attribute \src "libresoc.v:168490.7-168490.32" + process $proc$libresoc.v:168490$9520 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9521 1'0 + sync always + sync init + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9521 + end + attribute \src "libresoc.v:168499.7-168499.36" + process $proc$libresoc.v:168499$9522 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$9523 1'0 + sync always + sync init + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9523 + end + attribute \src "libresoc.v:168508.7-168508.33" + process $proc$libresoc.v:168508$9524 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$9525 1'0 + sync always + sync init + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9525 + end + attribute \src "libresoc.v:168521.13-168521.29" + process $proc$libresoc.v:168521$9526 + assign { } { } + assign $0\cr_a$22[3:0]$9527 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$9527 + end + attribute \src "libresoc.v:168530.7-168530.26" + process $proc$libresoc.v:168530$9528 + assign { } { } + assign $0\cr_a_ok$23[0:0]$9529 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9529 + end + attribute \src "libresoc.v:168541.13-168541.29" + process $proc$libresoc.v:168541$9530 + assign { } { } + assign $0\muxid$1[1:0]$9531 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9531 + end + attribute \src "libresoc.v:168556.14-168556.43" + process $proc$libresoc.v:168556$9532 + assign { } { } + assign $0\o$20[63:0]$9533 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$9533 + end + attribute \src "libresoc.v:168565.7-168565.23" + process $proc$libresoc.v:168565$9534 + assign { } { } + assign $0\o_ok$21[0:0]$9535 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$9535 + end + attribute \src "libresoc.v:168875.7-168875.20" + process $proc$libresoc.v:168875$9536 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:168882.13-168882.31" + process $proc$libresoc.v:168882$9537 + assign { } { } + assign $0\xer_ca$24[1:0]$9538 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$9538 + end + attribute \src "libresoc.v:168891.7-168891.28" + process $proc$libresoc.v:168891$9539 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9540 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9540 + end + attribute \src "libresoc.v:168902.13-168902.31" + process $proc$libresoc.v:168902$9541 + assign { } { } + assign $0\xer_ov$26[1:0]$9542 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$9542 + end + attribute \src "libresoc.v:168911.7-168911.28" + process $proc$libresoc.v:168911$9543 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9544 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9544 + end + attribute \src "libresoc.v:168922.7-168922.25" + process $proc$libresoc.v:168922$9545 + assign { } { } + assign $0\xer_so$28[0:0]$9546 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$9546 + end + attribute \src "libresoc.v:168931.7-168931.28" + process $proc$libresoc.v:168931$9547 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9548 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9548 + end + attribute \src "libresoc.v:168939.3-168940.37" + process $proc$libresoc.v:168939$9350 + assign { } { } + assign $0\xer_so$28[0:0]$9351 \xer_so$28$next + sync posedge \coresync_clk + update \xer_so$28 $0\xer_so$28[0:0]$9351 + end + attribute \src "libresoc.v:168941.3-168942.43" + process $proc$libresoc.v:168941$9352 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9353 \xer_so_ok$29$next + sync posedge \coresync_clk + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9353 + end + attribute \src "libresoc.v:168943.3-168944.37" + process $proc$libresoc.v:168943$9354 + assign { } { } + assign $0\xer_ov$26[1:0]$9355 \xer_ov$26$next + sync posedge \coresync_clk + update \xer_ov$26 $0\xer_ov$26[1:0]$9355 + end + attribute \src "libresoc.v:168945.3-168946.43" + process $proc$libresoc.v:168945$9356 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9357 \xer_ov_ok$27$next + sync posedge \coresync_clk + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9357 + end + attribute \src "libresoc.v:168947.3-168948.37" + process $proc$libresoc.v:168947$9358 + assign { } { } + assign $0\xer_ca$24[1:0]$9359 \xer_ca$24$next + sync posedge \coresync_clk + update \xer_ca$24 $0\xer_ca$24[1:0]$9359 + end + attribute \src "libresoc.v:168949.3-168950.43" + process $proc$libresoc.v:168949$9360 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9361 \xer_ca_ok$25$next + sync posedge \coresync_clk + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9361 + end + attribute \src "libresoc.v:168951.3-168952.33" + process $proc$libresoc.v:168951$9362 + assign { } { } + assign $0\cr_a$22[3:0]$9363 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$9363 + end + attribute \src "libresoc.v:168953.3-168954.39" + process $proc$libresoc.v:168953$9364 + assign { } { } + assign $0\cr_a_ok$23[0:0]$9365 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9365 + end + attribute \src "libresoc.v:168955.3-168956.27" + process $proc$libresoc.v:168955$9366 + assign { } { } + assign $0\o$20[63:0]$9367 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$9367 + end + attribute \src "libresoc.v:168957.3-168958.33" + process $proc$libresoc.v:168957$9368 + assign { } { } + assign $0\o_ok$21[0:0]$9369 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$9369 + end + attribute \src "libresoc.v:168959.3-168960.57" + process $proc$libresoc.v:168959$9370 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9371 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9371 + end + attribute \src "libresoc.v:168961.3-168962.53" + process $proc$libresoc.v:168961$9372 + assign { } { } + assign $0\alu_op__fn_unit$3[13:0]$9373 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9373 + end + attribute \src "libresoc.v:168963.3-168964.67" + process $proc$libresoc.v:168963$9374 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9375 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9375 + end + attribute \src "libresoc.v:168965.3-168966.63" + process $proc$libresoc.v:168965$9376 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9377 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9377 + end + attribute \src "libresoc.v:168967.3-168968.51" + process $proc$libresoc.v:168967$9378 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9379 \alu_op__rc__rc$6$next + sync posedge \coresync_clk + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9379 + end + attribute \src "libresoc.v:168969.3-168970.51" + process $proc$libresoc.v:168969$9380 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9381 \alu_op__rc__ok$7$next + sync posedge \coresync_clk + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9381 + end + attribute \src "libresoc.v:168971.3-168972.51" + process $proc$libresoc.v:168971$9382 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9383 \alu_op__oe__oe$8$next + sync posedge \coresync_clk + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9383 + end + attribute \src "libresoc.v:168973.3-168974.51" + process $proc$libresoc.v:168973$9384 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9385 \alu_op__oe__ok$9$next + sync posedge \coresync_clk + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9385 + end + attribute \src "libresoc.v:168975.3-168976.59" + process $proc$libresoc.v:168975$9386 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9387 \alu_op__invert_in$10$next + sync posedge \coresync_clk + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9387 + end + attribute \src "libresoc.v:168977.3-168978.53" + process $proc$libresoc.v:168977$9388 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$9389 \alu_op__zero_a$11$next + sync posedge \coresync_clk + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9389 + end + attribute \src "libresoc.v:168979.3-168980.61" + process $proc$libresoc.v:168979$9390 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$9391 \alu_op__invert_out$12$next + sync posedge \coresync_clk + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9391 + end + attribute \src "libresoc.v:168981.3-168982.59" + process $proc$libresoc.v:168981$9392 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$9393 \alu_op__write_cr0$13$next + sync posedge \coresync_clk + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9393 + end + attribute \src "libresoc.v:168983.3-168984.63" + process $proc$libresoc.v:168983$9394 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$9395 \alu_op__input_carry$14$next + sync posedge \coresync_clk + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9395 + end + attribute \src "libresoc.v:168985.3-168986.65" + process $proc$libresoc.v:168985$9396 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$9397 \alu_op__output_carry$15$next + sync posedge \coresync_clk + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9397 + end + attribute \src "libresoc.v:168987.3-168988.57" + process $proc$libresoc.v:168987$9398 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$9399 \alu_op__is_32bit$16$next + sync posedge \coresync_clk + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9399 + end + attribute \src "libresoc.v:168989.3-168990.59" + process $proc$libresoc.v:168989$9400 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9401 \alu_op__is_signed$17$next + sync posedge \coresync_clk + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9401 + end + attribute \src "libresoc.v:168991.3-168992.57" + process $proc$libresoc.v:168991$9402 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9403 \alu_op__data_len$18$next + sync posedge \coresync_clk + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9403 + end + attribute \src "libresoc.v:168993.3-168994.49" + process $proc$libresoc.v:168993$9404 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9405 \alu_op__insn$19$next + sync posedge \coresync_clk + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9405 + end + attribute \src "libresoc.v:168995.3-168996.33" + process $proc$libresoc.v:168995$9406 + assign { } { } + assign $0\muxid$1[1:0]$9407 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9407 + end + attribute \src "libresoc.v:168997.3-168998.29" + process $proc$libresoc.v:168997$9408 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:169063.3-169080.6" + process $proc$libresoc.v:169063$9409 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9410 $2\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:169064.5-169064.29" + switch \initial + attribute \src "libresoc.v:169064.9-169064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9411 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9411 1'0 + case + assign $1\r_busy$next[0:0]$9411 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9412 1'0 + case + assign $2\r_busy$next[0:0]$9412 $1\r_busy$next[0:0]$9411 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9410 + end + attribute \src "libresoc.v:169081.3-169093.6" + process $proc$libresoc.v:169081$9413 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9414 $1\muxid$1$next[1:0]$9415 + attribute \src "libresoc.v:169082.5-169082.29" + switch \initial + attribute \src "libresoc.v:169082.9-169082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9415 \muxid$62 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9415 \muxid$62 + case + assign $1\muxid$1$next[1:0]$9415 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9414 + end + attribute \src "libresoc.v:169094.3-169135.6" + process $proc$libresoc.v:169094$9416 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$9417 $1\alu_op__data_len$18$next[3:0]$9435 + assign $0\alu_op__fn_unit$3$next[13:0]$9418 $1\alu_op__fn_unit$3$next[13:0]$9436 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$9421 $1\alu_op__input_carry$14$next[1:0]$9439 + assign $0\alu_op__insn$19$next[31:0]$9422 $1\alu_op__insn$19$next[31:0]$9440 + assign $0\alu_op__insn_type$2$next[6:0]$9423 $1\alu_op__insn_type$2$next[6:0]$9441 + assign $0\alu_op__invert_in$10$next[0:0]$9424 $1\alu_op__invert_in$10$next[0:0]$9442 + assign $0\alu_op__invert_out$12$next[0:0]$9425 $1\alu_op__invert_out$12$next[0:0]$9443 + assign $0\alu_op__is_32bit$16$next[0:0]$9426 $1\alu_op__is_32bit$16$next[0:0]$9444 + assign $0\alu_op__is_signed$17$next[0:0]$9427 $1\alu_op__is_signed$17$next[0:0]$9445 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$9430 $1\alu_op__output_carry$15$next[0:0]$9448 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$9433 $1\alu_op__write_cr0$13$next[0:0]$9451 + assign $0\alu_op__zero_a$11$next[0:0]$9434 $1\alu_op__zero_a$11$next[0:0]$9452 + assign $0\alu_op__imm_data__data$4$next[63:0]$9419 $2\alu_op__imm_data__data$4$next[63:0]$9453 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9420 $2\alu_op__imm_data__ok$5$next[0:0]$9454 + assign $0\alu_op__oe__oe$8$next[0:0]$9428 $2\alu_op__oe__oe$8$next[0:0]$9455 + assign $0\alu_op__oe__ok$9$next[0:0]$9429 $2\alu_op__oe__ok$9$next[0:0]$9456 + assign $0\alu_op__rc__ok$7$next[0:0]$9431 $2\alu_op__rc__ok$7$next[0:0]$9457 + assign $0\alu_op__rc__rc$6$next[0:0]$9432 $2\alu_op__rc__rc$6$next[0:0]$9458 + attribute \src "libresoc.v:169095.5-169095.29" + switch \initial + attribute \src "libresoc.v:169095.9-169095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$9435 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9436 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9437 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9438 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9439 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9440 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9441 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9442 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9443 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9444 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9445 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9446 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9447 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9448 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9449 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9450 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9451 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9452 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$9453 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9458 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9457 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9455 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9456 1'0 + case + assign $2\alu_op__imm_data__data$4$next[63:0]$9453 $1\alu_op__imm_data__data$4$next[63:0]$9437 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 $1\alu_op__imm_data__ok$5$next[0:0]$9438 + assign $2\alu_op__oe__oe$8$next[0:0]$9455 $1\alu_op__oe__oe$8$next[0:0]$9446 + assign $2\alu_op__oe__ok$9$next[0:0]$9456 $1\alu_op__oe__ok$9$next[0:0]$9447 + assign $2\alu_op__rc__ok$7$next[0:0]$9457 $1\alu_op__rc__ok$7$next[0:0]$9449 + assign $2\alu_op__rc__rc$6$next[0:0]$9458 $1\alu_op__rc__rc$6$next[0:0]$9450 + end + sync always + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9417 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9418 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9419 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9420 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9421 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9422 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9423 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9424 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9425 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9426 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9427 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9428 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9429 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9430 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9431 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9432 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9433 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9434 + end + attribute \src "libresoc.v:169136.3-169154.6" + process $proc$libresoc.v:169136$9459 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$9460 $1\o$20$next[63:0]$9462 + assign { } { } + assign $0\o_ok$21$next[0:0]$9461 $2\o_ok$21$next[0:0]$9464 + attribute \src "libresoc.v:169137.5-169137.29" + switch \initial + attribute \src "libresoc.v:169137.9-169137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } + case + assign $1\o$20$next[63:0]$9462 \o$20 + assign $1\o_ok$21$next[0:0]$9463 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$9464 1'0 + case + assign $2\o_ok$21$next[0:0]$9464 $1\o_ok$21$next[0:0]$9463 + end + sync always + update \o$20$next $0\o$20$next[63:0]$9460 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9461 + end + attribute \src "libresoc.v:169155.3-169173.6" + process $proc$libresoc.v:169155$9465 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$9466 $1\cr_a$22$next[3:0]$9468 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$9467 $2\cr_a_ok$23$next[0:0]$9470 + attribute \src "libresoc.v:169156.5-169156.29" + switch \initial + attribute \src "libresoc.v:169156.9-169156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$22$next[3:0]$9468 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9469 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$9470 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$9470 $1\cr_a_ok$23$next[0:0]$9469 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$9466 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9467 + end + attribute \src "libresoc.v:169174.3-169192.6" + process $proc$libresoc.v:169174$9471 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$24$next[1:0]$9472 $1\xer_ca$24$next[1:0]$9474 + assign { } { } + assign $0\xer_ca_ok$25$next[0:0]$9473 $2\xer_ca_ok$25$next[0:0]$9476 + attribute \src "libresoc.v:169175.5-169175.29" + switch \initial + attribute \src "libresoc.v:169175.9-169175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } + case + assign $1\xer_ca$24$next[1:0]$9474 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9475 \xer_ca_ok$25 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$25$next[0:0]$9476 1'0 + case + assign $2\xer_ca_ok$25$next[0:0]$9476 $1\xer_ca_ok$25$next[0:0]$9475 + end + sync always + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9472 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9473 + end + attribute \src "libresoc.v:169193.3-169211.6" + process $proc$libresoc.v:169193$9477 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$26$next[1:0]$9478 $1\xer_ov$26$next[1:0]$9480 + assign { } { } + assign $0\xer_ov_ok$27$next[0:0]$9479 $2\xer_ov_ok$27$next[0:0]$9482 + attribute \src "libresoc.v:169194.5-169194.29" + switch \initial + attribute \src "libresoc.v:169194.9-169194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } + case + assign $1\xer_ov$26$next[1:0]$9480 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9481 \xer_ov_ok$27 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$27$next[0:0]$9482 1'0 + case + assign $2\xer_ov_ok$27$next[0:0]$9482 $1\xer_ov_ok$27$next[0:0]$9481 + end + sync always + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9478 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9479 + end + attribute \src "libresoc.v:169212.3-169230.6" + process $proc$libresoc.v:169212$9483 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$28$next[0:0]$9484 $1\xer_so$28$next[0:0]$9486 + assign { } { } + assign $0\xer_so_ok$29$next[0:0]$9485 $2\xer_so_ok$29$next[0:0]$9488 + attribute \src "libresoc.v:169213.5-169213.29" + switch \initial + attribute \src "libresoc.v:169213.9-169213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } + case + assign $1\xer_so$28$next[0:0]$9486 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9487 \xer_so_ok$29 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$29$next[0:0]$9488 1'0 + case + assign $2\xer_so_ok$29$next[0:0]$9488 $1\xer_so_ok$29$next[0:0]$9487 + end + sync always + update \xer_so$28$next $0\xer_so$28$next[0:0]$9484 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9485 + end + connect \$60 $and$libresoc.v:168938$9349_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:169254.1-170323.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \generator "nMigen" +module \pipe2$115 + attribute \src "libresoc.v:170269.3-170287.6" + wire width 4 $0\cr_a$21$next[3:0]$9654 + attribute \src "libresoc.v:170075.3-170076.33" + wire width 4 $0\cr_a$21[3:0]$9555 + attribute \src "libresoc.v:169266.13-169266.29" + wire width 4 $0\cr_a$21[3:0]$9667 + attribute \src "libresoc.v:170269.3-170287.6" + wire $0\cr_a_ok$22$next[0:0]$9655 + attribute \src "libresoc.v:170077.3-170078.39" + wire $0\cr_a_ok$22[0:0]$9557 + attribute \src "libresoc.v:169275.7-169275.26" + wire $0\cr_a_ok$22[0:0]$9669 + attribute \src "libresoc.v:169255.7-169255.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170196.3-170208.6" + wire width 2 $0\muxid$1$next[1:0]$9604 + attribute \src "libresoc.v:170117.3-170118.33" + wire width 2 $0\muxid$1[1:0]$9597 + attribute \src "libresoc.v:169286.13-169286.29" + wire width 2 $0\muxid$1[1:0]$9671 + attribute \src "libresoc.v:170250.3-170268.6" + wire width 64 $0\o$19$next[63:0]$9648 + attribute \src "libresoc.v:170079.3-170080.27" + wire width 64 $0\o$19[63:0]$9559 + attribute \src "libresoc.v:169301.14-169301.43" + wire width 64 $0\o$19[63:0]$9673 + attribute \src "libresoc.v:170250.3-170268.6" + wire $0\o_ok$20$next[0:0]$9649 + attribute \src "libresoc.v:170081.3-170082.33" + wire $0\o_ok$20[0:0]$9561 + attribute \src "libresoc.v:169310.7-169310.23" + wire $0\o_ok$20[0:0]$9675 + attribute \src "libresoc.v:170178.3-170195.6" + wire $0\r_busy$next[0:0]$9600 + attribute \src "libresoc.v:170119.3-170120.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:170209.3-170249.6" + wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9607 + attribute \src "libresoc.v:170085.3-170086.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9565 + attribute \src "libresoc.v:169643.14-169643.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9678 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9608 + attribute \src "libresoc.v:170087.3-170088.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9567 + attribute \src "libresoc.v:169667.14-169667.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9680 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9609 + attribute \src "libresoc.v:170089.3-170090.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9569 + attribute \src "libresoc.v:169676.7-169676.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9682 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9610 + attribute \src "libresoc.v:170103.3-170104.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9583 + attribute \src "libresoc.v:169693.13-169693.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9684 + attribute \src "libresoc.v:170209.3-170249.6" + wire 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"OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 43 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 33 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 54 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \xer_ca_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:170070$9549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$50 + connect \B \p_ready_o + connect \Y $and$libresoc.v:170070$9549_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:170121.11-170124.4" + cell \n$117 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:170125.16-170173.4" + cell \output$118 \output + connect \cr_a \output_cr_a + connect \cr_a$21 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$25 + connect \o \output_o + connect \o$19 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$20 \output_o_ok$44 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$18 \output_sr_op__insn$42 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 + connect \sr_op__invert_in \output_sr_op__invert_in + connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 + connect \xer_ca \output_xer_ca + connect \xer_ca$22 \output_xer_ca$46 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:170174.11-170177.4" + cell \p$116 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:169255.7-169255.20" + process $proc$libresoc.v:169255$9665 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169266.13-169266.29" + process $proc$libresoc.v:169266$9666 + assign { } { } + assign $0\cr_a$21[3:0]$9667 4'0000 + sync always + sync init + update \cr_a$21 $0\cr_a$21[3:0]$9667 + end + attribute \src "libresoc.v:169275.7-169275.26" + process $proc$libresoc.v:169275$9668 + assign { } { } + assign $0\cr_a_ok$22[0:0]$9669 1'0 + sync always + sync init + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9669 + end + attribute \src "libresoc.v:169286.13-169286.29" + process $proc$libresoc.v:169286$9670 + assign { } { } + assign $0\muxid$1[1:0]$9671 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9671 + end + attribute \src "libresoc.v:169301.14-169301.43" + process $proc$libresoc.v:169301$9672 + assign { } { } + assign $0\o$19[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$19 $0\o$19[63:0]$9673 + end + attribute \src "libresoc.v:169310.7-169310.23" + process $proc$libresoc.v:169310$9674 + assign { } { } + assign $0\o_ok$20[0:0]$9675 1'0 + sync always + sync init + update \o_ok$20 $0\o_ok$20[0:0]$9675 + end + attribute \src "libresoc.v:169606.7-169606.20" + process $proc$libresoc.v:169606$9676 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:169643.14-169643.43" + process $proc$libresoc.v:169643$9677 + assign { } { } + assign $0\sr_op__fn_unit$3[13:0]$9678 14'00000000000000 + sync always + sync init + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9678 + end + attribute \src "libresoc.v:169667.14-169667.62" + process $proc$libresoc.v:169667$9679 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9680 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9680 + end + attribute \src "libresoc.v:169676.7-169676.37" + process $proc$libresoc.v:169676$9681 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9682 1'0 + sync always + sync init + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9682 + end + attribute \src "libresoc.v:169693.13-169693.43" + process $proc$libresoc.v:169693$9683 + assign { } { } + assign $0\sr_op__input_carry$12[1:0]$9684 2'00 + sync always + sync init + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9684 + end + attribute \src "libresoc.v:169706.7-169706.34" + process $proc$libresoc.v:169706$9685 + assign { } { } + assign $0\sr_op__input_cr$14[0:0]$9686 1'0 + sync always + sync init + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9686 + end + attribute \src "libresoc.v:169715.14-169715.38" + process $proc$libresoc.v:169715$9687 + assign { } { } + assign $0\sr_op__insn$18[31:0]$9688 0 + sync always + sync init + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9688 + end + attribute \src "libresoc.v:169874.13-169874.41" + process $proc$libresoc.v:169874$9689 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9690 7'0000000 + sync always + sync init + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9690 + end + attribute \src "libresoc.v:169958.7-169958.35" + process $proc$libresoc.v:169958$9691 + assign { } { } + assign $0\sr_op__invert_in$11[0:0]$9692 1'0 + sync always + sync init + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9692 + end + attribute \src "libresoc.v:169967.7-169967.34" + process $proc$libresoc.v:169967$9693 + assign { } { } + assign $0\sr_op__is_32bit$16[0:0]$9694 1'0 + sync always + sync init + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9694 + end + attribute \src "libresoc.v:169976.7-169976.35" + process $proc$libresoc.v:169976$9695 + assign { } { } + assign $0\sr_op__is_signed$17[0:0]$9696 1'0 + sync always + sync init + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9696 + end + attribute \src "libresoc.v:169987.7-169987.31" + process $proc$libresoc.v:169987$9697 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9698 1'0 + sync always + sync init + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9698 + end + attribute \src "libresoc.v:169996.7-169996.31" + process $proc$libresoc.v:169996$9699 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9700 1'0 + sync always + sync init + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9700 + end + attribute \src "libresoc.v:170003.7-170003.38" + process $proc$libresoc.v:170003$9701 + assign { } { } + assign $0\sr_op__output_carry$13[0:0]$9702 1'0 + sync always + sync init + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9702 + end + attribute \src "libresoc.v:170012.7-170012.35" + process $proc$libresoc.v:170012$9703 + assign { } { } + assign $0\sr_op__output_cr$15[0:0]$9704 1'0 + sync always + sync init + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9704 + end + attribute \src "libresoc.v:170023.7-170023.31" + process $proc$libresoc.v:170023$9705 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9706 1'0 + sync always + sync init + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9706 + end + attribute \src "libresoc.v:170032.7-170032.31" + process $proc$libresoc.v:170032$9707 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9708 1'0 + sync always + sync init + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9708 + end + attribute \src "libresoc.v:170039.7-170039.35" + process $proc$libresoc.v:170039$9709 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9710 1'0 + sync always + sync init + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9710 + end + attribute \src "libresoc.v:170048.13-170048.31" + process $proc$libresoc.v:170048$9711 + assign { } { } + assign $0\xer_ca$23[1:0]$9712 2'00 + sync always + sync init + update \xer_ca$23 $0\xer_ca$23[1:0]$9712 + end + attribute \src "libresoc.v:170057.7-170057.28" + process $proc$libresoc.v:170057$9713 + assign { } { } + assign $0\xer_ca_ok$24[0:0]$9714 1'0 + sync always + sync init + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9714 + end + attribute \src "libresoc.v:170071.3-170072.37" + process $proc$libresoc.v:170071$9550 + assign { } { } + assign $0\xer_ca$23[1:0]$9551 \xer_ca$23$next + sync posedge \coresync_clk + update \xer_ca$23 $0\xer_ca$23[1:0]$9551 + end + attribute \src "libresoc.v:170073.3-170074.43" + process $proc$libresoc.v:170073$9552 + assign { } { } + assign $0\xer_ca_ok$24[0:0]$9553 \xer_ca_ok$24$next + sync posedge \coresync_clk + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9553 + end + attribute \src "libresoc.v:170075.3-170076.33" + process $proc$libresoc.v:170075$9554 + assign { } { } + assign $0\cr_a$21[3:0]$9555 \cr_a$21$next + sync posedge \coresync_clk + update \cr_a$21 $0\cr_a$21[3:0]$9555 + end + attribute \src "libresoc.v:170077.3-170078.39" + process $proc$libresoc.v:170077$9556 + assign { } { } + assign $0\cr_a_ok$22[0:0]$9557 \cr_a_ok$22$next + sync posedge \coresync_clk + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9557 + end + attribute \src "libresoc.v:170079.3-170080.27" + process $proc$libresoc.v:170079$9558 + assign { } { } + assign $0\o$19[63:0]$9559 \o$19$next + sync posedge \coresync_clk + update \o$19 $0\o$19[63:0]$9559 + end + attribute \src "libresoc.v:170081.3-170082.33" + process $proc$libresoc.v:170081$9560 + assign { } { } + assign $0\o_ok$20[0:0]$9561 \o_ok$20$next + sync posedge \coresync_clk + update \o_ok$20 $0\o_ok$20[0:0]$9561 + end + attribute \src "libresoc.v:170083.3-170084.55" + process $proc$libresoc.v:170083$9562 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9563 \sr_op__insn_type$2$next + sync posedge \coresync_clk + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9563 + end + attribute \src "libresoc.v:170085.3-170086.51" + process $proc$libresoc.v:170085$9564 + assign { } { } + assign $0\sr_op__fn_unit$3[13:0]$9565 \sr_op__fn_unit$3$next + sync posedge \coresync_clk + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9565 + end + attribute \src "libresoc.v:170087.3-170088.65" + process $proc$libresoc.v:170087$9566 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9567 \sr_op__imm_data__data$4$next + sync posedge \coresync_clk + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9567 + end + attribute \src "libresoc.v:170089.3-170090.61" + process $proc$libresoc.v:170089$9568 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9569 \sr_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9569 + end + attribute \src "libresoc.v:170091.3-170092.49" + process $proc$libresoc.v:170091$9570 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9571 \sr_op__rc__rc$6$next + sync posedge \coresync_clk + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9571 + end + attribute \src "libresoc.v:170093.3-170094.49" + process $proc$libresoc.v:170093$9572 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9573 \sr_op__rc__ok$7$next + sync posedge \coresync_clk + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9573 + end + attribute \src "libresoc.v:170095.3-170096.49" + process $proc$libresoc.v:170095$9574 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9575 \sr_op__oe__oe$8$next + sync posedge \coresync_clk + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9575 + end + attribute \src "libresoc.v:170097.3-170098.49" + process $proc$libresoc.v:170097$9576 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9577 \sr_op__oe__ok$9$next + sync posedge \coresync_clk + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9577 + end + attribute \src "libresoc.v:170099.3-170100.57" + process $proc$libresoc.v:170099$9578 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9579 \sr_op__write_cr0$10$next + sync posedge \coresync_clk + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9579 + end + attribute \src "libresoc.v:170101.3-170102.57" + process $proc$libresoc.v:170101$9580 + assign { } { } + assign $0\sr_op__invert_in$11[0:0]$9581 \sr_op__invert_in$11$next + sync posedge \coresync_clk + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9581 + end + attribute \src "libresoc.v:170103.3-170104.61" + process $proc$libresoc.v:170103$9582 + assign { } { } + assign $0\sr_op__input_carry$12[1:0]$9583 \sr_op__input_carry$12$next + sync posedge \coresync_clk + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9583 + end + attribute \src "libresoc.v:170105.3-170106.63" + process $proc$libresoc.v:170105$9584 + assign { } { } + assign $0\sr_op__output_carry$13[0:0]$9585 \sr_op__output_carry$13$next + sync posedge \coresync_clk + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9585 + end + attribute \src "libresoc.v:170107.3-170108.55" + process $proc$libresoc.v:170107$9586 + assign { } { } + assign $0\sr_op__input_cr$14[0:0]$9587 \sr_op__input_cr$14$next + sync posedge \coresync_clk + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9587 + end + attribute \src "libresoc.v:170109.3-170110.57" + process $proc$libresoc.v:170109$9588 + assign { } { } + assign $0\sr_op__output_cr$15[0:0]$9589 \sr_op__output_cr$15$next + sync posedge \coresync_clk + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9589 + end + attribute \src "libresoc.v:170111.3-170112.55" + process $proc$libresoc.v:170111$9590 + assign { } { } + assign $0\sr_op__is_32bit$16[0:0]$9591 \sr_op__is_32bit$16$next + sync posedge \coresync_clk + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9591 + end + attribute \src "libresoc.v:170113.3-170114.57" + process $proc$libresoc.v:170113$9592 + assign { } { } + assign $0\sr_op__is_signed$17[0:0]$9593 \sr_op__is_signed$17$next + sync posedge \coresync_clk + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9593 + end + attribute \src "libresoc.v:170115.3-170116.47" + process $proc$libresoc.v:170115$9594 + assign { } { } + assign $0\sr_op__insn$18[31:0]$9595 \sr_op__insn$18$next + sync posedge \coresync_clk + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 + end + attribute \src "libresoc.v:170117.3-170118.33" + process $proc$libresoc.v:170117$9596 + assign { } { } + assign $0\muxid$1[1:0]$9597 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9597 + end + attribute \src "libresoc.v:170119.3-170120.29" + process $proc$libresoc.v:170119$9598 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:170178.3-170195.6" + process $proc$libresoc.v:170178$9599 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9600 $2\r_busy$next[0:0]$9602 + attribute \src "libresoc.v:170179.5-170179.29" + switch \initial + attribute \src "libresoc.v:170179.9-170179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9601 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9601 1'0 + case + assign $1\r_busy$next[0:0]$9601 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9602 1'0 + case + assign $2\r_busy$next[0:0]$9602 $1\r_busy$next[0:0]$9601 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9600 + end + attribute \src "libresoc.v:170196.3-170208.6" + process $proc$libresoc.v:170196$9603 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9604 $1\muxid$1$next[1:0]$9605 + attribute \src "libresoc.v:170197.5-170197.29" + switch \initial + attribute \src "libresoc.v:170197.9-170197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9605 \muxid$53 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9605 \muxid$53 + case + assign $1\muxid$1$next[1:0]$9605 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9604 + end + attribute \src "libresoc.v:170209.3-170249.6" + process $proc$libresoc.v:170209$9606 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[13:0]$9607 $1\sr_op__fn_unit$3$next[13:0]$9624 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$12$next[1:0]$9610 $1\sr_op__input_carry$12$next[1:0]$9627 + assign $0\sr_op__input_cr$14$next[0:0]$9611 $1\sr_op__input_cr$14$next[0:0]$9628 + assign $0\sr_op__insn$18$next[31:0]$9612 $1\sr_op__insn$18$next[31:0]$9629 + assign $0\sr_op__insn_type$2$next[6:0]$9613 $1\sr_op__insn_type$2$next[6:0]$9630 + assign $0\sr_op__invert_in$11$next[0:0]$9614 $1\sr_op__invert_in$11$next[0:0]$9631 + assign $0\sr_op__is_32bit$16$next[0:0]$9615 $1\sr_op__is_32bit$16$next[0:0]$9632 + assign $0\sr_op__is_signed$17$next[0:0]$9616 $1\sr_op__is_signed$17$next[0:0]$9633 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$13$next[0:0]$9619 $1\sr_op__output_carry$13$next[0:0]$9636 + assign $0\sr_op__output_cr$15$next[0:0]$9620 $1\sr_op__output_cr$15$next[0:0]$9637 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$9623 $1\sr_op__write_cr0$10$next[0:0]$9640 + assign $0\sr_op__imm_data__data$4$next[63:0]$9608 $2\sr_op__imm_data__data$4$next[63:0]$9641 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9609 $2\sr_op__imm_data__ok$5$next[0:0]$9642 + assign $0\sr_op__oe__oe$8$next[0:0]$9617 $2\sr_op__oe__oe$8$next[0:0]$9643 + assign $0\sr_op__oe__ok$9$next[0:0]$9618 $2\sr_op__oe__ok$9$next[0:0]$9644 + assign $0\sr_op__rc__ok$7$next[0:0]$9621 $2\sr_op__rc__ok$7$next[0:0]$9645 + assign $0\sr_op__rc__rc$6$next[0:0]$9622 $2\sr_op__rc__rc$6$next[0:0]$9646 + attribute \src "libresoc.v:170210.5-170210.29" + switch \initial + attribute \src "libresoc.v:170210.9-170210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + case + assign $1\sr_op__fn_unit$3$next[13:0]$9624 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9625 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9626 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9627 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9628 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9629 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9630 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9631 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9632 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9633 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9634 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9635 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9636 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9637 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9638 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9639 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9640 \sr_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9646 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9645 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9643 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9644 1'0 + case + assign $2\sr_op__imm_data__data$4$next[63:0]$9641 $1\sr_op__imm_data__data$4$next[63:0]$9625 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 $1\sr_op__imm_data__ok$5$next[0:0]$9626 + assign $2\sr_op__oe__oe$8$next[0:0]$9643 $1\sr_op__oe__oe$8$next[0:0]$9634 + assign $2\sr_op__oe__ok$9$next[0:0]$9644 $1\sr_op__oe__ok$9$next[0:0]$9635 + assign $2\sr_op__rc__ok$7$next[0:0]$9645 $1\sr_op__rc__ok$7$next[0:0]$9638 + assign $2\sr_op__rc__rc$6$next[0:0]$9646 $1\sr_op__rc__rc$6$next[0:0]$9639 + end + sync always + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9607 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9608 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9609 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9610 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9611 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9612 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9613 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9614 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9615 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9616 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9617 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9618 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9619 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9620 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9621 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9622 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9623 + end + attribute \src "libresoc.v:170250.3-170268.6" + process $proc$libresoc.v:170250$9647 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$19$next[63:0]$9648 $1\o$19$next[63:0]$9650 + assign { } { } + assign $0\o_ok$20$next[0:0]$9649 $2\o_ok$20$next[0:0]$9652 + attribute \src "libresoc.v:170251.5-170251.29" + switch \initial + attribute \src "libresoc.v:170251.9-170251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } + case + assign $1\o$19$next[63:0]$9650 \o$19 + assign $1\o_ok$20$next[0:0]$9651 \o_ok$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$20$next[0:0]$9652 1'0 + case + assign $2\o_ok$20$next[0:0]$9652 $1\o_ok$20$next[0:0]$9651 + end + sync always + update \o$19$next $0\o$19$next[63:0]$9648 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9649 + end + attribute \src "libresoc.v:170269.3-170287.6" + process $proc$libresoc.v:170269$9653 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$21$next[3:0]$9654 $1\cr_a$21$next[3:0]$9656 + assign { } { } + assign $0\cr_a_ok$22$next[0:0]$9655 $2\cr_a_ok$22$next[0:0]$9658 + attribute \src "libresoc.v:170270.5-170270.29" + switch \initial + attribute \src "libresoc.v:170270.9-170270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$21$next[3:0]$9656 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9657 \cr_a_ok$22 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$22$next[0:0]$9658 1'0 + case + assign $2\cr_a_ok$22$next[0:0]$9658 $1\cr_a_ok$22$next[0:0]$9657 + end + sync always + update \cr_a$21$next $0\cr_a$21$next[3:0]$9654 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9655 + end + attribute \src "libresoc.v:170288.3-170306.6" + process $proc$libresoc.v:170288$9659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$23$next[1:0]$9660 $1\xer_ca$23$next[1:0]$9662 + assign { } { } + assign $0\xer_ca_ok$24$next[0:0]$9661 $2\xer_ca_ok$24$next[0:0]$9664 + attribute \src "libresoc.v:170289.5-170289.29" + switch \initial + attribute \src "libresoc.v:170289.9-170289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } + case + assign $1\xer_ca$23$next[1:0]$9662 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9663 \xer_ca_ok$24 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$24$next[0:0]$9664 1'0 + case + assign $2\xer_ca_ok$24$next[0:0]$9664 $1\xer_ca_ok$24$next[0:0]$9663 + end + sync always + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9660 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9661 + end + connect \$51 $and$libresoc.v:170070$9549_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } + connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } + connect \muxid$53 \output_muxid$25 + connect \p_valid_i_p_ready_o \$51 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$50 \p_valid_i + connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:170327.1-171291.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" +attribute \generator "nMigen" +module \pipe2$35 + attribute \src "libresoc.v:171197.3-171215.6" + wire width 64 $0\fast1$11$next[63:0]$9783 + attribute \src "libresoc.v:171052.3-171053.35" + wire width 64 $0\fast1$11[63:0]$9724 + attribute \src "libresoc.v:170339.14-170339.47" + wire width 64 $0\fast1$11[63:0]$9807 + attribute \src "libresoc.v:171197.3-171215.6" + wire $0\fast1_ok$next[0:0]$9782 + attribute \src "libresoc.v:171054.3-171055.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:171216.3-171234.6" + wire width 64 $0\fast2$12$next[63:0]$9789 + attribute \src "libresoc.v:171048.3-171049.35" + wire width 64 $0\fast2$12[63:0]$9721 + attribute \src "libresoc.v:170355.14-170355.47" + wire width 64 $0\fast2$12[63:0]$9810 + attribute \src "libresoc.v:171216.3-171234.6" + wire $0\fast2_ok$next[0:0]$9788 + attribute \src "libresoc.v:171050.3-171051.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:170328.7-170328.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171254.3-171272.6" + wire width 64 $0\msr$next[63:0]$9800 + attribute \src "libresoc.v:171040.3-171041.23" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:171254.3-171272.6" + wire $0\msr_ok$next[0:0]$9801 + attribute \src "libresoc.v:171042.3-171043.29" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:171144.3-171156.6" + wire width 2 $0\muxid$1$next[1:0]$9754 + attribute \src "libresoc.v:171078.3-171079.33" + wire width 2 $0\muxid$1[1:0]$9747 + attribute \src "libresoc.v:170633.13-170633.29" + wire width 2 $0\muxid$1[1:0]$9815 + attribute \src "libresoc.v:171235.3-171253.6" + wire width 64 $0\nia$next[63:0]$9794 + attribute \src "libresoc.v:171044.3-171045.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:171235.3-171253.6" + wire $0\nia_ok$next[0:0]$9795 + attribute \src "libresoc.v:171046.3-171047.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:171178.3-171196.6" + wire width 64 $0\o$next[63:0]$9776 + attribute \src "libresoc.v:171056.3-171057.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:171178.3-171196.6" + wire $0\o_ok$next[0:0]$9777 + attribute \src "libresoc.v:171058.3-171059.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:171126.3-171143.6" + wire $0\r_busy$next[0:0]$9750 + attribute \src "libresoc.v:171080.3-171081.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9757 + attribute \src "libresoc.v:171068.3-171069.47" + wire width 64 $0\trap_op__cia$6[63:0]$9737 + attribute \src "libresoc.v:170694.14-170694.53" + wire width 64 $0\trap_op__cia$6[63:0]$9822 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9758 + attribute \src "libresoc.v:171062.3-171063.55" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9731 + attribute \src "libresoc.v:170731.14-170731.45" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9824 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9759 + attribute \src "libresoc.v:171064.3-171065.49" + wire width 32 $0\trap_op__insn$4[31:0]$9733 + attribute \src "libresoc.v:170757.14-170757.39" + wire width 32 $0\trap_op__insn$4[31:0]$9826 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9760 + attribute \src "libresoc.v:171060.3-171061.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9729 + attribute \src "libresoc.v:170914.13-170914.43" + wire width 7 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\main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 19 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 18 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 22 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 23 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 21 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 13 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 29 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 28 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:171039$9715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$25 + connect \B \p_ready_o + connect \Y $and$libresoc.v:171039$9715_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171082.13-171117.4" + cell \main$38 \main + connect \fast1 \main_fast1 + connect \fast1$11 \main_fast1$23 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$12 \main_fast2$24 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$13 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$18 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$16 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 + connect \trap_op__ldst_exc \main_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$17 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$20 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171118.10-171121.4" + cell \n$37 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171122.10-171125.4" + cell \p$36 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:170328.7-170328.20" + process $proc$libresoc.v:170328$9805 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170339.14-170339.47" + process $proc$libresoc.v:170339$9806 + assign { } { } + assign $0\fast1$11[63:0]$9807 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$11 $0\fast1$11[63:0]$9807 + end + attribute \src "libresoc.v:170346.7-170346.22" + process $proc$libresoc.v:170346$9808 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:170355.14-170355.47" + process $proc$libresoc.v:170355$9809 + assign { } { } + assign $0\fast2$12[63:0]$9810 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$12 $0\fast2$12[63:0]$9810 + end + attribute \src "libresoc.v:170362.7-170362.22" + process $proc$libresoc.v:170362$9811 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:170617.14-170617.40" + process $proc$libresoc.v:170617$9812 + assign { } { } + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr $1\msr[63:0] + end + attribute \src "libresoc.v:170624.7-170624.20" + process $proc$libresoc.v:170624$9813 + assign { } { } + assign $1\msr_ok[0:0] 1'0 + sync always + sync init + update \msr_ok $1\msr_ok[0:0] + end + attribute \src "libresoc.v:170633.13-170633.29" + process $proc$libresoc.v:170633$9814 + assign { } { } + assign $0\muxid$1[1:0]$9815 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9815 + end + attribute \src "libresoc.v:170646.14-170646.40" + process $proc$libresoc.v:170646$9816 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:170653.7-170653.20" + process $proc$libresoc.v:170653$9817 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:170660.14-170660.38" + process $proc$libresoc.v:170660$9818 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:170667.7-170667.18" + process $proc$libresoc.v:170667$9819 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:170681.7-170681.20" + process $proc$libresoc.v:170681$9820 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:170694.14-170694.53" + process $proc$libresoc.v:170694$9821 + assign { } { } + assign $0\trap_op__cia$6[63:0]$9822 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9822 + end + attribute \src "libresoc.v:170731.14-170731.45" + process $proc$libresoc.v:170731$9823 + assign { } { } + assign $0\trap_op__fn_unit$3[13:0]$9824 14'00000000000000 + sync always + sync init + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9824 + end + attribute \src "libresoc.v:170757.14-170757.39" + process $proc$libresoc.v:170757$9825 + assign { } { } + assign $0\trap_op__insn$4[31:0]$9826 0 + sync always + sync init + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9826 + end + attribute \src "libresoc.v:170914.13-170914.43" + process $proc$libresoc.v:170914$9827 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$9828 7'0000000 + sync always + sync init + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9828 + end + attribute \src "libresoc.v:171000.7-171000.35" + process $proc$libresoc.v:171000$9829 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$9830 1'0 + sync always + sync init + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9830 + end + attribute \src "libresoc.v:171007.13-171007.43" + process $proc$libresoc.v:171007$9831 + assign { } { } + assign $0\trap_op__ldst_exc$10[7:0]$9832 8'00000000 + sync always + sync init + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9832 + end + attribute \src "libresoc.v:171018.14-171018.53" + process $proc$libresoc.v:171018$9833 + assign { } { } + assign $0\trap_op__msr$5[63:0]$9834 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9834 + end + attribute \src "libresoc.v:171027.14-171027.46" + process $proc$libresoc.v:171027$9835 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$9836 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9836 + end + attribute \src "libresoc.v:171036.13-171036.42" + process $proc$libresoc.v:171036$9837 + assign { } { } + assign $0\trap_op__traptype$8[7:0]$9838 8'00000000 + sync always + sync init + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9838 + end + attribute \src "libresoc.v:171040.3-171041.23" + process $proc$libresoc.v:171040$9716 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "libresoc.v:171042.3-171043.29" + process $proc$libresoc.v:171042$9717 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:171044.3-171045.23" + process $proc$libresoc.v:171044$9718 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:171046.3-171047.29" + process $proc$libresoc.v:171046$9719 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:171048.3-171049.35" + process $proc$libresoc.v:171048$9720 + assign { } { } + assign $0\fast2$12[63:0]$9721 \fast2$12$next + sync posedge \coresync_clk + update \fast2$12 $0\fast2$12[63:0]$9721 + end + attribute \src "libresoc.v:171050.3-171051.33" + process $proc$libresoc.v:171050$9722 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:171052.3-171053.35" + process $proc$libresoc.v:171052$9723 + assign { } { } + assign $0\fast1$11[63:0]$9724 \fast1$11$next + sync posedge \coresync_clk + update \fast1$11 $0\fast1$11[63:0]$9724 + end + attribute \src "libresoc.v:171054.3-171055.33" + process $proc$libresoc.v:171054$9725 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:171056.3-171057.19" + process $proc$libresoc.v:171056$9726 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:171058.3-171059.25" + process $proc$libresoc.v:171058$9727 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:171060.3-171061.59" + process $proc$libresoc.v:171060$9728 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$9729 \trap_op__insn_type$2$next + sync posedge \coresync_clk + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9729 + end + attribute \src "libresoc.v:171062.3-171063.55" + process $proc$libresoc.v:171062$9730 + assign { } { } + assign $0\trap_op__fn_unit$3[13:0]$9731 \trap_op__fn_unit$3$next + sync posedge \coresync_clk + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9731 + end + attribute \src "libresoc.v:171064.3-171065.49" + process $proc$libresoc.v:171064$9732 + assign { } { } + assign $0\trap_op__insn$4[31:0]$9733 \trap_op__insn$4$next + sync posedge \coresync_clk + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 + end + attribute \src "libresoc.v:171066.3-171067.47" + process $proc$libresoc.v:171066$9734 + assign { } { } + assign $0\trap_op__msr$5[63:0]$9735 \trap_op__msr$5$next + sync posedge \coresync_clk + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9735 + end + attribute \src "libresoc.v:171068.3-171069.47" + process $proc$libresoc.v:171068$9736 + assign { } { } + assign $0\trap_op__cia$6[63:0]$9737 \trap_op__cia$6$next + sync posedge \coresync_clk + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9737 + end + attribute \src "libresoc.v:171070.3-171071.57" + process $proc$libresoc.v:171070$9738 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$9739 \trap_op__is_32bit$7$next + sync posedge \coresync_clk + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9739 + end + attribute \src "libresoc.v:171072.3-171073.57" + process $proc$libresoc.v:171072$9740 + assign { } { } + assign $0\trap_op__traptype$8[7:0]$9741 \trap_op__traptype$8$next + sync posedge \coresync_clk + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9741 + end + attribute \src "libresoc.v:171074.3-171075.57" + process $proc$libresoc.v:171074$9742 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$9743 \trap_op__trapaddr$9$next + sync posedge \coresync_clk + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 + end + attribute \src "libresoc.v:171076.3-171077.59" + process $proc$libresoc.v:171076$9744 + assign { } { } + assign $0\trap_op__ldst_exc$10[7:0]$9745 \trap_op__ldst_exc$10$next + sync posedge \coresync_clk + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9745 + end + attribute \src "libresoc.v:171078.3-171079.33" + process $proc$libresoc.v:171078$9746 + assign { } { } + assign $0\muxid$1[1:0]$9747 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9747 + end + attribute \src "libresoc.v:171080.3-171081.29" + process $proc$libresoc.v:171080$9748 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:171126.3-171143.6" + process $proc$libresoc.v:171126$9749 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9750 $2\r_busy$next[0:0]$9752 + attribute \src "libresoc.v:171127.5-171127.29" + switch \initial + attribute \src "libresoc.v:171127.9-171127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9751 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9751 1'0 + case + assign $1\r_busy$next[0:0]$9751 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9752 1'0 + case + assign $2\r_busy$next[0:0]$9752 $1\r_busy$next[0:0]$9751 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9750 + end + attribute \src "libresoc.v:171144.3-171156.6" + process $proc$libresoc.v:171144$9753 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9754 $1\muxid$1$next[1:0]$9755 + attribute \src "libresoc.v:171145.5-171145.29" + switch \initial + attribute \src "libresoc.v:171145.9-171145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9755 \muxid$28 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9755 \muxid$28 + case + assign $1\muxid$1$next[1:0]$9755 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9754 + end + attribute \src "libresoc.v:171157.3-171177.6" + process $proc$libresoc.v:171157$9756 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$6$next[63:0]$9757 $1\trap_op__cia$6$next[63:0]$9766 + assign $0\trap_op__fn_unit$3$next[13:0]$9758 $1\trap_op__fn_unit$3$next[13:0]$9767 + assign $0\trap_op__insn$4$next[31:0]$9759 $1\trap_op__insn$4$next[31:0]$9768 + assign $0\trap_op__insn_type$2$next[6:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9769 + assign $0\trap_op__is_32bit$7$next[0:0]$9761 $1\trap_op__is_32bit$7$next[0:0]$9770 + assign $0\trap_op__ldst_exc$10$next[7:0]$9762 $1\trap_op__ldst_exc$10$next[7:0]$9771 + assign $0\trap_op__msr$5$next[63:0]$9763 $1\trap_op__msr$5$next[63:0]$9772 + assign $0\trap_op__trapaddr$9$next[12:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9773 + assign $0\trap_op__traptype$8$next[7:0]$9765 $1\trap_op__traptype$8$next[7:0]$9774 + attribute \src "libresoc.v:171158.5-171158.29" + switch \initial + attribute \src "libresoc.v:171158.9-171158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + case + assign $1\trap_op__cia$6$next[63:0]$9766 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9767 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9768 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9769 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9770 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9771 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9772 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9773 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9774 \trap_op__traptype$8 + end + sync always + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9757 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9758 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9759 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9760 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9761 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9762 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9763 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9764 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9765 + end + attribute \src "libresoc.v:171178.3-171196.6" + process $proc$libresoc.v:171178$9775 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9776 $1\o$next[63:0]$9778 + assign { } { } + assign $0\o_ok$next[0:0]$9777 $2\o_ok$next[0:0]$9780 + attribute \src "libresoc.v:171179.5-171179.29" + switch \initial + attribute \src "libresoc.v:171179.9-171179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } + case + assign $1\o$next[63:0]$9778 \o + assign $1\o_ok$next[0:0]$9779 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9780 1'0 + case + assign $2\o_ok$next[0:0]$9780 $1\o_ok$next[0:0]$9779 + end + sync always + update \o$next $0\o$next[63:0]$9776 + update \o_ok$next $0\o_ok$next[0:0]$9777 + end + attribute \src "libresoc.v:171197.3-171215.6" + process $proc$libresoc.v:171197$9781 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$11$next[63:0]$9783 $1\fast1$11$next[63:0]$9785 + assign $0\fast1_ok$next[0:0]$9782 $2\fast1_ok$next[0:0]$9786 + attribute \src "libresoc.v:171198.5-171198.29" + switch \initial + attribute \src "libresoc.v:171198.9-171198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } + case + assign $1\fast1_ok$next[0:0]$9784 \fast1_ok + assign $1\fast1$11$next[63:0]$9785 \fast1$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$9786 1'0 + case + assign $2\fast1_ok$next[0:0]$9786 $1\fast1_ok$next[0:0]$9784 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$9782 + update \fast1$11$next $0\fast1$11$next[63:0]$9783 + end + attribute \src "libresoc.v:171216.3-171234.6" + process $proc$libresoc.v:171216$9787 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$12$next[63:0]$9789 $1\fast2$12$next[63:0]$9791 + assign $0\fast2_ok$next[0:0]$9788 $2\fast2_ok$next[0:0]$9792 + attribute \src "libresoc.v:171217.5-171217.29" + switch \initial + attribute \src "libresoc.v:171217.9-171217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } + case + assign $1\fast2_ok$next[0:0]$9790 \fast2_ok + assign $1\fast2$12$next[63:0]$9791 \fast2$12 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$9792 1'0 + case + assign $2\fast2_ok$next[0:0]$9792 $1\fast2_ok$next[0:0]$9790 + end + sync always + update \fast2_ok$next $0\fast2_ok$next[0:0]$9788 + update \fast2$12$next $0\fast2$12$next[63:0]$9789 + end + attribute \src "libresoc.v:171235.3-171253.6" + process $proc$libresoc.v:171235$9793 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$9794 $1\nia$next[63:0]$9796 + assign { } { } + assign $0\nia_ok$next[0:0]$9795 $2\nia_ok$next[0:0]$9798 + attribute \src "libresoc.v:171236.5-171236.29" + switch \initial + attribute \src "libresoc.v:171236.9-171236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } + case + assign $1\nia$next[63:0]$9796 \nia + assign $1\nia_ok$next[0:0]$9797 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$9798 1'0 + case + assign $2\nia_ok$next[0:0]$9798 $1\nia_ok$next[0:0]$9797 + end + sync always + update \nia$next $0\nia$next[63:0]$9794 + update \nia_ok$next $0\nia_ok$next[0:0]$9795 + end + attribute \src "libresoc.v:171254.3-171272.6" + process $proc$libresoc.v:171254$9799 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr$next[63:0]$9800 $1\msr$next[63:0]$9802 + assign { } { } + assign $0\msr_ok$next[0:0]$9801 $2\msr_ok$next[0:0]$9804 + attribute \src "libresoc.v:171255.5-171255.29" + switch \initial + attribute \src "libresoc.v:171255.9-171255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } + case + assign $1\msr$next[63:0]$9802 \msr + assign $1\msr_ok$next[0:0]$9803 \msr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_ok$next[0:0]$9804 1'0 + case + assign $2\msr_ok$next[0:0]$9804 $1\msr_ok$next[0:0]$9803 + end + sync always + update \msr$next $0\msr$next[63:0]$9800 + update \msr_ok$next $0\msr_ok$next[0:0]$9801 + end + connect \$26 $and$libresoc.v:171039$9715_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } + connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } + connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } + connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } + connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } + connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } + connect \muxid$28 \main_muxid$13 + connect \p_valid_i_p_ready_o \$26 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$25 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:171295.1-172798.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" +attribute \generator "nMigen" +module \pipe_end + attribute \src "libresoc.v:172636.3-172654.6" + wire width 4 $0\cr_a$next[3:0]$9895 + attribute \src "libresoc.v:172455.3-172456.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:172636.3-172654.6" + wire $0\cr_a_ok$next[0:0]$9896 + attribute \src "libresoc.v:172457.3-172458.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:171296.7-171296.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172724.3-172765.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9920 + attribute \src "libresoc.v:172495.3-172496.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9882 + attribute \src "libresoc.v:171337.13-171337.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9966 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9921 + attribute \src "libresoc.v:172465.3-172466.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9852 + attribute \src "libresoc.v:171376.14-171376.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9968 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9922 + attribute \src "libresoc.v:172467.3-172468.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9854 + attribute \src "libresoc.v:171400.14-171400.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9970 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9923 + attribute \src "libresoc.v:172469.3-172470.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9856 + attribute \src "libresoc.v:171409.7-171409.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9972 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9924 + attribute \src "libresoc.v:172483.3-172484.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9870 + attribute \src "libresoc.v:171426.13-171426.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9974 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9925 + attribute \src "libresoc.v:172497.3-172498.57" + wire width 32 $0\logical_op__insn$19[31:0]$9884 + attribute \src "libresoc.v:171439.14-171439.43" + wire width 32 $0\logical_op__insn$19[31:0]$9976 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9926 + attribute \src "libresoc.v:172463.3-172464.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9850 + attribute \src "libresoc.v:171598.13-171598.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9978 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__invert_in$10$next[0:0]$9927 + attribute \src "libresoc.v:172479.3-172480.67" + wire $0\logical_op__invert_in$10[0:0]$9866 + attribute \src "libresoc.v:171682.7-171682.40" + wire $0\logical_op__invert_in$10[0:0]$9980 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__invert_out$13$next[0:0]$9928 + attribute \src "libresoc.v:172485.3-172486.69" + wire $0\logical_op__invert_out$13[0:0]$9872 + attribute \src "libresoc.v:171691.7-171691.41" + wire $0\logical_op__invert_out$13[0:0]$9982 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9929 + attribute \src "libresoc.v:172491.3-172492.65" + wire $0\logical_op__is_32bit$16[0:0]$9878 + attribute \src "libresoc.v:171700.7-171700.39" + wire $0\logical_op__is_32bit$16[0:0]$9984 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__is_signed$17$next[0:0]$9930 + attribute \src "libresoc.v:172493.3-172494.67" + wire $0\logical_op__is_signed$17[0:0]$9880 + attribute \src "libresoc.v:171709.7-171709.40" + wire $0\logical_op__is_signed$17[0:0]$9986 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9931 + attribute \src "libresoc.v:172475.3-172476.59" + wire $0\logical_op__oe__oe$8[0:0]$9862 + attribute \src "libresoc.v:171718.7-171718.36" + wire $0\logical_op__oe__oe$8[0:0]$9988 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9932 + attribute \src "libresoc.v:172477.3-172478.59" + wire $0\logical_op__oe__ok$9[0:0]$9864 + attribute \src "libresoc.v:171729.7-171729.36" + wire $0\logical_op__oe__ok$9[0:0]$9990 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__output_carry$15$next[0:0]$9933 + attribute \src "libresoc.v:172489.3-172490.73" + wire $0\logical_op__output_carry$15[0:0]$9876 + attribute \src "libresoc.v:171736.7-171736.43" + wire $0\logical_op__output_carry$15[0:0]$9992 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9934 + attribute \src "libresoc.v:172473.3-172474.59" + wire $0\logical_op__rc__ok$7[0:0]$9860 + attribute \src "libresoc.v:171745.7-171745.36" + wire $0\logical_op__rc__ok$7[0:0]$9994 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9935 + attribute \src "libresoc.v:172471.3-172472.59" + wire $0\logical_op__rc__rc$6[0:0]$9858 + attribute \src "libresoc.v:171754.7-171754.36" + wire $0\logical_op__rc__rc$6[0:0]$9996 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9936 + attribute \src "libresoc.v:172487.3-172488.67" + wire $0\logical_op__write_cr0$14[0:0]$9874 + attribute \src "libresoc.v:171763.7-171763.40" + wire $0\logical_op__write_cr0$14[0:0]$9998 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__zero_a$11$next[0:0]$9937 + attribute \src "libresoc.v:171772.7-171772.37" + wire $0\logical_op__zero_a$11[0:0]$10000 + attribute \src "libresoc.v:172481.3-172482.61" + wire $0\logical_op__zero_a$11[0:0]$9868 + attribute \src "libresoc.v:172711.3-172723.6" + wire width 2 $0\muxid$1$next[1:0]$9917 + attribute \src "libresoc.v:171781.13-171781.29" + wire width 2 $0\muxid$1[1:0]$10002 + attribute \src "libresoc.v:172499.3-172500.33" + wire width 2 $0\muxid$1[1:0]$9886 + attribute \src "libresoc.v:172617.3-172635.6" + wire width 64 $0\o$next[63:0]$9889 + attribute \src "libresoc.v:172459.3-172460.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:172617.3-172635.6" + wire $0\o_ok$next[0:0]$9890 + attribute \src "libresoc.v:172461.3-172462.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:172693.3-172710.6" + wire $0\r_busy$next[0:0]$9913 + attribute \src "libresoc.v:172501.3-172502.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:172655.3-172673.6" + wire width 2 $0\xer_ov$next[1:0]$9901 + attribute \src "libresoc.v:172451.3-172452.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:172655.3-172673.6" + wire $0\xer_ov_ok$next[0:0]$9902 + attribute \src "libresoc.v:172453.3-172454.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:172674.3-172692.6" + wire $0\xer_so$20$next[0:0]$9908 + attribute \src "libresoc.v:172432.7-172432.25" + wire $0\xer_so$20[0:0]$10009 + attribute \src "libresoc.v:172447.3-172448.37" + wire $0\xer_so$20[0:0]$9841 + attribute \src "libresoc.v:172674.3-172692.6" + wire $0\xer_so_ok$next[0:0]$9907 + attribute \src "libresoc.v:172449.3-172450.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:172636.3-172654.6" + wire width 4 $1\cr_a$next[3:0]$9897 + attribute \src "libresoc.v:171305.13-171305.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:172636.3-172654.6" + wire $1\cr_a_ok$next[0:0]$9898 + attribute \src "libresoc.v:171314.7-171314.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:172724.3-172765.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9938 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9939 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9940 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9941 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9942 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9943 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9944 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__invert_in$10$next[0:0]$9945 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__invert_out$13$next[0:0]$9946 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9947 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__is_signed$17$next[0:0]$9948 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9949 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9950 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__output_carry$15$next[0:0]$9951 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9952 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9953 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9954 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__zero_a$11$next[0:0]$9955 + attribute \src "libresoc.v:172711.3-172723.6" + wire width 2 $1\muxid$1$next[1:0]$9918 + attribute \src "libresoc.v:172617.3-172635.6" + wire width 64 $1\o$next[63:0]$9891 + attribute \src "libresoc.v:171794.14-171794.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:172617.3-172635.6" + wire $1\o_ok$next[0:0]$9892 + attribute \src "libresoc.v:171801.7-171801.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:172693.3-172710.6" + wire $1\r_busy$next[0:0]$9914 + attribute \src "libresoc.v:172397.7-172397.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:172655.3-172673.6" + wire width 2 $1\xer_ov$next[1:0]$9903 + attribute \src "libresoc.v:172412.13-172412.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:172655.3-172673.6" + wire $1\xer_ov_ok$next[0:0]$9904 + attribute \src "libresoc.v:172419.7-172419.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:172674.3-172692.6" + wire $1\xer_so$20$next[0:0]$9910 + attribute \src "libresoc.v:172674.3-172692.6" + wire $1\xer_so_ok$next[0:0]$9909 + attribute \src "libresoc.v:172437.7-172437.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:172636.3-172654.6" + wire $2\cr_a_ok$next[0:0]$9899 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9956 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9957 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9958 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9959 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9960 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9961 + attribute \src "libresoc.v:172617.3-172635.6" + wire $2\o_ok$next[0:0]$9893 + attribute \src "libresoc.v:172693.3-172710.6" + wire $2\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:172655.3-172673.6" + wire $2\xer_ov_ok$next[0:0]$9905 + attribute \src "libresoc.v:172674.3-172692.6" + wire $2\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:172446.18-172446.118" + wire $and$libresoc.v:172446$9839_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "libresoc.v:171296.7-171296.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 46 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \output_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \output_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_stage_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 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\o_ok$21 \output_o_ok$61 + connect \xer_ov \output_xer_ov + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:172560.16-172612.4" + cell \output_stage \output_stage + connect \div_by_zero \output_stage_div_by_zero + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \dividend_neg \output_stage_dividend_neg + connect \divisor_neg \output_stage_divisor_neg + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 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attribute \src "libresoc.v:171305.13-171305.24" + process $proc$libresoc.v:171305$9963 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:171314.7-171314.21" + process $proc$libresoc.v:171314$9964 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:171337.13-171337.45" + process $proc$libresoc.v:171337$9965 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9966 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9966 + end + attribute \src "libresoc.v:171376.14-171376.48" + process $proc$libresoc.v:171376$9967 + assign { } { } + assign $0\logical_op__fn_unit$3[13:0]$9968 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9968 + end + attribute \src "libresoc.v:171400.14-171400.67" + process $proc$libresoc.v:171400$9969 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9970 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9970 + end + attribute \src "libresoc.v:171409.7-171409.42" + process $proc$libresoc.v:171409$9971 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9972 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9972 + end + attribute \src "libresoc.v:171426.13-171426.48" + process $proc$libresoc.v:171426$9973 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9974 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9974 + end + attribute \src "libresoc.v:171439.14-171439.43" + process $proc$libresoc.v:171439$9975 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9976 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9976 + end + attribute \src "libresoc.v:171598.13-171598.46" + process $proc$libresoc.v:171598$9977 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9978 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9978 + end + attribute \src "libresoc.v:171682.7-171682.40" + process $proc$libresoc.v:171682$9979 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9980 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9980 + end + attribute \src "libresoc.v:171691.7-171691.41" + process $proc$libresoc.v:171691$9981 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9982 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9982 + end + attribute \src "libresoc.v:171700.7-171700.39" + process $proc$libresoc.v:171700$9983 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9984 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9984 + end + attribute \src "libresoc.v:171709.7-171709.40" + process $proc$libresoc.v:171709$9985 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9986 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9986 + end + attribute \src "libresoc.v:171718.7-171718.36" + process $proc$libresoc.v:171718$9987 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9988 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9988 + end + attribute \src "libresoc.v:171729.7-171729.36" + process $proc$libresoc.v:171729$9989 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9990 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9990 + end + attribute \src "libresoc.v:171736.7-171736.43" + process $proc$libresoc.v:171736$9991 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9992 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9992 + end + attribute \src "libresoc.v:171745.7-171745.36" + process $proc$libresoc.v:171745$9993 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9994 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9994 + end + attribute \src "libresoc.v:171754.7-171754.36" + process $proc$libresoc.v:171754$9995 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9996 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9996 + end + attribute \src "libresoc.v:171763.7-171763.40" + process $proc$libresoc.v:171763$9997 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9998 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9998 + end + attribute \src "libresoc.v:171772.7-171772.37" + process $proc$libresoc.v:171772$9999 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$10000 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10000 + end + attribute \src "libresoc.v:171781.13-171781.29" + process $proc$libresoc.v:171781$10001 + assign { } { } + assign $0\muxid$1[1:0]$10002 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$10002 + end + attribute \src "libresoc.v:171794.14-171794.38" + process $proc$libresoc.v:171794$10003 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:171801.7-171801.18" + process $proc$libresoc.v:171801$10004 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:172397.7-172397.20" + process $proc$libresoc.v:172397$10005 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:172412.13-172412.26" + process $proc$libresoc.v:172412$10006 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:172419.7-172419.23" + process $proc$libresoc.v:172419$10007 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:172432.7-172432.25" + process $proc$libresoc.v:172432$10008 + assign { } { } + assign $0\xer_so$20[0:0]$10009 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$10009 + end + attribute \src "libresoc.v:172437.7-172437.23" + process $proc$libresoc.v:172437$10010 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:172447.3-172448.37" + process $proc$libresoc.v:172447$9840 + assign { } { } + assign $0\xer_so$20[0:0]$9841 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$9841 + end + attribute \src "libresoc.v:172449.3-172450.35" + process $proc$libresoc.v:172449$9842 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:172451.3-172452.29" + process $proc$libresoc.v:172451$9843 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:172453.3-172454.35" + process $proc$libresoc.v:172453$9844 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:172455.3-172456.25" + process $proc$libresoc.v:172455$9845 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:172457.3-172458.31" + process $proc$libresoc.v:172457$9846 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:172459.3-172460.19" + process $proc$libresoc.v:172459$9847 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:172461.3-172462.25" + process $proc$libresoc.v:172461$9848 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:172463.3-172464.65" + process $proc$libresoc.v:172463$9849 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9850 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9850 + end + attribute \src "libresoc.v:172465.3-172466.61" + process $proc$libresoc.v:172465$9851 + assign { } { } + assign $0\logical_op__fn_unit$3[13:0]$9852 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9852 + end + attribute \src "libresoc.v:172467.3-172468.75" + process $proc$libresoc.v:172467$9853 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9854 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9854 + end + attribute \src "libresoc.v:172469.3-172470.71" + process $proc$libresoc.v:172469$9855 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9856 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9856 + end + attribute \src "libresoc.v:172471.3-172472.59" + process $proc$libresoc.v:172471$9857 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9858 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9858 + end + attribute \src "libresoc.v:172473.3-172474.59" + process $proc$libresoc.v:172473$9859 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9860 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9860 + end + attribute \src "libresoc.v:172475.3-172476.59" + process $proc$libresoc.v:172475$9861 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9862 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9862 + end + attribute \src "libresoc.v:172477.3-172478.59" + process $proc$libresoc.v:172477$9863 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9864 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9864 + end + attribute \src "libresoc.v:172479.3-172480.67" + process $proc$libresoc.v:172479$9865 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9866 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9866 + end + attribute \src "libresoc.v:172481.3-172482.61" + process $proc$libresoc.v:172481$9867 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9868 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9868 + end + attribute \src "libresoc.v:172483.3-172484.71" + process $proc$libresoc.v:172483$9869 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9870 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9870 + end + attribute \src "libresoc.v:172485.3-172486.69" + process $proc$libresoc.v:172485$9871 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9872 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9872 + end + attribute \src "libresoc.v:172487.3-172488.67" + process $proc$libresoc.v:172487$9873 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9874 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9874 + end + attribute \src "libresoc.v:172489.3-172490.73" + process $proc$libresoc.v:172489$9875 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9876 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9876 + end + attribute \src "libresoc.v:172491.3-172492.65" + process $proc$libresoc.v:172491$9877 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9878 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9878 + end + attribute \src "libresoc.v:172493.3-172494.67" + process $proc$libresoc.v:172493$9879 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9880 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9880 + end + attribute \src "libresoc.v:172495.3-172496.65" + process $proc$libresoc.v:172495$9881 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9882 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9882 + end + attribute \src "libresoc.v:172497.3-172498.57" + process $proc$libresoc.v:172497$9883 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9884 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9884 + end + attribute \src "libresoc.v:172499.3-172500.33" + process $proc$libresoc.v:172499$9885 + assign { } { } + assign $0\muxid$1[1:0]$9886 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9886 + end + attribute \src "libresoc.v:172501.3-172502.29" + process $proc$libresoc.v:172501$9887 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:172617.3-172635.6" + process $proc$libresoc.v:172617$9888 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9889 $1\o$next[63:0]$9891 + assign { } { } + assign $0\o_ok$next[0:0]$9890 $2\o_ok$next[0:0]$9893 + attribute \src "libresoc.v:172618.5-172618.29" + switch \initial + attribute \src "libresoc.v:172618.9-172618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$9891 \o + assign $1\o_ok$next[0:0]$9892 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9893 1'0 + case + assign $2\o_ok$next[0:0]$9893 $1\o_ok$next[0:0]$9892 + end + sync always + update \o$next $0\o$next[63:0]$9889 + update \o_ok$next $0\o_ok$next[0:0]$9890 + end + attribute \src "libresoc.v:172636.3-172654.6" + process $proc$libresoc.v:172636$9894 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9895 $1\cr_a$next[3:0]$9897 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9896 $2\cr_a_ok$next[0:0]$9899 + attribute \src "libresoc.v:172637.5-172637.29" + switch \initial + attribute \src "libresoc.v:172637.9-172637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$9897 \cr_a + assign $1\cr_a_ok$next[0:0]$9898 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9899 1'0 + case + assign $2\cr_a_ok$next[0:0]$9899 $1\cr_a_ok$next[0:0]$9898 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9895 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9896 + end + attribute \src "libresoc.v:172655.3-172673.6" + process $proc$libresoc.v:172655$9900 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9901 $1\xer_ov$next[1:0]$9903 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9902 $2\xer_ov_ok$next[0:0]$9905 + attribute \src "libresoc.v:172656.5-172656.29" + switch \initial + attribute \src "libresoc.v:172656.9-172656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$9903 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9904 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9905 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9905 $1\xer_ov_ok$next[0:0]$9904 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9901 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9902 + end + attribute \src "libresoc.v:172674.3-172692.6" + process $proc$libresoc.v:172674$9906 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$9908 $1\xer_so$20$next[0:0]$9910 + assign $0\xer_so_ok$next[0:0]$9907 $2\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:172675.5-172675.29" + switch \initial + attribute \src "libresoc.v:172675.9-172675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$9909 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9910 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9911 1'0 + case + assign $2\xer_so_ok$next[0:0]$9911 $1\xer_so_ok$next[0:0]$9909 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9907 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9908 + end + attribute \src "libresoc.v:172693.3-172710.6" + process $proc$libresoc.v:172693$9912 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9913 $2\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:172694.5-172694.29" + switch \initial + attribute \src "libresoc.v:172694.9-172694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9914 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9914 1'0 + case + assign $1\r_busy$next[0:0]$9914 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9915 1'0 + case + assign $2\r_busy$next[0:0]$9915 $1\r_busy$next[0:0]$9914 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9913 + end + attribute \src "libresoc.v:172711.3-172723.6" + process $proc$libresoc.v:172711$9916 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9917 $1\muxid$1$next[1:0]$9918 + attribute \src "libresoc.v:172712.5-172712.29" + switch \initial + attribute \src "libresoc.v:172712.9-172712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9918 \muxid$76 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9918 \muxid$76 + case + assign $1\muxid$1$next[1:0]$9918 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9917 + end + attribute \src "libresoc.v:172724.3-172765.6" + process $proc$libresoc.v:172724$9919 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$9920 $1\logical_op__data_len$18$next[3:0]$9938 + assign $0\logical_op__fn_unit$3$next[13:0]$9921 $1\logical_op__fn_unit$3$next[13:0]$9939 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$9924 $1\logical_op__input_carry$12$next[1:0]$9942 + assign $0\logical_op__insn$19$next[31:0]$9925 $1\logical_op__insn$19$next[31:0]$9943 + assign $0\logical_op__insn_type$2$next[6:0]$9926 $1\logical_op__insn_type$2$next[6:0]$9944 + assign $0\logical_op__invert_in$10$next[0:0]$9927 $1\logical_op__invert_in$10$next[0:0]$9945 + assign $0\logical_op__invert_out$13$next[0:0]$9928 $1\logical_op__invert_out$13$next[0:0]$9946 + assign $0\logical_op__is_32bit$16$next[0:0]$9929 $1\logical_op__is_32bit$16$next[0:0]$9947 + assign $0\logical_op__is_signed$17$next[0:0]$9930 $1\logical_op__is_signed$17$next[0:0]$9948 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$9933 $1\logical_op__output_carry$15$next[0:0]$9951 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$9936 $1\logical_op__write_cr0$14$next[0:0]$9954 + assign $0\logical_op__zero_a$11$next[0:0]$9937 $1\logical_op__zero_a$11$next[0:0]$9955 + assign $0\logical_op__imm_data__data$4$next[63:0]$9922 $2\logical_op__imm_data__data$4$next[63:0]$9956 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9923 $2\logical_op__imm_data__ok$5$next[0:0]$9957 + assign $0\logical_op__oe__oe$8$next[0:0]$9931 $2\logical_op__oe__oe$8$next[0:0]$9958 + assign $0\logical_op__oe__ok$9$next[0:0]$9932 $2\logical_op__oe__ok$9$next[0:0]$9959 + assign $0\logical_op__rc__ok$7$next[0:0]$9934 $2\logical_op__rc__ok$7$next[0:0]$9960 + assign $0\logical_op__rc__rc$6$next[0:0]$9935 $2\logical_op__rc__rc$6$next[0:0]$9961 + attribute \src "libresoc.v:172725.5-172725.29" + switch \initial + attribute \src "libresoc.v:172725.9-172725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$9938 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9939 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9940 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9941 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9942 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9943 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9944 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9945 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9946 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9947 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9948 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9949 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9950 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9951 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9952 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9953 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9954 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9955 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$9956 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9961 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9960 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9958 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9959 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$9956 $1\logical_op__imm_data__data$4$next[63:0]$9940 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 $1\logical_op__imm_data__ok$5$next[0:0]$9941 + assign $2\logical_op__oe__oe$8$next[0:0]$9958 $1\logical_op__oe__oe$8$next[0:0]$9949 + assign $2\logical_op__oe__ok$9$next[0:0]$9959 $1\logical_op__oe__ok$9$next[0:0]$9950 + assign $2\logical_op__rc__ok$7$next[0:0]$9960 $1\logical_op__rc__ok$7$next[0:0]$9952 + assign $2\logical_op__rc__rc$6$next[0:0]$9961 $1\logical_op__rc__rc$6$next[0:0]$9953 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9920 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9921 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9922 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9923 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9924 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9925 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9926 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9927 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9928 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9929 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9930 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9931 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9932 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9933 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9934 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9935 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9936 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9937 + end + connect \$74 $and$libresoc.v:172446$9839_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "libresoc.v:172802.1-173789.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "libresoc.v:173714.3-173728.6" + wire $0\div_by_zero$54$next[0:0]$10190 + attribute \src "libresoc.v:173388.3-173389.47" + wire $0\div_by_zero$54[0:0]$10025 + attribute \src "libresoc.v:172825.7-172825.30" + wire $0\div_by_zero$54[0:0]$10207 + attribute \src "libresoc.v:173510.3-173521.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "libresoc.v:173498.3-173509.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:173486.3-173497.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:173684.3-173698.6" + wire $0\dive_abs_ov32$52$next[0:0]$10182 + attribute \src "libresoc.v:173392.3-173393.51" + wire $0\dive_abs_ov32$52[0:0]$10029 + attribute \src "libresoc.v:172849.7-172849.32" + wire $0\dive_abs_ov32$52[0:0]$10209 + attribute \src "libresoc.v:173699.3-173713.6" + wire $0\dive_abs_ov64$53$next[0:0]$10186 + attribute \src "libresoc.v:173390.3-173391.51" + wire $0\dive_abs_ov64$53[0:0]$10027 + attribute \src "libresoc.v:172857.7-172857.32" + wire $0\dive_abs_ov64$53[0:0]$10211 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $0\dividend$68$next[127:0]$10194 + attribute \src "libresoc.v:173386.3-173387.41" + wire width 128 $0\dividend$68[127:0]$10023 + attribute \src "libresoc.v:172863.15-172863.68" + wire width 128 $0\dividend$68[127:0]$10213 + attribute \src "libresoc.v:173669.3-173683.6" + wire $0\dividend_neg$51$next[0:0]$10178 + attribute \src "libresoc.v:173394.3-173395.49" + wire $0\dividend_neg$51[0:0]$10031 + attribute \src "libresoc.v:172871.7-172871.31" + wire $0\dividend_neg$51[0:0]$10215 + attribute \src "libresoc.v:173654.3-173668.6" + wire $0\divisor_neg$50$next[0:0]$10174 + attribute \src "libresoc.v:173396.3-173397.47" + wire $0\divisor_neg$50[0:0]$10033 + attribute \src "libresoc.v:172879.7-172879.30" + wire $0\divisor_neg$50[0:0]$10217 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10198 + attribute \src "libresoc.v:173384.3-173385.57" + wire width 64 $0\divisor_radicand$65[63:0]$10021 + attribute \src "libresoc.v:172885.14-172885.58" + wire width 64 $0\divisor_radicand$65[63:0]$10219 + attribute \src "libresoc.v:173522.3-173549.6" + wire $0\empty$next[0:0]$10091 + attribute \src "libresoc.v:173442.3-173443.27" + wire $0\empty[0:0] + attribute \src "libresoc.v:172803.7-172803.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10101 + attribute \src "libresoc.v:173436.3-173437.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10073 + attribute \src "libresoc.v:172897.13-172897.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10222 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10102 + attribute \src "libresoc.v:173406.3-173407.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10043 + attribute \src "libresoc.v:172950.14-172950.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10224 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10103 + attribute \src "libresoc.v:173408.3-173409.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10045 + attribute \src "libresoc.v:172956.14-172956.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10226 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10104 + attribute \src "libresoc.v:173410.3-173411.73" + wire $0\logical_op__imm_data__ok$32[0:0]$10047 + attribute \src "libresoc.v:172964.7-172964.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10228 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10105 + attribute \src "libresoc.v:173424.3-173425.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10061 + attribute \src "libresoc.v:172986.13-172986.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10230 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10106 + attribute \src "libresoc.v:173438.3-173439.57" + wire width 32 $0\logical_op__insn$46[31:0]$10075 + attribute \src "libresoc.v:172994.14-172994.43" + wire width 32 $0\logical_op__insn$46[31:0]$10232 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10107 + attribute \src "libresoc.v:173404.3-173405.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$10041 + attribute \src "libresoc.v:173227.13-173227.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10234 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__invert_in$37$next[0:0]$10108 + attribute \src "libresoc.v:173420.3-173421.67" + wire $0\logical_op__invert_in$37[0:0]$10057 + attribute \src "libresoc.v:173235.7-173235.40" + wire $0\logical_op__invert_in$37[0:0]$10236 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__invert_out$40$next[0:0]$10109 + attribute \src "libresoc.v:173426.3-173427.69" + wire $0\logical_op__invert_out$40[0:0]$10063 + attribute \src "libresoc.v:173243.7-173243.41" + wire $0\logical_op__invert_out$40[0:0]$10238 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10110 + attribute \src "libresoc.v:173432.3-173433.65" + wire $0\logical_op__is_32bit$43[0:0]$10069 + attribute \src "libresoc.v:173251.7-173251.39" + wire $0\logical_op__is_32bit$43[0:0]$10240 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__is_signed$44$next[0:0]$10111 + attribute \src "libresoc.v:173434.3-173435.67" + wire $0\logical_op__is_signed$44[0:0]$10071 + attribute \src "libresoc.v:173259.7-173259.40" + wire $0\logical_op__is_signed$44[0:0]$10242 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10112 + attribute \src "libresoc.v:173416.3-173417.61" + wire $0\logical_op__oe__oe$35[0:0]$10053 + attribute \src "libresoc.v:173265.7-173265.37" + wire $0\logical_op__oe__oe$35[0:0]$10244 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10113 + attribute \src "libresoc.v:173418.3-173419.61" + wire $0\logical_op__oe__ok$36[0:0]$10055 + attribute \src "libresoc.v:173273.7-173273.37" + wire $0\logical_op__oe__ok$36[0:0]$10246 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__output_carry$42$next[0:0]$10114 + attribute \src "libresoc.v:173430.3-173431.73" + wire $0\logical_op__output_carry$42[0:0]$10067 + attribute \src "libresoc.v:173283.7-173283.43" + wire $0\logical_op__output_carry$42[0:0]$10248 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10115 + attribute \src "libresoc.v:173414.3-173415.61" + wire $0\logical_op__rc__ok$34[0:0]$10051 + attribute \src "libresoc.v:173289.7-173289.37" + wire $0\logical_op__rc__ok$34[0:0]$10250 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10116 + attribute \src "libresoc.v:173412.3-173413.61" + wire $0\logical_op__rc__rc$33[0:0]$10049 + attribute \src "libresoc.v:173297.7-173297.37" + wire $0\logical_op__rc__rc$33[0:0]$10252 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10117 + attribute \src "libresoc.v:173428.3-173429.67" + wire $0\logical_op__write_cr0$41[0:0]$10065 + attribute \src "libresoc.v:173307.7-173307.40" + wire $0\logical_op__write_cr0$41[0:0]$10254 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__zero_a$38$next[0:0]$10118 + attribute \src "libresoc.v:173422.3-173423.61" + wire $0\logical_op__zero_a$38[0:0]$10059 + attribute \src "libresoc.v:173315.7-173315.37" + wire $0\logical_op__zero_a$38[0:0]$10256 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $0\muxid$28$next[1:0]$10097 + attribute \src "libresoc.v:173440.3-173441.35" + wire width 2 $0\muxid$28[1:0]$10077 + attribute \src "libresoc.v:173323.13-173323.30" + wire width 2 $0\muxid$28[1:0]$10258 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $0\operation$69$next[1:0]$10202 + attribute \src "libresoc.v:173382.3-173383.43" + wire width 2 $0\operation$69[1:0]$10019 + attribute \src "libresoc.v:173333.13-173333.34" + wire width 2 $0\operation$69[1:0]$10260 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $0\ra$47$next[63:0]$10162 + attribute \src "libresoc.v:173402.3-173403.29" + wire width 64 $0\ra$47[63:0]$10039 + attribute \src "libresoc.v:173347.14-173347.44" + wire width 64 $0\ra$47[63:0]$10262 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $0\rb$48$next[63:0]$10166 + attribute \src "libresoc.v:173400.3-173401.29" + wire width 64 $0\rb$48[63:0]$10037 + attribute \src "libresoc.v:173355.14-173355.44" + wire width 64 $0\rb$48[63:0]$10264 + attribute \src "libresoc.v:173477.3-173485.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10085 + attribute \src "libresoc.v:173444.3-173445.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:173468.3-173476.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10082 + attribute \src "libresoc.v:173446.3-173447.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:173639.3-173653.6" + wire $0\xer_so$49$next[0:0]$10170 + attribute \src "libresoc.v:173398.3-173399.37" + wire $0\xer_so$49[0:0]$10035 + attribute \src "libresoc.v:173373.7-173373.25" + wire $0\xer_so$49[0:0]$10268 + attribute \src "libresoc.v:173714.3-173728.6" + wire $1\div_by_zero$54$next[0:0]$10191 + attribute \src "libresoc.v:173510.3-173521.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:173498.3-173509.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:173486.3-173497.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:173684.3-173698.6" + wire $1\dive_abs_ov32$52$next[0:0]$10183 + attribute \src "libresoc.v:173699.3-173713.6" + wire $1\dive_abs_ov64$53$next[0:0]$10187 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $1\dividend$68$next[127:0]$10195 + attribute \src "libresoc.v:173669.3-173683.6" + wire $1\dividend_neg$51$next[0:0]$10179 + attribute \src "libresoc.v:173654.3-173668.6" + wire $1\divisor_neg$50$next[0:0]$10175 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10199 + attribute \src "libresoc.v:173522.3-173549.6" + wire $1\empty$next[0:0]$10092 + attribute \src "libresoc.v:172889.7-172889.19" + wire $1\empty[0:0] + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10119 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10120 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10121 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10122 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10123 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10124 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10125 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__invert_in$37$next[0:0]$10126 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__invert_out$40$next[0:0]$10127 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10128 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__is_signed$44$next[0:0]$10129 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10130 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10131 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__output_carry$42$next[0:0]$10132 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10133 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10134 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10135 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__zero_a$38$next[0:0]$10136 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $1\muxid$28$next[1:0]$10098 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $1\operation$69$next[1:0]$10203 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $1\ra$47$next[63:0]$10163 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $1\rb$48$next[63:0]$10167 + attribute \src "libresoc.v:173477.3-173485.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10086 + attribute \src "libresoc.v:173361.15-173361.84" + wire width 128 $1\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:173468.3-173476.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10083 + attribute \src "libresoc.v:173365.13-173365.45" + wire width 7 $1\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:173639.3-173653.6" + wire $1\xer_so$49$next[0:0]$10171 + attribute \src "libresoc.v:173714.3-173728.6" + wire $2\div_by_zero$54$next[0:0]$10192 + attribute \src "libresoc.v:173684.3-173698.6" + wire $2\dive_abs_ov32$52$next[0:0]$10184 + attribute \src "libresoc.v:173699.3-173713.6" + wire $2\dive_abs_ov64$53$next[0:0]$10188 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $2\dividend$68$next[127:0]$10196 + attribute \src "libresoc.v:173669.3-173683.6" + wire $2\dividend_neg$51$next[0:0]$10180 + attribute \src "libresoc.v:173654.3-173668.6" + wire $2\divisor_neg$50$next[0:0]$10176 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10200 + attribute \src "libresoc.v:173522.3-173549.6" + wire $2\empty$next[0:0]$10093 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10137 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10138 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10139 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10140 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10141 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10142 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10143 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__invert_in$37$next[0:0]$10144 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__invert_out$40$next[0:0]$10145 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10146 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__is_signed$44$next[0:0]$10147 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10148 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10149 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__output_carry$42$next[0:0]$10150 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10151 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10152 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10153 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__zero_a$38$next[0:0]$10154 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $2\muxid$28$next[1:0]$10099 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $2\operation$69$next[1:0]$10204 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $2\ra$47$next[63:0]$10164 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $2\rb$48$next[63:0]$10168 + attribute \src "libresoc.v:173639.3-173653.6" + wire $2\xer_so$49$next[0:0]$10172 + attribute \src "libresoc.v:173522.3-173549.6" + wire $3\empty$next[0:0]$10094 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10155 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10156 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10157 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10158 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10159 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10160 + attribute \src "libresoc.v:173522.3-173549.6" + wire $4\empty$next[0:0]$10095 + attribute \src "libresoc.v:173380.18-173380.98" + wire $and$libresoc.v:173380$10016_Y + attribute \src "libresoc.v:173381.18-173381.107" + wire $and$libresoc.v:173381$10017_Y + attribute \src "libresoc.v:173377.18-173377.92" + wire width 192 $extend$libresoc.v:173377$10012_Y + attribute \src "libresoc.v:173379.18-173379.119" + wire $ge$libresoc.v:173379$10015_Y + attribute \src "libresoc.v:173378.18-173378.93" + wire $not$libresoc.v:173378$10014_Y + attribute \src "libresoc.v:173377.18-173377.92" + wire width 192 $pos$libresoc.v:173377$10013_Y + attribute \src "libresoc.v:173376.18-173376.138" + wire width 191 $sshl$libresoc.v:173376$10011_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty$next + attribute \src "libresoc.v:172803.7-172803.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $and $and$libresoc.v:173380$10016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:173380$10016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + cell $and $and$libresoc.v:173381$10017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:173381$10017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $extend$libresoc.v:173377$10012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$libresoc.v:173377$10012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:173379$10015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \saved_state_q_bits_known + connect \B 6'111111 + connect \Y $ge$libresoc.v:173379$10015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $not $not$libresoc.v:173378$10014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$libresoc.v:173378$10014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $pos$libresoc.v:173377$10013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$libresoc.v:173377$10012_Y + connect \Y $pos$libresoc.v:173377$10013_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $sshl $sshl$libresoc.v:173376$10011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:173376$10011_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173448.18-173452.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173453.18-173459.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173460.10-173463.4" + cell \n$80 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173464.10-173467.4" + cell \p$79 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:172803.7-172803.20" + process $proc$libresoc.v:172803$10205 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172825.7-172825.30" + process $proc$libresoc.v:172825$10206 + assign { } { } + assign $0\div_by_zero$54[0:0]$10207 1'0 + sync always + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10207 + end + attribute \src "libresoc.v:172849.7-172849.32" + process $proc$libresoc.v:172849$10208 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10209 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10209 + end + attribute \src "libresoc.v:172857.7-172857.32" + process $proc$libresoc.v:172857$10210 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10211 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10211 + end + attribute \src "libresoc.v:172863.15-172863.68" + process $proc$libresoc.v:172863$10212 + assign { } { } + assign $0\dividend$68[127:0]$10213 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend$68 $0\dividend$68[127:0]$10213 + end + attribute \src "libresoc.v:172871.7-172871.31" + process $proc$libresoc.v:172871$10214 + assign { } { } + assign $0\dividend_neg$51[0:0]$10215 1'0 + sync always + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10215 + end + attribute \src "libresoc.v:172879.7-172879.30" + process $proc$libresoc.v:172879$10216 + assign { } { } + assign $0\divisor_neg$50[0:0]$10217 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10217 + end + attribute \src "libresoc.v:172885.14-172885.58" + process $proc$libresoc.v:172885$10218 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10219 + end + attribute \src "libresoc.v:172889.7-172889.19" + process $proc$libresoc.v:172889$10220 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] + end + attribute \src "libresoc.v:172897.13-172897.45" + process $proc$libresoc.v:172897$10221 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10222 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10222 + end + attribute \src "libresoc.v:172950.14-172950.49" + process $proc$libresoc.v:172950$10223 + assign { } { } + assign $0\logical_op__fn_unit$30[13:0]$10224 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10224 + end + attribute \src "libresoc.v:172956.14-172956.68" + process $proc$libresoc.v:172956$10225 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10226 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10226 + end + attribute \src "libresoc.v:172964.7-172964.43" + process $proc$libresoc.v:172964$10227 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10228 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10228 + end + attribute \src "libresoc.v:172986.13-172986.48" + process $proc$libresoc.v:172986$10229 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10230 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10230 + end + attribute \src "libresoc.v:172994.14-172994.43" + process $proc$libresoc.v:172994$10231 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10232 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10232 + end + attribute \src "libresoc.v:173227.13-173227.47" + process $proc$libresoc.v:173227$10233 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10234 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10234 + end + attribute \src "libresoc.v:173235.7-173235.40" + process $proc$libresoc.v:173235$10235 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10236 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10236 + end + attribute \src "libresoc.v:173243.7-173243.41" + process $proc$libresoc.v:173243$10237 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10238 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10238 + end + attribute \src "libresoc.v:173251.7-173251.39" + process $proc$libresoc.v:173251$10239 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10240 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10240 + end + attribute \src "libresoc.v:173259.7-173259.40" + process $proc$libresoc.v:173259$10241 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10242 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10242 + end + attribute \src "libresoc.v:173265.7-173265.37" + process $proc$libresoc.v:173265$10243 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10244 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10244 + end + attribute \src "libresoc.v:173273.7-173273.37" + process $proc$libresoc.v:173273$10245 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10246 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10246 + end + attribute \src "libresoc.v:173283.7-173283.43" + process $proc$libresoc.v:173283$10247 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10248 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10248 + end + attribute \src "libresoc.v:173289.7-173289.37" + process $proc$libresoc.v:173289$10249 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10250 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10250 + end + attribute \src "libresoc.v:173297.7-173297.37" + process $proc$libresoc.v:173297$10251 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10252 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10252 + end + attribute \src "libresoc.v:173307.7-173307.40" + process $proc$libresoc.v:173307$10253 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10254 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10254 + end + attribute \src "libresoc.v:173315.7-173315.37" + process $proc$libresoc.v:173315$10255 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10256 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10256 + end + attribute \src "libresoc.v:173323.13-173323.30" + process $proc$libresoc.v:173323$10257 + assign { } { } + assign $0\muxid$28[1:0]$10258 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$10258 + end + attribute \src "libresoc.v:173333.13-173333.34" + process $proc$libresoc.v:173333$10259 + assign { } { } + assign $0\operation$69[1:0]$10260 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$10260 + end + attribute \src "libresoc.v:173347.14-173347.44" + process $proc$libresoc.v:173347$10261 + assign { } { } + assign $0\ra$47[63:0]$10262 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$10262 + end + attribute \src "libresoc.v:173355.14-173355.44" + process $proc$libresoc.v:173355$10263 + assign { } { } + assign $0\rb$48[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$10264 + end + attribute \src "libresoc.v:173361.15-173361.84" + process $proc$libresoc.v:173361$10265 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:173365.13-173365.45" + process $proc$libresoc.v:173365$10266 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:173373.7-173373.25" + process $proc$libresoc.v:173373$10267 + assign { } { } + assign $0\xer_so$49[0:0]$10268 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$10268 + end + attribute \src "libresoc.v:173382.3-173383.43" + process $proc$libresoc.v:173382$10018 + assign { } { } + assign $0\operation$69[1:0]$10019 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$10019 + end + attribute \src "libresoc.v:173384.3-173385.57" + process $proc$libresoc.v:173384$10020 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10021 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10021 + end + attribute \src "libresoc.v:173386.3-173387.41" + process $proc$libresoc.v:173386$10022 + assign { } { } + assign $0\dividend$68[127:0]$10023 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$10023 + end + attribute \src "libresoc.v:173388.3-173389.47" + process $proc$libresoc.v:173388$10024 + assign { } { } + assign $0\div_by_zero$54[0:0]$10025 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10025 + end + attribute \src "libresoc.v:173390.3-173391.51" + process $proc$libresoc.v:173390$10026 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10027 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10027 + end + attribute \src "libresoc.v:173392.3-173393.51" + process $proc$libresoc.v:173392$10028 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10029 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10029 + end + attribute \src "libresoc.v:173394.3-173395.49" + process $proc$libresoc.v:173394$10030 + assign { } { } + assign $0\dividend_neg$51[0:0]$10031 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10031 + end + attribute \src "libresoc.v:173396.3-173397.47" + process $proc$libresoc.v:173396$10032 + assign { } { } + assign $0\divisor_neg$50[0:0]$10033 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10033 + end + attribute \src "libresoc.v:173398.3-173399.37" + process $proc$libresoc.v:173398$10034 + assign { } { } + assign $0\xer_so$49[0:0]$10035 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$10035 + end + attribute \src "libresoc.v:173400.3-173401.29" + process $proc$libresoc.v:173400$10036 + assign { } { } + assign $0\rb$48[63:0]$10037 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$10037 + end + attribute \src "libresoc.v:173402.3-173403.29" + process $proc$libresoc.v:173402$10038 + assign { } { } + assign $0\ra$47[63:0]$10039 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$10039 + end + attribute \src "libresoc.v:173404.3-173405.67" + process $proc$libresoc.v:173404$10040 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10041 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10041 + end + attribute \src "libresoc.v:173406.3-173407.63" + process $proc$libresoc.v:173406$10042 + assign { } { } + assign $0\logical_op__fn_unit$30[13:0]$10043 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10043 + end + attribute \src "libresoc.v:173408.3-173409.77" + process $proc$libresoc.v:173408$10044 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10045 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10045 + end + attribute \src "libresoc.v:173410.3-173411.73" + process $proc$libresoc.v:173410$10046 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10047 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10047 + end + attribute \src "libresoc.v:173412.3-173413.61" + process $proc$libresoc.v:173412$10048 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10049 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10049 + end + attribute \src "libresoc.v:173414.3-173415.61" + process $proc$libresoc.v:173414$10050 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10051 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10051 + end + attribute \src "libresoc.v:173416.3-173417.61" + process $proc$libresoc.v:173416$10052 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10053 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10053 + end + attribute \src "libresoc.v:173418.3-173419.61" + process $proc$libresoc.v:173418$10054 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10055 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10055 + end + attribute \src "libresoc.v:173420.3-173421.67" + process $proc$libresoc.v:173420$10056 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10057 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10057 + end + attribute \src "libresoc.v:173422.3-173423.61" + process $proc$libresoc.v:173422$10058 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10059 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10059 + end + attribute \src "libresoc.v:173424.3-173425.71" + process $proc$libresoc.v:173424$10060 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10061 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10061 + end + attribute \src "libresoc.v:173426.3-173427.69" + process $proc$libresoc.v:173426$10062 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10063 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10063 + end + attribute \src "libresoc.v:173428.3-173429.67" + process $proc$libresoc.v:173428$10064 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10065 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10065 + end + attribute \src "libresoc.v:173430.3-173431.73" + process $proc$libresoc.v:173430$10066 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10067 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10067 + end + attribute \src "libresoc.v:173432.3-173433.65" + process $proc$libresoc.v:173432$10068 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10069 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10069 + end + attribute \src "libresoc.v:173434.3-173435.67" + process $proc$libresoc.v:173434$10070 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10071 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10071 + end + attribute \src "libresoc.v:173436.3-173437.65" + process $proc$libresoc.v:173436$10072 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10073 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10073 + end + attribute \src "libresoc.v:173438.3-173439.57" + process $proc$libresoc.v:173438$10074 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10075 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10075 + end + attribute \src "libresoc.v:173440.3-173441.35" + process $proc$libresoc.v:173440$10076 + assign { } { } + assign $0\muxid$28[1:0]$10077 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$10077 + end + attribute \src "libresoc.v:173442.3-173443.27" + process $proc$libresoc.v:173442$10078 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] + end + attribute \src "libresoc.v:173444.3-173445.75" + process $proc$libresoc.v:173444$10079 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:173446.3-173447.65" + process $proc$libresoc.v:173446$10080 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:173468.3-173476.6" + process $proc$libresoc.v:173468$10081 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$10082 $1\saved_state_q_bits_known$next[6:0]$10083 + attribute \src "libresoc.v:173469.5-173469.29" + switch \initial + attribute \src "libresoc.v:173469.9-173469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$10083 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$10083 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10082 + end + attribute \src "libresoc.v:173477.3-173485.6" + process $proc$libresoc.v:173477$10084 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$10085 $1\saved_state_dividend_quotient$next[127:0]$10086 + attribute \src "libresoc.v:173478.5-173478.29" + switch \initial + attribute \src "libresoc.v:173478.9-173478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$10086 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$10086 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10085 + end + attribute \src "libresoc.v:173486.3-173497.6" + process $proc$libresoc.v:173486$10087 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:173487.5-173487.29" + switch \initial + attribute \src "libresoc.v:173487.9-173487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] + end + attribute \src "libresoc.v:173498.3-173509.6" + process $proc$libresoc.v:173498$10088 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:173499.5-173499.29" + switch \initial + attribute \src "libresoc.v:173499.9-173499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] + end + attribute \src "libresoc.v:173510.3-173521.6" + process $proc$libresoc.v:173510$10089 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:173511.5-173511.29" + switch \initial + attribute \src "libresoc.v:173511.9-173511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] + end + attribute \src "libresoc.v:173522.3-173549.6" + process $proc$libresoc.v:173522$10090 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$10091 $4\empty$next[0:0]$10095 + attribute \src "libresoc.v:173523.5-173523.29" + switch \initial + attribute \src "libresoc.v:173523.9-173523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$10092 $2\empty$next[0:0]$10093 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$10093 1'0 + case + assign $2\empty$next[0:0]$10093 \empty + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$10092 $3\empty$next[0:0]$10094 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$10094 1'1 + case + assign $3\empty$next[0:0]$10094 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$10095 1'1 + case + assign $4\empty$next[0:0]$10095 $1\empty$next[0:0]$10092 + end + sync always + update \empty$next $0\empty$next[0:0]$10091 + end + attribute \src "libresoc.v:173550.3-173564.6" + process $proc$libresoc.v:173550$10096 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$10097 $1\muxid$28$next[1:0]$10098 + attribute \src "libresoc.v:173551.5-173551.29" + switch \initial + attribute \src "libresoc.v:173551.9-173551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$10098 $2\muxid$28$next[1:0]$10099 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$10099 \muxid + case + assign $2\muxid$28$next[1:0]$10099 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$10098 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$10097 + end + attribute \src "libresoc.v:173565.3-173608.6" + process $proc$libresoc.v:173565$10100 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$10101 $1\logical_op__data_len$45$next[3:0]$10119 + assign $0\logical_op__fn_unit$30$next[13:0]$10102 $1\logical_op__fn_unit$30$next[13:0]$10120 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$10105 $1\logical_op__input_carry$39$next[1:0]$10123 + assign $0\logical_op__insn$46$next[31:0]$10106 $1\logical_op__insn$46$next[31:0]$10124 + assign $0\logical_op__insn_type$29$next[6:0]$10107 $1\logical_op__insn_type$29$next[6:0]$10125 + assign $0\logical_op__invert_in$37$next[0:0]$10108 $1\logical_op__invert_in$37$next[0:0]$10126 + assign $0\logical_op__invert_out$40$next[0:0]$10109 $1\logical_op__invert_out$40$next[0:0]$10127 + assign $0\logical_op__is_32bit$43$next[0:0]$10110 $1\logical_op__is_32bit$43$next[0:0]$10128 + assign $0\logical_op__is_signed$44$next[0:0]$10111 $1\logical_op__is_signed$44$next[0:0]$10129 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$10114 $1\logical_op__output_carry$42$next[0:0]$10132 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$10117 $1\logical_op__write_cr0$41$next[0:0]$10135 + assign $0\logical_op__zero_a$38$next[0:0]$10118 $1\logical_op__zero_a$38$next[0:0]$10136 + assign $0\logical_op__imm_data__data$31$next[63:0]$10103 $3\logical_op__imm_data__data$31$next[63:0]$10155 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10104 $3\logical_op__imm_data__ok$32$next[0:0]$10156 + assign $0\logical_op__oe__oe$35$next[0:0]$10112 $3\logical_op__oe__oe$35$next[0:0]$10157 + assign $0\logical_op__oe__ok$36$next[0:0]$10113 $3\logical_op__oe__ok$36$next[0:0]$10158 + assign $0\logical_op__rc__ok$34$next[0:0]$10115 $3\logical_op__rc__ok$34$next[0:0]$10159 + assign $0\logical_op__rc__rc$33$next[0:0]$10116 $3\logical_op__rc__rc$33$next[0:0]$10160 + attribute \src "libresoc.v:173566.5-173566.29" + switch \initial + attribute \src "libresoc.v:173566.9-173566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$10119 $2\logical_op__data_len$45$next[3:0]$10137 + assign $1\logical_op__fn_unit$30$next[13:0]$10120 $2\logical_op__fn_unit$30$next[13:0]$10138 + assign $1\logical_op__imm_data__data$31$next[63:0]$10121 $2\logical_op__imm_data__data$31$next[63:0]$10139 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 $2\logical_op__imm_data__ok$32$next[0:0]$10140 + assign $1\logical_op__input_carry$39$next[1:0]$10123 $2\logical_op__input_carry$39$next[1:0]$10141 + assign $1\logical_op__insn$46$next[31:0]$10124 $2\logical_op__insn$46$next[31:0]$10142 + assign $1\logical_op__insn_type$29$next[6:0]$10125 $2\logical_op__insn_type$29$next[6:0]$10143 + assign $1\logical_op__invert_in$37$next[0:0]$10126 $2\logical_op__invert_in$37$next[0:0]$10144 + assign $1\logical_op__invert_out$40$next[0:0]$10127 $2\logical_op__invert_out$40$next[0:0]$10145 + assign $1\logical_op__is_32bit$43$next[0:0]$10128 $2\logical_op__is_32bit$43$next[0:0]$10146 + assign $1\logical_op__is_signed$44$next[0:0]$10129 $2\logical_op__is_signed$44$next[0:0]$10147 + assign $1\logical_op__oe__oe$35$next[0:0]$10130 $2\logical_op__oe__oe$35$next[0:0]$10148 + assign $1\logical_op__oe__ok$36$next[0:0]$10131 $2\logical_op__oe__ok$36$next[0:0]$10149 + assign $1\logical_op__output_carry$42$next[0:0]$10132 $2\logical_op__output_carry$42$next[0:0]$10150 + assign $1\logical_op__rc__ok$34$next[0:0]$10133 $2\logical_op__rc__ok$34$next[0:0]$10151 + assign $1\logical_op__rc__rc$33$next[0:0]$10134 $2\logical_op__rc__rc$33$next[0:0]$10152 + assign $1\logical_op__write_cr0$41$next[0:0]$10135 $2\logical_op__write_cr0$41$next[0:0]$10153 + assign $1\logical_op__zero_a$38$next[0:0]$10136 $2\logical_op__zero_a$38$next[0:0]$10154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$10142 $2\logical_op__data_len$45$next[3:0]$10137 $2\logical_op__is_signed$44$next[0:0]$10147 $2\logical_op__is_32bit$43$next[0:0]$10146 $2\logical_op__output_carry$42$next[0:0]$10150 $2\logical_op__write_cr0$41$next[0:0]$10153 $2\logical_op__invert_out$40$next[0:0]$10145 $2\logical_op__input_carry$39$next[1:0]$10141 $2\logical_op__zero_a$38$next[0:0]$10154 $2\logical_op__invert_in$37$next[0:0]$10144 $2\logical_op__oe__ok$36$next[0:0]$10149 $2\logical_op__oe__oe$35$next[0:0]$10148 $2\logical_op__rc__ok$34$next[0:0]$10151 $2\logical_op__rc__rc$33$next[0:0]$10152 $2\logical_op__imm_data__ok$32$next[0:0]$10140 $2\logical_op__imm_data__data$31$next[63:0]$10139 $2\logical_op__fn_unit$30$next[13:0]$10138 $2\logical_op__insn_type$29$next[6:0]$10143 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$10137 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10138 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10139 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10140 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10141 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10142 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10143 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10144 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10145 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10146 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10147 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10148 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10149 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10150 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10151 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10152 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10153 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10154 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$10119 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10120 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10121 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10123 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10124 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10125 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10126 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10127 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10128 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10129 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10130 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10131 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10132 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10133 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10134 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10135 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10136 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$10155 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10160 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10159 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10157 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10158 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$10155 $1\logical_op__imm_data__data$31$next[63:0]$10121 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 $1\logical_op__imm_data__ok$32$next[0:0]$10122 + assign $3\logical_op__oe__oe$35$next[0:0]$10157 $1\logical_op__oe__oe$35$next[0:0]$10130 + assign $3\logical_op__oe__ok$36$next[0:0]$10158 $1\logical_op__oe__ok$36$next[0:0]$10131 + assign $3\logical_op__rc__ok$34$next[0:0]$10159 $1\logical_op__rc__ok$34$next[0:0]$10133 + assign $3\logical_op__rc__rc$33$next[0:0]$10160 $1\logical_op__rc__rc$33$next[0:0]$10134 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10101 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10102 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10103 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10104 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10105 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10106 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10107 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10108 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10109 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10110 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10111 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10112 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10113 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10114 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10115 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10116 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10117 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10118 + end + attribute \src "libresoc.v:173609.3-173623.6" + process $proc$libresoc.v:173609$10161 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$10162 $1\ra$47$next[63:0]$10163 + attribute \src "libresoc.v:173610.5-173610.29" + switch \initial + attribute \src "libresoc.v:173610.9-173610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$10163 $2\ra$47$next[63:0]$10164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$10164 \ra + case + assign $2\ra$47$next[63:0]$10164 \ra$47 + end + case + assign $1\ra$47$next[63:0]$10163 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$10162 + end + attribute \src "libresoc.v:173624.3-173638.6" + process $proc$libresoc.v:173624$10165 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$10166 $1\rb$48$next[63:0]$10167 + attribute \src "libresoc.v:173625.5-173625.29" + switch \initial + attribute \src "libresoc.v:173625.9-173625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$10167 $2\rb$48$next[63:0]$10168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$10168 \rb + case + assign $2\rb$48$next[63:0]$10168 \rb$48 + end + case + assign $1\rb$48$next[63:0]$10167 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$10166 + end + attribute \src "libresoc.v:173639.3-173653.6" + process $proc$libresoc.v:173639$10169 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$10170 $1\xer_so$49$next[0:0]$10171 + attribute \src "libresoc.v:173640.5-173640.29" + switch \initial + attribute \src "libresoc.v:173640.9-173640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$10171 $2\xer_so$49$next[0:0]$10172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$10172 \xer_so + case + assign $2\xer_so$49$next[0:0]$10172 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$10171 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$10170 + end + attribute \src "libresoc.v:173654.3-173668.6" + process $proc$libresoc.v:173654$10173 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$10174 $1\divisor_neg$50$next[0:0]$10175 + attribute \src "libresoc.v:173655.5-173655.29" + switch \initial + attribute \src "libresoc.v:173655.9-173655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$10175 $2\divisor_neg$50$next[0:0]$10176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$10175 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10174 + end + attribute \src "libresoc.v:173669.3-173683.6" + process $proc$libresoc.v:173669$10177 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$10178 $1\dividend_neg$51$next[0:0]$10179 + attribute \src "libresoc.v:173670.5-173670.29" + switch \initial + attribute \src "libresoc.v:173670.9-173670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$10179 $2\dividend_neg$51$next[0:0]$10180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$10179 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10178 + end + attribute \src "libresoc.v:173684.3-173698.6" + process $proc$libresoc.v:173684$10181 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$10182 $1\dive_abs_ov32$52$next[0:0]$10183 + attribute \src "libresoc.v:173685.5-173685.29" + switch \initial + attribute \src "libresoc.v:173685.9-173685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$10183 $2\dive_abs_ov32$52$next[0:0]$10184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$10183 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10182 + end + attribute \src "libresoc.v:173699.3-173713.6" + process $proc$libresoc.v:173699$10185 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$10186 $1\dive_abs_ov64$53$next[0:0]$10187 + attribute \src "libresoc.v:173700.5-173700.29" + switch \initial + attribute \src "libresoc.v:173700.9-173700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$10187 $2\dive_abs_ov64$53$next[0:0]$10188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$10187 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10186 + end + attribute \src "libresoc.v:173714.3-173728.6" + process $proc$libresoc.v:173714$10189 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$10190 $1\div_by_zero$54$next[0:0]$10191 + attribute \src "libresoc.v:173715.5-173715.29" + switch \initial + attribute \src "libresoc.v:173715.9-173715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$10191 $2\div_by_zero$54$next[0:0]$10192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$10191 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10190 + end + attribute \src "libresoc.v:173729.3-173743.6" + process $proc$libresoc.v:173729$10193 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$10194 $1\dividend$68$next[127:0]$10195 + attribute \src "libresoc.v:173730.5-173730.29" + switch \initial + attribute \src "libresoc.v:173730.9-173730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$10195 $2\dividend$68$next[127:0]$10196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$10196 \dividend + case + assign $2\dividend$68$next[127:0]$10196 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$10195 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$10194 + end + attribute \src "libresoc.v:173744.3-173758.6" + process $proc$libresoc.v:173744$10197 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$10198 $1\divisor_radicand$65$next[63:0]$10199 + attribute \src "libresoc.v:173745.5-173745.29" + switch \initial + attribute \src "libresoc.v:173745.9-173745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$10199 $2\divisor_radicand$65$next[63:0]$10200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$10199 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10198 + end + attribute \src "libresoc.v:173759.3-173773.6" + process $proc$libresoc.v:173759$10201 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$10202 $1\operation$69$next[1:0]$10203 + attribute \src "libresoc.v:173760.5-173760.29" + switch \initial + attribute \src "libresoc.v:173760.9-173760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$10203 $2\operation$69$next[1:0]$10204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$10204 \operation + case + assign $2\operation$69$next[1:0]$10204 \operation$69 + end + case + assign $1\operation$69$next[1:0]$10203 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$10202 + end + connect \$56 $sshl$libresoc.v:173376$10011_Y + connect \$55 $pos$libresoc.v:173377$10013_Y + connect \$59 $not$libresoc.v:173378$10014_Y + connect \$61 $ge$libresoc.v:173379$10015_Y + connect \$63 $and$libresoc.v:173380$10016_Y + connect \$66 $and$libresoc.v:173381$10017_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend +end +attribute \src "libresoc.v:173793.1-175338.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \generator "nMigen" +module \pipe_start + attribute \src "libresoc.v:175144.3-175156.6" + wire $0\div_by_zero$next[0:0]$10314 + attribute \src "libresoc.v:174930.3-174931.39" + wire $0\div_by_zero[0:0] + attribute \src "libresoc.v:175118.3-175130.6" + wire $0\dive_abs_ov32$next[0:0]$10308 + attribute \src "libresoc.v:174934.3-174935.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "libresoc.v:175131.3-175143.6" + wire $0\dive_abs_ov64$next[0:0]$10311 + attribute \src "libresoc.v:174932.3-174933.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "libresoc.v:175157.3-175169.6" + wire width 128 $0\dividend$next[127:0]$10317 + attribute \src "libresoc.v:174928.3-174929.33" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:175105.3-175117.6" + wire $0\dividend_neg$next[0:0]$10305 + attribute \src "libresoc.v:174936.3-174937.41" + wire $0\dividend_neg[0:0] + attribute \src "libresoc.v:175092.3-175104.6" + wire $0\divisor_neg$next[0:0]$10302 + attribute \src "libresoc.v:174938.3-174939.39" + wire $0\divisor_neg[0:0] + attribute \src "libresoc.v:175170.3-175182.6" + wire width 64 $0\divisor_radicand$next[63:0]$10320 + attribute \src "libresoc.v:174926.3-174927.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "libresoc.v:173794.7-173794.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10333 + attribute \src "libresoc.v:174978.3-174979.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10334 + attribute \src "libresoc.v:174948.3-174949.55" + wire width 14 $0\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10335 + attribute \src "libresoc.v:174950.3-174951.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10336 + attribute \src "libresoc.v:174952.3-174953.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10337 + attribute \src "libresoc.v:174966.3-174967.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 32 $0\logical_op__insn$next[31:0]$10338 + attribute \src "libresoc.v:174980.3-174981.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10339 + attribute \src "libresoc.v:174946.3-174947.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__invert_in$next[0:0]$10340 + attribute \src "libresoc.v:174962.3-174963.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__invert_out$next[0:0]$10341 + attribute \src "libresoc.v:174968.3-174969.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__is_32bit$next[0:0]$10342 + attribute \src "libresoc.v:174974.3-174975.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__is_signed$next[0:0]$10343 + attribute \src "libresoc.v:174976.3-174977.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__oe__oe$next[0:0]$10344 + attribute \src "libresoc.v:174958.3-174959.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__oe__ok$next[0:0]$10345 + attribute \src "libresoc.v:174960.3-174961.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__output_carry$next[0:0]$10346 + attribute \src "libresoc.v:174972.3-174973.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__rc__ok$next[0:0]$10347 + attribute \src "libresoc.v:174956.3-174957.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__rc__rc$next[0:0]$10348 + attribute \src "libresoc.v:174954.3-174955.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__write_cr0$next[0:0]$10349 + attribute \src "libresoc.v:174970.3-174971.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__zero_a$next[0:0]$10350 + attribute \src "libresoc.v:174964.3-174965.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:175214.3-175226.6" + wire width 2 $0\muxid$next[1:0]$10330 + attribute \src "libresoc.v:174982.3-174983.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:175183.3-175195.6" + wire width 2 $0\operation$next[1:0]$10323 + attribute \src "libresoc.v:174924.3-174925.35" + wire width 2 $0\operation[1:0] + attribute \src "libresoc.v:175196.3-175213.6" + wire $0\r_busy$next[0:0]$10326 + attribute \src "libresoc.v:174984.3-174985.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:175269.3-175281.6" + wire width 64 $0\ra$next[63:0]$10376 + attribute \src "libresoc.v:174944.3-174945.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:175282.3-175294.6" + wire width 64 $0\rb$next[63:0]$10379 + attribute \src "libresoc.v:174942.3-174943.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:175295.3-175307.6" + wire $0\xer_so$next[0:0]$10382 + attribute \src "libresoc.v:174940.3-174941.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:175144.3-175156.6" + wire $1\div_by_zero$next[0:0]$10315 + attribute \src "libresoc.v:173803.7-173803.25" + wire $1\div_by_zero[0:0] + attribute \src "libresoc.v:175118.3-175130.6" + wire $1\dive_abs_ov32$next[0:0]$10309 + attribute \src "libresoc.v:173810.7-173810.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "libresoc.v:175131.3-175143.6" + wire $1\dive_abs_ov64$next[0:0]$10312 + attribute \src "libresoc.v:173817.7-173817.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "libresoc.v:175157.3-175169.6" + wire width 128 $1\dividend$next[127:0]$10318 + attribute \src "libresoc.v:173824.15-173824.63" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:175105.3-175117.6" + wire $1\dividend_neg$next[0:0]$10306 + attribute \src "libresoc.v:173831.7-173831.26" + wire $1\dividend_neg[0:0] + attribute \src "libresoc.v:175092.3-175104.6" + wire $1\divisor_neg$next[0:0]$10303 + attribute \src "libresoc.v:173838.7-173838.25" + wire $1\divisor_neg[0:0] + attribute \src "libresoc.v:175170.3-175182.6" + wire width 64 $1\divisor_radicand$next[63:0]$10321 + attribute \src "libresoc.v:173845.14-173845.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10351 + attribute \src "libresoc.v:174128.13-174128.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10352 + attribute \src "libresoc.v:174152.14-174152.44" + wire width 14 $1\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10353 + attribute \src "libresoc.v:174191.14-174191.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10354 + attribute \src "libresoc.v:174200.7-174200.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10355 + attribute \src "libresoc.v:174213.13-174213.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 32 $1\logical_op__insn$next[31:0]$10356 + attribute \src "libresoc.v:174230.14-174230.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10357 + attribute \src "libresoc.v:174314.13-174314.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__invert_in$next[0:0]$10358 + attribute \src "libresoc.v:174473.7-174473.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__invert_out$next[0:0]$10359 + attribute \src "libresoc.v:174482.7-174482.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__is_32bit$next[0:0]$10360 + attribute \src "libresoc.v:174491.7-174491.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__is_signed$next[0:0]$10361 + attribute \src "libresoc.v:174500.7-174500.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__oe__oe$next[0:0]$10362 + attribute \src "libresoc.v:174509.7-174509.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__oe__ok$next[0:0]$10363 + attribute \src "libresoc.v:174518.7-174518.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__output_carry$next[0:0]$10364 + attribute \src "libresoc.v:174527.7-174527.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__rc__ok$next[0:0]$10365 + attribute \src "libresoc.v:174536.7-174536.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__rc__rc$next[0:0]$10366 + attribute \src "libresoc.v:174545.7-174545.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__write_cr0$next[0:0]$10367 + attribute \src "libresoc.v:174554.7-174554.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__zero_a$next[0:0]$10368 + attribute \src "libresoc.v:174563.7-174563.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:175214.3-175226.6" + wire width 2 $1\muxid$next[1:0]$10331 + attribute \src "libresoc.v:174572.13-174572.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:175183.3-175195.6" + wire width 2 $1\operation$next[1:0]$10324 + attribute \src "libresoc.v:174587.13-174587.29" + wire width 2 $1\operation[1:0] + attribute \src "libresoc.v:175196.3-175213.6" + wire $1\r_busy$next[0:0]$10327 + attribute \src "libresoc.v:174601.7-174601.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:175269.3-175281.6" + wire width 64 $1\ra$next[63:0]$10377 + attribute \src "libresoc.v:174606.14-174606.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:175282.3-175294.6" + wire width 64 $1\rb$next[63:0]$10380 + attribute \src "libresoc.v:174617.14-174617.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:175295.3-175307.6" + wire $1\xer_so$next[0:0]$10383 + attribute \src "libresoc.v:174916.7-174916.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10369 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10370 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__oe__oe$next[0:0]$10371 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__oe__ok$next[0:0]$10372 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__rc__ok$next[0:0]$10373 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__rc__rc$next[0:0]$10374 + attribute \src "libresoc.v:175196.3-175213.6" + wire $2\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:174923.18-174923.118" + wire $and$libresoc.v:174923$10269_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "libresoc.v:173794.7-173794.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$65 + attribute \src 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wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:174923$10269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$65 + connect \B \p_ready_o + connect \Y $and$libresoc.v:174923$10269_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174986.14-175031.4" + cell \input$78 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$40 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$41 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$23 + connect \ra \input_ra + connect \ra$20 \input_ra$42 + connect \rb \input_rb + connect \rb$21 \input_rb$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$44 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:175032.10-175035.4" + cell \n$77 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:175036.10-175039.4" + cell \p$76 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:175040.15-175091.4" + cell \setup_stage \setup_stage + connect \div_by_zero \setup_stage_div_by_zero + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \dividend \setup_stage_dividend + connect \dividend_neg \setup_stage_dividend_neg + connect \divisor_neg \setup_stage_divisor_neg + connect \divisor_radicand \setup_stage_divisor_radicand + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__insn \setup_stage_logical_op__insn + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 + end + attribute \src "libresoc.v:173794.7-173794.20" + process $proc$libresoc.v:173794$10384 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173803.7-173803.25" + process $proc$libresoc.v:173803$10385 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] + end + attribute \src "libresoc.v:173810.7-173810.27" + process $proc$libresoc.v:173810$10386 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:173817.7-173817.27" + process $proc$libresoc.v:173817$10387 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:173824.15-173824.63" + process $proc$libresoc.v:173824$10388 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] + end + attribute \src "libresoc.v:173831.7-173831.26" + process $proc$libresoc.v:173831$10389 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] + end + attribute \src "libresoc.v:173838.7-173838.25" + process $proc$libresoc.v:173838$10390 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] + end + attribute \src "libresoc.v:173845.14-173845.53" + process $proc$libresoc.v:173845$10391 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] + end + attribute \src "libresoc.v:174128.13-174128.40" + process $proc$libresoc.v:174128$10392 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:174152.14-174152.44" + process $proc$libresoc.v:174152$10393 + assign { } { } + assign $1\logical_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:174191.14-174191.63" + process $proc$libresoc.v:174191$10394 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:174200.7-174200.38" + process $proc$libresoc.v:174200$10395 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:174213.13-174213.43" + process $proc$libresoc.v:174213$10396 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:174230.14-174230.38" + process $proc$libresoc.v:174230$10397 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:174314.13-174314.42" + process $proc$libresoc.v:174314$10398 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:174473.7-174473.35" + process $proc$libresoc.v:174473$10399 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:174482.7-174482.36" + process $proc$libresoc.v:174482$10400 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:174491.7-174491.34" + process $proc$libresoc.v:174491$10401 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:174500.7-174500.35" + process $proc$libresoc.v:174500$10402 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:174509.7-174509.32" + process $proc$libresoc.v:174509$10403 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:174518.7-174518.32" + process $proc$libresoc.v:174518$10404 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:174527.7-174527.38" + process $proc$libresoc.v:174527$10405 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:174536.7-174536.32" + process $proc$libresoc.v:174536$10406 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:174545.7-174545.32" + process $proc$libresoc.v:174545$10407 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:174554.7-174554.35" + process $proc$libresoc.v:174554$10408 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:174563.7-174563.32" + process $proc$libresoc.v:174563$10409 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:174572.13-174572.25" + process $proc$libresoc.v:174572$10410 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:174587.13-174587.29" + process $proc$libresoc.v:174587$10411 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] + end + attribute \src "libresoc.v:174601.7-174601.20" + process $proc$libresoc.v:174601$10412 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:174606.14-174606.39" + process $proc$libresoc.v:174606$10413 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:174617.14-174617.39" + process $proc$libresoc.v:174617$10414 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:174916.7-174916.20" + process $proc$libresoc.v:174916$10415 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:174924.3-174925.35" + process $proc$libresoc.v:174924$10270 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] + end + attribute \src "libresoc.v:174926.3-174927.49" + process $proc$libresoc.v:174926$10271 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] + end + attribute \src "libresoc.v:174928.3-174929.33" + process $proc$libresoc.v:174928$10272 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] + end + attribute \src "libresoc.v:174930.3-174931.39" + process $proc$libresoc.v:174930$10273 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] + end + attribute \src "libresoc.v:174932.3-174933.43" + process $proc$libresoc.v:174932$10274 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:174934.3-174935.43" + process $proc$libresoc.v:174934$10275 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:174936.3-174937.41" + process $proc$libresoc.v:174936$10276 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] + end + attribute \src "libresoc.v:174938.3-174939.39" + process $proc$libresoc.v:174938$10277 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] + end + attribute \src "libresoc.v:174940.3-174941.29" + process $proc$libresoc.v:174940$10278 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:174942.3-174943.21" + process $proc$libresoc.v:174942$10279 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:174944.3-174945.21" + process $proc$libresoc.v:174944$10280 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:174946.3-174947.59" + process $proc$libresoc.v:174946$10281 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:174948.3-174949.55" + process $proc$libresoc.v:174948$10282 + assign { } { } + assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] + end + attribute \src "libresoc.v:174950.3-174951.69" + process $proc$libresoc.v:174950$10283 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:174952.3-174953.65" + process $proc$libresoc.v:174952$10284 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:174954.3-174955.53" + process $proc$libresoc.v:174954$10285 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:174956.3-174957.53" + process $proc$libresoc.v:174956$10286 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:174958.3-174959.53" + process $proc$libresoc.v:174958$10287 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:174960.3-174961.53" + process $proc$libresoc.v:174960$10288 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:174962.3-174963.59" + process $proc$libresoc.v:174962$10289 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:174964.3-174965.53" + process $proc$libresoc.v:174964$10290 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:174966.3-174967.63" + process $proc$libresoc.v:174966$10291 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:174968.3-174969.61" + process $proc$libresoc.v:174968$10292 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:174970.3-174971.59" + process $proc$libresoc.v:174970$10293 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:174972.3-174973.65" + process $proc$libresoc.v:174972$10294 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:174974.3-174975.57" + process $proc$libresoc.v:174974$10295 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:174976.3-174977.59" + process $proc$libresoc.v:174976$10296 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:174978.3-174979.57" + process $proc$libresoc.v:174978$10297 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:174980.3-174981.49" + process $proc$libresoc.v:174980$10298 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:174982.3-174983.27" + process $proc$libresoc.v:174982$10299 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:174984.3-174985.29" + process $proc$libresoc.v:174984$10300 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:175092.3-175104.6" + process $proc$libresoc.v:175092$10301 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$10302 $1\divisor_neg$next[0:0]$10303 + attribute \src "libresoc.v:175093.5-175093.29" + switch \initial + attribute \src "libresoc.v:175093.9-175093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$10302 + end + attribute \src "libresoc.v:175105.3-175117.6" + process $proc$libresoc.v:175105$10304 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$10305 $1\dividend_neg$next[0:0]$10306 + attribute \src "libresoc.v:175106.5-175106.29" + switch \initial + attribute \src "libresoc.v:175106.9-175106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$10305 + end + attribute \src "libresoc.v:175118.3-175130.6" + process $proc$libresoc.v:175118$10307 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$10308 $1\dive_abs_ov32$next[0:0]$10309 + attribute \src "libresoc.v:175119.5-175119.29" + switch \initial + attribute \src "libresoc.v:175119.9-175119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10308 + end + attribute \src "libresoc.v:175131.3-175143.6" + process $proc$libresoc.v:175131$10310 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$10311 $1\dive_abs_ov64$next[0:0]$10312 + attribute \src "libresoc.v:175132.5-175132.29" + switch \initial + attribute \src "libresoc.v:175132.9-175132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10311 + end + attribute \src "libresoc.v:175144.3-175156.6" + process $proc$libresoc.v:175144$10313 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$10314 $1\div_by_zero$next[0:0]$10315 + attribute \src "libresoc.v:175145.5-175145.29" + switch \initial + attribute \src "libresoc.v:175145.9-175145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$10314 + end + attribute \src "libresoc.v:175157.3-175169.6" + process $proc$libresoc.v:175157$10316 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$10317 $1\dividend$next[127:0]$10318 + attribute \src "libresoc.v:175158.5-175158.29" + switch \initial + attribute \src "libresoc.v:175158.9-175158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$10318 \dividend$97 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$10318 \dividend$97 + case + assign $1\dividend$next[127:0]$10318 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$10317 + end + attribute \src "libresoc.v:175170.3-175182.6" + process $proc$libresoc.v:175170$10319 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$10320 $1\divisor_radicand$next[63:0]$10321 + attribute \src "libresoc.v:175171.5-175171.29" + switch \initial + attribute \src "libresoc.v:175171.9-175171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10320 + end + attribute \src "libresoc.v:175183.3-175195.6" + process $proc$libresoc.v:175183$10322 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$10323 $1\operation$next[1:0]$10324 + attribute \src "libresoc.v:175184.5-175184.29" + switch \initial + attribute \src "libresoc.v:175184.9-175184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$10324 \operation$99 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$10324 \operation$99 + case + assign $1\operation$next[1:0]$10324 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$10323 + end + attribute \src "libresoc.v:175196.3-175213.6" + process $proc$libresoc.v:175196$10325 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$10326 $2\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:175197.5-175197.29" + switch \initial + attribute \src "libresoc.v:175197.9-175197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$10327 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$10327 1'0 + case + assign $1\r_busy$next[0:0]$10327 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$10328 1'0 + case + assign $2\r_busy$next[0:0]$10328 $1\r_busy$next[0:0]$10327 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$10326 + end + attribute \src "libresoc.v:175214.3-175226.6" + process $proc$libresoc.v:175214$10329 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$10330 $1\muxid$next[1:0]$10331 + attribute \src "libresoc.v:175215.5-175215.29" + switch \initial + attribute \src "libresoc.v:175215.9-175215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$10331 \muxid$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$10331 \muxid$68 + case + assign $1\muxid$next[1:0]$10331 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$10330 + end + attribute \src "libresoc.v:175227.3-175268.6" + process $proc$libresoc.v:175227$10332 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$10333 $1\logical_op__data_len$next[3:0]$10351 + assign $0\logical_op__fn_unit$next[13:0]$10334 $1\logical_op__fn_unit$next[13:0]$10352 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$10337 $1\logical_op__input_carry$next[1:0]$10355 + assign $0\logical_op__insn$next[31:0]$10338 $1\logical_op__insn$next[31:0]$10356 + assign $0\logical_op__insn_type$next[6:0]$10339 $1\logical_op__insn_type$next[6:0]$10357 + assign $0\logical_op__invert_in$next[0:0]$10340 $1\logical_op__invert_in$next[0:0]$10358 + assign $0\logical_op__invert_out$next[0:0]$10341 $1\logical_op__invert_out$next[0:0]$10359 + assign $0\logical_op__is_32bit$next[0:0]$10342 $1\logical_op__is_32bit$next[0:0]$10360 + assign $0\logical_op__is_signed$next[0:0]$10343 $1\logical_op__is_signed$next[0:0]$10361 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$10346 $1\logical_op__output_carry$next[0:0]$10364 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$10349 $1\logical_op__write_cr0$next[0:0]$10367 + assign $0\logical_op__zero_a$next[0:0]$10350 $1\logical_op__zero_a$next[0:0]$10368 + assign $0\logical_op__imm_data__data$next[63:0]$10335 $2\logical_op__imm_data__data$next[63:0]$10369 + assign $0\logical_op__imm_data__ok$next[0:0]$10336 $2\logical_op__imm_data__ok$next[0:0]$10370 + assign $0\logical_op__oe__oe$next[0:0]$10344 $2\logical_op__oe__oe$next[0:0]$10371 + assign $0\logical_op__oe__ok$next[0:0]$10345 $2\logical_op__oe__ok$next[0:0]$10372 + assign $0\logical_op__rc__ok$next[0:0]$10347 $2\logical_op__rc__ok$next[0:0]$10373 + assign $0\logical_op__rc__rc$next[0:0]$10348 $2\logical_op__rc__rc$next[0:0]$10374 + attribute \src "libresoc.v:175228.5-175228.29" + switch \initial + attribute \src "libresoc.v:175228.9-175228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$10351 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10352 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10353 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10354 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10355 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10356 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10357 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10358 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10359 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10360 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10361 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10362 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10363 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10364 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10365 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10366 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10367 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10368 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$10369 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10370 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10374 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10373 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10371 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10372 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$10369 $1\logical_op__imm_data__data$next[63:0]$10353 + assign $2\logical_op__imm_data__ok$next[0:0]$10370 $1\logical_op__imm_data__ok$next[0:0]$10354 + assign $2\logical_op__oe__oe$next[0:0]$10371 $1\logical_op__oe__oe$next[0:0]$10362 + assign $2\logical_op__oe__ok$next[0:0]$10372 $1\logical_op__oe__ok$next[0:0]$10363 + assign $2\logical_op__rc__ok$next[0:0]$10373 $1\logical_op__rc__ok$next[0:0]$10365 + assign $2\logical_op__rc__rc$next[0:0]$10374 $1\logical_op__rc__rc$next[0:0]$10366 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10333 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10334 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10335 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10336 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10337 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10338 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10339 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10340 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10341 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10342 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10343 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10344 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10345 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10346 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10347 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10348 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10349 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10350 + end + attribute \src "libresoc.v:175269.3-175281.6" + process $proc$libresoc.v:175269$10375 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$10376 $1\ra$next[63:0]$10377 + attribute \src "libresoc.v:175270.5-175270.29" + switch \initial + attribute \src "libresoc.v:175270.9-175270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$10377 \ra$87 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$10377 \ra$87 + case + assign $1\ra$next[63:0]$10377 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$10376 + end + attribute \src "libresoc.v:175282.3-175294.6" + process $proc$libresoc.v:175282$10378 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$10379 $1\rb$next[63:0]$10380 + attribute \src "libresoc.v:175283.5-175283.29" + switch \initial + attribute \src "libresoc.v:175283.9-175283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$10380 \rb$89 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$10380 \rb$89 + case + assign $1\rb$next[63:0]$10380 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$10379 + end + attribute \src "libresoc.v:175295.3-175307.6" + process $proc$libresoc.v:175295$10381 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$10382 $1\xer_so$next[0:0]$10383 + attribute \src "libresoc.v:175296.5-175296.29" + switch \initial + attribute \src "libresoc.v:175296.9-175296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$10383 \xer_so$91 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$10383 \xer_so$91 + case + assign $1\xer_so$next[0:0]$10383 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$10382 + end + connect \$66 $and$libresoc.v:174923$10269_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:175342.1-175386.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "libresoc.v:175343.7-175343.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175375.3-175384.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:175365.3-175374.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:175375.3-175384.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:175365.3-175374.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:175362.17-175362.105" + wire $eq$libresoc.v:175362$10416_Y + attribute \src "libresoc.v:175363.17-175363.105" + wire $eq$libresoc.v:175363$10417_Y + attribute \src "libresoc.v:175364.17-175364.98" + wire $not$libresoc.v:175364$10418_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:175343.7-175343.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:175362$10416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:175362$10416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:175363$10417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:175363$10417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:175364$10418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk_24_i + connect \Y $not$libresoc.v:175364$10418_Y + end + attribute \src "libresoc.v:175343.7-175343.20" + process $proc$libresoc.v:175343$10421 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175365.3-175374.6" + process $proc$libresoc.v:175365$10419 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:175366.5-175366.29" + switch \initial + attribute \src "libresoc.v:175366.9-175366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end + sync always + update \pll_lck_o $0\pll_lck_o[0:0] + end + attribute \src "libresoc.v:175375.3-175384.6" + process $proc$libresoc.v:175375$10420 + assign { } { } + assign { } { } + assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] + attribute \src "libresoc.v:175376.5-175376.29" + switch \initial + attribute \src "libresoc.v:175376.9-175376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_18_o[0:0] \$5 + case + assign $1\pll_18_o[0:0] 1'0 + end + sync always + update \pll_18_o $0\pll_18_o[0:0] + end + connect \$1 $eq$libresoc.v:175362$10416_Y + connect \$3 $eq$libresoc.v:175363$10417_Y + connect \$5 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parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_2 } + connect \B { 2'00 \pop_2_3 } + connect \Y $add$libresoc.v:175803$10422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175804$10423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_4 } + connect \B { 2'00 \pop_2_5 } + connect \Y $add$libresoc.v:175804$10423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175805$10424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_6 } + connect \B { 2'00 \pop_2_7 } + connect \Y $add$libresoc.v:175805$10424_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add 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parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_28 } + connect \B { 2'00 \pop_2_29 } + connect \Y $add$libresoc.v:175817$10436_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175818$10437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_30 } + connect \B { 2'00 \pop_2_31 } + connect \Y $add$libresoc.v:175818$10437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175819$10438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_0 } + connect \B { 2'00 \pop_3_1 } + connect \Y $add$libresoc.v:175819$10438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175820$10439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [8] } + connect \B { 2'00 \a [9] } + connect \Y $add$libresoc.v:175820$10439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175821$10440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_2 } + connect \B { 2'00 \pop_3_3 } + connect \Y $add$libresoc.v:175821$10440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175822$10441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_4 } + connect \B { 2'00 \pop_3_5 } + connect \Y $add$libresoc.v:175822$10441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175823$10442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_6 } + connect \B { 2'00 \pop_3_7 } + connect \Y $add$libresoc.v:175823$10442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175824$10443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_8 } + connect \B { 2'00 \pop_3_9 } + connect \Y $add$libresoc.v:175824$10443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175825$10444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_10 } + connect \B { 2'00 \pop_3_11 } + connect \Y $add$libresoc.v:175825$10444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175826$10445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_12 } + connect \B { 2'00 \pop_3_13 } + connect \Y $add$libresoc.v:175826$10445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175827$10446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_14 } + connect \B { 2'00 \pop_3_15 } + connect \Y $add$libresoc.v:175827$10446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175828$10447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_0 } + connect \B { 2'00 \pop_4_1 } + connect \Y $add$libresoc.v:175828$10447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175829$10448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_2 } + connect \B { 2'00 \pop_4_3 } + connect \Y $add$libresoc.v:175829$10448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175830$10449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_4 } + connect \B { 2'00 \pop_4_5 } + connect \Y $add$libresoc.v:175830$10449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175831$10450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [10] } + connect \B { 2'00 \a [11] } + connect \Y $add$libresoc.v:175831$10450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175832$10451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$libresoc.v:175832$10451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175833$10452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$libresoc.v:175833$10452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175834$10453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$libresoc.v:175834$10453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175835$10454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$libresoc.v:175835$10454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175846$10473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$libresoc.v:175846$10473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175850$10480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$libresoc.v:175850$10480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175851$10481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$libresoc.v:175851$10481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175852$10482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$libresoc.v:175852$10482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175853$10483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$libresoc.v:175853$10483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175854$10484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$libresoc.v:175854$10484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175855$10485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$libresoc.v:175855$10485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175856$10486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$libresoc.v:175856$10486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175857$10487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$libresoc.v:175857$10487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175858$10488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$libresoc.v:175858$10488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175859$10489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$libresoc.v:175859$10489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175860$10490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$libresoc.v:175860$10490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175861$10491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$libresoc.v:175861$10491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175862$10492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$libresoc.v:175862$10492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175863$10493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$libresoc.v:175863$10493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175864$10494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$libresoc.v:175864$10494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175865$10495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$libresoc.v:175865$10495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175866$10496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$libresoc.v:175866$10496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175867$10497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$libresoc.v:175867$10497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175868$10498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$libresoc.v:175868$10498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175869$10499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$libresoc.v:175869$10499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175870$10500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$libresoc.v:175870$10500_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175871$10501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$libresoc.v:175871$10501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175872$10502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$libresoc.v:175872$10502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175873$10503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$libresoc.v:175873$10503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175874$10504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$libresoc.v:175874$10504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175875$10505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$libresoc.v:175875$10505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175876$10506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$libresoc.v:175876$10506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175877$10507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$libresoc.v:175877$10507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:175878$10508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$libresoc.v:175878$10508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$libresoc.v:175836$10455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:175836$10455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$libresoc.v:175837$10456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:175837$10456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175838$10457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$libresoc.v:175838$10457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175839$10459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$libresoc.v:175839$10459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175840$10461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$libresoc.v:175840$10461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175841$10463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$libresoc.v:175841$10463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175842$10465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$libresoc.v:175842$10465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175843$10467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$libresoc.v:175843$10467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175844$10469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $extend$libresoc.v:175844$10469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175845$10471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$libresoc.v:175845$10471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175847$10474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$libresoc.v:175847$10474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175848$10476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$libresoc.v:175848$10476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:175849$10478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$libresoc.v:175849$10478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175838$10458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175838$10457_Y + connect \Y $pos$libresoc.v:175838$10458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175839$10460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175839$10459_Y + connect \Y $pos$libresoc.v:175839$10460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175840$10462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175840$10461_Y + connect \Y $pos$libresoc.v:175840$10462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175841$10464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175841$10463_Y + connect \Y $pos$libresoc.v:175841$10464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175842$10466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175842$10465_Y + connect \Y $pos$libresoc.v:175842$10466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175843$10468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175843$10467_Y + connect \Y $pos$libresoc.v:175843$10468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175844$10470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175844$10469_Y + connect \Y $pos$libresoc.v:175844$10470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175845$10472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:175845$10471_Y + connect \Y $pos$libresoc.v:175845$10472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175847$10475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:175847$10474_Y + connect \Y $pos$libresoc.v:175847$10475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175848$10477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:175848$10476_Y + connect \Y $pos$libresoc.v:175848$10477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:175849$10479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:175849$10478_Y + connect \Y $pos$libresoc.v:175849$10479_Y + end + attribute \src "libresoc.v:175391.7-175391.20" + process $proc$libresoc.v:175391$10510 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175879.3-175905.6" + process $proc$libresoc.v:175879$10509 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:175880.5-175880.29" + switch \initial + attribute \src "libresoc.v:175880.9-175880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$libresoc.v:175803$10422_Y + connect \$104 $add$libresoc.v:175804$10423_Y + connect \$107 $add$libresoc.v:175805$10424_Y + connect \$110 $add$libresoc.v:175806$10425_Y + connect \$113 $add$libresoc.v:175807$10426_Y + connect \$116 $add$libresoc.v:175808$10427_Y + connect \$11 $add$libresoc.v:175809$10428_Y + connect \$119 $add$libresoc.v:175810$10429_Y + connect \$122 $add$libresoc.v:175811$10430_Y + connect \$125 $add$libresoc.v:175812$10431_Y + connect \$128 $add$libresoc.v:175813$10432_Y + connect \$131 $add$libresoc.v:175814$10433_Y + connect \$134 $add$libresoc.v:175815$10434_Y + connect \$137 $add$libresoc.v:175816$10435_Y + connect \$140 $add$libresoc.v:175817$10436_Y + connect \$143 $add$libresoc.v:175818$10437_Y + connect \$146 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connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] +end +attribute \src "libresoc.v:176036.1-176120.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:176093.17-176093.91" + wire $not$libresoc.v:176093$10511_Y + attribute \src "libresoc.v:176095.18-176095.93" + wire $not$libresoc.v:176095$10513_Y + attribute \src "libresoc.v:176097.18-176097.93" + wire $not$libresoc.v:176097$10515_Y + attribute \src "libresoc.v:176098.17-176098.138" + wire width 8 $not$libresoc.v:176098$10516_Y + attribute \src "libresoc.v:176100.18-176100.93" + wire $not$libresoc.v:176100$10518_Y + attribute \src "libresoc.v:176102.18-176102.93" + wire $not$libresoc.v:176102$10520_Y + attribute \src "libresoc.v:176104.18-176104.93" + wire $not$libresoc.v:176104$10522_Y + attribute \src "libresoc.v:176107.17-176107.91" + wire $not$libresoc.v:176107$10525_Y + attribute \src "libresoc.v:176094.18-176094.116" + wire $reduce_or$libresoc.v:176094$10512_Y + attribute \src "libresoc.v:176096.18-176096.122" + wire $reduce_or$libresoc.v:176096$10514_Y + attribute \src "libresoc.v:176099.18-176099.128" + wire $reduce_or$libresoc.v:176099$10517_Y + attribute \src "libresoc.v:176101.18-176101.134" + wire $reduce_or$libresoc.v:176101$10519_Y + attribute \src "libresoc.v:176103.18-176103.140" + wire $reduce_or$libresoc.v:176103$10521_Y + attribute \src "libresoc.v:176105.18-176105.90" + wire $reduce_or$libresoc.v:176105$10523_Y + attribute \src "libresoc.v:176106.17-176106.103" + wire $reduce_or$libresoc.v:176106$10524_Y + attribute \src "libresoc.v:176108.17-176108.109" + wire $reduce_or$libresoc.v:176108$10526_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176093$10511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176093$10511_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176095$10513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:176095$10513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176097$10515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:176097$10515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176098$10516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:176098$10516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176100$10518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:176100$10518_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176102$10520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:176102$10520_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176104$10522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:176104$10522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176107$10525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176107$10525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176094$10512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:176094$10512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176096$10514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:176096$10514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176099$10517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:176099$10517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176101$10519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:176101$10519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176103$10521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:176103$10521_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176105$10523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176105$10523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176106$10524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:176106$10524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176108$10526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:176108$10526_Y + end + connect \$7 $not$libresoc.v:176093$10511_Y + connect \$12 $reduce_or$libresoc.v:176094$10512_Y + connect \$11 $not$libresoc.v:176095$10513_Y + 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"test_issuer.ti.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$175 + attribute \src "libresoc.v:176181.17-176181.91" + wire $not$libresoc.v:176181$10527_Y + attribute \src "libresoc.v:176183.18-176183.93" + wire $not$libresoc.v:176183$10529_Y + attribute \src "libresoc.v:176185.18-176185.93" + wire $not$libresoc.v:176185$10531_Y + attribute \src "libresoc.v:176186.17-176186.138" + wire width 8 $not$libresoc.v:176186$10532_Y + attribute \src "libresoc.v:176188.18-176188.93" + wire $not$libresoc.v:176188$10534_Y + attribute \src "libresoc.v:176190.18-176190.93" + wire $not$libresoc.v:176190$10536_Y + attribute \src "libresoc.v:176192.18-176192.93" + wire $not$libresoc.v:176192$10538_Y + attribute \src "libresoc.v:176195.17-176195.91" + wire $not$libresoc.v:176195$10541_Y + attribute \src "libresoc.v:176182.18-176182.116" + wire $reduce_or$libresoc.v:176182$10528_Y + attribute \src "libresoc.v:176184.18-176184.122" + wire $reduce_or$libresoc.v:176184$10530_Y + attribute \src "libresoc.v:176187.18-176187.128" + wire $reduce_or$libresoc.v:176187$10533_Y + attribute \src "libresoc.v:176189.18-176189.134" + wire $reduce_or$libresoc.v:176189$10535_Y + attribute \src "libresoc.v:176191.18-176191.140" + wire $reduce_or$libresoc.v:176191$10537_Y + attribute \src "libresoc.v:176193.18-176193.90" + wire $reduce_or$libresoc.v:176193$10539_Y + attribute \src "libresoc.v:176194.17-176194.103" + wire $reduce_or$libresoc.v:176194$10540_Y + attribute \src "libresoc.v:176196.17-176196.109" + wire $reduce_or$libresoc.v:176196$10542_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176181$10527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176181$10527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176183$10529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:176183$10529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176185$10531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:176185$10531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176186$10532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:176186$10532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176188$10534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:176188$10534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176190$10536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:176190$10536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176192$10538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:176192$10538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176195$10541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176195$10541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176182$10528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:176182$10528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176184$10530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:176184$10530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176187$10533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:176187$10533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176189$10535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:176189$10535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176191$10537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:176191$10537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176193$10539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176193$10539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176194$10540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:176194$10540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176196$10542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:176196$10542_Y + end + connect \$7 $not$libresoc.v:176181$10527_Y + connect \$12 $reduce_or$libresoc.v:176182$10528_Y + connect \$11 $not$libresoc.v:176183$10529_Y + connect \$16 $reduce_or$libresoc.v:176184$10530_Y + connect \$15 $not$libresoc.v:176185$10531_Y + connect \$1 $not$libresoc.v:176186$10532_Y + connect \$20 $reduce_or$libresoc.v:176187$10533_Y + connect \$19 $not$libresoc.v:176188$10534_Y + connect \$24 $reduce_or$libresoc.v:176189$10535_Y + connect \$23 $not$libresoc.v:176190$10536_Y + connect \$28 $reduce_or$libresoc.v:176191$10537_Y + connect \$27 $not$libresoc.v:176192$10538_Y + connect \$31 $reduce_or$libresoc.v:176193$10539_Y + connect \$4 $reduce_or$libresoc.v:176194$10540_Y + connect \$3 $not$libresoc.v:176195$10541_Y + connect \$8 $reduce_or$libresoc.v:176196$10542_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:176212.1-176242.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" +attribute \generator "nMigen" +module \rdpick_CR_cr_a + attribute \src "libresoc.v:176233.17-176233.89" + wire width 2 $not$libresoc.v:176233$10543_Y + attribute \src "libresoc.v:176235.17-176235.91" + wire $not$libresoc.v:176235$10545_Y + attribute \src "libresoc.v:176234.17-176234.103" + wire $reduce_or$libresoc.v:176234$10544_Y + attribute \src "libresoc.v:176236.17-176236.89" + wire $reduce_or$libresoc.v:176236$10546_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176233$10543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:176233$10543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176235$10545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176235$10545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176234$10544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176234$10544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176236$10546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176236$10546_Y + end + connect \$1 $not$libresoc.v:176233$10543_Y + connect \$4 $reduce_or$libresoc.v:176234$10544_Y + connect \$3 $not$libresoc.v:176235$10545_Y + connect \$7 $reduce_or$libresoc.v:176236$10546_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176246.1-176267.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" +attribute \generator "nMigen" +module \rdpick_CR_cr_b + attribute \src "libresoc.v:176261.17-176261.89" + wire $not$libresoc.v:176261$10547_Y + attribute \src "libresoc.v:176262.17-176262.89" + wire $reduce_or$libresoc.v:176262$10548_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176261$10547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:176261$10547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176262$10548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176262$10548_Y + end + connect \$1 $not$libresoc.v:176261$10547_Y + connect \$3 $reduce_or$libresoc.v:176262$10548_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:176271.1-176292.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" +attribute \generator "nMigen" +module \rdpick_CR_cr_c + attribute \src "libresoc.v:176286.17-176286.89" + wire $not$libresoc.v:176286$10549_Y + attribute \src "libresoc.v:176287.17-176287.89" + wire $reduce_or$libresoc.v:176287$10550_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176286$10549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:176286$10549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176287$10550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176287$10550_Y + end + connect \$1 $not$libresoc.v:176286$10549_Y + connect \$3 $reduce_or$libresoc.v:176287$10550_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:176296.1-176317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" +attribute \generator "nMigen" +module \rdpick_CR_full_cr + attribute \src "libresoc.v:176311.17-176311.89" + wire $not$libresoc.v:176311$10551_Y + attribute \src "libresoc.v:176312.17-176312.89" + wire $reduce_or$libresoc.v:176312$10552_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176311$10551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:176311$10551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176312$10552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176312$10552_Y + end + connect \$1 $not$libresoc.v:176311$10551_Y + connect \$3 $reduce_or$libresoc.v:176312$10552_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:176321.1-176360.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" +attribute \generator "nMigen" +module \rdpick_FAST_fast1 + attribute \src "libresoc.v:176348.17-176348.91" + wire $not$libresoc.v:176348$10553_Y + attribute \src "libresoc.v:176350.17-176350.89" + wire width 3 $not$libresoc.v:176350$10555_Y + attribute \src "libresoc.v:176352.17-176352.91" + wire $not$libresoc.v:176352$10557_Y + attribute \src "libresoc.v:176349.18-176349.90" + wire $reduce_or$libresoc.v:176349$10554_Y + attribute \src "libresoc.v:176351.17-176351.103" + wire $reduce_or$libresoc.v:176351$10556_Y + attribute \src "libresoc.v:176353.17-176353.105" + wire $reduce_or$libresoc.v:176353$10558_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176348$10553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176348$10553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176350$10555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:176350$10555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176352$10557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176352$10557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176349$10554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176349$10554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176351$10556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176351$10556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176353$10558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:176353$10558_Y + end + connect \$7 $not$libresoc.v:176348$10553_Y + connect \$11 $reduce_or$libresoc.v:176349$10554_Y + connect \$1 $not$libresoc.v:176350$10555_Y + connect \$4 $reduce_or$libresoc.v:176351$10556_Y + connect \$3 $not$libresoc.v:176352$10557_Y + connect \$8 $reduce_or$libresoc.v:176353$10558_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176364.1-176394.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" +attribute \generator "nMigen" +module \rdpick_FAST_fast2 + attribute \src "libresoc.v:176385.17-176385.89" + wire width 2 $not$libresoc.v:176385$10559_Y + attribute \src "libresoc.v:176387.17-176387.91" + wire $not$libresoc.v:176387$10561_Y + attribute \src "libresoc.v:176386.17-176386.103" + wire $reduce_or$libresoc.v:176386$10560_Y + attribute \src "libresoc.v:176388.17-176388.89" + wire $reduce_or$libresoc.v:176388$10562_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176385$10559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:176385$10559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176387$10561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176387$10561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176386$10560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176386$10560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176388$10562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176388$10562_Y + end + connect \$1 $not$libresoc.v:176385$10559_Y + connect \$4 $reduce_or$libresoc.v:176386$10560_Y + connect \$3 $not$libresoc.v:176387$10561_Y + connect \$7 $reduce_or$libresoc.v:176388$10562_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176398.1-176491.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" +attribute \generator "nMigen" +module \rdpick_INT_ra + attribute \src "libresoc.v:176461.17-176461.91" + wire $not$libresoc.v:176461$10563_Y + attribute \src "libresoc.v:176463.18-176463.93" + wire $not$libresoc.v:176463$10565_Y + attribute \src "libresoc.v:176465.18-176465.93" + wire $not$libresoc.v:176465$10567_Y + attribute \src "libresoc.v:176466.17-176466.89" + wire width 9 $not$libresoc.v:176466$10568_Y + attribute \src "libresoc.v:176468.18-176468.93" + wire $not$libresoc.v:176468$10570_Y + attribute \src "libresoc.v:176470.18-176470.93" + wire $not$libresoc.v:176470$10572_Y + attribute \src "libresoc.v:176472.18-176472.93" + wire $not$libresoc.v:176472$10574_Y + attribute \src "libresoc.v:176474.18-176474.93" + wire $not$libresoc.v:176474$10576_Y + attribute \src "libresoc.v:176477.17-176477.91" + wire $not$libresoc.v:176477$10579_Y + attribute \src "libresoc.v:176462.18-176462.106" + wire $reduce_or$libresoc.v:176462$10564_Y + attribute \src "libresoc.v:176464.18-176464.106" + wire $reduce_or$libresoc.v:176464$10566_Y + attribute \src "libresoc.v:176467.18-176467.106" + wire $reduce_or$libresoc.v:176467$10569_Y + attribute \src "libresoc.v:176469.18-176469.106" + wire $reduce_or$libresoc.v:176469$10571_Y + attribute \src "libresoc.v:176471.18-176471.106" + wire $reduce_or$libresoc.v:176471$10573_Y + attribute \src "libresoc.v:176473.18-176473.106" + wire $reduce_or$libresoc.v:176473$10575_Y + attribute \src "libresoc.v:176475.18-176475.90" + wire $reduce_or$libresoc.v:176475$10577_Y + attribute \src "libresoc.v:176476.17-176476.103" + wire $reduce_or$libresoc.v:176476$10578_Y + attribute \src "libresoc.v:176478.17-176478.105" + wire $reduce_or$libresoc.v:176478$10580_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 9 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 9 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176461$10563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176461$10563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176463$10565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:176463$10565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176465$10567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:176465$10567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176466$10568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A \i + connect \Y $not$libresoc.v:176466$10568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176468$10570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:176468$10570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176470$10572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:176470$10572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176472$10574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:176472$10574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176474$10576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:176474$10576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176477$10579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176477$10579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176462$10564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:176462$10564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176464$10566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:176464$10566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176467$10569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:176467$10569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176469$10571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:176469$10571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176471$10573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:176471$10573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176473$10575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:176473$10575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176475$10577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176475$10577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176476$10578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176476$10578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176478$10580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:176478$10580_Y + end + connect \$7 $not$libresoc.v:176461$10563_Y + connect \$12 $reduce_or$libresoc.v:176462$10564_Y + connect \$11 $not$libresoc.v:176463$10565_Y + connect \$16 $reduce_or$libresoc.v:176464$10566_Y + connect \$15 $not$libresoc.v:176465$10567_Y + connect \$1 $not$libresoc.v:176466$10568_Y + connect \$20 $reduce_or$libresoc.v:176467$10569_Y + connect \$19 $not$libresoc.v:176468$10570_Y + connect \$24 $reduce_or$libresoc.v:176469$10571_Y + connect \$23 $not$libresoc.v:176470$10572_Y + connect \$28 $reduce_or$libresoc.v:176471$10573_Y + connect \$27 $not$libresoc.v:176472$10574_Y + connect \$32 $reduce_or$libresoc.v:176473$10575_Y + connect \$31 $not$libresoc.v:176474$10576_Y + connect \$35 $reduce_or$libresoc.v:176475$10577_Y + connect \$4 $reduce_or$libresoc.v:176476$10578_Y + connect \$3 $not$libresoc.v:176477$10579_Y + connect \$8 $reduce_or$libresoc.v:176478$10580_Y + connect \en_o \$35 + connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176495.1-176579.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" +attribute \generator "nMigen" +module \rdpick_INT_rb + attribute \src "libresoc.v:176552.17-176552.91" + wire $not$libresoc.v:176552$10581_Y + attribute \src "libresoc.v:176554.18-176554.93" + wire $not$libresoc.v:176554$10583_Y + attribute \src "libresoc.v:176556.18-176556.93" + wire $not$libresoc.v:176556$10585_Y + attribute \src "libresoc.v:176557.17-176557.89" + wire width 8 $not$libresoc.v:176557$10586_Y + attribute \src "libresoc.v:176559.18-176559.93" + wire $not$libresoc.v:176559$10588_Y + attribute \src "libresoc.v:176561.18-176561.93" + wire $not$libresoc.v:176561$10590_Y + attribute \src "libresoc.v:176563.18-176563.93" + wire $not$libresoc.v:176563$10592_Y + attribute \src "libresoc.v:176566.17-176566.91" + wire $not$libresoc.v:176566$10595_Y + attribute \src "libresoc.v:176553.18-176553.106" + wire $reduce_or$libresoc.v:176553$10582_Y + attribute \src "libresoc.v:176555.18-176555.106" + wire $reduce_or$libresoc.v:176555$10584_Y + attribute \src "libresoc.v:176558.18-176558.106" + wire $reduce_or$libresoc.v:176558$10587_Y + attribute \src "libresoc.v:176560.18-176560.106" + wire $reduce_or$libresoc.v:176560$10589_Y + attribute \src "libresoc.v:176562.18-176562.106" + wire $reduce_or$libresoc.v:176562$10591_Y + attribute \src "libresoc.v:176564.18-176564.90" + wire $reduce_or$libresoc.v:176564$10593_Y + attribute \src "libresoc.v:176565.17-176565.103" + wire $reduce_or$libresoc.v:176565$10594_Y + attribute \src "libresoc.v:176567.17-176567.105" + wire $reduce_or$libresoc.v:176567$10596_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176552$10581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176552$10581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176554$10583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:176554$10583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176556$10585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:176556$10585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176557$10586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \i + connect \Y $not$libresoc.v:176557$10586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176559$10588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:176559$10588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176561$10590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:176561$10590_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176563$10592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:176563$10592_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176566$10595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176566$10595_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176553$10582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:176553$10582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176555$10584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:176555$10584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176558$10587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:176558$10587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176560$10589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:176560$10589_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176562$10591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:176562$10591_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176564$10593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176564$10593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176565$10594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176565$10594_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176567$10596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:176567$10596_Y + end + connect \$7 $not$libresoc.v:176552$10581_Y + connect \$12 $reduce_or$libresoc.v:176553$10582_Y + connect \$11 $not$libresoc.v:176554$10583_Y + connect \$16 $reduce_or$libresoc.v:176555$10584_Y + connect \$15 $not$libresoc.v:176556$10585_Y + connect \$1 $not$libresoc.v:176557$10586_Y + connect \$20 $reduce_or$libresoc.v:176558$10587_Y + connect \$19 $not$libresoc.v:176559$10588_Y + connect \$24 $reduce_or$libresoc.v:176560$10589_Y + connect \$23 $not$libresoc.v:176561$10590_Y + connect \$28 $reduce_or$libresoc.v:176562$10591_Y + connect \$27 $not$libresoc.v:176563$10592_Y + connect \$31 $reduce_or$libresoc.v:176564$10593_Y + connect \$4 $reduce_or$libresoc.v:176565$10594_Y + connect \$3 $not$libresoc.v:176566$10595_Y + connect \$8 $reduce_or$libresoc.v:176567$10596_Y + connect \en_o \$31 + connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176583.1-176613.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" +attribute \generator "nMigen" +module \rdpick_INT_rc + attribute \src "libresoc.v:176604.17-176604.89" + wire width 2 $not$libresoc.v:176604$10597_Y + attribute \src "libresoc.v:176606.17-176606.91" + wire $not$libresoc.v:176606$10599_Y + attribute \src "libresoc.v:176605.17-176605.103" + wire $reduce_or$libresoc.v:176605$10598_Y + attribute \src "libresoc.v:176607.17-176607.89" + wire $reduce_or$libresoc.v:176607$10600_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176604$10597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:176604$10597_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176606$10599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176606$10599_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176605$10598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176605$10598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176607$10600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176607$10600_Y + end + connect \$1 $not$libresoc.v:176604$10597_Y + connect \$4 $reduce_or$libresoc.v:176605$10598_Y + connect \$3 $not$libresoc.v:176606$10599_Y + connect \$7 $reduce_or$libresoc.v:176607$10600_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176617.1-176638.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" +attribute \generator "nMigen" +module \rdpick_SPR_spr1 + attribute \src "libresoc.v:176632.17-176632.89" + wire $not$libresoc.v:176632$10601_Y + attribute \src "libresoc.v:176633.17-176633.89" + wire $reduce_or$libresoc.v:176633$10602_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176632$10601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:176632$10601_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176633$10602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176633$10602_Y + end + connect \$1 $not$libresoc.v:176632$10601_Y + connect \$3 $reduce_or$libresoc.v:176633$10602_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:176642.1-176681.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" +attribute \generator "nMigen" +module \rdpick_XER_xer_ca + attribute \src "libresoc.v:176669.17-176669.91" + wire $not$libresoc.v:176669$10603_Y + attribute \src "libresoc.v:176671.17-176671.89" + wire width 3 $not$libresoc.v:176671$10605_Y + attribute \src "libresoc.v:176673.17-176673.91" + wire $not$libresoc.v:176673$10607_Y + attribute \src "libresoc.v:176670.18-176670.90" + wire $reduce_or$libresoc.v:176670$10604_Y + attribute \src "libresoc.v:176672.17-176672.103" + wire $reduce_or$libresoc.v:176672$10606_Y + attribute \src "libresoc.v:176674.17-176674.105" + wire $reduce_or$libresoc.v:176674$10608_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176669$10603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176669$10603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176671$10605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:176671$10605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176673$10607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176673$10607_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176670$10604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176670$10604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176672$10606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176672$10606_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176674$10608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:176674$10608_Y + end + connect \$7 $not$libresoc.v:176669$10603_Y + connect \$11 $reduce_or$libresoc.v:176670$10604_Y + connect \$1 $not$libresoc.v:176671$10605_Y + connect \$4 $reduce_or$libresoc.v:176672$10606_Y + connect \$3 $not$libresoc.v:176673$10607_Y + connect \$8 $reduce_or$libresoc.v:176674$10608_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176685.1-176706.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" +attribute \generator "nMigen" +module \rdpick_XER_xer_ov + attribute \src "libresoc.v:176700.17-176700.89" + wire $not$libresoc.v:176700$10609_Y + attribute \src "libresoc.v:176701.17-176701.89" + wire $reduce_or$libresoc.v:176701$10610_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176700$10609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:176700$10609_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176701$10610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176701$10610_Y + end + connect \$1 $not$libresoc.v:176700$10609_Y + connect \$3 $reduce_or$libresoc.v:176701$10610_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:176710.1-176776.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" +attribute \generator "nMigen" +module \rdpick_XER_xer_so + attribute \src "libresoc.v:176755.17-176755.91" + wire $not$libresoc.v:176755$10611_Y + attribute \src "libresoc.v:176757.18-176757.93" + wire $not$libresoc.v:176757$10613_Y + attribute \src "libresoc.v:176759.18-176759.93" + wire $not$libresoc.v:176759$10615_Y + attribute \src "libresoc.v:176760.17-176760.89" + wire width 6 $not$libresoc.v:176760$10616_Y + attribute \src "libresoc.v:176762.18-176762.93" + wire $not$libresoc.v:176762$10618_Y + attribute \src "libresoc.v:176765.17-176765.91" + wire $not$libresoc.v:176765$10621_Y + attribute \src "libresoc.v:176756.18-176756.106" + wire $reduce_or$libresoc.v:176756$10612_Y + attribute \src "libresoc.v:176758.18-176758.106" + wire $reduce_or$libresoc.v:176758$10614_Y + attribute \src "libresoc.v:176761.18-176761.106" + wire $reduce_or$libresoc.v:176761$10617_Y + attribute \src "libresoc.v:176763.18-176763.90" + wire $reduce_or$libresoc.v:176763$10619_Y + attribute \src "libresoc.v:176764.17-176764.103" + wire $reduce_or$libresoc.v:176764$10620_Y + attribute \src "libresoc.v:176766.17-176766.105" + wire $reduce_or$libresoc.v:176766$10622_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176755$10611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:176755$10611_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176757$10613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:176757$10613_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176759$10615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:176759$10615_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:176760$10616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:176760$10616_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176762$10618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:176762$10618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:176765$10621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:176765$10621_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176756$10612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:176756$10612_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176758$10614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:176758$10614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176761$10617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:176761$10617_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:176763$10619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:176763$10619_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176764$10620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:176764$10620_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:176766$10622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:176766$10622_Y + end + connect \$7 $not$libresoc.v:176755$10611_Y + connect \$12 $reduce_or$libresoc.v:176756$10612_Y + connect \$11 $not$libresoc.v:176757$10613_Y + connect \$16 $reduce_or$libresoc.v:176758$10614_Y + connect \$15 $not$libresoc.v:176759$10615_Y + connect \$1 $not$libresoc.v:176760$10616_Y + connect \$20 $reduce_or$libresoc.v:176761$10617_Y + connect \$19 $not$libresoc.v:176762$10618_Y + connect \$23 $reduce_or$libresoc.v:176763$10619_Y + connect \$4 $reduce_or$libresoc.v:176764$10620_Y + connect \$3 $not$libresoc.v:176765$10621_Y + connect \$8 $reduce_or$libresoc.v:176766$10622_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:176780.1-177335.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" +attribute \generator "nMigen" +module \reg_0 + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $0\cr_pred0__data_o$next[3:0]$10637 + attribute \src "libresoc.v:176886.3-176887.49" + wire width 4 $0\cr_pred0__data_o[3:0] + attribute \src "libresoc.v:176781.7-176781.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $0\r0__data_o$next[3:0]$10708 + attribute \src "libresoc.v:176878.3-176879.37" + wire width 4 $0\r0__data_o[3:0] + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $0\r20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:176876.3-176877.39" + wire width 4 $0\r20__data_o[3:0] + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $0\reg$next[3:0]$10660 + attribute \src "libresoc.v:176874.3-176875.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $0\src10__data_o$next[3:0]$10666 + attribute \src "libresoc.v:176884.3-176885.43" + wire width 4 $0\src10__data_o[3:0] + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $0\src20__data_o$next[3:0]$10680 + attribute \src "libresoc.v:176882.3-176883.43" + wire width 4 $0\src20__data_o[3:0] + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $0\src30__data_o$next[3:0]$10694 + attribute \src "libresoc.v:176880.3-176881.43" + wire width 4 $0\src30__data_o[3:0] + attribute \src "libresoc.v:177235.3-177264.6" + wire $0\wr_detect$10[0:0]$10702 + attribute \src "libresoc.v:177305.3-177334.6" + wire $0\wr_detect$13[0:0]$10716 + attribute \src "libresoc.v:176998.3-177027.6" + wire $0\wr_detect$16[0:0]$10654 + attribute \src "libresoc.v:177095.3-177124.6" + wire $0\wr_detect$4[0:0]$10674 + attribute \src "libresoc.v:177165.3-177194.6" + wire $0\wr_detect$7[0:0]$10688 + attribute \src "libresoc.v:176928.3-176957.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $1\cr_pred0__data_o$next[3:0]$10638 + attribute \src "libresoc.v:176800.13-176800.36" + wire width 4 $1\cr_pred0__data_o[3:0] + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $1\r0__data_o$next[3:0]$10709 + attribute \src "libresoc.v:176815.13-176815.30" + wire width 4 $1\r0__data_o[3:0] + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $1\r20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:176822.13-176822.31" + wire width 4 $1\r20__data_o[3:0] + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $1\reg$next[3:0]$10661 + attribute \src "libresoc.v:176828.13-176828.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $1\src10__data_o$next[3:0]$10667 + attribute \src "libresoc.v:176833.13-176833.33" + wire width 4 $1\src10__data_o[3:0] + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $1\src20__data_o$next[3:0]$10681 + attribute \src "libresoc.v:176840.13-176840.33" + wire width 4 $1\src20__data_o[3:0] + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $1\src30__data_o$next[3:0]$10695 + attribute \src "libresoc.v:176847.13-176847.33" + wire width 4 $1\src30__data_o[3:0] + attribute \src "libresoc.v:177235.3-177264.6" + wire $1\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:177305.3-177334.6" + wire $1\wr_detect$13[0:0]$10717 + attribute \src "libresoc.v:176998.3-177027.6" + wire $1\wr_detect$16[0:0]$10655 + attribute \src "libresoc.v:177095.3-177124.6" + wire $1\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:177165.3-177194.6" + wire $1\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:176928.3-176957.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $2\cr_pred0__data_o$next[3:0]$10639 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $2\r0__data_o$next[3:0]$10710 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $2\r20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $2\reg$next[3:0]$10662 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $2\src10__data_o$next[3:0]$10668 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $2\src20__data_o$next[3:0]$10682 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $2\src30__data_o$next[3:0]$10696 + attribute \src "libresoc.v:177235.3-177264.6" + wire $2\wr_detect$10[0:0]$10704 + attribute \src "libresoc.v:177305.3-177334.6" + wire $2\wr_detect$13[0:0]$10718 + attribute \src "libresoc.v:176998.3-177027.6" + wire $2\wr_detect$16[0:0]$10656 + attribute \src "libresoc.v:177095.3-177124.6" + wire $2\wr_detect$4[0:0]$10676 + attribute \src "libresoc.v:177165.3-177194.6" + wire $2\wr_detect$7[0:0]$10690 + attribute \src "libresoc.v:176928.3-176957.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $3\cr_pred0__data_o$next[3:0]$10640 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $3\r0__data_o$next[3:0]$10711 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $3\r20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $3\reg$next[3:0]$10663 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $3\src10__data_o$next[3:0]$10669 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $3\src20__data_o$next[3:0]$10683 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $3\src30__data_o$next[3:0]$10697 + attribute \src "libresoc.v:177235.3-177264.6" + wire $3\wr_detect$10[0:0]$10705 + attribute \src "libresoc.v:177305.3-177334.6" + wire $3\wr_detect$13[0:0]$10719 + attribute \src "libresoc.v:176998.3-177027.6" + wire $3\wr_detect$16[0:0]$10657 + attribute \src "libresoc.v:177095.3-177124.6" + wire $3\wr_detect$4[0:0]$10677 + attribute \src "libresoc.v:177165.3-177194.6" + wire $3\wr_detect$7[0:0]$10691 + attribute \src "libresoc.v:176928.3-176957.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $4\cr_pred0__data_o$next[3:0]$10641 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $4\r0__data_o$next[3:0]$10712 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $4\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $4\reg$next[3:0]$10664 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $4\src10__data_o$next[3:0]$10670 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $4\src20__data_o$next[3:0]$10684 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $4\src30__data_o$next[3:0]$10698 + attribute \src "libresoc.v:177235.3-177264.6" + wire $4\wr_detect$10[0:0]$10706 + attribute \src "libresoc.v:177305.3-177334.6" + wire $4\wr_detect$13[0:0]$10720 + attribute \src "libresoc.v:176998.3-177027.6" + wire $4\wr_detect$16[0:0]$10658 + attribute \src "libresoc.v:177095.3-177124.6" + wire $4\wr_detect$4[0:0]$10678 + attribute \src "libresoc.v:177165.3-177194.6" + wire $4\wr_detect$7[0:0]$10692 + attribute \src "libresoc.v:176928.3-176957.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $5\cr_pred0__data_o$next[3:0]$10642 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $5\r0__data_o$next[3:0]$10713 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $5\r20__data_o$next[3:0]$10651 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $5\src10__data_o$next[3:0]$10671 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $5\src20__data_o$next[3:0]$10685 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $5\src30__data_o$next[3:0]$10699 + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $6\cr_pred0__data_o$next[3:0]$10643 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $6\r0__data_o$next[3:0]$10714 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $6\r20__data_o$next[3:0]$10652 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $6\src10__data_o$next[3:0]$10672 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $6\src20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $6\src30__data_o$next[3:0]$10700 + attribute \src "libresoc.v:176868.17-176868.104" + wire $not$libresoc.v:176868$10623_Y + attribute \src "libresoc.v:176869.18-176869.105" + wire $not$libresoc.v:176869$10624_Y + attribute \src "libresoc.v:176870.18-176870.105" + wire $not$libresoc.v:176870$10625_Y + attribute \src "libresoc.v:176871.17-176871.100" + wire $not$libresoc.v:176871$10626_Y + attribute \src "libresoc.v:176872.17-176872.103" + wire $not$libresoc.v:176872$10627_Y + attribute \src "libresoc.v:176873.17-176873.103" + wire $not$libresoc.v:176873$10628_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest20__wen + attribute \src "libresoc.v:176781.7-176781.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176868$10623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:176868$10623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176869$10624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:176869$10624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176870$10625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:176870$10625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176871$10626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:176871$10626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176872$10627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:176872$10627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176873$10628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:176873$10628_Y + end + attribute \src "libresoc.v:176781.7-176781.20" + process $proc$libresoc.v:176781$10721 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:176800.13-176800.36" + process $proc$libresoc.v:176800$10722 + assign { } { } + assign $1\cr_pred0__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred0__data_o $1\cr_pred0__data_o[3:0] + end + attribute \src "libresoc.v:176815.13-176815.30" + process $proc$libresoc.v:176815$10723 + assign { } { } + assign $1\r0__data_o[3:0] 4'0000 + sync always + sync init + update \r0__data_o $1\r0__data_o[3:0] + end + attribute \src "libresoc.v:176822.13-176822.31" + process $proc$libresoc.v:176822$10724 + assign { } { } + assign $1\r20__data_o[3:0] 4'0000 + sync always + sync init + update \r20__data_o $1\r20__data_o[3:0] + end + attribute \src "libresoc.v:176828.13-176828.25" + process $proc$libresoc.v:176828$10725 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:176833.13-176833.33" + process $proc$libresoc.v:176833$10726 + assign { } { } + assign $1\src10__data_o[3:0] 4'0000 + sync always + sync init + update \src10__data_o $1\src10__data_o[3:0] + end + attribute \src "libresoc.v:176840.13-176840.33" + process $proc$libresoc.v:176840$10727 + assign { } { } + assign $1\src20__data_o[3:0] 4'0000 + sync always + sync init + update \src20__data_o $1\src20__data_o[3:0] + end + attribute \src "libresoc.v:176847.13-176847.33" + process $proc$libresoc.v:176847$10728 + assign { } { } + assign $1\src30__data_o[3:0] 4'0000 + sync always + sync init + update \src30__data_o $1\src30__data_o[3:0] + end + attribute \src "libresoc.v:176874.3-176875.25" + process $proc$libresoc.v:176874$10629 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:176876.3-176877.39" + process $proc$libresoc.v:176876$10630 + assign { } { } + assign $0\r20__data_o[3:0] \r20__data_o$next + sync posedge \coresync_clk + update \r20__data_o $0\r20__data_o[3:0] + end + attribute \src "libresoc.v:176878.3-176879.37" + process $proc$libresoc.v:176878$10631 + assign { } { } + assign $0\r0__data_o[3:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[3:0] + end + attribute \src "libresoc.v:176880.3-176881.43" + process $proc$libresoc.v:176880$10632 + assign { } { } + assign $0\src30__data_o[3:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[3:0] + end + attribute \src "libresoc.v:176882.3-176883.43" + process $proc$libresoc.v:176882$10633 + assign { } { } + assign $0\src20__data_o[3:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[3:0] + end + attribute \src "libresoc.v:176884.3-176885.43" + process $proc$libresoc.v:176884$10634 + assign { } { } + assign $0\src10__data_o[3:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[3:0] + end + attribute \src "libresoc.v:176886.3-176887.49" + process $proc$libresoc.v:176886$10635 + assign { } { } + assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next + sync posedge \coresync_clk + update \cr_pred0__data_o $0\cr_pred0__data_o[3:0] + end + attribute \src "libresoc.v:176888.3-176927.6" + process $proc$libresoc.v:176888$10636 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred0__data_o$next[3:0]$10637 $6\cr_pred0__data_o$next[3:0]$10643 + attribute \src "libresoc.v:176889.5-176889.29" + switch \initial + attribute \src "libresoc.v:176889.9-176889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred0__data_o$next[3:0]$10638 $5\cr_pred0__data_o$next[3:0]$10642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred0__data_o$next[3:0]$10639 \dest10__data_i + case + assign $2\cr_pred0__data_o$next[3:0]$10639 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred0__data_o$next[3:0]$10640 \dest20__data_i + case + assign $3\cr_pred0__data_o$next[3:0]$10640 $2\cr_pred0__data_o$next[3:0]$10639 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred0__data_o$next[3:0]$10641 \w0__data_i + case + assign $4\cr_pred0__data_o$next[3:0]$10641 $3\cr_pred0__data_o$next[3:0]$10640 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred0__data_o$next[3:0]$10642 \reg + case + assign $5\cr_pred0__data_o$next[3:0]$10642 $4\cr_pred0__data_o$next[3:0]$10641 + end + case + assign $1\cr_pred0__data_o$next[3:0]$10638 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred0__data_o$next[3:0]$10643 4'0000 + case + assign $6\cr_pred0__data_o$next[3:0]$10643 $1\cr_pred0__data_o$next[3:0]$10638 + end + sync always + update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10637 + end + attribute \src "libresoc.v:176928.3-176957.6" + process $proc$libresoc.v:176928$10644 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:176929.5-176929.29" + switch \initial + attribute \src "libresoc.v:176929.9-176929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:176958.3-176997.6" + process $proc$libresoc.v:176958$10645 + assign { } { } + assign { } { } + assign { } { } + assign $0\r20__data_o$next[3:0]$10646 $6\r20__data_o$next[3:0]$10652 + attribute \src "libresoc.v:176959.5-176959.29" + switch \initial + attribute \src "libresoc.v:176959.9-176959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r20__data_o$next[3:0]$10647 $5\r20__data_o$next[3:0]$10651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$10648 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$10648 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$10649 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$10649 $2\r20__data_o$next[3:0]$10648 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$10650 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$10650 $3\r20__data_o$next[3:0]$10649 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$10651 \reg + case + assign $5\r20__data_o$next[3:0]$10651 $4\r20__data_o$next[3:0]$10650 + end + case + assign $1\r20__data_o$next[3:0]$10647 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r20__data_o$next[3:0]$10652 4'0000 + case + assign $6\r20__data_o$next[3:0]$10652 $1\r20__data_o$next[3:0]$10647 + end + sync always + update \r20__data_o$next $0\r20__data_o$next[3:0]$10646 + end + attribute \src "libresoc.v:176998.3-177027.6" + process $proc$libresoc.v:176998$10653 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$10654 $1\wr_detect$16[0:0]$10655 + attribute \src "libresoc.v:176999.5-176999.29" + switch \initial + attribute \src "libresoc.v:176999.9-176999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$10655 $4\wr_detect$16[0:0]$10658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$10656 1'1 + case + assign $2\wr_detect$16[0:0]$10656 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$10657 1'1 + case + assign $3\wr_detect$16[0:0]$10657 $2\wr_detect$16[0:0]$10656 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$10658 1'1 + case + assign $4\wr_detect$16[0:0]$10658 $3\wr_detect$16[0:0]$10657 + end + case + assign $1\wr_detect$16[0:0]$10655 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$10654 + end + attribute \src "libresoc.v:177028.3-177054.6" + process $proc$libresoc.v:177028$10659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10660 $4\reg$next[3:0]$10664 + attribute \src "libresoc.v:177029.5-177029.29" + switch \initial + attribute \src "libresoc.v:177029.9-177029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10661 \dest10__data_i + case + assign $1\reg$next[3:0]$10661 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10662 \dest20__data_i + case + assign $2\reg$next[3:0]$10662 $1\reg$next[3:0]$10661 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10663 \w0__data_i + case + assign $3\reg$next[3:0]$10663 $2\reg$next[3:0]$10662 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10664 4'0000 + case + assign $4\reg$next[3:0]$10664 $3\reg$next[3:0]$10663 + end + sync always + update \reg$next $0\reg$next[3:0]$10660 + end + attribute \src "libresoc.v:177055.3-177094.6" + process $proc$libresoc.v:177055$10665 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$10666 $6\src10__data_o$next[3:0]$10672 + attribute \src "libresoc.v:177056.5-177056.29" + switch \initial + attribute \src "libresoc.v:177056.9-177056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$10667 $5\src10__data_o$next[3:0]$10671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$10668 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$10668 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$10669 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$10669 $2\src10__data_o$next[3:0]$10668 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$10670 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$10670 $3\src10__data_o$next[3:0]$10669 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[3:0]$10671 \reg + case + assign $5\src10__data_o$next[3:0]$10671 $4\src10__data_o$next[3:0]$10670 + end + case + assign $1\src10__data_o$next[3:0]$10667 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[3:0]$10672 4'0000 + case + assign $6\src10__data_o$next[3:0]$10672 $1\src10__data_o$next[3:0]$10667 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[3:0]$10666 + end + attribute \src "libresoc.v:177095.3-177124.6" + process $proc$libresoc.v:177095$10673 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10674 $1\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:177096.5-177096.29" + switch \initial + attribute \src "libresoc.v:177096.9-177096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10675 $4\wr_detect$4[0:0]$10678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10676 1'1 + case + assign $2\wr_detect$4[0:0]$10676 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10677 1'1 + case + assign $3\wr_detect$4[0:0]$10677 $2\wr_detect$4[0:0]$10676 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10678 1'1 + case + assign $4\wr_detect$4[0:0]$10678 $3\wr_detect$4[0:0]$10677 + end + case + assign $1\wr_detect$4[0:0]$10675 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10674 + end + attribute \src "libresoc.v:177125.3-177164.6" + process $proc$libresoc.v:177125$10679 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[3:0]$10680 $6\src20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:177126.5-177126.29" + switch \initial + attribute \src "libresoc.v:177126.9-177126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[3:0]$10681 $5\src20__data_o$next[3:0]$10685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[3:0]$10682 \dest10__data_i + case + assign $2\src20__data_o$next[3:0]$10682 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[3:0]$10683 \dest20__data_i + case + assign $3\src20__data_o$next[3:0]$10683 $2\src20__data_o$next[3:0]$10682 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[3:0]$10684 \w0__data_i + case + assign $4\src20__data_o$next[3:0]$10684 $3\src20__data_o$next[3:0]$10683 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[3:0]$10685 \reg + case + assign $5\src20__data_o$next[3:0]$10685 $4\src20__data_o$next[3:0]$10684 + end + case + assign $1\src20__data_o$next[3:0]$10681 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[3:0]$10686 4'0000 + case + assign $6\src20__data_o$next[3:0]$10686 $1\src20__data_o$next[3:0]$10681 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[3:0]$10680 + end + attribute \src "libresoc.v:177165.3-177194.6" + process $proc$libresoc.v:177165$10687 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10688 $1\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:177166.5-177166.29" + switch \initial + attribute \src "libresoc.v:177166.9-177166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10689 $4\wr_detect$7[0:0]$10692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10690 1'1 + case + assign $2\wr_detect$7[0:0]$10690 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10691 1'1 + case + assign $3\wr_detect$7[0:0]$10691 $2\wr_detect$7[0:0]$10690 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10692 1'1 + case + assign $4\wr_detect$7[0:0]$10692 $3\wr_detect$7[0:0]$10691 + end + case + assign $1\wr_detect$7[0:0]$10689 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10688 + end + attribute \src "libresoc.v:177195.3-177234.6" + process $proc$libresoc.v:177195$10693 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[3:0]$10694 $6\src30__data_o$next[3:0]$10700 + attribute \src "libresoc.v:177196.5-177196.29" + switch \initial + attribute \src "libresoc.v:177196.9-177196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[3:0]$10695 $5\src30__data_o$next[3:0]$10699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[3:0]$10696 \dest10__data_i + case + assign $2\src30__data_o$next[3:0]$10696 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[3:0]$10697 \dest20__data_i + case + assign $3\src30__data_o$next[3:0]$10697 $2\src30__data_o$next[3:0]$10696 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[3:0]$10698 \w0__data_i + case + assign $4\src30__data_o$next[3:0]$10698 $3\src30__data_o$next[3:0]$10697 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[3:0]$10699 \reg + case + assign $5\src30__data_o$next[3:0]$10699 $4\src30__data_o$next[3:0]$10698 + end + case + assign $1\src30__data_o$next[3:0]$10695 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[3:0]$10700 4'0000 + case + assign $6\src30__data_o$next[3:0]$10700 $1\src30__data_o$next[3:0]$10695 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[3:0]$10694 + end + attribute \src "libresoc.v:177235.3-177264.6" + process $proc$libresoc.v:177235$10701 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10702 $1\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:177236.5-177236.29" + switch \initial + attribute \src "libresoc.v:177236.9-177236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10703 $4\wr_detect$10[0:0]$10706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10704 1'1 + case + assign $2\wr_detect$10[0:0]$10704 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10705 1'1 + case + assign $3\wr_detect$10[0:0]$10705 $2\wr_detect$10[0:0]$10704 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10706 1'1 + case + assign $4\wr_detect$10[0:0]$10706 $3\wr_detect$10[0:0]$10705 + end + case + assign $1\wr_detect$10[0:0]$10703 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10702 + end + attribute \src "libresoc.v:177265.3-177304.6" + process $proc$libresoc.v:177265$10707 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[3:0]$10708 $6\r0__data_o$next[3:0]$10714 + attribute \src "libresoc.v:177266.5-177266.29" + switch \initial + attribute \src "libresoc.v:177266.9-177266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[3:0]$10709 $5\r0__data_o$next[3:0]$10713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[3:0]$10710 \dest10__data_i + case + assign $2\r0__data_o$next[3:0]$10710 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[3:0]$10711 \dest20__data_i + case + assign $3\r0__data_o$next[3:0]$10711 $2\r0__data_o$next[3:0]$10710 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[3:0]$10712 \w0__data_i + case + assign $4\r0__data_o$next[3:0]$10712 $3\r0__data_o$next[3:0]$10711 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[3:0]$10713 \reg + case + assign $5\r0__data_o$next[3:0]$10713 $4\r0__data_o$next[3:0]$10712 + end + case + assign $1\r0__data_o$next[3:0]$10709 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[3:0]$10714 4'0000 + case + assign $6\r0__data_o$next[3:0]$10714 $1\r0__data_o$next[3:0]$10709 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[3:0]$10708 + end + attribute \src "libresoc.v:177305.3-177334.6" + process $proc$libresoc.v:177305$10715 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10716 $1\wr_detect$13[0:0]$10717 + attribute \src "libresoc.v:177306.5-177306.29" + switch \initial + attribute \src "libresoc.v:177306.9-177306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10717 $4\wr_detect$13[0:0]$10720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10718 1'1 + case + assign $2\wr_detect$13[0:0]$10718 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10719 1'1 + case + assign $3\wr_detect$13[0:0]$10719 $2\wr_detect$13[0:0]$10718 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10720 1'1 + case + assign $4\wr_detect$13[0:0]$10720 $3\wr_detect$13[0:0]$10719 + end + case + assign $1\wr_detect$13[0:0]$10717 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10716 + end + connect \$9 $not$libresoc.v:176868$10623_Y + connect \$12 $not$libresoc.v:176869$10624_Y + connect \$15 $not$libresoc.v:176870$10625_Y + connect \$1 $not$libresoc.v:176871$10626_Y + connect \$3 $not$libresoc.v:176872$10627_Y + connect \$6 $not$libresoc.v:176873$10628_Y +end +attribute \src "libresoc.v:177339.1-177784.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" +attribute \generator "nMigen" +module \reg_0$132 + attribute \src "libresoc.v:177340.7-177340.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $0\r0__data_o$next[1:0]$10781 + attribute \src "libresoc.v:177415.3-177416.37" + wire width 2 $0\r0__data_o[1:0] + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $0\reg$next[1:0]$10797 + attribute \src "libresoc.v:177413.3-177414.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $0\src10__data_o$next[1:0]$10739 + attribute \src "libresoc.v:177421.3-177422.43" + wire width 2 $0\src10__data_o[1:0] + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $0\src20__data_o$next[1:0]$10749 + attribute \src "libresoc.v:177419.3-177420.43" + wire width 2 $0\src20__data_o[1:0] + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $0\src30__data_o$next[1:0]$10765 + attribute \src "libresoc.v:177417.3-177418.43" + wire width 2 $0\src30__data_o[1:0] + attribute \src "libresoc.v:177715.3-177750.6" + wire $0\wr_detect$10[0:0]$10790 + attribute \src "libresoc.v:177551.3-177586.6" + wire $0\wr_detect$4[0:0]$10758 + attribute \src "libresoc.v:177633.3-177668.6" + wire $0\wr_detect$7[0:0]$10774 + attribute \src "libresoc.v:177469.3-177504.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $1\r0__data_o$next[1:0]$10782 + attribute \src "libresoc.v:177367.13-177367.30" + wire width 2 $1\r0__data_o[1:0] + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $1\reg$next[1:0]$10798 + attribute \src "libresoc.v:177373.13-177373.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $1\src10__data_o$next[1:0]$10740 + attribute \src "libresoc.v:177378.13-177378.33" + wire width 2 $1\src10__data_o[1:0] + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $1\src20__data_o$next[1:0]$10750 + attribute \src "libresoc.v:177385.13-177385.33" + wire width 2 $1\src20__data_o[1:0] + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $1\src30__data_o$next[1:0]$10766 + attribute \src "libresoc.v:177392.13-177392.33" + wire width 2 $1\src30__data_o[1:0] + attribute \src "libresoc.v:177715.3-177750.6" + wire $1\wr_detect$10[0:0]$10791 + attribute \src "libresoc.v:177551.3-177586.6" + wire $1\wr_detect$4[0:0]$10759 + attribute \src "libresoc.v:177633.3-177668.6" + wire $1\wr_detect$7[0:0]$10775 + attribute \src "libresoc.v:177469.3-177504.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $2\r0__data_o$next[1:0]$10783 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $2\reg$next[1:0]$10799 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $2\src10__data_o$next[1:0]$10741 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $2\src20__data_o$next[1:0]$10751 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $2\src30__data_o$next[1:0]$10767 + attribute \src "libresoc.v:177715.3-177750.6" + wire $2\wr_detect$10[0:0]$10792 + attribute \src "libresoc.v:177551.3-177586.6" + wire $2\wr_detect$4[0:0]$10760 + attribute \src "libresoc.v:177633.3-177668.6" + wire $2\wr_detect$7[0:0]$10776 + attribute \src "libresoc.v:177469.3-177504.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $3\r0__data_o$next[1:0]$10784 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $3\reg$next[1:0]$10800 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $3\src10__data_o$next[1:0]$10742 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $3\src20__data_o$next[1:0]$10752 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $3\src30__data_o$next[1:0]$10768 + attribute \src "libresoc.v:177715.3-177750.6" + wire $3\wr_detect$10[0:0]$10793 + attribute \src "libresoc.v:177551.3-177586.6" + wire $3\wr_detect$4[0:0]$10761 + attribute \src "libresoc.v:177633.3-177668.6" + wire $3\wr_detect$7[0:0]$10777 + attribute \src "libresoc.v:177469.3-177504.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $4\r0__data_o$next[1:0]$10785 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $4\reg$next[1:0]$10801 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $4\src10__data_o$next[1:0]$10743 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $4\src20__data_o$next[1:0]$10753 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $4\src30__data_o$next[1:0]$10769 + attribute \src "libresoc.v:177715.3-177750.6" + wire $4\wr_detect$10[0:0]$10794 + attribute \src "libresoc.v:177551.3-177586.6" + wire $4\wr_detect$4[0:0]$10762 + attribute \src "libresoc.v:177633.3-177668.6" + wire $4\wr_detect$7[0:0]$10778 + attribute \src "libresoc.v:177469.3-177504.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $5\r0__data_o$next[1:0]$10786 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $5\reg$next[1:0]$10802 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $5\src10__data_o$next[1:0]$10744 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $5\src20__data_o$next[1:0]$10754 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $5\src30__data_o$next[1:0]$10770 + attribute \src "libresoc.v:177715.3-177750.6" + wire $5\wr_detect$10[0:0]$10795 + attribute \src "libresoc.v:177551.3-177586.6" + wire $5\wr_detect$4[0:0]$10763 + attribute \src "libresoc.v:177633.3-177668.6" + wire $5\wr_detect$7[0:0]$10779 + attribute \src "libresoc.v:177469.3-177504.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $6\r0__data_o$next[1:0]$10787 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $6\src10__data_o$next[1:0]$10745 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $6\src20__data_o$next[1:0]$10755 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $6\src30__data_o$next[1:0]$10771 + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $7\r0__data_o$next[1:0]$10788 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $7\src10__data_o$next[1:0]$10746 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $7\src20__data_o$next[1:0]$10756 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $7\src30__data_o$next[1:0]$10772 + attribute \src "libresoc.v:177409.17-177409.104" + wire $not$libresoc.v:177409$10729_Y + attribute \src "libresoc.v:177410.17-177410.100" + wire $not$libresoc.v:177410$10730_Y + attribute \src "libresoc.v:177411.17-177411.103" + wire $not$libresoc.v:177411$10731_Y + attribute \src "libresoc.v:177412.17-177412.103" + wire $not$libresoc.v:177412$10732_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 13 \dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest30__wen + attribute \src "libresoc.v:177340.7-177340.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177409$10729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:177409$10729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177410$10730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:177410$10730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177411$10731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:177411$10731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177412$10732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:177412$10732_Y + end + attribute \src "libresoc.v:177340.7-177340.20" + process $proc$libresoc.v:177340$10803 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177367.13-177367.30" + process $proc$libresoc.v:177367$10804 + assign { } { } + assign $1\r0__data_o[1:0] 2'00 + sync always + sync init + update \r0__data_o $1\r0__data_o[1:0] + end + attribute \src "libresoc.v:177373.13-177373.25" + process $proc$libresoc.v:177373$10805 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:177378.13-177378.33" + process $proc$libresoc.v:177378$10806 + assign { } { } + assign $1\src10__data_o[1:0] 2'00 + sync always + sync init + update \src10__data_o $1\src10__data_o[1:0] + end + attribute \src "libresoc.v:177385.13-177385.33" + process $proc$libresoc.v:177385$10807 + assign { } { } + assign $1\src20__data_o[1:0] 2'00 + sync always + sync init + update \src20__data_o $1\src20__data_o[1:0] + end + attribute \src "libresoc.v:177392.13-177392.33" + process $proc$libresoc.v:177392$10808 + assign { } { } + assign $1\src30__data_o[1:0] 2'00 + sync always + sync init + update \src30__data_o $1\src30__data_o[1:0] + end + attribute \src "libresoc.v:177413.3-177414.25" + process $proc$libresoc.v:177413$10733 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:177415.3-177416.37" + process $proc$libresoc.v:177415$10734 + assign { } { } + assign $0\r0__data_o[1:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[1:0] + end + attribute \src "libresoc.v:177417.3-177418.43" + process $proc$libresoc.v:177417$10735 + assign { } { } + assign $0\src30__data_o[1:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[1:0] + end + attribute \src "libresoc.v:177419.3-177420.43" + process $proc$libresoc.v:177419$10736 + assign { } { } + assign $0\src20__data_o[1:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[1:0] + end + attribute \src "libresoc.v:177421.3-177422.43" + process $proc$libresoc.v:177421$10737 + assign { } { } + assign $0\src10__data_o[1:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[1:0] + end + attribute \src "libresoc.v:177423.3-177468.6" + process $proc$libresoc.v:177423$10738 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[1:0]$10739 $7\src10__data_o$next[1:0]$10746 + attribute \src "libresoc.v:177424.5-177424.29" + switch \initial + attribute \src "libresoc.v:177424.9-177424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[1:0]$10740 $6\src10__data_o$next[1:0]$10745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[1:0]$10741 \dest10__data_i + case + assign $2\src10__data_o$next[1:0]$10741 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[1:0]$10742 \dest20__data_i + case + assign $3\src10__data_o$next[1:0]$10742 $2\src10__data_o$next[1:0]$10741 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[1:0]$10743 \dest30__data_i + case + assign $4\src10__data_o$next[1:0]$10743 $3\src10__data_o$next[1:0]$10742 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[1:0]$10744 \w0__data_i + case + assign $5\src10__data_o$next[1:0]$10744 $4\src10__data_o$next[1:0]$10743 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[1:0]$10745 \reg + case + assign $6\src10__data_o$next[1:0]$10745 $5\src10__data_o$next[1:0]$10744 + end + case + assign $1\src10__data_o$next[1:0]$10740 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src10__data_o$next[1:0]$10746 2'00 + case + assign $7\src10__data_o$next[1:0]$10746 $1\src10__data_o$next[1:0]$10740 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[1:0]$10739 + end + attribute \src "libresoc.v:177469.3-177504.6" + process $proc$libresoc.v:177469$10747 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:177470.5-177470.29" + switch \initial + attribute \src "libresoc.v:177470.9-177470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:177505.3-177550.6" + process $proc$libresoc.v:177505$10748 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[1:0]$10749 $7\src20__data_o$next[1:0]$10756 + attribute \src "libresoc.v:177506.5-177506.29" + switch \initial + attribute \src "libresoc.v:177506.9-177506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[1:0]$10750 $6\src20__data_o$next[1:0]$10755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[1:0]$10751 \dest10__data_i + case + assign $2\src20__data_o$next[1:0]$10751 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[1:0]$10752 \dest20__data_i + case + assign $3\src20__data_o$next[1:0]$10752 $2\src20__data_o$next[1:0]$10751 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[1:0]$10753 \dest30__data_i + case + assign $4\src20__data_o$next[1:0]$10753 $3\src20__data_o$next[1:0]$10752 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[1:0]$10754 \w0__data_i + case + assign $5\src20__data_o$next[1:0]$10754 $4\src20__data_o$next[1:0]$10753 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[1:0]$10755 \reg + case + assign $6\src20__data_o$next[1:0]$10755 $5\src20__data_o$next[1:0]$10754 + end + case + assign $1\src20__data_o$next[1:0]$10750 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src20__data_o$next[1:0]$10756 2'00 + case + assign $7\src20__data_o$next[1:0]$10756 $1\src20__data_o$next[1:0]$10750 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[1:0]$10749 + end + attribute \src "libresoc.v:177551.3-177586.6" + process $proc$libresoc.v:177551$10757 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10758 $1\wr_detect$4[0:0]$10759 + attribute \src "libresoc.v:177552.5-177552.29" + switch \initial + attribute \src "libresoc.v:177552.9-177552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10759 $5\wr_detect$4[0:0]$10763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10760 1'1 + case + assign $2\wr_detect$4[0:0]$10760 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10761 1'1 + case + assign $3\wr_detect$4[0:0]$10761 $2\wr_detect$4[0:0]$10760 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10762 1'1 + case + assign $4\wr_detect$4[0:0]$10762 $3\wr_detect$4[0:0]$10761 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10763 1'1 + case + assign $5\wr_detect$4[0:0]$10763 $4\wr_detect$4[0:0]$10762 + end + case + assign $1\wr_detect$4[0:0]$10759 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10758 + end + attribute \src "libresoc.v:177587.3-177632.6" + process $proc$libresoc.v:177587$10764 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[1:0]$10765 $7\src30__data_o$next[1:0]$10772 + attribute \src "libresoc.v:177588.5-177588.29" + switch \initial + attribute \src "libresoc.v:177588.9-177588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[1:0]$10766 $6\src30__data_o$next[1:0]$10771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[1:0]$10767 \dest10__data_i + case + assign $2\src30__data_o$next[1:0]$10767 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[1:0]$10768 \dest20__data_i + case + assign $3\src30__data_o$next[1:0]$10768 $2\src30__data_o$next[1:0]$10767 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[1:0]$10769 \dest30__data_i + case + assign $4\src30__data_o$next[1:0]$10769 $3\src30__data_o$next[1:0]$10768 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[1:0]$10770 \w0__data_i + case + assign $5\src30__data_o$next[1:0]$10770 $4\src30__data_o$next[1:0]$10769 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[1:0]$10771 \reg + case + assign $6\src30__data_o$next[1:0]$10771 $5\src30__data_o$next[1:0]$10770 + end + case + assign $1\src30__data_o$next[1:0]$10766 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src30__data_o$next[1:0]$10772 2'00 + case + assign $7\src30__data_o$next[1:0]$10772 $1\src30__data_o$next[1:0]$10766 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[1:0]$10765 + end + attribute \src "libresoc.v:177633.3-177668.6" + process $proc$libresoc.v:177633$10773 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10774 $1\wr_detect$7[0:0]$10775 + attribute \src "libresoc.v:177634.5-177634.29" + switch \initial + attribute \src "libresoc.v:177634.9-177634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10775 $5\wr_detect$7[0:0]$10779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10776 1'1 + case + assign $2\wr_detect$7[0:0]$10776 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10777 1'1 + case + assign $3\wr_detect$7[0:0]$10777 $2\wr_detect$7[0:0]$10776 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10778 1'1 + case + assign $4\wr_detect$7[0:0]$10778 $3\wr_detect$7[0:0]$10777 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10779 1'1 + case + assign $5\wr_detect$7[0:0]$10779 $4\wr_detect$7[0:0]$10778 + end + case + assign $1\wr_detect$7[0:0]$10775 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10774 + end + attribute \src "libresoc.v:177669.3-177714.6" + process $proc$libresoc.v:177669$10780 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[1:0]$10781 $7\r0__data_o$next[1:0]$10788 + attribute \src "libresoc.v:177670.5-177670.29" + switch \initial + attribute \src "libresoc.v:177670.9-177670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[1:0]$10782 $6\r0__data_o$next[1:0]$10787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[1:0]$10783 \dest10__data_i + case + assign $2\r0__data_o$next[1:0]$10783 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[1:0]$10784 \dest20__data_i + case + assign $3\r0__data_o$next[1:0]$10784 $2\r0__data_o$next[1:0]$10783 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[1:0]$10785 \dest30__data_i + case + assign $4\r0__data_o$next[1:0]$10785 $3\r0__data_o$next[1:0]$10784 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[1:0]$10786 \w0__data_i + case + assign $5\r0__data_o$next[1:0]$10786 $4\r0__data_o$next[1:0]$10785 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[1:0]$10787 \reg + case + assign $6\r0__data_o$next[1:0]$10787 $5\r0__data_o$next[1:0]$10786 + end + case + assign $1\r0__data_o$next[1:0]$10782 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r0__data_o$next[1:0]$10788 2'00 + case + assign $7\r0__data_o$next[1:0]$10788 $1\r0__data_o$next[1:0]$10782 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[1:0]$10781 + end + attribute \src "libresoc.v:177715.3-177750.6" + process $proc$libresoc.v:177715$10789 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10790 $1\wr_detect$10[0:0]$10791 + attribute \src "libresoc.v:177716.5-177716.29" + switch \initial + attribute \src "libresoc.v:177716.9-177716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10791 $5\wr_detect$10[0:0]$10795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10792 1'1 + case + assign $2\wr_detect$10[0:0]$10792 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10793 1'1 + case + assign $3\wr_detect$10[0:0]$10793 $2\wr_detect$10[0:0]$10792 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10794 1'1 + case + assign $4\wr_detect$10[0:0]$10794 $3\wr_detect$10[0:0]$10793 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10795 1'1 + case + assign $5\wr_detect$10[0:0]$10795 $4\wr_detect$10[0:0]$10794 + end + case + assign $1\wr_detect$10[0:0]$10791 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10790 + end + attribute \src "libresoc.v:177751.3-177783.6" + process $proc$libresoc.v:177751$10796 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10797 $5\reg$next[1:0]$10802 + attribute \src "libresoc.v:177752.5-177752.29" + switch \initial + attribute \src "libresoc.v:177752.9-177752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10798 \dest10__data_i + case + assign $1\reg$next[1:0]$10798 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10799 \dest20__data_i + case + assign $2\reg$next[1:0]$10799 $1\reg$next[1:0]$10798 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10800 \dest30__data_i + case + assign $3\reg$next[1:0]$10800 $2\reg$next[1:0]$10799 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10801 \w0__data_i + case + assign $4\reg$next[1:0]$10801 $3\reg$next[1:0]$10800 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10802 2'00 + case + assign $5\reg$next[1:0]$10802 $4\reg$next[1:0]$10801 + end + sync always + update \reg$next $0\reg$next[1:0]$10797 + end + connect \$9 $not$libresoc.v:177409$10729_Y + connect \$1 $not$libresoc.v:177410$10730_Y + connect \$3 $not$libresoc.v:177411$10731_Y + connect \$6 $not$libresoc.v:177412$10732_Y +end +attribute \src "libresoc.v:177788.1-178137.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" +attribute \generator "nMigen" +module \reg_0$135 + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $0\cia0__data_o$next[63:0]$10817 + attribute \src "libresoc.v:177856.3-177857.41" + wire width 64 $0\cia0__data_o[63:0] + attribute \src "libresoc.v:177789.7-177789.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $0\msr0__data_o$next[63:0]$10827 + attribute \src "libresoc.v:177854.3-177855.41" + wire width 64 $0\msr0__data_o[63:0] + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $0\reg$next[63:0]$10859 + attribute \src "libresoc.v:177850.3-177851.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $0\sv0__data_o$next[63:0]$10843 + attribute \src "libresoc.v:177852.3-177853.39" + wire width 64 $0\sv0__data_o[63:0] + attribute \src "libresoc.v:177986.3-178021.6" + wire $0\wr_detect$4[0:0]$10836 + attribute \src "libresoc.v:178068.3-178103.6" + wire $0\wr_detect$7[0:0]$10852 + attribute \src "libresoc.v:177904.3-177939.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $1\cia0__data_o$next[63:0]$10818 + attribute \src "libresoc.v:177798.14-177798.49" + wire width 64 $1\cia0__data_o[63:0] + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $1\msr0__data_o$next[63:0]$10828 + attribute \src "libresoc.v:177815.14-177815.49" + wire width 64 $1\msr0__data_o[63:0] + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $1\reg$next[63:0]$10860 + attribute \src "libresoc.v:177827.14-177827.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $1\sv0__data_o$next[63:0]$10844 + attribute \src "libresoc.v:177834.14-177834.48" + wire width 64 $1\sv0__data_o[63:0] + attribute \src "libresoc.v:177986.3-178021.6" + wire $1\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:178068.3-178103.6" + wire $1\wr_detect$7[0:0]$10853 + attribute \src "libresoc.v:177904.3-177939.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $2\cia0__data_o$next[63:0]$10819 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $2\msr0__data_o$next[63:0]$10829 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $2\reg$next[63:0]$10861 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $2\sv0__data_o$next[63:0]$10845 + attribute \src "libresoc.v:177986.3-178021.6" + wire $2\wr_detect$4[0:0]$10838 + attribute \src "libresoc.v:178068.3-178103.6" + wire $2\wr_detect$7[0:0]$10854 + attribute \src "libresoc.v:177904.3-177939.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $3\cia0__data_o$next[63:0]$10820 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $3\msr0__data_o$next[63:0]$10830 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $3\reg$next[63:0]$10862 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $3\sv0__data_o$next[63:0]$10846 + attribute \src "libresoc.v:177986.3-178021.6" + wire $3\wr_detect$4[0:0]$10839 + attribute \src "libresoc.v:178068.3-178103.6" + wire $3\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:177904.3-177939.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $4\cia0__data_o$next[63:0]$10821 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $4\msr0__data_o$next[63:0]$10831 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $4\reg$next[63:0]$10863 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $4\sv0__data_o$next[63:0]$10847 + attribute \src "libresoc.v:177986.3-178021.6" + wire $4\wr_detect$4[0:0]$10840 + attribute \src "libresoc.v:178068.3-178103.6" + wire $4\wr_detect$7[0:0]$10856 + attribute \src "libresoc.v:177904.3-177939.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $5\cia0__data_o$next[63:0]$10822 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $5\msr0__data_o$next[63:0]$10832 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $5\reg$next[63:0]$10864 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $5\sv0__data_o$next[63:0]$10848 + attribute \src "libresoc.v:177986.3-178021.6" + wire $5\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:178068.3-178103.6" + wire $5\wr_detect$7[0:0]$10857 + attribute \src "libresoc.v:177904.3-177939.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $6\cia0__data_o$next[63:0]$10823 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $6\msr0__data_o$next[63:0]$10833 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $6\sv0__data_o$next[63:0]$10849 + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $7\cia0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $7\msr0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $7\sv0__data_o$next[63:0]$10850 + attribute \src "libresoc.v:177847.17-177847.100" + wire $not$libresoc.v:177847$10809_Y + attribute \src "libresoc.v:177848.17-177848.103" + wire $not$libresoc.v:177848$10810_Y + attribute \src "libresoc.v:177849.17-177849.103" + wire $not$libresoc.v:177849$10811_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr10__wen + attribute \src "libresoc.v:177789.7-177789.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177847$10809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:177847$10809_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177848$10810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:177848$10810_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:177849$10811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:177849$10811_Y + end + attribute \src "libresoc.v:177789.7-177789.20" + process $proc$libresoc.v:177789$10865 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177798.14-177798.49" + process $proc$libresoc.v:177798$10866 + assign { } { } + assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia0__data_o $1\cia0__data_o[63:0] + end + attribute \src "libresoc.v:177815.14-177815.49" + process $proc$libresoc.v:177815$10867 + assign { } { } + assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr0__data_o $1\msr0__data_o[63:0] + end + attribute \src "libresoc.v:177827.14-177827.42" + process $proc$libresoc.v:177827$10868 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:177834.14-177834.48" + process $proc$libresoc.v:177834$10869 + assign { } { } + assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv0__data_o $1\sv0__data_o[63:0] + end + attribute \src "libresoc.v:177850.3-177851.25" + process $proc$libresoc.v:177850$10812 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:177852.3-177853.39" + process $proc$libresoc.v:177852$10813 + assign { } { } + assign $0\sv0__data_o[63:0] \sv0__data_o$next + sync posedge \coresync_clk + update \sv0__data_o $0\sv0__data_o[63:0] + end + attribute \src "libresoc.v:177854.3-177855.41" + process $proc$libresoc.v:177854$10814 + assign { } { } + assign $0\msr0__data_o[63:0] \msr0__data_o$next + sync posedge \coresync_clk + update \msr0__data_o $0\msr0__data_o[63:0] + end + attribute \src "libresoc.v:177856.3-177857.41" + process $proc$libresoc.v:177856$10815 + assign { } { } + assign $0\cia0__data_o[63:0] \cia0__data_o$next + sync posedge \coresync_clk + update \cia0__data_o $0\cia0__data_o[63:0] + end + attribute \src "libresoc.v:177858.3-177903.6" + process $proc$libresoc.v:177858$10816 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia0__data_o$next[63:0]$10817 $7\cia0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:177859.5-177859.29" + switch \initial + attribute \src "libresoc.v:177859.9-177859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia0__data_o$next[63:0]$10818 $6\cia0__data_o$next[63:0]$10823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia0__data_o$next[63:0]$10819 \nia0__data_i + case + assign $2\cia0__data_o$next[63:0]$10819 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia0__data_o$next[63:0]$10820 \msr0__data_i + case + assign $3\cia0__data_o$next[63:0]$10820 $2\cia0__data_o$next[63:0]$10819 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia0__data_o$next[63:0]$10821 \sv0__data_i + case + assign $4\cia0__data_o$next[63:0]$10821 $3\cia0__data_o$next[63:0]$10820 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia0__data_o$next[63:0]$10822 \d_wr10__data_i + case + assign $5\cia0__data_o$next[63:0]$10822 $4\cia0__data_o$next[63:0]$10821 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia0__data_o$next[63:0]$10823 \reg + case + assign $6\cia0__data_o$next[63:0]$10823 $5\cia0__data_o$next[63:0]$10822 + end + case + assign $1\cia0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia0__data_o$next[63:0]$10824 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia0__data_o$next[63:0]$10824 $1\cia0__data_o$next[63:0]$10818 + end + sync always + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10817 + end + attribute \src "libresoc.v:177904.3-177939.6" + process $proc$libresoc.v:177904$10825 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:177905.5-177905.29" + switch \initial + attribute \src "libresoc.v:177905.9-177905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:177940.3-177985.6" + process $proc$libresoc.v:177940$10826 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr0__data_o$next[63:0]$10827 $7\msr0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:177941.5-177941.29" + switch \initial + attribute \src "libresoc.v:177941.9-177941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr0__data_o$next[63:0]$10828 $6\msr0__data_o$next[63:0]$10833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr0__data_o$next[63:0]$10829 \nia0__data_i + case + assign $2\msr0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr0__data_o$next[63:0]$10830 \msr0__data_i + case + assign $3\msr0__data_o$next[63:0]$10830 $2\msr0__data_o$next[63:0]$10829 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr0__data_o$next[63:0]$10831 \sv0__data_i + case + assign $4\msr0__data_o$next[63:0]$10831 $3\msr0__data_o$next[63:0]$10830 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr0__data_o$next[63:0]$10832 \d_wr10__data_i + case + assign $5\msr0__data_o$next[63:0]$10832 $4\msr0__data_o$next[63:0]$10831 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr0__data_o$next[63:0]$10833 \reg + case + assign $6\msr0__data_o$next[63:0]$10833 $5\msr0__data_o$next[63:0]$10832 + end + case + assign $1\msr0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\msr0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\msr0__data_o$next[63:0]$10834 $1\msr0__data_o$next[63:0]$10828 + end + sync always + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10827 + end + attribute \src "libresoc.v:177986.3-178021.6" + process $proc$libresoc.v:177986$10835 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10836 $1\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:177987.5-177987.29" + switch \initial + attribute \src "libresoc.v:177987.9-177987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10837 $5\wr_detect$4[0:0]$10841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10838 1'1 + case + assign $2\wr_detect$4[0:0]$10838 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10839 1'1 + case + assign $3\wr_detect$4[0:0]$10839 $2\wr_detect$4[0:0]$10838 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10840 1'1 + case + assign $4\wr_detect$4[0:0]$10840 $3\wr_detect$4[0:0]$10839 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10841 1'1 + case + assign $5\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10840 + end + case + assign $1\wr_detect$4[0:0]$10837 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10836 + end + attribute \src "libresoc.v:178022.3-178067.6" + process $proc$libresoc.v:178022$10842 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv0__data_o$next[63:0]$10843 $7\sv0__data_o$next[63:0]$10850 + attribute \src "libresoc.v:178023.5-178023.29" + switch \initial + attribute \src "libresoc.v:178023.9-178023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv0__data_o$next[63:0]$10844 $6\sv0__data_o$next[63:0]$10849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv0__data_o$next[63:0]$10845 \nia0__data_i + case + assign $2\sv0__data_o$next[63:0]$10845 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv0__data_o$next[63:0]$10846 \msr0__data_i + case + assign $3\sv0__data_o$next[63:0]$10846 $2\sv0__data_o$next[63:0]$10845 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv0__data_o$next[63:0]$10847 \sv0__data_i + case + assign $4\sv0__data_o$next[63:0]$10847 $3\sv0__data_o$next[63:0]$10846 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv0__data_o$next[63:0]$10848 \d_wr10__data_i + case + assign $5\sv0__data_o$next[63:0]$10848 $4\sv0__data_o$next[63:0]$10847 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv0__data_o$next[63:0]$10849 \reg + case + assign $6\sv0__data_o$next[63:0]$10849 $5\sv0__data_o$next[63:0]$10848 + end + case + assign $1\sv0__data_o$next[63:0]$10844 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv0__data_o$next[63:0]$10850 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv0__data_o$next[63:0]$10850 $1\sv0__data_o$next[63:0]$10844 + end + sync always + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10843 + end + attribute \src "libresoc.v:178068.3-178103.6" + process $proc$libresoc.v:178068$10851 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10852 $1\wr_detect$7[0:0]$10853 + attribute \src "libresoc.v:178069.5-178069.29" + switch \initial + attribute \src "libresoc.v:178069.9-178069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10853 $5\wr_detect$7[0:0]$10857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10854 1'1 + case + assign $2\wr_detect$7[0:0]$10854 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10855 1'1 + case + assign $3\wr_detect$7[0:0]$10855 $2\wr_detect$7[0:0]$10854 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10856 1'1 + case + assign $4\wr_detect$7[0:0]$10856 $3\wr_detect$7[0:0]$10855 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10857 1'1 + case + assign $5\wr_detect$7[0:0]$10857 $4\wr_detect$7[0:0]$10856 + end + case + assign $1\wr_detect$7[0:0]$10853 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10852 + end + attribute \src "libresoc.v:178104.3-178136.6" + process $proc$libresoc.v:178104$10858 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10859 $5\reg$next[63:0]$10864 + attribute \src "libresoc.v:178105.5-178105.29" + switch \initial + attribute \src "libresoc.v:178105.9-178105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10860 \nia0__data_i + case + assign $1\reg$next[63:0]$10860 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10861 \msr0__data_i + case + assign $2\reg$next[63:0]$10861 $1\reg$next[63:0]$10860 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10862 \sv0__data_i + case + assign $3\reg$next[63:0]$10862 $2\reg$next[63:0]$10861 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10863 \d_wr10__data_i + case + assign $4\reg$next[63:0]$10863 $3\reg$next[63:0]$10862 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[63:0]$10864 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $5\reg$next[63:0]$10864 $4\reg$next[63:0]$10863 + end + sync always + update \reg$next $0\reg$next[63:0]$10859 + end + connect \$1 $not$libresoc.v:177847$10809_Y + connect \$3 $not$libresoc.v:177848$10810_Y + connect \$6 $not$libresoc.v:177849$10811_Y +end +attribute \src "libresoc.v:178141.1-178696.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" +attribute \generator "nMigen" +module \reg_1 + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $0\cr_pred1__data_o$next[3:0]$10884 + attribute \src "libresoc.v:178247.3-178248.49" + wire width 4 $0\cr_pred1__data_o[3:0] + attribute \src "libresoc.v:178142.7-178142.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $0\r1__data_o$next[3:0]$10955 + attribute \src "libresoc.v:178239.3-178240.37" + wire width 4 $0\r1__data_o[3:0] + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $0\r21__data_o$next[3:0]$10893 + attribute \src "libresoc.v:178237.3-178238.39" + wire width 4 $0\r21__data_o[3:0] + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $0\reg$next[3:0]$10907 + attribute \src "libresoc.v:178235.3-178236.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $0\src11__data_o$next[3:0]$10913 + attribute \src "libresoc.v:178245.3-178246.43" + wire width 4 $0\src11__data_o[3:0] + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $0\src21__data_o$next[3:0]$10927 + attribute \src "libresoc.v:178243.3-178244.43" + wire width 4 $0\src21__data_o[3:0] + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $0\src31__data_o$next[3:0]$10941 + attribute \src "libresoc.v:178241.3-178242.43" + wire width 4 $0\src31__data_o[3:0] + attribute \src "libresoc.v:178596.3-178625.6" + wire $0\wr_detect$10[0:0]$10949 + attribute \src "libresoc.v:178666.3-178695.6" + wire $0\wr_detect$13[0:0]$10963 + attribute \src "libresoc.v:178359.3-178388.6" + wire $0\wr_detect$16[0:0]$10901 + attribute \src "libresoc.v:178456.3-178485.6" + wire $0\wr_detect$4[0:0]$10921 + attribute \src "libresoc.v:178526.3-178555.6" + wire $0\wr_detect$7[0:0]$10935 + attribute \src "libresoc.v:178289.3-178318.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $1\cr_pred1__data_o$next[3:0]$10885 + attribute \src "libresoc.v:178161.13-178161.36" + wire width 4 $1\cr_pred1__data_o[3:0] + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $1\r1__data_o$next[3:0]$10956 + attribute \src "libresoc.v:178176.13-178176.30" + wire width 4 $1\r1__data_o[3:0] + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $1\r21__data_o$next[3:0]$10894 + attribute \src "libresoc.v:178183.13-178183.31" + wire width 4 $1\r21__data_o[3:0] + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $1\reg$next[3:0]$10908 + attribute \src "libresoc.v:178189.13-178189.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $1\src11__data_o$next[3:0]$10914 + attribute \src "libresoc.v:178194.13-178194.33" + wire width 4 $1\src11__data_o[3:0] + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $1\src21__data_o$next[3:0]$10928 + attribute \src "libresoc.v:178201.13-178201.33" + wire width 4 $1\src21__data_o[3:0] + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $1\src31__data_o$next[3:0]$10942 + attribute \src "libresoc.v:178208.13-178208.33" + wire width 4 $1\src31__data_o[3:0] + attribute \src "libresoc.v:178596.3-178625.6" + wire $1\wr_detect$10[0:0]$10950 + attribute \src "libresoc.v:178666.3-178695.6" + wire $1\wr_detect$13[0:0]$10964 + attribute \src "libresoc.v:178359.3-178388.6" + wire $1\wr_detect$16[0:0]$10902 + attribute \src "libresoc.v:178456.3-178485.6" + wire $1\wr_detect$4[0:0]$10922 + attribute \src "libresoc.v:178526.3-178555.6" + wire $1\wr_detect$7[0:0]$10936 + attribute \src "libresoc.v:178289.3-178318.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $2\cr_pred1__data_o$next[3:0]$10886 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $2\r1__data_o$next[3:0]$10957 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $2\r21__data_o$next[3:0]$10895 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $2\reg$next[3:0]$10909 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $2\src11__data_o$next[3:0]$10915 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $2\src21__data_o$next[3:0]$10929 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $2\src31__data_o$next[3:0]$10943 + attribute \src "libresoc.v:178596.3-178625.6" + wire $2\wr_detect$10[0:0]$10951 + attribute \src "libresoc.v:178666.3-178695.6" + wire $2\wr_detect$13[0:0]$10965 + attribute \src "libresoc.v:178359.3-178388.6" + wire $2\wr_detect$16[0:0]$10903 + attribute \src "libresoc.v:178456.3-178485.6" + wire $2\wr_detect$4[0:0]$10923 + attribute \src "libresoc.v:178526.3-178555.6" + wire $2\wr_detect$7[0:0]$10937 + attribute \src "libresoc.v:178289.3-178318.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $3\cr_pred1__data_o$next[3:0]$10887 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $3\r1__data_o$next[3:0]$10958 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $3\r21__data_o$next[3:0]$10896 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $3\reg$next[3:0]$10910 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $3\src11__data_o$next[3:0]$10916 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $3\src21__data_o$next[3:0]$10930 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $3\src31__data_o$next[3:0]$10944 + attribute \src "libresoc.v:178596.3-178625.6" + wire $3\wr_detect$10[0:0]$10952 + attribute \src "libresoc.v:178666.3-178695.6" + wire $3\wr_detect$13[0:0]$10966 + attribute \src "libresoc.v:178359.3-178388.6" + wire $3\wr_detect$16[0:0]$10904 + attribute \src "libresoc.v:178456.3-178485.6" + wire $3\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:178526.3-178555.6" + wire $3\wr_detect$7[0:0]$10938 + attribute \src "libresoc.v:178289.3-178318.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $4\cr_pred1__data_o$next[3:0]$10888 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $4\r1__data_o$next[3:0]$10959 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $4\r21__data_o$next[3:0]$10897 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $4\reg$next[3:0]$10911 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $4\src11__data_o$next[3:0]$10917 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $4\src21__data_o$next[3:0]$10931 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $4\src31__data_o$next[3:0]$10945 + attribute \src "libresoc.v:178596.3-178625.6" + wire $4\wr_detect$10[0:0]$10953 + attribute \src "libresoc.v:178666.3-178695.6" + wire $4\wr_detect$13[0:0]$10967 + attribute \src "libresoc.v:178359.3-178388.6" + wire $4\wr_detect$16[0:0]$10905 + attribute \src "libresoc.v:178456.3-178485.6" + wire $4\wr_detect$4[0:0]$10925 + attribute \src "libresoc.v:178526.3-178555.6" + wire $4\wr_detect$7[0:0]$10939 + attribute \src "libresoc.v:178289.3-178318.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $5\cr_pred1__data_o$next[3:0]$10889 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $5\r1__data_o$next[3:0]$10960 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $5\r21__data_o$next[3:0]$10898 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $5\src11__data_o$next[3:0]$10918 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $5\src21__data_o$next[3:0]$10932 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $5\src31__data_o$next[3:0]$10946 + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $6\cr_pred1__data_o$next[3:0]$10890 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $6\r1__data_o$next[3:0]$10961 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $6\r21__data_o$next[3:0]$10899 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $6\src11__data_o$next[3:0]$10919 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $6\src21__data_o$next[3:0]$10933 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $6\src31__data_o$next[3:0]$10947 + attribute \src "libresoc.v:178229.17-178229.104" + wire $not$libresoc.v:178229$10870_Y + attribute \src "libresoc.v:178230.18-178230.105" + wire $not$libresoc.v:178230$10871_Y + attribute \src "libresoc.v:178231.18-178231.105" + wire $not$libresoc.v:178231$10872_Y + attribute \src "libresoc.v:178232.17-178232.100" + wire $not$libresoc.v:178232$10873_Y + attribute \src "libresoc.v:178233.17-178233.103" + wire $not$libresoc.v:178233$10874_Y + attribute \src "libresoc.v:178234.17-178234.103" + wire $not$libresoc.v:178234$10875_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest21__wen + attribute \src "libresoc.v:178142.7-178142.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178229$10870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:178229$10870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178230$10871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:178230$10871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178231$10872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:178231$10872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178232$10873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:178232$10873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178233$10874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:178233$10874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178234$10875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:178234$10875_Y + end + attribute \src "libresoc.v:178142.7-178142.20" + process $proc$libresoc.v:178142$10968 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178161.13-178161.36" + process $proc$libresoc.v:178161$10969 + assign { } { } + assign $1\cr_pred1__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred1__data_o $1\cr_pred1__data_o[3:0] + end + attribute \src "libresoc.v:178176.13-178176.30" + process $proc$libresoc.v:178176$10970 + assign { } { } + assign $1\r1__data_o[3:0] 4'0000 + sync always + sync init + update \r1__data_o $1\r1__data_o[3:0] + end + attribute \src "libresoc.v:178183.13-178183.31" + process $proc$libresoc.v:178183$10971 + assign { } { } + assign $1\r21__data_o[3:0] 4'0000 + sync always + sync init + update \r21__data_o $1\r21__data_o[3:0] + end + attribute \src "libresoc.v:178189.13-178189.25" + process $proc$libresoc.v:178189$10972 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:178194.13-178194.33" + process $proc$libresoc.v:178194$10973 + assign { } { } + assign $1\src11__data_o[3:0] 4'0000 + sync always + sync init + update \src11__data_o $1\src11__data_o[3:0] + end + attribute \src "libresoc.v:178201.13-178201.33" + process $proc$libresoc.v:178201$10974 + assign { } { } + assign $1\src21__data_o[3:0] 4'0000 + sync always + sync init + update \src21__data_o $1\src21__data_o[3:0] + end + attribute \src "libresoc.v:178208.13-178208.33" + process $proc$libresoc.v:178208$10975 + assign { } { } + assign $1\src31__data_o[3:0] 4'0000 + sync always + sync init + update \src31__data_o $1\src31__data_o[3:0] + end + attribute \src "libresoc.v:178235.3-178236.25" + process $proc$libresoc.v:178235$10876 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:178237.3-178238.39" + process $proc$libresoc.v:178237$10877 + assign { } { } + assign $0\r21__data_o[3:0] \r21__data_o$next + sync posedge \coresync_clk + update \r21__data_o $0\r21__data_o[3:0] + end + attribute \src "libresoc.v:178239.3-178240.37" + process $proc$libresoc.v:178239$10878 + assign { } { } + assign $0\r1__data_o[3:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[3:0] + end + attribute \src "libresoc.v:178241.3-178242.43" + process $proc$libresoc.v:178241$10879 + assign { } { } + assign $0\src31__data_o[3:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[3:0] + end + attribute \src "libresoc.v:178243.3-178244.43" + process $proc$libresoc.v:178243$10880 + assign { } { } + assign $0\src21__data_o[3:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[3:0] + end + attribute \src "libresoc.v:178245.3-178246.43" + process $proc$libresoc.v:178245$10881 + assign { } { } + assign $0\src11__data_o[3:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[3:0] + end + attribute \src "libresoc.v:178247.3-178248.49" + process $proc$libresoc.v:178247$10882 + assign { } { } + assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next + sync posedge \coresync_clk + update \cr_pred1__data_o $0\cr_pred1__data_o[3:0] + end + attribute \src "libresoc.v:178249.3-178288.6" + process $proc$libresoc.v:178249$10883 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred1__data_o$next[3:0]$10884 $6\cr_pred1__data_o$next[3:0]$10890 + attribute \src "libresoc.v:178250.5-178250.29" + switch \initial + attribute \src "libresoc.v:178250.9-178250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred1__data_o$next[3:0]$10885 $5\cr_pred1__data_o$next[3:0]$10889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred1__data_o$next[3:0]$10886 \dest11__data_i + case + assign $2\cr_pred1__data_o$next[3:0]$10886 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred1__data_o$next[3:0]$10887 \dest21__data_i + case + assign $3\cr_pred1__data_o$next[3:0]$10887 $2\cr_pred1__data_o$next[3:0]$10886 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred1__data_o$next[3:0]$10888 \w1__data_i + case + assign $4\cr_pred1__data_o$next[3:0]$10888 $3\cr_pred1__data_o$next[3:0]$10887 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred1__data_o$next[3:0]$10889 \reg + case + assign $5\cr_pred1__data_o$next[3:0]$10889 $4\cr_pred1__data_o$next[3:0]$10888 + end + case + assign $1\cr_pred1__data_o$next[3:0]$10885 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred1__data_o$next[3:0]$10890 4'0000 + case + assign $6\cr_pred1__data_o$next[3:0]$10890 $1\cr_pred1__data_o$next[3:0]$10885 + end + sync always + update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10884 + end + attribute \src "libresoc.v:178289.3-178318.6" + process $proc$libresoc.v:178289$10891 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:178290.5-178290.29" + switch \initial + attribute \src "libresoc.v:178290.9-178290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:178319.3-178358.6" + process $proc$libresoc.v:178319$10892 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$10893 $6\r21__data_o$next[3:0]$10899 + attribute \src "libresoc.v:178320.5-178320.29" + switch \initial + attribute \src "libresoc.v:178320.9-178320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$10894 $5\r21__data_o$next[3:0]$10898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$10895 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$10895 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$10896 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$10896 $2\r21__data_o$next[3:0]$10895 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$10897 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$10897 $3\r21__data_o$next[3:0]$10896 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$10898 \reg + case + assign $5\r21__data_o$next[3:0]$10898 $4\r21__data_o$next[3:0]$10897 + end + case + assign $1\r21__data_o$next[3:0]$10894 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$10899 4'0000 + case + assign $6\r21__data_o$next[3:0]$10899 $1\r21__data_o$next[3:0]$10894 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$10893 + end + attribute \src "libresoc.v:178359.3-178388.6" + process $proc$libresoc.v:178359$10900 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$10901 $1\wr_detect$16[0:0]$10902 + attribute \src "libresoc.v:178360.5-178360.29" + switch \initial + attribute \src "libresoc.v:178360.9-178360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$10902 $4\wr_detect$16[0:0]$10905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$10903 1'1 + case + assign $2\wr_detect$16[0:0]$10903 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$10904 1'1 + case + assign $3\wr_detect$16[0:0]$10904 $2\wr_detect$16[0:0]$10903 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$10905 1'1 + case + assign $4\wr_detect$16[0:0]$10905 $3\wr_detect$16[0:0]$10904 + end + case + assign $1\wr_detect$16[0:0]$10902 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$10901 + end + attribute \src "libresoc.v:178389.3-178415.6" + process $proc$libresoc.v:178389$10906 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10907 $4\reg$next[3:0]$10911 + attribute \src "libresoc.v:178390.5-178390.29" + switch \initial + attribute \src "libresoc.v:178390.9-178390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10908 \dest11__data_i + case + assign $1\reg$next[3:0]$10908 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10909 \dest21__data_i + case + assign $2\reg$next[3:0]$10909 $1\reg$next[3:0]$10908 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10910 \w1__data_i + case + assign $3\reg$next[3:0]$10910 $2\reg$next[3:0]$10909 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10911 4'0000 + case + assign $4\reg$next[3:0]$10911 $3\reg$next[3:0]$10910 + end + sync always + update \reg$next $0\reg$next[3:0]$10907 + end + attribute \src "libresoc.v:178416.3-178455.6" + process $proc$libresoc.v:178416$10912 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[3:0]$10913 $6\src11__data_o$next[3:0]$10919 + attribute \src "libresoc.v:178417.5-178417.29" + switch \initial + attribute \src "libresoc.v:178417.9-178417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[3:0]$10914 $5\src11__data_o$next[3:0]$10918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[3:0]$10915 \dest11__data_i + case + assign $2\src11__data_o$next[3:0]$10915 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[3:0]$10916 \dest21__data_i + case + assign $3\src11__data_o$next[3:0]$10916 $2\src11__data_o$next[3:0]$10915 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[3:0]$10917 \w1__data_i + case + assign $4\src11__data_o$next[3:0]$10917 $3\src11__data_o$next[3:0]$10916 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[3:0]$10918 \reg + case + assign $5\src11__data_o$next[3:0]$10918 $4\src11__data_o$next[3:0]$10917 + end + case + assign $1\src11__data_o$next[3:0]$10914 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[3:0]$10919 4'0000 + case + assign $6\src11__data_o$next[3:0]$10919 $1\src11__data_o$next[3:0]$10914 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[3:0]$10913 + end + attribute \src "libresoc.v:178456.3-178485.6" + process $proc$libresoc.v:178456$10920 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10921 $1\wr_detect$4[0:0]$10922 + attribute \src "libresoc.v:178457.5-178457.29" + switch \initial + attribute \src "libresoc.v:178457.9-178457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10922 $4\wr_detect$4[0:0]$10925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10923 1'1 + case + assign $2\wr_detect$4[0:0]$10923 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10924 1'1 + case + assign $3\wr_detect$4[0:0]$10924 $2\wr_detect$4[0:0]$10923 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10925 1'1 + case + assign $4\wr_detect$4[0:0]$10925 $3\wr_detect$4[0:0]$10924 + end + case + assign $1\wr_detect$4[0:0]$10922 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10921 + end + attribute \src "libresoc.v:178486.3-178525.6" + process $proc$libresoc.v:178486$10926 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[3:0]$10927 $6\src21__data_o$next[3:0]$10933 + attribute \src "libresoc.v:178487.5-178487.29" + switch \initial + attribute \src "libresoc.v:178487.9-178487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[3:0]$10928 $5\src21__data_o$next[3:0]$10932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[3:0]$10929 \dest11__data_i + case + assign $2\src21__data_o$next[3:0]$10929 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[3:0]$10930 \dest21__data_i + case + assign $3\src21__data_o$next[3:0]$10930 $2\src21__data_o$next[3:0]$10929 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[3:0]$10931 \w1__data_i + case + assign $4\src21__data_o$next[3:0]$10931 $3\src21__data_o$next[3:0]$10930 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[3:0]$10932 \reg + case + assign $5\src21__data_o$next[3:0]$10932 $4\src21__data_o$next[3:0]$10931 + end + case + assign $1\src21__data_o$next[3:0]$10928 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[3:0]$10933 4'0000 + case + assign $6\src21__data_o$next[3:0]$10933 $1\src21__data_o$next[3:0]$10928 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[3:0]$10927 + end + attribute \src "libresoc.v:178526.3-178555.6" + process $proc$libresoc.v:178526$10934 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10935 $1\wr_detect$7[0:0]$10936 + attribute \src "libresoc.v:178527.5-178527.29" + switch \initial + attribute \src "libresoc.v:178527.9-178527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10936 $4\wr_detect$7[0:0]$10939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10937 1'1 + case + assign $2\wr_detect$7[0:0]$10937 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10938 1'1 + case + assign $3\wr_detect$7[0:0]$10938 $2\wr_detect$7[0:0]$10937 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10939 1'1 + case + assign $4\wr_detect$7[0:0]$10939 $3\wr_detect$7[0:0]$10938 + end + case + assign $1\wr_detect$7[0:0]$10936 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10935 + end + attribute \src "libresoc.v:178556.3-178595.6" + process $proc$libresoc.v:178556$10940 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[3:0]$10941 $6\src31__data_o$next[3:0]$10947 + attribute \src "libresoc.v:178557.5-178557.29" + switch \initial + attribute \src "libresoc.v:178557.9-178557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[3:0]$10942 $5\src31__data_o$next[3:0]$10946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[3:0]$10943 \dest11__data_i + case + assign $2\src31__data_o$next[3:0]$10943 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[3:0]$10944 \dest21__data_i + case + assign $3\src31__data_o$next[3:0]$10944 $2\src31__data_o$next[3:0]$10943 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[3:0]$10945 \w1__data_i + case + assign $4\src31__data_o$next[3:0]$10945 $3\src31__data_o$next[3:0]$10944 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[3:0]$10946 \reg + case + assign $5\src31__data_o$next[3:0]$10946 $4\src31__data_o$next[3:0]$10945 + end + case + assign $1\src31__data_o$next[3:0]$10942 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[3:0]$10947 4'0000 + case + assign $6\src31__data_o$next[3:0]$10947 $1\src31__data_o$next[3:0]$10942 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[3:0]$10941 + end + attribute \src "libresoc.v:178596.3-178625.6" + process $proc$libresoc.v:178596$10948 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10949 $1\wr_detect$10[0:0]$10950 + attribute \src "libresoc.v:178597.5-178597.29" + switch \initial + attribute \src "libresoc.v:178597.9-178597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10950 $4\wr_detect$10[0:0]$10953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10951 1'1 + case + assign $2\wr_detect$10[0:0]$10951 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10952 1'1 + case + assign $3\wr_detect$10[0:0]$10952 $2\wr_detect$10[0:0]$10951 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10953 1'1 + case + assign $4\wr_detect$10[0:0]$10953 $3\wr_detect$10[0:0]$10952 + end + case + assign $1\wr_detect$10[0:0]$10950 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10949 + end + attribute \src "libresoc.v:178626.3-178665.6" + process $proc$libresoc.v:178626$10954 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[3:0]$10955 $6\r1__data_o$next[3:0]$10961 + attribute \src "libresoc.v:178627.5-178627.29" + switch \initial + attribute \src "libresoc.v:178627.9-178627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[3:0]$10956 $5\r1__data_o$next[3:0]$10960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[3:0]$10957 \dest11__data_i + case + assign $2\r1__data_o$next[3:0]$10957 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[3:0]$10958 \dest21__data_i + case + assign $3\r1__data_o$next[3:0]$10958 $2\r1__data_o$next[3:0]$10957 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[3:0]$10959 \w1__data_i + case + assign $4\r1__data_o$next[3:0]$10959 $3\r1__data_o$next[3:0]$10958 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[3:0]$10960 \reg + case + assign $5\r1__data_o$next[3:0]$10960 $4\r1__data_o$next[3:0]$10959 + end + case + assign $1\r1__data_o$next[3:0]$10956 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[3:0]$10961 4'0000 + case + assign $6\r1__data_o$next[3:0]$10961 $1\r1__data_o$next[3:0]$10956 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[3:0]$10955 + end + attribute \src "libresoc.v:178666.3-178695.6" + process $proc$libresoc.v:178666$10962 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10963 $1\wr_detect$13[0:0]$10964 + attribute \src "libresoc.v:178667.5-178667.29" + switch \initial + attribute \src "libresoc.v:178667.9-178667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10964 $4\wr_detect$13[0:0]$10967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10965 1'1 + case + assign $2\wr_detect$13[0:0]$10965 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10966 1'1 + case + assign $3\wr_detect$13[0:0]$10966 $2\wr_detect$13[0:0]$10965 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10967 1'1 + case + assign $4\wr_detect$13[0:0]$10967 $3\wr_detect$13[0:0]$10966 + end + case + assign $1\wr_detect$13[0:0]$10964 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10963 + end + connect \$9 $not$libresoc.v:178229$10870_Y + connect \$12 $not$libresoc.v:178230$10871_Y + connect \$15 $not$libresoc.v:178231$10872_Y + connect \$1 $not$libresoc.v:178232$10873_Y + connect \$3 $not$libresoc.v:178233$10874_Y + connect \$6 $not$libresoc.v:178234$10875_Y +end +attribute \src "libresoc.v:178700.1-179145.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" +attribute \generator "nMigen" +module \reg_1$133 + attribute \src "libresoc.v:178701.7-178701.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $0\r1__data_o$next[1:0]$11028 + attribute \src "libresoc.v:178776.3-178777.37" + wire width 2 $0\r1__data_o[1:0] + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $0\reg$next[1:0]$11044 + attribute \src "libresoc.v:178774.3-178775.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $0\src11__data_o$next[1:0]$10986 + attribute \src "libresoc.v:178782.3-178783.43" + wire width 2 $0\src11__data_o[1:0] + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $0\src21__data_o$next[1:0]$10996 + attribute \src "libresoc.v:178780.3-178781.43" + wire width 2 $0\src21__data_o[1:0] + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $0\src31__data_o$next[1:0]$11012 + attribute \src "libresoc.v:178778.3-178779.43" + wire width 2 $0\src31__data_o[1:0] + attribute \src "libresoc.v:179076.3-179111.6" + wire $0\wr_detect$10[0:0]$11037 + attribute \src "libresoc.v:178912.3-178947.6" + wire $0\wr_detect$4[0:0]$11005 + attribute \src "libresoc.v:178994.3-179029.6" + wire $0\wr_detect$7[0:0]$11021 + attribute \src "libresoc.v:178830.3-178865.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $1\r1__data_o$next[1:0]$11029 + attribute \src "libresoc.v:178728.13-178728.30" + wire width 2 $1\r1__data_o[1:0] + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $1\reg$next[1:0]$11045 + attribute \src "libresoc.v:178734.13-178734.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $1\src11__data_o$next[1:0]$10987 + attribute \src "libresoc.v:178739.13-178739.33" + wire width 2 $1\src11__data_o[1:0] + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $1\src21__data_o$next[1:0]$10997 + attribute \src "libresoc.v:178746.13-178746.33" + wire width 2 $1\src21__data_o[1:0] + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $1\src31__data_o$next[1:0]$11013 + attribute \src "libresoc.v:178753.13-178753.33" + wire width 2 $1\src31__data_o[1:0] + attribute \src "libresoc.v:179076.3-179111.6" + wire $1\wr_detect$10[0:0]$11038 + attribute \src "libresoc.v:178912.3-178947.6" + wire $1\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:178994.3-179029.6" + wire $1\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:178830.3-178865.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $2\r1__data_o$next[1:0]$11030 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $2\reg$next[1:0]$11046 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $2\src11__data_o$next[1:0]$10988 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $2\src21__data_o$next[1:0]$10998 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $2\src31__data_o$next[1:0]$11014 + attribute \src "libresoc.v:179076.3-179111.6" + wire $2\wr_detect$10[0:0]$11039 + attribute \src "libresoc.v:178912.3-178947.6" + wire $2\wr_detect$4[0:0]$11007 + attribute \src "libresoc.v:178994.3-179029.6" + wire $2\wr_detect$7[0:0]$11023 + attribute \src "libresoc.v:178830.3-178865.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $3\r1__data_o$next[1:0]$11031 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $3\reg$next[1:0]$11047 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $3\src11__data_o$next[1:0]$10989 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $3\src21__data_o$next[1:0]$10999 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $3\src31__data_o$next[1:0]$11015 + attribute \src "libresoc.v:179076.3-179111.6" + wire $3\wr_detect$10[0:0]$11040 + attribute \src "libresoc.v:178912.3-178947.6" + wire $3\wr_detect$4[0:0]$11008 + attribute \src "libresoc.v:178994.3-179029.6" + wire $3\wr_detect$7[0:0]$11024 + attribute \src "libresoc.v:178830.3-178865.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $4\r1__data_o$next[1:0]$11032 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $4\reg$next[1:0]$11048 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $4\src11__data_o$next[1:0]$10990 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $4\src21__data_o$next[1:0]$11000 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $4\src31__data_o$next[1:0]$11016 + attribute \src "libresoc.v:179076.3-179111.6" + wire $4\wr_detect$10[0:0]$11041 + attribute \src "libresoc.v:178912.3-178947.6" + wire $4\wr_detect$4[0:0]$11009 + attribute \src "libresoc.v:178994.3-179029.6" + wire $4\wr_detect$7[0:0]$11025 + attribute \src "libresoc.v:178830.3-178865.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $5\r1__data_o$next[1:0]$11033 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $5\reg$next[1:0]$11049 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $5\src11__data_o$next[1:0]$10991 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $5\src21__data_o$next[1:0]$11001 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $5\src31__data_o$next[1:0]$11017 + attribute \src "libresoc.v:179076.3-179111.6" + wire $5\wr_detect$10[0:0]$11042 + attribute \src "libresoc.v:178912.3-178947.6" + wire $5\wr_detect$4[0:0]$11010 + attribute \src "libresoc.v:178994.3-179029.6" + wire $5\wr_detect$7[0:0]$11026 + attribute \src "libresoc.v:178830.3-178865.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $6\r1__data_o$next[1:0]$11034 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $6\src11__data_o$next[1:0]$10992 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $6\src21__data_o$next[1:0]$11002 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $6\src31__data_o$next[1:0]$11018 + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $7\r1__data_o$next[1:0]$11035 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $7\src11__data_o$next[1:0]$10993 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $7\src21__data_o$next[1:0]$11003 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $7\src31__data_o$next[1:0]$11019 + attribute \src "libresoc.v:178770.17-178770.104" + wire $not$libresoc.v:178770$10976_Y + attribute \src "libresoc.v:178771.17-178771.100" + wire $not$libresoc.v:178771$10977_Y + attribute \src "libresoc.v:178772.17-178772.103" + wire $not$libresoc.v:178772$10978_Y + attribute \src "libresoc.v:178773.17-178773.103" + wire $not$libresoc.v:178773$10979_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 13 \dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest31__wen + attribute \src "libresoc.v:178701.7-178701.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178770$10976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:178770$10976_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178771$10977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:178771$10977_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178772$10978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:178772$10978_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178773$10979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:178773$10979_Y + end + attribute \src "libresoc.v:178701.7-178701.20" + process $proc$libresoc.v:178701$11050 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178728.13-178728.30" + process $proc$libresoc.v:178728$11051 + assign { } { } + assign $1\r1__data_o[1:0] 2'00 + sync always + sync init + update \r1__data_o $1\r1__data_o[1:0] + end + attribute \src "libresoc.v:178734.13-178734.25" + process $proc$libresoc.v:178734$11052 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:178739.13-178739.33" + process $proc$libresoc.v:178739$11053 + assign { } { } + assign $1\src11__data_o[1:0] 2'00 + sync always + sync init + update \src11__data_o $1\src11__data_o[1:0] + end + attribute \src "libresoc.v:178746.13-178746.33" + process $proc$libresoc.v:178746$11054 + assign { } { } + assign $1\src21__data_o[1:0] 2'00 + sync always + sync init + update \src21__data_o $1\src21__data_o[1:0] + end + attribute \src "libresoc.v:178753.13-178753.33" + process $proc$libresoc.v:178753$11055 + assign { } { } + assign $1\src31__data_o[1:0] 2'00 + sync always + sync init + update \src31__data_o $1\src31__data_o[1:0] + end + attribute \src "libresoc.v:178774.3-178775.25" + process $proc$libresoc.v:178774$10980 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:178776.3-178777.37" + process $proc$libresoc.v:178776$10981 + assign { } { } + assign $0\r1__data_o[1:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[1:0] + end + attribute \src "libresoc.v:178778.3-178779.43" + process $proc$libresoc.v:178778$10982 + assign { } { } + assign $0\src31__data_o[1:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[1:0] + end + attribute \src "libresoc.v:178780.3-178781.43" + process $proc$libresoc.v:178780$10983 + assign { } { } + assign $0\src21__data_o[1:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[1:0] + end + attribute \src "libresoc.v:178782.3-178783.43" + process $proc$libresoc.v:178782$10984 + assign { } { } + assign $0\src11__data_o[1:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[1:0] + end + attribute \src "libresoc.v:178784.3-178829.6" + process $proc$libresoc.v:178784$10985 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[1:0]$10986 $7\src11__data_o$next[1:0]$10993 + attribute \src "libresoc.v:178785.5-178785.29" + switch \initial + attribute \src "libresoc.v:178785.9-178785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[1:0]$10987 $6\src11__data_o$next[1:0]$10992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[1:0]$10988 \dest11__data_i + case + assign $2\src11__data_o$next[1:0]$10988 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[1:0]$10989 \dest21__data_i + case + assign $3\src11__data_o$next[1:0]$10989 $2\src11__data_o$next[1:0]$10988 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[1:0]$10990 \dest31__data_i + case + assign $4\src11__data_o$next[1:0]$10990 $3\src11__data_o$next[1:0]$10989 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[1:0]$10991 \w1__data_i + case + assign $5\src11__data_o$next[1:0]$10991 $4\src11__data_o$next[1:0]$10990 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[1:0]$10992 \reg + case + assign $6\src11__data_o$next[1:0]$10992 $5\src11__data_o$next[1:0]$10991 + end + case + assign $1\src11__data_o$next[1:0]$10987 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src11__data_o$next[1:0]$10993 2'00 + case + assign $7\src11__data_o$next[1:0]$10993 $1\src11__data_o$next[1:0]$10987 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[1:0]$10986 + end + attribute \src "libresoc.v:178830.3-178865.6" + process $proc$libresoc.v:178830$10994 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:178831.5-178831.29" + switch \initial + attribute \src "libresoc.v:178831.9-178831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:178866.3-178911.6" + process $proc$libresoc.v:178866$10995 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[1:0]$10996 $7\src21__data_o$next[1:0]$11003 + attribute \src "libresoc.v:178867.5-178867.29" + switch \initial + attribute \src "libresoc.v:178867.9-178867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[1:0]$10997 $6\src21__data_o$next[1:0]$11002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[1:0]$10998 \dest11__data_i + case + assign $2\src21__data_o$next[1:0]$10998 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[1:0]$10999 \dest21__data_i + case + assign $3\src21__data_o$next[1:0]$10999 $2\src21__data_o$next[1:0]$10998 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[1:0]$11000 \dest31__data_i + case + assign $4\src21__data_o$next[1:0]$11000 $3\src21__data_o$next[1:0]$10999 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[1:0]$11001 \w1__data_i + case + assign $5\src21__data_o$next[1:0]$11001 $4\src21__data_o$next[1:0]$11000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[1:0]$11002 \reg + case + assign $6\src21__data_o$next[1:0]$11002 $5\src21__data_o$next[1:0]$11001 + end + case + assign $1\src21__data_o$next[1:0]$10997 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src21__data_o$next[1:0]$11003 2'00 + case + assign $7\src21__data_o$next[1:0]$11003 $1\src21__data_o$next[1:0]$10997 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[1:0]$10996 + end + attribute \src "libresoc.v:178912.3-178947.6" + process $proc$libresoc.v:178912$11004 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11005 $1\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:178913.5-178913.29" + switch \initial + attribute \src "libresoc.v:178913.9-178913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11006 $5\wr_detect$4[0:0]$11010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11007 1'1 + case + assign $2\wr_detect$4[0:0]$11007 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11008 1'1 + case + assign $3\wr_detect$4[0:0]$11008 $2\wr_detect$4[0:0]$11007 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11009 1'1 + case + assign $4\wr_detect$4[0:0]$11009 $3\wr_detect$4[0:0]$11008 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11010 1'1 + case + assign $5\wr_detect$4[0:0]$11010 $4\wr_detect$4[0:0]$11009 + end + case + assign $1\wr_detect$4[0:0]$11006 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11005 + end + attribute \src "libresoc.v:178948.3-178993.6" + process $proc$libresoc.v:178948$11011 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[1:0]$11012 $7\src31__data_o$next[1:0]$11019 + attribute \src "libresoc.v:178949.5-178949.29" + switch \initial + attribute \src "libresoc.v:178949.9-178949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[1:0]$11013 $6\src31__data_o$next[1:0]$11018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[1:0]$11014 \dest11__data_i + case + assign $2\src31__data_o$next[1:0]$11014 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[1:0]$11015 \dest21__data_i + case + assign $3\src31__data_o$next[1:0]$11015 $2\src31__data_o$next[1:0]$11014 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[1:0]$11016 \dest31__data_i + case + assign $4\src31__data_o$next[1:0]$11016 $3\src31__data_o$next[1:0]$11015 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[1:0]$11017 \w1__data_i + case + assign $5\src31__data_o$next[1:0]$11017 $4\src31__data_o$next[1:0]$11016 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[1:0]$11018 \reg + case + assign $6\src31__data_o$next[1:0]$11018 $5\src31__data_o$next[1:0]$11017 + end + case + assign $1\src31__data_o$next[1:0]$11013 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src31__data_o$next[1:0]$11019 2'00 + case + assign $7\src31__data_o$next[1:0]$11019 $1\src31__data_o$next[1:0]$11013 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[1:0]$11012 + end + attribute \src "libresoc.v:178994.3-179029.6" + process $proc$libresoc.v:178994$11020 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11021 $1\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:178995.5-178995.29" + switch \initial + attribute \src "libresoc.v:178995.9-178995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11022 $5\wr_detect$7[0:0]$11026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11023 1'1 + case + assign $2\wr_detect$7[0:0]$11023 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11024 1'1 + case + assign $3\wr_detect$7[0:0]$11024 $2\wr_detect$7[0:0]$11023 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11025 1'1 + case + assign $4\wr_detect$7[0:0]$11025 $3\wr_detect$7[0:0]$11024 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11026 1'1 + case + assign $5\wr_detect$7[0:0]$11026 $4\wr_detect$7[0:0]$11025 + end + case + assign $1\wr_detect$7[0:0]$11022 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11021 + end + attribute \src "libresoc.v:179030.3-179075.6" + process $proc$libresoc.v:179030$11027 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[1:0]$11028 $7\r1__data_o$next[1:0]$11035 + attribute \src "libresoc.v:179031.5-179031.29" + switch \initial + attribute \src "libresoc.v:179031.9-179031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[1:0]$11029 $6\r1__data_o$next[1:0]$11034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[1:0]$11030 \dest11__data_i + case + assign $2\r1__data_o$next[1:0]$11030 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[1:0]$11031 \dest21__data_i + case + assign $3\r1__data_o$next[1:0]$11031 $2\r1__data_o$next[1:0]$11030 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[1:0]$11032 \dest31__data_i + case + assign $4\r1__data_o$next[1:0]$11032 $3\r1__data_o$next[1:0]$11031 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[1:0]$11033 \w1__data_i + case + assign $5\r1__data_o$next[1:0]$11033 $4\r1__data_o$next[1:0]$11032 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[1:0]$11034 \reg + case + assign $6\r1__data_o$next[1:0]$11034 $5\r1__data_o$next[1:0]$11033 + end + case + assign $1\r1__data_o$next[1:0]$11029 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r1__data_o$next[1:0]$11035 2'00 + case + assign $7\r1__data_o$next[1:0]$11035 $1\r1__data_o$next[1:0]$11029 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[1:0]$11028 + end + attribute \src "libresoc.v:179076.3-179111.6" + process $proc$libresoc.v:179076$11036 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11037 $1\wr_detect$10[0:0]$11038 + attribute \src "libresoc.v:179077.5-179077.29" + switch \initial + attribute \src "libresoc.v:179077.9-179077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11038 $5\wr_detect$10[0:0]$11042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11039 1'1 + case + assign $2\wr_detect$10[0:0]$11039 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11040 1'1 + case + assign $3\wr_detect$10[0:0]$11040 $2\wr_detect$10[0:0]$11039 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11041 1'1 + case + assign $4\wr_detect$10[0:0]$11041 $3\wr_detect$10[0:0]$11040 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11042 1'1 + case + assign $5\wr_detect$10[0:0]$11042 $4\wr_detect$10[0:0]$11041 + end + case + assign $1\wr_detect$10[0:0]$11038 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11037 + end + attribute \src "libresoc.v:179112.3-179144.6" + process $proc$libresoc.v:179112$11043 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11044 $5\reg$next[1:0]$11049 + attribute \src "libresoc.v:179113.5-179113.29" + switch \initial + attribute \src "libresoc.v:179113.9-179113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11045 \dest11__data_i + case + assign $1\reg$next[1:0]$11045 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11046 \dest21__data_i + case + assign $2\reg$next[1:0]$11046 $1\reg$next[1:0]$11045 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11047 \dest31__data_i + case + assign $3\reg$next[1:0]$11047 $2\reg$next[1:0]$11046 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11048 \w1__data_i + case + assign $4\reg$next[1:0]$11048 $3\reg$next[1:0]$11047 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11049 2'00 + case + assign $5\reg$next[1:0]$11049 $4\reg$next[1:0]$11048 + end + sync always + update \reg$next $0\reg$next[1:0]$11044 + end + connect \$9 $not$libresoc.v:178770$10976_Y + connect \$1 $not$libresoc.v:178771$10977_Y + connect \$3 $not$libresoc.v:178772$10978_Y + connect \$6 $not$libresoc.v:178773$10979_Y +end +attribute \src "libresoc.v:179149.1-179498.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" +attribute \generator "nMigen" +module \reg_1$136 + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $0\cia1__data_o$next[63:0]$11064 + attribute \src "libresoc.v:179217.3-179218.41" + wire width 64 $0\cia1__data_o[63:0] + attribute \src "libresoc.v:179150.7-179150.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $0\msr1__data_o$next[63:0]$11074 + attribute \src "libresoc.v:179215.3-179216.41" + wire width 64 $0\msr1__data_o[63:0] + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $0\reg$next[63:0]$11106 + attribute \src "libresoc.v:179211.3-179212.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $0\sv1__data_o$next[63:0]$11090 + attribute \src "libresoc.v:179213.3-179214.39" + wire width 64 $0\sv1__data_o[63:0] + attribute \src "libresoc.v:179347.3-179382.6" + wire $0\wr_detect$4[0:0]$11083 + attribute \src "libresoc.v:179429.3-179464.6" + wire $0\wr_detect$7[0:0]$11099 + attribute \src "libresoc.v:179265.3-179300.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $1\cia1__data_o$next[63:0]$11065 + attribute \src "libresoc.v:179159.14-179159.49" + wire width 64 $1\cia1__data_o[63:0] + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $1\msr1__data_o$next[63:0]$11075 + attribute \src "libresoc.v:179176.14-179176.49" + wire width 64 $1\msr1__data_o[63:0] + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $1\reg$next[63:0]$11107 + attribute \src "libresoc.v:179188.14-179188.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $1\sv1__data_o$next[63:0]$11091 + attribute \src "libresoc.v:179195.14-179195.48" + wire width 64 $1\sv1__data_o[63:0] + attribute \src "libresoc.v:179347.3-179382.6" + wire $1\wr_detect$4[0:0]$11084 + attribute \src "libresoc.v:179429.3-179464.6" + wire $1\wr_detect$7[0:0]$11100 + attribute \src "libresoc.v:179265.3-179300.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $2\cia1__data_o$next[63:0]$11066 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $2\msr1__data_o$next[63:0]$11076 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $2\reg$next[63:0]$11108 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $2\sv1__data_o$next[63:0]$11092 + attribute \src "libresoc.v:179347.3-179382.6" + wire $2\wr_detect$4[0:0]$11085 + attribute \src "libresoc.v:179429.3-179464.6" + wire $2\wr_detect$7[0:0]$11101 + attribute \src "libresoc.v:179265.3-179300.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $3\cia1__data_o$next[63:0]$11067 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $3\msr1__data_o$next[63:0]$11077 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $3\reg$next[63:0]$11109 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $3\sv1__data_o$next[63:0]$11093 + attribute \src "libresoc.v:179347.3-179382.6" + wire $3\wr_detect$4[0:0]$11086 + attribute \src "libresoc.v:179429.3-179464.6" + wire $3\wr_detect$7[0:0]$11102 + attribute \src "libresoc.v:179265.3-179300.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $4\cia1__data_o$next[63:0]$11068 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $4\msr1__data_o$next[63:0]$11078 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $4\reg$next[63:0]$11110 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $4\sv1__data_o$next[63:0]$11094 + attribute \src "libresoc.v:179347.3-179382.6" + wire $4\wr_detect$4[0:0]$11087 + attribute \src "libresoc.v:179429.3-179464.6" + wire $4\wr_detect$7[0:0]$11103 + attribute \src "libresoc.v:179265.3-179300.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $5\cia1__data_o$next[63:0]$11069 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $5\msr1__data_o$next[63:0]$11079 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $5\reg$next[63:0]$11111 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $5\sv1__data_o$next[63:0]$11095 + attribute \src "libresoc.v:179347.3-179382.6" + wire $5\wr_detect$4[0:0]$11088 + attribute \src "libresoc.v:179429.3-179464.6" + wire $5\wr_detect$7[0:0]$11104 + attribute \src "libresoc.v:179265.3-179300.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $6\cia1__data_o$next[63:0]$11070 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $6\msr1__data_o$next[63:0]$11080 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $6\sv1__data_o$next[63:0]$11096 + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $7\cia1__data_o$next[63:0]$11071 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $7\msr1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $7\sv1__data_o$next[63:0]$11097 + attribute \src "libresoc.v:179208.17-179208.100" + wire $not$libresoc.v:179208$11056_Y + attribute \src "libresoc.v:179209.17-179209.103" + wire $not$libresoc.v:179209$11057_Y + attribute \src "libresoc.v:179210.17-179210.103" + wire $not$libresoc.v:179210$11058_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr11__wen + attribute \src "libresoc.v:179150.7-179150.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179208$11056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:179208$11056_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179209$11057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:179209$11057_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179210$11058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:179210$11058_Y + end + attribute \src "libresoc.v:179150.7-179150.20" + process $proc$libresoc.v:179150$11112 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:179159.14-179159.49" + process $proc$libresoc.v:179159$11113 + assign { } { } + assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia1__data_o $1\cia1__data_o[63:0] + end + attribute \src "libresoc.v:179176.14-179176.49" + process $proc$libresoc.v:179176$11114 + assign { } { } + assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr1__data_o $1\msr1__data_o[63:0] + end + attribute \src "libresoc.v:179188.14-179188.42" + process $proc$libresoc.v:179188$11115 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:179195.14-179195.48" + process $proc$libresoc.v:179195$11116 + assign { } { } + assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv1__data_o $1\sv1__data_o[63:0] + end + attribute \src "libresoc.v:179211.3-179212.25" + process $proc$libresoc.v:179211$11059 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:179213.3-179214.39" + process $proc$libresoc.v:179213$11060 + assign { } { } + assign $0\sv1__data_o[63:0] \sv1__data_o$next + sync posedge \coresync_clk + update \sv1__data_o $0\sv1__data_o[63:0] + end + attribute \src "libresoc.v:179215.3-179216.41" + process $proc$libresoc.v:179215$11061 + assign { } { } + assign $0\msr1__data_o[63:0] \msr1__data_o$next + sync posedge \coresync_clk + update \msr1__data_o $0\msr1__data_o[63:0] + end + attribute \src "libresoc.v:179217.3-179218.41" + process $proc$libresoc.v:179217$11062 + assign { } { } + assign $0\cia1__data_o[63:0] \cia1__data_o$next + sync posedge \coresync_clk + update \cia1__data_o $0\cia1__data_o[63:0] + end + attribute \src "libresoc.v:179219.3-179264.6" + process $proc$libresoc.v:179219$11063 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia1__data_o$next[63:0]$11064 $7\cia1__data_o$next[63:0]$11071 + attribute \src "libresoc.v:179220.5-179220.29" + switch \initial + attribute \src "libresoc.v:179220.9-179220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia1__data_o$next[63:0]$11065 $6\cia1__data_o$next[63:0]$11070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia1__data_o$next[63:0]$11066 \nia1__data_i + case + assign $2\cia1__data_o$next[63:0]$11066 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia1__data_o$next[63:0]$11067 \msr1__data_i + case + assign $3\cia1__data_o$next[63:0]$11067 $2\cia1__data_o$next[63:0]$11066 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia1__data_o$next[63:0]$11068 \sv1__data_i + case + assign $4\cia1__data_o$next[63:0]$11068 $3\cia1__data_o$next[63:0]$11067 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia1__data_o$next[63:0]$11069 \d_wr11__data_i + case + assign $5\cia1__data_o$next[63:0]$11069 $4\cia1__data_o$next[63:0]$11068 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia1__data_o$next[63:0]$11070 \reg + case + assign $6\cia1__data_o$next[63:0]$11070 $5\cia1__data_o$next[63:0]$11069 + end + case + assign $1\cia1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia1__data_o$next[63:0]$11071 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia1__data_o$next[63:0]$11071 $1\cia1__data_o$next[63:0]$11065 + end + sync always + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11064 + end + attribute \src "libresoc.v:179265.3-179300.6" + process $proc$libresoc.v:179265$11072 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:179266.5-179266.29" + switch \initial + attribute \src "libresoc.v:179266.9-179266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:179301.3-179346.6" + process $proc$libresoc.v:179301$11073 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr1__data_o$next[63:0]$11074 $7\msr1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:179302.5-179302.29" + switch \initial + attribute \src "libresoc.v:179302.9-179302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr1__data_o$next[63:0]$11075 $6\msr1__data_o$next[63:0]$11080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr1__data_o$next[63:0]$11076 \nia1__data_i + case + assign $2\msr1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr1__data_o$next[63:0]$11077 \msr1__data_i + case + assign $3\msr1__data_o$next[63:0]$11077 $2\msr1__data_o$next[63:0]$11076 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr1__data_o$next[63:0]$11078 \sv1__data_i + case + assign $4\msr1__data_o$next[63:0]$11078 $3\msr1__data_o$next[63:0]$11077 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr1__data_o$next[63:0]$11079 \d_wr11__data_i + case + assign $5\msr1__data_o$next[63:0]$11079 $4\msr1__data_o$next[63:0]$11078 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr1__data_o$next[63:0]$11080 \reg + case + assign $6\msr1__data_o$next[63:0]$11080 $5\msr1__data_o$next[63:0]$11079 + end + case + assign $1\msr1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\msr1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\msr1__data_o$next[63:0]$11081 $1\msr1__data_o$next[63:0]$11075 + end + sync always + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11074 + end + attribute \src "libresoc.v:179347.3-179382.6" + process $proc$libresoc.v:179347$11082 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11083 $1\wr_detect$4[0:0]$11084 + attribute \src "libresoc.v:179348.5-179348.29" + switch \initial + attribute \src "libresoc.v:179348.9-179348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11084 $5\wr_detect$4[0:0]$11088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11085 1'1 + case + assign $2\wr_detect$4[0:0]$11085 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11086 1'1 + case + assign $3\wr_detect$4[0:0]$11086 $2\wr_detect$4[0:0]$11085 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11087 1'1 + case + assign $4\wr_detect$4[0:0]$11087 $3\wr_detect$4[0:0]$11086 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11088 1'1 + case + assign $5\wr_detect$4[0:0]$11088 $4\wr_detect$4[0:0]$11087 + end + case + assign $1\wr_detect$4[0:0]$11084 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11083 + end + attribute \src "libresoc.v:179383.3-179428.6" + process $proc$libresoc.v:179383$11089 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv1__data_o$next[63:0]$11090 $7\sv1__data_o$next[63:0]$11097 + attribute \src "libresoc.v:179384.5-179384.29" + switch \initial + attribute \src "libresoc.v:179384.9-179384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv1__data_o$next[63:0]$11091 $6\sv1__data_o$next[63:0]$11096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv1__data_o$next[63:0]$11092 \nia1__data_i + case + assign $2\sv1__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv1__data_o$next[63:0]$11093 \msr1__data_i + case + assign $3\sv1__data_o$next[63:0]$11093 $2\sv1__data_o$next[63:0]$11092 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv1__data_o$next[63:0]$11094 \sv1__data_i + case + assign $4\sv1__data_o$next[63:0]$11094 $3\sv1__data_o$next[63:0]$11093 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv1__data_o$next[63:0]$11095 \d_wr11__data_i + case + assign $5\sv1__data_o$next[63:0]$11095 $4\sv1__data_o$next[63:0]$11094 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv1__data_o$next[63:0]$11096 \reg + case + assign $6\sv1__data_o$next[63:0]$11096 $5\sv1__data_o$next[63:0]$11095 + end + case + assign $1\sv1__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv1__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv1__data_o$next[63:0]$11097 $1\sv1__data_o$next[63:0]$11091 + end + sync always + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11090 + end + attribute \src "libresoc.v:179429.3-179464.6" + process $proc$libresoc.v:179429$11098 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11099 $1\wr_detect$7[0:0]$11100 + attribute \src "libresoc.v:179430.5-179430.29" + switch \initial + attribute \src "libresoc.v:179430.9-179430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11100 $5\wr_detect$7[0:0]$11104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11101 1'1 + case + assign $2\wr_detect$7[0:0]$11101 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11102 1'1 + case + assign $3\wr_detect$7[0:0]$11102 $2\wr_detect$7[0:0]$11101 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11103 1'1 + case + assign $4\wr_detect$7[0:0]$11103 $3\wr_detect$7[0:0]$11102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11104 1'1 + case + assign $5\wr_detect$7[0:0]$11104 $4\wr_detect$7[0:0]$11103 + end + case + assign $1\wr_detect$7[0:0]$11100 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11099 + end + attribute \src "libresoc.v:179465.3-179497.6" + process $proc$libresoc.v:179465$11105 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11106 $5\reg$next[63:0]$11111 + attribute \src "libresoc.v:179466.5-179466.29" + switch \initial + attribute \src "libresoc.v:179466.9-179466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11107 \nia1__data_i + case + assign $1\reg$next[63:0]$11107 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11108 \msr1__data_i + case + assign $2\reg$next[63:0]$11108 $1\reg$next[63:0]$11107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11109 \sv1__data_i + case + assign $3\reg$next[63:0]$11109 $2\reg$next[63:0]$11108 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11110 \d_wr11__data_i + case + assign $4\reg$next[63:0]$11110 $3\reg$next[63:0]$11109 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[63:0]$11111 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $5\reg$next[63:0]$11111 $4\reg$next[63:0]$11110 + end + sync always + update \reg$next $0\reg$next[63:0]$11106 + end + connect \$1 $not$libresoc.v:179208$11056_Y + connect \$3 $not$libresoc.v:179209$11057_Y + connect \$6 $not$libresoc.v:179210$11058_Y +end +attribute \src "libresoc.v:179502.1-180057.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" +attribute \generator "nMigen" +module \reg_2 + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $0\cr_pred2__data_o$next[3:0]$11131 + attribute \src "libresoc.v:179608.3-179609.49" + wire width 4 $0\cr_pred2__data_o[3:0] + attribute \src "libresoc.v:179503.7-179503.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $0\r22__data_o$next[3:0]$11140 + attribute \src "libresoc.v:179598.3-179599.39" + wire width 4 $0\r22__data_o[3:0] + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $0\r2__data_o$next[3:0]$11202 + attribute \src "libresoc.v:179600.3-179601.37" + wire width 4 $0\r2__data_o[3:0] + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $0\reg$next[3:0]$11154 + attribute \src "libresoc.v:179596.3-179597.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $0\src12__data_o$next[3:0]$11160 + attribute \src "libresoc.v:179606.3-179607.43" + wire width 4 $0\src12__data_o[3:0] + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $0\src22__data_o$next[3:0]$11174 + attribute \src "libresoc.v:179604.3-179605.43" + wire width 4 $0\src22__data_o[3:0] + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $0\src32__data_o$next[3:0]$11188 + attribute \src "libresoc.v:179602.3-179603.43" + wire width 4 $0\src32__data_o[3:0] + attribute \src "libresoc.v:179957.3-179986.6" + wire $0\wr_detect$10[0:0]$11196 + attribute \src "libresoc.v:180027.3-180056.6" + wire $0\wr_detect$13[0:0]$11210 + attribute \src "libresoc.v:179720.3-179749.6" + wire $0\wr_detect$16[0:0]$11148 + attribute \src "libresoc.v:179817.3-179846.6" + wire $0\wr_detect$4[0:0]$11168 + attribute \src "libresoc.v:179887.3-179916.6" + wire $0\wr_detect$7[0:0]$11182 + attribute \src "libresoc.v:179650.3-179679.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $1\cr_pred2__data_o$next[3:0]$11132 + attribute \src "libresoc.v:179522.13-179522.36" + wire width 4 $1\cr_pred2__data_o[3:0] + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $1\r22__data_o$next[3:0]$11141 + attribute \src "libresoc.v:179537.13-179537.31" + wire width 4 $1\r22__data_o[3:0] + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $1\r2__data_o$next[3:0]$11203 + attribute \src "libresoc.v:179544.13-179544.30" + wire width 4 $1\r2__data_o[3:0] + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $1\reg$next[3:0]$11155 + attribute \src "libresoc.v:179550.13-179550.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $1\src12__data_o$next[3:0]$11161 + attribute \src "libresoc.v:179555.13-179555.33" + wire width 4 $1\src12__data_o[3:0] + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $1\src22__data_o$next[3:0]$11175 + attribute \src "libresoc.v:179562.13-179562.33" + wire width 4 $1\src22__data_o[3:0] + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $1\src32__data_o$next[3:0]$11189 + attribute \src "libresoc.v:179569.13-179569.33" + wire width 4 $1\src32__data_o[3:0] + attribute \src "libresoc.v:179957.3-179986.6" + wire $1\wr_detect$10[0:0]$11197 + attribute \src "libresoc.v:180027.3-180056.6" + wire $1\wr_detect$13[0:0]$11211 + attribute \src "libresoc.v:179720.3-179749.6" + wire $1\wr_detect$16[0:0]$11149 + attribute \src "libresoc.v:179817.3-179846.6" + wire $1\wr_detect$4[0:0]$11169 + attribute \src "libresoc.v:179887.3-179916.6" + wire $1\wr_detect$7[0:0]$11183 + attribute \src "libresoc.v:179650.3-179679.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $2\cr_pred2__data_o$next[3:0]$11133 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $2\r22__data_o$next[3:0]$11142 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $2\r2__data_o$next[3:0]$11204 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $2\reg$next[3:0]$11156 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $2\src12__data_o$next[3:0]$11162 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $2\src22__data_o$next[3:0]$11176 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $2\src32__data_o$next[3:0]$11190 + attribute \src "libresoc.v:179957.3-179986.6" + wire $2\wr_detect$10[0:0]$11198 + attribute \src "libresoc.v:180027.3-180056.6" + wire $2\wr_detect$13[0:0]$11212 + attribute \src "libresoc.v:179720.3-179749.6" + wire $2\wr_detect$16[0:0]$11150 + attribute \src "libresoc.v:179817.3-179846.6" + wire $2\wr_detect$4[0:0]$11170 + attribute \src "libresoc.v:179887.3-179916.6" + wire $2\wr_detect$7[0:0]$11184 + attribute \src "libresoc.v:179650.3-179679.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $3\cr_pred2__data_o$next[3:0]$11134 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $3\r22__data_o$next[3:0]$11143 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $3\r2__data_o$next[3:0]$11205 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $3\reg$next[3:0]$11157 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $3\src12__data_o$next[3:0]$11163 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $3\src22__data_o$next[3:0]$11177 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $3\src32__data_o$next[3:0]$11191 + attribute \src "libresoc.v:179957.3-179986.6" + wire $3\wr_detect$10[0:0]$11199 + attribute \src "libresoc.v:180027.3-180056.6" + wire $3\wr_detect$13[0:0]$11213 + attribute \src "libresoc.v:179720.3-179749.6" + wire $3\wr_detect$16[0:0]$11151 + attribute \src "libresoc.v:179817.3-179846.6" + wire $3\wr_detect$4[0:0]$11171 + attribute \src "libresoc.v:179887.3-179916.6" + wire $3\wr_detect$7[0:0]$11185 + attribute \src "libresoc.v:179650.3-179679.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $4\cr_pred2__data_o$next[3:0]$11135 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $4\r22__data_o$next[3:0]$11144 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $4\r2__data_o$next[3:0]$11206 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $4\reg$next[3:0]$11158 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $4\src12__data_o$next[3:0]$11164 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $4\src22__data_o$next[3:0]$11178 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $4\src32__data_o$next[3:0]$11192 + attribute \src "libresoc.v:179957.3-179986.6" + wire $4\wr_detect$10[0:0]$11200 + attribute \src "libresoc.v:180027.3-180056.6" + wire $4\wr_detect$13[0:0]$11214 + attribute \src "libresoc.v:179720.3-179749.6" + wire $4\wr_detect$16[0:0]$11152 + attribute \src "libresoc.v:179817.3-179846.6" + wire $4\wr_detect$4[0:0]$11172 + attribute \src "libresoc.v:179887.3-179916.6" + wire $4\wr_detect$7[0:0]$11186 + attribute \src "libresoc.v:179650.3-179679.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $5\cr_pred2__data_o$next[3:0]$11136 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $5\r22__data_o$next[3:0]$11145 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $5\r2__data_o$next[3:0]$11207 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $5\src12__data_o$next[3:0]$11165 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $5\src22__data_o$next[3:0]$11179 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $5\src32__data_o$next[3:0]$11193 + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $6\cr_pred2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $6\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $6\r2__data_o$next[3:0]$11208 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $6\src12__data_o$next[3:0]$11166 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $6\src22__data_o$next[3:0]$11180 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $6\src32__data_o$next[3:0]$11194 + attribute \src "libresoc.v:179590.17-179590.104" + wire $not$libresoc.v:179590$11117_Y + attribute \src "libresoc.v:179591.18-179591.105" + wire $not$libresoc.v:179591$11118_Y + attribute \src "libresoc.v:179592.18-179592.105" + wire $not$libresoc.v:179592$11119_Y + attribute \src "libresoc.v:179593.17-179593.100" + wire $not$libresoc.v:179593$11120_Y + attribute \src "libresoc.v:179594.17-179594.103" + wire $not$libresoc.v:179594$11121_Y + attribute \src "libresoc.v:179595.17-179595.103" + wire $not$libresoc.v:179595$11122_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest22__wen + attribute \src "libresoc.v:179503.7-179503.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179590$11117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:179590$11117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179591$11118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:179591$11118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179592$11119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:179592$11119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179593$11120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:179593$11120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179594$11121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:179594$11121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179595$11122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:179595$11122_Y + end + attribute \src "libresoc.v:179503.7-179503.20" + process $proc$libresoc.v:179503$11215 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:179522.13-179522.36" + process $proc$libresoc.v:179522$11216 + assign { } { } + assign $1\cr_pred2__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred2__data_o $1\cr_pred2__data_o[3:0] + end + attribute \src "libresoc.v:179537.13-179537.31" + process $proc$libresoc.v:179537$11217 + assign { } { } + assign $1\r22__data_o[3:0] 4'0000 + sync always + sync init + update \r22__data_o $1\r22__data_o[3:0] + end + attribute \src "libresoc.v:179544.13-179544.30" + process $proc$libresoc.v:179544$11218 + assign { } { } + assign $1\r2__data_o[3:0] 4'0000 + sync always + sync init + update \r2__data_o $1\r2__data_o[3:0] + end + attribute \src "libresoc.v:179550.13-179550.25" + process $proc$libresoc.v:179550$11219 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:179555.13-179555.33" + process $proc$libresoc.v:179555$11220 + assign { } { } + assign $1\src12__data_o[3:0] 4'0000 + sync always + sync init + update \src12__data_o $1\src12__data_o[3:0] + end + attribute \src "libresoc.v:179562.13-179562.33" + process $proc$libresoc.v:179562$11221 + assign { } { } + assign $1\src22__data_o[3:0] 4'0000 + sync always + sync init + update \src22__data_o $1\src22__data_o[3:0] + end + attribute \src "libresoc.v:179569.13-179569.33" + process $proc$libresoc.v:179569$11222 + assign { } { } + assign $1\src32__data_o[3:0] 4'0000 + sync always + sync init + update \src32__data_o $1\src32__data_o[3:0] + end + attribute \src "libresoc.v:179596.3-179597.25" + process $proc$libresoc.v:179596$11123 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:179598.3-179599.39" + process $proc$libresoc.v:179598$11124 + assign { } { } + assign $0\r22__data_o[3:0] \r22__data_o$next + sync posedge \coresync_clk + update \r22__data_o $0\r22__data_o[3:0] + end + attribute \src "libresoc.v:179600.3-179601.37" + process $proc$libresoc.v:179600$11125 + assign { } { } + assign $0\r2__data_o[3:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[3:0] + end + attribute \src "libresoc.v:179602.3-179603.43" + process $proc$libresoc.v:179602$11126 + assign { } { } + assign $0\src32__data_o[3:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[3:0] + end + attribute \src "libresoc.v:179604.3-179605.43" + process $proc$libresoc.v:179604$11127 + assign { } { } + assign $0\src22__data_o[3:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[3:0] + end + attribute \src "libresoc.v:179606.3-179607.43" + process $proc$libresoc.v:179606$11128 + assign { } { } + assign $0\src12__data_o[3:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[3:0] + end + attribute \src "libresoc.v:179608.3-179609.49" + process $proc$libresoc.v:179608$11129 + assign { } { } + assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next + sync posedge \coresync_clk + update \cr_pred2__data_o $0\cr_pred2__data_o[3:0] + end + attribute \src "libresoc.v:179610.3-179649.6" + process $proc$libresoc.v:179610$11130 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred2__data_o$next[3:0]$11131 $6\cr_pred2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:179611.5-179611.29" + switch \initial + attribute \src "libresoc.v:179611.9-179611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred2__data_o$next[3:0]$11132 $5\cr_pred2__data_o$next[3:0]$11136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred2__data_o$next[3:0]$11133 \dest12__data_i + case + assign $2\cr_pred2__data_o$next[3:0]$11133 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred2__data_o$next[3:0]$11134 \dest22__data_i + case + assign $3\cr_pred2__data_o$next[3:0]$11134 $2\cr_pred2__data_o$next[3:0]$11133 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred2__data_o$next[3:0]$11135 \w2__data_i + case + assign $4\cr_pred2__data_o$next[3:0]$11135 $3\cr_pred2__data_o$next[3:0]$11134 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred2__data_o$next[3:0]$11136 \reg + case + assign $5\cr_pred2__data_o$next[3:0]$11136 $4\cr_pred2__data_o$next[3:0]$11135 + end + case + assign $1\cr_pred2__data_o$next[3:0]$11132 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred2__data_o$next[3:0]$11137 4'0000 + case + assign $6\cr_pred2__data_o$next[3:0]$11137 $1\cr_pred2__data_o$next[3:0]$11132 + end + sync always + update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11131 + end + attribute \src "libresoc.v:179650.3-179679.6" + process $proc$libresoc.v:179650$11138 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:179651.5-179651.29" + switch \initial + attribute \src "libresoc.v:179651.9-179651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:179680.3-179719.6" + process $proc$libresoc.v:179680$11139 + assign { } { } + assign { } { } + assign { } { } + assign $0\r22__data_o$next[3:0]$11140 $6\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:179681.5-179681.29" + switch \initial + attribute \src "libresoc.v:179681.9-179681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r22__data_o$next[3:0]$11141 $5\r22__data_o$next[3:0]$11145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$11142 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$11142 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$11143 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$11143 $2\r22__data_o$next[3:0]$11142 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$11144 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$11144 $3\r22__data_o$next[3:0]$11143 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$11145 \reg + case + assign $5\r22__data_o$next[3:0]$11145 $4\r22__data_o$next[3:0]$11144 + end + case + assign $1\r22__data_o$next[3:0]$11141 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r22__data_o$next[3:0]$11146 4'0000 + case + assign $6\r22__data_o$next[3:0]$11146 $1\r22__data_o$next[3:0]$11141 + end + sync always + update \r22__data_o$next $0\r22__data_o$next[3:0]$11140 + end + attribute \src "libresoc.v:179720.3-179749.6" + process $proc$libresoc.v:179720$11147 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11148 $1\wr_detect$16[0:0]$11149 + attribute \src "libresoc.v:179721.5-179721.29" + switch \initial + attribute \src "libresoc.v:179721.9-179721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11149 $4\wr_detect$16[0:0]$11152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11150 1'1 + case + assign $2\wr_detect$16[0:0]$11150 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11151 1'1 + case + assign $3\wr_detect$16[0:0]$11151 $2\wr_detect$16[0:0]$11150 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11152 1'1 + case + assign $4\wr_detect$16[0:0]$11152 $3\wr_detect$16[0:0]$11151 + end + case + assign $1\wr_detect$16[0:0]$11149 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11148 + end + attribute \src "libresoc.v:179750.3-179776.6" + process $proc$libresoc.v:179750$11153 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11154 $4\reg$next[3:0]$11158 + attribute \src "libresoc.v:179751.5-179751.29" + switch \initial + attribute \src "libresoc.v:179751.9-179751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11155 \dest12__data_i + case + assign $1\reg$next[3:0]$11155 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11156 \dest22__data_i + case + assign $2\reg$next[3:0]$11156 $1\reg$next[3:0]$11155 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11157 \w2__data_i + case + assign $3\reg$next[3:0]$11157 $2\reg$next[3:0]$11156 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11158 4'0000 + case + assign $4\reg$next[3:0]$11158 $3\reg$next[3:0]$11157 + end + sync always + update \reg$next $0\reg$next[3:0]$11154 + end + attribute \src "libresoc.v:179777.3-179816.6" + process $proc$libresoc.v:179777$11159 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$11160 $6\src12__data_o$next[3:0]$11166 + attribute \src "libresoc.v:179778.5-179778.29" + switch \initial + attribute \src "libresoc.v:179778.9-179778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$11161 $5\src12__data_o$next[3:0]$11165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$11162 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$11162 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$11163 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$11163 $2\src12__data_o$next[3:0]$11162 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$11164 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$11164 $3\src12__data_o$next[3:0]$11163 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[3:0]$11165 \reg + case + assign $5\src12__data_o$next[3:0]$11165 $4\src12__data_o$next[3:0]$11164 + end + case + assign $1\src12__data_o$next[3:0]$11161 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[3:0]$11166 4'0000 + case + assign $6\src12__data_o$next[3:0]$11166 $1\src12__data_o$next[3:0]$11161 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[3:0]$11160 + end + attribute \src "libresoc.v:179817.3-179846.6" + process $proc$libresoc.v:179817$11167 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11168 $1\wr_detect$4[0:0]$11169 + attribute \src "libresoc.v:179818.5-179818.29" + switch \initial + attribute \src "libresoc.v:179818.9-179818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11169 $4\wr_detect$4[0:0]$11172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11170 1'1 + case + assign $2\wr_detect$4[0:0]$11170 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11171 1'1 + case + assign $3\wr_detect$4[0:0]$11171 $2\wr_detect$4[0:0]$11170 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11172 1'1 + case + assign $4\wr_detect$4[0:0]$11172 $3\wr_detect$4[0:0]$11171 + end + case + assign $1\wr_detect$4[0:0]$11169 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11168 + end + attribute \src "libresoc.v:179847.3-179886.6" + process $proc$libresoc.v:179847$11173 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[3:0]$11174 $6\src22__data_o$next[3:0]$11180 + attribute \src "libresoc.v:179848.5-179848.29" + switch \initial + attribute \src "libresoc.v:179848.9-179848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[3:0]$11175 $5\src22__data_o$next[3:0]$11179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[3:0]$11176 \dest12__data_i + case + assign $2\src22__data_o$next[3:0]$11176 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[3:0]$11177 \dest22__data_i + case + assign $3\src22__data_o$next[3:0]$11177 $2\src22__data_o$next[3:0]$11176 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[3:0]$11178 \w2__data_i + case + assign $4\src22__data_o$next[3:0]$11178 $3\src22__data_o$next[3:0]$11177 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[3:0]$11179 \reg + case + assign $5\src22__data_o$next[3:0]$11179 $4\src22__data_o$next[3:0]$11178 + end + case + assign $1\src22__data_o$next[3:0]$11175 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[3:0]$11180 4'0000 + case + assign $6\src22__data_o$next[3:0]$11180 $1\src22__data_o$next[3:0]$11175 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[3:0]$11174 + end + attribute \src "libresoc.v:179887.3-179916.6" + process $proc$libresoc.v:179887$11181 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11182 $1\wr_detect$7[0:0]$11183 + attribute \src "libresoc.v:179888.5-179888.29" + switch \initial + attribute \src "libresoc.v:179888.9-179888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11183 $4\wr_detect$7[0:0]$11186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11184 1'1 + case + assign $2\wr_detect$7[0:0]$11184 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11185 1'1 + case + assign $3\wr_detect$7[0:0]$11185 $2\wr_detect$7[0:0]$11184 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11186 1'1 + case + assign $4\wr_detect$7[0:0]$11186 $3\wr_detect$7[0:0]$11185 + end + case + assign $1\wr_detect$7[0:0]$11183 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11182 + end + attribute \src "libresoc.v:179917.3-179956.6" + process $proc$libresoc.v:179917$11187 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[3:0]$11188 $6\src32__data_o$next[3:0]$11194 + attribute \src "libresoc.v:179918.5-179918.29" + switch \initial + attribute \src "libresoc.v:179918.9-179918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[3:0]$11189 $5\src32__data_o$next[3:0]$11193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[3:0]$11190 \dest12__data_i + case + assign $2\src32__data_o$next[3:0]$11190 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[3:0]$11191 \dest22__data_i + case + assign $3\src32__data_o$next[3:0]$11191 $2\src32__data_o$next[3:0]$11190 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[3:0]$11192 \w2__data_i + case + assign $4\src32__data_o$next[3:0]$11192 $3\src32__data_o$next[3:0]$11191 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[3:0]$11193 \reg + case + assign $5\src32__data_o$next[3:0]$11193 $4\src32__data_o$next[3:0]$11192 + end + case + assign $1\src32__data_o$next[3:0]$11189 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[3:0]$11194 4'0000 + case + assign $6\src32__data_o$next[3:0]$11194 $1\src32__data_o$next[3:0]$11189 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[3:0]$11188 + end + attribute \src "libresoc.v:179957.3-179986.6" + process $proc$libresoc.v:179957$11195 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11196 $1\wr_detect$10[0:0]$11197 + attribute \src "libresoc.v:179958.5-179958.29" + switch \initial + attribute \src "libresoc.v:179958.9-179958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11197 $4\wr_detect$10[0:0]$11200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11198 1'1 + case + assign $2\wr_detect$10[0:0]$11198 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11199 1'1 + case + assign $3\wr_detect$10[0:0]$11199 $2\wr_detect$10[0:0]$11198 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11200 1'1 + case + assign $4\wr_detect$10[0:0]$11200 $3\wr_detect$10[0:0]$11199 + end + case + assign $1\wr_detect$10[0:0]$11197 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11196 + end + attribute \src "libresoc.v:179987.3-180026.6" + process $proc$libresoc.v:179987$11201 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[3:0]$11202 $6\r2__data_o$next[3:0]$11208 + attribute \src "libresoc.v:179988.5-179988.29" + switch \initial + attribute \src "libresoc.v:179988.9-179988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[3:0]$11203 $5\r2__data_o$next[3:0]$11207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[3:0]$11204 \dest12__data_i + case + assign $2\r2__data_o$next[3:0]$11204 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[3:0]$11205 \dest22__data_i + case + assign $3\r2__data_o$next[3:0]$11205 $2\r2__data_o$next[3:0]$11204 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[3:0]$11206 \w2__data_i + case + assign $4\r2__data_o$next[3:0]$11206 $3\r2__data_o$next[3:0]$11205 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[3:0]$11207 \reg + case + assign $5\r2__data_o$next[3:0]$11207 $4\r2__data_o$next[3:0]$11206 + end + case + assign $1\r2__data_o$next[3:0]$11203 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[3:0]$11208 4'0000 + case + assign $6\r2__data_o$next[3:0]$11208 $1\r2__data_o$next[3:0]$11203 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[3:0]$11202 + end + attribute \src "libresoc.v:180027.3-180056.6" + process $proc$libresoc.v:180027$11209 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11210 $1\wr_detect$13[0:0]$11211 + attribute \src "libresoc.v:180028.5-180028.29" + switch \initial + attribute \src "libresoc.v:180028.9-180028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11211 $4\wr_detect$13[0:0]$11214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11212 1'1 + case + assign $2\wr_detect$13[0:0]$11212 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11213 1'1 + case + assign $3\wr_detect$13[0:0]$11213 $2\wr_detect$13[0:0]$11212 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11214 1'1 + case + assign $4\wr_detect$13[0:0]$11214 $3\wr_detect$13[0:0]$11213 + end + case + assign $1\wr_detect$13[0:0]$11211 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11210 + end + connect \$9 $not$libresoc.v:179590$11117_Y + connect \$12 $not$libresoc.v:179591$11118_Y + connect \$15 $not$libresoc.v:179592$11119_Y + connect \$1 $not$libresoc.v:179593$11120_Y + connect \$3 $not$libresoc.v:179594$11121_Y + connect \$6 $not$libresoc.v:179595$11122_Y +end +attribute \src "libresoc.v:180061.1-180506.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" +attribute \generator "nMigen" +module \reg_2$134 + attribute \src "libresoc.v:180062.7-180062.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $0\r2__data_o$next[1:0]$11275 + attribute \src "libresoc.v:180137.3-180138.37" + wire width 2 $0\r2__data_o[1:0] + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $0\reg$next[1:0]$11291 + attribute \src "libresoc.v:180135.3-180136.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $0\src12__data_o$next[1:0]$11233 + attribute \src "libresoc.v:180143.3-180144.43" + wire width 2 $0\src12__data_o[1:0] + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $0\src22__data_o$next[1:0]$11243 + attribute \src "libresoc.v:180141.3-180142.43" + wire width 2 $0\src22__data_o[1:0] + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $0\src32__data_o$next[1:0]$11259 + attribute \src "libresoc.v:180139.3-180140.43" + wire width 2 $0\src32__data_o[1:0] + attribute \src "libresoc.v:180437.3-180472.6" + wire $0\wr_detect$10[0:0]$11284 + attribute \src "libresoc.v:180273.3-180308.6" + wire $0\wr_detect$4[0:0]$11252 + attribute \src "libresoc.v:180355.3-180390.6" + wire $0\wr_detect$7[0:0]$11268 + attribute \src "libresoc.v:180191.3-180226.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $1\r2__data_o$next[1:0]$11276 + attribute \src "libresoc.v:180089.13-180089.30" + wire width 2 $1\r2__data_o[1:0] + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $1\reg$next[1:0]$11292 + attribute \src "libresoc.v:180095.13-180095.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $1\src12__data_o$next[1:0]$11234 + attribute \src "libresoc.v:180100.13-180100.33" + wire width 2 $1\src12__data_o[1:0] + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $1\src22__data_o$next[1:0]$11244 + attribute \src "libresoc.v:180107.13-180107.33" + wire width 2 $1\src22__data_o[1:0] + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $1\src32__data_o$next[1:0]$11260 + attribute \src "libresoc.v:180114.13-180114.33" + wire width 2 $1\src32__data_o[1:0] + attribute \src "libresoc.v:180437.3-180472.6" + wire $1\wr_detect$10[0:0]$11285 + attribute \src "libresoc.v:180273.3-180308.6" + wire $1\wr_detect$4[0:0]$11253 + attribute \src "libresoc.v:180355.3-180390.6" + wire $1\wr_detect$7[0:0]$11269 + attribute \src "libresoc.v:180191.3-180226.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $2\r2__data_o$next[1:0]$11277 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $2\reg$next[1:0]$11293 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $2\src12__data_o$next[1:0]$11235 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $2\src22__data_o$next[1:0]$11245 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $2\src32__data_o$next[1:0]$11261 + attribute \src "libresoc.v:180437.3-180472.6" + wire $2\wr_detect$10[0:0]$11286 + attribute \src "libresoc.v:180273.3-180308.6" + wire $2\wr_detect$4[0:0]$11254 + attribute \src "libresoc.v:180355.3-180390.6" + wire $2\wr_detect$7[0:0]$11270 + attribute \src "libresoc.v:180191.3-180226.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $3\r2__data_o$next[1:0]$11278 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $3\reg$next[1:0]$11294 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $3\src12__data_o$next[1:0]$11236 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $3\src22__data_o$next[1:0]$11246 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $3\src32__data_o$next[1:0]$11262 + attribute \src "libresoc.v:180437.3-180472.6" + wire $3\wr_detect$10[0:0]$11287 + attribute \src "libresoc.v:180273.3-180308.6" + wire $3\wr_detect$4[0:0]$11255 + attribute \src "libresoc.v:180355.3-180390.6" + wire $3\wr_detect$7[0:0]$11271 + attribute \src "libresoc.v:180191.3-180226.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $4\r2__data_o$next[1:0]$11279 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $4\reg$next[1:0]$11295 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $4\src12__data_o$next[1:0]$11237 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $4\src22__data_o$next[1:0]$11247 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $4\src32__data_o$next[1:0]$11263 + attribute \src "libresoc.v:180437.3-180472.6" + wire $4\wr_detect$10[0:0]$11288 + attribute \src "libresoc.v:180273.3-180308.6" + wire $4\wr_detect$4[0:0]$11256 + attribute \src "libresoc.v:180355.3-180390.6" + wire $4\wr_detect$7[0:0]$11272 + attribute \src "libresoc.v:180191.3-180226.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $5\r2__data_o$next[1:0]$11280 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $5\reg$next[1:0]$11296 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $5\src12__data_o$next[1:0]$11238 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $5\src22__data_o$next[1:0]$11248 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $5\src32__data_o$next[1:0]$11264 + attribute \src "libresoc.v:180437.3-180472.6" + wire $5\wr_detect$10[0:0]$11289 + attribute \src "libresoc.v:180273.3-180308.6" + wire $5\wr_detect$4[0:0]$11257 + attribute \src "libresoc.v:180355.3-180390.6" + wire $5\wr_detect$7[0:0]$11273 + attribute \src "libresoc.v:180191.3-180226.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $6\r2__data_o$next[1:0]$11281 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $6\src12__data_o$next[1:0]$11239 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $6\src22__data_o$next[1:0]$11249 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $6\src32__data_o$next[1:0]$11265 + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $7\r2__data_o$next[1:0]$11282 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $7\src12__data_o$next[1:0]$11240 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $7\src22__data_o$next[1:0]$11250 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $7\src32__data_o$next[1:0]$11266 + attribute \src "libresoc.v:180131.17-180131.104" + wire $not$libresoc.v:180131$11223_Y + attribute \src "libresoc.v:180132.17-180132.100" + wire $not$libresoc.v:180132$11224_Y + attribute \src "libresoc.v:180133.17-180133.103" + wire $not$libresoc.v:180133$11225_Y + attribute \src "libresoc.v:180134.17-180134.103" + wire $not$libresoc.v:180134$11226_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 13 \dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest32__wen + attribute \src "libresoc.v:180062.7-180062.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180131$11223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:180131$11223_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180132$11224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:180132$11224_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180133$11225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:180133$11225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180134$11226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:180134$11226_Y + end + attribute \src "libresoc.v:180062.7-180062.20" + process $proc$libresoc.v:180062$11297 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180089.13-180089.30" + process $proc$libresoc.v:180089$11298 + assign { } { } + assign $1\r2__data_o[1:0] 2'00 + sync always + sync init + update \r2__data_o $1\r2__data_o[1:0] + end + attribute \src "libresoc.v:180095.13-180095.25" + process $proc$libresoc.v:180095$11299 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:180100.13-180100.33" + process $proc$libresoc.v:180100$11300 + assign { } { } + assign $1\src12__data_o[1:0] 2'00 + sync always + sync init + update \src12__data_o $1\src12__data_o[1:0] + end + attribute \src "libresoc.v:180107.13-180107.33" + process $proc$libresoc.v:180107$11301 + assign { } { } + assign $1\src22__data_o[1:0] 2'00 + sync always + sync init + update \src22__data_o $1\src22__data_o[1:0] + end + attribute \src "libresoc.v:180114.13-180114.33" + process $proc$libresoc.v:180114$11302 + assign { } { } + assign $1\src32__data_o[1:0] 2'00 + sync always + sync init + update \src32__data_o $1\src32__data_o[1:0] + end + attribute \src "libresoc.v:180135.3-180136.25" + process $proc$libresoc.v:180135$11227 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:180137.3-180138.37" + process $proc$libresoc.v:180137$11228 + assign { } { } + assign $0\r2__data_o[1:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[1:0] + end + attribute \src "libresoc.v:180139.3-180140.43" + process $proc$libresoc.v:180139$11229 + assign { } { } + assign $0\src32__data_o[1:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[1:0] + end + attribute \src "libresoc.v:180141.3-180142.43" + process $proc$libresoc.v:180141$11230 + assign { } { } + assign $0\src22__data_o[1:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[1:0] + end + attribute \src "libresoc.v:180143.3-180144.43" + process $proc$libresoc.v:180143$11231 + assign { } { } + assign $0\src12__data_o[1:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[1:0] + end + attribute \src "libresoc.v:180145.3-180190.6" + process $proc$libresoc.v:180145$11232 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[1:0]$11233 $7\src12__data_o$next[1:0]$11240 + attribute \src "libresoc.v:180146.5-180146.29" + switch \initial + attribute \src "libresoc.v:180146.9-180146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[1:0]$11234 $6\src12__data_o$next[1:0]$11239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[1:0]$11235 \dest12__data_i + case + assign $2\src12__data_o$next[1:0]$11235 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[1:0]$11236 \dest22__data_i + case + assign $3\src12__data_o$next[1:0]$11236 $2\src12__data_o$next[1:0]$11235 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[1:0]$11237 \dest32__data_i + case + assign $4\src12__data_o$next[1:0]$11237 $3\src12__data_o$next[1:0]$11236 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[1:0]$11238 \w2__data_i + case + assign $5\src12__data_o$next[1:0]$11238 $4\src12__data_o$next[1:0]$11237 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[1:0]$11239 \reg + case + assign $6\src12__data_o$next[1:0]$11239 $5\src12__data_o$next[1:0]$11238 + end + case + assign $1\src12__data_o$next[1:0]$11234 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src12__data_o$next[1:0]$11240 2'00 + case + assign $7\src12__data_o$next[1:0]$11240 $1\src12__data_o$next[1:0]$11234 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[1:0]$11233 + end + attribute \src "libresoc.v:180191.3-180226.6" + process $proc$libresoc.v:180191$11241 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:180192.5-180192.29" + switch \initial + attribute \src "libresoc.v:180192.9-180192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:180227.3-180272.6" + process $proc$libresoc.v:180227$11242 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[1:0]$11243 $7\src22__data_o$next[1:0]$11250 + attribute \src "libresoc.v:180228.5-180228.29" + switch \initial + attribute \src "libresoc.v:180228.9-180228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[1:0]$11244 $6\src22__data_o$next[1:0]$11249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[1:0]$11245 \dest12__data_i + case + assign $2\src22__data_o$next[1:0]$11245 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[1:0]$11246 \dest22__data_i + case + assign $3\src22__data_o$next[1:0]$11246 $2\src22__data_o$next[1:0]$11245 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[1:0]$11247 \dest32__data_i + case + assign $4\src22__data_o$next[1:0]$11247 $3\src22__data_o$next[1:0]$11246 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[1:0]$11248 \w2__data_i + case + assign $5\src22__data_o$next[1:0]$11248 $4\src22__data_o$next[1:0]$11247 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[1:0]$11249 \reg + case + assign $6\src22__data_o$next[1:0]$11249 $5\src22__data_o$next[1:0]$11248 + end + case + assign $1\src22__data_o$next[1:0]$11244 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src22__data_o$next[1:0]$11250 2'00 + case + assign $7\src22__data_o$next[1:0]$11250 $1\src22__data_o$next[1:0]$11244 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[1:0]$11243 + end + attribute \src "libresoc.v:180273.3-180308.6" + process $proc$libresoc.v:180273$11251 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11252 $1\wr_detect$4[0:0]$11253 + attribute \src "libresoc.v:180274.5-180274.29" + switch \initial + attribute \src "libresoc.v:180274.9-180274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11253 $5\wr_detect$4[0:0]$11257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11254 1'1 + case + assign $2\wr_detect$4[0:0]$11254 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11255 1'1 + case + assign $3\wr_detect$4[0:0]$11255 $2\wr_detect$4[0:0]$11254 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11256 1'1 + case + assign $4\wr_detect$4[0:0]$11256 $3\wr_detect$4[0:0]$11255 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11257 1'1 + case + assign $5\wr_detect$4[0:0]$11257 $4\wr_detect$4[0:0]$11256 + end + case + assign $1\wr_detect$4[0:0]$11253 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11252 + end + attribute \src "libresoc.v:180309.3-180354.6" + process $proc$libresoc.v:180309$11258 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[1:0]$11259 $7\src32__data_o$next[1:0]$11266 + attribute \src "libresoc.v:180310.5-180310.29" + switch \initial + attribute \src "libresoc.v:180310.9-180310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[1:0]$11260 $6\src32__data_o$next[1:0]$11265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[1:0]$11261 \dest12__data_i + case + assign $2\src32__data_o$next[1:0]$11261 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[1:0]$11262 \dest22__data_i + case + assign $3\src32__data_o$next[1:0]$11262 $2\src32__data_o$next[1:0]$11261 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[1:0]$11263 \dest32__data_i + case + assign $4\src32__data_o$next[1:0]$11263 $3\src32__data_o$next[1:0]$11262 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[1:0]$11264 \w2__data_i + case + assign $5\src32__data_o$next[1:0]$11264 $4\src32__data_o$next[1:0]$11263 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[1:0]$11265 \reg + case + assign $6\src32__data_o$next[1:0]$11265 $5\src32__data_o$next[1:0]$11264 + end + case + assign $1\src32__data_o$next[1:0]$11260 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src32__data_o$next[1:0]$11266 2'00 + case + assign $7\src32__data_o$next[1:0]$11266 $1\src32__data_o$next[1:0]$11260 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[1:0]$11259 + end + attribute \src "libresoc.v:180355.3-180390.6" + process $proc$libresoc.v:180355$11267 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11268 $1\wr_detect$7[0:0]$11269 + attribute \src "libresoc.v:180356.5-180356.29" + switch \initial + attribute \src "libresoc.v:180356.9-180356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11269 $5\wr_detect$7[0:0]$11273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11270 1'1 + case + assign $2\wr_detect$7[0:0]$11270 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11271 1'1 + case + assign $3\wr_detect$7[0:0]$11271 $2\wr_detect$7[0:0]$11270 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11272 1'1 + case + assign $4\wr_detect$7[0:0]$11272 $3\wr_detect$7[0:0]$11271 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11273 1'1 + case + assign $5\wr_detect$7[0:0]$11273 $4\wr_detect$7[0:0]$11272 + end + case + assign $1\wr_detect$7[0:0]$11269 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11268 + end + attribute \src "libresoc.v:180391.3-180436.6" + process $proc$libresoc.v:180391$11274 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[1:0]$11275 $7\r2__data_o$next[1:0]$11282 + attribute \src "libresoc.v:180392.5-180392.29" + switch \initial + attribute \src "libresoc.v:180392.9-180392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[1:0]$11276 $6\r2__data_o$next[1:0]$11281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[1:0]$11277 \dest12__data_i + case + assign $2\r2__data_o$next[1:0]$11277 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[1:0]$11278 \dest22__data_i + case + assign $3\r2__data_o$next[1:0]$11278 $2\r2__data_o$next[1:0]$11277 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[1:0]$11279 \dest32__data_i + case + assign $4\r2__data_o$next[1:0]$11279 $3\r2__data_o$next[1:0]$11278 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[1:0]$11280 \w2__data_i + case + assign $5\r2__data_o$next[1:0]$11280 $4\r2__data_o$next[1:0]$11279 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[1:0]$11281 \reg + case + assign $6\r2__data_o$next[1:0]$11281 $5\r2__data_o$next[1:0]$11280 + end + case + assign $1\r2__data_o$next[1:0]$11276 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r2__data_o$next[1:0]$11282 2'00 + case + assign $7\r2__data_o$next[1:0]$11282 $1\r2__data_o$next[1:0]$11276 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[1:0]$11275 + end + attribute \src "libresoc.v:180437.3-180472.6" + process $proc$libresoc.v:180437$11283 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11284 $1\wr_detect$10[0:0]$11285 + attribute \src "libresoc.v:180438.5-180438.29" + switch \initial + attribute \src "libresoc.v:180438.9-180438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11285 $5\wr_detect$10[0:0]$11289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11286 1'1 + case + assign $2\wr_detect$10[0:0]$11286 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11287 1'1 + case + assign $3\wr_detect$10[0:0]$11287 $2\wr_detect$10[0:0]$11286 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11288 1'1 + case + assign $4\wr_detect$10[0:0]$11288 $3\wr_detect$10[0:0]$11287 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11289 1'1 + case + assign $5\wr_detect$10[0:0]$11289 $4\wr_detect$10[0:0]$11288 + end + case + assign $1\wr_detect$10[0:0]$11285 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11284 + end + attribute \src "libresoc.v:180473.3-180505.6" + process $proc$libresoc.v:180473$11290 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11291 $5\reg$next[1:0]$11296 + attribute \src "libresoc.v:180474.5-180474.29" + switch \initial + attribute \src "libresoc.v:180474.9-180474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11292 \dest12__data_i + case + assign $1\reg$next[1:0]$11292 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11293 \dest22__data_i + case + assign $2\reg$next[1:0]$11293 $1\reg$next[1:0]$11292 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11294 \dest32__data_i + case + assign $3\reg$next[1:0]$11294 $2\reg$next[1:0]$11293 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11295 \w2__data_i + case + assign $4\reg$next[1:0]$11295 $3\reg$next[1:0]$11294 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11296 2'00 + case + assign $5\reg$next[1:0]$11296 $4\reg$next[1:0]$11295 + end + sync always + update \reg$next $0\reg$next[1:0]$11291 + end + connect \$9 $not$libresoc.v:180131$11223_Y + connect \$1 $not$libresoc.v:180132$11224_Y + connect \$3 $not$libresoc.v:180133$11225_Y + connect \$6 $not$libresoc.v:180134$11226_Y +end +attribute \src "libresoc.v:180510.1-180859.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" +attribute \generator "nMigen" +module \reg_2$137 + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $0\cia2__data_o$next[63:0]$11311 + attribute \src "libresoc.v:180578.3-180579.41" + wire width 64 $0\cia2__data_o[63:0] + attribute \src "libresoc.v:180511.7-180511.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $0\msr2__data_o$next[63:0]$11321 + attribute \src "libresoc.v:180576.3-180577.41" + wire width 64 $0\msr2__data_o[63:0] + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $0\reg$next[63:0]$11353 + attribute \src "libresoc.v:180572.3-180573.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $0\sv2__data_o$next[63:0]$11337 + attribute \src "libresoc.v:180574.3-180575.39" + wire width 64 $0\sv2__data_o[63:0] + attribute \src "libresoc.v:180708.3-180743.6" + wire $0\wr_detect$4[0:0]$11330 + attribute \src "libresoc.v:180790.3-180825.6" + wire $0\wr_detect$7[0:0]$11346 + attribute \src "libresoc.v:180626.3-180661.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $1\cia2__data_o$next[63:0]$11312 + attribute \src "libresoc.v:180520.14-180520.49" + wire width 64 $1\cia2__data_o[63:0] + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $1\msr2__data_o$next[63:0]$11322 + attribute \src "libresoc.v:180537.14-180537.49" + wire width 64 $1\msr2__data_o[63:0] + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $1\reg$next[63:0]$11354 + attribute \src "libresoc.v:180549.14-180549.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $1\sv2__data_o$next[63:0]$11338 + attribute \src "libresoc.v:180556.14-180556.48" + wire width 64 $1\sv2__data_o[63:0] + attribute \src "libresoc.v:180708.3-180743.6" + wire $1\wr_detect$4[0:0]$11331 + attribute \src "libresoc.v:180790.3-180825.6" + wire $1\wr_detect$7[0:0]$11347 + attribute \src "libresoc.v:180626.3-180661.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $2\cia2__data_o$next[63:0]$11313 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $2\msr2__data_o$next[63:0]$11323 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $2\reg$next[63:0]$11355 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $2\sv2__data_o$next[63:0]$11339 + attribute \src "libresoc.v:180708.3-180743.6" + wire $2\wr_detect$4[0:0]$11332 + attribute \src "libresoc.v:180790.3-180825.6" + wire $2\wr_detect$7[0:0]$11348 + attribute \src "libresoc.v:180626.3-180661.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $3\cia2__data_o$next[63:0]$11314 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $3\msr2__data_o$next[63:0]$11324 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $3\reg$next[63:0]$11356 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $3\sv2__data_o$next[63:0]$11340 + attribute \src "libresoc.v:180708.3-180743.6" + wire $3\wr_detect$4[0:0]$11333 + attribute \src "libresoc.v:180790.3-180825.6" + wire $3\wr_detect$7[0:0]$11349 + attribute \src "libresoc.v:180626.3-180661.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $4\cia2__data_o$next[63:0]$11315 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $4\msr2__data_o$next[63:0]$11325 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $4\reg$next[63:0]$11357 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $4\sv2__data_o$next[63:0]$11341 + attribute \src "libresoc.v:180708.3-180743.6" + wire $4\wr_detect$4[0:0]$11334 + attribute \src "libresoc.v:180790.3-180825.6" + wire $4\wr_detect$7[0:0]$11350 + attribute \src "libresoc.v:180626.3-180661.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $5\cia2__data_o$next[63:0]$11316 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $5\msr2__data_o$next[63:0]$11326 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $5\reg$next[63:0]$11358 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $5\sv2__data_o$next[63:0]$11342 + attribute \src "libresoc.v:180708.3-180743.6" + wire $5\wr_detect$4[0:0]$11335 + attribute \src "libresoc.v:180790.3-180825.6" + wire $5\wr_detect$7[0:0]$11351 + attribute \src "libresoc.v:180626.3-180661.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $6\cia2__data_o$next[63:0]$11317 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $6\msr2__data_o$next[63:0]$11327 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $6\sv2__data_o$next[63:0]$11343 + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $7\cia2__data_o$next[63:0]$11318 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $7\msr2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $7\sv2__data_o$next[63:0]$11344 + attribute \src "libresoc.v:180569.17-180569.100" + wire $not$libresoc.v:180569$11303_Y + attribute \src "libresoc.v:180570.17-180570.103" + wire $not$libresoc.v:180570$11304_Y + attribute \src "libresoc.v:180571.17-180571.103" + wire $not$libresoc.v:180571$11305_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr12__wen + attribute \src "libresoc.v:180511.7-180511.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180569$11303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:180569$11303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180570$11304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:180570$11304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180571$11305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:180571$11305_Y + end + attribute \src "libresoc.v:180511.7-180511.20" + process $proc$libresoc.v:180511$11359 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180520.14-180520.49" + process $proc$libresoc.v:180520$11360 + assign { } { } + assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia2__data_o $1\cia2__data_o[63:0] + end + attribute \src "libresoc.v:180537.14-180537.49" + process $proc$libresoc.v:180537$11361 + assign { } { } + assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr2__data_o $1\msr2__data_o[63:0] + end + attribute \src "libresoc.v:180549.14-180549.42" + process $proc$libresoc.v:180549$11362 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:180556.14-180556.48" + process $proc$libresoc.v:180556$11363 + assign { } { } + assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv2__data_o $1\sv2__data_o[63:0] + end + attribute \src "libresoc.v:180572.3-180573.25" + process $proc$libresoc.v:180572$11306 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:180574.3-180575.39" + process $proc$libresoc.v:180574$11307 + assign { } { } + assign $0\sv2__data_o[63:0] \sv2__data_o$next + sync posedge \coresync_clk + update \sv2__data_o $0\sv2__data_o[63:0] + end + attribute \src "libresoc.v:180576.3-180577.41" + process $proc$libresoc.v:180576$11308 + assign { } { } + assign $0\msr2__data_o[63:0] \msr2__data_o$next + sync posedge \coresync_clk + update \msr2__data_o $0\msr2__data_o[63:0] + end + attribute \src "libresoc.v:180578.3-180579.41" + process $proc$libresoc.v:180578$11309 + assign { } { } + assign $0\cia2__data_o[63:0] \cia2__data_o$next + sync posedge \coresync_clk + update \cia2__data_o $0\cia2__data_o[63:0] + end + attribute \src "libresoc.v:180580.3-180625.6" + process $proc$libresoc.v:180580$11310 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia2__data_o$next[63:0]$11311 $7\cia2__data_o$next[63:0]$11318 + attribute \src "libresoc.v:180581.5-180581.29" + switch \initial + attribute \src "libresoc.v:180581.9-180581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia2__data_o$next[63:0]$11312 $6\cia2__data_o$next[63:0]$11317 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia2__data_o$next[63:0]$11313 \nia2__data_i + case + assign $2\cia2__data_o$next[63:0]$11313 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia2__data_o$next[63:0]$11314 \msr2__data_i + case + assign $3\cia2__data_o$next[63:0]$11314 $2\cia2__data_o$next[63:0]$11313 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia2__data_o$next[63:0]$11315 \sv2__data_i + case + assign $4\cia2__data_o$next[63:0]$11315 $3\cia2__data_o$next[63:0]$11314 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia2__data_o$next[63:0]$11316 \d_wr12__data_i + case + assign $5\cia2__data_o$next[63:0]$11316 $4\cia2__data_o$next[63:0]$11315 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia2__data_o$next[63:0]$11317 \reg + case + assign $6\cia2__data_o$next[63:0]$11317 $5\cia2__data_o$next[63:0]$11316 + end + case + assign $1\cia2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia2__data_o$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia2__data_o$next[63:0]$11318 $1\cia2__data_o$next[63:0]$11312 + end + sync always + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11311 + end + attribute \src "libresoc.v:180626.3-180661.6" + process $proc$libresoc.v:180626$11319 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:180627.5-180627.29" + switch \initial + attribute \src "libresoc.v:180627.9-180627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:180662.3-180707.6" + process $proc$libresoc.v:180662$11320 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr2__data_o$next[63:0]$11321 $7\msr2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:180663.5-180663.29" + switch \initial + attribute \src "libresoc.v:180663.9-180663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr2__data_o$next[63:0]$11322 $6\msr2__data_o$next[63:0]$11327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr2__data_o$next[63:0]$11323 \nia2__data_i + case + assign $2\msr2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr2__data_o$next[63:0]$11324 \msr2__data_i + case + assign $3\msr2__data_o$next[63:0]$11324 $2\msr2__data_o$next[63:0]$11323 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr2__data_o$next[63:0]$11325 \sv2__data_i + case + assign $4\msr2__data_o$next[63:0]$11325 $3\msr2__data_o$next[63:0]$11324 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr2__data_o$next[63:0]$11326 \d_wr12__data_i + case + assign $5\msr2__data_o$next[63:0]$11326 $4\msr2__data_o$next[63:0]$11325 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr2__data_o$next[63:0]$11327 \reg + case + assign $6\msr2__data_o$next[63:0]$11327 $5\msr2__data_o$next[63:0]$11326 + end + case + assign $1\msr2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\msr2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\msr2__data_o$next[63:0]$11328 $1\msr2__data_o$next[63:0]$11322 + end + sync always + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11321 + end + attribute \src "libresoc.v:180708.3-180743.6" + process $proc$libresoc.v:180708$11329 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11330 $1\wr_detect$4[0:0]$11331 + attribute \src "libresoc.v:180709.5-180709.29" + switch \initial + attribute \src "libresoc.v:180709.9-180709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11331 $5\wr_detect$4[0:0]$11335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11332 1'1 + case + assign $2\wr_detect$4[0:0]$11332 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11333 1'1 + case + assign $3\wr_detect$4[0:0]$11333 $2\wr_detect$4[0:0]$11332 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11334 1'1 + case + assign $4\wr_detect$4[0:0]$11334 $3\wr_detect$4[0:0]$11333 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11335 1'1 + case + assign $5\wr_detect$4[0:0]$11335 $4\wr_detect$4[0:0]$11334 + end + case + assign $1\wr_detect$4[0:0]$11331 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11330 + end + attribute \src "libresoc.v:180744.3-180789.6" + process $proc$libresoc.v:180744$11336 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv2__data_o$next[63:0]$11337 $7\sv2__data_o$next[63:0]$11344 + attribute \src "libresoc.v:180745.5-180745.29" + switch \initial + attribute \src "libresoc.v:180745.9-180745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv2__data_o$next[63:0]$11338 $6\sv2__data_o$next[63:0]$11343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv2__data_o$next[63:0]$11339 \nia2__data_i + case + assign $2\sv2__data_o$next[63:0]$11339 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv2__data_o$next[63:0]$11340 \msr2__data_i + case + assign $3\sv2__data_o$next[63:0]$11340 $2\sv2__data_o$next[63:0]$11339 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv2__data_o$next[63:0]$11341 \sv2__data_i + case + assign $4\sv2__data_o$next[63:0]$11341 $3\sv2__data_o$next[63:0]$11340 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv2__data_o$next[63:0]$11342 \d_wr12__data_i + case + assign $5\sv2__data_o$next[63:0]$11342 $4\sv2__data_o$next[63:0]$11341 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv2__data_o$next[63:0]$11343 \reg + case + assign $6\sv2__data_o$next[63:0]$11343 $5\sv2__data_o$next[63:0]$11342 + end + case + assign $1\sv2__data_o$next[63:0]$11338 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv2__data_o$next[63:0]$11344 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv2__data_o$next[63:0]$11344 $1\sv2__data_o$next[63:0]$11338 + end + sync always + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11337 + end + attribute \src "libresoc.v:180790.3-180825.6" + process $proc$libresoc.v:180790$11345 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11346 $1\wr_detect$7[0:0]$11347 + attribute \src "libresoc.v:180791.5-180791.29" + switch \initial + attribute \src "libresoc.v:180791.9-180791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11347 $5\wr_detect$7[0:0]$11351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11348 1'1 + case + assign $2\wr_detect$7[0:0]$11348 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11349 1'1 + case + assign $3\wr_detect$7[0:0]$11349 $2\wr_detect$7[0:0]$11348 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11350 1'1 + case + assign $4\wr_detect$7[0:0]$11350 $3\wr_detect$7[0:0]$11349 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11351 1'1 + case + assign $5\wr_detect$7[0:0]$11351 $4\wr_detect$7[0:0]$11350 + end + case + assign $1\wr_detect$7[0:0]$11347 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11346 + end + attribute \src "libresoc.v:180826.3-180858.6" + process $proc$libresoc.v:180826$11352 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11353 $5\reg$next[63:0]$11358 + attribute \src "libresoc.v:180827.5-180827.29" + switch \initial + attribute \src "libresoc.v:180827.9-180827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11354 \nia2__data_i + case + assign $1\reg$next[63:0]$11354 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11355 \msr2__data_i + case + assign $2\reg$next[63:0]$11355 $1\reg$next[63:0]$11354 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11356 \sv2__data_i + case + assign $3\reg$next[63:0]$11356 $2\reg$next[63:0]$11355 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11357 \d_wr12__data_i + case + assign $4\reg$next[63:0]$11357 $3\reg$next[63:0]$11356 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[63:0]$11358 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $5\reg$next[63:0]$11358 $4\reg$next[63:0]$11357 + end + sync always + update \reg$next $0\reg$next[63:0]$11353 + end + connect \$1 $not$libresoc.v:180569$11303_Y + connect \$3 $not$libresoc.v:180570$11304_Y + connect \$6 $not$libresoc.v:180571$11305_Y +end +attribute \src "libresoc.v:180863.1-181418.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" +attribute \generator "nMigen" +module \reg_3 + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $0\cr_pred3__data_o$next[3:0]$11378 + attribute \src "libresoc.v:180969.3-180970.49" + wire width 4 $0\cr_pred3__data_o[3:0] + attribute \src "libresoc.v:180864.7-180864.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $0\r23__data_o$next[3:0]$11387 + attribute \src "libresoc.v:180959.3-180960.39" + wire width 4 $0\r23__data_o[3:0] + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $0\r3__data_o$next[3:0]$11449 + attribute \src "libresoc.v:180961.3-180962.37" + wire width 4 $0\r3__data_o[3:0] + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $0\reg$next[3:0]$11401 + attribute \src "libresoc.v:180957.3-180958.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $0\src13__data_o$next[3:0]$11407 + attribute \src "libresoc.v:180967.3-180968.43" + wire width 4 $0\src13__data_o[3:0] + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $0\src23__data_o$next[3:0]$11421 + attribute \src "libresoc.v:180965.3-180966.43" + wire width 4 $0\src23__data_o[3:0] + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $0\src33__data_o$next[3:0]$11435 + attribute \src "libresoc.v:180963.3-180964.43" + wire width 4 $0\src33__data_o[3:0] + attribute \src "libresoc.v:181318.3-181347.6" + wire $0\wr_detect$10[0:0]$11443 + attribute \src "libresoc.v:181388.3-181417.6" + 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$1\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:181011.3-181040.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $2\cr_pred3__data_o$next[3:0]$11380 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $2\r23__data_o$next[3:0]$11389 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $2\r3__data_o$next[3:0]$11451 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $2\reg$next[3:0]$11403 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $2\src13__data_o$next[3:0]$11409 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $2\src23__data_o$next[3:0]$11423 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $2\src33__data_o$next[3:0]$11437 + attribute \src "libresoc.v:181318.3-181347.6" + wire $2\wr_detect$10[0:0]$11445 + attribute \src "libresoc.v:181388.3-181417.6" + wire $2\wr_detect$13[0:0]$11459 + attribute \src "libresoc.v:181081.3-181110.6" + wire $2\wr_detect$16[0:0]$11397 + attribute \src "libresoc.v:181178.3-181207.6" + wire $2\wr_detect$4[0:0]$11417 + attribute \src "libresoc.v:181248.3-181277.6" + wire $2\wr_detect$7[0:0]$11431 + attribute \src "libresoc.v:181011.3-181040.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $3\cr_pred3__data_o$next[3:0]$11381 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $3\r23__data_o$next[3:0]$11390 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $3\r3__data_o$next[3:0]$11452 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $3\reg$next[3:0]$11404 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $3\src13__data_o$next[3:0]$11410 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $3\src23__data_o$next[3:0]$11424 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $3\src33__data_o$next[3:0]$11438 + attribute \src "libresoc.v:181318.3-181347.6" + wire $3\wr_detect$10[0:0]$11446 + attribute \src "libresoc.v:181388.3-181417.6" + wire $3\wr_detect$13[0:0]$11460 + attribute \src "libresoc.v:181081.3-181110.6" + wire $3\wr_detect$16[0:0]$11398 + attribute \src "libresoc.v:181178.3-181207.6" + wire $3\wr_detect$4[0:0]$11418 + attribute \src "libresoc.v:181248.3-181277.6" + wire $3\wr_detect$7[0:0]$11432 + attribute \src "libresoc.v:181011.3-181040.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $4\cr_pred3__data_o$next[3:0]$11382 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $4\r23__data_o$next[3:0]$11391 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $4\r3__data_o$next[3:0]$11453 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $4\reg$next[3:0]$11405 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $4\src13__data_o$next[3:0]$11411 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $4\src23__data_o$next[3:0]$11425 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $4\src33__data_o$next[3:0]$11439 + attribute \src "libresoc.v:181318.3-181347.6" + wire $4\wr_detect$10[0:0]$11447 + attribute \src "libresoc.v:181388.3-181417.6" + wire $4\wr_detect$13[0:0]$11461 + attribute \src "libresoc.v:181081.3-181110.6" + wire $4\wr_detect$16[0:0]$11399 + attribute \src "libresoc.v:181178.3-181207.6" + wire $4\wr_detect$4[0:0]$11419 + attribute \src "libresoc.v:181248.3-181277.6" + wire $4\wr_detect$7[0:0]$11433 + attribute \src "libresoc.v:181011.3-181040.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $5\cr_pred3__data_o$next[3:0]$11383 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $5\r23__data_o$next[3:0]$11392 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $5\r3__data_o$next[3:0]$11454 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $5\src13__data_o$next[3:0]$11412 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $5\src23__data_o$next[3:0]$11426 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $5\src33__data_o$next[3:0]$11440 + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $6\cr_pred3__data_o$next[3:0]$11384 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $6\r23__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $6\r3__data_o$next[3:0]$11455 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $6\src13__data_o$next[3:0]$11413 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $6\src23__data_o$next[3:0]$11427 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $6\src33__data_o$next[3:0]$11441 + attribute \src "libresoc.v:180951.17-180951.104" + wire $not$libresoc.v:180951$11364_Y + attribute \src "libresoc.v:180952.18-180952.105" + wire $not$libresoc.v:180952$11365_Y + attribute \src "libresoc.v:180953.18-180953.105" + wire $not$libresoc.v:180953$11366_Y + attribute \src "libresoc.v:180954.17-180954.100" + wire $not$libresoc.v:180954$11367_Y + attribute \src "libresoc.v:180955.17-180955.103" + wire $not$libresoc.v:180955$11368_Y + attribute \src "libresoc.v:180956.17-180956.103" + wire $not$libresoc.v:180956$11369_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest23__wen + attribute \src "libresoc.v:180864.7-180864.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src13__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src33__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180951$11364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:180951$11364_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180952$11365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:180952$11365_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180953$11366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:180953$11366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180954$11367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:180954$11367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180955$11368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:180955$11368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180956$11369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:180956$11369_Y + end + attribute \src "libresoc.v:180864.7-180864.20" + process $proc$libresoc.v:180864$11462 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180883.13-180883.36" + process $proc$libresoc.v:180883$11463 + assign { } { } + assign $1\cr_pred3__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred3__data_o $1\cr_pred3__data_o[3:0] + end + attribute \src "libresoc.v:180898.13-180898.31" + process $proc$libresoc.v:180898$11464 + assign { } { } + assign $1\r23__data_o[3:0] 4'0000 + sync always + sync init + update \r23__data_o $1\r23__data_o[3:0] + end + attribute \src "libresoc.v:180905.13-180905.30" + process $proc$libresoc.v:180905$11465 + assign { } { } + assign $1\r3__data_o[3:0] 4'0000 + sync always + sync init + update \r3__data_o $1\r3__data_o[3:0] + end + attribute \src "libresoc.v:180911.13-180911.25" + process $proc$libresoc.v:180911$11466 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:180916.13-180916.33" + process $proc$libresoc.v:180916$11467 + assign { } { } + assign $1\src13__data_o[3:0] 4'0000 + sync always + sync init + update \src13__data_o $1\src13__data_o[3:0] + end + attribute \src "libresoc.v:180923.13-180923.33" + process $proc$libresoc.v:180923$11468 + assign { } { } + assign $1\src23__data_o[3:0] 4'0000 + sync always + sync init + update \src23__data_o $1\src23__data_o[3:0] + end + attribute \src "libresoc.v:180930.13-180930.33" + process $proc$libresoc.v:180930$11469 + assign { } { } + assign $1\src33__data_o[3:0] 4'0000 + sync always + sync init + update \src33__data_o $1\src33__data_o[3:0] + end + attribute \src "libresoc.v:180957.3-180958.25" + process $proc$libresoc.v:180957$11370 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:180959.3-180960.39" + process $proc$libresoc.v:180959$11371 + assign { } { } + assign $0\r23__data_o[3:0] \r23__data_o$next + sync posedge \coresync_clk + update \r23__data_o $0\r23__data_o[3:0] + end + attribute \src "libresoc.v:180961.3-180962.37" + process $proc$libresoc.v:180961$11372 + assign { } { } + assign $0\r3__data_o[3:0] \r3__data_o$next + sync posedge \coresync_clk + update \r3__data_o $0\r3__data_o[3:0] + end + attribute \src "libresoc.v:180963.3-180964.43" + process $proc$libresoc.v:180963$11373 + assign { } { } + assign $0\src33__data_o[3:0] \src33__data_o$next + sync posedge \coresync_clk + update \src33__data_o $0\src33__data_o[3:0] + end + attribute \src "libresoc.v:180965.3-180966.43" + process $proc$libresoc.v:180965$11374 + assign { } { } + assign $0\src23__data_o[3:0] \src23__data_o$next + sync posedge \coresync_clk + update \src23__data_o $0\src23__data_o[3:0] + end + attribute \src "libresoc.v:180967.3-180968.43" + process $proc$libresoc.v:180967$11375 + assign { } { } + assign $0\src13__data_o[3:0] \src13__data_o$next + sync posedge \coresync_clk + update \src13__data_o $0\src13__data_o[3:0] + end + attribute \src "libresoc.v:180969.3-180970.49" + process $proc$libresoc.v:180969$11376 + assign { } { } + assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next + sync posedge \coresync_clk + update \cr_pred3__data_o $0\cr_pred3__data_o[3:0] + end + attribute \src "libresoc.v:180971.3-181010.6" + process $proc$libresoc.v:180971$11377 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred3__data_o$next[3:0]$11378 $6\cr_pred3__data_o$next[3:0]$11384 + attribute \src "libresoc.v:180972.5-180972.29" + switch \initial + attribute \src "libresoc.v:180972.9-180972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred3__data_o$next[3:0]$11379 $5\cr_pred3__data_o$next[3:0]$11383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred3__data_o$next[3:0]$11380 \dest13__data_i + case + assign $2\cr_pred3__data_o$next[3:0]$11380 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred3__data_o$next[3:0]$11381 \dest23__data_i + case + assign $3\cr_pred3__data_o$next[3:0]$11381 $2\cr_pred3__data_o$next[3:0]$11380 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred3__data_o$next[3:0]$11382 \w3__data_i + case + assign $4\cr_pred3__data_o$next[3:0]$11382 $3\cr_pred3__data_o$next[3:0]$11381 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred3__data_o$next[3:0]$11383 \reg + case + assign $5\cr_pred3__data_o$next[3:0]$11383 $4\cr_pred3__data_o$next[3:0]$11382 + end + case + assign $1\cr_pred3__data_o$next[3:0]$11379 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred3__data_o$next[3:0]$11384 4'0000 + case + assign $6\cr_pred3__data_o$next[3:0]$11384 $1\cr_pred3__data_o$next[3:0]$11379 + end + sync always + update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11378 + end + attribute \src "libresoc.v:181011.3-181040.6" + process $proc$libresoc.v:181011$11385 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:181012.5-181012.29" + switch \initial + attribute \src "libresoc.v:181012.9-181012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:181041.3-181080.6" + process $proc$libresoc.v:181041$11386 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$11387 $6\r23__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181042.5-181042.29" + switch \initial + attribute \src "libresoc.v:181042.9-181042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$11388 $5\r23__data_o$next[3:0]$11392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$11389 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$11389 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$11390 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$11390 $2\r23__data_o$next[3:0]$11389 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$11391 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$11391 $3\r23__data_o$next[3:0]$11390 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$11392 \reg + case + assign $5\r23__data_o$next[3:0]$11392 $4\r23__data_o$next[3:0]$11391 + end + case + assign $1\r23__data_o$next[3:0]$11388 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$11393 4'0000 + case + assign $6\r23__data_o$next[3:0]$11393 $1\r23__data_o$next[3:0]$11388 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$11387 + end + attribute \src "libresoc.v:181081.3-181110.6" + process $proc$libresoc.v:181081$11394 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11395 $1\wr_detect$16[0:0]$11396 + attribute \src "libresoc.v:181082.5-181082.29" + switch \initial + attribute \src "libresoc.v:181082.9-181082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11396 $4\wr_detect$16[0:0]$11399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11397 1'1 + case + assign $2\wr_detect$16[0:0]$11397 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11398 1'1 + case + assign $3\wr_detect$16[0:0]$11398 $2\wr_detect$16[0:0]$11397 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11399 1'1 + case + assign $4\wr_detect$16[0:0]$11399 $3\wr_detect$16[0:0]$11398 + end + case + assign $1\wr_detect$16[0:0]$11396 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11395 + end + attribute \src "libresoc.v:181111.3-181137.6" + process $proc$libresoc.v:181111$11400 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11401 $4\reg$next[3:0]$11405 + attribute \src "libresoc.v:181112.5-181112.29" + switch \initial + attribute \src "libresoc.v:181112.9-181112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11402 \dest13__data_i + case + assign $1\reg$next[3:0]$11402 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11403 \dest23__data_i + case + assign $2\reg$next[3:0]$11403 $1\reg$next[3:0]$11402 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11404 \w3__data_i + case + assign $3\reg$next[3:0]$11404 $2\reg$next[3:0]$11403 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11405 4'0000 + case + assign $4\reg$next[3:0]$11405 $3\reg$next[3:0]$11404 + end + sync always + update \reg$next $0\reg$next[3:0]$11401 + end + attribute \src "libresoc.v:181138.3-181177.6" + process $proc$libresoc.v:181138$11406 + assign { } { } + assign { } { } + assign { } { } + assign $0\src13__data_o$next[3:0]$11407 $6\src13__data_o$next[3:0]$11413 + attribute \src "libresoc.v:181139.5-181139.29" + switch \initial + attribute \src "libresoc.v:181139.9-181139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src13__data_o$next[3:0]$11408 $5\src13__data_o$next[3:0]$11412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src13__data_o$next[3:0]$11409 \dest13__data_i + case + assign $2\src13__data_o$next[3:0]$11409 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src13__data_o$next[3:0]$11410 \dest23__data_i + case + assign $3\src13__data_o$next[3:0]$11410 $2\src13__data_o$next[3:0]$11409 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src13__data_o$next[3:0]$11411 \w3__data_i + case + assign $4\src13__data_o$next[3:0]$11411 $3\src13__data_o$next[3:0]$11410 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src13__data_o$next[3:0]$11412 \reg + case + assign $5\src13__data_o$next[3:0]$11412 $4\src13__data_o$next[3:0]$11411 + end + case + assign $1\src13__data_o$next[3:0]$11408 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src13__data_o$next[3:0]$11413 4'0000 + case + assign $6\src13__data_o$next[3:0]$11413 $1\src13__data_o$next[3:0]$11408 + end + sync always + update \src13__data_o$next $0\src13__data_o$next[3:0]$11407 + end + attribute \src "libresoc.v:181178.3-181207.6" + process $proc$libresoc.v:181178$11414 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11415 $1\wr_detect$4[0:0]$11416 + attribute \src "libresoc.v:181179.5-181179.29" + switch \initial + attribute \src "libresoc.v:181179.9-181179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11416 $4\wr_detect$4[0:0]$11419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11417 1'1 + case + assign $2\wr_detect$4[0:0]$11417 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11418 1'1 + case + assign $3\wr_detect$4[0:0]$11418 $2\wr_detect$4[0:0]$11417 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11419 1'1 + case + assign $4\wr_detect$4[0:0]$11419 $3\wr_detect$4[0:0]$11418 + end + case + assign $1\wr_detect$4[0:0]$11416 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11415 + end + attribute \src "libresoc.v:181208.3-181247.6" + process $proc$libresoc.v:181208$11420 + assign { } { } + assign { } { } + assign { } { } + assign $0\src23__data_o$next[3:0]$11421 $6\src23__data_o$next[3:0]$11427 + attribute \src "libresoc.v:181209.5-181209.29" + switch \initial + attribute \src "libresoc.v:181209.9-181209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src23__data_o$next[3:0]$11422 $5\src23__data_o$next[3:0]$11426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src23__data_o$next[3:0]$11423 \dest13__data_i + case + assign $2\src23__data_o$next[3:0]$11423 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src23__data_o$next[3:0]$11424 \dest23__data_i + case + assign $3\src23__data_o$next[3:0]$11424 $2\src23__data_o$next[3:0]$11423 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src23__data_o$next[3:0]$11425 \w3__data_i + case + assign $4\src23__data_o$next[3:0]$11425 $3\src23__data_o$next[3:0]$11424 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src23__data_o$next[3:0]$11426 \reg + case + assign $5\src23__data_o$next[3:0]$11426 $4\src23__data_o$next[3:0]$11425 + end + case + assign $1\src23__data_o$next[3:0]$11422 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src23__data_o$next[3:0]$11427 4'0000 + case + assign $6\src23__data_o$next[3:0]$11427 $1\src23__data_o$next[3:0]$11422 + end + sync always + update \src23__data_o$next $0\src23__data_o$next[3:0]$11421 + end + attribute \src "libresoc.v:181248.3-181277.6" + process $proc$libresoc.v:181248$11428 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11429 $1\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:181249.5-181249.29" + switch \initial + attribute \src "libresoc.v:181249.9-181249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11430 $4\wr_detect$7[0:0]$11433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11431 1'1 + case + assign $2\wr_detect$7[0:0]$11431 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11432 1'1 + case + assign $3\wr_detect$7[0:0]$11432 $2\wr_detect$7[0:0]$11431 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11433 1'1 + case + assign $4\wr_detect$7[0:0]$11433 $3\wr_detect$7[0:0]$11432 + end + case + assign $1\wr_detect$7[0:0]$11430 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11429 + end + attribute \src "libresoc.v:181278.3-181317.6" + process $proc$libresoc.v:181278$11434 + assign { } { } + assign { } { } + assign { } { } + assign $0\src33__data_o$next[3:0]$11435 $6\src33__data_o$next[3:0]$11441 + attribute \src "libresoc.v:181279.5-181279.29" + switch \initial + attribute \src "libresoc.v:181279.9-181279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src33__data_o$next[3:0]$11436 $5\src33__data_o$next[3:0]$11440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src33__data_o$next[3:0]$11437 \dest13__data_i + case + assign $2\src33__data_o$next[3:0]$11437 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src33__data_o$next[3:0]$11438 \dest23__data_i + case + assign $3\src33__data_o$next[3:0]$11438 $2\src33__data_o$next[3:0]$11437 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src33__data_o$next[3:0]$11439 \w3__data_i + case + assign $4\src33__data_o$next[3:0]$11439 $3\src33__data_o$next[3:0]$11438 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src33__data_o$next[3:0]$11440 \reg + case + assign $5\src33__data_o$next[3:0]$11440 $4\src33__data_o$next[3:0]$11439 + end + case + assign $1\src33__data_o$next[3:0]$11436 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src33__data_o$next[3:0]$11441 4'0000 + case + assign $6\src33__data_o$next[3:0]$11441 $1\src33__data_o$next[3:0]$11436 + end + sync always + update \src33__data_o$next $0\src33__data_o$next[3:0]$11435 + end + attribute \src "libresoc.v:181318.3-181347.6" + process $proc$libresoc.v:181318$11442 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11443 $1\wr_detect$10[0:0]$11444 + attribute \src "libresoc.v:181319.5-181319.29" + switch \initial + attribute \src "libresoc.v:181319.9-181319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11444 $4\wr_detect$10[0:0]$11447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11445 1'1 + case + assign $2\wr_detect$10[0:0]$11445 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11446 1'1 + case + assign $3\wr_detect$10[0:0]$11446 $2\wr_detect$10[0:0]$11445 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11447 1'1 + case + assign $4\wr_detect$10[0:0]$11447 $3\wr_detect$10[0:0]$11446 + end + case + assign $1\wr_detect$10[0:0]$11444 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11443 + end + attribute \src "libresoc.v:181348.3-181387.6" + process $proc$libresoc.v:181348$11448 + assign { } { } + assign { } { } + assign { } { } + assign $0\r3__data_o$next[3:0]$11449 $6\r3__data_o$next[3:0]$11455 + attribute \src "libresoc.v:181349.5-181349.29" + switch \initial + attribute \src "libresoc.v:181349.9-181349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r3__data_o$next[3:0]$11450 $5\r3__data_o$next[3:0]$11454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r3__data_o$next[3:0]$11451 \dest13__data_i + case + assign $2\r3__data_o$next[3:0]$11451 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r3__data_o$next[3:0]$11452 \dest23__data_i + case + assign $3\r3__data_o$next[3:0]$11452 $2\r3__data_o$next[3:0]$11451 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r3__data_o$next[3:0]$11453 \w3__data_i + case + assign $4\r3__data_o$next[3:0]$11453 $3\r3__data_o$next[3:0]$11452 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r3__data_o$next[3:0]$11454 \reg + case + assign $5\r3__data_o$next[3:0]$11454 $4\r3__data_o$next[3:0]$11453 + end + case + assign $1\r3__data_o$next[3:0]$11450 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r3__data_o$next[3:0]$11455 4'0000 + case + assign $6\r3__data_o$next[3:0]$11455 $1\r3__data_o$next[3:0]$11450 + end + sync always + update \r3__data_o$next $0\r3__data_o$next[3:0]$11449 + end + attribute \src "libresoc.v:181388.3-181417.6" + process $proc$libresoc.v:181388$11456 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11457 $1\wr_detect$13[0:0]$11458 + attribute \src "libresoc.v:181389.5-181389.29" + switch \initial + attribute \src "libresoc.v:181389.9-181389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11458 $4\wr_detect$13[0:0]$11461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11459 1'1 + case + assign $2\wr_detect$13[0:0]$11459 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11460 1'1 + case + assign $3\wr_detect$13[0:0]$11460 $2\wr_detect$13[0:0]$11459 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11461 1'1 + case + assign $4\wr_detect$13[0:0]$11461 $3\wr_detect$13[0:0]$11460 + end + case + assign $1\wr_detect$13[0:0]$11458 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11457 + end + connect \$9 $not$libresoc.v:180951$11364_Y + connect \$12 $not$libresoc.v:180952$11365_Y + connect \$15 $not$libresoc.v:180953$11366_Y + connect \$1 $not$libresoc.v:180954$11367_Y + connect \$3 $not$libresoc.v:180955$11368_Y + connect \$6 $not$libresoc.v:180956$11369_Y +end +attribute \src "libresoc.v:181422.1-181977.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" +attribute \generator "nMigen" +module \reg_4 + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $0\cr_pred4__data_o$next[3:0]$11484 + attribute \src "libresoc.v:181528.3-181529.49" + wire width 4 $0\cr_pred4__data_o[3:0] + attribute \src "libresoc.v:181423.7-181423.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $0\r24__data_o$next[3:0]$11493 + attribute \src "libresoc.v:181518.3-181519.39" + wire width 4 $0\r24__data_o[3:0] + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $0\r4__data_o$next[3:0]$11555 + attribute \src "libresoc.v:181520.3-181521.37" + wire width 4 $0\r4__data_o[3:0] + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $0\reg$next[3:0]$11507 + attribute \src "libresoc.v:181516.3-181517.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $0\src14__data_o$next[3:0]$11513 + attribute \src "libresoc.v:181526.3-181527.43" + wire width 4 $0\src14__data_o[3:0] + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $0\src24__data_o$next[3:0]$11527 + attribute \src "libresoc.v:181524.3-181525.43" + wire width 4 $0\src24__data_o[3:0] + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $0\src34__data_o$next[3:0]$11541 + attribute \src "libresoc.v:181522.3-181523.43" + wire width 4 $0\src34__data_o[3:0] + attribute \src "libresoc.v:181877.3-181906.6" + wire $0\wr_detect$10[0:0]$11549 + attribute \src "libresoc.v:181947.3-181976.6" + wire $0\wr_detect$13[0:0]$11563 + attribute \src "libresoc.v:181640.3-181669.6" + wire $0\wr_detect$16[0:0]$11501 + attribute \src "libresoc.v:181737.3-181766.6" + wire $0\wr_detect$4[0:0]$11521 + attribute \src "libresoc.v:181807.3-181836.6" + wire $0\wr_detect$7[0:0]$11535 + attribute \src "libresoc.v:181570.3-181599.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $1\cr_pred4__data_o$next[3:0]$11485 + attribute \src "libresoc.v:181442.13-181442.36" + wire width 4 $1\cr_pred4__data_o[3:0] + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $1\r24__data_o$next[3:0]$11494 + attribute \src "libresoc.v:181457.13-181457.31" + wire width 4 $1\r24__data_o[3:0] + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $1\r4__data_o$next[3:0]$11556 + attribute \src "libresoc.v:181464.13-181464.30" + wire width 4 $1\r4__data_o[3:0] + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $1\reg$next[3:0]$11508 + attribute \src "libresoc.v:181470.13-181470.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $1\src14__data_o$next[3:0]$11514 + attribute \src "libresoc.v:181475.13-181475.33" + wire width 4 $1\src14__data_o[3:0] + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $1\src24__data_o$next[3:0]$11528 + attribute \src "libresoc.v:181482.13-181482.33" + wire width 4 $1\src24__data_o[3:0] + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $1\src34__data_o$next[3:0]$11542 + attribute \src "libresoc.v:181489.13-181489.33" + wire width 4 $1\src34__data_o[3:0] + attribute \src "libresoc.v:181877.3-181906.6" + wire $1\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:181947.3-181976.6" + wire $1\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:181640.3-181669.6" + wire $1\wr_detect$16[0:0]$11502 + attribute \src "libresoc.v:181737.3-181766.6" + wire $1\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:181807.3-181836.6" + wire $1\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:181570.3-181599.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $2\cr_pred4__data_o$next[3:0]$11486 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $2\r24__data_o$next[3:0]$11495 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $2\r4__data_o$next[3:0]$11557 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $2\reg$next[3:0]$11509 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $2\src14__data_o$next[3:0]$11515 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $2\src24__data_o$next[3:0]$11529 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $2\src34__data_o$next[3:0]$11543 + attribute \src "libresoc.v:181877.3-181906.6" + wire $2\wr_detect$10[0:0]$11551 + attribute \src "libresoc.v:181947.3-181976.6" + wire $2\wr_detect$13[0:0]$11565 + attribute \src "libresoc.v:181640.3-181669.6" + wire $2\wr_detect$16[0:0]$11503 + attribute \src "libresoc.v:181737.3-181766.6" + wire $2\wr_detect$4[0:0]$11523 + attribute \src "libresoc.v:181807.3-181836.6" + wire $2\wr_detect$7[0:0]$11537 + attribute \src "libresoc.v:181570.3-181599.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $3\cr_pred4__data_o$next[3:0]$11487 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $3\r24__data_o$next[3:0]$11496 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $3\r4__data_o$next[3:0]$11558 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $3\reg$next[3:0]$11510 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $3\src14__data_o$next[3:0]$11516 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $3\src24__data_o$next[3:0]$11530 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $3\src34__data_o$next[3:0]$11544 + attribute \src "libresoc.v:181877.3-181906.6" + wire $3\wr_detect$10[0:0]$11552 + attribute \src "libresoc.v:181947.3-181976.6" + wire $3\wr_detect$13[0:0]$11566 + attribute \src "libresoc.v:181640.3-181669.6" + wire $3\wr_detect$16[0:0]$11504 + attribute \src "libresoc.v:181737.3-181766.6" + wire $3\wr_detect$4[0:0]$11524 + attribute \src "libresoc.v:181807.3-181836.6" + wire $3\wr_detect$7[0:0]$11538 + attribute \src "libresoc.v:181570.3-181599.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $4\cr_pred4__data_o$next[3:0]$11488 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $4\r24__data_o$next[3:0]$11497 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $4\r4__data_o$next[3:0]$11559 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $4\reg$next[3:0]$11511 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $4\src14__data_o$next[3:0]$11517 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $4\src24__data_o$next[3:0]$11531 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $4\src34__data_o$next[3:0]$11545 + attribute \src "libresoc.v:181877.3-181906.6" + wire $4\wr_detect$10[0:0]$11553 + attribute \src "libresoc.v:181947.3-181976.6" + wire $4\wr_detect$13[0:0]$11567 + attribute \src "libresoc.v:181640.3-181669.6" + wire $4\wr_detect$16[0:0]$11505 + attribute \src "libresoc.v:181737.3-181766.6" + wire $4\wr_detect$4[0:0]$11525 + attribute \src "libresoc.v:181807.3-181836.6" + wire $4\wr_detect$7[0:0]$11539 + attribute \src "libresoc.v:181570.3-181599.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $5\cr_pred4__data_o$next[3:0]$11489 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $5\r24__data_o$next[3:0]$11498 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $5\r4__data_o$next[3:0]$11560 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $5\src14__data_o$next[3:0]$11518 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $5\src24__data_o$next[3:0]$11532 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $5\src34__data_o$next[3:0]$11546 + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $6\cr_pred4__data_o$next[3:0]$11490 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $6\r24__data_o$next[3:0]$11499 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $6\r4__data_o$next[3:0]$11561 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $6\src14__data_o$next[3:0]$11519 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $6\src24__data_o$next[3:0]$11533 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $6\src34__data_o$next[3:0]$11547 + attribute \src "libresoc.v:181510.17-181510.104" + wire $not$libresoc.v:181510$11470_Y + attribute \src "libresoc.v:181511.18-181511.105" + wire $not$libresoc.v:181511$11471_Y + attribute \src "libresoc.v:181512.18-181512.105" + wire $not$libresoc.v:181512$11472_Y + attribute \src "libresoc.v:181513.17-181513.100" + wire $not$libresoc.v:181513$11473_Y + attribute \src "libresoc.v:181514.17-181514.103" + wire $not$libresoc.v:181514$11474_Y + attribute \src "libresoc.v:181515.17-181515.103" + wire $not$libresoc.v:181515$11475_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest24__wen + attribute \src "libresoc.v:181423.7-181423.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src14__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src34__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181510$11470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:181510$11470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181511$11471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:181511$11471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181512$11472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:181512$11472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181513$11473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:181513$11473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181514$11474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:181514$11474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181515$11475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:181515$11475_Y + end + attribute \src "libresoc.v:181423.7-181423.20" + process $proc$libresoc.v:181423$11568 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181442.13-181442.36" + process $proc$libresoc.v:181442$11569 + assign { } { } + assign $1\cr_pred4__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred4__data_o $1\cr_pred4__data_o[3:0] + end + attribute \src "libresoc.v:181457.13-181457.31" + process $proc$libresoc.v:181457$11570 + assign { } { } + assign $1\r24__data_o[3:0] 4'0000 + sync always + sync init + update \r24__data_o $1\r24__data_o[3:0] + end + attribute \src "libresoc.v:181464.13-181464.30" + process $proc$libresoc.v:181464$11571 + assign { } { } + assign $1\r4__data_o[3:0] 4'0000 + sync always + sync init + update \r4__data_o $1\r4__data_o[3:0] + end + attribute \src "libresoc.v:181470.13-181470.25" + process $proc$libresoc.v:181470$11572 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:181475.13-181475.33" + process $proc$libresoc.v:181475$11573 + assign { } { } + assign $1\src14__data_o[3:0] 4'0000 + sync always + sync init + update \src14__data_o $1\src14__data_o[3:0] + end + attribute \src "libresoc.v:181482.13-181482.33" + process $proc$libresoc.v:181482$11574 + assign { } { } + assign $1\src24__data_o[3:0] 4'0000 + sync always + sync init + update \src24__data_o $1\src24__data_o[3:0] + end + attribute \src "libresoc.v:181489.13-181489.33" + process $proc$libresoc.v:181489$11575 + assign { } { } + assign $1\src34__data_o[3:0] 4'0000 + sync always + sync init + update \src34__data_o $1\src34__data_o[3:0] + end + attribute \src "libresoc.v:181516.3-181517.25" + process $proc$libresoc.v:181516$11476 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:181518.3-181519.39" + process $proc$libresoc.v:181518$11477 + assign { } { } + assign $0\r24__data_o[3:0] \r24__data_o$next + sync posedge \coresync_clk + update \r24__data_o $0\r24__data_o[3:0] + end + attribute \src "libresoc.v:181520.3-181521.37" + process $proc$libresoc.v:181520$11478 + assign { } { } + assign $0\r4__data_o[3:0] \r4__data_o$next + sync posedge \coresync_clk + update \r4__data_o $0\r4__data_o[3:0] + end + attribute \src "libresoc.v:181522.3-181523.43" + process $proc$libresoc.v:181522$11479 + assign { } { } + assign $0\src34__data_o[3:0] \src34__data_o$next + sync posedge \coresync_clk + update \src34__data_o $0\src34__data_o[3:0] + end + attribute \src "libresoc.v:181524.3-181525.43" + process $proc$libresoc.v:181524$11480 + assign { } { } + assign $0\src24__data_o[3:0] \src24__data_o$next + sync posedge \coresync_clk + update \src24__data_o $0\src24__data_o[3:0] + end + attribute \src "libresoc.v:181526.3-181527.43" + process $proc$libresoc.v:181526$11481 + assign { } { } + assign $0\src14__data_o[3:0] \src14__data_o$next + sync posedge \coresync_clk + update \src14__data_o $0\src14__data_o[3:0] + end + attribute \src "libresoc.v:181528.3-181529.49" + process $proc$libresoc.v:181528$11482 + assign { } { } + assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next + sync posedge \coresync_clk + update \cr_pred4__data_o $0\cr_pred4__data_o[3:0] + end + attribute \src "libresoc.v:181530.3-181569.6" + process $proc$libresoc.v:181530$11483 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred4__data_o$next[3:0]$11484 $6\cr_pred4__data_o$next[3:0]$11490 + attribute \src "libresoc.v:181531.5-181531.29" + switch \initial + attribute \src "libresoc.v:181531.9-181531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred4__data_o$next[3:0]$11485 $5\cr_pred4__data_o$next[3:0]$11489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred4__data_o$next[3:0]$11486 \dest14__data_i + case + assign $2\cr_pred4__data_o$next[3:0]$11486 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred4__data_o$next[3:0]$11487 \dest24__data_i + case + assign $3\cr_pred4__data_o$next[3:0]$11487 $2\cr_pred4__data_o$next[3:0]$11486 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred4__data_o$next[3:0]$11488 \w4__data_i + case + assign $4\cr_pred4__data_o$next[3:0]$11488 $3\cr_pred4__data_o$next[3:0]$11487 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred4__data_o$next[3:0]$11489 \reg + case + assign $5\cr_pred4__data_o$next[3:0]$11489 $4\cr_pred4__data_o$next[3:0]$11488 + end + case + assign $1\cr_pred4__data_o$next[3:0]$11485 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred4__data_o$next[3:0]$11490 4'0000 + case + assign $6\cr_pred4__data_o$next[3:0]$11490 $1\cr_pred4__data_o$next[3:0]$11485 + end + sync always + update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11484 + end + attribute \src "libresoc.v:181570.3-181599.6" + process $proc$libresoc.v:181570$11491 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:181571.5-181571.29" + switch \initial + attribute \src "libresoc.v:181571.9-181571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:181600.3-181639.6" + process $proc$libresoc.v:181600$11492 + assign { } { } + assign { } { } + assign { } { } + assign $0\r24__data_o$next[3:0]$11493 $6\r24__data_o$next[3:0]$11499 + attribute \src "libresoc.v:181601.5-181601.29" + switch \initial + attribute \src "libresoc.v:181601.9-181601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r24__data_o$next[3:0]$11494 $5\r24__data_o$next[3:0]$11498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$11495 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$11495 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$11496 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$11496 $2\r24__data_o$next[3:0]$11495 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$11497 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$11497 $3\r24__data_o$next[3:0]$11496 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$11498 \reg + case + assign $5\r24__data_o$next[3:0]$11498 $4\r24__data_o$next[3:0]$11497 + end + case + assign $1\r24__data_o$next[3:0]$11494 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r24__data_o$next[3:0]$11499 4'0000 + case + assign $6\r24__data_o$next[3:0]$11499 $1\r24__data_o$next[3:0]$11494 + end + sync always + update \r24__data_o$next $0\r24__data_o$next[3:0]$11493 + end + attribute \src "libresoc.v:181640.3-181669.6" + process $proc$libresoc.v:181640$11500 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11501 $1\wr_detect$16[0:0]$11502 + attribute \src "libresoc.v:181641.5-181641.29" + switch \initial + attribute \src "libresoc.v:181641.9-181641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11502 $4\wr_detect$16[0:0]$11505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11503 1'1 + case + assign $2\wr_detect$16[0:0]$11503 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11504 1'1 + case + assign $3\wr_detect$16[0:0]$11504 $2\wr_detect$16[0:0]$11503 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11505 1'1 + case + assign $4\wr_detect$16[0:0]$11505 $3\wr_detect$16[0:0]$11504 + end + case + assign $1\wr_detect$16[0:0]$11502 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11501 + end + attribute \src "libresoc.v:181670.3-181696.6" + process $proc$libresoc.v:181670$11506 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11507 $4\reg$next[3:0]$11511 + attribute \src "libresoc.v:181671.5-181671.29" + switch \initial + attribute \src "libresoc.v:181671.9-181671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11508 \dest14__data_i + case + assign $1\reg$next[3:0]$11508 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11509 \dest24__data_i + case + assign $2\reg$next[3:0]$11509 $1\reg$next[3:0]$11508 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11510 \w4__data_i + case + assign $3\reg$next[3:0]$11510 $2\reg$next[3:0]$11509 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11511 4'0000 + case + assign $4\reg$next[3:0]$11511 $3\reg$next[3:0]$11510 + end + sync always + update \reg$next $0\reg$next[3:0]$11507 + end + attribute \src "libresoc.v:181697.3-181736.6" + process $proc$libresoc.v:181697$11512 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$11513 $6\src14__data_o$next[3:0]$11519 + attribute \src "libresoc.v:181698.5-181698.29" + switch \initial + attribute \src "libresoc.v:181698.9-181698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$11514 $5\src14__data_o$next[3:0]$11518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$11515 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$11515 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$11516 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$11516 $2\src14__data_o$next[3:0]$11515 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$11517 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$11517 $3\src14__data_o$next[3:0]$11516 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src14__data_o$next[3:0]$11518 \reg + case + assign $5\src14__data_o$next[3:0]$11518 $4\src14__data_o$next[3:0]$11517 + end + case + assign $1\src14__data_o$next[3:0]$11514 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src14__data_o$next[3:0]$11519 4'0000 + case + assign $6\src14__data_o$next[3:0]$11519 $1\src14__data_o$next[3:0]$11514 + end + sync always + update \src14__data_o$next $0\src14__data_o$next[3:0]$11513 + end + attribute \src "libresoc.v:181737.3-181766.6" + process $proc$libresoc.v:181737$11520 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11521 $1\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:181738.5-181738.29" + switch \initial + attribute \src "libresoc.v:181738.9-181738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11522 $4\wr_detect$4[0:0]$11525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11523 1'1 + case + assign $2\wr_detect$4[0:0]$11523 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11524 1'1 + case + assign $3\wr_detect$4[0:0]$11524 $2\wr_detect$4[0:0]$11523 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11525 1'1 + case + assign $4\wr_detect$4[0:0]$11525 $3\wr_detect$4[0:0]$11524 + end + case + assign $1\wr_detect$4[0:0]$11522 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11521 + end + attribute \src "libresoc.v:181767.3-181806.6" + process $proc$libresoc.v:181767$11526 + assign { } { } + assign { } { } + assign { } { } + assign $0\src24__data_o$next[3:0]$11527 $6\src24__data_o$next[3:0]$11533 + attribute \src "libresoc.v:181768.5-181768.29" + switch \initial + attribute \src "libresoc.v:181768.9-181768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src24__data_o$next[3:0]$11528 $5\src24__data_o$next[3:0]$11532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src24__data_o$next[3:0]$11529 \dest14__data_i + case + assign $2\src24__data_o$next[3:0]$11529 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src24__data_o$next[3:0]$11530 \dest24__data_i + case + assign $3\src24__data_o$next[3:0]$11530 $2\src24__data_o$next[3:0]$11529 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src24__data_o$next[3:0]$11531 \w4__data_i + case + assign $4\src24__data_o$next[3:0]$11531 $3\src24__data_o$next[3:0]$11530 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src24__data_o$next[3:0]$11532 \reg + case + assign $5\src24__data_o$next[3:0]$11532 $4\src24__data_o$next[3:0]$11531 + end + case + assign $1\src24__data_o$next[3:0]$11528 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src24__data_o$next[3:0]$11533 4'0000 + case + assign $6\src24__data_o$next[3:0]$11533 $1\src24__data_o$next[3:0]$11528 + end + sync always + update \src24__data_o$next $0\src24__data_o$next[3:0]$11527 + end + attribute \src "libresoc.v:181807.3-181836.6" + process $proc$libresoc.v:181807$11534 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11535 $1\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:181808.5-181808.29" + switch \initial + attribute \src "libresoc.v:181808.9-181808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11536 $4\wr_detect$7[0:0]$11539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11537 1'1 + case + assign $2\wr_detect$7[0:0]$11537 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11538 1'1 + case + assign $3\wr_detect$7[0:0]$11538 $2\wr_detect$7[0:0]$11537 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11539 1'1 + case + assign $4\wr_detect$7[0:0]$11539 $3\wr_detect$7[0:0]$11538 + end + case + assign $1\wr_detect$7[0:0]$11536 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11535 + end + attribute \src "libresoc.v:181837.3-181876.6" + process $proc$libresoc.v:181837$11540 + assign { } { } + assign { } { } + assign { } { } + assign $0\src34__data_o$next[3:0]$11541 $6\src34__data_o$next[3:0]$11547 + attribute \src "libresoc.v:181838.5-181838.29" + switch \initial + attribute \src "libresoc.v:181838.9-181838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src34__data_o$next[3:0]$11542 $5\src34__data_o$next[3:0]$11546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src34__data_o$next[3:0]$11543 \dest14__data_i + case + assign $2\src34__data_o$next[3:0]$11543 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src34__data_o$next[3:0]$11544 \dest24__data_i + case + assign $3\src34__data_o$next[3:0]$11544 $2\src34__data_o$next[3:0]$11543 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src34__data_o$next[3:0]$11545 \w4__data_i + case + assign $4\src34__data_o$next[3:0]$11545 $3\src34__data_o$next[3:0]$11544 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src34__data_o$next[3:0]$11546 \reg + case + assign $5\src34__data_o$next[3:0]$11546 $4\src34__data_o$next[3:0]$11545 + end + case + assign $1\src34__data_o$next[3:0]$11542 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src34__data_o$next[3:0]$11547 4'0000 + case + assign $6\src34__data_o$next[3:0]$11547 $1\src34__data_o$next[3:0]$11542 + end + sync always + update \src34__data_o$next $0\src34__data_o$next[3:0]$11541 + end + attribute \src "libresoc.v:181877.3-181906.6" + process $proc$libresoc.v:181877$11548 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11549 $1\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:181878.5-181878.29" + switch \initial + attribute \src "libresoc.v:181878.9-181878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11550 $4\wr_detect$10[0:0]$11553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11551 1'1 + case + assign $2\wr_detect$10[0:0]$11551 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11552 1'1 + case + assign $3\wr_detect$10[0:0]$11552 $2\wr_detect$10[0:0]$11551 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11553 1'1 + case + assign $4\wr_detect$10[0:0]$11553 $3\wr_detect$10[0:0]$11552 + end + case + assign $1\wr_detect$10[0:0]$11550 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11549 + end + attribute \src "libresoc.v:181907.3-181946.6" + process $proc$libresoc.v:181907$11554 + assign { } { } + assign { } { } + assign { } { } + assign $0\r4__data_o$next[3:0]$11555 $6\r4__data_o$next[3:0]$11561 + attribute \src "libresoc.v:181908.5-181908.29" + switch \initial + attribute \src "libresoc.v:181908.9-181908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r4__data_o$next[3:0]$11556 $5\r4__data_o$next[3:0]$11560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r4__data_o$next[3:0]$11557 \dest14__data_i + case + assign $2\r4__data_o$next[3:0]$11557 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r4__data_o$next[3:0]$11558 \dest24__data_i + case + assign $3\r4__data_o$next[3:0]$11558 $2\r4__data_o$next[3:0]$11557 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r4__data_o$next[3:0]$11559 \w4__data_i + case + assign $4\r4__data_o$next[3:0]$11559 $3\r4__data_o$next[3:0]$11558 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r4__data_o$next[3:0]$11560 \reg + case + assign $5\r4__data_o$next[3:0]$11560 $4\r4__data_o$next[3:0]$11559 + end + case + assign $1\r4__data_o$next[3:0]$11556 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r4__data_o$next[3:0]$11561 4'0000 + case + assign $6\r4__data_o$next[3:0]$11561 $1\r4__data_o$next[3:0]$11556 + end + sync always + update \r4__data_o$next $0\r4__data_o$next[3:0]$11555 + end + attribute \src "libresoc.v:181947.3-181976.6" + process $proc$libresoc.v:181947$11562 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11563 $1\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:181948.5-181948.29" + switch \initial + attribute \src "libresoc.v:181948.9-181948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11564 $4\wr_detect$13[0:0]$11567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11565 1'1 + case + assign $2\wr_detect$13[0:0]$11565 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11566 1'1 + case + assign $3\wr_detect$13[0:0]$11566 $2\wr_detect$13[0:0]$11565 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11567 1'1 + case + assign $4\wr_detect$13[0:0]$11567 $3\wr_detect$13[0:0]$11566 + end + case + assign $1\wr_detect$13[0:0]$11564 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11563 + end + connect \$9 $not$libresoc.v:181510$11470_Y + connect \$12 $not$libresoc.v:181511$11471_Y + connect \$15 $not$libresoc.v:181512$11472_Y + connect \$1 $not$libresoc.v:181513$11473_Y + connect \$3 $not$libresoc.v:181514$11474_Y + connect \$6 $not$libresoc.v:181515$11475_Y +end +attribute \src "libresoc.v:181981.1-182536.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" +attribute \generator "nMigen" +module \reg_5 + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $0\cr_pred5__data_o$next[3:0]$11590 + attribute \src "libresoc.v:182087.3-182088.49" + wire width 4 $0\cr_pred5__data_o[3:0] + attribute \src "libresoc.v:181982.7-181982.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $0\r25__data_o$next[3:0]$11599 + attribute \src "libresoc.v:182077.3-182078.39" + wire width 4 $0\r25__data_o[3:0] + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $0\r5__data_o$next[3:0]$11661 + attribute \src "libresoc.v:182079.3-182080.37" + wire width 4 $0\r5__data_o[3:0] + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $0\reg$next[3:0]$11613 + attribute \src "libresoc.v:182075.3-182076.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $0\src15__data_o$next[3:0]$11619 + attribute \src "libresoc.v:182085.3-182086.43" + wire width 4 $0\src15__data_o[3:0] + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $0\src25__data_o$next[3:0]$11633 + attribute \src "libresoc.v:182083.3-182084.43" + wire width 4 $0\src25__data_o[3:0] + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $0\src35__data_o$next[3:0]$11647 + attribute \src "libresoc.v:182081.3-182082.43" + wire width 4 $0\src35__data_o[3:0] + attribute \src "libresoc.v:182436.3-182465.6" + wire $0\wr_detect$10[0:0]$11655 + attribute \src "libresoc.v:182506.3-182535.6" + wire $0\wr_detect$13[0:0]$11669 + attribute \src "libresoc.v:182199.3-182228.6" + wire $0\wr_detect$16[0:0]$11607 + attribute \src "libresoc.v:182296.3-182325.6" + wire $0\wr_detect$4[0:0]$11627 + attribute \src "libresoc.v:182366.3-182395.6" + wire $0\wr_detect$7[0:0]$11641 + attribute \src "libresoc.v:182129.3-182158.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $1\cr_pred5__data_o$next[3:0]$11591 + attribute \src "libresoc.v:182001.13-182001.36" + wire width 4 $1\cr_pred5__data_o[3:0] + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $1\r25__data_o$next[3:0]$11600 + attribute \src "libresoc.v:182016.13-182016.31" + wire width 4 $1\r25__data_o[3:0] + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $1\r5__data_o$next[3:0]$11662 + attribute \src "libresoc.v:182023.13-182023.30" + wire width 4 $1\r5__data_o[3:0] + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $1\reg$next[3:0]$11614 + attribute \src "libresoc.v:182029.13-182029.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $1\src15__data_o$next[3:0]$11620 + attribute \src "libresoc.v:182034.13-182034.33" + wire width 4 $1\src15__data_o[3:0] + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $1\src25__data_o$next[3:0]$11634 + attribute \src "libresoc.v:182041.13-182041.33" + wire width 4 $1\src25__data_o[3:0] + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $1\src35__data_o$next[3:0]$11648 + attribute \src "libresoc.v:182048.13-182048.33" + wire width 4 $1\src35__data_o[3:0] + attribute \src "libresoc.v:182436.3-182465.6" + wire $1\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:182506.3-182535.6" + wire $1\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:182199.3-182228.6" + wire $1\wr_detect$16[0:0]$11608 + attribute \src "libresoc.v:182296.3-182325.6" + wire $1\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:182366.3-182395.6" + wire $1\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:182129.3-182158.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $2\cr_pred5__data_o$next[3:0]$11592 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $2\r25__data_o$next[3:0]$11601 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $2\r5__data_o$next[3:0]$11663 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $2\reg$next[3:0]$11615 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $2\src15__data_o$next[3:0]$11621 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $2\src25__data_o$next[3:0]$11635 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $2\src35__data_o$next[3:0]$11649 + attribute \src "libresoc.v:182436.3-182465.6" + wire $2\wr_detect$10[0:0]$11657 + attribute \src "libresoc.v:182506.3-182535.6" + wire $2\wr_detect$13[0:0]$11671 + attribute \src "libresoc.v:182199.3-182228.6" + wire $2\wr_detect$16[0:0]$11609 + attribute \src "libresoc.v:182296.3-182325.6" + wire $2\wr_detect$4[0:0]$11629 + attribute \src "libresoc.v:182366.3-182395.6" + wire $2\wr_detect$7[0:0]$11643 + attribute \src "libresoc.v:182129.3-182158.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $3\cr_pred5__data_o$next[3:0]$11593 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $3\r25__data_o$next[3:0]$11602 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $3\r5__data_o$next[3:0]$11664 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $3\reg$next[3:0]$11616 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $3\src15__data_o$next[3:0]$11622 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $3\src25__data_o$next[3:0]$11636 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $3\src35__data_o$next[3:0]$11650 + attribute \src "libresoc.v:182436.3-182465.6" + wire $3\wr_detect$10[0:0]$11658 + attribute \src "libresoc.v:182506.3-182535.6" + wire $3\wr_detect$13[0:0]$11672 + attribute \src "libresoc.v:182199.3-182228.6" + wire $3\wr_detect$16[0:0]$11610 + attribute \src "libresoc.v:182296.3-182325.6" + wire $3\wr_detect$4[0:0]$11630 + attribute \src "libresoc.v:182366.3-182395.6" + wire $3\wr_detect$7[0:0]$11644 + attribute \src "libresoc.v:182129.3-182158.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $4\cr_pred5__data_o$next[3:0]$11594 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $4\r25__data_o$next[3:0]$11603 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $4\r5__data_o$next[3:0]$11665 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $4\reg$next[3:0]$11617 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $4\src15__data_o$next[3:0]$11623 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $4\src25__data_o$next[3:0]$11637 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $4\src35__data_o$next[3:0]$11651 + attribute \src "libresoc.v:182436.3-182465.6" + wire $4\wr_detect$10[0:0]$11659 + attribute \src "libresoc.v:182506.3-182535.6" + wire $4\wr_detect$13[0:0]$11673 + attribute \src "libresoc.v:182199.3-182228.6" + wire $4\wr_detect$16[0:0]$11611 + attribute \src "libresoc.v:182296.3-182325.6" + wire $4\wr_detect$4[0:0]$11631 + attribute \src "libresoc.v:182366.3-182395.6" + wire $4\wr_detect$7[0:0]$11645 + attribute \src "libresoc.v:182129.3-182158.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $5\cr_pred5__data_o$next[3:0]$11595 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $5\r25__data_o$next[3:0]$11604 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $5\r5__data_o$next[3:0]$11666 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $5\src15__data_o$next[3:0]$11624 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $5\src25__data_o$next[3:0]$11638 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $5\src35__data_o$next[3:0]$11652 + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $6\cr_pred5__data_o$next[3:0]$11596 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $6\r25__data_o$next[3:0]$11605 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $6\r5__data_o$next[3:0]$11667 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $6\src15__data_o$next[3:0]$11625 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $6\src25__data_o$next[3:0]$11639 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $6\src35__data_o$next[3:0]$11653 + attribute \src "libresoc.v:182069.17-182069.104" + wire $not$libresoc.v:182069$11576_Y + attribute \src "libresoc.v:182070.18-182070.105" + wire $not$libresoc.v:182070$11577_Y + attribute \src "libresoc.v:182071.18-182071.105" + wire $not$libresoc.v:182071$11578_Y + attribute \src "libresoc.v:182072.17-182072.100" + wire $not$libresoc.v:182072$11579_Y + attribute \src "libresoc.v:182073.17-182073.103" + wire $not$libresoc.v:182073$11580_Y + attribute \src "libresoc.v:182074.17-182074.103" + wire $not$libresoc.v:182074$11581_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest25__wen + attribute \src "libresoc.v:181982.7-181982.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src15__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src35__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182069$11576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:182069$11576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182070$11577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:182070$11577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182071$11578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:182071$11578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182072$11579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:182072$11579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182073$11580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:182073$11580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182074$11581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:182074$11581_Y + end + attribute \src "libresoc.v:181982.7-181982.20" + process $proc$libresoc.v:181982$11674 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182001.13-182001.36" + process $proc$libresoc.v:182001$11675 + assign { } { } + assign $1\cr_pred5__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred5__data_o $1\cr_pred5__data_o[3:0] + end + attribute \src "libresoc.v:182016.13-182016.31" + process $proc$libresoc.v:182016$11676 + assign { } { } + assign $1\r25__data_o[3:0] 4'0000 + sync always + sync init + update \r25__data_o $1\r25__data_o[3:0] + end + attribute \src "libresoc.v:182023.13-182023.30" + process $proc$libresoc.v:182023$11677 + assign { } { } + assign $1\r5__data_o[3:0] 4'0000 + sync always + sync init + update \r5__data_o $1\r5__data_o[3:0] + end + attribute \src "libresoc.v:182029.13-182029.25" + process $proc$libresoc.v:182029$11678 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:182034.13-182034.33" + process $proc$libresoc.v:182034$11679 + assign { } { } + assign $1\src15__data_o[3:0] 4'0000 + sync always + sync init + update \src15__data_o $1\src15__data_o[3:0] + end + attribute \src "libresoc.v:182041.13-182041.33" + process $proc$libresoc.v:182041$11680 + assign { } { } + assign $1\src25__data_o[3:0] 4'0000 + sync always + sync init + update \src25__data_o $1\src25__data_o[3:0] + end + attribute \src "libresoc.v:182048.13-182048.33" + process $proc$libresoc.v:182048$11681 + assign { } { } + assign $1\src35__data_o[3:0] 4'0000 + sync always + sync init + update \src35__data_o $1\src35__data_o[3:0] + end + attribute \src "libresoc.v:182075.3-182076.25" + process $proc$libresoc.v:182075$11582 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:182077.3-182078.39" + process $proc$libresoc.v:182077$11583 + assign { } { } + assign $0\r25__data_o[3:0] \r25__data_o$next + sync posedge \coresync_clk + update \r25__data_o $0\r25__data_o[3:0] + end + attribute \src "libresoc.v:182079.3-182080.37" + process $proc$libresoc.v:182079$11584 + assign { } { } + assign $0\r5__data_o[3:0] \r5__data_o$next + sync posedge \coresync_clk + update \r5__data_o $0\r5__data_o[3:0] + end + attribute \src "libresoc.v:182081.3-182082.43" + process $proc$libresoc.v:182081$11585 + assign { } { } + assign $0\src35__data_o[3:0] \src35__data_o$next + sync posedge \coresync_clk + update \src35__data_o $0\src35__data_o[3:0] + end + attribute \src "libresoc.v:182083.3-182084.43" + process $proc$libresoc.v:182083$11586 + assign { } { } + assign $0\src25__data_o[3:0] \src25__data_o$next + sync posedge \coresync_clk + update \src25__data_o $0\src25__data_o[3:0] + end + attribute \src "libresoc.v:182085.3-182086.43" + process $proc$libresoc.v:182085$11587 + assign { } { } + assign $0\src15__data_o[3:0] \src15__data_o$next + sync posedge \coresync_clk + update \src15__data_o $0\src15__data_o[3:0] + end + attribute \src "libresoc.v:182087.3-182088.49" + process $proc$libresoc.v:182087$11588 + assign { } { } + assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next + sync posedge \coresync_clk + update \cr_pred5__data_o $0\cr_pred5__data_o[3:0] + end + attribute \src "libresoc.v:182089.3-182128.6" + process $proc$libresoc.v:182089$11589 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred5__data_o$next[3:0]$11590 $6\cr_pred5__data_o$next[3:0]$11596 + attribute \src "libresoc.v:182090.5-182090.29" + switch \initial + attribute \src "libresoc.v:182090.9-182090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred5__data_o$next[3:0]$11591 $5\cr_pred5__data_o$next[3:0]$11595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred5__data_o$next[3:0]$11592 \dest15__data_i + case + assign $2\cr_pred5__data_o$next[3:0]$11592 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred5__data_o$next[3:0]$11593 \dest25__data_i + case + assign $3\cr_pred5__data_o$next[3:0]$11593 $2\cr_pred5__data_o$next[3:0]$11592 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred5__data_o$next[3:0]$11594 \w5__data_i + case + assign $4\cr_pred5__data_o$next[3:0]$11594 $3\cr_pred5__data_o$next[3:0]$11593 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred5__data_o$next[3:0]$11595 \reg + case + assign $5\cr_pred5__data_o$next[3:0]$11595 $4\cr_pred5__data_o$next[3:0]$11594 + end + case + assign $1\cr_pred5__data_o$next[3:0]$11591 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred5__data_o$next[3:0]$11596 4'0000 + case + assign $6\cr_pred5__data_o$next[3:0]$11596 $1\cr_pred5__data_o$next[3:0]$11591 + end + sync always + update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11590 + end + attribute \src "libresoc.v:182129.3-182158.6" + process $proc$libresoc.v:182129$11597 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:182130.5-182130.29" + switch \initial + attribute \src "libresoc.v:182130.9-182130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:182159.3-182198.6" + process $proc$libresoc.v:182159$11598 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$11599 $6\r25__data_o$next[3:0]$11605 + attribute \src "libresoc.v:182160.5-182160.29" + switch \initial + attribute \src "libresoc.v:182160.9-182160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$11600 $5\r25__data_o$next[3:0]$11604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$11601 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$11601 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$11602 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$11602 $2\r25__data_o$next[3:0]$11601 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$11603 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$11603 $3\r25__data_o$next[3:0]$11602 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$11604 \reg + case + assign $5\r25__data_o$next[3:0]$11604 $4\r25__data_o$next[3:0]$11603 + end + case + assign $1\r25__data_o$next[3:0]$11600 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$11605 4'0000 + case + assign $6\r25__data_o$next[3:0]$11605 $1\r25__data_o$next[3:0]$11600 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$11599 + end + attribute \src "libresoc.v:182199.3-182228.6" + process $proc$libresoc.v:182199$11606 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11607 $1\wr_detect$16[0:0]$11608 + attribute \src "libresoc.v:182200.5-182200.29" + switch \initial + attribute \src "libresoc.v:182200.9-182200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11608 $4\wr_detect$16[0:0]$11611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11609 1'1 + case + assign $2\wr_detect$16[0:0]$11609 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11610 1'1 + case + assign $3\wr_detect$16[0:0]$11610 $2\wr_detect$16[0:0]$11609 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11611 1'1 + case + assign $4\wr_detect$16[0:0]$11611 $3\wr_detect$16[0:0]$11610 + end + case + assign $1\wr_detect$16[0:0]$11608 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11607 + end + attribute \src "libresoc.v:182229.3-182255.6" + process $proc$libresoc.v:182229$11612 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11613 $4\reg$next[3:0]$11617 + attribute \src "libresoc.v:182230.5-182230.29" + switch \initial + attribute \src "libresoc.v:182230.9-182230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11614 \dest15__data_i + case + assign $1\reg$next[3:0]$11614 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11615 \dest25__data_i + case + assign $2\reg$next[3:0]$11615 $1\reg$next[3:0]$11614 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11616 \w5__data_i + case + assign $3\reg$next[3:0]$11616 $2\reg$next[3:0]$11615 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11617 4'0000 + case + assign $4\reg$next[3:0]$11617 $3\reg$next[3:0]$11616 + end + sync always + update \reg$next $0\reg$next[3:0]$11613 + end + attribute \src "libresoc.v:182256.3-182295.6" + process $proc$libresoc.v:182256$11618 + assign { } { } + assign { } { } + assign { } { } + assign $0\src15__data_o$next[3:0]$11619 $6\src15__data_o$next[3:0]$11625 + attribute \src "libresoc.v:182257.5-182257.29" + switch \initial + attribute \src "libresoc.v:182257.9-182257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src15__data_o$next[3:0]$11620 $5\src15__data_o$next[3:0]$11624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src15__data_o$next[3:0]$11621 \dest15__data_i + case + assign $2\src15__data_o$next[3:0]$11621 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src15__data_o$next[3:0]$11622 \dest25__data_i + case + assign $3\src15__data_o$next[3:0]$11622 $2\src15__data_o$next[3:0]$11621 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src15__data_o$next[3:0]$11623 \w5__data_i + case + assign $4\src15__data_o$next[3:0]$11623 $3\src15__data_o$next[3:0]$11622 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src15__data_o$next[3:0]$11624 \reg + case + assign $5\src15__data_o$next[3:0]$11624 $4\src15__data_o$next[3:0]$11623 + end + case + assign $1\src15__data_o$next[3:0]$11620 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src15__data_o$next[3:0]$11625 4'0000 + case + assign $6\src15__data_o$next[3:0]$11625 $1\src15__data_o$next[3:0]$11620 + end + sync always + update \src15__data_o$next $0\src15__data_o$next[3:0]$11619 + end + attribute \src "libresoc.v:182296.3-182325.6" + process $proc$libresoc.v:182296$11626 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11627 $1\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:182297.5-182297.29" + switch \initial + attribute \src "libresoc.v:182297.9-182297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11628 $4\wr_detect$4[0:0]$11631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11629 1'1 + case + assign $2\wr_detect$4[0:0]$11629 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11630 1'1 + case + assign $3\wr_detect$4[0:0]$11630 $2\wr_detect$4[0:0]$11629 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11631 1'1 + case + assign $4\wr_detect$4[0:0]$11631 $3\wr_detect$4[0:0]$11630 + end + case + assign $1\wr_detect$4[0:0]$11628 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11627 + end + attribute \src "libresoc.v:182326.3-182365.6" + process $proc$libresoc.v:182326$11632 + assign { } { } + assign { } { } + assign { } { } + assign $0\src25__data_o$next[3:0]$11633 $6\src25__data_o$next[3:0]$11639 + attribute \src "libresoc.v:182327.5-182327.29" + switch \initial + attribute \src "libresoc.v:182327.9-182327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src25__data_o$next[3:0]$11634 $5\src25__data_o$next[3:0]$11638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src25__data_o$next[3:0]$11635 \dest15__data_i + case + assign $2\src25__data_o$next[3:0]$11635 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src25__data_o$next[3:0]$11636 \dest25__data_i + case + assign $3\src25__data_o$next[3:0]$11636 $2\src25__data_o$next[3:0]$11635 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src25__data_o$next[3:0]$11637 \w5__data_i + case + assign $4\src25__data_o$next[3:0]$11637 $3\src25__data_o$next[3:0]$11636 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src25__data_o$next[3:0]$11638 \reg + case + assign $5\src25__data_o$next[3:0]$11638 $4\src25__data_o$next[3:0]$11637 + end + case + assign $1\src25__data_o$next[3:0]$11634 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src25__data_o$next[3:0]$11639 4'0000 + case + assign $6\src25__data_o$next[3:0]$11639 $1\src25__data_o$next[3:0]$11634 + end + sync always + update \src25__data_o$next $0\src25__data_o$next[3:0]$11633 + end + attribute \src "libresoc.v:182366.3-182395.6" + process $proc$libresoc.v:182366$11640 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11641 $1\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:182367.5-182367.29" + switch \initial + attribute \src "libresoc.v:182367.9-182367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11642 $4\wr_detect$7[0:0]$11645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11643 1'1 + case + assign $2\wr_detect$7[0:0]$11643 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11644 1'1 + case + assign $3\wr_detect$7[0:0]$11644 $2\wr_detect$7[0:0]$11643 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11645 1'1 + case + assign $4\wr_detect$7[0:0]$11645 $3\wr_detect$7[0:0]$11644 + end + case + assign $1\wr_detect$7[0:0]$11642 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11641 + end + attribute \src "libresoc.v:182396.3-182435.6" + process $proc$libresoc.v:182396$11646 + assign { } { } + assign { } { } + assign { } { } + assign $0\src35__data_o$next[3:0]$11647 $6\src35__data_o$next[3:0]$11653 + attribute \src "libresoc.v:182397.5-182397.29" + switch \initial + attribute \src "libresoc.v:182397.9-182397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src35__data_o$next[3:0]$11648 $5\src35__data_o$next[3:0]$11652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src35__data_o$next[3:0]$11649 \dest15__data_i + case + assign $2\src35__data_o$next[3:0]$11649 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src35__data_o$next[3:0]$11650 \dest25__data_i + case + assign $3\src35__data_o$next[3:0]$11650 $2\src35__data_o$next[3:0]$11649 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src35__data_o$next[3:0]$11651 \w5__data_i + case + assign $4\src35__data_o$next[3:0]$11651 $3\src35__data_o$next[3:0]$11650 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src35__data_o$next[3:0]$11652 \reg + case + assign $5\src35__data_o$next[3:0]$11652 $4\src35__data_o$next[3:0]$11651 + end + case + assign $1\src35__data_o$next[3:0]$11648 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src35__data_o$next[3:0]$11653 4'0000 + case + assign $6\src35__data_o$next[3:0]$11653 $1\src35__data_o$next[3:0]$11648 + end + sync always + update \src35__data_o$next $0\src35__data_o$next[3:0]$11647 + end + attribute \src "libresoc.v:182436.3-182465.6" + process $proc$libresoc.v:182436$11654 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11655 $1\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:182437.5-182437.29" + switch \initial + attribute \src "libresoc.v:182437.9-182437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11656 $4\wr_detect$10[0:0]$11659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11657 1'1 + case + assign $2\wr_detect$10[0:0]$11657 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11658 1'1 + case + assign $3\wr_detect$10[0:0]$11658 $2\wr_detect$10[0:0]$11657 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11659 1'1 + case + assign $4\wr_detect$10[0:0]$11659 $3\wr_detect$10[0:0]$11658 + end + case + assign $1\wr_detect$10[0:0]$11656 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11655 + end + attribute \src "libresoc.v:182466.3-182505.6" + process $proc$libresoc.v:182466$11660 + assign { } { } + assign { } { } + assign { } { } + assign $0\r5__data_o$next[3:0]$11661 $6\r5__data_o$next[3:0]$11667 + attribute \src "libresoc.v:182467.5-182467.29" + switch \initial + attribute \src "libresoc.v:182467.9-182467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r5__data_o$next[3:0]$11662 $5\r5__data_o$next[3:0]$11666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r5__data_o$next[3:0]$11663 \dest15__data_i + case + assign $2\r5__data_o$next[3:0]$11663 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r5__data_o$next[3:0]$11664 \dest25__data_i + case + assign $3\r5__data_o$next[3:0]$11664 $2\r5__data_o$next[3:0]$11663 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r5__data_o$next[3:0]$11665 \w5__data_i + case + assign $4\r5__data_o$next[3:0]$11665 $3\r5__data_o$next[3:0]$11664 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r5__data_o$next[3:0]$11666 \reg + case + assign $5\r5__data_o$next[3:0]$11666 $4\r5__data_o$next[3:0]$11665 + end + case + assign $1\r5__data_o$next[3:0]$11662 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r5__data_o$next[3:0]$11667 4'0000 + case + assign $6\r5__data_o$next[3:0]$11667 $1\r5__data_o$next[3:0]$11662 + end + sync always + update \r5__data_o$next $0\r5__data_o$next[3:0]$11661 + end + attribute \src "libresoc.v:182506.3-182535.6" + process $proc$libresoc.v:182506$11668 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11669 $1\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:182507.5-182507.29" + switch \initial + attribute \src "libresoc.v:182507.9-182507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11670 $4\wr_detect$13[0:0]$11673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11671 1'1 + case + assign $2\wr_detect$13[0:0]$11671 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11672 1'1 + case + assign $3\wr_detect$13[0:0]$11672 $2\wr_detect$13[0:0]$11671 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11673 1'1 + case + assign $4\wr_detect$13[0:0]$11673 $3\wr_detect$13[0:0]$11672 + end + case + assign $1\wr_detect$13[0:0]$11670 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11669 + end + connect \$9 $not$libresoc.v:182069$11576_Y + connect \$12 $not$libresoc.v:182070$11577_Y + connect \$15 $not$libresoc.v:182071$11578_Y + connect \$1 $not$libresoc.v:182072$11579_Y + connect \$3 $not$libresoc.v:182073$11580_Y + connect \$6 $not$libresoc.v:182074$11581_Y +end +attribute \src "libresoc.v:182540.1-183095.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" +attribute \generator "nMigen" +module \reg_6 + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $0\cr_pred6__data_o$next[3:0]$11696 + attribute \src "libresoc.v:182646.3-182647.49" + wire width 4 $0\cr_pred6__data_o[3:0] + attribute \src "libresoc.v:182541.7-182541.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $0\r26__data_o$next[3:0]$11705 + attribute \src "libresoc.v:182636.3-182637.39" + wire width 4 $0\r26__data_o[3:0] + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $0\r6__data_o$next[3:0]$11767 + attribute \src "libresoc.v:182638.3-182639.37" + wire width 4 $0\r6__data_o[3:0] + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $0\reg$next[3:0]$11719 + attribute \src "libresoc.v:182634.3-182635.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $0\src16__data_o$next[3:0]$11725 + attribute \src "libresoc.v:182644.3-182645.43" + wire width 4 $0\src16__data_o[3:0] + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $0\src26__data_o$next[3:0]$11739 + attribute \src "libresoc.v:182642.3-182643.43" + wire width 4 $0\src26__data_o[3:0] + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $0\src36__data_o$next[3:0]$11753 + attribute \src "libresoc.v:182640.3-182641.43" + wire width 4 $0\src36__data_o[3:0] + attribute \src "libresoc.v:182995.3-183024.6" + wire $0\wr_detect$10[0:0]$11761 + attribute \src "libresoc.v:183065.3-183094.6" + wire $0\wr_detect$13[0:0]$11775 + attribute \src "libresoc.v:182758.3-182787.6" + wire $0\wr_detect$16[0:0]$11713 + attribute \src "libresoc.v:182855.3-182884.6" + wire $0\wr_detect$4[0:0]$11733 + attribute \src "libresoc.v:182925.3-182954.6" + wire $0\wr_detect$7[0:0]$11747 + attribute \src "libresoc.v:182688.3-182717.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $1\cr_pred6__data_o$next[3:0]$11697 + attribute \src "libresoc.v:182560.13-182560.36" + wire width 4 $1\cr_pred6__data_o[3:0] + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $1\r26__data_o$next[3:0]$11706 + attribute \src "libresoc.v:182575.13-182575.31" + wire width 4 $1\r26__data_o[3:0] + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $1\r6__data_o$next[3:0]$11768 + attribute \src "libresoc.v:182582.13-182582.30" + wire width 4 $1\r6__data_o[3:0] + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $1\reg$next[3:0]$11720 + attribute \src "libresoc.v:182588.13-182588.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $1\src16__data_o$next[3:0]$11726 + attribute \src "libresoc.v:182593.13-182593.33" + wire width 4 $1\src16__data_o[3:0] + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $1\src26__data_o$next[3:0]$11740 + attribute \src "libresoc.v:182600.13-182600.33" + wire width 4 $1\src26__data_o[3:0] + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $1\src36__data_o$next[3:0]$11754 + attribute \src "libresoc.v:182607.13-182607.33" + wire width 4 $1\src36__data_o[3:0] + attribute \src "libresoc.v:182995.3-183024.6" + wire $1\wr_detect$10[0:0]$11762 + attribute \src "libresoc.v:183065.3-183094.6" + wire $1\wr_detect$13[0:0]$11776 + attribute \src "libresoc.v:182758.3-182787.6" + wire $1\wr_detect$16[0:0]$11714 + attribute \src "libresoc.v:182855.3-182884.6" + wire $1\wr_detect$4[0:0]$11734 + attribute \src "libresoc.v:182925.3-182954.6" + wire $1\wr_detect$7[0:0]$11748 + attribute \src "libresoc.v:182688.3-182717.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $2\cr_pred6__data_o$next[3:0]$11698 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $2\r26__data_o$next[3:0]$11707 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $2\r6__data_o$next[3:0]$11769 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $2\reg$next[3:0]$11721 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $2\src16__data_o$next[3:0]$11727 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $2\src26__data_o$next[3:0]$11741 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $2\src36__data_o$next[3:0]$11755 + attribute \src "libresoc.v:182995.3-183024.6" + wire $2\wr_detect$10[0:0]$11763 + attribute \src "libresoc.v:183065.3-183094.6" + wire $2\wr_detect$13[0:0]$11777 + attribute \src "libresoc.v:182758.3-182787.6" + wire $2\wr_detect$16[0:0]$11715 + attribute \src "libresoc.v:182855.3-182884.6" + wire $2\wr_detect$4[0:0]$11735 + attribute \src "libresoc.v:182925.3-182954.6" + wire $2\wr_detect$7[0:0]$11749 + attribute \src "libresoc.v:182688.3-182717.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $3\cr_pred6__data_o$next[3:0]$11699 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $3\r26__data_o$next[3:0]$11708 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $3\r6__data_o$next[3:0]$11770 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $3\reg$next[3:0]$11722 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $3\src16__data_o$next[3:0]$11728 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $3\src26__data_o$next[3:0]$11742 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $3\src36__data_o$next[3:0]$11756 + attribute \src "libresoc.v:182995.3-183024.6" + wire $3\wr_detect$10[0:0]$11764 + attribute \src "libresoc.v:183065.3-183094.6" + wire $3\wr_detect$13[0:0]$11778 + attribute \src "libresoc.v:182758.3-182787.6" + wire $3\wr_detect$16[0:0]$11716 + attribute \src "libresoc.v:182855.3-182884.6" + wire $3\wr_detect$4[0:0]$11736 + attribute \src "libresoc.v:182925.3-182954.6" + wire $3\wr_detect$7[0:0]$11750 + attribute \src "libresoc.v:182688.3-182717.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $4\cr_pred6__data_o$next[3:0]$11700 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $4\r26__data_o$next[3:0]$11709 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $4\r6__data_o$next[3:0]$11771 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $4\reg$next[3:0]$11723 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $4\src16__data_o$next[3:0]$11729 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $4\src26__data_o$next[3:0]$11743 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $4\src36__data_o$next[3:0]$11757 + attribute \src "libresoc.v:182995.3-183024.6" + wire $4\wr_detect$10[0:0]$11765 + attribute \src "libresoc.v:183065.3-183094.6" + wire $4\wr_detect$13[0:0]$11779 + attribute \src "libresoc.v:182758.3-182787.6" + wire $4\wr_detect$16[0:0]$11717 + attribute \src "libresoc.v:182855.3-182884.6" + wire $4\wr_detect$4[0:0]$11737 + attribute \src "libresoc.v:182925.3-182954.6" + wire $4\wr_detect$7[0:0]$11751 + attribute \src "libresoc.v:182688.3-182717.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $5\cr_pred6__data_o$next[3:0]$11701 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $5\r26__data_o$next[3:0]$11710 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $5\r6__data_o$next[3:0]$11772 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $5\src16__data_o$next[3:0]$11730 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $5\src26__data_o$next[3:0]$11744 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $5\src36__data_o$next[3:0]$11758 + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $6\cr_pred6__data_o$next[3:0]$11702 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $6\r26__data_o$next[3:0]$11711 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $6\r6__data_o$next[3:0]$11773 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $6\src16__data_o$next[3:0]$11731 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $6\src26__data_o$next[3:0]$11745 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $6\src36__data_o$next[3:0]$11759 + attribute \src "libresoc.v:182628.17-182628.104" + wire $not$libresoc.v:182628$11682_Y + attribute \src "libresoc.v:182629.18-182629.105" + wire $not$libresoc.v:182629$11683_Y + attribute \src "libresoc.v:182630.18-182630.105" + wire $not$libresoc.v:182630$11684_Y + attribute \src "libresoc.v:182631.17-182631.100" + wire $not$libresoc.v:182631$11685_Y + attribute \src "libresoc.v:182632.17-182632.103" + wire $not$libresoc.v:182632$11686_Y + attribute \src "libresoc.v:182633.17-182633.103" + wire $not$libresoc.v:182633$11687_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest26__wen + attribute \src "libresoc.v:182541.7-182541.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src16__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src36__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182628$11682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:182628$11682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182629$11683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:182629$11683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182630$11684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:182630$11684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182631$11685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:182631$11685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182632$11686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:182632$11686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182633$11687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:182633$11687_Y + end + attribute \src "libresoc.v:182541.7-182541.20" + process $proc$libresoc.v:182541$11780 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182560.13-182560.36" + process $proc$libresoc.v:182560$11781 + assign { } { } + assign $1\cr_pred6__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred6__data_o $1\cr_pred6__data_o[3:0] + end + attribute \src "libresoc.v:182575.13-182575.31" + process $proc$libresoc.v:182575$11782 + assign { } { } + assign $1\r26__data_o[3:0] 4'0000 + sync always + sync init + update \r26__data_o $1\r26__data_o[3:0] + end + attribute \src "libresoc.v:182582.13-182582.30" + process $proc$libresoc.v:182582$11783 + assign { } { } + assign $1\r6__data_o[3:0] 4'0000 + sync always + sync init + update \r6__data_o $1\r6__data_o[3:0] + end + attribute \src "libresoc.v:182588.13-182588.25" + process $proc$libresoc.v:182588$11784 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:182593.13-182593.33" + process $proc$libresoc.v:182593$11785 + assign { } { } + assign $1\src16__data_o[3:0] 4'0000 + sync always + sync init + update \src16__data_o $1\src16__data_o[3:0] + end + attribute \src "libresoc.v:182600.13-182600.33" + process $proc$libresoc.v:182600$11786 + assign { } { } + assign $1\src26__data_o[3:0] 4'0000 + sync always + sync init + update \src26__data_o $1\src26__data_o[3:0] + end + attribute \src "libresoc.v:182607.13-182607.33" + process $proc$libresoc.v:182607$11787 + assign { } { } + assign $1\src36__data_o[3:0] 4'0000 + sync always + sync init + update \src36__data_o $1\src36__data_o[3:0] + end + attribute \src "libresoc.v:182634.3-182635.25" + process $proc$libresoc.v:182634$11688 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:182636.3-182637.39" + process $proc$libresoc.v:182636$11689 + assign { } { } + assign $0\r26__data_o[3:0] \r26__data_o$next + sync posedge \coresync_clk + update \r26__data_o $0\r26__data_o[3:0] + end + attribute \src "libresoc.v:182638.3-182639.37" + process $proc$libresoc.v:182638$11690 + assign { } { } + assign $0\r6__data_o[3:0] \r6__data_o$next + sync posedge \coresync_clk + update \r6__data_o $0\r6__data_o[3:0] + end + attribute \src "libresoc.v:182640.3-182641.43" + process $proc$libresoc.v:182640$11691 + assign { } { } + assign $0\src36__data_o[3:0] \src36__data_o$next + sync posedge \coresync_clk + update \src36__data_o $0\src36__data_o[3:0] + end + attribute \src "libresoc.v:182642.3-182643.43" + process $proc$libresoc.v:182642$11692 + assign { } { } + assign $0\src26__data_o[3:0] \src26__data_o$next + sync posedge \coresync_clk + update \src26__data_o $0\src26__data_o[3:0] + end + attribute \src "libresoc.v:182644.3-182645.43" + process $proc$libresoc.v:182644$11693 + assign { } { } + assign $0\src16__data_o[3:0] \src16__data_o$next + sync posedge \coresync_clk + update \src16__data_o $0\src16__data_o[3:0] + end + attribute \src "libresoc.v:182646.3-182647.49" + process $proc$libresoc.v:182646$11694 + assign { } { } + assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next + sync posedge \coresync_clk + update \cr_pred6__data_o $0\cr_pred6__data_o[3:0] + end + attribute \src "libresoc.v:182648.3-182687.6" + process $proc$libresoc.v:182648$11695 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred6__data_o$next[3:0]$11696 $6\cr_pred6__data_o$next[3:0]$11702 + attribute \src "libresoc.v:182649.5-182649.29" + switch \initial + attribute \src "libresoc.v:182649.9-182649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred6__data_o$next[3:0]$11697 $5\cr_pred6__data_o$next[3:0]$11701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred6__data_o$next[3:0]$11698 \dest16__data_i + case + assign $2\cr_pred6__data_o$next[3:0]$11698 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred6__data_o$next[3:0]$11699 \dest26__data_i + case + assign $3\cr_pred6__data_o$next[3:0]$11699 $2\cr_pred6__data_o$next[3:0]$11698 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred6__data_o$next[3:0]$11700 \w6__data_i + case + assign $4\cr_pred6__data_o$next[3:0]$11700 $3\cr_pred6__data_o$next[3:0]$11699 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred6__data_o$next[3:0]$11701 \reg + case + assign $5\cr_pred6__data_o$next[3:0]$11701 $4\cr_pred6__data_o$next[3:0]$11700 + end + case + assign $1\cr_pred6__data_o$next[3:0]$11697 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred6__data_o$next[3:0]$11702 4'0000 + case + assign $6\cr_pred6__data_o$next[3:0]$11702 $1\cr_pred6__data_o$next[3:0]$11697 + end + sync always + update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11696 + end + attribute \src "libresoc.v:182688.3-182717.6" + process $proc$libresoc.v:182688$11703 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:182689.5-182689.29" + switch \initial + attribute \src "libresoc.v:182689.9-182689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:182718.3-182757.6" + process $proc$libresoc.v:182718$11704 + assign { } { } + assign { } { } + assign { } { } + assign $0\r26__data_o$next[3:0]$11705 $6\r26__data_o$next[3:0]$11711 + attribute \src "libresoc.v:182719.5-182719.29" + switch \initial + attribute \src "libresoc.v:182719.9-182719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r26__data_o$next[3:0]$11706 $5\r26__data_o$next[3:0]$11710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$11707 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$11707 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$11708 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$11708 $2\r26__data_o$next[3:0]$11707 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$11709 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$11709 $3\r26__data_o$next[3:0]$11708 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$11710 \reg + case + assign $5\r26__data_o$next[3:0]$11710 $4\r26__data_o$next[3:0]$11709 + end + case + assign $1\r26__data_o$next[3:0]$11706 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r26__data_o$next[3:0]$11711 4'0000 + case + assign $6\r26__data_o$next[3:0]$11711 $1\r26__data_o$next[3:0]$11706 + end + sync always + update \r26__data_o$next $0\r26__data_o$next[3:0]$11705 + end + attribute \src "libresoc.v:182758.3-182787.6" + process $proc$libresoc.v:182758$11712 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11713 $1\wr_detect$16[0:0]$11714 + attribute \src "libresoc.v:182759.5-182759.29" + switch \initial + attribute \src "libresoc.v:182759.9-182759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11714 $4\wr_detect$16[0:0]$11717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11715 1'1 + case + assign $2\wr_detect$16[0:0]$11715 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11716 1'1 + case + assign $3\wr_detect$16[0:0]$11716 $2\wr_detect$16[0:0]$11715 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11717 1'1 + case + assign $4\wr_detect$16[0:0]$11717 $3\wr_detect$16[0:0]$11716 + end + case + assign $1\wr_detect$16[0:0]$11714 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11713 + end + attribute \src "libresoc.v:182788.3-182814.6" + process $proc$libresoc.v:182788$11718 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11719 $4\reg$next[3:0]$11723 + attribute \src "libresoc.v:182789.5-182789.29" + switch \initial + attribute \src "libresoc.v:182789.9-182789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11720 \dest16__data_i + case + assign $1\reg$next[3:0]$11720 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11721 \dest26__data_i + case + assign $2\reg$next[3:0]$11721 $1\reg$next[3:0]$11720 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11722 \w6__data_i + case + assign $3\reg$next[3:0]$11722 $2\reg$next[3:0]$11721 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11723 4'0000 + case + assign $4\reg$next[3:0]$11723 $3\reg$next[3:0]$11722 + end + sync always + update \reg$next $0\reg$next[3:0]$11719 + end + attribute \src "libresoc.v:182815.3-182854.6" + process $proc$libresoc.v:182815$11724 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$11725 $6\src16__data_o$next[3:0]$11731 + attribute \src "libresoc.v:182816.5-182816.29" + switch \initial + attribute \src "libresoc.v:182816.9-182816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$11726 $5\src16__data_o$next[3:0]$11730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$11727 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$11727 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$11728 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$11728 $2\src16__data_o$next[3:0]$11727 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$11729 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$11729 $3\src16__data_o$next[3:0]$11728 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src16__data_o$next[3:0]$11730 \reg + case + assign $5\src16__data_o$next[3:0]$11730 $4\src16__data_o$next[3:0]$11729 + end + case + assign $1\src16__data_o$next[3:0]$11726 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src16__data_o$next[3:0]$11731 4'0000 + case + assign $6\src16__data_o$next[3:0]$11731 $1\src16__data_o$next[3:0]$11726 + end + sync always + update \src16__data_o$next $0\src16__data_o$next[3:0]$11725 + end + attribute \src "libresoc.v:182855.3-182884.6" + process $proc$libresoc.v:182855$11732 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11733 $1\wr_detect$4[0:0]$11734 + attribute \src "libresoc.v:182856.5-182856.29" + switch \initial + attribute \src "libresoc.v:182856.9-182856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11734 $4\wr_detect$4[0:0]$11737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11735 1'1 + case + assign $2\wr_detect$4[0:0]$11735 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11736 1'1 + case + assign $3\wr_detect$4[0:0]$11736 $2\wr_detect$4[0:0]$11735 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11737 1'1 + case + assign $4\wr_detect$4[0:0]$11737 $3\wr_detect$4[0:0]$11736 + end + case + assign $1\wr_detect$4[0:0]$11734 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11733 + end + attribute \src "libresoc.v:182885.3-182924.6" + process $proc$libresoc.v:182885$11738 + assign { } { } + assign { } { } + assign { } { } + assign $0\src26__data_o$next[3:0]$11739 $6\src26__data_o$next[3:0]$11745 + attribute \src "libresoc.v:182886.5-182886.29" + switch \initial + attribute \src "libresoc.v:182886.9-182886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src26__data_o$next[3:0]$11740 $5\src26__data_o$next[3:0]$11744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src26__data_o$next[3:0]$11741 \dest16__data_i + case + assign $2\src26__data_o$next[3:0]$11741 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src26__data_o$next[3:0]$11742 \dest26__data_i + case + assign $3\src26__data_o$next[3:0]$11742 $2\src26__data_o$next[3:0]$11741 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src26__data_o$next[3:0]$11743 \w6__data_i + case + assign $4\src26__data_o$next[3:0]$11743 $3\src26__data_o$next[3:0]$11742 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src26__data_o$next[3:0]$11744 \reg + case + assign $5\src26__data_o$next[3:0]$11744 $4\src26__data_o$next[3:0]$11743 + end + case + assign $1\src26__data_o$next[3:0]$11740 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src26__data_o$next[3:0]$11745 4'0000 + case + assign $6\src26__data_o$next[3:0]$11745 $1\src26__data_o$next[3:0]$11740 + end + sync always + update \src26__data_o$next $0\src26__data_o$next[3:0]$11739 + end + attribute \src "libresoc.v:182925.3-182954.6" + process $proc$libresoc.v:182925$11746 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11747 $1\wr_detect$7[0:0]$11748 + attribute \src "libresoc.v:182926.5-182926.29" + switch \initial + attribute \src "libresoc.v:182926.9-182926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11748 $4\wr_detect$7[0:0]$11751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11749 1'1 + case + assign $2\wr_detect$7[0:0]$11749 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11750 1'1 + case + assign $3\wr_detect$7[0:0]$11750 $2\wr_detect$7[0:0]$11749 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11751 1'1 + case + assign $4\wr_detect$7[0:0]$11751 $3\wr_detect$7[0:0]$11750 + end + case + assign $1\wr_detect$7[0:0]$11748 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11747 + end + attribute \src "libresoc.v:182955.3-182994.6" + process $proc$libresoc.v:182955$11752 + assign { } { } + assign { } { } + assign { } { } + assign $0\src36__data_o$next[3:0]$11753 $6\src36__data_o$next[3:0]$11759 + attribute \src "libresoc.v:182956.5-182956.29" + switch \initial + attribute \src "libresoc.v:182956.9-182956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src36__data_o$next[3:0]$11754 $5\src36__data_o$next[3:0]$11758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src36__data_o$next[3:0]$11755 \dest16__data_i + case + assign $2\src36__data_o$next[3:0]$11755 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src36__data_o$next[3:0]$11756 \dest26__data_i + case + assign $3\src36__data_o$next[3:0]$11756 $2\src36__data_o$next[3:0]$11755 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src36__data_o$next[3:0]$11757 \w6__data_i + case + assign $4\src36__data_o$next[3:0]$11757 $3\src36__data_o$next[3:0]$11756 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src36__data_o$next[3:0]$11758 \reg + case + assign $5\src36__data_o$next[3:0]$11758 $4\src36__data_o$next[3:0]$11757 + end + case + assign $1\src36__data_o$next[3:0]$11754 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src36__data_o$next[3:0]$11759 4'0000 + case + assign $6\src36__data_o$next[3:0]$11759 $1\src36__data_o$next[3:0]$11754 + end + sync always + update \src36__data_o$next $0\src36__data_o$next[3:0]$11753 + end + attribute \src "libresoc.v:182995.3-183024.6" + process $proc$libresoc.v:182995$11760 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11761 $1\wr_detect$10[0:0]$11762 + attribute \src "libresoc.v:182996.5-182996.29" + switch \initial + attribute \src "libresoc.v:182996.9-182996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11762 $4\wr_detect$10[0:0]$11765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11763 1'1 + case + assign $2\wr_detect$10[0:0]$11763 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11764 1'1 + case + assign $3\wr_detect$10[0:0]$11764 $2\wr_detect$10[0:0]$11763 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11765 1'1 + case + assign $4\wr_detect$10[0:0]$11765 $3\wr_detect$10[0:0]$11764 + end + case + assign $1\wr_detect$10[0:0]$11762 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11761 + end + attribute \src "libresoc.v:183025.3-183064.6" + process $proc$libresoc.v:183025$11766 + assign { } { } + assign { } { } + assign { } { } + assign $0\r6__data_o$next[3:0]$11767 $6\r6__data_o$next[3:0]$11773 + attribute \src "libresoc.v:183026.5-183026.29" + switch \initial + attribute \src "libresoc.v:183026.9-183026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r6__data_o$next[3:0]$11768 $5\r6__data_o$next[3:0]$11772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r6__data_o$next[3:0]$11769 \dest16__data_i + case + assign $2\r6__data_o$next[3:0]$11769 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r6__data_o$next[3:0]$11770 \dest26__data_i + case + assign $3\r6__data_o$next[3:0]$11770 $2\r6__data_o$next[3:0]$11769 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r6__data_o$next[3:0]$11771 \w6__data_i + case + assign $4\r6__data_o$next[3:0]$11771 $3\r6__data_o$next[3:0]$11770 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r6__data_o$next[3:0]$11772 \reg + case + assign $5\r6__data_o$next[3:0]$11772 $4\r6__data_o$next[3:0]$11771 + end + case + assign $1\r6__data_o$next[3:0]$11768 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r6__data_o$next[3:0]$11773 4'0000 + case + assign $6\r6__data_o$next[3:0]$11773 $1\r6__data_o$next[3:0]$11768 + end + sync always + update \r6__data_o$next $0\r6__data_o$next[3:0]$11767 + end + attribute \src "libresoc.v:183065.3-183094.6" + process $proc$libresoc.v:183065$11774 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11775 $1\wr_detect$13[0:0]$11776 + attribute \src "libresoc.v:183066.5-183066.29" + switch \initial + attribute \src "libresoc.v:183066.9-183066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11776 $4\wr_detect$13[0:0]$11779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11777 1'1 + case + assign $2\wr_detect$13[0:0]$11777 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11778 1'1 + case + assign $3\wr_detect$13[0:0]$11778 $2\wr_detect$13[0:0]$11777 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11779 1'1 + case + assign $4\wr_detect$13[0:0]$11779 $3\wr_detect$13[0:0]$11778 + end + case + assign $1\wr_detect$13[0:0]$11776 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11775 + end + connect \$9 $not$libresoc.v:182628$11682_Y + connect \$12 $not$libresoc.v:182629$11683_Y + connect \$15 $not$libresoc.v:182630$11684_Y + connect \$1 $not$libresoc.v:182631$11685_Y + connect \$3 $not$libresoc.v:182632$11686_Y + connect \$6 $not$libresoc.v:182633$11687_Y +end +attribute \src "libresoc.v:183099.1-183654.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" +attribute \generator "nMigen" +module \reg_7 + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $0\cr_pred7__data_o$next[3:0]$11802 + attribute \src "libresoc.v:183205.3-183206.49" + wire width 4 $0\cr_pred7__data_o[3:0] + attribute \src "libresoc.v:183100.7-183100.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $0\r27__data_o$next[3:0]$11811 + attribute \src "libresoc.v:183195.3-183196.39" + wire width 4 $0\r27__data_o[3:0] + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $0\r7__data_o$next[3:0]$11873 + attribute \src "libresoc.v:183197.3-183198.37" + wire width 4 $0\r7__data_o[3:0] + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $0\reg$next[3:0]$11825 + attribute \src "libresoc.v:183193.3-183194.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $0\src17__data_o$next[3:0]$11831 + attribute \src "libresoc.v:183203.3-183204.43" + wire width 4 $0\src17__data_o[3:0] + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $0\src27__data_o$next[3:0]$11845 + attribute \src "libresoc.v:183201.3-183202.43" + wire width 4 $0\src27__data_o[3:0] + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $0\src37__data_o$next[3:0]$11859 + attribute \src "libresoc.v:183199.3-183200.43" + wire width 4 $0\src37__data_o[3:0] + attribute \src "libresoc.v:183554.3-183583.6" + wire $0\wr_detect$10[0:0]$11867 + attribute \src "libresoc.v:183624.3-183653.6" + wire $0\wr_detect$13[0:0]$11881 + attribute \src "libresoc.v:183317.3-183346.6" + wire $0\wr_detect$16[0:0]$11819 + attribute \src "libresoc.v:183414.3-183443.6" + wire $0\wr_detect$4[0:0]$11839 + attribute \src "libresoc.v:183484.3-183513.6" + wire $0\wr_detect$7[0:0]$11853 + attribute \src "libresoc.v:183247.3-183276.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $1\cr_pred7__data_o$next[3:0]$11803 + attribute \src "libresoc.v:183119.13-183119.36" + wire width 4 $1\cr_pred7__data_o[3:0] + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $1\r27__data_o$next[3:0]$11812 + attribute \src "libresoc.v:183134.13-183134.31" + wire width 4 $1\r27__data_o[3:0] + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $1\r7__data_o$next[3:0]$11874 + attribute \src "libresoc.v:183141.13-183141.30" + wire width 4 $1\r7__data_o[3:0] + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $1\reg$next[3:0]$11826 + attribute \src "libresoc.v:183147.13-183147.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $1\src17__data_o$next[3:0]$11832 + attribute \src "libresoc.v:183152.13-183152.33" + wire width 4 $1\src17__data_o[3:0] + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $1\src27__data_o$next[3:0]$11846 + attribute \src "libresoc.v:183159.13-183159.33" + wire width 4 $1\src27__data_o[3:0] + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $1\src37__data_o$next[3:0]$11860 + attribute \src "libresoc.v:183166.13-183166.33" + wire width 4 $1\src37__data_o[3:0] + attribute \src "libresoc.v:183554.3-183583.6" + wire $1\wr_detect$10[0:0]$11868 + attribute \src "libresoc.v:183624.3-183653.6" + wire $1\wr_detect$13[0:0]$11882 + attribute \src "libresoc.v:183317.3-183346.6" + wire $1\wr_detect$16[0:0]$11820 + attribute \src "libresoc.v:183414.3-183443.6" + wire $1\wr_detect$4[0:0]$11840 + attribute \src "libresoc.v:183484.3-183513.6" + wire $1\wr_detect$7[0:0]$11854 + attribute \src "libresoc.v:183247.3-183276.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $2\cr_pred7__data_o$next[3:0]$11804 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $2\r27__data_o$next[3:0]$11813 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $2\r7__data_o$next[3:0]$11875 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $2\reg$next[3:0]$11827 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $2\src17__data_o$next[3:0]$11833 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $2\src27__data_o$next[3:0]$11847 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $2\src37__data_o$next[3:0]$11861 + attribute \src "libresoc.v:183554.3-183583.6" + wire $2\wr_detect$10[0:0]$11869 + attribute \src "libresoc.v:183624.3-183653.6" + wire $2\wr_detect$13[0:0]$11883 + attribute \src "libresoc.v:183317.3-183346.6" + wire $2\wr_detect$16[0:0]$11821 + attribute \src "libresoc.v:183414.3-183443.6" + wire $2\wr_detect$4[0:0]$11841 + attribute \src "libresoc.v:183484.3-183513.6" + wire $2\wr_detect$7[0:0]$11855 + attribute \src "libresoc.v:183247.3-183276.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $3\cr_pred7__data_o$next[3:0]$11805 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $3\r27__data_o$next[3:0]$11814 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $3\r7__data_o$next[3:0]$11876 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $3\reg$next[3:0]$11828 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $3\src17__data_o$next[3:0]$11834 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $3\src27__data_o$next[3:0]$11848 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $3\src37__data_o$next[3:0]$11862 + attribute \src "libresoc.v:183554.3-183583.6" + wire $3\wr_detect$10[0:0]$11870 + attribute \src "libresoc.v:183624.3-183653.6" + wire $3\wr_detect$13[0:0]$11884 + attribute \src "libresoc.v:183317.3-183346.6" + wire $3\wr_detect$16[0:0]$11822 + attribute \src "libresoc.v:183414.3-183443.6" + wire $3\wr_detect$4[0:0]$11842 + attribute \src "libresoc.v:183484.3-183513.6" + wire $3\wr_detect$7[0:0]$11856 + attribute \src "libresoc.v:183247.3-183276.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $4\cr_pred7__data_o$next[3:0]$11806 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $4\r27__data_o$next[3:0]$11815 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $4\r7__data_o$next[3:0]$11877 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $4\reg$next[3:0]$11829 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $4\src17__data_o$next[3:0]$11835 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $4\src27__data_o$next[3:0]$11849 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $4\src37__data_o$next[3:0]$11863 + attribute \src "libresoc.v:183554.3-183583.6" + wire $4\wr_detect$10[0:0]$11871 + attribute \src "libresoc.v:183624.3-183653.6" + wire $4\wr_detect$13[0:0]$11885 + attribute \src "libresoc.v:183317.3-183346.6" + wire $4\wr_detect$16[0:0]$11823 + attribute \src "libresoc.v:183414.3-183443.6" + wire $4\wr_detect$4[0:0]$11843 + attribute \src "libresoc.v:183484.3-183513.6" + wire $4\wr_detect$7[0:0]$11857 + attribute \src "libresoc.v:183247.3-183276.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $5\cr_pred7__data_o$next[3:0]$11807 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $5\r27__data_o$next[3:0]$11816 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $5\r7__data_o$next[3:0]$11878 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $5\src17__data_o$next[3:0]$11836 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $5\src27__data_o$next[3:0]$11850 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $5\src37__data_o$next[3:0]$11864 + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $6\cr_pred7__data_o$next[3:0]$11808 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $6\r27__data_o$next[3:0]$11817 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $6\r7__data_o$next[3:0]$11879 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $6\src17__data_o$next[3:0]$11837 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $6\src27__data_o$next[3:0]$11851 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $6\src37__data_o$next[3:0]$11865 + attribute \src "libresoc.v:183187.17-183187.104" + wire $not$libresoc.v:183187$11788_Y + attribute \src "libresoc.v:183188.18-183188.105" + wire $not$libresoc.v:183188$11789_Y + attribute \src "libresoc.v:183189.18-183189.105" + wire $not$libresoc.v:183189$11790_Y + attribute \src "libresoc.v:183190.17-183190.100" + wire $not$libresoc.v:183190$11791_Y + attribute \src "libresoc.v:183191.17-183191.103" + wire $not$libresoc.v:183191$11792_Y + attribute \src "libresoc.v:183192.17-183192.103" + wire $not$libresoc.v:183192$11793_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \cr_pred7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest27__wen + attribute \src "libresoc.v:183100.7-183100.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 16 \r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src17__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 9 \src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src37__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 18 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 19 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183187$11788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:183187$11788_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183188$11789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:183188$11789_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183189$11790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:183189$11790_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183190$11791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:183190$11791_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183191$11792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:183191$11792_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183192$11793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:183192$11793_Y + end + attribute \src "libresoc.v:183100.7-183100.20" + process $proc$libresoc.v:183100$11886 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183119.13-183119.36" + process $proc$libresoc.v:183119$11887 + assign { } { } + assign $1\cr_pred7__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred7__data_o $1\cr_pred7__data_o[3:0] + end + attribute \src "libresoc.v:183134.13-183134.31" + process $proc$libresoc.v:183134$11888 + assign { } { } + assign $1\r27__data_o[3:0] 4'0000 + sync always + sync init + update \r27__data_o $1\r27__data_o[3:0] + end + attribute \src "libresoc.v:183141.13-183141.30" + process $proc$libresoc.v:183141$11889 + assign { } { } + assign $1\r7__data_o[3:0] 4'0000 + sync always + sync init + update \r7__data_o $1\r7__data_o[3:0] + end + attribute \src "libresoc.v:183147.13-183147.25" + process $proc$libresoc.v:183147$11890 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:183152.13-183152.33" + process $proc$libresoc.v:183152$11891 + assign { } { } + assign $1\src17__data_o[3:0] 4'0000 + sync always + sync init + update \src17__data_o $1\src17__data_o[3:0] + end + attribute \src "libresoc.v:183159.13-183159.33" + process $proc$libresoc.v:183159$11892 + assign { } { } + assign $1\src27__data_o[3:0] 4'0000 + sync always + sync init + update \src27__data_o $1\src27__data_o[3:0] + end + attribute \src "libresoc.v:183166.13-183166.33" + process $proc$libresoc.v:183166$11893 + assign { } { } + assign $1\src37__data_o[3:0] 4'0000 + sync always + sync init + update \src37__data_o $1\src37__data_o[3:0] + end + attribute \src "libresoc.v:183193.3-183194.25" + process $proc$libresoc.v:183193$11794 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:183195.3-183196.39" + process $proc$libresoc.v:183195$11795 + assign { } { } + assign $0\r27__data_o[3:0] \r27__data_o$next + sync posedge \coresync_clk + update \r27__data_o $0\r27__data_o[3:0] + end + attribute \src "libresoc.v:183197.3-183198.37" + process $proc$libresoc.v:183197$11796 + assign { } { } + assign $0\r7__data_o[3:0] \r7__data_o$next + sync posedge \coresync_clk + update \r7__data_o $0\r7__data_o[3:0] + end + attribute \src "libresoc.v:183199.3-183200.43" + process $proc$libresoc.v:183199$11797 + assign { } { } + assign $0\src37__data_o[3:0] \src37__data_o$next + sync posedge \coresync_clk + update \src37__data_o $0\src37__data_o[3:0] + end + attribute \src "libresoc.v:183201.3-183202.43" + process $proc$libresoc.v:183201$11798 + assign { } { } + assign $0\src27__data_o[3:0] \src27__data_o$next + sync posedge \coresync_clk + update \src27__data_o $0\src27__data_o[3:0] + end + attribute \src "libresoc.v:183203.3-183204.43" + process $proc$libresoc.v:183203$11799 + assign { } { } + assign $0\src17__data_o[3:0] \src17__data_o$next + sync posedge \coresync_clk + update \src17__data_o $0\src17__data_o[3:0] + end + attribute \src "libresoc.v:183205.3-183206.49" + process $proc$libresoc.v:183205$11800 + assign { } { } + assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next + sync posedge \coresync_clk + update \cr_pred7__data_o $0\cr_pred7__data_o[3:0] + end + attribute \src "libresoc.v:183207.3-183246.6" + process $proc$libresoc.v:183207$11801 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_pred7__data_o$next[3:0]$11802 $6\cr_pred7__data_o$next[3:0]$11808 + attribute \src "libresoc.v:183208.5-183208.29" + switch \initial + attribute \src "libresoc.v:183208.9-183208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_pred7__data_o$next[3:0]$11803 $5\cr_pred7__data_o$next[3:0]$11807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_pred7__data_o$next[3:0]$11804 \dest17__data_i + case + assign $2\cr_pred7__data_o$next[3:0]$11804 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_pred7__data_o$next[3:0]$11805 \dest27__data_i + case + assign $3\cr_pred7__data_o$next[3:0]$11805 $2\cr_pred7__data_o$next[3:0]$11804 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_pred7__data_o$next[3:0]$11806 \w7__data_i + case + assign $4\cr_pred7__data_o$next[3:0]$11806 $3\cr_pred7__data_o$next[3:0]$11805 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cr_pred7__data_o$next[3:0]$11807 \reg + case + assign $5\cr_pred7__data_o$next[3:0]$11807 $4\cr_pred7__data_o$next[3:0]$11806 + end + case + assign $1\cr_pred7__data_o$next[3:0]$11803 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cr_pred7__data_o$next[3:0]$11808 4'0000 + case + assign $6\cr_pred7__data_o$next[3:0]$11808 $1\cr_pred7__data_o$next[3:0]$11803 + end + sync always + update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11802 + end + attribute \src "libresoc.v:183247.3-183276.6" + process $proc$libresoc.v:183247$11809 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:183248.5-183248.29" + switch \initial + attribute \src "libresoc.v:183248.9-183248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cr_pred7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:183277.3-183316.6" + process $proc$libresoc.v:183277$11810 + assign { } { } + assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$11811 $6\r27__data_o$next[3:0]$11817 + attribute \src "libresoc.v:183278.5-183278.29" + switch \initial + attribute \src "libresoc.v:183278.9-183278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$11812 $5\r27__data_o$next[3:0]$11816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$11813 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$11813 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$11814 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$11814 $2\r27__data_o$next[3:0]$11813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$11815 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$11815 $3\r27__data_o$next[3:0]$11814 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$11816 \reg + case + assign $5\r27__data_o$next[3:0]$11816 $4\r27__data_o$next[3:0]$11815 + end + case + assign $1\r27__data_o$next[3:0]$11812 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$11817 4'0000 + case + assign $6\r27__data_o$next[3:0]$11817 $1\r27__data_o$next[3:0]$11812 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$11811 + end + attribute \src "libresoc.v:183317.3-183346.6" + process $proc$libresoc.v:183317$11818 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11819 $1\wr_detect$16[0:0]$11820 + attribute \src "libresoc.v:183318.5-183318.29" + switch \initial + attribute \src "libresoc.v:183318.9-183318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11820 $4\wr_detect$16[0:0]$11823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11821 1'1 + case + assign $2\wr_detect$16[0:0]$11821 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11822 1'1 + case + assign $3\wr_detect$16[0:0]$11822 $2\wr_detect$16[0:0]$11821 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11823 1'1 + case + assign $4\wr_detect$16[0:0]$11823 $3\wr_detect$16[0:0]$11822 + end + case + assign $1\wr_detect$16[0:0]$11820 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11819 + end + attribute \src "libresoc.v:183347.3-183373.6" + process $proc$libresoc.v:183347$11824 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11825 $4\reg$next[3:0]$11829 + attribute \src "libresoc.v:183348.5-183348.29" + switch \initial + attribute \src "libresoc.v:183348.9-183348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11826 \dest17__data_i + case + assign $1\reg$next[3:0]$11826 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11827 \dest27__data_i + case + assign $2\reg$next[3:0]$11827 $1\reg$next[3:0]$11826 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11828 \w7__data_i + case + assign $3\reg$next[3:0]$11828 $2\reg$next[3:0]$11827 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11829 4'0000 + case + assign $4\reg$next[3:0]$11829 $3\reg$next[3:0]$11828 + end + sync always + update \reg$next $0\reg$next[3:0]$11825 + end + attribute \src "libresoc.v:183374.3-183413.6" + process $proc$libresoc.v:183374$11830 + assign { } { } + assign { } { } + assign { } { } + assign $0\src17__data_o$next[3:0]$11831 $6\src17__data_o$next[3:0]$11837 + attribute \src "libresoc.v:183375.5-183375.29" + switch \initial + attribute \src "libresoc.v:183375.9-183375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src17__data_o$next[3:0]$11832 $5\src17__data_o$next[3:0]$11836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src17__data_o$next[3:0]$11833 \dest17__data_i + case + assign $2\src17__data_o$next[3:0]$11833 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src17__data_o$next[3:0]$11834 \dest27__data_i + case + assign $3\src17__data_o$next[3:0]$11834 $2\src17__data_o$next[3:0]$11833 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src17__data_o$next[3:0]$11835 \w7__data_i + case + assign $4\src17__data_o$next[3:0]$11835 $3\src17__data_o$next[3:0]$11834 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src17__data_o$next[3:0]$11836 \reg + case + assign $5\src17__data_o$next[3:0]$11836 $4\src17__data_o$next[3:0]$11835 + end + case + assign $1\src17__data_o$next[3:0]$11832 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src17__data_o$next[3:0]$11837 4'0000 + case + assign $6\src17__data_o$next[3:0]$11837 $1\src17__data_o$next[3:0]$11832 + end + sync always + update \src17__data_o$next $0\src17__data_o$next[3:0]$11831 + end + attribute \src "libresoc.v:183414.3-183443.6" + process $proc$libresoc.v:183414$11838 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11839 $1\wr_detect$4[0:0]$11840 + attribute \src "libresoc.v:183415.5-183415.29" + switch \initial + attribute \src "libresoc.v:183415.9-183415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11840 $4\wr_detect$4[0:0]$11843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11841 1'1 + case + assign $2\wr_detect$4[0:0]$11841 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11842 1'1 + case + assign $3\wr_detect$4[0:0]$11842 $2\wr_detect$4[0:0]$11841 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11843 1'1 + case + assign $4\wr_detect$4[0:0]$11843 $3\wr_detect$4[0:0]$11842 + end + case + assign $1\wr_detect$4[0:0]$11840 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11839 + end + attribute \src "libresoc.v:183444.3-183483.6" + process $proc$libresoc.v:183444$11844 + assign { } { } + assign { } { } + assign { } { } + assign $0\src27__data_o$next[3:0]$11845 $6\src27__data_o$next[3:0]$11851 + attribute \src "libresoc.v:183445.5-183445.29" + switch \initial + attribute \src "libresoc.v:183445.9-183445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src27__data_o$next[3:0]$11846 $5\src27__data_o$next[3:0]$11850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src27__data_o$next[3:0]$11847 \dest17__data_i + case + assign $2\src27__data_o$next[3:0]$11847 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src27__data_o$next[3:0]$11848 \dest27__data_i + case + assign $3\src27__data_o$next[3:0]$11848 $2\src27__data_o$next[3:0]$11847 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src27__data_o$next[3:0]$11849 \w7__data_i + case + assign $4\src27__data_o$next[3:0]$11849 $3\src27__data_o$next[3:0]$11848 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src27__data_o$next[3:0]$11850 \reg + case + assign $5\src27__data_o$next[3:0]$11850 $4\src27__data_o$next[3:0]$11849 + end + case + assign $1\src27__data_o$next[3:0]$11846 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src27__data_o$next[3:0]$11851 4'0000 + case + assign $6\src27__data_o$next[3:0]$11851 $1\src27__data_o$next[3:0]$11846 + end + sync always + update \src27__data_o$next $0\src27__data_o$next[3:0]$11845 + end + attribute \src "libresoc.v:183484.3-183513.6" + process $proc$libresoc.v:183484$11852 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11853 $1\wr_detect$7[0:0]$11854 + attribute \src "libresoc.v:183485.5-183485.29" + switch \initial + attribute \src "libresoc.v:183485.9-183485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11854 $4\wr_detect$7[0:0]$11857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11855 1'1 + case + assign $2\wr_detect$7[0:0]$11855 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11856 1'1 + case + assign $3\wr_detect$7[0:0]$11856 $2\wr_detect$7[0:0]$11855 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11857 1'1 + case + assign $4\wr_detect$7[0:0]$11857 $3\wr_detect$7[0:0]$11856 + end + case + assign $1\wr_detect$7[0:0]$11854 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11853 + end + attribute \src "libresoc.v:183514.3-183553.6" + process $proc$libresoc.v:183514$11858 + assign { } { } + assign { } { } + assign { } { } + assign $0\src37__data_o$next[3:0]$11859 $6\src37__data_o$next[3:0]$11865 + attribute \src "libresoc.v:183515.5-183515.29" + switch \initial + attribute \src "libresoc.v:183515.9-183515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src37__data_o$next[3:0]$11860 $5\src37__data_o$next[3:0]$11864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src37__data_o$next[3:0]$11861 \dest17__data_i + case + assign $2\src37__data_o$next[3:0]$11861 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src37__data_o$next[3:0]$11862 \dest27__data_i + case + assign $3\src37__data_o$next[3:0]$11862 $2\src37__data_o$next[3:0]$11861 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src37__data_o$next[3:0]$11863 \w7__data_i + case + assign $4\src37__data_o$next[3:0]$11863 $3\src37__data_o$next[3:0]$11862 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src37__data_o$next[3:0]$11864 \reg + case + assign $5\src37__data_o$next[3:0]$11864 $4\src37__data_o$next[3:0]$11863 + end + case + assign $1\src37__data_o$next[3:0]$11860 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src37__data_o$next[3:0]$11865 4'0000 + case + assign $6\src37__data_o$next[3:0]$11865 $1\src37__data_o$next[3:0]$11860 + end + sync always + update \src37__data_o$next $0\src37__data_o$next[3:0]$11859 + end + attribute \src "libresoc.v:183554.3-183583.6" + process $proc$libresoc.v:183554$11866 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11867 $1\wr_detect$10[0:0]$11868 + attribute \src "libresoc.v:183555.5-183555.29" + switch \initial + attribute \src "libresoc.v:183555.9-183555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11868 $4\wr_detect$10[0:0]$11871 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11869 1'1 + case + assign $2\wr_detect$10[0:0]$11869 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11870 1'1 + case + assign $3\wr_detect$10[0:0]$11870 $2\wr_detect$10[0:0]$11869 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11871 1'1 + case + assign $4\wr_detect$10[0:0]$11871 $3\wr_detect$10[0:0]$11870 + end + case + assign $1\wr_detect$10[0:0]$11868 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11867 + end + attribute \src "libresoc.v:183584.3-183623.6" + process $proc$libresoc.v:183584$11872 + assign { } { } + assign { } { } + assign { } { } + assign $0\r7__data_o$next[3:0]$11873 $6\r7__data_o$next[3:0]$11879 + attribute \src "libresoc.v:183585.5-183585.29" + switch \initial + attribute \src "libresoc.v:183585.9-183585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r7__data_o$next[3:0]$11874 $5\r7__data_o$next[3:0]$11878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r7__data_o$next[3:0]$11875 \dest17__data_i + case + assign $2\r7__data_o$next[3:0]$11875 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r7__data_o$next[3:0]$11876 \dest27__data_i + case + assign $3\r7__data_o$next[3:0]$11876 $2\r7__data_o$next[3:0]$11875 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r7__data_o$next[3:0]$11877 \w7__data_i + case + assign $4\r7__data_o$next[3:0]$11877 $3\r7__data_o$next[3:0]$11876 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r7__data_o$next[3:0]$11878 \reg + case + assign $5\r7__data_o$next[3:0]$11878 $4\r7__data_o$next[3:0]$11877 + end + case + assign $1\r7__data_o$next[3:0]$11874 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r7__data_o$next[3:0]$11879 4'0000 + case + assign $6\r7__data_o$next[3:0]$11879 $1\r7__data_o$next[3:0]$11874 + end + sync always + update \r7__data_o$next $0\r7__data_o$next[3:0]$11873 + end + attribute \src "libresoc.v:183624.3-183653.6" + process $proc$libresoc.v:183624$11880 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11881 $1\wr_detect$13[0:0]$11882 + attribute \src "libresoc.v:183625.5-183625.29" + switch \initial + attribute \src "libresoc.v:183625.9-183625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11882 $4\wr_detect$13[0:0]$11885 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11883 1'1 + case + assign $2\wr_detect$13[0:0]$11883 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11884 1'1 + case + assign $3\wr_detect$13[0:0]$11884 $2\wr_detect$13[0:0]$11883 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11885 1'1 + case + assign $4\wr_detect$13[0:0]$11885 $3\wr_detect$13[0:0]$11884 + end + case + assign $1\wr_detect$13[0:0]$11882 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11881 + end + connect \$9 $not$libresoc.v:183187$11788_Y + connect \$12 $not$libresoc.v:183188$11789_Y + connect \$15 $not$libresoc.v:183189$11790_Y + connect \$1 $not$libresoc.v:183190$11791_Y + connect \$3 $not$libresoc.v:183191$11792_Y + connect \$6 $not$libresoc.v:183192$11793_Y +end +attribute \src "libresoc.v:183658.1-183716.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" +attribute \generator "nMigen" +module \req_l + attribute \src "libresoc.v:183659.7-183659.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183704.3-183712.6" + wire width 5 $0\q_int$next[4:0]$11904 + attribute \src "libresoc.v:183702.3-183703.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:183704.3-183712.6" + wire width 5 $1\q_int$next[4:0]$11905 + attribute \src "libresoc.v:183681.13-183681.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:183694.17-183694.96" + wire width 5 $and$libresoc.v:183694$11894_Y + attribute \src "libresoc.v:183699.17-183699.96" + wire width 5 $and$libresoc.v:183699$11899_Y + attribute \src "libresoc.v:183696.18-183696.93" + wire width 5 $not$libresoc.v:183696$11896_Y + attribute \src "libresoc.v:183698.17-183698.92" + wire width 5 $not$libresoc.v:183698$11898_Y + attribute \src "libresoc.v:183701.17-183701.92" + wire width 5 $not$libresoc.v:183701$11901_Y + attribute \src "libresoc.v:183695.18-183695.98" + wire width 5 $or$libresoc.v:183695$11895_Y + attribute \src "libresoc.v:183697.18-183697.99" + wire width 5 $or$libresoc.v:183697$11897_Y + attribute \src "libresoc.v:183700.17-183700.97" + wire width 5 $or$libresoc.v:183700$11900_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:183659.7-183659.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183694$11894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:183694$11894_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183699$11899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:183699$11899_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183696$11896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$libresoc.v:183696$11896_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183698$11898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:183698$11898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183701$11901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:183701$11901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183695$11895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:183695$11895_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183697$11897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:183697$11897_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183700$11900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:183700$11900_Y + end + attribute \src "libresoc.v:183659.7-183659.20" + process $proc$libresoc.v:183659$11906 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183681.13-183681.26" + process $proc$libresoc.v:183681$11907 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:183702.3-183703.27" + process $proc$libresoc.v:183702$11902 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:183704.3-183712.6" + process $proc$libresoc.v:183704$11903 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$11904 $1\q_int$next[4:0]$11905 + attribute \src "libresoc.v:183705.5-183705.29" + switch \initial + attribute \src "libresoc.v:183705.9-183705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$11905 5'00000 + case + assign $1\q_int$next[4:0]$11905 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$11904 + end + connect \$9 $and$libresoc.v:183694$11894_Y + connect \$11 $or$libresoc.v:183695$11895_Y + connect \$13 $not$libresoc.v:183696$11896_Y + connect \$15 $or$libresoc.v:183697$11897_Y + connect \$1 $not$libresoc.v:183698$11898_Y + connect \$3 $and$libresoc.v:183699$11899_Y + connect \$5 $or$libresoc.v:183700$11900_Y + connect \$7 $not$libresoc.v:183701$11901_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:183720.1-183778.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" +attribute \generator "nMigen" +module \req_l$103 + attribute \src "libresoc.v:183721.7-183721.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183766.3-183774.6" + wire width 4 $0\q_int$next[3:0]$11918 + attribute \src "libresoc.v:183764.3-183765.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:183766.3-183774.6" + wire width 4 $1\q_int$next[3:0]$11919 + attribute \src "libresoc.v:183743.13-183743.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:183756.17-183756.96" + wire width 4 $and$libresoc.v:183756$11908_Y + attribute \src "libresoc.v:183761.17-183761.96" + wire width 4 $and$libresoc.v:183761$11913_Y + attribute \src "libresoc.v:183758.18-183758.93" + wire width 4 $not$libresoc.v:183758$11910_Y + attribute \src "libresoc.v:183760.17-183760.92" + wire width 4 $not$libresoc.v:183760$11912_Y + attribute \src "libresoc.v:183763.17-183763.92" + wire width 4 $not$libresoc.v:183763$11915_Y + attribute \src "libresoc.v:183757.18-183757.98" + wire width 4 $or$libresoc.v:183757$11909_Y + attribute \src "libresoc.v:183759.18-183759.99" + wire width 4 $or$libresoc.v:183759$11911_Y + attribute \src "libresoc.v:183762.17-183762.97" + wire width 4 $or$libresoc.v:183762$11914_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:183721.7-183721.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183756$11908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:183756$11908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183761$11913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:183761$11913_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183758$11910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:183758$11910_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183760$11912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:183760$11912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183763$11915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:183763$11915_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183757$11909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:183757$11909_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183759$11911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:183759$11911_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183762$11914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:183762$11914_Y + end + attribute \src "libresoc.v:183721.7-183721.20" + process $proc$libresoc.v:183721$11920 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183743.13-183743.25" + process $proc$libresoc.v:183743$11921 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:183764.3-183765.27" + process $proc$libresoc.v:183764$11916 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:183766.3-183774.6" + process $proc$libresoc.v:183766$11917 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$11918 $1\q_int$next[3:0]$11919 + attribute \src "libresoc.v:183767.5-183767.29" + switch \initial + attribute \src "libresoc.v:183767.9-183767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$11919 4'0000 + case + assign $1\q_int$next[3:0]$11919 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$11918 + end + connect \$9 $and$libresoc.v:183756$11908_Y + connect \$11 $or$libresoc.v:183757$11909_Y + connect \$13 $not$libresoc.v:183758$11910_Y + connect \$15 $or$libresoc.v:183759$11911_Y + connect \$1 $not$libresoc.v:183760$11912_Y + connect \$3 $and$libresoc.v:183761$11913_Y + connect \$5 $or$libresoc.v:183762$11914_Y + connect \$7 $not$libresoc.v:183763$11915_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:183782.1-183840.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" +attribute \generator "nMigen" +module \req_l$12 + attribute \src "libresoc.v:183783.7-183783.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183828.3-183836.6" + wire width 3 $0\q_int$next[2:0]$11932 + attribute \src "libresoc.v:183826.3-183827.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:183828.3-183836.6" + wire width 3 $1\q_int$next[2:0]$11933 + attribute \src "libresoc.v:183805.13-183805.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:183818.17-183818.96" + wire width 3 $and$libresoc.v:183818$11922_Y + attribute \src "libresoc.v:183823.17-183823.96" + wire width 3 $and$libresoc.v:183823$11927_Y + attribute \src "libresoc.v:183820.18-183820.93" + wire width 3 $not$libresoc.v:183820$11924_Y + attribute \src "libresoc.v:183822.17-183822.92" + wire width 3 $not$libresoc.v:183822$11926_Y + attribute \src "libresoc.v:183825.17-183825.92" + wire width 3 $not$libresoc.v:183825$11929_Y + attribute \src "libresoc.v:183819.18-183819.98" + wire width 3 $or$libresoc.v:183819$11923_Y + attribute \src "libresoc.v:183821.18-183821.99" + wire width 3 $or$libresoc.v:183821$11925_Y + attribute \src "libresoc.v:183824.17-183824.97" + wire width 3 $or$libresoc.v:183824$11928_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:183783.7-183783.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183818$11922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:183818$11922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183823$11927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:183823$11927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183820$11924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:183820$11924_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183822$11926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:183822$11926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183825$11929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:183825$11929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183819$11923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:183819$11923_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183821$11925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:183821$11925_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183824$11928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:183824$11928_Y + end + attribute \src "libresoc.v:183783.7-183783.20" + process $proc$libresoc.v:183783$11934 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183805.13-183805.25" + process $proc$libresoc.v:183805$11935 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:183826.3-183827.27" + process $proc$libresoc.v:183826$11930 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:183828.3-183836.6" + process $proc$libresoc.v:183828$11931 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11932 $1\q_int$next[2:0]$11933 + attribute \src "libresoc.v:183829.5-183829.29" + switch \initial + attribute \src "libresoc.v:183829.9-183829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11933 3'000 + case + assign $1\q_int$next[2:0]$11933 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11932 + end + connect \$9 $and$libresoc.v:183818$11922_Y + connect \$11 $or$libresoc.v:183819$11923_Y + connect \$13 $not$libresoc.v:183820$11924_Y + connect \$15 $or$libresoc.v:183821$11925_Y + connect \$1 $not$libresoc.v:183822$11926_Y + connect \$3 $and$libresoc.v:183823$11927_Y + connect \$5 $or$libresoc.v:183824$11928_Y + connect \$7 $not$libresoc.v:183825$11929_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:183844.1-183902.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" +attribute \generator "nMigen" +module \req_l$121 + attribute \src "libresoc.v:183845.7-183845.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183890.3-183898.6" + wire width 3 $0\q_int$next[2:0]$11946 + attribute \src "libresoc.v:183888.3-183889.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:183890.3-183898.6" + wire width 3 $1\q_int$next[2:0]$11947 + attribute \src "libresoc.v:183867.13-183867.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:183880.17-183880.96" + wire width 3 $and$libresoc.v:183880$11936_Y + attribute \src "libresoc.v:183885.17-183885.96" + wire width 3 $and$libresoc.v:183885$11941_Y + attribute \src "libresoc.v:183882.18-183882.93" + wire width 3 $not$libresoc.v:183882$11938_Y + attribute \src "libresoc.v:183884.17-183884.92" + wire width 3 $not$libresoc.v:183884$11940_Y + attribute \src "libresoc.v:183887.17-183887.92" + wire width 3 $not$libresoc.v:183887$11943_Y + attribute \src "libresoc.v:183881.18-183881.98" + wire width 3 $or$libresoc.v:183881$11937_Y + attribute \src "libresoc.v:183883.18-183883.99" + wire width 3 $or$libresoc.v:183883$11939_Y + attribute \src "libresoc.v:183886.17-183886.97" + wire width 3 $or$libresoc.v:183886$11942_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:183845.7-183845.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:183880$11936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:183880$11936_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:183885$11941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:183885$11941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:183882$11938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:183882$11938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:183884$11940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:183884$11940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:183887$11943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:183887$11943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:183881$11937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:183881$11937_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:183883$11939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:183883$11939_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:183886$11942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:183886$11942_Y + end + attribute \src "libresoc.v:183845.7-183845.20" + process $proc$libresoc.v:183845$11948 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183867.13-183867.25" + process $proc$libresoc.v:183867$11949 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:183888.3-183889.27" + process $proc$libresoc.v:183888$11944 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:183890.3-183898.6" + process $proc$libresoc.v:183890$11945 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11946 $1\q_int$next[2:0]$11947 + attribute \src "libresoc.v:183891.5-183891.29" + switch \initial + attribute \src "libresoc.v:183891.9-183891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11947 3'000 + case + assign $1\q_int$next[2:0]$11947 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11946 + end + connect \$9 $and$libresoc.v:183880$11936_Y + connect \$11 $or$libresoc.v:183881$11937_Y + connect \$13 $not$libresoc.v:183882$11938_Y + connect \$15 $or$libresoc.v:183883$11939_Y + connect \$1 $not$libresoc.v:183884$11940_Y + connect \$3 $and$libresoc.v:183885$11941_Y + connect \$5 $or$libresoc.v:183886$11942_Y + connect \$7 $not$libresoc.v:183887$11943_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:183906.1-183964.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" +attribute \generator "nMigen" +module \req_l$25 + attribute \src "libresoc.v:183907.7-183907.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183952.3-183960.6" + wire width 3 $0\q_int$next[2:0]$11960 + attribute \src "libresoc.v:183950.3-183951.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:183952.3-183960.6" + wire width 3 $1\q_int$next[2:0]$11961 + attribute \src "libresoc.v:183929.13-183929.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:183942.17-183942.96" + wire width 3 $and$libresoc.v:183942$11950_Y + attribute \src "libresoc.v:183947.17-183947.96" + wire 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\Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:184073$11985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:184067$11979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:184067$11979_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184069$11981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:184069$11981_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184072$11984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:184072$11984_Y + end + attribute \src "libresoc.v:184031.7-184031.20" + process $proc$libresoc.v:184031$11990 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184053.13-184053.25" + process $proc$libresoc.v:184053$11991 + assign { } { } + assign $1\q_int[1:0] 2'00 + sync always + sync init + update \q_int $1\q_int[1:0] + end + attribute \src "libresoc.v:184074.3-184075.27" + process $proc$libresoc.v:184074$11986 + assign { } { } + assign $0\q_int[1:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[1:0] + end + attribute \src "libresoc.v:184076.3-184084.6" + process $proc$libresoc.v:184076$11987 + assign { } { } + assign { } { } + assign $0\q_int$next[1:0]$11988 $1\q_int$next[1:0]$11989 + attribute \src "libresoc.v:184077.5-184077.29" + switch \initial + attribute \src "libresoc.v:184077.9-184077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[1:0]$11989 2'00 + case + assign $1\q_int$next[1:0]$11989 \$5 + end + sync always + update \q_int$next $0\q_int$next[1:0]$11988 + end + connect \$9 $and$libresoc.v:184066$11978_Y + connect \$11 $or$libresoc.v:184067$11979_Y + connect \$13 $not$libresoc.v:184068$11980_Y + connect \$15 $or$libresoc.v:184069$11981_Y + connect \$1 $not$libresoc.v:184070$11982_Y + connect \$3 $and$libresoc.v:184071$11983_Y + connect \$5 $or$libresoc.v:184072$11984_Y + connect \$7 $not$libresoc.v:184073$11985_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:184092.1-184150.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" +attribute \generator "nMigen" +module \req_l$69 + attribute \src "libresoc.v:184093.7-184093.20" + wire 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$or$libresoc.v:184131$11995_Y + attribute \src "libresoc.v:184134.17-184134.97" + wire width 6 $or$libresoc.v:184134$11998_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src 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\A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:184128$11992_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184133$11997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:184133$11997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184130$11994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \Y $not$libresoc.v:184130$11994_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184132$11996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:184132$11996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:184135$11999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:184135$11999_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:184129$11993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:184129$11993_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184131$11995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:184131$11995_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184134$11998 + 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attribute \src "libresoc.v:184139.5-184139.29" + switch \initial + attribute \src "libresoc.v:184139.9-184139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$12003 6'000000 + case + assign $1\q_int$next[5:0]$12003 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$12002 + end + connect \$9 $and$libresoc.v:184128$11992_Y + connect \$11 $or$libresoc.v:184129$11993_Y + connect \$13 $not$libresoc.v:184130$11994_Y + connect \$15 $or$libresoc.v:184131$11995_Y + connect \$1 $not$libresoc.v:184132$11996_Y + connect \$3 $and$libresoc.v:184133$11997_Y + connect \$5 $or$libresoc.v:184134$11998_Y + connect \$7 $not$libresoc.v:184135$11999_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:184154.1-184212.10" +attribute \cells_not_processed 1 +attribute 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width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:184155.7-184155.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:184190$12006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:184190$12006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184195$12011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:184195$12011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184192$12008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:184192$12008_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184194$12010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:184194$12010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:184197$12013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:184197$12013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:184191$12007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:184191$12007_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184193$12009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:184193$12009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184196$12012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:184196$12012_Y + end + attribute \src "libresoc.v:184155.7-184155.20" + process $proc$libresoc.v:184155$12018 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184177.13-184177.25" + process $proc$libresoc.v:184177$12019 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:184198.3-184199.27" + process $proc$libresoc.v:184198$12014 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:184200.3-184208.6" + process $proc$libresoc.v:184200$12015 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$12016 $1\q_int$next[3:0]$12017 + attribute \src "libresoc.v:184201.5-184201.29" + switch \initial + attribute \src "libresoc.v:184201.9-184201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$12017 4'0000 + case + assign $1\q_int$next[3:0]$12017 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$12016 + end + connect \$9 $and$libresoc.v:184190$12006_Y + connect \$11 $or$libresoc.v:184191$12007_Y + connect \$13 $not$libresoc.v:184192$12008_Y + connect \$15 $or$libresoc.v:184193$12009_Y + connect \$1 $not$libresoc.v:184194$12010_Y + connect \$3 $and$libresoc.v:184195$12011_Y + connect \$5 $or$libresoc.v:184196$12012_Y + connect \$7 $not$libresoc.v:184197$12013_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:184216.1-184265.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" +attribute \generator "nMigen" +module \reset_l + attribute \src "libresoc.v:184217.7-184217.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184253.3-184261.6" + wire $0\q_int$next[0:0]$12027 + attribute \src "libresoc.v:184251.3-184252.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:184253.3-184261.6" + wire $1\q_int$next[0:0]$12028 + attribute \src "libresoc.v:184233.7-184233.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:184248.17-184248.96" + wire $and$libresoc.v:184248$12022_Y + attribute \src "libresoc.v:184247.17-184247.94" + wire $not$libresoc.v:184247$12021_Y + attribute \src "libresoc.v:184250.17-184250.94" + wire $not$libresoc.v:184250$12024_Y + attribute \src "libresoc.v:184246.17-184246.100" + wire $or$libresoc.v:184246$12020_Y + attribute \src "libresoc.v:184249.17-184249.99" + wire $or$libresoc.v:184249$12023_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:184217.7-184217.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184248$12022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:184248$12022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184247$12021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:184247$12021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184250$12024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:184250$12024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184246$12020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:184246$12020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184249$12023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:184249$12023_Y + end + attribute \src "libresoc.v:184217.7-184217.20" + process $proc$libresoc.v:184217$12029 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184233.7-184233.19" + process $proc$libresoc.v:184233$12030 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:184251.3-184252.27" + process $proc$libresoc.v:184251$12025 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:184253.3-184261.6" + process $proc$libresoc.v:184253$12026 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12027 $1\q_int$next[0:0]$12028 + attribute \src "libresoc.v:184254.5-184254.29" + switch \initial + attribute \src "libresoc.v:184254.9-184254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12028 1'0 + case + assign $1\q_int$next[0:0]$12028 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12027 + end + connect \$9 $or$libresoc.v:184246$12020_Y + connect \$1 $not$libresoc.v:184247$12021_Y + connect \$3 $and$libresoc.v:184248$12022_Y + connect \$5 $or$libresoc.v:184249$12023_Y + connect \$7 $not$libresoc.v:184250$12024_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:184269.1-184318.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" +attribute \generator "nMigen" +module \reset_l$131 + attribute \src "libresoc.v:184270.7-184270.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184306.3-184314.6" + wire $0\q_int$next[0:0]$12038 + attribute \src "libresoc.v:184304.3-184305.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:184306.3-184314.6" + wire $1\q_int$next[0:0]$12039 + attribute \src "libresoc.v:184286.7-184286.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:184301.17-184301.96" + wire $and$libresoc.v:184301$12033_Y + attribute \src "libresoc.v:184300.17-184300.94" + wire $not$libresoc.v:184300$12032_Y + attribute \src "libresoc.v:184303.17-184303.94" + wire $not$libresoc.v:184303$12035_Y + attribute \src "libresoc.v:184299.17-184299.100" + wire $or$libresoc.v:184299$12031_Y + attribute \src "libresoc.v:184302.17-184302.99" + wire $or$libresoc.v:184302$12034_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:184270.7-184270.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:184301$12033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:184301$12033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:184300$12032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:184300$12032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:184303$12035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:184303$12035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:184299$12031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:184299$12031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:184302$12034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:184302$12034_Y + end + attribute \src "libresoc.v:184270.7-184270.20" + process $proc$libresoc.v:184270$12040 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184286.7-184286.19" + process $proc$libresoc.v:184286$12041 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:184304.3-184305.27" + process $proc$libresoc.v:184304$12036 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:184306.3-184314.6" + process $proc$libresoc.v:184306$12037 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12038 $1\q_int$next[0:0]$12039 + attribute \src "libresoc.v:184307.5-184307.29" + switch \initial + attribute \src "libresoc.v:184307.9-184307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12039 1'0 + case + assign $1\q_int$next[0:0]$12039 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12038 + end + connect \$9 $or$libresoc.v:184299$12031_Y + connect \$1 $not$libresoc.v:184300$12032_Y + connect \$3 $and$libresoc.v:184301$12033_Y + connect \$5 $or$libresoc.v:184302$12034_Y + connect \$7 $not$libresoc.v:184303$12035_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:184322.1-184909.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +attribute \generator "nMigen" +module \right_mask + attribute \src "libresoc.v:184323.7-184323.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184521.3-184908.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:184521.3-184908.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:184521.3-184908.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:184521.3-184908.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:184521.3-184908.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:184521.3-184908.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:184521.3-184908.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:184521.3-184908.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:184521.3-184908.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:184521.3-184908.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:184521.3-184908.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:184521.3-184908.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:184521.3-184908.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:184521.3-184908.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:184521.3-184908.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:184521.3-184908.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:184521.3-184908.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:184521.3-184908.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:184521.3-184908.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:184521.3-184908.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:184521.3-184908.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:184521.3-184908.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:184521.3-184908.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:184521.3-184908.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:184521.3-184908.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:184521.3-184908.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:184521.3-184908.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:184521.3-184908.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:184521.3-184908.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:184521.3-184908.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:184521.3-184908.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:184521.3-184908.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:184521.3-184908.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:184521.3-184908.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:184521.3-184908.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:184521.3-184908.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:184521.3-184908.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:184521.3-184908.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:184521.3-184908.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:184521.3-184908.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:184521.3-184908.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:184521.3-184908.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:184521.3-184908.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:184521.3-184908.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:184521.3-184908.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:184521.3-184908.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:184521.3-184908.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:184521.3-184908.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:184521.3-184908.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:184521.3-184908.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:184521.3-184908.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:184521.3-184908.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:184521.3-184908.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:184521.3-184908.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:184521.3-184908.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:184521.3-184908.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:184521.3-184908.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:184521.3-184908.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:184521.3-184908.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:184521.3-184908.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:184521.3-184908.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:184521.3-184908.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:184521.3-184908.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:184521.3-184908.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:184521.3-184908.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:184457.17-184457.96" + wire $gt$libresoc.v:184457$12042_Y + attribute \src "libresoc.v:184458.18-184458.98" + wire $gt$libresoc.v:184458$12043_Y + attribute \src "libresoc.v:184459.19-184459.99" + wire $gt$libresoc.v:184459$12044_Y + attribute \src "libresoc.v:184460.19-184460.99" + wire $gt$libresoc.v:184460$12045_Y + attribute \src "libresoc.v:184461.19-184461.99" + wire $gt$libresoc.v:184461$12046_Y + attribute \src "libresoc.v:184462.19-184462.99" + wire $gt$libresoc.v:184462$12047_Y + attribute \src "libresoc.v:184463.19-184463.99" + wire $gt$libresoc.v:184463$12048_Y + attribute \src "libresoc.v:184464.19-184464.99" + wire $gt$libresoc.v:184464$12049_Y + attribute \src "libresoc.v:184465.19-184465.99" + wire $gt$libresoc.v:184465$12050_Y + attribute \src "libresoc.v:184466.19-184466.99" + wire $gt$libresoc.v:184466$12051_Y + attribute \src "libresoc.v:184467.19-184467.99" + wire $gt$libresoc.v:184467$12052_Y + attribute \src "libresoc.v:184468.18-184468.97" + wire $gt$libresoc.v:184468$12053_Y + attribute \src "libresoc.v:184469.19-184469.99" + wire $gt$libresoc.v:184469$12054_Y + attribute \src "libresoc.v:184470.19-184470.99" + wire $gt$libresoc.v:184470$12055_Y + attribute \src "libresoc.v:184471.19-184471.99" + wire $gt$libresoc.v:184471$12056_Y + attribute \src "libresoc.v:184472.19-184472.99" + wire $gt$libresoc.v:184472$12057_Y + attribute \src "libresoc.v:184473.19-184473.99" + wire $gt$libresoc.v:184473$12058_Y + attribute \src "libresoc.v:184474.18-184474.97" + wire $gt$libresoc.v:184474$12059_Y + attribute \src "libresoc.v:184475.18-184475.97" + wire $gt$libresoc.v:184475$12060_Y + attribute \src "libresoc.v:184476.18-184476.97" + wire $gt$libresoc.v:184476$12061_Y + attribute \src "libresoc.v:184477.17-184477.96" + wire $gt$libresoc.v:184477$12062_Y + attribute \src "libresoc.v:184478.18-184478.97" + wire $gt$libresoc.v:184478$12063_Y + attribute \src "libresoc.v:184479.18-184479.97" + wire $gt$libresoc.v:184479$12064_Y + attribute \src "libresoc.v:184480.18-184480.97" + wire $gt$libresoc.v:184480$12065_Y + attribute \src "libresoc.v:184481.18-184481.97" + wire $gt$libresoc.v:184481$12066_Y + attribute \src "libresoc.v:184482.18-184482.97" + wire $gt$libresoc.v:184482$12067_Y + attribute \src "libresoc.v:184483.18-184483.97" + wire $gt$libresoc.v:184483$12068_Y + attribute \src "libresoc.v:184484.18-184484.97" + wire $gt$libresoc.v:184484$12069_Y + attribute \src "libresoc.v:184485.18-184485.98" + wire $gt$libresoc.v:184485$12070_Y + attribute \src "libresoc.v:184486.18-184486.98" + wire $gt$libresoc.v:184486$12071_Y + attribute \src "libresoc.v:184487.18-184487.98" + wire $gt$libresoc.v:184487$12072_Y + attribute \src "libresoc.v:184488.17-184488.96" + wire $gt$libresoc.v:184488$12073_Y + attribute \src "libresoc.v:184489.18-184489.98" + wire $gt$libresoc.v:184489$12074_Y + attribute \src "libresoc.v:184490.18-184490.98" + wire $gt$libresoc.v:184490$12075_Y + attribute \src "libresoc.v:184491.18-184491.98" + wire $gt$libresoc.v:184491$12076_Y + attribute \src "libresoc.v:184492.18-184492.98" + wire $gt$libresoc.v:184492$12077_Y + attribute \src "libresoc.v:184493.18-184493.98" + wire $gt$libresoc.v:184493$12078_Y + attribute \src "libresoc.v:184494.18-184494.98" + wire $gt$libresoc.v:184494$12079_Y + attribute \src "libresoc.v:184495.18-184495.98" + wire $gt$libresoc.v:184495$12080_Y + attribute \src "libresoc.v:184496.18-184496.98" + wire $gt$libresoc.v:184496$12081_Y + attribute \src "libresoc.v:184497.18-184497.98" + wire $gt$libresoc.v:184497$12082_Y + attribute \src "libresoc.v:184498.18-184498.98" + wire $gt$libresoc.v:184498$12083_Y + attribute \src "libresoc.v:184499.17-184499.96" + wire $gt$libresoc.v:184499$12084_Y + attribute \src "libresoc.v:184500.18-184500.98" + wire $gt$libresoc.v:184500$12085_Y + attribute \src "libresoc.v:184501.18-184501.98" + wire $gt$libresoc.v:184501$12086_Y + attribute \src "libresoc.v:184502.18-184502.98" + wire $gt$libresoc.v:184502$12087_Y + attribute \src "libresoc.v:184503.18-184503.98" + wire $gt$libresoc.v:184503$12088_Y + attribute \src "libresoc.v:184504.18-184504.98" + wire $gt$libresoc.v:184504$12089_Y + attribute \src "libresoc.v:184505.18-184505.98" + wire $gt$libresoc.v:184505$12090_Y + attribute \src "libresoc.v:184506.18-184506.98" + wire $gt$libresoc.v:184506$12091_Y + attribute \src "libresoc.v:184507.18-184507.98" + wire $gt$libresoc.v:184507$12092_Y + attribute \src "libresoc.v:184508.18-184508.98" + wire $gt$libresoc.v:184508$12093_Y + attribute \src "libresoc.v:184509.18-184509.98" + wire $gt$libresoc.v:184509$12094_Y + attribute \src "libresoc.v:184510.17-184510.96" + wire $gt$libresoc.v:184510$12095_Y + attribute \src "libresoc.v:184511.18-184511.98" + wire $gt$libresoc.v:184511$12096_Y + attribute \src "libresoc.v:184512.18-184512.98" + wire $gt$libresoc.v:184512$12097_Y + attribute \src "libresoc.v:184513.18-184513.98" + wire $gt$libresoc.v:184513$12098_Y + attribute \src "libresoc.v:184514.18-184514.98" + wire $gt$libresoc.v:184514$12099_Y + attribute \src "libresoc.v:184515.18-184515.98" + wire $gt$libresoc.v:184515$12100_Y + attribute \src "libresoc.v:184516.18-184516.98" + wire $gt$libresoc.v:184516$12101_Y + attribute \src "libresoc.v:184517.18-184517.98" + wire $gt$libresoc.v:184517$12102_Y + attribute \src "libresoc.v:184518.18-184518.98" + wire $gt$libresoc.v:184518$12103_Y + attribute \src "libresoc.v:184519.18-184519.98" + wire $gt$libresoc.v:184519$12104_Y + attribute \src "libresoc.v:184520.18-184520.98" + wire $gt$libresoc.v:184520$12105_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$15 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wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$99 + attribute \src "libresoc.v:184323.7-184323.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184457$12042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:184457$12042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184458$12043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:184458$12043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184459$12044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:184459$12044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184460$12045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:184460$12045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184461$12046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:184461$12046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184462$12047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:184462$12047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184463$12048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:184463$12048_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184464$12049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:184464$12049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184465$12050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:184465$12050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184466$12051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:184466$12051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184467$12052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:184467$12052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184468$12053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:184468$12053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184469$12054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:184469$12054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184470$12055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:184470$12055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184471$12056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:184471$12056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184472$12057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:184472$12057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184473$12058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:184473$12058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184474$12059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:184474$12059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184475$12060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:184475$12060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184476$12061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:184476$12061_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184477$12062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:184477$12062_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184478$12063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:184478$12063_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184479$12064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:184479$12064_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184480$12065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:184480$12065_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184481$12066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:184481$12066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184482$12067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:184482$12067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184483$12068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:184483$12068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184484$12069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:184484$12069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184485$12070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:184485$12070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184486$12071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:184486$12071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184487$12072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:184487$12072_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184488$12073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:184488$12073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184489$12074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:184489$12074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184490$12075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:184490$12075_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184491$12076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:184491$12076_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184492$12077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:184492$12077_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184493$12078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:184493$12078_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184494$12079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:184494$12079_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184495$12080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:184495$12080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184496$12081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:184496$12081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184497$12082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:184497$12082_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184498$12083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:184498$12083_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184499$12084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$libresoc.v:184499$12084_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184500$12085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:184500$12085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184501$12086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:184501$12086_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184502$12087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:184502$12087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184503$12088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:184503$12088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184504$12089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:184504$12089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184505$12090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:184505$12090_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184506$12091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:184506$12091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184507$12092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:184507$12092_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184508$12093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:184508$12093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184509$12094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:184509$12094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184510$12095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:184510$12095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184511$12096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:184511$12096_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184512$12097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:184512$12097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184513$12098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:184513$12098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184514$12099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:184514$12099_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184515$12100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:184515$12100_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184516$12101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:184516$12101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184517$12102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:184517$12102_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184518$12103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:184518$12103_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184519$12104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:184519$12104_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:184520$12105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:184520$12105_Y + end + attribute \src "libresoc.v:184323.7-184323.20" + process $proc$libresoc.v:184323$12107 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184521.3-184908.6" + process $proc$libresoc.v:184521$12106 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:184522.5-184522.29" + switch \initial + attribute \src "libresoc.v:184522.9-184522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:184457$12042_Y + connect \$99 $gt$libresoc.v:184458$12043_Y + connect \$101 $gt$libresoc.v:184459$12044_Y + connect \$103 $gt$libresoc.v:184460$12045_Y + connect \$105 $gt$libresoc.v:184461$12046_Y + connect \$107 $gt$libresoc.v:184462$12047_Y + connect \$109 $gt$libresoc.v:184463$12048_Y + connect \$111 $gt$libresoc.v:184464$12049_Y + connect \$113 $gt$libresoc.v:184465$12050_Y + connect \$115 $gt$libresoc.v:184466$12051_Y + connect \$117 $gt$libresoc.v:184467$12052_Y + connect \$11 $gt$libresoc.v:184468$12053_Y + connect \$119 $gt$libresoc.v:184469$12054_Y + connect \$121 $gt$libresoc.v:184470$12055_Y + connect \$123 $gt$libresoc.v:184471$12056_Y + connect \$125 $gt$libresoc.v:184472$12057_Y + connect \$127 $gt$libresoc.v:184473$12058_Y + connect \$13 $gt$libresoc.v:184474$12059_Y + connect \$15 $gt$libresoc.v:184475$12060_Y + connect \$17 $gt$libresoc.v:184476$12061_Y + connect \$1 $gt$libresoc.v:184477$12062_Y + connect \$19 $gt$libresoc.v:184478$12063_Y + connect \$21 $gt$libresoc.v:184479$12064_Y + connect \$23 $gt$libresoc.v:184480$12065_Y + connect \$25 $gt$libresoc.v:184481$12066_Y + connect \$27 $gt$libresoc.v:184482$12067_Y + connect \$29 $gt$libresoc.v:184483$12068_Y + connect \$31 $gt$libresoc.v:184484$12069_Y + connect \$33 $gt$libresoc.v:184485$12070_Y + connect \$35 $gt$libresoc.v:184486$12071_Y + connect \$37 $gt$libresoc.v:184487$12072_Y + connect \$3 $gt$libresoc.v:184488$12073_Y + connect \$39 $gt$libresoc.v:184489$12074_Y + connect \$41 $gt$libresoc.v:184490$12075_Y + connect \$43 $gt$libresoc.v:184491$12076_Y + connect \$45 $gt$libresoc.v:184492$12077_Y + connect \$47 $gt$libresoc.v:184493$12078_Y + connect \$49 $gt$libresoc.v:184494$12079_Y + connect \$51 $gt$libresoc.v:184495$12080_Y + connect \$53 $gt$libresoc.v:184496$12081_Y + connect \$55 $gt$libresoc.v:184497$12082_Y + connect \$57 $gt$libresoc.v:184498$12083_Y + connect \$5 $gt$libresoc.v:184499$12084_Y + connect \$59 $gt$libresoc.v:184500$12085_Y + connect \$61 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185038.7-185038.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:185073$12136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185073$12136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185078$12141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185078$12141_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185075$12138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185075$12138_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185077$12140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185077$12140_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185080$12143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185080$12143_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185074$12137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185074$12137_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185076$12139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185076$12139_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185079$12142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:185079$12142_Y + end + attribute \src "libresoc.v:185038.7-185038.20" + process $proc$libresoc.v:185038$12148 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185060.7-185060.19" + process $proc$libresoc.v:185060$12149 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185081.3-185082.27" + process $proc$libresoc.v:185081$12144 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185083.3-185091.6" + process $proc$libresoc.v:185083$12145 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12146 $1\q_int$next[0:0]$12147 + attribute \src "libresoc.v:185084.5-185084.29" + switch \initial + attribute \src "libresoc.v:185084.9-185084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12147 1'0 + case + assign $1\q_int$next[0:0]$12147 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12146 + end + connect \$9 $and$libresoc.v:185073$12136_Y + connect \$11 $or$libresoc.v:185074$12137_Y + connect \$13 $not$libresoc.v:185075$12138_Y + connect \$15 $or$libresoc.v:185076$12139_Y + connect \$1 $not$libresoc.v:185077$12140_Y + connect \$3 $and$libresoc.v:185078$12141_Y + connect \$5 $or$libresoc.v:185079$12142_Y + connect \$7 $not$libresoc.v:185080$12143_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:185099.1-185157.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" +attribute \generator "nMigen" +module \rok_l$14 + attribute \src "libresoc.v:185100.7-185100.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185145.3-185153.6" + wire $0\q_int$next[0:0]$12160 + attribute \src "libresoc.v:185143.3-185144.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:185145.3-185153.6" + wire $1\q_int$next[0:0]$12161 + attribute \src "libresoc.v:185122.7-185122.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:185135.17-185135.96" + wire $and$libresoc.v:185135$12150_Y + attribute \src "libresoc.v:185140.17-185140.96" + wire $and$libresoc.v:185140$12155_Y + attribute \src "libresoc.v:185137.18-185137.94" + wire $not$libresoc.v:185137$12152_Y + attribute \src "libresoc.v:185139.17-185139.93" + wire $not$libresoc.v:185139$12154_Y + attribute \src "libresoc.v:185142.17-185142.93" + wire $not$libresoc.v:185142$12157_Y + attribute \src "libresoc.v:185136.18-185136.99" + wire $or$libresoc.v:185136$12151_Y + attribute \src "libresoc.v:185138.18-185138.100" + wire $or$libresoc.v:185138$12153_Y + attribute \src "libresoc.v:185141.17-185141.98" + wire $or$libresoc.v:185141$12156_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185100.7-185100.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:185135$12150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185135$12150_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185140$12155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185140$12155_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185137$12152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185137$12152_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185139$12154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185139$12154_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185142$12157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185142$12157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185136$12151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185136$12151_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185138$12153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185138$12153_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185141$12156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:185141$12156_Y + end + attribute \src "libresoc.v:185100.7-185100.20" + process $proc$libresoc.v:185100$12162 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185122.7-185122.19" + process $proc$libresoc.v:185122$12163 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185143.3-185144.27" + process $proc$libresoc.v:185143$12158 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185145.3-185153.6" + process $proc$libresoc.v:185145$12159 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12160 $1\q_int$next[0:0]$12161 + attribute \src "libresoc.v:185146.5-185146.29" + switch \initial + attribute \src "libresoc.v:185146.9-185146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12161 1'0 + case + assign $1\q_int$next[0:0]$12161 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12160 + end + connect \$9 $and$libresoc.v:185135$12150_Y + connect \$11 $or$libresoc.v:185136$12151_Y + connect \$13 $not$libresoc.v:185137$12152_Y + connect \$15 $or$libresoc.v:185138$12153_Y + connect \$1 $not$libresoc.v:185139$12154_Y + connect \$3 $and$libresoc.v:185140$12155_Y + connect \$5 $or$libresoc.v:185141$12156_Y + connect \$7 $not$libresoc.v:185142$12157_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:185161.1-185219.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" +attribute \generator "nMigen" +module \rok_l$27 + attribute \src "libresoc.v:185162.7-185162.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185207.3-185215.6" + wire $0\q_int$next[0:0]$12174 + attribute \src "libresoc.v:185205.3-185206.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:185207.3-185215.6" + wire $1\q_int$next[0:0]$12175 + attribute \src "libresoc.v:185184.7-185184.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:185197.17-185197.96" + wire $and$libresoc.v:185197$12164_Y + attribute \src "libresoc.v:185202.17-185202.96" + wire $and$libresoc.v:185202$12169_Y + attribute \src "libresoc.v:185199.18-185199.94" + wire $not$libresoc.v:185199$12166_Y + attribute \src "libresoc.v:185201.17-185201.93" + wire $not$libresoc.v:185201$12168_Y + attribute \src "libresoc.v:185204.17-185204.93" + wire $not$libresoc.v:185204$12171_Y + attribute \src "libresoc.v:185198.18-185198.99" + wire $or$libresoc.v:185198$12165_Y + attribute \src "libresoc.v:185200.18-185200.100" + wire $or$libresoc.v:185200$12167_Y + attribute \src "libresoc.v:185203.17-185203.98" + wire $or$libresoc.v:185203$12170_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185162.7-185162.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:185197$12164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185197$12164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185202$12169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185202$12169_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185199$12166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185199$12166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185201$12168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185201$12168_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185204$12171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185204$12171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185198$12165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185198$12165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185200$12167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185200$12167_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185203$12170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:185203$12170_Y + end + attribute \src "libresoc.v:185162.7-185162.20" + process $proc$libresoc.v:185162$12176 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185184.7-185184.19" + process $proc$libresoc.v:185184$12177 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185205.3-185206.27" + process $proc$libresoc.v:185205$12172 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185207.3-185215.6" + process $proc$libresoc.v:185207$12173 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12174 $1\q_int$next[0:0]$12175 + attribute \src "libresoc.v:185208.5-185208.29" + switch \initial + attribute \src "libresoc.v:185208.9-185208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12175 1'0 + case + assign $1\q_int$next[0:0]$12175 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12174 + end + connect \$9 $and$libresoc.v:185197$12164_Y + connect \$11 $or$libresoc.v:185198$12165_Y + connect \$13 $not$libresoc.v:185199$12166_Y + connect \$15 $or$libresoc.v:185200$12167_Y + connect \$1 $not$libresoc.v:185201$12168_Y + connect \$3 $and$libresoc.v:185202$12169_Y + connect \$5 $or$libresoc.v:185203$12170_Y + connect \$7 $not$libresoc.v:185204$12171_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:185223.1-185281.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" +attribute \generator "nMigen" +module \rok_l$43 + attribute \src "libresoc.v:185224.7-185224.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185269.3-185277.6" + wire $0\q_int$next[0:0]$12188 + attribute \src "libresoc.v:185267.3-185268.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:185269.3-185277.6" + wire $1\q_int$next[0:0]$12189 + attribute \src "libresoc.v:185246.7-185246.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:185259.17-185259.96" + wire $and$libresoc.v:185259$12178_Y + attribute \src "libresoc.v:185264.17-185264.96" + wire $and$libresoc.v:185264$12183_Y + attribute \src "libresoc.v:185261.18-185261.94" + wire $not$libresoc.v:185261$12180_Y + attribute \src "libresoc.v:185263.17-185263.93" + wire $not$libresoc.v:185263$12182_Y + attribute \src "libresoc.v:185266.17-185266.93" + wire $not$libresoc.v:185266$12185_Y + attribute \src "libresoc.v:185260.18-185260.99" + wire $or$libresoc.v:185260$12179_Y + attribute \src "libresoc.v:185262.18-185262.100" + wire $or$libresoc.v:185262$12181_Y + attribute \src "libresoc.v:185265.17-185265.98" + wire $or$libresoc.v:185265$12184_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185224.7-185224.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:185259$12178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185259$12178_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185264$12183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185264$12183_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185261$12180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185261$12180_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185263$12182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185263$12182_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185266$12185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185266$12185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185260$12179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185260$12179_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185262$12181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185262$12181_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185265$12184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:185265$12184_Y + end + attribute \src "libresoc.v:185224.7-185224.20" + process $proc$libresoc.v:185224$12190 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185246.7-185246.19" + process $proc$libresoc.v:185246$12191 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185267.3-185268.27" + process $proc$libresoc.v:185267$12186 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185269.3-185277.6" + process $proc$libresoc.v:185269$12187 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12188 $1\q_int$next[0:0]$12189 + attribute \src "libresoc.v:185270.5-185270.29" + switch \initial + attribute \src "libresoc.v:185270.9-185270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12189 1'0 + case + assign $1\q_int$next[0:0]$12189 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12188 + end + connect \$9 $and$libresoc.v:185259$12178_Y + connect \$11 $or$libresoc.v:185260$12179_Y + connect \$13 $not$libresoc.v:185261$12180_Y + connect \$15 $or$libresoc.v:185262$12181_Y + connect \$1 $not$libresoc.v:185263$12182_Y + connect \$3 $and$libresoc.v:185264$12183_Y + connect \$5 $or$libresoc.v:185265$12184_Y + connect \$7 $not$libresoc.v:185266$12185_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:185285.1-185343.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" +attribute \generator "nMigen" +module \rok_l$59 + attribute \src "libresoc.v:185286.7-185286.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185331.3-185339.6" + wire $0\q_int$next[0:0]$12202 + attribute \src "libresoc.v:185329.3-185330.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:185331.3-185339.6" + wire $1\q_int$next[0:0]$12203 + attribute \src "libresoc.v:185308.7-185308.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:185321.17-185321.96" + wire $and$libresoc.v:185321$12192_Y + attribute \src "libresoc.v:185326.17-185326.96" + wire $and$libresoc.v:185326$12197_Y + attribute \src "libresoc.v:185323.18-185323.94" + wire $not$libresoc.v:185323$12194_Y + attribute \src "libresoc.v:185325.17-185325.93" + wire $not$libresoc.v:185325$12196_Y + attribute \src "libresoc.v:185328.17-185328.93" + wire $not$libresoc.v:185328$12199_Y + attribute \src "libresoc.v:185322.18-185322.99" + wire $or$libresoc.v:185322$12193_Y + attribute \src "libresoc.v:185324.18-185324.100" + wire $or$libresoc.v:185324$12195_Y + attribute \src "libresoc.v:185327.17-185327.98" + wire $or$libresoc.v:185327$12198_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185286.7-185286.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:185321$12192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185321$12192_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185326$12197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185326$12197_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185323$12194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185323$12194_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185325$12196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185325$12196_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185328$12199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185328$12199_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185322$12193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185322$12193_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185324$12195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185324$12195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185327$12198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:185327$12198_Y + end + attribute \src "libresoc.v:185286.7-185286.20" + process $proc$libresoc.v:185286$12204 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185308.7-185308.19" + process $proc$libresoc.v:185308$12205 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185329.3-185330.27" + process $proc$libresoc.v:185329$12200 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185331.3-185339.6" + process $proc$libresoc.v:185331$12201 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12202 $1\q_int$next[0:0]$12203 + attribute \src "libresoc.v:185332.5-185332.29" + switch \initial + attribute \src "libresoc.v:185332.9-185332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12203 1'0 + case + assign $1\q_int$next[0:0]$12203 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12202 + end + connect \$9 $and$libresoc.v:185321$12192_Y + connect \$11 $or$libresoc.v:185322$12193_Y + connect \$13 $not$libresoc.v:185323$12194_Y + connect \$15 $or$libresoc.v:185324$12195_Y + connect \$1 $not$libresoc.v:185325$12196_Y + connect \$3 $and$libresoc.v:185326$12197_Y + connect \$5 $or$libresoc.v:185327$12198_Y + connect \$7 $not$libresoc.v:185328$12199_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:185347.1-185405.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" +attribute \generator "nMigen" +module \rok_l$71 + attribute \src "libresoc.v:185348.7-185348.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185393.3-185401.6" + wire $0\q_int$next[0:0]$12216 + attribute \src "libresoc.v:185391.3-185392.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:185393.3-185401.6" + wire $1\q_int$next[0:0]$12217 + attribute \src "libresoc.v:185370.7-185370.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:185383.17-185383.96" + wire $and$libresoc.v:185383$12206_Y + attribute \src "libresoc.v:185388.17-185388.96" + wire $and$libresoc.v:185388$12211_Y + attribute \src "libresoc.v:185385.18-185385.94" + wire $not$libresoc.v:185385$12208_Y + attribute \src "libresoc.v:185387.17-185387.93" + wire $not$libresoc.v:185387$12210_Y + attribute \src "libresoc.v:185390.17-185390.93" + wire $not$libresoc.v:185390$12213_Y + attribute \src "libresoc.v:185384.18-185384.99" + wire $or$libresoc.v:185384$12207_Y + attribute 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\B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185383$12206_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185388$12211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185388$12211_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185385$12208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185385$12208_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185387$12210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185387$12210_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185390$12213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185390$12213_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185384$12207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185384$12207_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185386$12209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185386$12209_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185389$12212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:185389$12212_Y + end + attribute \src "libresoc.v:185348.7-185348.20" + process $proc$libresoc.v:185348$12218 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185370.7-185370.19" + process $proc$libresoc.v:185370$12219 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185391.3-185392.27" + process $proc$libresoc.v:185391$12214 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185393.3-185401.6" + process $proc$libresoc.v:185393$12215 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12216 $1\q_int$next[0:0]$12217 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185410.7-185410.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:185445$12220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:185445$12220_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:185450$12225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185450$12225_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185447$12222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:185447$12222_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185449$12224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185449$12224_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185452$12227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:185452$12227_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185446$12221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:185446$12221_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185448$12223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:185448$12223_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185451$12226 + parameter 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"/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $not $not$libresoc.v:185656$12270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ml + connect \Y $not$libresoc.v:185656$12270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $or $or$libresoc.v:185635$12249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \right_shift + connect \Y $or$libresoc.v:185635$12249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $or $or$libresoc.v:185645$12259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$48 + connect \B \$54 + connect \Y $or$libresoc.v:185645$12259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:185646$12260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:185646$12260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:185648$12262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:185648$12262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:185651$12265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$60 + connect \B \$66 + connect \Y $or$libresoc.v:185651$12265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $or $or$libresoc.v:185655$12269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$72 + connect \Y $or$libresoc.v:185655$12269_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $pos$libresoc.v:185621$12235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:185621$12234_Y + connect \Y $pos$libresoc.v:185621$12235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $reduce_or $reduce_or$libresoc.v:185658$12272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \Y $reduce_or$libresoc.v:185658$12272_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + cell $sub $sub$libresoc.v:185628$12242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \mb$8 + connect \Y $sub$libresoc.v:185628$12242_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + cell $sub $sub$libresoc.v:185631$12245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 6'111111 + connect \B \me$13 + connect \Y $sub$libresoc.v:185631$12245_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185659.13-185662.4" + cell \left_mask \left_mask + connect \mask \left_mask_mask + connect \shift \left_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185663.14-185666.4" + cell \right_mask \right_mask + connect \mask \right_mask_mask + connect \shift \right_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185667.8-185671.4" + cell \rotl \rotl + connect \a \rotl_a + connect \b \rotl_b + connect \o \rotl_o + end + attribute \src "libresoc.v:185472.7-185472.20" + process $proc$libresoc.v:185472$12288 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185672.3-185686.6" + process $proc$libresoc.v:185672$12273 + assign { } { } + assign $0\hi32[31:0] $1\hi32[31:0] + attribute \src "libresoc.v:185673.5-185673.29" + switch \initial + attribute \src "libresoc.v:185673.9-185673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + switch { \sign_ext_rs \is_32bit } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\hi32[31:0] \rs [31:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\hi32[31:0] \rs [63:32] + end + sync always + update \hi32 $0\hi32[31:0] + end + attribute \src "libresoc.v:185687.3-185696.6" + process $proc$libresoc.v:185687$12274 + assign { } { } + assign { } { } + assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] + attribute \src "libresoc.v:185688.5-185688.29" + switch \initial + attribute \src "libresoc.v:185688.9-185688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\right_mask_shift[6:0] \$24 [6:0] + case + assign $1\right_mask_shift[6:0] 7'0000000 + end + sync always + update \right_mask_shift $0\right_mask_shift[6:0] + end + attribute \src "libresoc.v:185697.3-185708.6" + process $proc$libresoc.v:185697$12275 + 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:185885$12296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:185882$12293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:185882$12293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:185884$12295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:185884$12295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:185887$12298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:185887$12298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:185881$12292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:185881$12292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:185883$12294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:185883$12294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:185886$12297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:185886$12297_Y + end + attribute \src "libresoc.v:185845.7-185845.20" + process $proc$libresoc.v:185845$12303 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185867.7-185867.19" + process $proc$libresoc.v:185867$12304 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185888.3-185889.27" + process $proc$libresoc.v:185888$12299 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185890.3-185898.6" + process $proc$libresoc.v:185890$12300 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12301 $1\q_int$next[0:0]$12302 + attribute \src "libresoc.v:185891.5-185891.29" + switch \initial + attribute \src "libresoc.v:185891.9-185891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12302 1'0 + case + assign $1\q_int$next[0:0]$12302 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12301 + end + connect \$9 $and$libresoc.v:185880$12291_Y + connect \$11 $or$libresoc.v:185881$12292_Y + connect \$13 $not$libresoc.v:185882$12293_Y + connect \$15 $or$libresoc.v:185883$12294_Y + connect \$1 $not$libresoc.v:185884$12295_Y + connect \$3 $and$libresoc.v:185885$12296_Y + connect \$5 $or$libresoc.v:185886$12297_Y + connect \$7 $not$libresoc.v:185887$12298_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:185906.1-185964.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" +attribute \generator "nMigen" +module \rst_l$104 + attribute \src "libresoc.v:185907.7-185907.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185952.3-185960.6" + wire $0\q_int$next[0:0]$12315 + attribute \src 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\src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:185907.7-185907.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src 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$proc$libresoc.v:185907$12317 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185929.7-185929.19" + process $proc$libresoc.v:185929$12318 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:185950.3-185951.27" + process $proc$libresoc.v:185950$12313 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:185952.3-185960.6" + process $proc$libresoc.v:185952$12314 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12315 $1\q_int$next[0:0]$12316 + attribute \src "libresoc.v:185953.5-185953.29" + switch \initial + attribute \src "libresoc.v:185953.9-185953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12316 1'0 + case + assign $1\q_int$next[0:0]$12316 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12315 + end + connect \$9 $and$libresoc.v:185942$12305_Y + connect \$11 $or$libresoc.v:185943$12306_Y + connect \$13 $not$libresoc.v:185944$12307_Y + connect \$15 $or$libresoc.v:185945$12308_Y + connect \$1 $not$libresoc.v:185946$12309_Y + connect \$3 $and$libresoc.v:185947$12310_Y + connect \$5 $or$libresoc.v:185948$12311_Y + connect \$7 $not$libresoc.v:185949$12312_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:185968.1-186026.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" +attribute \generator "nMigen" +module \rst_l$122 + attribute \src "libresoc.v:185969.7-185969.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186014.3-186022.6" + wire $0\q_int$next[0:0]$12329 + attribute \src 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186009$12324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186006$12321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186006$12321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186008$12323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186008$12323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186011$12326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186011$12326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186005$12320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186005$12320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186007$12322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186007$12322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186010$12325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186010$12325_Y + end + attribute \src "libresoc.v:185969.7-185969.20" + process $proc$libresoc.v:185969$12331 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185991.7-185991.19" + process $proc$libresoc.v:185991$12332 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186012.3-186013.27" + process $proc$libresoc.v:186012$12327 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186014.3-186022.6" + process $proc$libresoc.v:186014$12328 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12329 $1\q_int$next[0:0]$12330 + attribute \src "libresoc.v:186015.5-186015.29" + switch \initial + attribute \src "libresoc.v:186015.9-186015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12330 1'0 + case + assign $1\q_int$next[0:0]$12330 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12329 + end + connect \$9 $and$libresoc.v:186004$12319_Y + connect \$11 $or$libresoc.v:186005$12320_Y + connect \$13 $not$libresoc.v:186006$12321_Y + connect \$15 $or$libresoc.v:186007$12322_Y + connect \$1 $not$libresoc.v:186008$12323_Y + connect \$3 $and$libresoc.v:186009$12324_Y + connect \$5 $or$libresoc.v:186010$12325_Y + connect \$7 $not$libresoc.v:186011$12326_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186030.1-186088.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" +attribute \generator "nMigen" +module \rst_l$129 + attribute \src "libresoc.v:186031.7-186031.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186076.3-186084.6" + wire $0\q_int$next[0:0]$12343 + attribute \src "libresoc.v:186074.3-186075.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186076.3-186084.6" + wire $1\q_int$next[0:0]$12344 + attribute \src "libresoc.v:186053.7-186053.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186066.17-186066.96" + wire $and$libresoc.v:186066$12333_Y + attribute \src "libresoc.v:186071.17-186071.96" + wire $and$libresoc.v:186071$12338_Y + attribute \src "libresoc.v:186068.18-186068.93" + wire $not$libresoc.v:186068$12335_Y + attribute \src "libresoc.v:186070.17-186070.92" + wire $not$libresoc.v:186070$12337_Y + attribute \src "libresoc.v:186073.17-186073.92" + wire $not$libresoc.v:186073$12340_Y + attribute \src "libresoc.v:186067.18-186067.98" + wire $or$libresoc.v:186067$12334_Y + attribute \src "libresoc.v:186069.18-186069.99" + wire $or$libresoc.v:186069$12336_Y + attribute \src "libresoc.v:186072.17-186072.97" + wire $or$libresoc.v:186072$12339_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186031.7-186031.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186066$12333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186066$12333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186071$12338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186071$12338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186068$12335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186068$12335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186070$12337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186070$12337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186073$12340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186073$12340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186067$12334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186067$12334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186069$12336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186069$12336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186072$12339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186072$12339_Y + end + attribute \src "libresoc.v:186031.7-186031.20" + process $proc$libresoc.v:186031$12345 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186053.7-186053.19" + process $proc$libresoc.v:186053$12346 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186074.3-186075.27" + process $proc$libresoc.v:186074$12341 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186076.3-186084.6" + process $proc$libresoc.v:186076$12342 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12343 $1\q_int$next[0:0]$12344 + attribute \src "libresoc.v:186077.5-186077.29" + switch \initial + attribute \src "libresoc.v:186077.9-186077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12344 1'0 + case + assign $1\q_int$next[0:0]$12344 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12343 + end + connect \$9 $and$libresoc.v:186066$12333_Y + connect \$11 $or$libresoc.v:186067$12334_Y + connect \$13 $not$libresoc.v:186068$12335_Y + connect \$15 $or$libresoc.v:186069$12336_Y + connect \$1 $not$libresoc.v:186070$12337_Y + connect \$3 $and$libresoc.v:186071$12338_Y + connect \$5 $or$libresoc.v:186072$12339_Y + connect \$7 $not$libresoc.v:186073$12340_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186092.1-186150.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" +attribute \generator "nMigen" +module \rst_l$13 + attribute \src "libresoc.v:186093.7-186093.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186138.3-186146.6" + wire $0\q_int$next[0:0]$12357 + attribute \src "libresoc.v:186136.3-186137.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186138.3-186146.6" + wire $1\q_int$next[0:0]$12358 + attribute \src "libresoc.v:186115.7-186115.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186128.17-186128.96" + wire $and$libresoc.v:186128$12347_Y + attribute \src "libresoc.v:186133.17-186133.96" + wire $and$libresoc.v:186133$12352_Y + attribute \src "libresoc.v:186130.18-186130.93" + wire $not$libresoc.v:186130$12349_Y + attribute \src "libresoc.v:186132.17-186132.92" + wire $not$libresoc.v:186132$12351_Y + attribute \src "libresoc.v:186135.17-186135.92" + wire $not$libresoc.v:186135$12354_Y + attribute \src "libresoc.v:186129.18-186129.98" + wire $or$libresoc.v:186129$12348_Y + attribute \src "libresoc.v:186131.18-186131.99" + wire $or$libresoc.v:186131$12350_Y + attribute \src "libresoc.v:186134.17-186134.97" + wire $or$libresoc.v:186134$12353_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186093.7-186093.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186128$12347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186128$12347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186133$12352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186133$12352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186130$12349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186130$12349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186132$12351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186132$12351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186135$12354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186135$12354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186129$12348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186129$12348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186131$12350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186131$12350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186134$12353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186134$12353_Y + end + attribute \src "libresoc.v:186093.7-186093.20" + process $proc$libresoc.v:186093$12359 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186115.7-186115.19" + process $proc$libresoc.v:186115$12360 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186136.3-186137.27" + process $proc$libresoc.v:186136$12355 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186138.3-186146.6" + process $proc$libresoc.v:186138$12356 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12357 $1\q_int$next[0:0]$12358 + attribute \src "libresoc.v:186139.5-186139.29" + switch \initial + attribute \src "libresoc.v:186139.9-186139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12358 1'0 + case + assign $1\q_int$next[0:0]$12358 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12357 + end + connect \$9 $and$libresoc.v:186128$12347_Y + connect \$11 $or$libresoc.v:186129$12348_Y + connect \$13 $not$libresoc.v:186130$12349_Y + connect \$15 $or$libresoc.v:186131$12350_Y + connect \$1 $not$libresoc.v:186132$12351_Y + connect \$3 $and$libresoc.v:186133$12352_Y + connect \$5 $or$libresoc.v:186134$12353_Y + connect \$7 $not$libresoc.v:186135$12354_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186154.1-186212.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" +attribute \generator "nMigen" +module \rst_l$26 + attribute \src "libresoc.v:186155.7-186155.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186200.3-186208.6" + wire $0\q_int$next[0:0]$12371 + attribute \src "libresoc.v:186198.3-186199.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186200.3-186208.6" + wire $1\q_int$next[0:0]$12372 + attribute \src "libresoc.v:186177.7-186177.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186190.17-186190.96" + wire $and$libresoc.v:186190$12361_Y + attribute \src "libresoc.v:186195.17-186195.96" + wire $and$libresoc.v:186195$12366_Y + attribute \src "libresoc.v:186192.18-186192.93" + wire $not$libresoc.v:186192$12363_Y + attribute \src "libresoc.v:186194.17-186194.92" + wire $not$libresoc.v:186194$12365_Y + attribute \src "libresoc.v:186197.17-186197.92" + wire $not$libresoc.v:186197$12368_Y + attribute \src "libresoc.v:186191.18-186191.98" + wire $or$libresoc.v:186191$12362_Y + attribute \src "libresoc.v:186193.18-186193.99" + wire $or$libresoc.v:186193$12364_Y + attribute \src "libresoc.v:186196.17-186196.97" + wire $or$libresoc.v:186196$12367_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186155.7-186155.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186190$12361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186190$12361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186195$12366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186195$12366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186192$12363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186192$12363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186194$12365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186194$12365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186197$12368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186197$12368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186191$12362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186191$12362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186193$12364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186193$12364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186196$12367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186196$12367_Y + end + attribute \src "libresoc.v:186155.7-186155.20" + process $proc$libresoc.v:186155$12373 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186177.7-186177.19" + process $proc$libresoc.v:186177$12374 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186198.3-186199.27" + process $proc$libresoc.v:186198$12369 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186200.3-186208.6" + process $proc$libresoc.v:186200$12370 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12371 $1\q_int$next[0:0]$12372 + attribute \src "libresoc.v:186201.5-186201.29" + switch \initial + attribute \src "libresoc.v:186201.9-186201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12372 1'0 + case + assign $1\q_int$next[0:0]$12372 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12371 + end + connect \$9 $and$libresoc.v:186190$12361_Y + connect \$11 $or$libresoc.v:186191$12362_Y + connect \$13 $not$libresoc.v:186192$12363_Y + connect \$15 $or$libresoc.v:186193$12364_Y + connect \$1 $not$libresoc.v:186194$12365_Y + connect \$3 $and$libresoc.v:186195$12366_Y + connect \$5 $or$libresoc.v:186196$12367_Y + connect \$7 $not$libresoc.v:186197$12368_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186216.1-186274.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" +attribute \generator "nMigen" +module \rst_l$42 + attribute \src "libresoc.v:186217.7-186217.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186262.3-186270.6" + wire $0\q_int$next[0:0]$12385 + attribute \src "libresoc.v:186260.3-186261.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186262.3-186270.6" + wire $1\q_int$next[0:0]$12386 + attribute \src "libresoc.v:186239.7-186239.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186252.17-186252.96" + wire $and$libresoc.v:186252$12375_Y + attribute \src "libresoc.v:186257.17-186257.96" + wire $and$libresoc.v:186257$12380_Y + attribute \src "libresoc.v:186254.18-186254.93" + wire $not$libresoc.v:186254$12377_Y + attribute \src "libresoc.v:186256.17-186256.92" + wire $not$libresoc.v:186256$12379_Y + attribute \src "libresoc.v:186259.17-186259.92" + wire $not$libresoc.v:186259$12382_Y + attribute \src "libresoc.v:186253.18-186253.98" + wire $or$libresoc.v:186253$12376_Y + attribute \src "libresoc.v:186255.18-186255.99" + wire $or$libresoc.v:186255$12378_Y + attribute \src "libresoc.v:186258.17-186258.97" + wire $or$libresoc.v:186258$12381_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186217.7-186217.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186252$12375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186252$12375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186257$12380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186257$12380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186254$12377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186254$12377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186256$12379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186256$12379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186259$12382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186259$12382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186253$12376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186253$12376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186255$12378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186255$12378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186258$12381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186258$12381_Y + end + attribute \src "libresoc.v:186217.7-186217.20" + process $proc$libresoc.v:186217$12387 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186239.7-186239.19" + process $proc$libresoc.v:186239$12388 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186260.3-186261.27" + process $proc$libresoc.v:186260$12383 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186262.3-186270.6" + process $proc$libresoc.v:186262$12384 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12385 $1\q_int$next[0:0]$12386 + attribute \src "libresoc.v:186263.5-186263.29" + switch \initial + attribute \src "libresoc.v:186263.9-186263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12386 1'0 + case + assign $1\q_int$next[0:0]$12386 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12385 + end + connect \$9 $and$libresoc.v:186252$12375_Y + connect \$11 $or$libresoc.v:186253$12376_Y + connect \$13 $not$libresoc.v:186254$12377_Y + connect \$15 $or$libresoc.v:186255$12378_Y + connect \$1 $not$libresoc.v:186256$12379_Y + connect \$3 $and$libresoc.v:186257$12380_Y + connect \$5 $or$libresoc.v:186258$12381_Y + connect \$7 $not$libresoc.v:186259$12382_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186278.1-186336.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" +attribute \generator "nMigen" +module \rst_l$58 + attribute \src "libresoc.v:186279.7-186279.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186324.3-186332.6" + wire $0\q_int$next[0:0]$12399 + attribute \src "libresoc.v:186322.3-186323.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186324.3-186332.6" + wire $1\q_int$next[0:0]$12400 + attribute \src "libresoc.v:186301.7-186301.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186314.17-186314.96" + wire $and$libresoc.v:186314$12389_Y + attribute \src "libresoc.v:186319.17-186319.96" + wire $and$libresoc.v:186319$12394_Y + attribute \src "libresoc.v:186316.18-186316.93" + wire $not$libresoc.v:186316$12391_Y + attribute \src "libresoc.v:186318.17-186318.92" + wire $not$libresoc.v:186318$12393_Y + attribute \src "libresoc.v:186321.17-186321.92" + wire $not$libresoc.v:186321$12396_Y + attribute \src "libresoc.v:186315.18-186315.98" + wire $or$libresoc.v:186315$12390_Y + attribute \src "libresoc.v:186317.18-186317.99" + wire $or$libresoc.v:186317$12392_Y + attribute \src "libresoc.v:186320.17-186320.97" + wire $or$libresoc.v:186320$12395_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186279.7-186279.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186314$12389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186314$12389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186319$12394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186319$12394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186316$12391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186316$12391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186318$12393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186318$12393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186321$12396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186321$12396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186315$12390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186315$12390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186317$12392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186317$12392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186320$12395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186320$12395_Y + end + attribute \src "libresoc.v:186279.7-186279.20" + process $proc$libresoc.v:186279$12401 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186301.7-186301.19" + process $proc$libresoc.v:186301$12402 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186322.3-186323.27" + process $proc$libresoc.v:186322$12397 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186324.3-186332.6" + process $proc$libresoc.v:186324$12398 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12399 $1\q_int$next[0:0]$12400 + attribute \src "libresoc.v:186325.5-186325.29" + switch \initial + attribute \src "libresoc.v:186325.9-186325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12400 1'0 + case + assign $1\q_int$next[0:0]$12400 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12399 + end + connect \$9 $and$libresoc.v:186314$12389_Y + connect \$11 $or$libresoc.v:186315$12390_Y + connect \$13 $not$libresoc.v:186316$12391_Y + connect \$15 $or$libresoc.v:186317$12392_Y + connect \$1 $not$libresoc.v:186318$12393_Y + connect \$3 $and$libresoc.v:186319$12394_Y + connect \$5 $or$libresoc.v:186320$12395_Y + connect \$7 $not$libresoc.v:186321$12396_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186340.1-186398.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" +attribute \generator "nMigen" +module \rst_l$70 + attribute \src "libresoc.v:186341.7-186341.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186386.3-186394.6" + wire $0\q_int$next[0:0]$12413 + attribute \src "libresoc.v:186384.3-186385.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186386.3-186394.6" + wire $1\q_int$next[0:0]$12414 + attribute \src "libresoc.v:186363.7-186363.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186376.17-186376.96" + wire $and$libresoc.v:186376$12403_Y + attribute \src "libresoc.v:186381.17-186381.96" + wire $and$libresoc.v:186381$12408_Y + attribute \src "libresoc.v:186378.18-186378.93" + wire $not$libresoc.v:186378$12405_Y + attribute \src "libresoc.v:186380.17-186380.92" + wire $not$libresoc.v:186380$12407_Y + attribute \src "libresoc.v:186383.17-186383.92" + wire $not$libresoc.v:186383$12410_Y + attribute \src "libresoc.v:186377.18-186377.98" + wire $or$libresoc.v:186377$12404_Y + attribute \src "libresoc.v:186379.18-186379.99" + wire $or$libresoc.v:186379$12406_Y + attribute \src "libresoc.v:186382.17-186382.97" + wire $or$libresoc.v:186382$12409_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186341.7-186341.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186376$12403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186376$12403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186381$12408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186381$12408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186378$12405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186378$12405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186380$12407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186380$12407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186383$12410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186383$12410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:186377$12404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:186377$12404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:186379$12406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:186379$12406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:186382$12409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:186382$12409_Y + end + attribute \src "libresoc.v:186341.7-186341.20" + process $proc$libresoc.v:186341$12415 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186363.7-186363.19" + process $proc$libresoc.v:186363$12416 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:186384.3-186385.27" + process $proc$libresoc.v:186384$12411 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:186386.3-186394.6" + process $proc$libresoc.v:186386$12412 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12413 $1\q_int$next[0:0]$12414 + attribute \src "libresoc.v:186387.5-186387.29" + switch \initial + attribute \src "libresoc.v:186387.9-186387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12414 1'0 + case + assign $1\q_int$next[0:0]$12414 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12413 + end + connect \$9 $and$libresoc.v:186376$12403_Y + connect \$11 $or$libresoc.v:186377$12404_Y + connect \$13 $not$libresoc.v:186378$12405_Y + connect \$15 $or$libresoc.v:186379$12406_Y + connect \$1 $not$libresoc.v:186380$12407_Y + connect \$3 $and$libresoc.v:186381$12408_Y + connect \$5 $or$libresoc.v:186382$12409_Y + connect \$7 $not$libresoc.v:186383$12410_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:186402.1-186460.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" +attribute \generator "nMigen" +module \rst_l$87 + attribute \src "libresoc.v:186403.7-186403.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186448.3-186456.6" + wire $0\q_int$next[0:0]$12427 + attribute \src "libresoc.v:186446.3-186447.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:186448.3-186456.6" + wire $1\q_int$next[0:0]$12428 + attribute \src "libresoc.v:186425.7-186425.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:186438.17-186438.96" + wire $and$libresoc.v:186438$12417_Y + attribute \src "libresoc.v:186443.17-186443.96" + wire $and$libresoc.v:186443$12422_Y + attribute \src "libresoc.v:186440.18-186440.93" + wire $not$libresoc.v:186440$12419_Y + attribute \src "libresoc.v:186442.17-186442.92" + wire $not$libresoc.v:186442$12421_Y + attribute \src "libresoc.v:186445.17-186445.92" + wire $not$libresoc.v:186445$12424_Y + attribute \src "libresoc.v:186439.18-186439.98" + wire $or$libresoc.v:186439$12418_Y + attribute \src "libresoc.v:186441.18-186441.99" + wire $or$libresoc.v:186441$12420_Y + attribute \src "libresoc.v:186444.17-186444.97" + wire $or$libresoc.v:186444$12423_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:186403.7-186403.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:186438$12417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:186438$12417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:186443$12422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:186443$12422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:186440$12419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:186440$12419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:186442$12421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186442$12421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:186445$12424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:186445$12424_Y + end + attribute \src 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"OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 50 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 49 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 41 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $and $and$libresoc.v:186810$12432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:186810$12432_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $and $and$libresoc.v:186812$12434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:186812$12434_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $and $and$libresoc.v:186821$12447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \$45 + connect \Y $and$libresoc.v:186821$12447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $and$libresoc.v:186824$12450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$libresoc.v:186824$12450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $eq $eq$libresoc.v:186820$12446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:186820$12446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $eq$libresoc.v:186823$12449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:186823$12449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + cell $eq $eq$libresoc.v:186826$12452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $eq$libresoc.v:186826$12452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $pos $extend$libresoc.v:186813$12435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:186813$12435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:186814$12437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:186814$12437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $pos $extend$libresoc.v:186816$12440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:186816$12440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:186817$12442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:186817$12442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $extend$libresoc.v:186829$12455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A \$62 + connect \Y $extend$libresoc.v:186829$12455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $ge $ge$libresoc.v:186819$12445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $ge$libresoc.v:186819$12445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $ge$libresoc.v:186822$12448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $ge$libresoc.v:186822$12448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $neg $neg$libresoc.v:186813$12436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:186813$12435_Y + connect \Y $neg$libresoc.v:186813$12436_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $neg $neg$libresoc.v:186816$12441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:186816$12440_Y + connect \Y $neg$libresoc.v:186816$12441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:186814$12438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:186814$12437_Y + connect \Y $pos$libresoc.v:186814$12438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:186817$12443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:186817$12442_Y + connect \Y $pos$libresoc.v:186817$12443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $pos$libresoc.v:186829$12456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 128 + connect \A $extend$libresoc.v:186829$12455_Y + connect \Y $pos$libresoc.v:186829$12456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $sshl $sshl$libresoc.v:186828$12454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $sshl$libresoc.v:186828$12454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + cell $sshl $sshl$libresoc.v:186830$12457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:186830$12457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $mux $ternary$libresoc.v:186809$12431 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:186809$12431_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $mux $ternary$libresoc.v:186811$12433 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:186811$12433_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $mux $ternary$libresoc.v:186815$12439 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \divisor_neg + connect \Y $ternary$libresoc.v:186815$12439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $mux $ternary$libresoc.v:186818$12444 + parameter \WIDTH 65 + connect \A \$39 + connect \B \$37 + connect \S \dividend_neg + connect \Y $ternary$libresoc.v:186818$12444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:186825$12451 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:186825$12451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:186827$12453 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:186827$12453_Y + end + attribute \src "libresoc.v:186465.7-186465.20" + process $proc$libresoc.v:186465$12459 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186831.3-186856.6" + process $proc$libresoc.v:186831$12458 + assign { } { } + assign { } { } + assign $0\dividend[127:0] $1\dividend[127:0] + attribute \src "libresoc.v:186832.5-186832.29" + switch \initial + attribute \src "libresoc.v:186832.9-186832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 , 7'0101111 + assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dividend[127:0] [31:0] \abs_dend [31:0] + assign $1\dividend[127:0] [63:32] \$59 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $1\dividend[127:0] $2\dividend[127:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend[127:0] \$61 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dividend[127:0] \$65 [127:0] + end + case + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dividend $0\dividend[127:0] + end + connect \$21 $ternary$libresoc.v:186809$12431_Y + connect \$23 $and$libresoc.v:186810$12432_Y + connect \$25 $ternary$libresoc.v:186811$12433_Y + connect \$27 $and$libresoc.v:186812$12434_Y + connect \$30 $neg$libresoc.v:186813$12436_Y + connect \$32 $pos$libresoc.v:186814$12438_Y + connect \$34 $ternary$libresoc.v:186815$12439_Y + connect \$37 $neg$libresoc.v:186816$12441_Y + connect \$39 $pos$libresoc.v:186817$12443_Y + connect \$41 $ternary$libresoc.v:186818$12444_Y + connect \$43 $ge$libresoc.v:186819$12445_Y + connect \$45 $eq$libresoc.v:186820$12446_Y + connect \$47 $and$libresoc.v:186821$12447_Y + connect \$49 $ge$libresoc.v:186822$12448_Y + connect \$51 $eq$libresoc.v:186823$12449_Y + connect \$53 $and$libresoc.v:186824$12450_Y + connect \$55 $ternary$libresoc.v:186825$12451_Y + connect \$57 $eq$libresoc.v:186826$12452_Y + connect \$59 $ternary$libresoc.v:186827$12453_Y + connect \$62 $sshl$libresoc.v:186828$12454_Y + connect \$61 $pos$libresoc.v:186829$12456_Y + connect \$66 $sshl$libresoc.v:186830$12457_Y + connect \$29 \$34 + connect \$36 \$41 + connect \$65 \$66 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \div_by_zero \$57 + connect \divisor_radicand [63:32] \$55 + connect \divisor_radicand [31:0] \abs_dor [31:0] + connect \dive_abs_ov32 \$53 + connect \dive_abs_ov64 \$47 + connect \abs_dend \$41 [63:0] + connect \abs_dor \$34 [63:0] + connect \divisor_neg \$27 + connect \dividend_neg \$23 + connect \operation 2'01 +end +attribute \src "libresoc.v:186877.1-188084.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" +attribute \generator "nMigen" +module \shiftrot0 + attribute \src "libresoc.v:187655.3-187656.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:187653.3-187654.46" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:188004.3-188012.6" + wire $0\alu_l_r_alu$next[0:0]$12677 + attribute \src "libresoc.v:187571.3-187572.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 + attribute \src "libresoc.v:187599.3-187600.75" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 + attribute \src "libresoc.v:187601.3-187602.89" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 + attribute \src "libresoc.v:187603.3-187604.85" + wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 + attribute \src "libresoc.v:187617.3-187618.83" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 + attribute \src "libresoc.v:187621.3-187622.77" + wire $0\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 + attribute \src "libresoc.v:187629.3-187630.69" + wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 + attribute \src "libresoc.v:187597.3-187598.79" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 + attribute \src "libresoc.v:187615.3-187616.79" + wire $0\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 + attribute \src "libresoc.v:187625.3-187626.77" + wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 + attribute \src "libresoc.v:187627.3-187628.79" + wire $0\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 + attribute \src "libresoc.v:187609.3-187610.73" + wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 + attribute \src "libresoc.v:187611.3-187612.73" + wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 + attribute \src "libresoc.v:187619.3-187620.85" + wire $0\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 + attribute \src "libresoc.v:187623.3-187624.79" + wire $0\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 + attribute \src "libresoc.v:187607.3-187608.73" + wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 + attribute \src "libresoc.v:187605.3-187606.73" + wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 + attribute \src "libresoc.v:187613.3-187614.79" + wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:187995.3-188003.6" + wire $0\alui_l_r_alui$next[0:0]$12674 + attribute \src "libresoc.v:187573.3-187574.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $0\data_r0__o$next[63:0]$12635 + attribute \src "libresoc.v:187593.3-187594.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:187879.3-187900.6" + wire $0\data_r0__o_ok$next[0:0]$12636 + attribute \src "libresoc.v:187595.3-187596.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12643 + attribute \src "libresoc.v:187589.3-187590.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:187901.3-187922.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12644 + attribute \src "libresoc.v:187591.3-187592.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12651 + attribute \src "libresoc.v:187585.3-187586.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:187923.3-187944.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12652 + attribute \src "libresoc.v:187587.3-187588.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:188013.3-188022.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:188023.3-188032.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:188033.3-188042.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:186878.7-186878.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187796.3-187804.6" + wire $0\opc_l_r_opc$next[0:0]$12579 + attribute \src "libresoc.v:187639.3-187640.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:187787.3-187795.6" + wire $0\opc_l_s_opc$next[0:0]$12576 + attribute \src "libresoc.v:187641.3-187642.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:188043.3-188051.6" + wire width 3 $0\prev_wr_go$next[2:0]$12683 + attribute \src "libresoc.v:187651.3-187652.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:187741.3-187750.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:187832.3-187840.6" + wire width 3 $0\req_l_r_req$next[2:0]$12591 + attribute \src "libresoc.v:187631.3-187632.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:187823.3-187831.6" + wire width 3 $0\req_l_s_req$next[2:0]$12588 + attribute \src "libresoc.v:187633.3-187634.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:187760.3-187768.6" + wire $0\rok_l_r_rdok$next[0:0]$12567 + attribute \src "libresoc.v:187647.3-187648.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:187751.3-187759.6" + wire $0\rok_l_s_rdok$next[0:0]$12564 + attribute \src "libresoc.v:187649.3-187650.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:187778.3-187786.6" + wire $0\rst_l_r_rst$next[0:0]$12573 + attribute \src "libresoc.v:187643.3-187644.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:187769.3-187777.6" + wire $0\rst_l_s_rst$next[0:0]$12570 + attribute \src "libresoc.v:187645.3-187646.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:187814.3-187822.6" + wire width 5 $0\src_l_r_src$next[4:0]$12585 + attribute \src "libresoc.v:187635.3-187636.39" + wire width 5 $0\src_l_r_src[4:0] + attribute \src "libresoc.v:187805.3-187813.6" + wire width 5 $0\src_l_s_src$next[4:0]$12582 + attribute \src "libresoc.v:187637.3-187638.39" + wire width 5 $0\src_l_s_src[4:0] + attribute \src "libresoc.v:187945.3-187954.6" + wire width 64 $0\src_r0$next[63:0]$12659 + attribute \src "libresoc.v:187583.3-187584.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:187955.3-187964.6" + wire width 64 $0\src_r1$next[63:0]$12662 + attribute \src "libresoc.v:187581.3-187582.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:187965.3-187974.6" + wire width 64 $0\src_r2$next[63:0]$12665 + attribute \src "libresoc.v:187579.3-187580.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:187975.3-187984.6" + wire $0\src_r3$next[0:0]$12668 + attribute \src "libresoc.v:187577.3-187578.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:187985.3-187994.6" + wire width 2 $0\src_r4$next[1:0]$12671 + attribute \src "libresoc.v:187575.3-187576.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:187000.7-187000.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:187010.7-187010.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:188004.3-188012.6" + wire $1\alu_l_r_alu$next[0:0]$12678 + attribute \src "libresoc.v:187018.7-187018.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 + attribute \src "libresoc.v:187061.14-187061.54" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + attribute \src "libresoc.v:187065.14-187065.73" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + attribute \src "libresoc.v:187069.7-187069.48" + wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 + attribute \src "libresoc.v:187077.13-187077.53" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 + attribute \src "libresoc.v:187081.7-187081.44" + wire $1\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 + attribute \src "libresoc.v:187085.14-187085.48" + wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 + attribute \src "libresoc.v:187164.13-187164.52" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 + attribute \src "libresoc.v:187168.7-187168.45" + wire $1\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 + attribute \src "libresoc.v:187172.7-187172.44" + wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 + attribute \src "libresoc.v:187176.7-187176.45" + wire $1\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 + attribute \src "libresoc.v:187180.7-187180.42" + wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 + attribute \src "libresoc.v:187184.7-187184.42" + wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 + attribute \src "libresoc.v:187188.7-187188.48" + wire $1\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 + attribute \src "libresoc.v:187192.7-187192.45" + wire $1\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 + attribute \src "libresoc.v:187196.7-187196.42" + wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 + attribute \src "libresoc.v:187200.7-187200.42" + wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 + attribute \src "libresoc.v:187204.7-187204.45" + wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:187995.3-188003.6" + wire $1\alui_l_r_alui$next[0:0]$12675 + attribute \src "libresoc.v:187216.7-187216.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $1\data_r0__o$next[63:0]$12637 + attribute \src "libresoc.v:187250.14-187250.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:187879.3-187900.6" + wire $1\data_r0__o_ok$next[0:0]$12638 + attribute \src "libresoc.v:187254.7-187254.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12645 + attribute \src "libresoc.v:187258.13-187258.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:187901.3-187922.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12646 + attribute \src "libresoc.v:187262.7-187262.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12653 + attribute \src "libresoc.v:187266.13-187266.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:187923.3-187944.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12654 + attribute \src "libresoc.v:187270.7-187270.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:188013.3-188022.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:188023.3-188032.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:188033.3-188042.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:187796.3-187804.6" + wire $1\opc_l_r_opc$next[0:0]$12580 + attribute \src "libresoc.v:187287.7-187287.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:187787.3-187795.6" + wire $1\opc_l_s_opc$next[0:0]$12577 + attribute \src "libresoc.v:187291.7-187291.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:188043.3-188051.6" + wire width 3 $1\prev_wr_go$next[2:0]$12684 + attribute \src "libresoc.v:187423.13-187423.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:187741.3-187750.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:187832.3-187840.6" + wire width 3 $1\req_l_r_req$next[2:0]$12592 + attribute \src "libresoc.v:187431.13-187431.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:187823.3-187831.6" + wire width 3 $1\req_l_s_req$next[2:0]$12589 + attribute \src "libresoc.v:187435.13-187435.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:187760.3-187768.6" + wire $1\rok_l_r_rdok$next[0:0]$12568 + attribute \src "libresoc.v:187447.7-187447.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:187751.3-187759.6" + wire $1\rok_l_s_rdok$next[0:0]$12565 + attribute \src "libresoc.v:187451.7-187451.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:187778.3-187786.6" + wire $1\rst_l_r_rst$next[0:0]$12574 + attribute \src "libresoc.v:187455.7-187455.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:187769.3-187777.6" + wire $1\rst_l_s_rst$next[0:0]$12571 + attribute \src "libresoc.v:187459.7-187459.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:187814.3-187822.6" + wire width 5 $1\src_l_r_src$next[4:0]$12586 + attribute \src "libresoc.v:187477.13-187477.32" + wire width 5 $1\src_l_r_src[4:0] + attribute \src "libresoc.v:187805.3-187813.6" + wire width 5 $1\src_l_s_src$next[4:0]$12583 + attribute \src "libresoc.v:187481.13-187481.32" + wire width 5 $1\src_l_s_src[4:0] + attribute \src "libresoc.v:187945.3-187954.6" + wire width 64 $1\src_r0$next[63:0]$12660 + attribute \src "libresoc.v:187487.14-187487.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:187955.3-187964.6" + wire width 64 $1\src_r1$next[63:0]$12663 + attribute \src "libresoc.v:187491.14-187491.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:187965.3-187974.6" + wire width 64 $1\src_r2$next[63:0]$12666 + attribute \src "libresoc.v:187495.14-187495.43" + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_shift_rot0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_shift_rot0_xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_shift_rot0_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 37 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 31 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 30 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 32 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 34 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 36 \dest3_o + attribute \src "libresoc.v:186878.7-186878.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute 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connect \B { 3'111 \$96 1'1 } + connect \Y $and$libresoc.v:187570$12518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:187540$12488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:187540$12488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:187542$12490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:187542$12490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:187512$12460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:187512$12460_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:187523$12471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:187523$12471_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:187525$12473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:187525$12473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:187528$12476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:187528$12476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:187531$12479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:187531$12479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:187537$12485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_ready_i + connect \Y $not$libresoc.v:187537$12485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:187548$12496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:187548$12496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:187569$12517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $not$libresoc.v:187569$12517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:187536$12484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:187536$12484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:187546$12494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:187546$12494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:187547$12495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:187547$12495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:187549$12497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:187549$12497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:187550$12498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:187550$12498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:187553$12501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:187553$12501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:187559$12507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:187559$12507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:187565$12513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:187565$12513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:187530$12478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:187530$12478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:187534$12482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:187534$12482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:187535$12483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:187535$12483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:187557$12505 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:187557$12505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:187558$12506 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_shift_rot0_sr_op__imm_data__data + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:187558$12506_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:187560$12508 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:187560$12508_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:187561$12509 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:187561$12509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:187562$12510 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:187562$12510_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:187563$12511 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:187563$12511_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:187564$12512 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:187564$12512_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187657.15-187663.4" + cell \alu_l$125 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187664.18-187699.4" + cell \alu_shift_rot0 \alu_shift_rot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_shift_rot0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \o \alu_shift_rot0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_shift_rot0_p_ready_o + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit + connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data + connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok + connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry + connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr + connect \sr_op__insn \alu_shift_rot0_sr_op__insn + connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__invert_in \alu_shift_rot0_sr_op__invert_in + connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit + connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed + connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe + connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok + connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry + connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr + connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok + connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc + connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 + connect \xer_ca \alu_shift_rot0_xer_ca + connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 + connect \xer_ca_ok \xer_ca_ok + connect \xer_so \alu_shift_rot0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187700.16-187706.4" + cell \alui_l$124 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187707.15-187713.4" + cell \opc_l$120 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187714.15-187720.4" + cell \req_l$121 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187721.15-187727.4" + cell \rok_l$123 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187728.15-187733.4" + cell \rst_l$122 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:187734.15-187740.4" + cell \src_l$119 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:186878.7-186878.20" + process $proc$libresoc.v:186878$12685 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187000.7-187000.24" + process $proc$libresoc.v:187000$12686 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:187010.7-187010.26" + process $proc$libresoc.v:187010$12687 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:187018.7-187018.25" + process $proc$libresoc.v:187018$12688 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:187061.14-187061.54" + process $proc$libresoc.v:187061$12689 + assign { } { } + assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:187065.14-187065.73" + process $proc$libresoc.v:187065$12690 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:187069.7-187069.48" + process $proc$libresoc.v:187069$12691 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:187077.13-187077.53" + process $proc$libresoc.v:187077$12692 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:187081.7-187081.44" + process $proc$libresoc.v:187081$12693 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:187085.14-187085.48" + process $proc$libresoc.v:187085$12694 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 + sync always + sync init + update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:187164.13-187164.52" + process $proc$libresoc.v:187164$12695 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:187168.7-187168.45" + process $proc$libresoc.v:187168$12696 + assign { } { } + assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:187172.7-187172.44" + process $proc$libresoc.v:187172$12697 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:187176.7-187176.45" + process $proc$libresoc.v:187176$12698 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:187180.7-187180.42" + process $proc$libresoc.v:187180$12699 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:187184.7-187184.42" + process $proc$libresoc.v:187184$12700 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:187188.7-187188.48" + process $proc$libresoc.v:187188$12701 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:187192.7-187192.45" + process $proc$libresoc.v:187192$12702 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:187196.7-187196.42" + process $proc$libresoc.v:187196$12703 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:187200.7-187200.42" + process $proc$libresoc.v:187200$12704 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:187204.7-187204.45" + process $proc$libresoc.v:187204$12705 + assign { } { } + assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:187216.7-187216.27" + process $proc$libresoc.v:187216$12706 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:187250.14-187250.47" + process $proc$libresoc.v:187250$12707 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:187254.7-187254.27" + process $proc$libresoc.v:187254$12708 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:187258.13-187258.33" + process $proc$libresoc.v:187258$12709 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:187262.7-187262.30" + process $proc$libresoc.v:187262$12710 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:187266.13-187266.35" + process $proc$libresoc.v:187266$12711 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:187270.7-187270.32" + process $proc$libresoc.v:187270$12712 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:187287.7-187287.25" + process $proc$libresoc.v:187287$12713 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:187291.7-187291.25" + process $proc$libresoc.v:187291$12714 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:187423.13-187423.30" + process $proc$libresoc.v:187423$12715 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:187431.13-187431.31" + process $proc$libresoc.v:187431$12716 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:187435.13-187435.31" + process $proc$libresoc.v:187435$12717 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:187447.7-187447.26" + process $proc$libresoc.v:187447$12718 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:187451.7-187451.26" + process $proc$libresoc.v:187451$12719 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:187455.7-187455.25" + process $proc$libresoc.v:187455$12720 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:187459.7-187459.25" + process $proc$libresoc.v:187459$12721 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:187477.13-187477.32" + process $proc$libresoc.v:187477$12722 + assign { } { } + assign $1\src_l_r_src[4:0] 5'11111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[4:0] + end + attribute \src "libresoc.v:187481.13-187481.32" + process $proc$libresoc.v:187481$12723 + assign { } { } + assign $1\src_l_s_src[4:0] 5'00000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[4:0] + end + attribute \src "libresoc.v:187487.14-187487.43" + process $proc$libresoc.v:187487$12724 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:187491.14-187491.43" + process $proc$libresoc.v:187491$12725 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:187495.14-187495.43" + process $proc$libresoc.v:187495$12726 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:187499.7-187499.20" + process $proc$libresoc.v:187499$12727 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:187503.13-187503.26" + process $proc$libresoc.v:187503$12728 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:187571.3-187572.39" + process $proc$libresoc.v:187571$12519 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:187573.3-187574.43" + process $proc$libresoc.v:187573$12520 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:187575.3-187576.29" + process $proc$libresoc.v:187575$12521 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:187577.3-187578.29" + process $proc$libresoc.v:187577$12522 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:187579.3-187580.29" + process $proc$libresoc.v:187579$12523 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:187581.3-187582.29" + process $proc$libresoc.v:187581$12524 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:187583.3-187584.29" + process $proc$libresoc.v:187583$12525 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:187585.3-187586.47" + process $proc$libresoc.v:187585$12526 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:187587.3-187588.53" + process $proc$libresoc.v:187587$12527 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:187589.3-187590.43" + process $proc$libresoc.v:187589$12528 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:187591.3-187592.49" + process $proc$libresoc.v:187591$12529 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:187593.3-187594.37" + process $proc$libresoc.v:187593$12530 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:187595.3-187596.43" + process $proc$libresoc.v:187595$12531 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:187597.3-187598.79" + process $proc$libresoc.v:187597$12532 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:187599.3-187600.75" + process $proc$libresoc.v:187599$12533 + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:187601.3-187602.89" + process $proc$libresoc.v:187601$12534 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:187603.3-187604.85" + process $proc$libresoc.v:187603$12535 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:187605.3-187606.73" + process $proc$libresoc.v:187605$12536 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:187607.3-187608.73" + process $proc$libresoc.v:187607$12537 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:187609.3-187610.73" + process $proc$libresoc.v:187609$12538 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:187611.3-187612.73" + process $proc$libresoc.v:187611$12539 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:187613.3-187614.79" + process $proc$libresoc.v:187613$12540 + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:187615.3-187616.79" + process $proc$libresoc.v:187615$12541 + assign { } { } + assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:187617.3-187618.83" + process $proc$libresoc.v:187617$12542 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:187619.3-187620.85" + process $proc$libresoc.v:187619$12543 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:187621.3-187622.77" + process $proc$libresoc.v:187621$12544 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:187623.3-187624.79" + process $proc$libresoc.v:187623$12545 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:187625.3-187626.77" + process $proc$libresoc.v:187625$12546 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:187627.3-187628.79" + process $proc$libresoc.v:187627$12547 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:187629.3-187630.69" + process $proc$libresoc.v:187629$12548 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:187631.3-187632.39" + process $proc$libresoc.v:187631$12549 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:187633.3-187634.39" + process $proc$libresoc.v:187633$12550 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:187635.3-187636.39" + process $proc$libresoc.v:187635$12551 + assign { } { } + assign $0\src_l_r_src[4:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[4:0] + end + attribute \src "libresoc.v:187637.3-187638.39" + process $proc$libresoc.v:187637$12552 + assign { } { } + assign $0\src_l_s_src[4:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[4:0] + end + attribute \src "libresoc.v:187639.3-187640.39" + process $proc$libresoc.v:187639$12553 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:187641.3-187642.39" + process $proc$libresoc.v:187641$12554 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:187643.3-187644.39" + process $proc$libresoc.v:187643$12555 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:187645.3-187646.39" + process $proc$libresoc.v:187645$12556 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:187647.3-187648.41" + process $proc$libresoc.v:187647$12557 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:187649.3-187650.41" + process $proc$libresoc.v:187649$12558 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:187651.3-187652.37" + process $proc$libresoc.v:187651$12559 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:187653.3-187654.46" + process $proc$libresoc.v:187653$12560 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:187655.3-187656.25" + process $proc$libresoc.v:187655$12561 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:187741.3-187750.6" + process $proc$libresoc.v:187741$12562 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:187742.5-187742.29" + switch \initial + attribute \src "libresoc.v:187742.9-187742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:187751.3-187759.6" + process $proc$libresoc.v:187751$12563 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$12564 $1\rok_l_s_rdok$next[0:0]$12565 + attribute \src "libresoc.v:187752.5-187752.29" + switch \initial + attribute \src "libresoc.v:187752.9-187752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$12565 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$12565 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12564 + end + attribute \src "libresoc.v:187760.3-187768.6" + process $proc$libresoc.v:187760$12566 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$12567 $1\rok_l_r_rdok$next[0:0]$12568 + attribute \src "libresoc.v:187761.5-187761.29" + switch \initial + attribute \src "libresoc.v:187761.9-187761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$12568 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$12568 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12567 + end + attribute \src "libresoc.v:187769.3-187777.6" + process $proc$libresoc.v:187769$12569 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$12570 $1\rst_l_s_rst$next[0:0]$12571 + attribute \src "libresoc.v:187770.5-187770.29" + switch \initial + attribute \src "libresoc.v:187770.9-187770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$12571 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$12571 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12570 + end + attribute \src "libresoc.v:187778.3-187786.6" + process $proc$libresoc.v:187778$12572 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$12573 $1\rst_l_r_rst$next[0:0]$12574 + attribute \src "libresoc.v:187779.5-187779.29" + switch \initial + attribute \src "libresoc.v:187779.9-187779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$12574 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$12574 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12573 + end + attribute \src "libresoc.v:187787.3-187795.6" + process $proc$libresoc.v:187787$12575 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$12576 $1\opc_l_s_opc$next[0:0]$12577 + attribute \src "libresoc.v:187788.5-187788.29" + switch \initial + attribute \src "libresoc.v:187788.9-187788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$12577 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$12577 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12576 + end + attribute \src "libresoc.v:187796.3-187804.6" + process $proc$libresoc.v:187796$12578 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$12579 $1\opc_l_r_opc$next[0:0]$12580 + attribute \src "libresoc.v:187797.5-187797.29" + switch \initial + attribute \src "libresoc.v:187797.9-187797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$12580 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$12580 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12579 + end + attribute \src "libresoc.v:187805.3-187813.6" + process $proc$libresoc.v:187805$12581 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[4:0]$12582 $1\src_l_s_src$next[4:0]$12583 + attribute \src "libresoc.v:187806.5-187806.29" + switch \initial + attribute \src "libresoc.v:187806.9-187806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[4:0]$12583 5'00000 + case + assign $1\src_l_s_src$next[4:0]$12583 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12582 + end + attribute \src "libresoc.v:187814.3-187822.6" + process $proc$libresoc.v:187814$12584 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[4:0]$12585 $1\src_l_r_src$next[4:0]$12586 + attribute \src "libresoc.v:187815.5-187815.29" + switch \initial + attribute \src "libresoc.v:187815.9-187815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[4:0]$12586 5'11111 + case + assign $1\src_l_r_src$next[4:0]$12586 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12585 + end + attribute \src "libresoc.v:187823.3-187831.6" + process $proc$libresoc.v:187823$12587 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$12588 $1\req_l_s_req$next[2:0]$12589 + attribute \src "libresoc.v:187824.5-187824.29" + switch \initial + attribute \src "libresoc.v:187824.9-187824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$12589 3'000 + case + assign $1\req_l_s_req$next[2:0]$12589 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12588 + end + attribute \src "libresoc.v:187832.3-187840.6" + process $proc$libresoc.v:187832$12590 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$12591 $1\req_l_r_req$next[2:0]$12592 + attribute \src "libresoc.v:187833.5-187833.29" + switch \initial + attribute \src "libresoc.v:187833.9-187833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$12592 3'111 + case + assign $1\req_l_r_req$next[2:0]$12592 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12591 + end + attribute \src "libresoc.v:187841.3-187878.6" + process $proc$libresoc.v:187841$12593 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 + attribute \src "libresoc.v:187842.5-187842.29" + switch \initial + attribute \src "libresoc.v:187842.9-187842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + case + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 \alu_shift_rot0_sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 1'0 + case + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 + end + sync always + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 + end + attribute \src "libresoc.v:187879.3-187900.6" + process $proc$libresoc.v:187879$12634 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12635 $2\data_r0__o$next[63:0]$12639 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12636 $3\data_r0__o_ok$next[0:0]$12641 + attribute \src "libresoc.v:187880.5-187880.29" + switch \initial + attribute \src "libresoc.v:187880.9-187880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12638 $1\data_r0__o$next[63:0]$12637 } { \o_ok \alu_shift_rot0_o } + case + assign $1\data_r0__o$next[63:0]$12637 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12638 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12640 $2\data_r0__o$next[63:0]$12639 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12639 $1\data_r0__o$next[63:0]$12637 + assign $2\data_r0__o_ok$next[0:0]$12640 $1\data_r0__o_ok$next[0:0]$12638 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12641 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12641 $2\data_r0__o_ok$next[0:0]$12640 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12635 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12636 + end + attribute \src "libresoc.v:187901.3-187922.6" + process $proc$libresoc.v:187901$12642 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$12643 $2\data_r1__cr_a$next[3:0]$12647 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$12644 $3\data_r1__cr_a_ok$next[0:0]$12649 + attribute \src "libresoc.v:187902.5-187902.29" + switch \initial + attribute \src "libresoc.v:187902.9-187902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$12646 $1\data_r1__cr_a$next[3:0]$12645 } { \cr_a_ok \alu_shift_rot0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$12645 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12646 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$12648 $2\data_r1__cr_a$next[3:0]$12647 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$12647 $1\data_r1__cr_a$next[3:0]$12645 + assign $2\data_r1__cr_a_ok$next[0:0]$12648 $1\data_r1__cr_a_ok$next[0:0]$12646 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$12649 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$12649 $2\data_r1__cr_a_ok$next[0:0]$12648 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12643 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12644 + end + attribute \src "libresoc.v:187923.3-187944.6" + process $proc$libresoc.v:187923$12650 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$12651 $2\data_r2__xer_ca$next[1:0]$12655 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$12652 $3\data_r2__xer_ca_ok$next[0:0]$12657 + attribute \src "libresoc.v:187924.5-187924.29" + switch \initial + attribute \src "libresoc.v:187924.9-187924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12654 $1\data_r2__xer_ca$next[1:0]$12653 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$12653 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12654 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$12656 $2\data_r2__xer_ca$next[1:0]$12655 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$12655 $1\data_r2__xer_ca$next[1:0]$12653 + assign $2\data_r2__xer_ca_ok$next[0:0]$12656 $1\data_r2__xer_ca_ok$next[0:0]$12654 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$12657 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$12657 $2\data_r2__xer_ca_ok$next[0:0]$12656 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12651 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12652 + end + attribute \src "libresoc.v:187945.3-187954.6" + process $proc$libresoc.v:187945$12658 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12659 $1\src_r0$next[63:0]$12660 + attribute \src "libresoc.v:187946.5-187946.29" + switch \initial + attribute \src "libresoc.v:187946.9-187946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12660 \src1_i + case + assign $1\src_r0$next[63:0]$12660 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12659 + end + attribute \src "libresoc.v:187955.3-187964.6" + process $proc$libresoc.v:187955$12661 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12662 $1\src_r1$next[63:0]$12663 + attribute \src "libresoc.v:187956.5-187956.29" + switch \initial + attribute \src "libresoc.v:187956.9-187956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12663 \src_or_imm + case + assign $1\src_r1$next[63:0]$12663 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12662 + end + attribute \src "libresoc.v:187965.3-187974.6" + process $proc$libresoc.v:187965$12664 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12665 $1\src_r2$next[63:0]$12666 + attribute \src "libresoc.v:187966.5-187966.29" + switch \initial + attribute \src "libresoc.v:187966.9-187966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12666 \src3_i + case + assign $1\src_r2$next[63:0]$12666 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12665 + end + attribute \src "libresoc.v:187975.3-187984.6" + process $proc$libresoc.v:187975$12667 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12668 $1\src_r3$next[0:0]$12669 + attribute \src "libresoc.v:187976.5-187976.29" + switch \initial + attribute \src "libresoc.v:187976.9-187976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12669 \src4_i + case + assign $1\src_r3$next[0:0]$12669 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12668 + end + attribute \src "libresoc.v:187985.3-187994.6" + process $proc$libresoc.v:187985$12670 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12671 $1\src_r4$next[1:0]$12672 + attribute \src "libresoc.v:187986.5-187986.29" + switch \initial + attribute \src "libresoc.v:187986.9-187986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12672 \src5_i + case + assign $1\src_r4$next[1:0]$12672 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12671 + end + attribute \src "libresoc.v:187995.3-188003.6" + process $proc$libresoc.v:187995$12673 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12674 $1\alui_l_r_alui$next[0:0]$12675 + attribute \src "libresoc.v:187996.5-187996.29" + switch \initial + attribute \src "libresoc.v:187996.9-187996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12675 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12675 \$90 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12674 + end + attribute \src "libresoc.v:188004.3-188012.6" + process $proc$libresoc.v:188004$12676 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12677 $1\alu_l_r_alu$next[0:0]$12678 + attribute \src "libresoc.v:188005.5-188005.29" + switch \initial + attribute \src "libresoc.v:188005.9-188005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12678 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12678 \$92 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12677 + end + attribute \src "libresoc.v:188013.3-188022.6" + process $proc$libresoc.v:188013$12679 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:188014.5-188014.29" + switch \initial + attribute \src "libresoc.v:188014.9-188014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:188023.3-188032.6" + process $proc$libresoc.v:188023$12680 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:188024.5-188024.29" + switch \initial + attribute \src "libresoc.v:188024.9-188024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:188033.3-188042.6" + process $proc$libresoc.v:188033$12681 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:188034.5-188034.29" + switch \initial + attribute \src "libresoc.v:188034.9-188034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:188043.3-188051.6" + process $proc$libresoc.v:188043$12682 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$12683 $1\prev_wr_go$next[2:0]$12684 + attribute \src "libresoc.v:188044.5-188044.29" + switch \initial + attribute \src "libresoc.v:188044.9-188044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$12684 3'000 + case + assign $1\prev_wr_go$next[2:0]$12684 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12683 + end + connect \$100 $not$libresoc.v:187512$12460_Y + connect \$102 $and$libresoc.v:187513$12461_Y + connect \$104 $and$libresoc.v:187514$12462_Y + connect \$106 $and$libresoc.v:187515$12463_Y + connect \$108 $and$libresoc.v:187516$12464_Y + connect \$10 $and$libresoc.v:187517$12465_Y + connect \$110 $and$libresoc.v:187518$12466_Y + connect \$112 $and$libresoc.v:187519$12467_Y + connect \$114 $and$libresoc.v:187520$12468_Y + connect \$116 $and$libresoc.v:187521$12469_Y + connect \$118 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\reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_shift_rot0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "libresoc.v:188088.1-188268.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.spr" +attribute \generator "nMigen" +module \spr + attribute \src "libresoc.v:188240.3-188243.6" + wire width 7 $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 7 $0\_0_[6:0] + attribute \src "libresoc.v:188089.7-188089.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188245.3-188253.6" + wire $0\ren_delay$next[0:0]$12850 + attribute \src "libresoc.v:188121.3-188122.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:188254.3-188263.6" + wire width 64 $0\spr1__data_o[63:0] + attribute \src "libresoc.v:188245.3-188253.6" + wire $1\ren_delay$next[0:0]$12851 + attribute \src "libresoc.v:188105.7-188105.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:188254.3-188263.6" + wire width 64 $1\spr1__data_o[63:0] + attribute \src "libresoc.v:188244.26-188244.32" + wire width 64 $memrd$\memory$libresoc.v:188244$12848_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 7 $memwr$\memory$libresoc.v:188242$12842_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:188242$12842_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:188242$12842_EN + attribute \src "libresoc.v:188239.13-188239.16" + wire width 7 \_0_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 8 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188089.7-188089.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 7 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 7 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 7 input 3 \spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 7 input 6 \spr1__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 5 \spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 2 \spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 7 \spr1__wen + attribute \src "libresoc.v:188123.14-188123.20" + memory width 64 size 113 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12853 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 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parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12857 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12857 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12858 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12858 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12859 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12859 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 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64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12896 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12896 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 43 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12897 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12897 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 44 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12898 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12898 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 45 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12899 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12899 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 46 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12900 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12900 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 47 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12901 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12901 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 48 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12902 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12902 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 49 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12903 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12903 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 50 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12904 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12904 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 51 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12905 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12905 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 52 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12906 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12906 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 53 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12907 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12907 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 54 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12908 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12908 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 55 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12909 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12909 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 56 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12910 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12910 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 57 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12911 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12911 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 58 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12912 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12912 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 59 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12913 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12913 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 60 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12914 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12914 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 61 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12915 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12915 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 62 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12916 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12916 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 63 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12917 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12917 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 64 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12918 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12918 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 65 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12919 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12919 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 66 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12920 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12920 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 67 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12921 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12921 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 68 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12922 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12922 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 69 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12923 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12923 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 70 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12924 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12924 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 71 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12925 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12925 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 72 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12926 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12926 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 73 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12927 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12927 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 74 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12928 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12928 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 75 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12929 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12929 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 76 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12930 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12930 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 77 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12931 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12931 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 78 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12932 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12932 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 79 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12933 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12933 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 80 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12934 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12934 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 81 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12935 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12935 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 82 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12936 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12936 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 83 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12937 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12937 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 84 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12938 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12938 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 85 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12939 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12939 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 86 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12940 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12940 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 87 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12941 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12941 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 88 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12942 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12942 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 89 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12943 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12943 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 90 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12944 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12944 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 91 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12945 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12945 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 92 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12946 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12946 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 93 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12947 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12947 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 94 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12948 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12948 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 95 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12949 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12949 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 96 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12950 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12950 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 97 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12951 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12951 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 98 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12952 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12952 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 99 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12953 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12953 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 100 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12954 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12954 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 101 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12955 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12955 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 102 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12956 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12956 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 103 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12957 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12957 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 104 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12958 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12958 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 105 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12959 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12959 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 106 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12960 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12960 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 107 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12961 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12961 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 108 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12962 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12962 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 109 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12963 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12963 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 110 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12964 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12964 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 111 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12965 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12965 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 112 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:188244.26-188244.32" + cell $memrd $memrd$\memory$libresoc.v:188244$12848 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:188244$12848_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$12966 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 12966 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:188242$12842_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:188242$12842_DATA + connect \EN $memwr$\memory$libresoc.v:188242$12842_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$12969 + sync always + sync init + end + attribute \src "libresoc.v:188089.7-188089.20" + process $proc$libresoc.v:188089$12967 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188105.7-188105.23" + process $proc$libresoc.v:188105$12968 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:188121.3-188122.35" + process $proc$libresoc.v:188121$12843 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:188240.3-188243.6" + process $proc$libresoc.v:188240$12844 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[6:0] \spr1__addr + attribute \src "libresoc.v:188242.5-188242.59" + switch \spr1__wen + attribute \src "libresoc.v:188242.9-188242.18" + case 1'1 + assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[6:0] + update $memwr$\memory$libresoc.v:188242$12842_ADDR $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 + update $memwr$\memory$libresoc.v:188242$12842_DATA $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 + update $memwr$\memory$libresoc.v:188242$12842_EN $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 + end + attribute \src "libresoc.v:188245.3-188253.6" + process $proc$libresoc.v:188245$12849 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$12850 $1\ren_delay$next[0:0]$12851 + attribute \src "libresoc.v:188246.5-188246.29" + switch \initial + attribute \src "libresoc.v:188246.9-188246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$12851 1'0 + case + assign $1\ren_delay$next[0:0]$12851 \spr1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$12850 + end + attribute \src "libresoc.v:188254.3-188263.6" + process $proc$libresoc.v:188254$12852 + assign { } { } + assign { } { } + assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] + attribute \src "libresoc.v:188255.5-188255.29" + switch \initial + attribute \src "libresoc.v:188255.9-188255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\spr1__data_o[63:0] \memory_r_data + case + assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1__data_o $0\spr1__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:188244$12848_DATA + connect \memory_w_data \spr1__data_i + connect \memory_w_en \spr1__wen + connect \memory_w_addr \spr1__addr$1 + connect \memory_r_addr \spr1__addr +end +attribute \src "libresoc.v:188272.1-189525.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" +attribute \generator "nMigen" +module \spr0 + attribute \src "libresoc.v:189022.3-189023.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:189020.3-189021.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:189416.3-189424.6" + wire $0\alu_l_r_alu$next[0:0]$13183 + attribute \src "libresoc.v:188950.3-188951.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 + attribute \src "libresoc.v:188992.3-188993.65" + wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13106 + attribute \src "libresoc.v:188994.3-188995.59" + wire width 32 $0\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 + attribute \src "libresoc.v:188990.3-188991.69" + wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 + attribute \src "libresoc.v:188996.3-188997.67" + wire $0\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:189407.3-189415.6" + wire $0\alui_l_r_alui$next[0:0]$13180 + attribute \src "libresoc.v:188952.3-188953.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $0\data_r0__o$next[63:0]$13114 + attribute \src "libresoc.v:188986.3-188987.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:189215.3-189236.6" + wire $0\data_r0__o_ok$next[0:0]$13115 + attribute \src "libresoc.v:188988.3-188989.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $0\data_r1__spr1$next[63:0]$13122 + attribute \src "libresoc.v:188982.3-188983.43" + wire width 64 $0\data_r1__spr1[63:0] + attribute \src "libresoc.v:189237.3-189258.6" + wire $0\data_r1__spr1_ok$next[0:0]$13123 + attribute \src "libresoc.v:188984.3-188985.49" + wire $0\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $0\data_r2__fast1$next[63:0]$13130 + attribute \src "libresoc.v:188978.3-188979.45" + wire width 64 $0\data_r2__fast1[63:0] + attribute \src "libresoc.v:189259.3-189280.6" + wire $0\data_r2__fast1_ok$next[0:0]$13131 + attribute \src "libresoc.v:188980.3-188981.51" + wire $0\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:189281.3-189302.6" + wire $0\data_r3__xer_so$next[0:0]$13138 + attribute \src "libresoc.v:188974.3-188975.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:189281.3-189302.6" + wire $0\data_r3__xer_so_ok$next[0:0]$13139 + attribute \src "libresoc.v:188976.3-188977.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$13146 + attribute \src "libresoc.v:188970.3-188971.47" + wire width 2 $0\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:189303.3-189324.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$13147 + attribute \src "libresoc.v:188972.3-188973.53" + wire $0\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$13154 + attribute \src "libresoc.v:188966.3-188967.47" + wire width 2 $0\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:189325.3-189346.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$13155 + attribute \src "libresoc.v:188968.3-188969.53" + wire $0\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:189425.3-189434.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:189435.3-189444.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:189445.3-189454.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:189455.3-189464.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:189465.3-189474.6" + wire width 2 $0\dest5_o[1:0] + attribute \src "libresoc.v:189475.3-189484.6" + wire width 2 $0\dest6_o[1:0] + attribute \src "libresoc.v:188273.7-188273.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189157.3-189165.6" + wire $0\opc_l_r_opc$next[0:0]$13090 + attribute \src "libresoc.v:189006.3-189007.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:189148.3-189156.6" + wire $0\opc_l_s_opc$next[0:0]$13087 + attribute \src "libresoc.v:189008.3-189009.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:189485.3-189493.6" + wire width 6 $0\prev_wr_go$next[5:0]$13192 + attribute \src "libresoc.v:189018.3-189019.37" + wire width 6 $0\prev_wr_go[5:0] + attribute \src "libresoc.v:189102.3-189111.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:189193.3-189201.6" + wire width 6 $0\req_l_r_req$next[5:0]$13102 + attribute \src "libresoc.v:188998.3-188999.39" + wire width 6 $0\req_l_r_req[5:0] + attribute \src "libresoc.v:189184.3-189192.6" + wire width 6 $0\req_l_s_req$next[5:0]$13099 + attribute \src "libresoc.v:189000.3-189001.39" + wire width 6 $0\req_l_s_req[5:0] + attribute \src "libresoc.v:189121.3-189129.6" + wire $0\rok_l_r_rdok$next[0:0]$13078 + attribute \src "libresoc.v:189014.3-189015.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:189112.3-189120.6" + wire $0\rok_l_s_rdok$next[0:0]$13075 + attribute \src "libresoc.v:189016.3-189017.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:189139.3-189147.6" + wire $0\rst_l_r_rst$next[0:0]$13084 + attribute \src "libresoc.v:189010.3-189011.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:189130.3-189138.6" + wire $0\rst_l_s_rst$next[0:0]$13081 + attribute \src "libresoc.v:189012.3-189013.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:189175.3-189183.6" + wire width 6 $0\src_l_r_src$next[5:0]$13096 + attribute \src "libresoc.v:189002.3-189003.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:189166.3-189174.6" + wire width 6 $0\src_l_s_src$next[5:0]$13093 + attribute \src "libresoc.v:189004.3-189005.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:189347.3-189356.6" + wire width 64 $0\src_r0$next[63:0]$13162 + attribute \src "libresoc.v:188964.3-188965.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:189357.3-189366.6" + wire width 64 $0\src_r1$next[63:0]$13165 + attribute \src "libresoc.v:188962.3-188963.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:189367.3-189376.6" + wire width 64 $0\src_r2$next[63:0]$13168 + attribute \src "libresoc.v:188960.3-188961.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:189377.3-189386.6" + wire $0\src_r3$next[0:0]$13171 + attribute \src "libresoc.v:188958.3-188959.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:189387.3-189396.6" + wire width 2 $0\src_r4$next[1:0]$13174 + attribute \src "libresoc.v:188956.3-188957.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:189397.3-189406.6" + wire width 2 $0\src_r5$next[1:0]$13177 + attribute \src "libresoc.v:188954.3-188955.29" + wire width 2 $0\src_r5[1:0] + attribute \src "libresoc.v:188409.7-188409.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:188419.7-188419.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:189416.3-189424.6" + wire $1\alu_l_r_alu$next[0:0]$13184 + attribute \src "libresoc.v:188427.7-188427.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 + attribute \src "libresoc.v:188472.14-188472.49" + wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13110 + attribute \src "libresoc.v:188476.14-188476.43" + wire width 32 $1\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 + attribute \src "libresoc.v:188555.13-188555.47" + wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:189202.3-189214.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 + attribute \src "libresoc.v:188559.7-188559.39" + wire $1\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:189407.3-189415.6" + wire $1\alui_l_r_alui$next[0:0]$13181 + attribute \src "libresoc.v:188577.7-188577.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $1\data_r0__o$next[63:0]$13116 + attribute \src "libresoc.v:188609.14-188609.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:189215.3-189236.6" + wire $1\data_r0__o_ok$next[0:0]$13117 + attribute \src "libresoc.v:188613.7-188613.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $1\data_r1__spr1$next[63:0]$13124 + attribute \src "libresoc.v:188617.14-188617.50" + wire width 64 $1\data_r1__spr1[63:0] + attribute \src "libresoc.v:189237.3-189258.6" + wire $1\data_r1__spr1_ok$next[0:0]$13125 + attribute \src "libresoc.v:188621.7-188621.30" + wire $1\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $1\data_r2__fast1$next[63:0]$13132 + attribute \src "libresoc.v:188625.14-188625.51" + wire width 64 $1\data_r2__fast1[63:0] + attribute \src "libresoc.v:189259.3-189280.6" + wire $1\data_r2__fast1_ok$next[0:0]$13133 + attribute \src "libresoc.v:188629.7-188629.31" + wire $1\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:189281.3-189302.6" + wire $1\data_r3__xer_so$next[0:0]$13140 + attribute \src "libresoc.v:188633.7-188633.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:189281.3-189302.6" + wire $1\data_r3__xer_so_ok$next[0:0]$13141 + attribute \src "libresoc.v:188637.7-188637.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$13148 + attribute \src "libresoc.v:188641.13-188641.35" + wire width 2 $1\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:189303.3-189324.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$13149 + attribute \src "libresoc.v:188645.7-188645.32" + wire $1\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$13156 + attribute \src "libresoc.v:188649.13-188649.35" + wire width 2 $1\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:189325.3-189346.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$13157 + attribute \src "libresoc.v:188653.7-188653.32" + wire $1\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:189425.3-189434.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:189435.3-189444.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:189445.3-189454.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:189455.3-189464.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:189465.3-189474.6" + wire width 2 $1\dest5_o[1:0] + attribute \src "libresoc.v:189475.3-189484.6" + wire width 2 $1\dest6_o[1:0] + attribute \src "libresoc.v:189157.3-189165.6" + wire $1\opc_l_r_opc$next[0:0]$13091 + attribute \src "libresoc.v:188681.7-188681.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:189148.3-189156.6" + wire $1\opc_l_s_opc$next[0:0]$13088 + attribute \src "libresoc.v:188685.7-188685.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:189485.3-189493.6" + wire width 6 $1\prev_wr_go$next[5:0]$13193 + attribute \src "libresoc.v:188787.13-188787.31" + wire width 6 $1\prev_wr_go[5:0] + attribute \src "libresoc.v:189102.3-189111.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:189193.3-189201.6" + wire width 6 $1\req_l_r_req$next[5:0]$13103 + attribute \src "libresoc.v:188795.13-188795.32" + wire width 6 $1\req_l_r_req[5:0] + attribute \src "libresoc.v:189184.3-189192.6" + wire width 6 $1\req_l_s_req$next[5:0]$13100 + attribute \src "libresoc.v:188799.13-188799.32" + wire width 6 $1\req_l_s_req[5:0] + attribute \src "libresoc.v:189121.3-189129.6" + wire $1\rok_l_r_rdok$next[0:0]$13079 + attribute \src "libresoc.v:188811.7-188811.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:189112.3-189120.6" + wire $1\rok_l_s_rdok$next[0:0]$13076 + attribute \src "libresoc.v:188815.7-188815.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:189139.3-189147.6" + wire $1\rst_l_r_rst$next[0:0]$13085 + attribute \src "libresoc.v:188819.7-188819.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:189130.3-189138.6" + wire $1\rst_l_s_rst$next[0:0]$13082 + attribute \src "libresoc.v:188823.7-188823.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:189175.3-189183.6" + wire width 6 $1\src_l_r_src$next[5:0]$13097 + attribute \src "libresoc.v:188845.13-188845.32" + wire width 6 $1\src_l_r_src[5:0] + attribute \src "libresoc.v:189166.3-189174.6" + wire width 6 $1\src_l_s_src$next[5:0]$13094 + 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$eq$libresoc.v:188923$13009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$46 + connect \B 1'0 + connect \Y $eq$libresoc.v:188923$13009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:188925$13011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:188925$13011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:188884$12970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:188884$12970_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:188888$12974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:188888$12974_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:188907$12993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:188907$12993_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:188909$12995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:188909$12995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:188912$12998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:188912$12998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:188915$13001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $not$libresoc.v:188915$13001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:188920$13006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_ready_i + connect \Y $not$libresoc.v:188920$13006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:188895$12981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:188895$12981_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:188919$13005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:188919$13005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:188929$13015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:188929$13015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:188930$13016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:188930$13016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:188931$13017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:188931$13017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:188932$13018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:188932$13018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:188936$13022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:188936$13022_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:188901$12987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \Y $reduce_and$libresoc.v:188901$12987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:188914$13000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \Y $reduce_or$libresoc.v:188914$13000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:188917$13003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:188917$13003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:188918$13004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:188918$13004_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:188943$13029 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:188943$13029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:188944$13030 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:188944$13030_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:188945$13031 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:188945$13031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:188946$13032 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:188946$13032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:188947$13033 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:188947$13033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:188948$13034 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:188948$13034_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189024.14-189030.4" + cell \alu_l$73 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189031.12-189060.4" + cell \alu_spr0 \alu_spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_spr0_fast1 + connect \fast1$2 \alu_spr0_fast1$2 + connect \fast1_ok \fast1_ok + connect \n_ready_i \alu_spr0_n_ready_i + connect \n_valid_o \alu_spr0_n_valid_o + connect \o \alu_spr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_spr0_p_ready_o + connect \p_valid_i \alu_spr0_p_valid_i + connect \ra \alu_spr0_ra + connect \spr1 \alu_spr0_spr1 + connect \spr1$1 \alu_spr0_spr1$1 + connect \spr1_ok \spr1_ok + connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit + connect \spr_op__insn \alu_spr0_spr_op__insn + connect \spr_op__insn_type \alu_spr0_spr_op__insn_type + connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit + connect \xer_ca \alu_spr0_xer_ca + connect \xer_ca$5 \alu_spr0_xer_ca$5 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_spr0_xer_ov + connect \xer_ov$4 \alu_spr0_xer_ov$4 + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_spr0_xer_so + connect \xer_so$3 \alu_spr0_xer_so$3 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189061.15-189067.4" + cell \alui_l$72 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189068.14-189074.4" + cell \opc_l$68 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189075.14-189081.4" + cell \req_l$69 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189082.14-189088.4" + cell \rok_l$71 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189089.14-189094.4" + cell \rst_l$70 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189095.14-189101.4" + cell \src_l$67 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:188273.7-188273.20" + process $proc$libresoc.v:188273$13194 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188409.7-188409.24" + process $proc$libresoc.v:188409$13195 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:188419.7-188419.26" + process $proc$libresoc.v:188419$13196 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:188427.7-188427.25" + process $proc$libresoc.v:188427$13197 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:188472.14-188472.49" + process $proc$libresoc.v:188472$13198 + assign { } { } + assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:188476.14-188476.43" + process $proc$libresoc.v:188476$13199 + assign { } { } + assign $1\alu_spr0_spr_op__insn[31:0] 0 + sync always + sync init + update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:188555.13-188555.47" + process $proc$libresoc.v:188555$13200 + assign { } { } + assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:188559.7-188559.39" + process $proc$libresoc.v:188559$13201 + assign { } { } + assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:188577.7-188577.27" + process $proc$libresoc.v:188577$13202 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:188609.14-188609.47" + process $proc$libresoc.v:188609$13203 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:188613.7-188613.27" + process $proc$libresoc.v:188613$13204 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:188617.14-188617.50" + process $proc$libresoc.v:188617$13205 + assign { } { } + assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__spr1 $1\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:188621.7-188621.30" + process $proc$libresoc.v:188621$13206 + assign { } { } + assign $1\data_r1__spr1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:188625.14-188625.51" + process $proc$libresoc.v:188625$13207 + assign { } { } + assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast1 $1\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:188629.7-188629.31" + process $proc$libresoc.v:188629$13208 + assign { } { } + assign $1\data_r2__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:188633.7-188633.29" + process $proc$libresoc.v:188633$13209 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:188637.7-188637.32" + process $proc$libresoc.v:188637$13210 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:188641.13-188641.35" + process $proc$libresoc.v:188641$13211 + assign { } { } + assign $1\data_r4__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:188645.7-188645.32" + process $proc$libresoc.v:188645$13212 + assign { } { } + assign $1\data_r4__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:188649.13-188649.35" + process $proc$libresoc.v:188649$13213 + assign { } { } + assign $1\data_r5__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:188653.7-188653.32" + process $proc$libresoc.v:188653$13214 + assign { } { } + assign $1\data_r5__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:188681.7-188681.25" + process $proc$libresoc.v:188681$13215 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:188685.7-188685.25" + process $proc$libresoc.v:188685$13216 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:188787.13-188787.31" + process $proc$libresoc.v:188787$13217 + assign { } { } + assign $1\prev_wr_go[5:0] 6'000000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[5:0] + end + attribute \src "libresoc.v:188795.13-188795.32" + process $proc$libresoc.v:188795$13218 + assign { } { } + assign $1\req_l_r_req[5:0] 6'111111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[5:0] + end + attribute \src "libresoc.v:188799.13-188799.32" + process $proc$libresoc.v:188799$13219 + assign { } { } + assign $1\req_l_s_req[5:0] 6'000000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[5:0] + end + attribute \src "libresoc.v:188811.7-188811.26" + process $proc$libresoc.v:188811$13220 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:188815.7-188815.26" + process $proc$libresoc.v:188815$13221 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:188819.7-188819.25" + process $proc$libresoc.v:188819$13222 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:188823.7-188823.25" + process $proc$libresoc.v:188823$13223 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:188845.13-188845.32" + process $proc$libresoc.v:188845$13224 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:188849.13-188849.32" + process $proc$libresoc.v:188849$13225 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:188853.14-188853.43" + process $proc$libresoc.v:188853$13226 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:188857.14-188857.43" + process $proc$libresoc.v:188857$13227 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:188861.14-188861.43" + process $proc$libresoc.v:188861$13228 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:188865.7-188865.20" + process $proc$libresoc.v:188865$13229 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:188869.13-188869.26" + process $proc$libresoc.v:188869$13230 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:188873.13-188873.26" + process $proc$libresoc.v:188873$13231 + assign { } { } + assign $1\src_r5[1:0] 2'00 + sync always + sync init + update \src_r5 $1\src_r5[1:0] + end + attribute \src "libresoc.v:188950.3-188951.39" + process $proc$libresoc.v:188950$13036 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:188952.3-188953.43" + process $proc$libresoc.v:188952$13037 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:188954.3-188955.29" + process $proc$libresoc.v:188954$13038 + assign { } { } + assign $0\src_r5[1:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[1:0] + end + attribute \src "libresoc.v:188956.3-188957.29" + process $proc$libresoc.v:188956$13039 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:188958.3-188959.29" + process $proc$libresoc.v:188958$13040 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:188960.3-188961.29" + process $proc$libresoc.v:188960$13041 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:188962.3-188963.29" + process $proc$libresoc.v:188962$13042 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:188964.3-188965.29" + process $proc$libresoc.v:188964$13043 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:188966.3-188967.47" + process $proc$libresoc.v:188966$13044 + assign { } { } + assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next + sync posedge \coresync_clk + update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:188968.3-188969.53" + process $proc$libresoc.v:188968$13045 + assign { } { } + assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:188970.3-188971.47" + process $proc$libresoc.v:188970$13046 + assign { } { } + assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next + sync posedge \coresync_clk + update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:188972.3-188973.53" + process $proc$libresoc.v:188972$13047 + assign { } { } + assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:188974.3-188975.47" + process $proc$libresoc.v:188974$13048 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:188976.3-188977.53" + process $proc$libresoc.v:188976$13049 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:188978.3-188979.45" + process $proc$libresoc.v:188978$13050 + assign { } { } + assign $0\data_r2__fast1[63:0] \data_r2__fast1$next + sync posedge \coresync_clk + update \data_r2__fast1 $0\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:188980.3-188981.51" + process $proc$libresoc.v:188980$13051 + assign { } { } + assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next + sync posedge \coresync_clk + update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:188982.3-188983.43" + process $proc$libresoc.v:188982$13052 + assign { } { } + assign $0\data_r1__spr1[63:0] \data_r1__spr1$next + sync posedge \coresync_clk + update \data_r1__spr1 $0\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:188984.3-188985.49" + process $proc$libresoc.v:188984$13053 + assign { } { } + assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next + sync posedge \coresync_clk + update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:188986.3-188987.37" + process $proc$libresoc.v:188986$13054 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:188988.3-188989.43" + process $proc$libresoc.v:188988$13055 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:188990.3-188991.69" + process $proc$libresoc.v:188990$13056 + assign { } { } + assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:188992.3-188993.65" + process $proc$libresoc.v:188992$13057 + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] + end + attribute \src "libresoc.v:188994.3-188995.59" + process $proc$libresoc.v:188994$13058 + assign { } { } + assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:188996.3-188997.67" + process $proc$libresoc.v:188996$13059 + assign { } { } + assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:188998.3-188999.39" + process $proc$libresoc.v:188998$13060 + assign { } { } + assign $0\req_l_r_req[5:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[5:0] + end + attribute \src "libresoc.v:189000.3-189001.39" + process $proc$libresoc.v:189000$13061 + assign { } { } + assign $0\req_l_s_req[5:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[5:0] + end + attribute \src "libresoc.v:189002.3-189003.39" + process $proc$libresoc.v:189002$13062 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:189004.3-189005.39" + process $proc$libresoc.v:189004$13063 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:189006.3-189007.39" + process $proc$libresoc.v:189006$13064 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:189008.3-189009.39" + process $proc$libresoc.v:189008$13065 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:189010.3-189011.39" + process $proc$libresoc.v:189010$13066 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:189012.3-189013.39" + process $proc$libresoc.v:189012$13067 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:189014.3-189015.41" + process $proc$libresoc.v:189014$13068 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:189016.3-189017.41" + process $proc$libresoc.v:189016$13069 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:189018.3-189019.37" + process $proc$libresoc.v:189018$13070 + assign { } { } + assign $0\prev_wr_go[5:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[5:0] + end + attribute \src "libresoc.v:189020.3-189021.40" + process $proc$libresoc.v:189020$13071 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:189022.3-189023.25" + process $proc$libresoc.v:189022$13072 + assign { } { } + assign $0\all_rd_dly[0:0] \$14 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:189102.3-189111.6" + process $proc$libresoc.v:189102$13073 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:189103.5-189103.29" + switch \initial + attribute \src "libresoc.v:189103.9-189103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$50 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:189112.3-189120.6" + process $proc$libresoc.v:189112$13074 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$13075 $1\rok_l_s_rdok$next[0:0]$13076 + attribute \src "libresoc.v:189113.5-189113.29" + switch \initial + attribute \src "libresoc.v:189113.9-189113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$13076 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$13076 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13075 + end + attribute \src "libresoc.v:189121.3-189129.6" + process $proc$libresoc.v:189121$13077 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$13078 $1\rok_l_r_rdok$next[0:0]$13079 + attribute \src "libresoc.v:189122.5-189122.29" + switch \initial + attribute \src "libresoc.v:189122.9-189122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$13079 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$13079 \$68 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13078 + end + attribute \src "libresoc.v:189130.3-189138.6" + process $proc$libresoc.v:189130$13080 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$13081 $1\rst_l_s_rst$next[0:0]$13082 + attribute \src "libresoc.v:189131.5-189131.29" + switch \initial + attribute \src "libresoc.v:189131.9-189131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$13082 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$13082 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13081 + end + attribute \src "libresoc.v:189139.3-189147.6" + process $proc$libresoc.v:189139$13083 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$13084 $1\rst_l_r_rst$next[0:0]$13085 + attribute \src "libresoc.v:189140.5-189140.29" + switch \initial + attribute \src "libresoc.v:189140.9-189140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$13085 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$13085 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13084 + end + attribute \src "libresoc.v:189148.3-189156.6" + process $proc$libresoc.v:189148$13086 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$13087 $1\opc_l_s_opc$next[0:0]$13088 + attribute \src "libresoc.v:189149.5-189149.29" + switch \initial + attribute \src "libresoc.v:189149.9-189149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$13088 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$13088 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13087 + end + attribute \src "libresoc.v:189157.3-189165.6" + process $proc$libresoc.v:189157$13089 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$13090 $1\opc_l_r_opc$next[0:0]$13091 + attribute \src "libresoc.v:189158.5-189158.29" + switch \initial + attribute \src "libresoc.v:189158.9-189158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$13091 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$13091 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13090 + end + attribute \src "libresoc.v:189166.3-189174.6" + process $proc$libresoc.v:189166$13092 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$13093 $1\src_l_s_src$next[5:0]$13094 + attribute \src "libresoc.v:189167.5-189167.29" + switch \initial + attribute \src "libresoc.v:189167.9-189167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$13094 6'000000 + case + assign $1\src_l_s_src$next[5:0]$13094 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13093 + end + attribute \src "libresoc.v:189175.3-189183.6" + process $proc$libresoc.v:189175$13095 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$13096 $1\src_l_r_src$next[5:0]$13097 + attribute \src "libresoc.v:189176.5-189176.29" + switch \initial + attribute \src "libresoc.v:189176.9-189176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$13097 6'111111 + case + assign $1\src_l_r_src$next[5:0]$13097 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13096 + end + attribute \src "libresoc.v:189184.3-189192.6" + process $proc$libresoc.v:189184$13098 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[5:0]$13099 $1\req_l_s_req$next[5:0]$13100 + attribute \src "libresoc.v:189185.5-189185.29" + switch \initial + attribute \src "libresoc.v:189185.9-189185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[5:0]$13100 6'000000 + case + assign $1\req_l_s_req$next[5:0]$13100 \$70 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13099 + end + attribute \src "libresoc.v:189193.3-189201.6" + process $proc$libresoc.v:189193$13101 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[5:0]$13102 $1\req_l_r_req$next[5:0]$13103 + attribute \src "libresoc.v:189194.5-189194.29" + switch \initial + attribute \src "libresoc.v:189194.9-189194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[5:0]$13103 6'111111 + case + assign $1\req_l_r_req$next[5:0]$13103 \$72 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13102 + end + attribute \src "libresoc.v:189202.3-189214.6" + process $proc$libresoc.v:189202$13104 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 + assign $0\alu_spr0_spr_op__insn$next[31:0]$13106 $1\alu_spr0_spr_op__insn$next[31:0]$13110 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 + attribute \src "libresoc.v:189203.5-189203.29" + switch \initial + attribute \src "libresoc.v:189203.9-189203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 $1\alu_spr0_spr_op__insn$next[31:0]$13110 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + case + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$13110 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 \alu_spr0_spr_op__is_32bit + end + sync always + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13106 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 + end + attribute \src "libresoc.v:189215.3-189236.6" + process $proc$libresoc.v:189215$13113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$13114 $2\data_r0__o$next[63:0]$13118 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$13115 $3\data_r0__o_ok$next[0:0]$13120 + attribute \src "libresoc.v:189216.5-189216.29" + switch \initial + attribute \src "libresoc.v:189216.9-189216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$13117 $1\data_r0__o$next[63:0]$13116 } { \o_ok \alu_spr0_o } + case + assign $1\data_r0__o$next[63:0]$13116 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13117 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$13119 $2\data_r0__o$next[63:0]$13118 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$13118 $1\data_r0__o$next[63:0]$13116 + assign $2\data_r0__o_ok$next[0:0]$13119 $1\data_r0__o_ok$next[0:0]$13117 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$13120 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$13120 $2\data_r0__o_ok$next[0:0]$13119 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$13114 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13115 + end + attribute \src "libresoc.v:189237.3-189258.6" + process $proc$libresoc.v:189237$13121 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__spr1$next[63:0]$13122 $2\data_r1__spr1$next[63:0]$13126 + assign { } { } + assign $0\data_r1__spr1_ok$next[0:0]$13123 $3\data_r1__spr1_ok$next[0:0]$13128 + attribute \src "libresoc.v:189238.5-189238.29" + switch \initial + attribute \src "libresoc.v:189238.9-189238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__spr1_ok$next[0:0]$13125 $1\data_r1__spr1$next[63:0]$13124 } { \spr1_ok \alu_spr0_spr1 } + case + assign $1\data_r1__spr1$next[63:0]$13124 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$13125 \data_r1__spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__spr1_ok$next[0:0]$13127 $2\data_r1__spr1$next[63:0]$13126 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__spr1$next[63:0]$13126 $1\data_r1__spr1$next[63:0]$13124 + assign $2\data_r1__spr1_ok$next[0:0]$13127 $1\data_r1__spr1_ok$next[0:0]$13125 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__spr1_ok$next[0:0]$13128 1'0 + case + assign $3\data_r1__spr1_ok$next[0:0]$13128 $2\data_r1__spr1_ok$next[0:0]$13127 + end + sync always + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13122 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13123 + end + attribute \src "libresoc.v:189259.3-189280.6" + process $proc$libresoc.v:189259$13129 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast1$next[63:0]$13130 $2\data_r2__fast1$next[63:0]$13134 + assign { } { } + assign $0\data_r2__fast1_ok$next[0:0]$13131 $3\data_r2__fast1_ok$next[0:0]$13136 + attribute \src "libresoc.v:189260.5-189260.29" + switch \initial + attribute \src "libresoc.v:189260.9-189260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast1_ok$next[0:0]$13133 $1\data_r2__fast1$next[63:0]$13132 } { \fast1_ok \alu_spr0_fast1 } + case + assign $1\data_r2__fast1$next[63:0]$13132 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$13133 \data_r2__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast1_ok$next[0:0]$13135 $2\data_r2__fast1$next[63:0]$13134 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast1$next[63:0]$13134 $1\data_r2__fast1$next[63:0]$13132 + assign $2\data_r2__fast1_ok$next[0:0]$13135 $1\data_r2__fast1_ok$next[0:0]$13133 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast1_ok$next[0:0]$13136 1'0 + case + assign $3\data_r2__fast1_ok$next[0:0]$13136 $2\data_r2__fast1_ok$next[0:0]$13135 + end + sync always + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13130 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13131 + end + attribute \src "libresoc.v:189281.3-189302.6" + process $proc$libresoc.v:189281$13137 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$13138 $2\data_r3__xer_so$next[0:0]$13142 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$13139 $3\data_r3__xer_so_ok$next[0:0]$13144 + attribute \src "libresoc.v:189282.5-189282.29" + switch \initial + attribute \src "libresoc.v:189282.9-189282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$13141 $1\data_r3__xer_so$next[0:0]$13140 } { \xer_so_ok \alu_spr0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$13140 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$13141 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$13143 $2\data_r3__xer_so$next[0:0]$13142 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$13142 $1\data_r3__xer_so$next[0:0]$13140 + assign $2\data_r3__xer_so_ok$next[0:0]$13143 $1\data_r3__xer_so_ok$next[0:0]$13141 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$13144 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$13144 $2\data_r3__xer_so_ok$next[0:0]$13143 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13138 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13139 + end + attribute \src "libresoc.v:189303.3-189324.6" + process $proc$libresoc.v:189303$13145 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_ov$next[1:0]$13146 $2\data_r4__xer_ov$next[1:0]$13150 + assign { } { } + assign $0\data_r4__xer_ov_ok$next[0:0]$13147 $3\data_r4__xer_ov_ok$next[0:0]$13152 + attribute \src "libresoc.v:189304.5-189304.29" + switch \initial + attribute \src "libresoc.v:189304.9-189304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_ov_ok$next[0:0]$13149 $1\data_r4__xer_ov$next[1:0]$13148 } { \xer_ov_ok \alu_spr0_xer_ov } + case + assign $1\data_r4__xer_ov$next[1:0]$13148 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$13149 \data_r4__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_ov_ok$next[0:0]$13151 $2\data_r4__xer_ov$next[1:0]$13150 } 3'000 + case + assign $2\data_r4__xer_ov$next[1:0]$13150 $1\data_r4__xer_ov$next[1:0]$13148 + assign $2\data_r4__xer_ov_ok$next[0:0]$13151 $1\data_r4__xer_ov_ok$next[0:0]$13149 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_ov_ok$next[0:0]$13152 1'0 + case + assign $3\data_r4__xer_ov_ok$next[0:0]$13152 $2\data_r4__xer_ov_ok$next[0:0]$13151 + end + sync always + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13146 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13147 + end + attribute \src "libresoc.v:189325.3-189346.6" + process $proc$libresoc.v:189325$13153 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r5__xer_ca$next[1:0]$13154 $2\data_r5__xer_ca$next[1:0]$13158 + assign { } { } + assign $0\data_r5__xer_ca_ok$next[0:0]$13155 $3\data_r5__xer_ca_ok$next[0:0]$13160 + attribute \src "libresoc.v:189326.5-189326.29" + switch \initial + attribute \src "libresoc.v:189326.9-189326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r5__xer_ca_ok$next[0:0]$13157 $1\data_r5__xer_ca$next[1:0]$13156 } { \xer_ca_ok \alu_spr0_xer_ca } + case + assign $1\data_r5__xer_ca$next[1:0]$13156 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$13157 \data_r5__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r5__xer_ca_ok$next[0:0]$13159 $2\data_r5__xer_ca$next[1:0]$13158 } 3'000 + case + assign $2\data_r5__xer_ca$next[1:0]$13158 $1\data_r5__xer_ca$next[1:0]$13156 + assign $2\data_r5__xer_ca_ok$next[0:0]$13159 $1\data_r5__xer_ca_ok$next[0:0]$13157 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r5__xer_ca_ok$next[0:0]$13160 1'0 + case + assign $3\data_r5__xer_ca_ok$next[0:0]$13160 $2\data_r5__xer_ca_ok$next[0:0]$13159 + end + sync always + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13154 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13155 + end + attribute \src "libresoc.v:189347.3-189356.6" + process $proc$libresoc.v:189347$13161 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$13162 $1\src_r0$next[63:0]$13163 + attribute \src "libresoc.v:189348.5-189348.29" + switch \initial + attribute \src "libresoc.v:189348.9-189348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$13163 \src1_i + case + assign $1\src_r0$next[63:0]$13163 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$13162 + end + attribute \src "libresoc.v:189357.3-189366.6" + process $proc$libresoc.v:189357$13164 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$13165 $1\src_r1$next[63:0]$13166 + attribute \src "libresoc.v:189358.5-189358.29" + switch \initial + attribute \src "libresoc.v:189358.9-189358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$13166 \src2_i + case + assign $1\src_r1$next[63:0]$13166 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$13165 + end + attribute \src "libresoc.v:189367.3-189376.6" + process $proc$libresoc.v:189367$13167 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$13168 $1\src_r2$next[63:0]$13169 + attribute \src "libresoc.v:189368.5-189368.29" + switch \initial + attribute \src "libresoc.v:189368.9-189368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$13169 \src3_i + case + assign $1\src_r2$next[63:0]$13169 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$13168 + end + attribute \src "libresoc.v:189377.3-189386.6" + process $proc$libresoc.v:189377$13170 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$13171 $1\src_r3$next[0:0]$13172 + attribute \src "libresoc.v:189378.5-189378.29" + switch \initial + attribute \src "libresoc.v:189378.9-189378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$13172 \src4_i + case + assign $1\src_r3$next[0:0]$13172 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$13171 + end + attribute \src "libresoc.v:189387.3-189396.6" + process $proc$libresoc.v:189387$13173 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$13174 $1\src_r4$next[1:0]$13175 + attribute \src "libresoc.v:189388.5-189388.29" + switch \initial + attribute \src "libresoc.v:189388.9-189388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$13175 \src5_i + case + assign $1\src_r4$next[1:0]$13175 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$13174 + end + attribute \src "libresoc.v:189397.3-189406.6" + process $proc$libresoc.v:189397$13176 + assign { } { } + assign { } { } + assign $0\src_r5$next[1:0]$13177 $1\src_r5$next[1:0]$13178 + attribute \src "libresoc.v:189398.5-189398.29" + switch \initial + attribute \src "libresoc.v:189398.9-189398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[1:0]$13178 \src6_i + case + assign $1\src_r5$next[1:0]$13178 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[1:0]$13177 + end + attribute \src "libresoc.v:189407.3-189415.6" + process $proc$libresoc.v:189407$13179 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$13180 $1\alui_l_r_alui$next[0:0]$13181 + attribute \src "libresoc.v:189408.5-189408.29" + switch \initial + attribute \src "libresoc.v:189408.9-189408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$13181 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$13181 \$98 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13180 + end + attribute \src "libresoc.v:189416.3-189424.6" + process $proc$libresoc.v:189416$13182 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$13183 $1\alu_l_r_alu$next[0:0]$13184 + attribute \src "libresoc.v:189417.5-189417.29" + switch \initial + attribute \src "libresoc.v:189417.9-189417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$13184 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$13184 \$100 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13183 + end + attribute \src "libresoc.v:189425.3-189434.6" + process $proc$libresoc.v:189425$13185 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:189426.5-189426.29" + switch \initial + attribute \src "libresoc.v:189426.9-189426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:189435.3-189444.6" + process $proc$libresoc.v:189435$13186 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:189436.5-189436.29" + switch \initial + attribute \src "libresoc.v:189436.9-189436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__spr1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:189445.3-189454.6" + process $proc$libresoc.v:189445$13187 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:189446.5-189446.29" + switch \initial + attribute \src "libresoc.v:189446.9-189446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$130 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast1 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:189455.3-189464.6" + process $proc$libresoc.v:189455$13188 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:189456.5-189456.29" + switch \initial + attribute \src "libresoc.v:189456.9-189456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$132 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:189465.3-189474.6" + process $proc$libresoc.v:189465$13189 + assign { } { } + assign { } { } + assign $0\dest5_o[1:0] $1\dest5_o[1:0] + attribute \src "libresoc.v:189466.5-189466.29" + switch \initial + attribute \src "libresoc.v:189466.9-189466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$134 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[1:0] \data_r4__xer_ov + case + assign $1\dest5_o[1:0] 2'00 + end + sync always + update \dest5_o $0\dest5_o[1:0] + end + attribute \src "libresoc.v:189475.3-189484.6" + process $proc$libresoc.v:189475$13190 + assign { } { } + assign { } { } + assign $0\dest6_o[1:0] $1\dest6_o[1:0] + attribute \src "libresoc.v:189476.5-189476.29" + switch \initial + attribute \src "libresoc.v:189476.9-189476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$136 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest6_o[1:0] \data_r5__xer_ca + case + assign $1\dest6_o[1:0] 2'00 + end + sync always + update \dest6_o $0\dest6_o[1:0] + end + attribute \src "libresoc.v:189485.3-189493.6" + process $proc$libresoc.v:189485$13191 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[5:0]$13192 $1\prev_wr_go$next[5:0]$13193 + attribute \src "libresoc.v:189486.5-189486.29" + switch \initial + attribute \src "libresoc.v:189486.9-189486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[5:0]$13193 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13193 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13192 + end + connect \$9 $not$libresoc.v:188884$12970_Y + connect \$100 $and$libresoc.v:188885$12971_Y + connect \$102 $and$libresoc.v:188886$12972_Y + connect \$104 $and$libresoc.v:188887$12973_Y + connect \$106 $not$libresoc.v:188888$12974_Y + connect \$108 $and$libresoc.v:188889$12975_Y + connect \$110 $and$libresoc.v:188890$12976_Y + connect \$112 $and$libresoc.v:188891$12977_Y + connect \$114 $and$libresoc.v:188892$12978_Y + connect \$116 $and$libresoc.v:188893$12979_Y + connect \$118 $and$libresoc.v:188894$12980_Y + connect \$11 $or$libresoc.v:188895$12981_Y + connect \$120 $and$libresoc.v:188896$12982_Y + connect \$122 $and$libresoc.v:188897$12983_Y + connect \$124 $and$libresoc.v:188898$12984_Y + connect \$126 $and$libresoc.v:188899$12985_Y + connect \$128 $and$libresoc.v:188900$12986_Y + connect \$8 $reduce_and$libresoc.v:188901$12987_Y + connect \$130 $and$libresoc.v:188902$12988_Y + connect \$132 $and$libresoc.v:188903$12989_Y + connect \$134 $and$libresoc.v:188904$12990_Y + connect \$136 $and$libresoc.v:188905$12991_Y + connect \$14 $and$libresoc.v:188906$12992_Y + connect \$16 $not$libresoc.v:188907$12993_Y + connect \$18 $and$libresoc.v:188908$12994_Y + connect \$20 $not$libresoc.v:188909$12995_Y + connect \$22 $and$libresoc.v:188910$12996_Y + connect \$24 $and$libresoc.v:188911$12997_Y + connect \$28 $not$libresoc.v:188912$12998_Y + connect \$30 $and$libresoc.v:188913$12999_Y + connect \$27 $reduce_or$libresoc.v:188914$13000_Y + connect \$26 $not$libresoc.v:188915$13001_Y + connect \$34 $and$libresoc.v:188916$13002_Y + connect \$36 $reduce_or$libresoc.v:188917$13003_Y + connect \$38 $reduce_or$libresoc.v:188918$13004_Y + connect \$40 $or$libresoc.v:188919$13005_Y + connect \$42 $not$libresoc.v:188920$13006_Y + connect \$44 $and$libresoc.v:188921$13007_Y + connect \$46 $and$libresoc.v:188922$13008_Y + connect \$48 $eq$libresoc.v:188923$13009_Y + connect \$50 $and$libresoc.v:188924$13010_Y + connect \$52 $eq$libresoc.v:188925$13011_Y + connect \$54 $and$libresoc.v:188926$13012_Y + connect \$56 $and$libresoc.v:188927$13013_Y + connect \$58 $and$libresoc.v:188928$13014_Y + connect \$60 $or$libresoc.v:188929$13015_Y + connect \$62 $or$libresoc.v:188930$13016_Y + connect \$64 $or$libresoc.v:188931$13017_Y + connect \$66 $or$libresoc.v:188932$13018_Y + connect \$68 $and$libresoc.v:188933$13019_Y + connect \$6 $and$libresoc.v:188934$13020_Y + connect \$70 $and$libresoc.v:188935$13021_Y + connect \$72 $or$libresoc.v:188936$13022_Y + connect \$74 $and$libresoc.v:188937$13023_Y + connect \$76 $and$libresoc.v:188938$13024_Y + connect \$78 $and$libresoc.v:188939$13025_Y + connect \$80 $and$libresoc.v:188940$13026_Y + connect \$82 $and$libresoc.v:188941$13027_Y + connect \$84 $and$libresoc.v:188942$13028_Y + connect \$86 $ternary$libresoc.v:188943$13029_Y + connect \$88 $ternary$libresoc.v:188944$13030_Y + connect \$90 $ternary$libresoc.v:188945$13031_Y + connect \$92 $ternary$libresoc.v:188946$13032_Y + connect \$94 $ternary$libresoc.v:188947$13033_Y + connect \$96 $ternary$libresoc.v:188948$13034_Y + connect \$98 $and$libresoc.v:188949$13035_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$124 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_spr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_spr0_p_valid_i \alui_l_q_alui + connect \alu_spr0_xer_ca$5 \$96 + connect \alu_spr0_xer_ov$4 \$94 + connect \alu_spr0_xer_so$3 \$92 + connect \alu_spr0_fast1$2 \$90 + connect \alu_spr0_spr1$1 \$88 + connect \alu_spr0_ra \$86 + connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } + connect \reset_r \$66 + connect \reset_w \$64 + connect \rst_r \$62 + connect \reset \$60 + connect \wr_any \$40 + connect \cu_done_o \$34 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$22 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_spr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$18 + connect \all_rd_dly$next \all_rd + connect \all_rd \$14 +end +attribute \src "libresoc.v:189529.1-190049.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" +attribute \generator "nMigen" +module \spr_main + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $0\fast1$7[63:0]$13240 + attribute \src "libresoc.v:189879.3-189894.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:189530.7-189530.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189837.3-189878.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:189837.3-189878.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $0\spr1$6[63:0]$13265 + attribute \src "libresoc.v:189818.3-189836.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $0\xer_ca$10[1:0]$13259 + attribute \src "libresoc.v:190006.3-190026.6" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $0\xer_ov$9[1:0]$13253 + attribute \src "libresoc.v:189961.3-189981.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:189895.3-189915.6" + wire $0\xer_so$8[0:0]$13247 + attribute \src "libresoc.v:189916.3-189936.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $1\fast1$7[63:0]$13241 + attribute \src "libresoc.v:189879.3-189894.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:189837.3-189878.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:189837.3-189878.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $1\spr1$6[63:0]$13266 + attribute \src "libresoc.v:189818.3-189836.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $1\xer_ca$10[1:0]$13260 + attribute \src "libresoc.v:190006.3-190026.6" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $1\xer_ov$9[1:0]$13254 + attribute \src "libresoc.v:189961.3-189981.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:189895.3-189915.6" + wire $1\xer_so$8[0:0]$13248 + attribute \src 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attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $3\xer_ca$10[1:0]$13262 + attribute \src "libresoc.v:190006.3-190026.6" + wire $3\xer_ca_ok[0:0] + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $3\xer_ov$9[1:0]$13256 + attribute \src "libresoc.v:189961.3-189981.6" + wire $3\xer_ov_ok[0:0] + attribute \src "libresoc.v:189895.3-189915.6" + wire $3\xer_so$8[0:0]$13250 + attribute \src "libresoc.v:189916.3-189936.6" + wire $3\xer_so_ok[0:0] + attribute \src "libresoc.v:189795.18-189795.106" + wire $eq$libresoc.v:189795$13232_Y + attribute \src "libresoc.v:189796.18-189796.106" + wire $eq$libresoc.v:189796$13233_Y + attribute \src "libresoc.v:189797.18-189797.106" + wire $eq$libresoc.v:189797$13234_Y + attribute \src "libresoc.v:189798.18-189798.106" + wire $eq$libresoc.v:189798$13235_Y + attribute \src "libresoc.v:189799.18-189799.106" + wire $eq$libresoc.v:189799$13236_Y + attribute \src "libresoc.v:189800.18-189800.106" + wire $eq$libresoc.v:189800$13237_Y + attribute \src "libresoc.v:189801.18-189801.106" + wire $eq$libresoc.v:189801$13238_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 7 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \fast1_ok + attribute \src "libresoc.v:189530.7-189530.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 11 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 6 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 13 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 14 \spr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 12 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 10 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 24 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 8 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:189795$13232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189795$13232_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:189796$13233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189796$13233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:189797$13234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189797$13234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:189798$13235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189798$13235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:189799$13236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189799$13236_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:189800$13237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189800$13237_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + cell $eq $eq$libresoc.v:189801$13238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:189801$13238_Y + end + attribute \src "libresoc.v:189530.7-189530.20" + process $proc$libresoc.v:189530$13268 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189802.3-189817.6" + process $proc$libresoc.v:189802$13239 + assign { } { } + assign { } { } + assign $0\fast1$7[63:0]$13240 $1\fast1$7[63:0]$13241 + attribute \src "libresoc.v:189803.5-189803.29" + switch \initial + attribute \src "libresoc.v:189803.9-189803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1$7[63:0]$13241 $2\fast1$7[63:0]$13242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1$7[63:0]$13242 \ra + case + assign $2\fast1$7[63:0]$13242 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\fast1$7[63:0]$13241 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$7 $0\fast1$7[63:0]$13240 + end + attribute \src "libresoc.v:189818.3-189836.6" + process $proc$libresoc.v:189818$13243 + assign { } { } + assign { } { } + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + attribute \src "libresoc.v:189819.5-189819.29" + switch \initial + attribute \src "libresoc.v:189819.9-189819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1_ok[0:0] 1'1 + end + case + assign $1\spr1_ok[0:0] 1'0 + end + sync always + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:189837.3-189878.6" + process $proc$libresoc.v:189837$13244 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:189838.5-189838.29" + switch \initial + attribute \src "libresoc.v:189838.9-189838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign $1\o_ok[0:0] 1'1 + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 + assign { } { } + assign $2\o[63:0] [17:0] \fast1 [17:0] + assign $2\o[63:0] [63:18] $3\o[63:18] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:18] [45:14] 0 + assign $3\o[63:18] [10:2] 9'000000000 + assign $3\o[63:18] [13] \xer_so + assign $3\o[63:18] [12] \xer_ov [0] + assign $3\o[63:18] [1] \xer_ov [1] + assign $3\o[63:18] [11] \xer_ca [0] + assign $3\o[63:18] [0] \xer_ca [1] + case + assign $3\o[63:18] \fast1 [63:18] + end + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $2\o[63:0] [63:32] 0 + assign $2\o[63:0] [31:0] \fast1 [63:32] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] \spr1 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:189879.3-189894.6" + process $proc$libresoc.v:189879$13245 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:189880.5-189880.29" + switch \initial + attribute \src "libresoc.v:189880.9-189880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:189895.3-189915.6" + process $proc$libresoc.v:189895$13246 + assign { } { } + assign { } { } + assign $0\xer_so$8[0:0]$13247 $1\xer_so$8[0:0]$13248 + attribute \src "libresoc.v:189896.5-189896.29" + switch \initial + attribute \src "libresoc.v:189896.9-189896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so$8[0:0]$13248 $2\xer_so$8[0:0]$13249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so$8[0:0]$13249 $3\xer_so$8[0:0]$13250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so$8[0:0]$13250 \ra [31] + case + assign $3\xer_so$8[0:0]$13250 1'0 + end + case + assign $2\xer_so$8[0:0]$13249 1'0 + end + case + assign $1\xer_so$8[0:0]$13248 1'0 + end + sync always + update \xer_so$8 $0\xer_so$8[0:0]$13247 + end + attribute \src "libresoc.v:189916.3-189936.6" + process $proc$libresoc.v:189916$13251 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:189917.5-189917.29" + switch \initial + attribute \src "libresoc.v:189917.9-189917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so_ok[0:0] 1'1 + case + assign $3\xer_so_ok[0:0] 1'0 + end + case + assign $2\xer_so_ok[0:0] 1'0 + end + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:189937.3-189960.6" + process $proc$libresoc.v:189937$13252 + assign { } { } + assign { } { } + assign $0\xer_ov$9[1:0]$13253 $1\xer_ov$9[1:0]$13254 + attribute \src "libresoc.v:189938.5-189938.29" + switch \initial + attribute \src "libresoc.v:189938.9-189938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov$9[1:0]$13254 $2\xer_ov$9[1:0]$13255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov$9[1:0]$13255 $3\xer_ov$9[1:0]$13256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov$9[1:0]$13256 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13256 [1] \ra [19] + case + assign $3\xer_ov$9[1:0]$13256 2'00 + end + case + assign $2\xer_ov$9[1:0]$13255 2'00 + end + case + assign $1\xer_ov$9[1:0]$13254 2'00 + end + sync always + update \xer_ov$9 $0\xer_ov$9[1:0]$13253 + end + attribute \src "libresoc.v:189961.3-189981.6" + process $proc$libresoc.v:189961$13257 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:189962.5-189962.29" + switch \initial + attribute \src "libresoc.v:189962.9-189962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov_ok[0:0] 1'1 + case + assign $3\xer_ov_ok[0:0] 1'0 + end + case + assign $2\xer_ov_ok[0:0] 1'0 + end + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:189982.3-190005.6" + process $proc$libresoc.v:189982$13258 + assign { } { } + assign { } { } + assign $0\xer_ca$10[1:0]$13259 $1\xer_ca$10[1:0]$13260 + attribute \src "libresoc.v:189983.5-189983.29" + switch \initial + attribute \src "libresoc.v:189983.9-189983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca$10[1:0]$13260 $2\xer_ca$10[1:0]$13261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca$10[1:0]$13261 $3\xer_ca$10[1:0]$13262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca$10[1:0]$13262 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13262 [1] \ra [18] + case + assign $3\xer_ca$10[1:0]$13262 2'00 + end + case + assign $2\xer_ca$10[1:0]$13261 2'00 + end + case + assign $1\xer_ca$10[1:0]$13260 2'00 + end + sync always + update \xer_ca$10 $0\xer_ca$10[1:0]$13259 + end + attribute \src "libresoc.v:190006.3-190026.6" + process $proc$libresoc.v:190006$13263 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:190007.5-190007.29" + switch \initial + attribute \src "libresoc.v:190007.9-190007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca_ok[0:0] 1'1 + case + assign $3\xer_ca_ok[0:0] 1'0 + end + case + assign $2\xer_ca_ok[0:0] 1'0 + end + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:190027.3-190045.6" + process $proc$libresoc.v:190027$13264 + assign { } { } + assign { } { } + assign $0\spr1$6[63:0]$13265 $1\spr1$6[63:0]$13266 + attribute \src "libresoc.v:190028.5-190028.29" + switch \initial + attribute \src "libresoc.v:190028.9-190028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1$6[63:0]$13266 $2\spr1$6[63:0]$13267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1$6[63:0]$13267 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1$6[63:0]$13267 \ra + end + case + assign $1\spr1$6[63:0]$13266 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1$6 $0\spr1$6[63:0]$13265 + end + connect \$11 $eq$libresoc.v:189795$13232_Y + connect \$13 $eq$libresoc.v:189796$13233_Y + connect \$15 $eq$libresoc.v:189797$13234_Y + connect \$17 $eq$libresoc.v:189798$13235_Y + connect \$19 $eq$libresoc.v:189799$13236_Y + connect \$21 $eq$libresoc.v:189800$13237_Y + connect \$23 $eq$libresoc.v:189801$13238_Y + connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \muxid$1 \muxid + connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } +end +attribute \src "libresoc.v:190053.1-190889.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:190183.3-190213.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:190214.3-190244.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:190054.7-190054.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:190245.3-190566.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:190567.3-190888.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:190183.3-190213.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:190214.3-190244.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:190245.3-190566.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:190567.3-190888.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:190054.7-190054.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:190054.7-190054.20" + process $proc$libresoc.v:190054$13273 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:190183.3-190213.6" + process $proc$libresoc.v:190183$13269 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:190184.5-190184.29" + switch \initial + attribute \src "libresoc.v:190184.9-190184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:190214.3-190244.6" + process $proc$libresoc.v:190214$13270 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:190215.5-190215.29" + switch \initial + attribute \src "libresoc.v:190215.9-190215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:190245.3-190566.6" + process $proc$libresoc.v:190245$13271 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:190246.5-190246.29" + switch \initial + attribute \src "libresoc.v:190246.9-190246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001110000 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:190567.3-190888.6" + process $proc$libresoc.v:190567$13272 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:190568.5-190568.29" + switch \initial + attribute \src "libresoc.v:190568.9-190568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:190893.1-191729.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$174 + attribute \src "libresoc.v:191023.3-191053.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:191054.3-191084.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:190894.7-190894.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:191085.3-191406.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:191407.3-191728.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:191023.3-191053.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:191054.3-191084.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:191085.3-191406.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:191407.3-191728.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:190894.7-190894.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:190894.7-190894.20" + process $proc$libresoc.v:190894$13278 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:191023.3-191053.6" + process $proc$libresoc.v:191023$13274 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:191024.5-191024.29" + switch \initial + attribute \src "libresoc.v:191024.9-191024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:191054.3-191084.6" + process $proc$libresoc.v:191054$13275 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:191055.5-191055.29" + switch \initial + attribute \src "libresoc.v:191055.9-191055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:191085.3-191406.6" + process $proc$libresoc.v:191085$13276 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:191086.5-191086.29" + switch \initial + attribute \src "libresoc.v:191086.9-191086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001110000 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:191407.3-191728.6" + process $proc$libresoc.v:191407$13277 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:191408.5-191408.29" + switch \initial + attribute \src "libresoc.v:191408.9-191408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:191733.1-191873.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" +attribute \generator "nMigen" +module \sram4k_0 + attribute \src "libresoc.v:191808.3-191822.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:191838.3-191852.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:191734.7-191734.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:191793.3-191807.6" + wire $0\sram4k_0_wb__ack$next[0:0]$13283 + attribute \src "libresoc.v:191774.3-191775.49" + wire $0\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:191823.3-191837.6" + wire width 64 $0\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:191783.3-191792.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:191853.3-191872.6" + wire $0\we[0:0] + attribute \src "libresoc.v:191808.3-191822.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:191838.3-191852.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:191793.3-191807.6" + wire $1\sram4k_0_wb__ack$next[0:0]$13284 + attribute \src "libresoc.v:191751.7-191751.30" + wire $1\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:191823.3-191837.6" + wire width 64 $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:191783.3-191792.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:191853.3-191872.6" + wire $1\we[0:0] + attribute \src "libresoc.v:191808.3-191822.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:191838.3-191852.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:191793.3-191807.6" + wire $2\sram4k_0_wb__ack$next[0:0]$13285 + attribute \src "libresoc.v:191823.3-191837.6" + wire width 64 $2\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:191853.3-191872.6" + wire $2\we[0:0] + attribute \src "libresoc.v:191853.3-191872.6" + wire $3\we[0:0] + attribute \src "libresoc.v:191773.17-191773.129" + wire $and$libresoc.v:191773$13279_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:191734.7-191734.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_0_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:191773$13279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_0_wb__cyc + connect \B \sram4k_0_wb__stb + connect \Y $and$libresoc.v:191773$13279_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191776.21-191782.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:191734.7-191734.20" + process $proc$libresoc.v:191734$13290 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:191751.7-191751.30" + process $proc$libresoc.v:191751$13291 + assign { } { } + assign $1\sram4k_0_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] + end + attribute \src "libresoc.v:191774.3-191775.49" + process $proc$libresoc.v:191774$13280 + assign { } { } + assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next + sync posedge \clk + update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] + end + attribute \src "libresoc.v:191783.3-191792.6" + process $proc$libresoc.v:191783$13281 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:191784.5-191784.29" + switch \initial + attribute \src "libresoc.v:191784.9-191784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:191793.3-191807.6" + process $proc$libresoc.v:191793$13282 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_0_wb__ack$next[0:0]$13283 $2\sram4k_0_wb__ack$next[0:0]$13285 + attribute \src "libresoc.v:191794.5-191794.29" + switch \initial + attribute \src "libresoc.v:191794.9-191794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0_wb__ack$next[0:0]$13284 \wb_active + case + assign $1\sram4k_0_wb__ack$next[0:0]$13284 \sram4k_0_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0_wb__ack$next[0:0]$13285 1'0 + case + assign $2\sram4k_0_wb__ack$next[0:0]$13285 $1\sram4k_0_wb__ack$next[0:0]$13284 + end + sync always + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13283 + end + attribute \src "libresoc.v:191808.3-191822.6" + process $proc$libresoc.v:191808$13286 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:191809.5-191809.29" + switch \initial + attribute \src "libresoc.v:191809.9-191809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_0_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:191823.3-191837.6" + process $proc$libresoc.v:191823$13287 + assign { } { } + assign { } { } + assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:191824.5-191824.29" + switch \initial + attribute \src "libresoc.v:191824.9-191824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0_wb__dat_r[63:0] $2\sram4k_0_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0_wb__dat_r[63:0] \q + case + assign $2\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] + end + attribute \src "libresoc.v:191838.3-191852.6" + process $proc$libresoc.v:191838$13288 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:191839.5-191839.29" + switch \initial + attribute \src "libresoc.v:191839.9-191839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_0_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:191853.3-191872.6" + process $proc$libresoc.v:191853$13289 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:191854.5-191854.29" + switch \initial + attribute \src "libresoc.v:191854.9-191854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_0_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_0_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:191773$13279_Y +end +attribute \src "libresoc.v:191877.1-192017.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" +attribute \generator "nMigen" +module \sram4k_1 + attribute \src "libresoc.v:191952.3-191966.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:191982.3-191996.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:191878.7-191878.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:191937.3-191951.6" + wire $0\sram4k_1_wb__ack$next[0:0]$13296 + attribute \src "libresoc.v:191918.3-191919.49" + wire $0\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:191967.3-191981.6" + wire width 64 $0\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:191927.3-191936.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:191997.3-192016.6" + wire $0\we[0:0] + attribute \src "libresoc.v:191952.3-191966.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:191982.3-191996.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:191937.3-191951.6" + wire $1\sram4k_1_wb__ack$next[0:0]$13297 + attribute \src "libresoc.v:191895.7-191895.30" + wire $1\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:191967.3-191981.6" + wire width 64 $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:191927.3-191936.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:191997.3-192016.6" + wire $1\we[0:0] + attribute \src "libresoc.v:191952.3-191966.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:191982.3-191996.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:191937.3-191951.6" + wire $2\sram4k_1_wb__ack$next[0:0]$13298 + attribute \src "libresoc.v:191967.3-191981.6" + wire width 64 $2\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:191997.3-192016.6" + wire $2\we[0:0] + attribute \src "libresoc.v:191997.3-192016.6" + wire $3\we[0:0] + attribute \src "libresoc.v:191917.17-191917.129" + wire $and$libresoc.v:191917$13292_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:191878.7-191878.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_1_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:191917$13292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_1_wb__cyc + connect \B \sram4k_1_wb__stb + connect \Y $and$libresoc.v:191917$13292_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191920.21-191926.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:191878.7-191878.20" + process $proc$libresoc.v:191878$13303 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:191895.7-191895.30" + process $proc$libresoc.v:191895$13304 + assign { } { } + assign $1\sram4k_1_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] + end + attribute \src "libresoc.v:191918.3-191919.49" + process $proc$libresoc.v:191918$13293 + assign { } { } + assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next + sync posedge \clk + update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] + end + attribute \src "libresoc.v:191927.3-191936.6" + process $proc$libresoc.v:191927$13294 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:191928.5-191928.29" + switch \initial + attribute \src "libresoc.v:191928.9-191928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:191937.3-191951.6" + process $proc$libresoc.v:191937$13295 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_1_wb__ack$next[0:0]$13296 $2\sram4k_1_wb__ack$next[0:0]$13298 + attribute \src "libresoc.v:191938.5-191938.29" + switch \initial + attribute \src "libresoc.v:191938.9-191938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1_wb__ack$next[0:0]$13297 \wb_active + case + assign $1\sram4k_1_wb__ack$next[0:0]$13297 \sram4k_1_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1_wb__ack$next[0:0]$13298 1'0 + case + assign $2\sram4k_1_wb__ack$next[0:0]$13298 $1\sram4k_1_wb__ack$next[0:0]$13297 + end + sync always + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13296 + end + attribute \src "libresoc.v:191952.3-191966.6" + process $proc$libresoc.v:191952$13299 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:191953.5-191953.29" + switch \initial + attribute \src "libresoc.v:191953.9-191953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_1_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:191967.3-191981.6" + process $proc$libresoc.v:191967$13300 + assign { } { } + assign { } { } + assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:191968.5-191968.29" + switch \initial + attribute \src "libresoc.v:191968.9-191968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1_wb__dat_r[63:0] $2\sram4k_1_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1_wb__dat_r[63:0] \q + case + assign $2\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] + end + attribute \src "libresoc.v:191982.3-191996.6" + process $proc$libresoc.v:191982$13301 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:191983.5-191983.29" + switch \initial + attribute \src "libresoc.v:191983.9-191983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_1_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:191997.3-192016.6" + process $proc$libresoc.v:191997$13302 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:191998.5-191998.29" + switch \initial + attribute \src "libresoc.v:191998.9-191998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_1_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_1_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:191917$13292_Y +end +attribute \src "libresoc.v:192021.1-192161.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" +attribute \generator "nMigen" +module \sram4k_2 + attribute \src "libresoc.v:192096.3-192110.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:192126.3-192140.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:192022.7-192022.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192081.3-192095.6" + wire $0\sram4k_2_wb__ack$next[0:0]$13309 + attribute \src "libresoc.v:192062.3-192063.49" + wire $0\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:192111.3-192125.6" + wire width 64 $0\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:192071.3-192080.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:192141.3-192160.6" + wire $0\we[0:0] + attribute \src "libresoc.v:192096.3-192110.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:192126.3-192140.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:192081.3-192095.6" + wire $1\sram4k_2_wb__ack$next[0:0]$13310 + attribute \src "libresoc.v:192039.7-192039.30" + wire $1\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:192111.3-192125.6" + wire width 64 $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:192071.3-192080.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:192141.3-192160.6" + wire $1\we[0:0] + attribute \src "libresoc.v:192096.3-192110.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:192126.3-192140.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:192081.3-192095.6" + wire $2\sram4k_2_wb__ack$next[0:0]$13311 + attribute \src "libresoc.v:192111.3-192125.6" + wire width 64 $2\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:192141.3-192160.6" + wire $2\we[0:0] + attribute \src "libresoc.v:192141.3-192160.6" + wire $3\we[0:0] + attribute \src "libresoc.v:192061.17-192061.129" + wire $and$libresoc.v:192061$13305_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:192022.7-192022.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_2_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:192061$13305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_2_wb__cyc + connect \B \sram4k_2_wb__stb + connect \Y $and$libresoc.v:192061$13305_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192064.21-192070.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:192022.7-192022.20" + process $proc$libresoc.v:192022$13316 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192039.7-192039.30" + process $proc$libresoc.v:192039$13317 + assign { } { } + assign $1\sram4k_2_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] + end + attribute \src "libresoc.v:192062.3-192063.49" + process $proc$libresoc.v:192062$13306 + assign { } { } + assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next + sync posedge \clk + update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] + end + attribute \src "libresoc.v:192071.3-192080.6" + process $proc$libresoc.v:192071$13307 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:192072.5-192072.29" + switch \initial + attribute \src "libresoc.v:192072.9-192072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:192081.3-192095.6" + process $proc$libresoc.v:192081$13308 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_2_wb__ack$next[0:0]$13309 $2\sram4k_2_wb__ack$next[0:0]$13311 + attribute \src "libresoc.v:192082.5-192082.29" + switch \initial + attribute \src "libresoc.v:192082.9-192082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2_wb__ack$next[0:0]$13310 \wb_active + case + assign $1\sram4k_2_wb__ack$next[0:0]$13310 \sram4k_2_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2_wb__ack$next[0:0]$13311 1'0 + case + assign $2\sram4k_2_wb__ack$next[0:0]$13311 $1\sram4k_2_wb__ack$next[0:0]$13310 + end + sync always + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13309 + end + attribute \src "libresoc.v:192096.3-192110.6" + process $proc$libresoc.v:192096$13312 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:192097.5-192097.29" + switch \initial + attribute \src "libresoc.v:192097.9-192097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_2_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:192111.3-192125.6" + process $proc$libresoc.v:192111$13313 + assign { } { } + assign { } { } + assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:192112.5-192112.29" + switch \initial + attribute \src "libresoc.v:192112.9-192112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2_wb__dat_r[63:0] $2\sram4k_2_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2_wb__dat_r[63:0] \q + case + assign $2\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] + end + attribute \src "libresoc.v:192126.3-192140.6" + process $proc$libresoc.v:192126$13314 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:192127.5-192127.29" + switch \initial + attribute \src "libresoc.v:192127.9-192127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_2_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:192141.3-192160.6" + process $proc$libresoc.v:192141$13315 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:192142.5-192142.29" + switch \initial + attribute \src "libresoc.v:192142.9-192142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_2_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_2_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:192061$13305_Y +end +attribute \src "libresoc.v:192165.1-192305.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" +attribute \generator "nMigen" +module \sram4k_3 + attribute \src "libresoc.v:192240.3-192254.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:192270.3-192284.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:192166.7-192166.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192225.3-192239.6" + wire $0\sram4k_3_wb__ack$next[0:0]$13322 + attribute \src "libresoc.v:192206.3-192207.49" + wire $0\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:192255.3-192269.6" + wire width 64 $0\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:192215.3-192224.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:192285.3-192304.6" + wire $0\we[0:0] + attribute \src "libresoc.v:192240.3-192254.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:192270.3-192284.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:192225.3-192239.6" + wire $1\sram4k_3_wb__ack$next[0:0]$13323 + attribute \src "libresoc.v:192183.7-192183.30" + wire $1\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:192255.3-192269.6" + wire width 64 $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:192215.3-192224.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:192285.3-192304.6" + wire $1\we[0:0] + attribute \src "libresoc.v:192240.3-192254.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:192270.3-192284.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:192225.3-192239.6" + wire $2\sram4k_3_wb__ack$next[0:0]$13324 + attribute \src "libresoc.v:192255.3-192269.6" + wire width 64 $2\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:192285.3-192304.6" + wire $2\we[0:0] + attribute \src "libresoc.v:192285.3-192304.6" + wire $3\we[0:0] + attribute \src "libresoc.v:192205.17-192205.129" + wire $and$libresoc.v:192205$13318_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:192166.7-192166.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_3_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:192205$13318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_3_wb__cyc + connect \B \sram4k_3_wb__stb + connect \Y $and$libresoc.v:192205$13318_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192208.21-192214.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:192166.7-192166.20" + process $proc$libresoc.v:192166$13329 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192183.7-192183.30" + process $proc$libresoc.v:192183$13330 + assign { } { } + assign $1\sram4k_3_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] + end + attribute \src "libresoc.v:192206.3-192207.49" + process $proc$libresoc.v:192206$13319 + assign { } { } + assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next + sync posedge \clk + update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] + end + attribute \src "libresoc.v:192215.3-192224.6" + process $proc$libresoc.v:192215$13320 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:192216.5-192216.29" + switch \initial + attribute \src "libresoc.v:192216.9-192216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:192225.3-192239.6" + process $proc$libresoc.v:192225$13321 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_3_wb__ack$next[0:0]$13322 $2\sram4k_3_wb__ack$next[0:0]$13324 + attribute \src "libresoc.v:192226.5-192226.29" + switch \initial + attribute \src "libresoc.v:192226.9-192226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3_wb__ack$next[0:0]$13323 \wb_active + case + assign $1\sram4k_3_wb__ack$next[0:0]$13323 \sram4k_3_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_3_wb__ack$next[0:0]$13324 1'0 + case + assign $2\sram4k_3_wb__ack$next[0:0]$13324 $1\sram4k_3_wb__ack$next[0:0]$13323 + end + sync always + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13322 + end + attribute \src "libresoc.v:192240.3-192254.6" + process $proc$libresoc.v:192240$13325 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:192241.5-192241.29" + switch \initial + attribute \src "libresoc.v:192241.9-192241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_3_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:192255.3-192269.6" + process $proc$libresoc.v:192255$13326 + assign { } { } + assign { } { } + assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:192256.5-192256.29" + switch \initial + attribute \src "libresoc.v:192256.9-192256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3_wb__dat_r[63:0] $2\sram4k_3_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_3_wb__dat_r[63:0] \q + case + assign $2\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] + end + attribute \src "libresoc.v:192270.3-192284.6" + process $proc$libresoc.v:192270$13327 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:192271.5-192271.29" + switch \initial + attribute \src "libresoc.v:192271.9-192271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_3_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:192285.3-192304.6" + process $proc$libresoc.v:192285$13328 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:192286.5-192286.29" + switch \initial + attribute \src "libresoc.v:192286.9-192286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_3_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_3_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:192205$13318_Y +end +attribute \src "libresoc.v:192309.1-192367.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" +attribute \generator "nMigen" +module \src_l + attribute \src "libresoc.v:192310.7-192310.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192355.3-192363.6" + wire width 4 $0\q_int$next[3:0]$13341 + attribute \src "libresoc.v:192353.3-192354.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:192355.3-192363.6" + wire width 4 $1\q_int$next[3:0]$13342 + attribute \src "libresoc.v:192332.13-192332.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:192345.17-192345.96" + wire width 4 $and$libresoc.v:192345$13331_Y + attribute \src "libresoc.v:192350.17-192350.96" + wire width 4 $and$libresoc.v:192350$13336_Y + attribute \src "libresoc.v:192347.18-192347.93" + wire width 4 $not$libresoc.v:192347$13333_Y + attribute \src "libresoc.v:192349.17-192349.92" + wire width 4 $not$libresoc.v:192349$13335_Y + attribute \src "libresoc.v:192352.17-192352.92" + wire width 4 $not$libresoc.v:192352$13338_Y + attribute \src "libresoc.v:192346.18-192346.98" + wire width 4 $or$libresoc.v:192346$13332_Y + attribute \src "libresoc.v:192348.18-192348.99" + wire width 4 $or$libresoc.v:192348$13334_Y + attribute \src "libresoc.v:192351.17-192351.97" + wire width 4 $or$libresoc.v:192351$13337_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192310.7-192310.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192345$13331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192345$13331_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192350$13336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192350$13336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192347$13333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $not$libresoc.v:192347$13333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192349$13335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:192349$13335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192352$13338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:192352$13338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192346$13332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192346$13332_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192348$13334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192348$13334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192351$13337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192351$13337_Y + end + attribute \src "libresoc.v:192310.7-192310.20" + process $proc$libresoc.v:192310$13343 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192332.13-192332.25" + process $proc$libresoc.v:192332$13344 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:192353.3-192354.27" + process $proc$libresoc.v:192353$13339 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:192355.3-192363.6" + process $proc$libresoc.v:192355$13340 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$13341 $1\q_int$next[3:0]$13342 + attribute \src "libresoc.v:192356.5-192356.29" + switch \initial + attribute \src "libresoc.v:192356.9-192356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$13342 4'0000 + case + assign $1\q_int$next[3:0]$13342 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$13341 + end + connect \$9 $and$libresoc.v:192345$13331_Y + connect \$11 $or$libresoc.v:192346$13332_Y + connect \$13 $not$libresoc.v:192347$13333_Y + connect \$15 $or$libresoc.v:192348$13334_Y + connect \$1 $not$libresoc.v:192349$13335_Y + connect \$3 $and$libresoc.v:192350$13336_Y + connect \$5 $or$libresoc.v:192351$13337_Y + connect \$7 $not$libresoc.v:192352$13338_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192371.1-192429.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" +attribute \generator "nMigen" +module \src_l$10 + attribute \src "libresoc.v:192372.7-192372.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192417.3-192425.6" + wire width 6 $0\q_int$next[5:0]$13355 + attribute \src "libresoc.v:192415.3-192416.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:192417.3-192425.6" + wire width 6 $1\q_int$next[5:0]$13356 + attribute \src "libresoc.v:192394.13-192394.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:192407.17-192407.96" + wire width 6 $and$libresoc.v:192407$13345_Y + attribute \src "libresoc.v:192412.17-192412.96" + wire width 6 $and$libresoc.v:192412$13350_Y + attribute \src "libresoc.v:192409.18-192409.93" + wire width 6 $not$libresoc.v:192409$13347_Y + attribute \src "libresoc.v:192411.17-192411.92" + wire width 6 $not$libresoc.v:192411$13349_Y + attribute \src "libresoc.v:192414.17-192414.92" + wire width 6 $not$libresoc.v:192414$13352_Y + attribute \src "libresoc.v:192408.18-192408.98" + wire width 6 $or$libresoc.v:192408$13346_Y + attribute \src "libresoc.v:192410.18-192410.99" + wire width 6 $or$libresoc.v:192410$13348_Y + attribute \src "libresoc.v:192413.17-192413.97" + wire width 6 $or$libresoc.v:192413$13351_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192372.7-192372.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192407$13345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192407$13345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192412$13350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192412$13350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192409$13347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$libresoc.v:192409$13347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192411$13349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:192411$13349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192414$13352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:192414$13352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192408$13346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192408$13346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192410$13348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192410$13348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192413$13351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192413$13351_Y + end + attribute \src "libresoc.v:192372.7-192372.20" + process $proc$libresoc.v:192372$13357 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192394.13-192394.26" + process $proc$libresoc.v:192394$13358 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:192415.3-192416.27" + process $proc$libresoc.v:192415$13353 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:192417.3-192425.6" + process $proc$libresoc.v:192417$13354 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$13355 $1\q_int$next[5:0]$13356 + attribute \src "libresoc.v:192418.5-192418.29" + switch \initial + attribute \src "libresoc.v:192418.9-192418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$13356 6'000000 + case + assign $1\q_int$next[5:0]$13356 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$13355 + end + connect \$9 $and$libresoc.v:192407$13345_Y + connect \$11 $or$libresoc.v:192408$13346_Y + connect \$13 $not$libresoc.v:192409$13347_Y + connect \$15 $or$libresoc.v:192410$13348_Y + connect \$1 $not$libresoc.v:192411$13349_Y + connect \$3 $and$libresoc.v:192412$13350_Y + connect \$5 $or$libresoc.v:192413$13351_Y + connect \$7 $not$libresoc.v:192414$13352_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192433.1-192491.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" +attribute \generator "nMigen" +module \src_l$101 + attribute \src "libresoc.v:192434.7-192434.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192479.3-192487.6" + wire width 3 $0\q_int$next[2:0]$13369 + attribute \src "libresoc.v:192477.3-192478.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:192479.3-192487.6" + wire width 3 $1\q_int$next[2:0]$13370 + attribute \src "libresoc.v:192456.13-192456.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:192469.17-192469.96" + wire width 3 $and$libresoc.v:192469$13359_Y + attribute \src "libresoc.v:192474.17-192474.96" + wire width 3 $and$libresoc.v:192474$13364_Y + attribute \src "libresoc.v:192471.18-192471.93" + wire width 3 $not$libresoc.v:192471$13361_Y + attribute \src "libresoc.v:192473.17-192473.92" + wire width 3 $not$libresoc.v:192473$13363_Y + attribute \src "libresoc.v:192476.17-192476.92" + wire width 3 $not$libresoc.v:192476$13366_Y + attribute \src "libresoc.v:192470.18-192470.98" + wire width 3 $or$libresoc.v:192470$13360_Y + attribute \src "libresoc.v:192472.18-192472.99" + wire width 3 $or$libresoc.v:192472$13362_Y + attribute \src "libresoc.v:192475.17-192475.97" + wire width 3 $or$libresoc.v:192475$13365_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192434.7-192434.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192469$13359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192469$13359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192474$13364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192474$13364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192471$13361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:192471$13361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192473$13363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192473$13363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192476$13366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192476$13366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192470$13360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192470$13360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192472$13362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192472$13362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192475$13365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192475$13365_Y + end + attribute \src "libresoc.v:192434.7-192434.20" + process $proc$libresoc.v:192434$13371 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192456.13-192456.25" + process $proc$libresoc.v:192456$13372 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:192477.3-192478.27" + process $proc$libresoc.v:192477$13367 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:192479.3-192487.6" + process $proc$libresoc.v:192479$13368 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13369 $1\q_int$next[2:0]$13370 + attribute \src "libresoc.v:192480.5-192480.29" + switch \initial + attribute \src "libresoc.v:192480.9-192480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13370 3'000 + case + assign $1\q_int$next[2:0]$13370 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13369 + end + connect \$9 $and$libresoc.v:192469$13359_Y + connect \$11 $or$libresoc.v:192470$13360_Y + connect \$13 $not$libresoc.v:192471$13361_Y + connect \$15 $or$libresoc.v:192472$13362_Y + connect \$1 $not$libresoc.v:192473$13363_Y + connect \$3 $and$libresoc.v:192474$13364_Y + connect \$5 $or$libresoc.v:192475$13365_Y + connect \$7 $not$libresoc.v:192476$13366_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192495.1-192553.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" +attribute \generator "nMigen" +module \src_l$119 + attribute \src "libresoc.v:192496.7-192496.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192541.3-192549.6" + wire width 5 $0\q_int$next[4:0]$13383 + attribute \src "libresoc.v:192539.3-192540.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:192541.3-192549.6" + wire width 5 $1\q_int$next[4:0]$13384 + attribute \src "libresoc.v:192518.13-192518.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:192531.17-192531.96" + wire width 5 $and$libresoc.v:192531$13373_Y + attribute \src "libresoc.v:192536.17-192536.96" + wire width 5 $and$libresoc.v:192536$13378_Y + attribute \src "libresoc.v:192533.18-192533.93" + wire width 5 $not$libresoc.v:192533$13375_Y + attribute \src "libresoc.v:192535.17-192535.92" + wire width 5 $not$libresoc.v:192535$13377_Y + attribute \src "libresoc.v:192538.17-192538.92" + wire width 5 $not$libresoc.v:192538$13380_Y + attribute \src "libresoc.v:192532.18-192532.98" + wire width 5 $or$libresoc.v:192532$13374_Y + attribute \src "libresoc.v:192534.18-192534.99" + wire width 5 $or$libresoc.v:192534$13376_Y + attribute \src "libresoc.v:192537.17-192537.97" + wire width 5 $or$libresoc.v:192537$13379_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 5 \$15 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192533$13375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \Y $not$libresoc.v:192533$13375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192535$13377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:192535$13377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192538$13380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:192538$13380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192532$13374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192532$13374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192534$13376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192534$13376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192537$13379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192537$13379_Y + end + attribute \src "libresoc.v:192496.7-192496.20" + process $proc$libresoc.v:192496$13385 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192518.13-192518.26" + process $proc$libresoc.v:192518$13386 + assign { } { } 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$or$libresoc.v:192532$13374_Y + connect \$13 $not$libresoc.v:192533$13375_Y + connect \$15 $or$libresoc.v:192534$13376_Y + connect \$1 $not$libresoc.v:192535$13377_Y + connect \$3 $and$libresoc.v:192536$13378_Y + connect \$5 $or$libresoc.v:192537$13379_Y + connect \$7 $not$libresoc.v:192538$13380_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192557.1-192615.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" +attribute \generator "nMigen" +module \src_l$127 + attribute \src "libresoc.v:192558.7-192558.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192603.3-192611.6" + wire width 3 $0\q_int$next[2:0]$13397 + attribute \src "libresoc.v:192601.3-192602.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:192603.3-192611.6" + wire width 3 $1\q_int$next[2:0]$13398 + attribute \src "libresoc.v:192580.13-192580.25" + wire width 3 $1\q_int[2:0] + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192558.7-192558.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192593$13387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192593$13387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192598$13392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192598$13392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192595$13389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:192595$13389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192597$13391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192597$13391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192600$13394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192600$13394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192594$13388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192594$13388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192596$13390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192596$13390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192599$13393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192599$13393_Y + end + attribute \src "libresoc.v:192558.7-192558.20" + process $proc$libresoc.v:192558$13399 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192580.13-192580.25" + process $proc$libresoc.v:192580$13400 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:192601.3-192602.27" + process $proc$libresoc.v:192601$13395 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:192603.3-192611.6" + process $proc$libresoc.v:192603$13396 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13397 $1\q_int$next[2:0]$13398 + attribute \src "libresoc.v:192604.5-192604.29" + switch \initial + attribute \src "libresoc.v:192604.9-192604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13398 3'000 + case + assign $1\q_int$next[2:0]$13398 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13397 + end + connect \$9 $and$libresoc.v:192593$13387_Y + connect \$11 $or$libresoc.v:192594$13388_Y + connect \$13 $not$libresoc.v:192595$13389_Y + connect \$15 $or$libresoc.v:192596$13390_Y + connect \$1 $not$libresoc.v:192597$13391_Y + connect \$3 $and$libresoc.v:192598$13392_Y + connect \$5 $or$libresoc.v:192599$13393_Y + connect \$7 $not$libresoc.v:192600$13394_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192619.1-192677.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" +attribute \generator "nMigen" +module \src_l$23 + attribute \src "libresoc.v:192620.7-192620.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192665.3-192673.6" + wire width 3 $0\q_int$next[2:0]$13411 + attribute \src "libresoc.v:192663.3-192664.27" + wire width 3 $0\q_int[2:0] + attribute \src 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3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192620.7-192620.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192655$13401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192655$13401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192660$13406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192660$13406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192657$13403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:192657$13403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192659$13405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192659$13405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192662$13408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192662$13408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192656$13402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192656$13402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192658$13404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192658$13404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192661$13407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192661$13407_Y + end + attribute \src "libresoc.v:192620.7-192620.20" + process $proc$libresoc.v:192620$13413 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192642.13-192642.25" + process $proc$libresoc.v:192642$13414 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:192663.3-192664.27" + process $proc$libresoc.v:192663$13409 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:192665.3-192673.6" + process $proc$libresoc.v:192665$13410 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13411 $1\q_int$next[2:0]$13412 + attribute \src "libresoc.v:192666.5-192666.29" + switch \initial + attribute \src "libresoc.v:192666.9-192666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13412 3'000 + case + assign $1\q_int$next[2:0]$13412 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13411 + end + connect \$9 $and$libresoc.v:192655$13401_Y + connect \$11 $or$libresoc.v:192656$13402_Y + connect \$13 $not$libresoc.v:192657$13403_Y + connect \$15 $or$libresoc.v:192658$13404_Y + connect \$1 $not$libresoc.v:192659$13405_Y + connect \$3 $and$libresoc.v:192660$13406_Y + connect \$5 $or$libresoc.v:192661$13407_Y + connect \$7 $not$libresoc.v:192662$13408_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192681.1-192739.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" +attribute \generator "nMigen" +module \src_l$39 + attribute \src "libresoc.v:192682.7-192682.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192727.3-192735.6" + wire width 4 $0\q_int$next[3:0]$13425 + attribute \src "libresoc.v:192725.3-192726.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:192727.3-192735.6" + wire width 4 $1\q_int$next[3:0]$13426 + attribute \src "libresoc.v:192704.13-192704.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:192717.17-192717.96" + wire width 4 $and$libresoc.v:192717$13415_Y + attribute \src "libresoc.v:192722.17-192722.96" + wire width 4 $and$libresoc.v:192722$13420_Y + attribute \src "libresoc.v:192719.18-192719.93" + wire width 4 $not$libresoc.v:192719$13417_Y + attribute \src "libresoc.v:192721.17-192721.92" + wire width 4 $not$libresoc.v:192721$13419_Y + attribute \src "libresoc.v:192724.17-192724.92" + wire width 4 $not$libresoc.v:192724$13422_Y + attribute \src "libresoc.v:192718.18-192718.98" + wire width 4 $or$libresoc.v:192718$13416_Y + attribute \src "libresoc.v:192720.18-192720.99" + wire width 4 $or$libresoc.v:192720$13418_Y + attribute \src "libresoc.v:192723.17-192723.97" + wire width 4 $or$libresoc.v:192723$13421_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192682.7-192682.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192717$13415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192717$13415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192722$13420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192722$13420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192719$13417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $not$libresoc.v:192719$13417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192721$13419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:192721$13419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192724$13422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:192724$13422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192718$13416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192718$13416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192720$13418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192720$13418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192723$13421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192723$13421_Y + end + attribute \src "libresoc.v:192682.7-192682.20" + process $proc$libresoc.v:192682$13427 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192704.13-192704.25" + process $proc$libresoc.v:192704$13428 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:192725.3-192726.27" + process $proc$libresoc.v:192725$13423 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:192727.3-192735.6" + process $proc$libresoc.v:192727$13424 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$13425 $1\q_int$next[3:0]$13426 + attribute \src "libresoc.v:192728.5-192728.29" + switch \initial + attribute \src "libresoc.v:192728.9-192728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$13426 4'0000 + case + assign $1\q_int$next[3:0]$13426 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$13425 + end + connect \$9 $and$libresoc.v:192717$13415_Y + connect \$11 $or$libresoc.v:192718$13416_Y + connect \$13 $not$libresoc.v:192719$13417_Y + connect \$15 $or$libresoc.v:192720$13418_Y + connect \$1 $not$libresoc.v:192721$13419_Y + connect \$3 $and$libresoc.v:192722$13420_Y + connect \$5 $or$libresoc.v:192723$13421_Y + connect \$7 $not$libresoc.v:192724$13422_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192743.1-192801.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" +attribute \generator "nMigen" +module \src_l$55 + attribute \src "libresoc.v:192744.7-192744.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192789.3-192797.6" + wire width 3 $0\q_int$next[2:0]$13439 + attribute \src "libresoc.v:192787.3-192788.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:192789.3-192797.6" + wire width 3 $1\q_int$next[2:0]$13440 + attribute \src "libresoc.v:192766.13-192766.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:192779.17-192779.96" + wire width 3 $and$libresoc.v:192779$13429_Y + attribute \src "libresoc.v:192784.17-192784.96" + wire width 3 $and$libresoc.v:192784$13434_Y + attribute \src "libresoc.v:192781.18-192781.93" + wire width 3 $not$libresoc.v:192781$13431_Y + attribute \src "libresoc.v:192783.17-192783.92" + wire width 3 $not$libresoc.v:192783$13433_Y + attribute \src "libresoc.v:192786.17-192786.92" + wire width 3 $not$libresoc.v:192786$13436_Y + attribute \src "libresoc.v:192780.18-192780.98" + wire width 3 $or$libresoc.v:192780$13430_Y + attribute \src "libresoc.v:192782.18-192782.99" + wire width 3 $or$libresoc.v:192782$13432_Y + attribute \src "libresoc.v:192785.17-192785.97" + wire width 3 $or$libresoc.v:192785$13435_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192744.7-192744.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192779$13429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192779$13429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192784$13434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192784$13434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192781$13431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:192781$13431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192783$13433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192783$13433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192786$13436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192786$13436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192780$13430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192780$13430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192782$13432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192782$13432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192785$13435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192785$13435_Y + end + attribute \src "libresoc.v:192744.7-192744.20" + process $proc$libresoc.v:192744$13441 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192766.13-192766.25" + process $proc$libresoc.v:192766$13442 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:192787.3-192788.27" + process $proc$libresoc.v:192787$13437 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:192789.3-192797.6" + process $proc$libresoc.v:192789$13438 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13439 $1\q_int$next[2:0]$13440 + attribute \src "libresoc.v:192790.5-192790.29" + switch \initial + attribute \src "libresoc.v:192790.9-192790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13440 3'000 + case + assign $1\q_int$next[2:0]$13440 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13439 + end + connect \$9 $and$libresoc.v:192779$13429_Y + connect \$11 $or$libresoc.v:192780$13430_Y + connect \$13 $not$libresoc.v:192781$13431_Y + connect \$15 $or$libresoc.v:192782$13432_Y + connect \$1 $not$libresoc.v:192783$13433_Y + connect \$3 $and$libresoc.v:192784$13434_Y + connect \$5 $or$libresoc.v:192785$13435_Y + connect \$7 $not$libresoc.v:192786$13436_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192805.1-192863.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" +attribute \generator "nMigen" +module \src_l$67 + attribute \src "libresoc.v:192806.7-192806.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192851.3-192859.6" + wire width 6 $0\q_int$next[5:0]$13453 + attribute \src "libresoc.v:192849.3-192850.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:192851.3-192859.6" + wire width 6 $1\q_int$next[5:0]$13454 + attribute \src "libresoc.v:192828.13-192828.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:192841.17-192841.96" + wire width 6 $and$libresoc.v:192841$13443_Y + attribute \src "libresoc.v:192846.17-192846.96" + wire width 6 $and$libresoc.v:192846$13448_Y + attribute \src "libresoc.v:192843.18-192843.93" + wire width 6 $not$libresoc.v:192843$13445_Y + attribute \src "libresoc.v:192845.17-192845.92" + wire width 6 $not$libresoc.v:192845$13447_Y + attribute \src "libresoc.v:192848.17-192848.92" + wire width 6 $not$libresoc.v:192848$13450_Y + attribute \src "libresoc.v:192842.18-192842.98" + wire width 6 $or$libresoc.v:192842$13444_Y + attribute \src "libresoc.v:192844.18-192844.99" + wire width 6 $or$libresoc.v:192844$13446_Y + attribute \src "libresoc.v:192847.17-192847.97" + wire width 6 $or$libresoc.v:192847$13449_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192806.7-192806.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192841$13443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192841$13443_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192846$13448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192846$13448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192843$13445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$libresoc.v:192843$13445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192845$13447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:192845$13447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192848$13450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:192848$13450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192842$13444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192842$13444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192844$13446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192844$13446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192847$13449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192847$13449_Y + end + attribute \src "libresoc.v:192806.7-192806.20" + process $proc$libresoc.v:192806$13455 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192828.13-192828.26" + process $proc$libresoc.v:192828$13456 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:192849.3-192850.27" + process $proc$libresoc.v:192849$13451 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:192851.3-192859.6" + process $proc$libresoc.v:192851$13452 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$13453 $1\q_int$next[5:0]$13454 + attribute \src "libresoc.v:192852.5-192852.29" + switch \initial + attribute \src "libresoc.v:192852.9-192852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$13454 6'000000 + case + assign $1\q_int$next[5:0]$13454 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$13453 + end + connect \$9 $and$libresoc.v:192841$13443_Y + connect \$11 $or$libresoc.v:192842$13444_Y + connect \$13 $not$libresoc.v:192843$13445_Y + connect \$15 $or$libresoc.v:192844$13446_Y + connect \$1 $not$libresoc.v:192845$13447_Y + connect \$3 $and$libresoc.v:192846$13448_Y + connect \$5 $or$libresoc.v:192847$13449_Y + connect \$7 $not$libresoc.v:192848$13450_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192867.1-192925.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" +attribute \generator "nMigen" +module \src_l$84 + attribute \src "libresoc.v:192868.7-192868.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192913.3-192921.6" + wire width 3 $0\q_int$next[2:0]$13467 + attribute \src "libresoc.v:192911.3-192912.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:192913.3-192921.6" + wire width 3 $1\q_int$next[2:0]$13468 + attribute \src "libresoc.v:192890.13-192890.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:192903.17-192903.96" + wire width 3 $and$libresoc.v:192903$13457_Y + attribute \src "libresoc.v:192908.17-192908.96" + wire width 3 $and$libresoc.v:192908$13462_Y + attribute \src "libresoc.v:192905.18-192905.93" + wire width 3 $not$libresoc.v:192905$13459_Y + attribute \src "libresoc.v:192907.17-192907.92" + wire width 3 $not$libresoc.v:192907$13461_Y + attribute \src "libresoc.v:192910.17-192910.92" + wire width 3 $not$libresoc.v:192910$13464_Y + attribute \src "libresoc.v:192904.18-192904.98" + wire width 3 $or$libresoc.v:192904$13458_Y + attribute \src "libresoc.v:192906.18-192906.99" + wire width 3 $or$libresoc.v:192906$13460_Y + attribute \src "libresoc.v:192909.17-192909.97" + wire width 3 $or$libresoc.v:192909$13463_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192868.7-192868.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:192903$13457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:192903$13457_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:192908$13462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:192908$13462_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:192905$13459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:192905$13459_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:192907$13461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192907$13461_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:192910$13464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:192910$13464_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:192904$13458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:192904$13458_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192906$13460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:192906$13460_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192909$13463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:192909$13463_Y + end + attribute \src "libresoc.v:192868.7-192868.20" + process $proc$libresoc.v:192868$13469 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192890.13-192890.25" + process $proc$libresoc.v:192890$13470 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:192911.3-192912.27" + process $proc$libresoc.v:192911$13465 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:192913.3-192921.6" + process $proc$libresoc.v:192913$13466 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13467 $1\q_int$next[2:0]$13468 + attribute \src "libresoc.v:192914.5-192914.29" + switch \initial + attribute \src "libresoc.v:192914.9-192914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13468 3'000 + case + assign $1\q_int$next[2:0]$13468 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13467 + end + connect \$9 $and$libresoc.v:192903$13457_Y + connect \$11 $or$libresoc.v:192904$13458_Y + connect \$13 $not$libresoc.v:192905$13459_Y + connect \$15 $or$libresoc.v:192906$13460_Y + connect \$1 $not$libresoc.v:192907$13461_Y + connect \$3 $and$libresoc.v:192908$13462_Y + connect \$5 $or$libresoc.v:192909$13463_Y + connect \$7 $not$libresoc.v:192910$13464_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:192929.1-192987.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" +attribute \generator "nMigen" +module \st_active + attribute \src "libresoc.v:192930.7-192930.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192975.3-192983.6" + wire $0\q_int$next[0:0]$13481 + attribute \src "libresoc.v:192973.3-192974.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:192975.3-192983.6" + wire $1\q_int$next[0:0]$13482 + attribute \src "libresoc.v:192952.7-192952.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:192965.17-192965.96" + wire $and$libresoc.v:192965$13471_Y + attribute \src "libresoc.v:192970.17-192970.96" + wire $and$libresoc.v:192970$13476_Y + attribute \src "libresoc.v:192967.18-192967.99" + wire $not$libresoc.v:192967$13473_Y + attribute \src "libresoc.v:192969.17-192969.98" + wire $not$libresoc.v:192969$13475_Y + attribute \src "libresoc.v:192972.17-192972.98" + wire $not$libresoc.v:192972$13478_Y + attribute \src "libresoc.v:192966.18-192966.104" + wire $or$libresoc.v:192966$13472_Y + attribute \src "libresoc.v:192968.18-192968.105" + wire $or$libresoc.v:192968$13474_Y + attribute \src "libresoc.v:192971.17-192971.103" + wire $or$libresoc.v:192971$13477_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:192930.7-192930.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_st_active + attribute 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$or$libresoc.v:192966$13472_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:192968$13474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \B \q_int + connect \Y $or$libresoc.v:192968$13474_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:192971$13477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_active + connect \Y $or$libresoc.v:192971$13477_Y + end + attribute \src "libresoc.v:192930.7-192930.20" + process $proc$libresoc.v:192930$13483 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192952.7-192952.19" + process $proc$libresoc.v:192952$13484 + assign { } { } + assign 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 64 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 2 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 7 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \data_i$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \data_i$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \data_i$4 + attribute \src "libresoc.v:193054.7-193054.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 9 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 8 \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_cia0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_d_wr10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_sv0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_0_sv0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_sv0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_sv0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_sv1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_sv1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_sv1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_sv1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_d_wr12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_nia2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_sv2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_sv2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_sv2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_sv2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 12 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \sv__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 4 \sv__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 6 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 10 \wen$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \wen$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:193204$13499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_cia0__data_o + connect \B \$8 + connect \Y $or$libresoc.v:193204$13499_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:193206$13501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_1_msr1__data_o + connect \B \reg_2_msr2__data_o + connect \Y $or$libresoc.v:193206$13501_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:193207$13502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_msr0__data_o + connect \B \$15 + connect \Y $or$libresoc.v:193207$13502_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:193209$13504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_1_sv1__data_o + connect \B \reg_2_sv2__data_o + connect \Y $or$libresoc.v:193209$13504_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:193210$13505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_sv0__data_o + connect \B \$22 + connect \Y $or$libresoc.v:193210$13505_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:193212$13507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_1_cia1__data_o + connect \B \reg_2_cia2__data_o + connect \Y $or$libresoc.v:193212$13507_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:193205$13500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$12 + connect \Y $reduce_or$libresoc.v:193205$13500_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:193208$13503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$19 + connect \Y $reduce_or$libresoc.v:193208$13503_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:193211$13506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:193211$13506_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:193219.15-193236.4" + cell \reg_0$135 \reg_0 + connect \cia0__data_o \reg_0_cia0__data_o + connect \cia0__ren \reg_0_cia0__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr10__data_i \reg_0_d_wr10__data_i + connect \d_wr10__wen \reg_0_d_wr10__wen + connect \msr0__data_i \reg_0_msr0__data_i + connect \msr0__data_o \reg_0_msr0__data_o + connect \msr0__ren \reg_0_msr0__ren + connect \msr0__wen \reg_0_msr0__wen + connect \nia0__data_i \reg_0_nia0__data_i + connect \nia0__wen \reg_0_nia0__wen + connect \sv0__data_i \reg_0_sv0__data_i + connect \sv0__data_o \reg_0_sv0__data_o + connect \sv0__ren \reg_0_sv0__ren + connect \sv0__wen \reg_0_sv0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:193237.15-193254.4" + cell \reg_1$136 \reg_1 + connect \cia1__data_o \reg_1_cia1__data_o + connect \cia1__ren \reg_1_cia1__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr11__data_i \reg_1_d_wr11__data_i + connect \d_wr11__wen \reg_1_d_wr11__wen + connect \msr1__data_i \reg_1_msr1__data_i + connect \msr1__data_o \reg_1_msr1__data_o + connect \msr1__ren \reg_1_msr1__ren + connect \msr1__wen \reg_1_msr1__wen + connect \nia1__data_i \reg_1_nia1__data_i + connect \nia1__wen \reg_1_nia1__wen + connect \sv1__data_i \reg_1_sv1__data_i + connect \sv1__data_o \reg_1_sv1__data_o + connect \sv1__ren \reg_1_sv1__ren + connect \sv1__wen \reg_1_sv1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:193255.15-193272.4" + cell \reg_2$137 \reg_2 + connect \cia2__data_o \reg_2_cia2__data_o + connect \cia2__ren \reg_2_cia2__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr12__data_i \reg_2_d_wr12__data_i + connect \d_wr12__wen \reg_2_d_wr12__wen + connect \msr2__data_i \reg_2_msr2__data_i + connect \msr2__data_o \reg_2_msr2__data_o + connect \msr2__ren \reg_2_msr2__ren + connect \msr2__wen \reg_2_msr2__wen + connect \nia2__data_i \reg_2_nia2__data_i + connect \nia2__wen \reg_2_nia2__wen + connect \sv2__data_i \reg_2_sv2__data_i + connect \sv2__data_o \reg_2_sv2__data_o + connect \sv2__ren \reg_2_sv2__ren + connect \sv2__wen \reg_2_sv2__wen + end + attribute \src "libresoc.v:193054.7-193054.20" + process $proc$libresoc.v:193054$13525 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:193180.13-193180.29" + process $proc$libresoc.v:193180$13526 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "libresoc.v:193182.13-193182.34" + process $proc$libresoc.v:193182$13527 + assign { } { } + assign $0\ren_delay$12[2:0]$13528 3'000 + sync always + sync init + update \ren_delay$12 $0\ren_delay$12[2:0]$13528 + end + attribute \src "libresoc.v:193186.13-193186.34" + process $proc$libresoc.v:193186$13529 + assign { } { } + assign $0\ren_delay$19[2:0]$13530 3'000 + sync always + sync init + update \ren_delay$19 $0\ren_delay$19[2:0]$13530 + end + attribute \src "libresoc.v:193213.3-193214.43" + process $proc$libresoc.v:193213$13508 + assign { } { } + assign $0\ren_delay$19[2:0]$13509 \ren_delay$19$next + sync posedge \coresync_clk + update \ren_delay$19 $0\ren_delay$19[2:0]$13509 + end + attribute \src "libresoc.v:193215.3-193216.43" + process $proc$libresoc.v:193215$13510 + assign { } { } + assign $0\ren_delay$12[2:0]$13511 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[2:0]$13511 + end + attribute \src "libresoc.v:193217.3-193218.35" + process $proc$libresoc.v:193217$13512 + assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:193273.3-193281.6" + process $proc$libresoc.v:193273$13513 + assign { } { } + assign { } { } + assign $0\ren_delay$19$next[2:0]$13514 $1\ren_delay$19$next[2:0]$13515 + attribute \src "libresoc.v:193274.5-193274.29" + switch \initial + attribute \src "libresoc.v:193274.9-193274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$19$next[2:0]$13515 3'000 + case + assign $1\ren_delay$19$next[2:0]$13515 \sv__ren + end + sync always + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13514 + end + attribute \src "libresoc.v:193282.3-193291.6" + process $proc$libresoc.v:193282$13516 + assign { } { } + assign { } { } + assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] + attribute \src "libresoc.v:193283.5-193283.29" + switch \initial + attribute \src "libresoc.v:193283.9-193283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$20 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sv__data_o[63:0] \$24 + case + assign $1\sv__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sv__data_o $0\sv__data_o[63:0] + end + attribute \src "libresoc.v:193292.3-193300.6" + process $proc$libresoc.v:193292$13517 + assign { } { } + assign { } { } + assign $0\ren_delay$next[2:0]$13518 $1\ren_delay$next[2:0]$13519 + attribute \src "libresoc.v:193293.5-193293.29" + switch \initial + attribute \src "libresoc.v:193293.9-193293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[2:0]$13519 3'000 + case + assign $1\ren_delay$next[2:0]$13519 \cia__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[2:0]$13518 + end + attribute \src "libresoc.v:193301.3-193310.6" + process $proc$libresoc.v:193301$13520 + assign { } { } + assign { } { } + assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] + attribute \src "libresoc.v:193302.5-193302.29" + switch \initial + attribute \src "libresoc.v:193302.9-193302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cia__data_o[63:0] \$10 + case + assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cia__data_o $0\cia__data_o[63:0] + end + attribute \src "libresoc.v:193311.3-193319.6" + process $proc$libresoc.v:193311$13521 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[2:0]$13522 $1\ren_delay$12$next[2:0]$13523 + attribute \src "libresoc.v:193312.5-193312.29" + switch \initial + attribute \src "libresoc.v:193312.9-193312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[2:0]$13523 3'000 + case + assign $1\ren_delay$12$next[2:0]$13523 \msr__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13522 + end + attribute \src "libresoc.v:193320.3-193329.6" + process $proc$libresoc.v:193320$13524 + assign { } { } + assign { } { } + assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] + attribute \src "libresoc.v:193321.5-193321.29" + switch \initial + attribute \src "libresoc.v:193321.9-193321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\msr__data_o[63:0] \$17 + case + assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \msr__data_o $0\msr__data_o[63:0] + end + connect \$10 $or$libresoc.v:193204$13499_Y + connect \$13 $reduce_or$libresoc.v:193205$13500_Y + connect \$15 $or$libresoc.v:193206$13501_Y + connect \$17 $or$libresoc.v:193207$13502_Y + connect \$20 $reduce_or$libresoc.v:193208$13503_Y + connect \$22 $or$libresoc.v:193209$13504_Y + connect \$24 $or$libresoc.v:193210$13505_Y + connect \$6 $reduce_or$libresoc.v:193211$13506_Y + connect \$8 $or$libresoc.v:193212$13507_Y + connect \reg_2_d_wr12__data_i \data_i + connect \reg_1_d_wr11__data_i \data_i + connect \reg_0_d_wr10__data_i \data_i + connect { \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + connect \reg_2_sv2__data_i \data_i$2 + connect \reg_1_sv1__data_i \data_i$2 + connect \reg_0_sv0__data_i \data_i$2 + connect { \reg_2_sv2__wen \reg_1_sv1__wen \reg_0_sv0__wen } \wen$1 + connect \reg_2_msr2__data_i \data_i$4 + connect \reg_1_msr1__data_i \data_i$4 + connect \reg_0_msr0__data_i \data_i$4 + connect { \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$5 + connect \reg_2_nia2__data_i \data_i$3 + connect \reg_1_nia1__data_i \data_i$3 + connect \reg_0_nia0__data_i \data_i$3 + connect { \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + connect { \reg_2_sv2__ren \reg_1_sv1__ren \reg_0_sv0__ren } \sv__ren + connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren +end +attribute \src "libresoc.v:193353.1-193411.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" +attribute \generator "nMigen" +module \sto_l + attribute \src "libresoc.v:193354.7-193354.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:193399.3-193407.6" + wire $0\q_int$next[0:0]$13541 + attribute \src "libresoc.v:193397.3-193398.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:193399.3-193407.6" + wire $1\q_int$next[0:0]$13542 + attribute \src "libresoc.v:193376.7-193376.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:193389.17-193389.96" + wire $and$libresoc.v:193389$13531_Y + attribute \src "libresoc.v:193394.17-193394.96" + wire $and$libresoc.v:193394$13536_Y + attribute \src "libresoc.v:193391.18-193391.93" + wire $not$libresoc.v:193391$13533_Y + attribute \src "libresoc.v:193393.17-193393.92" + wire $not$libresoc.v:193393$13535_Y + attribute \src "libresoc.v:193396.17-193396.92" + wire $not$libresoc.v:193396$13538_Y + attribute \src "libresoc.v:193390.18-193390.98" + wire $or$libresoc.v:193390$13532_Y + attribute \src "libresoc.v:193392.18-193392.99" + wire $or$libresoc.v:193392$13534_Y + attribute \src "libresoc.v:193395.17-193395.97" + wire $or$libresoc.v:193395$13537_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:193354.7-193354.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:193389$13531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:193389$13531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:193394$13536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:193394$13536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:193391$13533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \Y $not$libresoc.v:193391$13533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:193393$13535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:193393$13535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:193396$13538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:193396$13538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:193390$13532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_sto + connect \Y $or$libresoc.v:193390$13532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:193392$13534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \B \q_int + connect \Y $or$libresoc.v:193392$13534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:193395$13537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_sto + connect \Y $or$libresoc.v:193395$13537_Y + end + attribute \src "libresoc.v:193354.7-193354.20" + process $proc$libresoc.v:193354$13543 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:193376.7-193376.19" + process $proc$libresoc.v:193376$13544 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:193397.3-193398.27" + process $proc$libresoc.v:193397$13539 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:193399.3-193407.6" + process $proc$libresoc.v:193399$13540 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13541 $1\q_int$next[0:0]$13542 + attribute \src "libresoc.v:193400.5-193400.29" + switch \initial + attribute \src "libresoc.v:193400.9-193400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13542 1'0 + case + assign $1\q_int$next[0:0]$13542 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13541 + end + connect \$9 $and$libresoc.v:193389$13531_Y + connect \$11 $or$libresoc.v:193390$13532_Y + connect \$13 $not$libresoc.v:193391$13533_Y + connect \$15 $or$libresoc.v:193392$13534_Y + connect \$1 $not$libresoc.v:193393$13535_Y + connect \$3 $and$libresoc.v:193394$13536_Y + connect \$5 $or$libresoc.v:193395$13537_Y + connect \$7 $not$libresoc.v:193396$13538_Y + connect \qlq_sto \$15 + connect \qn_sto \$13 + connect \q_sto \$11 +end +attribute \src "libresoc.v:193416.1-194641.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 400 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 402 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 340 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 334 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 344 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 343 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 338 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 336 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 335 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 342 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 337 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 339 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 341 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 19 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 21 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 23 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 37 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 41 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 42 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 43 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 47 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 48 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 49 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 53 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 54 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 55 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 59 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 60 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 61 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 65 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 66 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 67 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 71 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 72 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 25 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 29 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 30 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 31 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 35 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 36 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 73 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 77 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 78 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 79 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 83 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 84 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 85 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 89 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 90 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 91 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 95 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 96 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 97 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 101 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 102 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 103 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 107 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 108 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 109 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 113 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 114 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 115 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 119 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 120 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 329 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 323 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 333 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 332 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 327 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 325 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 324 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 331 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 326 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 328 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 330 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 387 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 381 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 385 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 383 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 382 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 389 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 384 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 386 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 388 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 396 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 390 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 394 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 392 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 391 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 398 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 393 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 395 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 397 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 399 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 122 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 124 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 127 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 126 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 130 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 132 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 135 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 134 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 144 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 137 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 141 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 405 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" + wire output 403 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 404 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire \pll_pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" + wire \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" + wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 146 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 148 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 401 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 156 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 149 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 153 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 154 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 157 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 161 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 162 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 163 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 178 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 231 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 267 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 269 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 271 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 233 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 235 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 237 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 239 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 241 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 243 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 245 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 247 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 249 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 251 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 253 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 261 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 257 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 255 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 265 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 181 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 273 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 184 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 185 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 186 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 288 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 289 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 290 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 294 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 295 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 296 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 300 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 301 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 302 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 306 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 307 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 308 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 312 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 313 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 314 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 318 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 319 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 320 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 190 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 191 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 192 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 196 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 197 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 198 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 202 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 203 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 204 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 208 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 209 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 210 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 214 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 215 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 216 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 220 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 221 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 222 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 226 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 227 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 228 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 276 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 277 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 278 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 282 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 283 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 284 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 259 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 263 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 352 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 345 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 349 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 347 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 346 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_0_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 348 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 350 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 351 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 361 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 354 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 358 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 356 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 355 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 362 \sram4k_1_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 357 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 359 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 360 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 370 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 363 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 367 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 365 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 364 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 371 \sram4k_2_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 366 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 368 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 369 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 379 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 372 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 376 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 374 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 373 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 380 \sram4k_3_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 375 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 377 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 378 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire \ti_coresync_clk + attribute \module_not_derived 1 + attribute \src "libresoc.v:194239.7-194245.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \clk_sel_i \clk_sel_i + connect \pll_18_o \pll_pll_18_o + connect \pll_lck_o \pll_lck_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:194246.6-194635.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \clk \clk + connect \core_bigendian_i \core_bigendian_i + connect \coresync_clk \ti_coresync_clk + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we + end + connect \ti_coresync_clk \pll_clk_pll_o + connect \pllclk_rst \rst + connect \pll_18_o \pll_pll_18_o + connect \pll_clk_24_i \clk + connect \pllclk_clk \pll_clk_pll_o +end +attribute \src "libresoc.v:194645.1-199858.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti" +attribute \generator "nMigen" +module \ti + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_asmcode$next[7:0]$14042 + attribute \src "libresoc.v:197237.3-197238.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:198140.3-198164.6" + wire $0\core_bigendian_i$10$next[0:0]$13837 + attribute \src "libresoc.v:197367.3-197368.57" + wire $0\core_bigendian_i$10[0:0]$13756 + attribute \src "libresoc.v:194920.7-194920.35" + wire $0\core_bigendian_i$10[0:0]$14249 + attribute \src "libresoc.v:198723.3-198735.6" + wire width 3 $0\core_cia__ren[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $0\core_core_core_cia$next[63:0]$14043 + attribute \src "libresoc.v:197311.3-197312.53" + wire width 64 $0\core_core_core_cia[63:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$14044 + attribute \src "libresoc.v:197355.3-197356.57" + wire width 8 $0\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$14045 + attribute \src "libresoc.v:197357.3-197358.63" + wire $0\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$14046 + attribute \src "libresoc.v:197359.3-197360.57" + wire width 8 $0\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$14047 + attribute \src "libresoc.v:197337.3-197338.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13734 + attribute \src "libresoc.v:194946.7-194946.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14257 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$14048 + attribute \src "libresoc.v:197339.3-197340.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13736 + attribute \src "libresoc.v:194950.7-194950.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14259 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$14049 + attribute \src "libresoc.v:197341.3-197342.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13738 + attribute \src "libresoc.v:194954.7-194954.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14261 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$14050 + attribute \src "libresoc.v:197343.3-197344.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13740 + attribute \src "libresoc.v:194958.7-194958.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14263 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$14051 + attribute \src "libresoc.v:197347.3-197348.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13743 + attribute \src "libresoc.v:194962.7-194962.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14265 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$14052 + attribute \src "libresoc.v:197349.3-197350.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13745 + attribute \src "libresoc.v:194966.7-194966.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14267 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$14053 + attribute \src "libresoc.v:197351.3-197352.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13747 + attribute \src "libresoc.v:194970.7-194970.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14269 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$next[0:0]$14054 + attribute \src "libresoc.v:197335.3-197336.71" + wire $0\core_core_core_exc_$signal[0:0]$13732 + attribute \src "libresoc.v:194944.7-194944.42" + wire $0\core_core_core_exc_$signal[0:0]$14255 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$14055 + attribute \src "libresoc.v:197317.3-197318.61" + wire width 14 $0\core_core_core_fn_unit[13:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$14056 + attribute \src "libresoc.v:197331.3-197332.69" + wire width 2 $0\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $0\core_core_core_insn$next[31:0]$14057 + attribute \src "libresoc.v:197313.3-197314.55" + wire width 32 $0\core_core_core_insn[31:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$14058 + attribute \src "libresoc.v:197315.3-197316.65" + wire width 7 $0\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_is_32bit$next[0:0]$14059 + attribute \src "libresoc.v:197363.3-197364.63" + wire $0\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $0\core_core_core_msr$next[63:0]$14060 + attribute \src "libresoc.v:197309.3-197310.53" + wire width 64 $0\core_core_core_msr[63:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_oe$next[0:0]$14061 + attribute \src "libresoc.v:197327.3-197328.51" + wire $0\core_core_core_oe[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_oe_ok$next[0:0]$14062 + attribute \src "libresoc.v:197329.3-197330.57" + wire $0\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_rc$next[0:0]$14063 + attribute \src "libresoc.v:197321.3-197322.51" + wire $0\core_core_core_rc[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_rc_ok$next[0:0]$14064 + attribute \src "libresoc.v:197325.3-197326.57" + wire $0\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$14065 + attribute \src "libresoc.v:197353.3-197354.63" + wire width 13 $0\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$14066 + attribute \src "libresoc.v:197333.3-197334.63" + wire width 8 $0\core_core_core_traptype[7:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$14067 + attribute \src "libresoc.v:197291.3-197292.49" + wire width 7 $0\core_core_cr_in1[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in1_ok$next[0:0]$14068 + attribute \src "libresoc.v:197293.3-197294.55" + wire $0\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$14069 + attribute \src "libresoc.v:197299.3-197300.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13712 + attribute \src "libresoc.v:195128.13-195128.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14286 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$14070 + attribute \src "libresoc.v:197295.3-197296.49" + wire width 7 $0\core_core_cr_in2[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$14071 + attribute \src "libresoc.v:197303.3-197304.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13715 + attribute \src "libresoc.v:195136.7-195136.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14289 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in2_ok$next[0:0]$14072 + attribute \src "libresoc.v:197297.3-197298.55" + wire $0\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_out$next[6:0]$14073 + attribute \src "libresoc.v:197305.3-197306.49" + wire width 7 $0\core_core_cr_out[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_wr_ok$next[0:0]$14074 + attribute \src "libresoc.v:197361.3-197362.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_dststep$next[6:0]$13791 + attribute \src "libresoc.v:197227.3-197228.51" + wire width 7 $0\core_core_dststep[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_ea$next[6:0]$14075 + attribute \src "libresoc.v:197243.3-197244.41" + wire width 7 $0\core_core_ea[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fast1$next[2:0]$14076 + attribute \src "libresoc.v:197273.3-197274.47" + wire width 3 $0\core_core_fast1[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_fast1_ok$next[0:0]$14077 + attribute \src "libresoc.v:197275.3-197276.53" + wire $0\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fast2$next[2:0]$14078 + attribute \src "libresoc.v:197277.3-197278.47" + wire width 3 $0\core_core_fast2[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_fast2_ok$next[0:0]$14079 + attribute \src "libresoc.v:197281.3-197282.53" + wire $0\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fasto1$next[2:0]$14080 + attribute \src "libresoc.v:197283.3-197284.49" + wire width 3 $0\core_core_fasto1[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fasto2$next[2:0]$14081 + attribute \src "libresoc.v:197287.3-197288.49" + wire width 3 $0\core_core_fasto2[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_lk$next[0:0]$14082 + attribute \src "libresoc.v:197319.3-197320.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13792 + attribute \src "libresoc.v:197233.3-197234.47" + wire width 7 $0\core_core_maxvl[6:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_core_pc$next[63:0]$13793 + attribute \src "libresoc.v:197205.3-197206.41" + wire width 64 $0\core_core_pc[63:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg1$next[6:0]$14083 + attribute \src "libresoc.v:197247.3-197248.45" + wire width 7 $0\core_core_reg1[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg1_ok$next[0:0]$14084 + attribute \src "libresoc.v:197249.3-197250.51" + wire $0\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg2$next[6:0]$14085 + attribute \src "libresoc.v:197251.3-197252.45" + wire width 7 $0\core_core_reg2[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg2_ok$next[0:0]$14086 + attribute \src "libresoc.v:197253.3-197254.51" + wire $0\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg3$next[6:0]$14087 + attribute \src "libresoc.v:197255.3-197256.45" + wire width 7 $0\core_core_reg3[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg3_ok$next[0:0]$14088 + attribute \src "libresoc.v:197259.3-197260.51" + wire $0\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_rego$next[6:0]$14089 + attribute \src "libresoc.v:197239.3-197240.45" + wire width 7 $0\core_core_rego[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $0\core_core_spr1$next[9:0]$14090 + attribute \src "libresoc.v:197265.3-197266.45" + wire width 10 $0\core_core_spr1[9:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_spr1_ok$next[0:0]$14091 + attribute \src "libresoc.v:197267.3-197268.51" + wire $0\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $0\core_core_spro$next[9:0]$14092 + attribute \src "libresoc.v:197261.3-197262.45" + wire width 10 $0\core_core_spro[9:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13794 + attribute \src "libresoc.v:197229.3-197230.51" + wire width 7 $0\core_core_srcstep[6:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $0\core_core_subvl$next[1:0]$13795 + attribute \src "libresoc.v:197225.3-197226.47" + wire width 2 $0\core_core_subvl[1:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $0\core_core_svstep$next[1:0]$13796 + attribute \src "libresoc.v:197223.3-197224.49" + wire width 2 $0\core_core_svstep[1:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_vl$next[6:0]$13797 + attribute \src "libresoc.v:197231.3-197232.41" + wire width 7 $0\core_core_vl[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_xer_in$next[2:0]$14093 + attribute \src "libresoc.v:197269.3-197270.49" + wire width 3 $0\core_core_xer_in[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_cr_out_ok$next[0:0]$14094 + attribute \src "libresoc.v:197307.3-197308.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:198308.3-198317.6" + wire width 64 $0\core_data_i$12[63:0]$13856 + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $0\core_data_i[63:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_dec$next[63:0]$13798 + attribute \src "libresoc.v:197221.3-197222.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:198421.3-198430.6" + wire width 5 $0\core_dmi__addr[4:0] + attribute \src "libresoc.v:198431.3-198440.6" + wire $0\core_dmi__ren[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_ea_ok$next[0:0]$14095 + attribute \src "libresoc.v:197245.3-197246.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire $0\core_eint$next[0:0]$13799 + attribute \src "libresoc.v:197219.3-197220.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_fasto1_ok$next[0:0]$14096 + attribute \src "libresoc.v:197285.3-197286.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_fasto2_ok$next[0:0]$14097 + attribute \src "libresoc.v:197289.3-197290.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:198470.3-198479.6" + wire width 8 $0\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:198509.3-198518.6" + wire width 3 $0\core_full_rd__ren[2:0] + attribute \src "libresoc.v:198617.3-198631.6" + wire width 3 $0\core_issue__addr$13[2:0]$13896 + attribute \src "libresoc.v:198548.3-198562.6" + wire width 3 $0\core_issue__addr[2:0] + attribute \src "libresoc.v:198647.3-198661.6" + wire width 64 $0\core_issue__data_i[63:0] + attribute \src "libresoc.v:198563.3-198577.6" + wire $0\core_issue__ren[0:0] + attribute \src "libresoc.v:198632.3-198646.6" + wire $0\core_issue__wen[0:0] + attribute \src "libresoc.v:198354.3-198369.6" + wire $0\core_issue_i[0:0] + attribute \src "libresoc.v:198329.3-198353.6" + wire $0\core_ivalid_i[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_msr$next[63:0]$13800 + attribute \src "libresoc.v:197217.3-197218.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:198919.3-198934.6" + wire width 3 $0\core_msr__ren[2:0] + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13832 + attribute \src "libresoc.v:197389.3-197390.47" + wire width 32 $0\core_raw_insn_i[31:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_rego_ok$next[0:0]$14098 + attribute \src "libresoc.v:197241.3-197242.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_spro_ok$next[0:0]$14099 + attribute \src "libresoc.v:197263.3-197264.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:199449.3-199479.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:198761.3-198773.6" + wire width 3 $0\core_sv__ren[2:0] + attribute \src "libresoc.v:198165.3-198189.6" + wire $0\core_sv_a_nz$next[0:0]$13842 + attribute \src "libresoc.v:197345.3-197346.41" + wire $0\core_sv_a_nz[0:0] + attribute \src "libresoc.v:198298.3-198307.6" + wire width 3 $0\core_wen$11[2:0]$13853 + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $0\core_wen[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_xer_out$next[0:0]$14100 + attribute \src "libresoc.v:197271.3-197272.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:197403.3-197404.43" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13937 + attribute \src "libresoc.v:197387.3-197388.47" + wire width 7 $0\cur_cur_dststep[6:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13938 + attribute \src "libresoc.v:197395.3-197396.43" + wire width 7 $0\cur_cur_maxvl[6:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13939 + attribute \src "libresoc.v:197391.3-197392.47" + wire width 7 $0\cur_cur_srcstep[6:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13940 + attribute \src "libresoc.v:197385.3-197386.43" + wire width 2 $0\cur_cur_subvl[1:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13941 + attribute \src "libresoc.v:197383.3-197384.45" + wire width 2 $0\cur_cur_svstep[1:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13942 + attribute \src "libresoc.v:197393.3-197394.37" + wire width 7 $0\cur_cur_vl[6:0] + attribute \src "libresoc.v:198480.3-198488.6" + wire $0\d_cr_delay$next[0:0]$13878 + attribute \src "libresoc.v:197279.3-197280.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:198441.3-198449.6" + wire $0\d_reg_delay$next[0:0]$13872 + attribute \src "libresoc.v:197301.3-197302.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:198519.3-198527.6" + wire $0\d_xer_delay$next[0:0]$13884 + attribute \src "libresoc.v:197257.3-197258.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:199480.3-199510.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:198499.3-198508.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:198489.3-198498.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:198460.3-198469.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:198450.3-198459.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:198538.3-198547.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:198528.3-198537.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:198037.3-198045.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13779 + attribute \src "libresoc.v:197215.3-197216.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:198774.3-198782.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13919 + attribute \src "libresoc.v:197209.3-197210.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:198046.3-198054.6" + wire $0\dbg_dmi_req_i$next[0:0]$13782 + attribute \src "libresoc.v:197213.3-197214.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:198689.3-198697.6" + wire $0\dbg_dmi_we_i$next[0:0]$13906 + attribute \src "libresoc.v:197211.3-197212.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13901 + attribute \src "libresoc.v:197203.3-197204.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:198055.3-198063.6" + wire $0\dec2_cur_eint$next[0:0]$13785 + attribute \src "libresoc.v:197407.3-197408.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13985 + attribute \src "libresoc.v:197377.3-197378.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13932 + attribute \src "libresoc.v:197397.3-197398.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13994 + attribute \src "libresoc.v:197373.3-197374.53" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:198064.3-198073.6" + wire width 2 $0\delay$next[1:0]$13788 + attribute \src "libresoc.v:197405.3-197406.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:198370.3-198404.6" + wire $0\exec_fsm_state$next[0:0]$13862 + attribute \src "libresoc.v:197323.3-197324.45" + wire $0\exec_fsm_state[0:0] + attribute \src "libresoc.v:198318.3-198328.6" + wire $0\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:198250.3-198260.6" + wire $0\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:198261.3-198276.6" + wire $0\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:198405.3-198420.6" + wire $0\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13977 + attribute \src "libresoc.v:197379.3-197380.47" + wire width 2 $0\fetch_fsm_state[1:0] + attribute \src "libresoc.v:199702.3-199712.6" + wire $0\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:199263.3-199273.6" + wire $0\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:198944.3-198954.6" + wire $0\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:199334.3-199349.6" + wire $0\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $0\fsm_state$next[1:0]$13891 + attribute \src "libresoc.v:197235.3-197236.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:198955.3-198970.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:198971.3-199004.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:199005.3-199038.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:194646.7-194646.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:198190.3-198227.6" + wire $0\insn_done[0:0] + attribute \src "libresoc.v:198277.3-198297.6" + wire $0\is_last[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $0\issue_fsm_state$next[2:0]$14002 + attribute \src "libresoc.v:197371.3-197372.47" + wire width 3 $0\issue_fsm_state[2:0] + attribute \src "libresoc.v:198935.3-198943.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13925 + attribute \src "libresoc.v:197207.3-197208.49" + wire $0\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:199099.3-199107.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13968 + attribute \src "libresoc.v:197409.3-197410.47" + wire width 64 $0\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:199108.3-199137.6" + wire $0\msr_read$next[0:0]$13971 + attribute \src "libresoc.v:197381.3-197382.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:198606.3-198616.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $0\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $0\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $0\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $0\new_svstate_subvl[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $0\new_svstate_svstep[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $0\new_svstate_vl[6:0] + attribute \src "libresoc.v:198678.3-198688.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $0\nia$next[63:0]$13990 + attribute \src "libresoc.v:197375.3-197376.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:198707.3-198722.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $0\pc_changed$next[0:0]$14018 + attribute \src "libresoc.v:197369.3-197370.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:198698.3-198706.6" + wire $0\pc_ok_delay$next[0:0]$13909 + attribute \src "libresoc.v:197401.3-197402.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:198228.3-198238.6" + wire $0\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198239.3-198249.6" + wire $0\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199635.3-199701.6" + wire $0\sv_changed$next[0:0]$14030 + attribute \src "libresoc.v:197365.3-197366.37" + wire $0\sv_changed[0:0] + attribute \src "libresoc.v:198745.3-198760.6" + wire width 64 $0\svstate[63:0] + attribute \src "libresoc.v:198736.3-198744.6" + wire $0\svstate_ok_delay$next[0:0]$13914 + attribute \src "libresoc.v:197399.3-197400.49" + wire $0\svstate_ok_delay[0:0] + attribute \src "libresoc.v:199578.3-199634.6" + wire $0\update_svstate[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $10\issue_fsm_state$next[2:0]$14012 + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $11\issue_fsm_state$next[2:0]$14013 + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $12\issue_fsm_state$next[2:0]$14014 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_asmcode$next[7:0]$14101 + attribute \src "libresoc.v:194914.13-194914.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:198140.3-198164.6" + wire $1\core_bigendian_i$10$next[0:0]$13838 + attribute \src "libresoc.v:198723.3-198735.6" + wire width 3 $1\core_cia__ren[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $1\core_core_core_cia$next[63:0]$14102 + attribute \src "libresoc.v:194928.14-194928.55" + wire width 64 $1\core_core_core_cia[63:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$14103 + attribute \src "libresoc.v:194932.13-194932.41" + wire width 8 $1\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$14104 + attribute \src "libresoc.v:194936.7-194936.37" + wire $1\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$14105 + attribute \src "libresoc.v:194940.13-194940.41" + wire width 8 $1\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$14106 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$14107 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$14108 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$14109 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$14110 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$14111 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$14112 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$next[0:0]$14113 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$14114 + attribute \src "libresoc.v:194991.14-194991.47" + wire width 14 $1\core_core_core_fn_unit[13:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$14115 + attribute \src "libresoc.v:194999.13-194999.46" + wire width 2 $1\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $1\core_core_core_insn$next[31:0]$14116 + attribute \src "libresoc.v:195003.14-195003.41" + wire width 32 $1\core_core_core_insn[31:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$14117 + attribute \src "libresoc.v:195082.13-195082.45" + wire width 7 $1\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_is_32bit$next[0:0]$14118 + attribute \src "libresoc.v:195086.7-195086.37" + wire $1\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $1\core_core_core_msr$next[63:0]$14119 + attribute \src "libresoc.v:195090.14-195090.55" + wire width 64 $1\core_core_core_msr[63:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_oe$next[0:0]$14120 + attribute \src "libresoc.v:195094.7-195094.31" + wire $1\core_core_core_oe[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_oe_ok$next[0:0]$14121 + attribute \src "libresoc.v:195098.7-195098.34" + wire $1\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_rc$next[0:0]$14122 + attribute \src "libresoc.v:195102.7-195102.31" + wire $1\core_core_core_rc[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_rc_ok$next[0:0]$14123 + attribute \src "libresoc.v:195106.7-195106.34" + wire $1\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$14124 + attribute \src "libresoc.v:195110.14-195110.48" + wire width 13 $1\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$14125 + attribute \src "libresoc.v:195114.13-195114.44" + wire width 8 $1\core_core_core_traptype[7:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$14126 + attribute \src "libresoc.v:195118.13-195118.37" + wire width 7 $1\core_core_cr_in1[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in1_ok$next[0:0]$14127 + attribute \src "libresoc.v:195122.7-195122.33" + wire $1\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$14128 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$14129 + attribute \src "libresoc.v:195126.13-195126.37" + wire width 7 $1\core_core_cr_in2[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$14130 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in2_ok$next[0:0]$14131 + attribute \src "libresoc.v:195134.7-195134.33" + wire $1\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_out$next[6:0]$14132 + attribute \src "libresoc.v:195142.13-195142.37" + wire width 7 $1\core_core_cr_out[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_wr_ok$next[0:0]$14133 + attribute \src "libresoc.v:195146.7-195146.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_dststep$next[6:0]$13801 + attribute \src "libresoc.v:195150.13-195150.38" + wire width 7 $1\core_core_dststep[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_ea$next[6:0]$14134 + attribute \src "libresoc.v:195154.13-195154.33" + wire width 7 $1\core_core_ea[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fast1$next[2:0]$14135 + attribute \src "libresoc.v:195158.13-195158.35" + wire width 3 $1\core_core_fast1[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_fast1_ok$next[0:0]$14136 + attribute \src "libresoc.v:195162.7-195162.32" + wire $1\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fast2$next[2:0]$14137 + attribute \src "libresoc.v:195166.13-195166.35" + wire width 3 $1\core_core_fast2[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_fast2_ok$next[0:0]$14138 + attribute \src "libresoc.v:195170.7-195170.32" + wire $1\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fasto1$next[2:0]$14139 + attribute \src "libresoc.v:195174.13-195174.36" + wire width 3 $1\core_core_fasto1[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fasto2$next[2:0]$14140 + attribute \src "libresoc.v:195178.13-195178.36" + wire width 3 $1\core_core_fasto2[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_lk$next[0:0]$14141 + attribute \src "libresoc.v:195182.7-195182.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13802 + attribute \src "libresoc.v:195186.13-195186.36" + wire width 7 $1\core_core_maxvl[6:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_core_pc$next[63:0]$13803 + attribute \src "libresoc.v:195190.14-195190.49" + wire width 64 $1\core_core_pc[63:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg1$next[6:0]$14142 + attribute \src "libresoc.v:195194.13-195194.35" + wire width 7 $1\core_core_reg1[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg1_ok$next[0:0]$14143 + attribute \src "libresoc.v:195198.7-195198.31" + wire $1\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg2$next[6:0]$14144 + attribute \src "libresoc.v:195202.13-195202.35" + wire width 7 $1\core_core_reg2[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg2_ok$next[0:0]$14145 + attribute \src "libresoc.v:195206.7-195206.31" + wire $1\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg3$next[6:0]$14146 + attribute \src "libresoc.v:195210.13-195210.35" + wire width 7 $1\core_core_reg3[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg3_ok$next[0:0]$14147 + attribute \src "libresoc.v:195214.7-195214.31" + wire $1\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_rego$next[6:0]$14148 + attribute \src "libresoc.v:195218.13-195218.35" + wire width 7 $1\core_core_rego[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $1\core_core_spr1$next[9:0]$14149 + attribute \src "libresoc.v:195336.13-195336.37" + wire width 10 $1\core_core_spr1[9:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_spr1_ok$next[0:0]$14150 + attribute \src "libresoc.v:195340.7-195340.31" + wire $1\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $1\core_core_spro$next[9:0]$14151 + attribute \src "libresoc.v:195458.13-195458.37" + wire width 10 $1\core_core_spro[9:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13804 + attribute \src "libresoc.v:195462.13-195462.38" + wire width 7 $1\core_core_srcstep[6:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $1\core_core_subvl$next[1:0]$13805 + attribute \src "libresoc.v:195466.13-195466.35" + wire width 2 $1\core_core_subvl[1:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $1\core_core_svstep$next[1:0]$13806 + attribute \src "libresoc.v:195470.13-195470.36" + wire width 2 $1\core_core_svstep[1:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_vl$next[6:0]$13807 + attribute \src "libresoc.v:195476.13-195476.33" + wire width 7 $1\core_core_vl[6:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_xer_in$next[2:0]$14152 + attribute \src "libresoc.v:195480.13-195480.36" + wire width 3 $1\core_core_xer_in[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_cr_out_ok$next[0:0]$14153 + attribute \src "libresoc.v:195488.7-195488.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:198308.3-198317.6" + wire width 64 $1\core_data_i$12[63:0]$13857 + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $1\core_data_i[63:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_dec$next[63:0]$13808 + attribute \src "libresoc.v:195504.14-195504.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:198421.3-198430.6" + wire width 5 $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:198431.3-198440.6" + wire $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_ea_ok$next[0:0]$14154 + attribute \src "libresoc.v:195514.7-195514.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire $1\core_eint$next[0:0]$13809 + attribute \src "libresoc.v:195518.7-195518.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_fasto1_ok$next[0:0]$14155 + attribute \src "libresoc.v:195522.7-195522.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_fasto2_ok$next[0:0]$14156 + attribute \src "libresoc.v:195526.7-195526.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:198470.3-198479.6" + wire width 8 $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:198509.3-198518.6" + wire width 3 $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:198617.3-198631.6" + wire width 3 $1\core_issue__addr$13[2:0]$13897 + attribute \src "libresoc.v:198548.3-198562.6" + wire width 3 $1\core_issue__addr[2:0] + attribute \src "libresoc.v:198647.3-198661.6" + wire width 64 $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:198563.3-198577.6" + wire $1\core_issue__ren[0:0] + attribute \src "libresoc.v:198632.3-198646.6" + wire $1\core_issue__wen[0:0] + attribute \src "libresoc.v:198354.3-198369.6" + wire $1\core_issue_i[0:0] + attribute \src "libresoc.v:198329.3-198353.6" + wire $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_msr$next[63:0]$13810 + attribute \src "libresoc.v:195554.14-195554.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:198919.3-198934.6" + wire width 3 $1\core_msr__ren[2:0] + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13833 + attribute \src "libresoc.v:195562.14-195562.37" + wire width 32 $1\core_raw_insn_i[31:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_rego_ok$next[0:0]$14157 + attribute \src "libresoc.v:195566.7-195566.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_spro_ok$next[0:0]$14158 + attribute \src "libresoc.v:195570.7-195570.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:199449.3-199479.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:198761.3-198773.6" + wire width 3 $1\core_sv__ren[2:0] + attribute \src "libresoc.v:198165.3-198189.6" + wire $1\core_sv_a_nz$next[0:0]$13843 + attribute \src "libresoc.v:195582.7-195582.26" + wire $1\core_sv_a_nz[0:0] + attribute \src "libresoc.v:198298.3-198307.6" + wire width 3 $1\core_wen$11[2:0]$13854 + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $1\core_wen[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_xer_out$next[0:0]$14159 + attribute \src "libresoc.v:195592.7-195592.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:195598.7-195598.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13943 + attribute \src "libresoc.v:195604.13-195604.36" + wire width 7 $1\cur_cur_dststep[6:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13944 + attribute \src "libresoc.v:195608.13-195608.34" + wire width 7 $1\cur_cur_maxvl[6:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13945 + attribute \src "libresoc.v:195612.13-195612.36" + wire width 7 $1\cur_cur_srcstep[6:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13946 + attribute \src "libresoc.v:195616.13-195616.33" + wire width 2 $1\cur_cur_subvl[1:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13947 + attribute \src "libresoc.v:195620.13-195620.34" + wire width 2 $1\cur_cur_svstep[1:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13948 + attribute \src "libresoc.v:195624.13-195624.31" + wire width 7 $1\cur_cur_vl[6:0] + attribute \src "libresoc.v:198480.3-198488.6" + wire $1\d_cr_delay$next[0:0]$13879 + attribute \src "libresoc.v:195628.7-195628.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:198441.3-198449.6" + wire $1\d_reg_delay$next[0:0]$13873 + attribute \src "libresoc.v:195632.7-195632.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:198519.3-198527.6" + wire $1\d_xer_delay$next[0:0]$13885 + attribute \src "libresoc.v:195636.7-195636.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:199480.3-199510.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:198499.3-198508.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:198489.3-198498.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:198460.3-198469.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:198450.3-198459.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:198538.3-198547.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:198528.3-198537.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:198037.3-198045.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13780 + attribute \src "libresoc.v:195684.13-195684.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:198774.3-198782.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13920 + attribute \src "libresoc.v:195688.14-195688.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:198046.3-198054.6" + wire $1\dbg_dmi_req_i$next[0:0]$13783 + attribute \src "libresoc.v:195694.7-195694.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:198689.3-198697.6" + wire $1\dbg_dmi_we_i$next[0:0]$13907 + attribute \src "libresoc.v:195698.7-195698.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13902 + attribute \src "libresoc.v:195752.14-195752.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:198055.3-198063.6" + wire $1\dec2_cur_eint$next[0:0]$13786 + attribute \src "libresoc.v:195756.7-195756.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13986 + attribute \src "libresoc.v:195760.14-195760.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13933 + attribute \src "libresoc.v:195764.14-195764.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13995 + attribute \src "libresoc.v:195916.14-195916.40" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:198064.3-198073.6" + wire width 2 $1\delay$next[1:0]$13789 + attribute \src "libresoc.v:196186.13-196186.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:198370.3-198404.6" + wire $1\exec_fsm_state$next[0:0]$13863 + attribute \src "libresoc.v:196202.7-196202.28" + wire $1\exec_fsm_state[0:0] + attribute \src "libresoc.v:198318.3-198328.6" + wire $1\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:198250.3-198260.6" + wire $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:198261.3-198276.6" + wire $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:198405.3-198420.6" + wire $1\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13978 + attribute \src "libresoc.v:196214.13-196214.35" + wire width 2 $1\fetch_fsm_state[1:0] + attribute \src "libresoc.v:199702.3-199712.6" + wire $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:199263.3-199273.6" + wire $1\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:198944.3-198954.6" + wire $1\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:199334.3-199349.6" + wire $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $1\fsm_state$next[1:0]$13892 + attribute \src "libresoc.v:196226.13-196226.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:198955.3-198970.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:198971.3-199004.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:199005.3-199038.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:198190.3-198227.6" + wire $1\insn_done[0:0] + attribute \src "libresoc.v:198277.3-198297.6" + wire $1\is_last[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $1\issue_fsm_state$next[2:0]$14003 + attribute \src "libresoc.v:196486.13-196486.35" + wire width 3 $1\issue_fsm_state[2:0] + attribute \src "libresoc.v:198935.3-198943.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13926 + attribute \src "libresoc.v:196490.7-196490.30" + wire $1\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:199099.3-199107.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13969 + attribute \src "libresoc.v:196498.14-196498.52" + wire width 64 $1\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:199108.3-199137.6" + wire $1\msr_read$next[0:0]$13972 + attribute \src "libresoc.v:196556.7-196556.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:198606.3-198616.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $1\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $1\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $1\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $1\new_svstate_subvl[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $1\new_svstate_svstep[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $1\new_svstate_vl[6:0] + attribute \src "libresoc.v:198678.3-198688.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $1\nia$next[63:0]$13991 + attribute \src "libresoc.v:196596.14-196596.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:198707.3-198722.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $1\pc_changed$next[0:0]$14019 + attribute \src "libresoc.v:196602.7-196602.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:198698.3-198706.6" + wire $1\pc_ok_delay$next[0:0]$13910 + attribute \src "libresoc.v:196612.7-196612.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:198228.3-198238.6" + wire $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198239.3-198249.6" + wire $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199635.3-199701.6" + wire $1\sv_changed$next[0:0]$14031 + attribute \src "libresoc.v:197056.7-197056.24" + wire $1\sv_changed[0:0] + attribute \src "libresoc.v:198745.3-198760.6" + wire width 64 $1\svstate[63:0] + attribute \src "libresoc.v:198736.3-198744.6" + wire $1\svstate_ok_delay$next[0:0]$13915 + attribute \src "libresoc.v:197066.7-197066.30" + wire $1\svstate_ok_delay[0:0] + attribute \src "libresoc.v:199578.3-199634.6" + wire $1\update_svstate[0:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_asmcode$next[7:0]$14160 + attribute \src "libresoc.v:198140.3-198164.6" + wire $2\core_bigendian_i$10$next[0:0]$13839 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $2\core_core_core_cia$next[63:0]$14161 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$14162 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14163 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14164 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14165 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14166 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14167 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14168 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14169 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14170 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14171 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14172 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$14173 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14174 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14175 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14176 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_is_32bit$next[0:0]$14177 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14178 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_oe$next[0:0]$14179 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_oe_ok$next[0:0]$14180 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_rc$next[0:0]$14181 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_rc_ok$next[0:0]$14182 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14183 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14184 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14185 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14186 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14187 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14188 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14189 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14190 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14191 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14192 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_dststep$next[6:0]$13811 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_ea$next[6:0]$14193 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fast1$next[2:0]$14194 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_fast1_ok$next[0:0]$14195 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fast2$next[2:0]$14196 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_fast2_ok$next[0:0]$14197 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14198 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14199 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_lk$next[0:0]$14200 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13812 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_core_pc$next[63:0]$13813 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg1$next[6:0]$14201 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg1_ok$next[0:0]$14202 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg2$next[6:0]$14203 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg2_ok$next[0:0]$14204 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg3$next[6:0]$14205 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg3_ok$next[0:0]$14206 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_rego$next[6:0]$14207 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $2\core_core_spr1$next[9:0]$14208 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_spr1_ok$next[0:0]$14209 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $2\core_core_spro$next[9:0]$14210 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13814 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $2\core_core_subvl$next[1:0]$13815 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $2\core_core_svstep$next[1:0]$13816 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_vl$next[6:0]$13817 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14211 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_cr_out_ok$next[0:0]$14212 + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $2\core_data_i[63:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_dec$next[63:0]$13818 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_ea_ok$next[0:0]$14213 + attribute \src "libresoc.v:198074.3-198118.6" + wire $2\core_eint$next[0:0]$13819 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_fasto1_ok$next[0:0]$14214 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_fasto2_ok$next[0:0]$14215 + attribute \src "libresoc.v:198354.3-198369.6" + wire $2\core_issue_i[0:0] + attribute \src "libresoc.v:198329.3-198353.6" + wire $2\core_ivalid_i[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_msr$next[63:0]$13820 + attribute \src "libresoc.v:198919.3-198934.6" + wire width 3 $2\core_msr__ren[2:0] + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13834 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_rego_ok$next[0:0]$14216 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_spro_ok$next[0:0]$14217 + attribute \src "libresoc.v:199449.3-199479.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:198165.3-198189.6" + wire $2\core_sv_a_nz$next[0:0]$13844 + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $2\core_wen[2:0] + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_xer_out$next[0:0]$14218 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13949 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13950 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13951 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13952 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13953 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13954 + attribute \src "libresoc.v:199480.3-199510.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13903 + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13987 + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13934 + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13996 + attribute \src "libresoc.v:198370.3-198404.6" + wire $2\exec_fsm_state$next[0:0]$13864 + attribute \src "libresoc.v:198261.3-198276.6" + wire $2\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:198405.3-198420.6" + wire $2\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13979 + attribute \src "libresoc.v:199334.3-199349.6" + wire $2\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $2\fsm_state$next[1:0]$13893 + attribute \src "libresoc.v:198955.3-198970.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:198971.3-199004.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:199005.3-199038.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:198190.3-198227.6" + wire $2\insn_done[0:0] + attribute \src "libresoc.v:198277.3-198297.6" + wire $2\is_last[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $2\issue_fsm_state$next[2:0]$14004 + attribute \src "libresoc.v:199108.3-199137.6" + wire $2\msr_read$next[0:0]$13973 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $2\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $2\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $2\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $2\new_svstate_subvl[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $2\new_svstate_svstep[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $2\new_svstate_vl[6:0] + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $2\nia$next[63:0]$13992 + attribute \src "libresoc.v:198707.3-198722.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $2\pc_changed$next[0:0]$14020 + attribute \src "libresoc.v:199635.3-199701.6" + wire $2\sv_changed$next[0:0]$14032 + attribute \src "libresoc.v:198745.3-198760.6" + wire width 64 $2\svstate[63:0] + attribute \src "libresoc.v:199578.3-199634.6" + wire $2\update_svstate[0:0] + attribute \src "libresoc.v:198140.3-198164.6" + wire $3\core_bigendian_i$10$next[0:0]$13840 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14219 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14220 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14221 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14222 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14223 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14224 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14225 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14226 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14227 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_oe_ok$next[0:0]$14228 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_rc_ok$next[0:0]$14229 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14230 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14231 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14232 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14233 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_dststep$next[6:0]$13821 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_fast1_ok$next[0:0]$14234 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_fast2_ok$next[0:0]$14235 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13822 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_core_pc$next[63:0]$13823 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg1_ok$next[0:0]$14236 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg2_ok$next[0:0]$14237 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg3_ok$next[0:0]$14238 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_spr1_ok$next[0:0]$14239 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13824 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $3\core_core_subvl$next[1:0]$13825 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $3\core_core_svstep$next[1:0]$13826 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_vl$next[6:0]$13827 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_cr_out_ok$next[0:0]$14240 + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $3\core_data_i[63:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_dec$next[63:0]$13828 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_ea_ok$next[0:0]$14241 + attribute \src "libresoc.v:198074.3-198118.6" + wire $3\core_eint$next[0:0]$13829 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_fasto1_ok$next[0:0]$14242 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_fasto2_ok$next[0:0]$14243 + attribute \src "libresoc.v:198329.3-198353.6" + wire $3\core_ivalid_i[0:0] + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_msr$next[63:0]$13830 + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13835 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_rego_ok$next[0:0]$14244 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_spro_ok$next[0:0]$14245 + attribute \src "libresoc.v:199449.3-199479.6" + wire $3\core_stopped_i[0:0] + attribute \src "libresoc.v:198165.3-198189.6" + wire $3\core_sv_a_nz$next[0:0]$13845 + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $3\core_wen[2:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13955 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13956 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13957 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13958 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13959 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13960 + attribute \src "libresoc.v:199480.3-199510.6" + wire $3\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13988 + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13935 + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13997 + attribute \src "libresoc.v:198370.3-198404.6" + wire $3\exec_fsm_state$next[0:0]$13865 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13980 + attribute \src "libresoc.v:198971.3-199004.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "libresoc.v:199005.3-199038.6" + wire $3\imem_f_valid_i[0:0] + attribute \src "libresoc.v:198190.3-198227.6" + wire $3\insn_done[0:0] + attribute \src "libresoc.v:198277.3-198297.6" + wire $3\is_last[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $3\issue_fsm_state$next[2:0]$14005 + attribute \src "libresoc.v:199108.3-199137.6" + wire $3\msr_read$next[0:0]$13974 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $3\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $3\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $3\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $3\new_svstate_subvl[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $3\new_svstate_svstep[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $3\new_svstate_vl[6:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $3\pc_changed$next[0:0]$14021 + attribute \src "libresoc.v:199635.3-199701.6" + wire $3\sv_changed$next[0:0]$14033 + attribute \src "libresoc.v:199578.3-199634.6" + wire $3\update_svstate[0:0] + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $4\core_data_i[63:0] + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $4\core_wen[2:0] + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13961 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13962 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13963 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13964 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13965 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13966 + attribute \src "libresoc.v:198370.3-198404.6" + wire $4\exec_fsm_state$next[0:0]$13866 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13981 + attribute \src "libresoc.v:198971.3-199004.6" + wire $4\imem_a_valid_i[0:0] + attribute \src "libresoc.v:199005.3-199038.6" + wire $4\imem_f_valid_i[0:0] + attribute \src "libresoc.v:198190.3-198227.6" + wire $4\insn_done[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $4\issue_fsm_state$next[2:0]$14006 + attribute \src "libresoc.v:199108.3-199137.6" + wire $4\msr_read$next[0:0]$13975 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $4\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $4\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $4\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $4\new_svstate_subvl[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $4\new_svstate_svstep[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $4\new_svstate_vl[6:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $4\pc_changed$next[0:0]$14022 + attribute \src "libresoc.v:199635.3-199701.6" + wire $4\sv_changed$next[0:0]$14034 + attribute \src "libresoc.v:199578.3-199634.6" + wire $4\update_svstate[0:0] + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $5\core_data_i[63:0] + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $5\core_wen[2:0] + attribute \src "libresoc.v:198370.3-198404.6" + wire $5\exec_fsm_state$next[0:0]$13867 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13982 + attribute \src "libresoc.v:198190.3-198227.6" + wire $5\insn_done[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $5\issue_fsm_state$next[2:0]$14007 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $5\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $5\new_svstate_maxvl[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $5\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $5\new_svstate_subvl[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 2 $5\new_svstate_svstep[1:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $5\new_svstate_vl[6:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $5\pc_changed$next[0:0]$14023 + attribute \src "libresoc.v:199635.3-199701.6" + wire $5\sv_changed$next[0:0]$14035 + attribute \src "libresoc.v:199578.3-199634.6" + wire $5\update_svstate[0:0] + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $6\core_data_i[63:0] + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $6\core_wen[2:0] + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13983 + attribute \src "libresoc.v:198190.3-198227.6" + wire $6\insn_done[0:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $6\issue_fsm_state$next[2:0]$14008 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $6\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $6\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $6\pc_changed$next[0:0]$14024 + attribute \src "libresoc.v:199635.3-199701.6" + wire $6\sv_changed$next[0:0]$14036 + attribute \src "libresoc.v:199578.3-199634.6" + wire $6\update_svstate[0:0] + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $7\core_data_i[63:0] + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $7\core_wen[2:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $7\issue_fsm_state$next[2:0]$14009 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $7\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $7\new_svstate_srcstep[6:0] + attribute \src "libresoc.v:199511.3-199577.6" + wire $7\pc_changed$next[0:0]$14025 + attribute \src "libresoc.v:199635.3-199701.6" + wire $7\sv_changed$next[0:0]$14037 + attribute \src "libresoc.v:199578.3-199634.6" + wire $7\update_svstate[0:0] + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $8\core_data_i[63:0] + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $8\core_wen[2:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $8\issue_fsm_state$next[2:0]$14010 + attribute \src "libresoc.v:199511.3-199577.6" + wire $8\pc_changed$next[0:0]$14026 + attribute \src "libresoc.v:199635.3-199701.6" + wire $8\sv_changed$next[0:0]$14038 + attribute \src "libresoc.v:198851.3-198918.6" + wire width 64 $9\core_data_i[63:0] + attribute \src "libresoc.v:198783.3-198850.6" + wire width 3 $9\core_wen[2:0] + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $9\issue_fsm_state$next[2:0]$14011 + attribute \src "libresoc.v:199511.3-199577.6" + wire $9\pc_changed$next[0:0]$14027 + attribute \src "libresoc.v:199635.3-199701.6" + wire $9\sv_changed$next[0:0]$14039 + attribute \src "libresoc.v:197083.19-197083.108" + wire width 65 $add$libresoc.v:197083$13545_Y + attribute \src "libresoc.v:197095.19-197095.112" + wire width 8 $add$libresoc.v:197095$13556_Y + attribute \src "libresoc.v:197096.19-197096.112" + wire width 8 $add$libresoc.v:197096$13557_Y + attribute \src "libresoc.v:197166.19-197166.116" + wire width 65 $add$libresoc.v:197166$13627_Y + attribute \src "libresoc.v:197200.18-197200.107" + wire width 65 $add$libresoc.v:197200$13660_Y + attribute \src "libresoc.v:197088.19-197088.104" + wire $and$libresoc.v:197088$13550_Y + attribute \src "libresoc.v:197091.19-197091.104" + wire $and$libresoc.v:197091$13553_Y + attribute \src "libresoc.v:197099.19-197099.104" + wire $and$libresoc.v:197099$13560_Y + attribute \src "libresoc.v:197102.19-197102.104" + wire $and$libresoc.v:197102$13563_Y + attribute \src "libresoc.v:197104.19-197104.111" + wire $and$libresoc.v:197104$13565_Y + attribute \src "libresoc.v:197107.19-197107.104" + wire $and$libresoc.v:197107$13568_Y + attribute \src "libresoc.v:197113.19-197113.104" + wire $and$libresoc.v:197113$13573_Y + attribute \src "libresoc.v:197116.19-197116.104" + wire $and$libresoc.v:197116$13576_Y + attribute \src "libresoc.v:197119.19-197119.104" + wire $and$libresoc.v:197119$13579_Y + attribute \src "libresoc.v:197122.19-197122.104" + wire $and$libresoc.v:197122$13582_Y + attribute \src "libresoc.v:197125.19-197125.104" + wire $and$libresoc.v:197125$13585_Y + attribute \src "libresoc.v:197128.19-197128.104" + wire $and$libresoc.v:197128$13588_Y + attribute \src "libresoc.v:197129.19-197129.115" + wire width 3 $and$libresoc.v:197129$13589_Y + attribute \src "libresoc.v:197133.19-197133.104" + wire $and$libresoc.v:197133$13593_Y + attribute \src "libresoc.v:197136.19-197136.104" + wire $and$libresoc.v:197136$13596_Y + attribute \src "libresoc.v:197142.19-197142.104" + wire $and$libresoc.v:197142$13601_Y + attribute \src "libresoc.v:197145.19-197145.104" + wire $and$libresoc.v:197145$13604_Y + attribute \src "libresoc.v:197146.19-197146.115" + wire width 3 $and$libresoc.v:197146$13605_Y + attribute \src "libresoc.v:197149.19-197149.111" + wire $and$libresoc.v:197149$13608_Y + attribute \src "libresoc.v:197154.19-197154.104" + wire $and$libresoc.v:197154$13613_Y + attribute \src "libresoc.v:197157.19-197157.104" + wire $and$libresoc.v:197157$13616_Y + attribute \src "libresoc.v:197172.18-197172.109" + wire $and$libresoc.v:197172$13633_Y + attribute \src "libresoc.v:197178.18-197178.101" + wire $and$libresoc.v:197178$13640_Y + attribute \src "libresoc.v:197180.18-197180.109" + wire $and$libresoc.v:197180$13642_Y + attribute \src "libresoc.v:197183.18-197183.101" + wire $and$libresoc.v:197183$13645_Y + attribute \src "libresoc.v:197189.18-197189.101" + wire $and$libresoc.v:197189$13650_Y + attribute \src "libresoc.v:197191.18-197191.109" + wire $and$libresoc.v:197191$13652_Y + attribute \src "libresoc.v:197194.18-197194.101" + wire $and$libresoc.v:197194$13655_Y + attribute \src "libresoc.v:197103.19-197103.108" + wire $eq$libresoc.v:197103$13564_Y + attribute \src "libresoc.v:197148.19-197148.108" + wire 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"reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + wire \dec2_sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + wire \exec_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + wire \exec_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" + wire \exec_insn_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879" + wire \exec_insn_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" + wire \exec_pc_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883" + wire \exec_pc_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + wire width 2 \fetch_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + wire width 2 \fetch_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" + wire \fetch_insn_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" + wire \fetch_insn_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" + wire \fetch_pc_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:863" + wire \fetch_pc_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 18 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 23 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 17 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 22 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 19 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 21 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 20 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 372 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 378 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 373 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 374 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 375 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 379 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 376 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 377 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 385 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 380 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 382 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 384 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 386 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 383 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 387 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \imem_wb_icache_en + attribute \src "libresoc.v:194646.7-194646.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \insn_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 381 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" + wire \is_last + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" + wire \is_svp64_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + wire width 3 \issue_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + wire width 3 \issue_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \jtag_dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 336 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 330 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 332 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 337 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 335 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 331 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 333 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 334 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \jtag_wb_sram_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:999" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \new_svstate_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \new_svstate_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \new_svstate_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \new_svstate_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \new_svstate_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \new_svstate_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" + wire width 7 \next_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:505" + wire width 7 \next_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 7 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 6 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + wire width 64 output 5 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" + wire \pred_insn_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" + wire \pred_insn_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" + wire \pred_mask_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" + wire \pred_mask_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 168 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 169 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 167 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 323 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 324 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 174 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 175 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 173 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 327 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 328 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_0_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 342 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 343 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 340 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 344 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 345 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 347 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 341 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 346 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_1_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 350 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 351 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 348 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 352 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 353 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 355 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 349 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 354 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_2_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 358 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 359 \sram4k_2_wb__adr + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:197159$13618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + connect \Y $pos$libresoc.v:197159$13618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:197163$13623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:197163$13622_Y + connect \Y $pos$libresoc.v:197163$13623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:197164$13625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:197164$13624_Y + connect \Y $pos$libresoc.v:197164$13625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:197175$13637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:197175$13636_Y + connect \Y $pos$libresoc.v:197175$13637_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:197130$13590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$195 + connect \Y $reduce_or$libresoc.v:197130$13590_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:197147$13606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$229 + connect \Y $reduce_or$libresoc.v:197147$13606_Y + end + attribute \src "libresoc.v:197085.18-197085.41" + cell $shr $shr$libresoc.v:197085$13547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$103 + connect \Y $shr$libresoc.v:197085$13547_Y + end + attribute \src "libresoc.v:197202.18-197202.40" + cell $shr $shr$libresoc.v:197202$13662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$96 + connect \Y $shr$libresoc.v:197202$13662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + cell $sub $sub$libresoc.v:197165$13626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:197165$13626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + cell $sub $sub$libresoc.v:197167$13628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:197167$13628_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197411.8-197509.4" + cell \core \core + connect \bigendian_i \core_bigendian_i$10 + connect \cia__data_o \core_cia__data_o + connect \cia__ren \core_cia__ren + connect \core_core_cia \core_core_core_cia + connect \core_core_cr_rd \core_core_core_cr_rd + connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok + connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_exc_$signal \core_core_core_exc_$signal + connect \core_core_exc_$signal$3 \core_core_core_exc_$signal$3 + connect \core_core_exc_$signal$4 \core_core_core_exc_$signal$4 + connect \core_core_exc_$signal$5 \core_core_core_exc_$signal$5 + connect \core_core_exc_$signal$6 \core_core_core_exc_$signal$6 + connect \core_core_exc_$signal$7 \core_core_core_exc_$signal$7 + connect \core_core_exc_$signal$8 \core_core_core_exc_$signal$8 + connect \core_core_exc_$signal$9 \core_core_core_exc_$signal$9 + connect \core_core_fn_unit \core_core_core_fn_unit + connect \core_core_input_carry \core_core_core_input_carry + connect \core_core_insn \core_core_core_insn + connect \core_core_insn_type \core_core_core_insn_type + connect \core_core_is_32bit \core_core_core_is_32bit + connect \core_core_msr \core_core_core_msr + connect \core_core_oe \core_core_core_oe + connect \core_core_oe_ok \core_core_core_oe_ok + connect \core_core_rc \core_core_core_rc + connect \core_core_rc_ok \core_core_core_rc_ok + connect \core_core_trapaddr \core_core_core_trapaddr + connect \core_core_traptype \core_core_core_traptype + connect \core_cr_in1 \core_core_cr_in1 + connect \core_cr_in1_ok \core_core_cr_in1_ok + connect \core_cr_in2 \core_core_cr_in2 + connect \core_cr_in2$1 \core_core_cr_in2$1 + connect \core_cr_in2_ok \core_core_cr_in2_ok + connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 + connect \core_cr_out \core_core_cr_out + connect \core_ea \core_core_ea + connect \core_fast1 \core_core_fast1 + connect \core_fast1_ok \core_core_fast1_ok + connect \core_fast2 \core_core_fast2 + connect \core_fast2_ok \core_core_fast2_ok + connect \core_fasto1 \core_core_fasto1 + connect \core_fasto2 \core_core_fasto2 + connect \core_pc \core_core_pc + connect \core_reg1 \core_core_reg1 + connect \core_reg1_ok \core_core_reg1_ok + connect \core_reg2 \core_core_reg2 + connect \core_reg2_ok \core_core_reg2_ok + connect \core_reg3 \core_core_reg3 + connect \core_reg3_ok \core_core_reg3_ok + connect \core_rego \core_core_rego + connect \core_spr1 \core_core_spr1 + connect \core_spr1_ok \core_core_spr1_ok + connect \core_spro \core_core_spro + connect \core_terminate_o \core_core_terminate_o + connect \core_xer_in \core_core_xer_in + connect \corebusy_o \core_corebusy_o + connect \coresync_clk \coresync_clk + connect \coresync_rst \core_coresync_rst + connect \cu_ad__go_i \core_cu_ad__go_i + connect \cu_ad__rel_o \core_cu_ad__rel_o + connect \cu_st__go_i \core_cu_st__go_i + connect \cu_st__rel_o \core_cu_st__rel_o + connect \data_i \core_data_i + connect \data_i$11 \core_data_i$12 + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \dmi__addr \core_dmi__addr + connect \dmi__data_o \core_dmi__data_o + connect \dmi__ren \core_dmi__ren + connect \full_rd2__data_o \core_full_rd2__data_o + connect \full_rd2__ren \core_full_rd2__ren + connect \full_rd__data_o \core_full_rd__data_o + connect \full_rd__ren \core_full_rd__ren + connect \issue__addr \core_issue__addr + connect \issue__addr$12 \core_issue__addr$13 + connect \issue__data_i \core_issue__data_i + connect \issue__data_o \core_issue__data_o + connect \issue__ren \core_issue__ren + connect \issue__wen \core_issue__wen + connect \issue_i \core_issue_i + connect \ivalid_i \core_ivalid_i + connect \msr__data_o \core_msr__data_o + connect \msr__ren \core_msr__ren + connect \raw_insn_i \core_raw_insn_i + connect \state_nia_wen \core_state_nia_wen + connect \sv__data_o \core_sv__data_o + connect \sv__ren \core_sv__ren + connect \sv_a_nz \core_sv_a_nz + connect \wb_dcache_en \core_wb_dcache_en + connect \wen \core_wen + connect \wen$10 \core_wen$11 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197510.7-197541.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep + connect \core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_maxvl + connect \core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_srcstep + connect \core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_subvl + connect \core_dbg_core_dbg_svstep \dbg_core_dbg_core_dbg_svstep + connect \core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_vl + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197542.8-197609.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$14 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$15 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \exc_$signal \dec2_exc_$signal + connect \exc_$signal$3 \dec2_exc_$signal$16 + connect \exc_$signal$4 \dec2_exc_$signal$17 + connect \exc_$signal$5 \dec2_exc_$signal$18 + connect \exc_$signal$6 \dec2_exc_$signal$19 + connect \exc_$signal$7 \dec2_exc_$signal$20 + connect \exc_$signal$8 \dec2_exc_$signal$21 + connect \exc_$signal$9 \dec2_exc_$signal$22 + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \sv_a_nz \dec2_sv_a_nz + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197610.8-197626.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197627.8-197955.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0__ack_o \jtag_dmi0__ack_o + connect \dmi0__addr_i \jtag_dmi0__addr_i + connect \dmi0__din \jtag_dmi0__din + connect \dmi0__dout \jtag_dmi0__dout + connect \dmi0__req_i \jtag_dmi0__req_i + connect \dmi0__we_i \jtag_dmi0__we_i + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \wb_dcache_en \core_wb_dcache_en + connect \wb_icache_en \imem_wb_icache_en + connect \wb_sram_en \jtag_wb_sram_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197956.12-197968.4" + cell \sram4k_0 \sram4k_0 + connect \clk \clk + connect \enable \sram4k_0_enable + connect \rst \rst + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197969.12-197981.4" + cell \sram4k_1 \sram4k_1 + connect \clk \clk + connect \enable \sram4k_1_enable + connect \rst \rst + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197982.12-197994.4" + cell \sram4k_2 \sram4k_2 + connect \clk \clk + connect \enable \sram4k_2_enable + connect \rst \rst + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197995.12-198007.4" + cell \sram4k_3 \sram4k_3 + connect \clk \clk + connect \enable \sram4k_3_enable + connect \rst \rst + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:198008.12-198022.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:198023.12-198036.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst + end + attribute \src "libresoc.v:194646.7-194646.20" + process $proc$libresoc.v:194646$14246 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:194914.13-194914.33" + process $proc$libresoc.v:194914$14247 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:194920.7-194920.35" + process $proc$libresoc.v:194920$14248 + assign { } { } + assign $0\core_bigendian_i$10[0:0]$14249 1'0 + sync always + sync init + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14249 + end + attribute \src "libresoc.v:194928.14-194928.55" + process $proc$libresoc.v:194928$14250 + assign { } { } + assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_cia $1\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:194932.13-194932.41" + process $proc$libresoc.v:194932$14251 + assign { } { } + assign $1\core_core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:194936.7-194936.37" + process $proc$libresoc.v:194936$14252 + assign { } { } + assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:194940.13-194940.41" + process $proc$libresoc.v:194940$14253 + assign { } { } + assign $1\core_core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:194944.7-194944.42" + process $proc$libresoc.v:194944$14254 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$14255 1'0 + sync always + sync init + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14255 + end + attribute \src "libresoc.v:194946.7-194946.44" + process $proc$libresoc.v:194946$14256 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$14257 1'0 + sync always + sync init + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14257 + end + attribute \src "libresoc.v:194950.7-194950.44" + process $proc$libresoc.v:194950$14258 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$14259 1'0 + sync always + sync init + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14259 + end + attribute \src "libresoc.v:194954.7-194954.44" + process $proc$libresoc.v:194954$14260 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$14261 1'0 + sync always + sync init + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14261 + end + attribute \src "libresoc.v:194958.7-194958.44" + process $proc$libresoc.v:194958$14262 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$14263 1'0 + sync always + sync init + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14263 + end + attribute \src "libresoc.v:194962.7-194962.44" + process $proc$libresoc.v:194962$14264 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$14265 1'0 + sync always + sync init + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14265 + end + attribute \src "libresoc.v:194966.7-194966.44" + process $proc$libresoc.v:194966$14266 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$14267 1'0 + sync always + sync init + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14267 + end + attribute \src "libresoc.v:194970.7-194970.44" + process $proc$libresoc.v:194970$14268 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$14269 1'0 + sync always + sync init + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14269 + end + attribute \src "libresoc.v:194991.14-194991.47" + process $proc$libresoc.v:194991$14270 + assign { } { } + assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] + end + attribute \src "libresoc.v:194999.13-194999.46" + process $proc$libresoc.v:194999$14271 + assign { } { } + assign $1\core_core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:195003.14-195003.41" + process $proc$libresoc.v:195003$14272 + assign { } { } + assign $1\core_core_core_insn[31:0] 0 + sync always + sync init + update \core_core_core_insn $1\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:195082.13-195082.45" + process $proc$libresoc.v:195082$14273 + assign { } { } + assign $1\core_core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:195086.7-195086.37" + process $proc$libresoc.v:195086$14274 + assign { } { } + assign $1\core_core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:195090.14-195090.55" + process $proc$libresoc.v:195090$14275 + assign { } { } + assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_msr $1\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:195094.7-195094.31" + process $proc$libresoc.v:195094$14276 + assign { } { } + assign $1\core_core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_core_oe $1\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:195098.7-195098.34" + process $proc$libresoc.v:195098$14277 + assign { } { } + assign $1\core_core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:195102.7-195102.31" + process $proc$libresoc.v:195102$14278 + assign { } { } + assign $1\core_core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_core_rc $1\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:195106.7-195106.34" + process $proc$libresoc.v:195106$14279 + assign { } { } + assign $1\core_core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:195110.14-195110.48" + process $proc$libresoc.v:195110$14280 + assign { } { } + assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:195114.13-195114.44" + process $proc$libresoc.v:195114$14281 + assign { } { } + assign $1\core_core_core_traptype[7:0] 8'00000000 + sync always + sync init + update \core_core_core_traptype $1\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:195118.13-195118.37" + process $proc$libresoc.v:195118$14282 + assign { } { } + assign $1\core_core_cr_in1[6:0] 7'0000000 + sync always + sync init + update \core_core_cr_in1 $1\core_core_cr_in1[6:0] + end + attribute \src "libresoc.v:195122.7-195122.33" + process $proc$libresoc.v:195122$14283 + assign { } { } + assign $1\core_core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:195126.13-195126.37" + process $proc$libresoc.v:195126$14284 + assign { } { } + assign $1\core_core_cr_in2[6:0] 7'0000000 + sync always + sync init + update \core_core_cr_in2 $1\core_core_cr_in2[6:0] + end + attribute \src "libresoc.v:195128.13-195128.41" + process $proc$libresoc.v:195128$14285 + assign { } { } + assign $0\core_core_cr_in2$1[6:0]$14286 7'0000000 + sync always + sync init + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14286 + end + attribute \src "libresoc.v:195134.7-195134.33" + process $proc$libresoc.v:195134$14287 + assign { } { } + assign $1\core_core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:195136.7-195136.37" + process $proc$libresoc.v:195136$14288 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$14289 1'0 + sync always + sync init + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14289 + end + attribute \src "libresoc.v:195142.13-195142.37" + process $proc$libresoc.v:195142$14290 + assign { } { } + assign $1\core_core_cr_out[6:0] 7'0000000 + sync always + sync init + update \core_core_cr_out $1\core_core_cr_out[6:0] + end + attribute \src "libresoc.v:195146.7-195146.32" + process $proc$libresoc.v:195146$14291 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:195150.13-195150.38" + process $proc$libresoc.v:195150$14292 + assign { } { } + assign $1\core_core_dststep[6:0] 7'0000000 + sync always + sync init + update \core_core_dststep $1\core_core_dststep[6:0] + end + attribute \src "libresoc.v:195154.13-195154.33" + process $proc$libresoc.v:195154$14293 + assign { } { } + assign $1\core_core_ea[6:0] 7'0000000 + sync always + sync init + update \core_core_ea $1\core_core_ea[6:0] + end + attribute \src "libresoc.v:195158.13-195158.35" + process $proc$libresoc.v:195158$14294 + assign { } { } + assign $1\core_core_fast1[2:0] 3'000 + sync always + sync init + update \core_core_fast1 $1\core_core_fast1[2:0] + end + attribute \src "libresoc.v:195162.7-195162.32" + process $proc$libresoc.v:195162$14295 + assign { } { } + assign $1\core_core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:195166.13-195166.35" + process $proc$libresoc.v:195166$14296 + assign { } { } + assign $1\core_core_fast2[2:0] 3'000 + sync always + sync init + update \core_core_fast2 $1\core_core_fast2[2:0] + end + attribute \src "libresoc.v:195170.7-195170.32" + process $proc$libresoc.v:195170$14297 + assign { } { } + assign $1\core_core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:195174.13-195174.36" + process $proc$libresoc.v:195174$14298 + assign { } { } + assign $1\core_core_fasto1[2:0] 3'000 + sync always + sync init + update \core_core_fasto1 $1\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:195178.13-195178.36" + process $proc$libresoc.v:195178$14299 + assign { } { } + assign $1\core_core_fasto2[2:0] 3'000 + sync always + sync init + update \core_core_fasto2 $1\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:195182.7-195182.26" + process $proc$libresoc.v:195182$14300 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] + end + attribute \src "libresoc.v:195186.13-195186.36" + process $proc$libresoc.v:195186$14301 + assign { } { } + assign $1\core_core_maxvl[6:0] 7'0000000 + sync always + sync init + update \core_core_maxvl $1\core_core_maxvl[6:0] + end + attribute \src "libresoc.v:195190.14-195190.49" + process $proc$libresoc.v:195190$14302 + assign { } { } + assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_pc $1\core_core_pc[63:0] + end + attribute \src "libresoc.v:195194.13-195194.35" + process $proc$libresoc.v:195194$14303 + assign { } { } + assign $1\core_core_reg1[6:0] 7'0000000 + sync always + sync init + update \core_core_reg1 $1\core_core_reg1[6:0] + end + attribute \src "libresoc.v:195198.7-195198.31" + process $proc$libresoc.v:195198$14304 + assign { } { } + assign $1\core_core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:195202.13-195202.35" + process $proc$libresoc.v:195202$14305 + assign { } { } + assign $1\core_core_reg2[6:0] 7'0000000 + sync always + sync init + update \core_core_reg2 $1\core_core_reg2[6:0] + end + attribute \src "libresoc.v:195206.7-195206.31" + process $proc$libresoc.v:195206$14306 + assign { } { } + assign $1\core_core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:195210.13-195210.35" + process $proc$libresoc.v:195210$14307 + assign { } { } + assign $1\core_core_reg3[6:0] 7'0000000 + sync always + sync init + update \core_core_reg3 $1\core_core_reg3[6:0] + end + attribute \src "libresoc.v:195214.7-195214.31" + process $proc$libresoc.v:195214$14308 + assign { } { } + assign $1\core_core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:195218.13-195218.35" + process $proc$libresoc.v:195218$14309 + assign { } { } + assign $1\core_core_rego[6:0] 7'0000000 + sync always + sync init + update \core_core_rego $1\core_core_rego[6:0] + end + attribute \src "libresoc.v:195336.13-195336.37" + process $proc$libresoc.v:195336$14310 + assign { } { } + assign $1\core_core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_core_spr1 $1\core_core_spr1[9:0] + end + attribute \src "libresoc.v:195340.7-195340.31" + process $proc$libresoc.v:195340$14311 + assign { } { } + assign $1\core_core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:195458.13-195458.37" + process $proc$libresoc.v:195458$14312 + assign { } { } + assign $1\core_core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_core_spro $1\core_core_spro[9:0] + end + attribute \src "libresoc.v:195462.13-195462.38" + process $proc$libresoc.v:195462$14313 + assign { } { } + assign $1\core_core_srcstep[6:0] 7'0000000 + sync always + sync init + update \core_core_srcstep $1\core_core_srcstep[6:0] + end + attribute \src "libresoc.v:195466.13-195466.35" + process $proc$libresoc.v:195466$14314 + assign { } { } + assign $1\core_core_subvl[1:0] 2'00 + sync always + sync init + update \core_core_subvl $1\core_core_subvl[1:0] + end + attribute \src "libresoc.v:195470.13-195470.36" + process $proc$libresoc.v:195470$14315 + assign { } { } + assign $1\core_core_svstep[1:0] 2'00 + sync always + sync init + update \core_core_svstep $1\core_core_svstep[1:0] + end + attribute \src "libresoc.v:195476.13-195476.33" + process $proc$libresoc.v:195476$14316 + assign { } { } + assign $1\core_core_vl[6:0] 7'0000000 + sync always + sync init + update \core_core_vl $1\core_core_vl[6:0] + end + attribute \src "libresoc.v:195480.13-195480.36" + process $proc$libresoc.v:195480$14317 + assign { } { } + assign $1\core_core_xer_in[2:0] 3'000 + sync always + sync init + update \core_core_xer_in $1\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:195488.7-195488.28" + process $proc$libresoc.v:195488$14318 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:195504.14-195504.45" + process $proc$libresoc.v:195504$14319 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] + end + attribute \src "libresoc.v:195514.7-195514.24" + process $proc$libresoc.v:195514$14320 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] + end + attribute \src "libresoc.v:195518.7-195518.23" + process $proc$libresoc.v:195518$14321 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] + end + attribute \src "libresoc.v:195522.7-195522.28" + process $proc$libresoc.v:195522$14322 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:195526.7-195526.28" + process $proc$libresoc.v:195526$14323 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:195554.14-195554.45" + process $proc$libresoc.v:195554$14324 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] + end + attribute \src "libresoc.v:195562.14-195562.37" + process $proc$libresoc.v:195562$14325 + assign { } { } + assign $1\core_raw_insn_i[31:0] 0 + sync always + sync init + update \core_raw_insn_i $1\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:195566.7-195566.26" + process $proc$libresoc.v:195566$14326 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] + end + attribute \src "libresoc.v:195570.7-195570.26" + process $proc$libresoc.v:195570$14327 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] + end + attribute \src "libresoc.v:195582.7-195582.26" + process $proc$libresoc.v:195582$14328 + assign { } { } + assign $1\core_sv_a_nz[0:0] 1'0 + sync always + sync init + update \core_sv_a_nz $1\core_sv_a_nz[0:0] + end + attribute \src "libresoc.v:195592.7-195592.26" + process $proc$libresoc.v:195592$14329 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] + end + attribute \src "libresoc.v:195598.7-195598.30" + process $proc$libresoc.v:195598$14330 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:195604.13-195604.36" + process $proc$libresoc.v:195604$14331 + assign { } { } + assign $1\cur_cur_dststep[6:0] 7'0000000 + sync always + sync init + update \cur_cur_dststep $1\cur_cur_dststep[6:0] + end + attribute \src "libresoc.v:195608.13-195608.34" + process $proc$libresoc.v:195608$14332 + assign { } { } + assign $1\cur_cur_maxvl[6:0] 7'0000000 + sync always + sync init + update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] + end + attribute \src "libresoc.v:195612.13-195612.36" + process $proc$libresoc.v:195612$14333 + assign { } { } + assign $1\cur_cur_srcstep[6:0] 7'0000000 + sync always + sync init + update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] + end + attribute \src "libresoc.v:195616.13-195616.33" + process $proc$libresoc.v:195616$14334 + assign { } { } + assign $1\cur_cur_subvl[1:0] 2'00 + sync always + sync init + update \cur_cur_subvl $1\cur_cur_subvl[1:0] + end + attribute \src "libresoc.v:195620.13-195620.34" + process $proc$libresoc.v:195620$14335 + assign { } { } + assign $1\cur_cur_svstep[1:0] 2'00 + sync always + sync init + update \cur_cur_svstep $1\cur_cur_svstep[1:0] + end + attribute \src "libresoc.v:195624.13-195624.31" + process $proc$libresoc.v:195624$14336 + assign { } { } + assign $1\cur_cur_vl[6:0] 7'0000000 + sync always + sync init + update \cur_cur_vl $1\cur_cur_vl[6:0] + end + attribute \src "libresoc.v:195628.7-195628.24" + process $proc$libresoc.v:195628$14337 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] + end + attribute \src "libresoc.v:195632.7-195632.25" + process $proc$libresoc.v:195632$14338 + assign { } { } + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] + end + attribute \src "libresoc.v:195636.7-195636.25" + process $proc$libresoc.v:195636$14339 + assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "libresoc.v:195684.13-195684.34" + process $proc$libresoc.v:195684$14340 + assign { } { } + assign $1\dbg_dmi_addr_i[3:0] 4'0000 + sync always + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:195688.14-195688.48" + process $proc$libresoc.v:195688$14341 + assign { } { } + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:195694.7-195694.27" + process $proc$libresoc.v:195694$14342 + assign { } { } + assign $1\dbg_dmi_req_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:195698.7-195698.26" + process $proc$libresoc.v:195698$14343 + assign { } { } + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:195752.14-195752.49" + process $proc$libresoc.v:195752$14344 + assign { } { } + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:195756.7-195756.27" + process $proc$libresoc.v:195756$14345 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:195760.14-195760.49" + process $proc$libresoc.v:195760$14346 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:195764.14-195764.48" + process $proc$libresoc.v:195764$14347 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:195916.14-195916.40" + process $proc$libresoc.v:195916$14348 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] 0 + sync always + sync init + update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:196186.13-196186.25" + process $proc$libresoc.v:196186$14349 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "libresoc.v:196202.7-196202.28" + process $proc$libresoc.v:196202$14350 + assign { } { } + assign $1\exec_fsm_state[0:0] 1'0 + sync always + sync init + update \exec_fsm_state $1\exec_fsm_state[0:0] + end + attribute \src "libresoc.v:196214.13-196214.35" + process $proc$libresoc.v:196214$14351 + assign { } { } + assign $1\fetch_fsm_state[1:0] 2'00 + sync always + sync init + update \fetch_fsm_state $1\fetch_fsm_state[1:0] + end + attribute \src "libresoc.v:196226.13-196226.29" + process $proc$libresoc.v:196226$14352 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:196486.13-196486.35" + process $proc$libresoc.v:196486$14353 + assign { } { } + assign $1\issue_fsm_state[2:0] 3'000 + sync always + sync init + update \issue_fsm_state $1\issue_fsm_state[2:0] + end + attribute \src "libresoc.v:196490.7-196490.30" + process $proc$libresoc.v:196490$14354 + assign { } { } + assign $1\jtag_dmi0__ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:196498.14-196498.52" + process $proc$libresoc.v:196498$14355 + assign { } { } + assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:196556.7-196556.22" + process $proc$libresoc.v:196556$14356 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:196596.14-196596.40" + process $proc$libresoc.v:196596$14357 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:196602.7-196602.24" + process $proc$libresoc.v:196602$14358 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "libresoc.v:196612.7-196612.25" + process $proc$libresoc.v:196612$14359 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:197056.7-197056.24" + process $proc$libresoc.v:197056$14360 + assign { } { } + assign $1\sv_changed[0:0] 1'0 + sync always + sync init + update \sv_changed $1\sv_changed[0:0] + end + attribute \src "libresoc.v:197066.7-197066.30" + process $proc$libresoc.v:197066$14361 + assign { } { } + assign $1\svstate_ok_delay[0:0] 1'0 + sync always + sync init + update \svstate_ok_delay $1\svstate_ok_delay[0:0] + end + attribute \src "libresoc.v:197203.3-197204.41" + process $proc$libresoc.v:197203$13663 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:197205.3-197206.41" + process $proc$libresoc.v:197205$13664 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:197207.3-197208.49" + process $proc$libresoc.v:197207$13665 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:197209.3-197210.39" + process $proc$libresoc.v:197209$13666 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:197211.3-197212.41" + process $proc$libresoc.v:197211$13667 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:197213.3-197214.43" + process $proc$libresoc.v:197213$13668 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:197215.3-197216.45" + process $proc$libresoc.v:197215$13669 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:197217.3-197218.33" + process $proc$libresoc.v:197217$13670 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:197219.3-197220.35" + process $proc$libresoc.v:197219$13671 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:197221.3-197222.33" + process $proc$libresoc.v:197221$13672 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "libresoc.v:197223.3-197224.49" + process $proc$libresoc.v:197223$13673 + assign { } { } + assign $0\core_core_svstep[1:0] \core_core_svstep$next + sync posedge \clk + update \core_core_svstep $0\core_core_svstep[1:0] + end + attribute \src "libresoc.v:197225.3-197226.47" + process $proc$libresoc.v:197225$13674 + assign { } { } + assign $0\core_core_subvl[1:0] \core_core_subvl$next + sync posedge \clk + update \core_core_subvl $0\core_core_subvl[1:0] + end + attribute \src "libresoc.v:197227.3-197228.51" + process $proc$libresoc.v:197227$13675 + assign { } { } + assign $0\core_core_dststep[6:0] \core_core_dststep$next + sync posedge \clk + update \core_core_dststep $0\core_core_dststep[6:0] + end + attribute \src "libresoc.v:197229.3-197230.51" + process $proc$libresoc.v:197229$13676 + assign { } { } + assign $0\core_core_srcstep[6:0] \core_core_srcstep$next + sync posedge \clk + update \core_core_srcstep $0\core_core_srcstep[6:0] + end + attribute \src "libresoc.v:197231.3-197232.41" + process $proc$libresoc.v:197231$13677 + assign { } { } + assign $0\core_core_vl[6:0] \core_core_vl$next + sync posedge \clk + update \core_core_vl $0\core_core_vl[6:0] + end + attribute \src "libresoc.v:197233.3-197234.47" + process $proc$libresoc.v:197233$13678 + assign { } { } + assign $0\core_core_maxvl[6:0] \core_core_maxvl$next + sync posedge \clk + update \core_core_maxvl $0\core_core_maxvl[6:0] + end + attribute \src "libresoc.v:197235.3-197236.35" + process $proc$libresoc.v:197235$13679 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:197237.3-197238.41" + process $proc$libresoc.v:197237$13680 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:197239.3-197240.45" + process $proc$libresoc.v:197239$13681 + assign { } { } + assign $0\core_core_rego[6:0] \core_core_rego$next + sync posedge \clk + update \core_core_rego $0\core_core_rego[6:0] + end + attribute \src "libresoc.v:197241.3-197242.41" + process $proc$libresoc.v:197241$13682 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:197243.3-197244.41" + process $proc$libresoc.v:197243$13683 + assign { } { } + assign $0\core_core_ea[6:0] \core_core_ea$next + sync posedge \clk + update \core_core_ea $0\core_core_ea[6:0] + end + attribute \src "libresoc.v:197245.3-197246.37" + process $proc$libresoc.v:197245$13684 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "libresoc.v:197247.3-197248.45" + process $proc$libresoc.v:197247$13685 + assign { } { } + assign $0\core_core_reg1[6:0] \core_core_reg1$next + sync posedge \clk + update \core_core_reg1 $0\core_core_reg1[6:0] + end + attribute \src "libresoc.v:197249.3-197250.51" + process $proc$libresoc.v:197249$13686 + assign { } { } + assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next + sync posedge \clk + update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:197251.3-197252.45" + process $proc$libresoc.v:197251$13687 + assign { } { } + assign $0\core_core_reg2[6:0] \core_core_reg2$next + sync posedge \clk + update \core_core_reg2 $0\core_core_reg2[6:0] + end + attribute \src "libresoc.v:197253.3-197254.51" + process $proc$libresoc.v:197253$13688 + assign { } { } + assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next + sync posedge \clk + update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:197255.3-197256.45" + process $proc$libresoc.v:197255$13689 + assign { } { } + assign $0\core_core_reg3[6:0] \core_core_reg3$next + sync posedge \clk + update \core_core_reg3 $0\core_core_reg3[6:0] + end + attribute \src "libresoc.v:197257.3-197258.39" + process $proc$libresoc.v:197257$13690 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:197259.3-197260.51" + process $proc$libresoc.v:197259$13691 + assign { } { } + assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next + sync posedge \clk + update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:197261.3-197262.45" + process $proc$libresoc.v:197261$13692 + assign { } { } + assign $0\core_core_spro[9:0] \core_core_spro$next + sync posedge \clk + update \core_core_spro $0\core_core_spro[9:0] + end + attribute \src "libresoc.v:197263.3-197264.41" + process $proc$libresoc.v:197263$13693 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:197265.3-197266.45" + process $proc$libresoc.v:197265$13694 + assign { } { } + assign $0\core_core_spr1[9:0] \core_core_spr1$next + sync posedge \clk + update \core_core_spr1 $0\core_core_spr1[9:0] + end + attribute \src "libresoc.v:197267.3-197268.51" + process $proc$libresoc.v:197267$13695 + assign { } { } + assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next + sync posedge \clk + update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:197269.3-197270.49" + process $proc$libresoc.v:197269$13696 + assign { } { } + assign $0\core_core_xer_in[2:0] \core_core_xer_in$next + sync posedge \clk + update \core_core_xer_in $0\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:197271.3-197272.41" + process $proc$libresoc.v:197271$13697 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:197273.3-197274.47" + process $proc$libresoc.v:197273$13698 + assign { } { } + assign $0\core_core_fast1[2:0] \core_core_fast1$next + sync posedge \clk + update \core_core_fast1 $0\core_core_fast1[2:0] + end + attribute \src "libresoc.v:197275.3-197276.53" + process $proc$libresoc.v:197275$13699 + assign { } { } + assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next + sync posedge \clk + update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:197277.3-197278.47" + process $proc$libresoc.v:197277$13700 + assign { } { } + assign $0\core_core_fast2[2:0] \core_core_fast2$next + sync posedge \clk + update \core_core_fast2 $0\core_core_fast2[2:0] + end + attribute \src "libresoc.v:197279.3-197280.37" + process $proc$libresoc.v:197279$13701 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:197281.3-197282.53" + process $proc$libresoc.v:197281$13702 + assign { } { } + assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next + sync posedge \clk + update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:197283.3-197284.49" + process $proc$libresoc.v:197283$13703 + assign { } { } + assign $0\core_core_fasto1[2:0] \core_core_fasto1$next + sync posedge \clk + update \core_core_fasto1 $0\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:197285.3-197286.45" + process $proc$libresoc.v:197285$13704 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:197287.3-197288.49" + process $proc$libresoc.v:197287$13705 + assign { } { } + assign $0\core_core_fasto2[2:0] \core_core_fasto2$next + sync posedge \clk + update \core_core_fasto2 $0\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:197289.3-197290.45" + process $proc$libresoc.v:197289$13706 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:197291.3-197292.49" + process $proc$libresoc.v:197291$13707 + assign { } { } + assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next + sync posedge \clk + update \core_core_cr_in1 $0\core_core_cr_in1[6:0] + end + attribute \src "libresoc.v:197293.3-197294.55" + process $proc$libresoc.v:197293$13708 + assign { } { } + assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next + sync posedge \clk + update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:197295.3-197296.49" + process $proc$libresoc.v:197295$13709 + assign { } { } + assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next + sync posedge \clk + update \core_core_cr_in2 $0\core_core_cr_in2[6:0] + end + attribute \src "libresoc.v:197297.3-197298.55" + process $proc$libresoc.v:197297$13710 + assign { } { } + assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next + sync posedge \clk + update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:197299.3-197300.55" + process $proc$libresoc.v:197299$13711 + assign { } { } + assign $0\core_core_cr_in2$1[6:0]$13712 \core_core_cr_in2$1$next + sync posedge \clk + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13712 + end + attribute \src "libresoc.v:197301.3-197302.39" + process $proc$libresoc.v:197301$13713 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:197303.3-197304.61" + process $proc$libresoc.v:197303$13714 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$13715 \core_core_cr_in2_ok$2$next + sync posedge \clk + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13715 + end + attribute \src "libresoc.v:197305.3-197306.49" + process $proc$libresoc.v:197305$13716 + assign { } { } + assign $0\core_core_cr_out[6:0] \core_core_cr_out$next + sync posedge \clk + update \core_core_cr_out $0\core_core_cr_out[6:0] + end + attribute \src "libresoc.v:197307.3-197308.45" + process $proc$libresoc.v:197307$13717 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:197309.3-197310.53" + process $proc$libresoc.v:197309$13718 + assign { } { } + assign $0\core_core_core_msr[63:0] \core_core_core_msr$next + sync posedge \clk + update \core_core_core_msr $0\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:197311.3-197312.53" + process $proc$libresoc.v:197311$13719 + assign { } { } + assign $0\core_core_core_cia[63:0] \core_core_core_cia$next + sync posedge \clk + update \core_core_core_cia $0\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:197313.3-197314.55" + process $proc$libresoc.v:197313$13720 + assign { } { } + assign $0\core_core_core_insn[31:0] \core_core_core_insn$next + sync posedge \clk + update \core_core_core_insn $0\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:197315.3-197316.65" + process $proc$libresoc.v:197315$13721 + assign { } { } + assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next + sync posedge \clk + update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:197317.3-197318.61" + process $proc$libresoc.v:197317$13722 + assign { } { } + assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next + sync posedge \clk + update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] + end + attribute \src "libresoc.v:197319.3-197320.41" + process $proc$libresoc.v:197319$13723 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:197321.3-197322.51" + process $proc$libresoc.v:197321$13724 + assign { } { } + assign $0\core_core_core_rc[0:0] \core_core_core_rc$next + sync posedge \clk + update \core_core_core_rc $0\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:197323.3-197324.45" + process $proc$libresoc.v:197323$13725 + assign { } { } + assign $0\exec_fsm_state[0:0] \exec_fsm_state$next + sync posedge \clk + update \exec_fsm_state $0\exec_fsm_state[0:0] + end + attribute \src "libresoc.v:197325.3-197326.57" + process $proc$libresoc.v:197325$13726 + assign { } { } + assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next + sync posedge \clk + update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:197327.3-197328.51" + process $proc$libresoc.v:197327$13727 + assign { } { } + assign $0\core_core_core_oe[0:0] \core_core_core_oe$next + sync posedge \clk + update \core_core_core_oe $0\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:197329.3-197330.57" + process $proc$libresoc.v:197329$13728 + assign { } { } + assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next + sync posedge \clk + update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:197331.3-197332.69" + process $proc$libresoc.v:197331$13729 + assign { } { } + assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next + sync posedge \clk + update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:197333.3-197334.63" + process $proc$libresoc.v:197333$13730 + assign { } { } + assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next + sync posedge \clk + update \core_core_core_traptype $0\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:197335.3-197336.71" + process $proc$libresoc.v:197335$13731 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$13732 \core_core_core_exc_$signal$next + sync posedge \clk + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13732 + end + attribute \src "libresoc.v:197337.3-197338.75" + process $proc$libresoc.v:197337$13733 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$13734 \core_core_core_exc_$signal$3$next + sync posedge \clk + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13734 + end + attribute \src "libresoc.v:197339.3-197340.75" + process $proc$libresoc.v:197339$13735 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$13736 \core_core_core_exc_$signal$4$next + sync posedge \clk + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13736 + end + attribute \src "libresoc.v:197341.3-197342.75" + process $proc$libresoc.v:197341$13737 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$13738 \core_core_core_exc_$signal$5$next + sync posedge \clk + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13738 + end + attribute \src "libresoc.v:197343.3-197344.75" + process $proc$libresoc.v:197343$13739 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$13740 \core_core_core_exc_$signal$6$next + sync posedge \clk + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13740 + end + attribute \src "libresoc.v:197345.3-197346.41" + process $proc$libresoc.v:197345$13741 + assign { } { } + assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next + sync posedge \clk + update \core_sv_a_nz $0\core_sv_a_nz[0:0] + end + attribute \src "libresoc.v:197347.3-197348.75" + process $proc$libresoc.v:197347$13742 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$13743 \core_core_core_exc_$signal$7$next + sync posedge \clk + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13743 + end + attribute \src "libresoc.v:197349.3-197350.75" + process $proc$libresoc.v:197349$13744 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$13745 \core_core_core_exc_$signal$8$next + sync posedge \clk + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13745 + end + attribute \src "libresoc.v:197351.3-197352.75" + process $proc$libresoc.v:197351$13746 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$13747 \core_core_core_exc_$signal$9$next + sync posedge \clk + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13747 + end + attribute \src "libresoc.v:197353.3-197354.63" + process $proc$libresoc.v:197353$13748 + assign { } { } + assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next + sync posedge \clk + update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:197355.3-197356.57" + process $proc$libresoc.v:197355$13749 + assign { } { } + assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next + sync posedge \clk + update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:197357.3-197358.63" + process $proc$libresoc.v:197357$13750 + assign { } { } + assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:197359.3-197360.57" + process $proc$libresoc.v:197359$13751 + assign { } { } + assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next + sync posedge \clk + update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:197361.3-197362.53" + process $proc$libresoc.v:197361$13752 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:197363.3-197364.63" + process $proc$libresoc.v:197363$13753 + assign { } { } + assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next + sync posedge \clk + update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:197365.3-197366.37" + process $proc$libresoc.v:197365$13754 + assign { } { } + assign $0\sv_changed[0:0] \sv_changed$next + sync posedge \clk + update \sv_changed $0\sv_changed[0:0] + end + attribute \src "libresoc.v:197367.3-197368.57" + process $proc$libresoc.v:197367$13755 + assign { } { } + assign $0\core_bigendian_i$10[0:0]$13756 \core_bigendian_i$10$next + sync posedge \clk + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13756 + end + attribute \src "libresoc.v:197369.3-197370.37" + process $proc$libresoc.v:197369$13757 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:197371.3-197372.47" + process $proc$libresoc.v:197371$13758 + assign { } { } + assign $0\issue_fsm_state[2:0] \issue_fsm_state$next + sync posedge \clk + update \issue_fsm_state $0\issue_fsm_state[2:0] + end + attribute \src "libresoc.v:197373.3-197374.53" + process $proc$libresoc.v:197373$13759 + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next + sync posedge \clk + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:197375.3-197376.23" + process $proc$libresoc.v:197375$13760 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:197377.3-197378.41" + process $proc$libresoc.v:197377$13761 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:197379.3-197380.47" + process $proc$libresoc.v:197379$13762 + assign { } { } + assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next + sync posedge \clk + update \fetch_fsm_state $0\fetch_fsm_state[1:0] + end + attribute \src "libresoc.v:197381.3-197382.33" + process $proc$libresoc.v:197381$13763 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:197383.3-197384.45" + process $proc$libresoc.v:197383$13764 + assign { } { } + assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next + sync posedge \clk + update \cur_cur_svstep $0\cur_cur_svstep[1:0] + end + attribute \src "libresoc.v:197385.3-197386.43" + process $proc$libresoc.v:197385$13765 + assign { } { } + assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next + sync posedge \clk + update \cur_cur_subvl $0\cur_cur_subvl[1:0] + end + attribute \src "libresoc.v:197387.3-197388.47" + process $proc$libresoc.v:197387$13766 + assign { } { } + assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next + sync posedge \clk + update \cur_cur_dststep $0\cur_cur_dststep[6:0] + end + attribute \src "libresoc.v:197389.3-197390.47" + process $proc$libresoc.v:197389$13767 + assign { } { } + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + sync posedge \clk + update \core_raw_insn_i $0\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:197391.3-197392.47" + process $proc$libresoc.v:197391$13768 + assign { } { } + assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next + sync posedge \clk + update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] + end + attribute \src "libresoc.v:197393.3-197394.37" + process $proc$libresoc.v:197393$13769 + assign { } { } + assign $0\cur_cur_vl[6:0] \cur_cur_vl$next + sync posedge \clk + update \cur_cur_vl $0\cur_cur_vl[6:0] + end + attribute \src "libresoc.v:197395.3-197396.43" + process $proc$libresoc.v:197395$13770 + assign { } { } + assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next + sync posedge \clk + update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] + end + attribute \src "libresoc.v:197397.3-197398.39" + process $proc$libresoc.v:197397$13771 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:197399.3-197400.49" + process $proc$libresoc.v:197399$13772 + assign { } { } + assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next + sync posedge \clk + update \svstate_ok_delay $0\svstate_ok_delay[0:0] + end + attribute \src "libresoc.v:197401.3-197402.39" + process $proc$libresoc.v:197401$13773 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:197403.3-197404.43" + process $proc$libresoc.v:197403$13774 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:197405.3-197406.27" + process $proc$libresoc.v:197405$13775 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:197407.3-197408.43" + process $proc$libresoc.v:197407$13776 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:197409.3-197410.47" + process $proc$libresoc.v:197409$13777 + assign { } { } + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + sync posedge \clk + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:198037.3-198045.6" + process $proc$libresoc.v:198037$13778 + assign { } { } + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$13779 $1\dbg_dmi_addr_i$next[3:0]$13780 + attribute \src "libresoc.v:198038.5-198038.29" + switch \initial + attribute \src "libresoc.v:198038.9-198038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$13780 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$13780 \jtag_dmi0__addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13779 + end + attribute \src "libresoc.v:198046.3-198054.6" + process $proc$libresoc.v:198046$13781 + assign { } { } + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$13782 $1\dbg_dmi_req_i$next[0:0]$13783 + attribute \src "libresoc.v:198047.5-198047.29" + switch \initial + attribute \src "libresoc.v:198047.9-198047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$13783 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$13783 \jtag_dmi0__req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13782 + end + attribute \src "libresoc.v:198055.3-198063.6" + process $proc$libresoc.v:198055$13784 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$13785 $1\dec2_cur_eint$next[0:0]$13786 + attribute \src "libresoc.v:198056.5-198056.29" + switch \initial + attribute \src "libresoc.v:198056.9-198056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$13786 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$13786 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13785 + end + attribute \src "libresoc.v:198064.3-198073.6" + process $proc$libresoc.v:198064$13787 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$13788 $1\delay$next[1:0]$13789 + attribute \src "libresoc.v:198065.5-198065.29" + switch \initial + attribute \src "libresoc.v:198065.9-198065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13789 \$25 [1:0] + case + assign $1\delay$next[1:0]$13789 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$13788 + end + attribute \src "libresoc.v:198074.3-198118.6" + process $proc$libresoc.v:198074$13790 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_dststep$next[6:0]$13791 $3\core_core_dststep$next[6:0]$13821 + assign $0\core_core_maxvl$next[6:0]$13792 $3\core_core_maxvl$next[6:0]$13822 + assign $0\core_core_pc$next[63:0]$13793 $3\core_core_pc$next[63:0]$13823 + assign $0\core_core_srcstep$next[6:0]$13794 $3\core_core_srcstep$next[6:0]$13824 + assign $0\core_core_subvl$next[1:0]$13795 $3\core_core_subvl$next[1:0]$13825 + assign $0\core_core_svstep$next[1:0]$13796 $3\core_core_svstep$next[1:0]$13826 + assign $0\core_core_vl$next[6:0]$13797 $3\core_core_vl$next[6:0]$13827 + assign $0\core_dec$next[63:0]$13798 $3\core_dec$next[63:0]$13828 + assign $0\core_eint$next[0:0]$13799 $3\core_eint$next[0:0]$13829 + assign $0\core_msr$next[63:0]$13800 $3\core_msr$next[63:0]$13830 + attribute \src "libresoc.v:198075.5-198075.29" + switch \initial + attribute \src "libresoc.v:198075.9-198075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_core_dststep$next[6:0]$13801 $2\core_core_dststep$next[6:0]$13811 + assign $1\core_core_maxvl$next[6:0]$13802 $2\core_core_maxvl$next[6:0]$13812 + assign $1\core_core_pc$next[63:0]$13803 $2\core_core_pc$next[63:0]$13813 + assign $1\core_core_srcstep$next[6:0]$13804 $2\core_core_srcstep$next[6:0]$13814 + assign $1\core_core_subvl$next[1:0]$13805 $2\core_core_subvl$next[1:0]$13815 + assign $1\core_core_svstep$next[1:0]$13806 $2\core_core_svstep$next[1:0]$13816 + assign $1\core_core_vl$next[6:0]$13807 $2\core_core_vl$next[6:0]$13817 + assign $1\core_dec$next[63:0]$13808 $2\core_dec$next[63:0]$13818 + assign $1\core_eint$next[0:0]$13809 $2\core_eint$next[0:0]$13819 + assign $1\core_msr$next[63:0]$13810 $2\core_msr$next[63:0]$13820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_maxvl$next[6:0]$13812 $2\core_core_vl$next[6:0]$13817 $2\core_core_srcstep$next[6:0]$13814 $2\core_core_dststep$next[6:0]$13811 $2\core_core_subvl$next[1:0]$13815 $2\core_core_svstep$next[1:0]$13816 $2\core_dec$next[63:0]$13818 $2\core_eint$next[0:0]$13819 $2\core_msr$next[63:0]$13820 $2\core_core_pc$next[63:0]$13813 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + case + assign $2\core_core_dststep$next[6:0]$13811 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13812 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13813 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13814 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13815 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13816 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13817 \core_core_vl + assign $2\core_dec$next[63:0]$13818 \core_dec + assign $2\core_eint$next[0:0]$13819 \core_eint + assign $2\core_msr$next[63:0]$13820 \core_msr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_maxvl$next[6:0]$13802 $1\core_core_vl$next[6:0]$13807 $1\core_core_srcstep$next[6:0]$13804 $1\core_core_dststep$next[6:0]$13801 $1\core_core_subvl$next[1:0]$13805 $1\core_core_svstep$next[1:0]$13806 $1\core_dec$next[63:0]$13808 $1\core_eint$next[0:0]$13809 $1\core_msr$next[63:0]$13810 $1\core_core_pc$next[63:0]$13803 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + case + assign $1\core_core_dststep$next[6:0]$13801 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13802 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13803 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13804 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13805 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13806 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13807 \core_core_vl + assign $1\core_dec$next[63:0]$13808 \core_dec + assign $1\core_eint$next[0:0]$13809 \core_eint + assign $1\core_msr$next[63:0]$13810 \core_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_core_pc$next[63:0]$13823 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13830 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13829 1'0 + assign $3\core_dec$next[63:0]$13828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13826 2'00 + assign $3\core_core_subvl$next[1:0]$13825 2'00 + assign $3\core_core_dststep$next[6:0]$13821 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13824 7'0000000 + assign $3\core_core_vl$next[6:0]$13827 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13822 7'0000000 + case + assign $3\core_core_dststep$next[6:0]$13821 $1\core_core_dststep$next[6:0]$13801 + assign $3\core_core_maxvl$next[6:0]$13822 $1\core_core_maxvl$next[6:0]$13802 + assign $3\core_core_pc$next[63:0]$13823 $1\core_core_pc$next[63:0]$13803 + assign $3\core_core_srcstep$next[6:0]$13824 $1\core_core_srcstep$next[6:0]$13804 + assign $3\core_core_subvl$next[1:0]$13825 $1\core_core_subvl$next[1:0]$13805 + assign $3\core_core_svstep$next[1:0]$13826 $1\core_core_svstep$next[1:0]$13806 + assign $3\core_core_vl$next[6:0]$13827 $1\core_core_vl$next[6:0]$13807 + assign $3\core_dec$next[63:0]$13828 $1\core_dec$next[63:0]$13808 + assign $3\core_eint$next[0:0]$13829 $1\core_eint$next[0:0]$13809 + assign $3\core_msr$next[63:0]$13830 $1\core_msr$next[63:0]$13810 + end + sync always + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13791 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13792 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13793 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13794 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13795 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13796 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13797 + update \core_dec$next $0\core_dec$next[63:0]$13798 + update \core_eint$next $0\core_eint$next[0:0]$13799 + update \core_msr$next $0\core_msr$next[63:0]$13800 + end + attribute \src "libresoc.v:198119.3-198139.6" + process $proc$libresoc.v:198119$13831 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$13832 $3\core_raw_insn_i$next[31:0]$13835 + attribute \src "libresoc.v:198120.5-198120.29" + switch \initial + attribute \src "libresoc.v:198120.9-198120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13833 $2\core_raw_insn_i$next[31:0]$13834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$13834 \dec2_raw_opcode_in + case + assign $2\core_raw_insn_i$next[31:0]$13834 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$13833 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$13835 0 + case + assign $3\core_raw_insn_i$next[31:0]$13835 $1\core_raw_insn_i$next[31:0]$13833 + end + sync always + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13832 + end + attribute \src "libresoc.v:198140.3-198164.6" + process $proc$libresoc.v:198140$13836 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_bigendian_i$10$next[0:0]$13837 $3\core_bigendian_i$10$next[0:0]$13840 + attribute \src "libresoc.v:198141.5-198141.29" + switch \initial + attribute \src "libresoc.v:198141.9-198141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13838 $2\core_bigendian_i$10$next[0:0]$13839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i + case + assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i$10 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i + case + assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_bigendian_i$10$next[0:0]$13840 1'0 + case + assign $3\core_bigendian_i$10$next[0:0]$13840 $1\core_bigendian_i$10$next[0:0]$13838 + end + sync always + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13837 + end + attribute \src "libresoc.v:198165.3-198189.6" + process $proc$libresoc.v:198165$13841 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_sv_a_nz$next[0:0]$13842 $3\core_sv_a_nz$next[0:0]$13845 + attribute \src "libresoc.v:198166.5-198166.29" + switch \initial + attribute \src "libresoc.v:198166.9-198166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_sv_a_nz$next[0:0]$13843 $2\core_sv_a_nz$next[0:0]$13844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_sv_a_nz$next[0:0]$13844 \dec2_sv_a_nz + case + assign $2\core_sv_a_nz$next[0:0]$13844 \core_sv_a_nz + end + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\core_sv_a_nz$next[0:0]$13843 \dec2_sv_a_nz + case + assign $1\core_sv_a_nz$next[0:0]$13843 \core_sv_a_nz + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_sv_a_nz$next[0:0]$13845 1'0 + case + assign $3\core_sv_a_nz$next[0:0]$13845 $1\core_sv_a_nz$next[0:0]$13843 + end + sync always + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13842 + end + attribute \src "libresoc.v:198190.3-198227.6" + process $proc$libresoc.v:198190$13846 + assign { } { } + assign { } { } + assign { } { } + assign $0\insn_done[0:0] $4\insn_done[0:0] + attribute \src "libresoc.v:198191.5-198191.29" + switch \initial + attribute \src "libresoc.v:198191.9-198191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\insn_done[0:0] $2\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\insn_done[0:0] $3\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$234 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\insn_done[0:0] 1'1 + case + assign $3\insn_done[0:0] 1'0 + end + case + assign $2\insn_done[0:0] 1'0 + end + case + assign $1\insn_done[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\insn_done[0:0] $5\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$236 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\insn_done[0:0] $6\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\insn_done[0:0] 1'1 + case + assign $6\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $5\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $4\insn_done[0:0] $1\insn_done[0:0] + end + sync always + update \insn_done $0\insn_done[0:0] + end + attribute \src "libresoc.v:198228.3-198238.6" + process $proc$libresoc.v:198228$13847 + assign { } { } + assign { } { } + assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198229.5-198229.29" + switch \initial + attribute \src "libresoc.v:198229.9-198229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\pred_insn_valid_i[0:0] 1'1 + case + assign $1\pred_insn_valid_i[0:0] 1'0 + end + sync always + update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] + end + attribute \src "libresoc.v:198239.3-198249.6" + process $proc$libresoc.v:198239$13848 + assign { } { } + assign { } { } + assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:198240.5-198240.29" + switch \initial + attribute \src "libresoc.v:198240.9-198240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\pred_mask_ready_i[0:0] 1'1 + case + assign $1\pred_mask_ready_i[0:0] 1'0 + end + sync always + update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] + end + attribute \src "libresoc.v:198250.3-198260.6" + process $proc$libresoc.v:198250$13849 + assign { } { } + assign { } { } + assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:198251.5-198251.29" + switch \initial + attribute \src "libresoc.v:198251.9-198251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\exec_insn_valid_i[0:0] 1'1 + case + assign $1\exec_insn_valid_i[0:0] 1'0 + end + sync always + update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + end + attribute \src "libresoc.v:198261.3-198276.6" + process $proc$libresoc.v:198261$13850 + assign { } { } + assign { } { } + assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:198262.5-198262.29" + switch \initial + attribute \src "libresoc.v:198262.9-198262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$242 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\exec_pc_ready_i[0:0] 1'1 + case + assign $2\exec_pc_ready_i[0:0] 1'0 + end + case + assign $1\exec_pc_ready_i[0:0] 1'0 + end + sync always + update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] + end + attribute \src "libresoc.v:198277.3-198297.6" + process $proc$libresoc.v:198277$13851 + assign { } { } + assign { } { } + assign $0\is_last[0:0] $1\is_last[0:0] + attribute \src "libresoc.v:198278.5-198278.29" + switch \initial + attribute \src "libresoc.v:198278.9-198278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\is_last[0:0] $2\is_last[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$248 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_last[0:0] $3\is_last[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\is_last[0:0] \$250 + case + assign $3\is_last[0:0] 1'0 + end + case + assign $2\is_last[0:0] 1'0 + end + case + assign $1\is_last[0:0] 1'0 + end + sync always + update \is_last $0\is_last[0:0] + end + attribute \src "libresoc.v:198298.3-198307.6" + process $proc$libresoc.v:198298$13852 + assign { } { } + assign { } { } + assign $0\core_wen$11[2:0]$13853 $1\core_wen$11[2:0]$13854 + attribute \src "libresoc.v:198299.5-198299.29" + switch \initial + attribute \src "libresoc.v:198299.9-198299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_wen$11[2:0]$13854 3'100 + case + assign $1\core_wen$11[2:0]$13854 3'000 + end + sync always + update \core_wen$11 $0\core_wen$11[2:0]$13853 + end + attribute \src "libresoc.v:198308.3-198317.6" + process $proc$libresoc.v:198308$13855 + assign { } { } + assign { } { } + assign $0\core_data_i$12[63:0]$13856 $1\core_data_i$12[63:0]$13857 + attribute \src "libresoc.v:198309.5-198309.29" + switch \initial + attribute \src "libresoc.v:198309.9-198309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_data_i$12[63:0]$13857 \$252 + case + assign $1\core_data_i$12[63:0]$13857 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i$12 $0\core_data_i$12[63:0]$13856 + end + attribute \src "libresoc.v:198318.3-198328.6" + process $proc$libresoc.v:198318$13858 + assign { } { } + assign { } { } + assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:198319.5-198319.29" + switch \initial + attribute \src "libresoc.v:198319.9-198319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $1\exec_insn_ready_o[0:0] 1'1 + case + assign $1\exec_insn_ready_o[0:0] 1'0 + end + sync always + update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] + end + attribute \src "libresoc.v:198329.3-198353.6" + process $proc$libresoc.v:198329$13859 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:198330.5-198330.29" + switch \initial + attribute \src "libresoc.v:198330.9-198330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + switch \$254 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_ivalid_i[0:0] 1'1 + case + assign $3\core_ivalid_i[0:0] 1'0 + end + case + assign $1\core_ivalid_i[0:0] 1'0 + end + sync always + update \core_ivalid_i $0\core_ivalid_i[0:0] + end + attribute \src "libresoc.v:198354.3-198369.6" + process $proc$libresoc.v:198354$13860 + assign { } { } + assign { } { } + assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] + attribute \src "libresoc.v:198355.5-198355.29" + switch \initial + attribute \src "libresoc.v:198355.9-198355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_issue_i[0:0] 1'1 + case + assign $2\core_issue_i[0:0] 1'0 + end + case + assign $1\core_issue_i[0:0] 1'0 + end + sync always + update \core_issue_i $0\core_issue_i[0:0] + end + attribute \src "libresoc.v:198370.3-198404.6" + process $proc$libresoc.v:198370$13861 + assign { } { } + assign { } { } + assign { } { } + assign $0\exec_fsm_state$next[0:0]$13862 $5\exec_fsm_state$next[0:0]$13867 + attribute \src "libresoc.v:198371.5-198371.29" + switch \initial + attribute \src "libresoc.v:198371.9-198371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $1\exec_fsm_state$next[0:0]$13863 $2\exec_fsm_state$next[0:0]$13864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\exec_fsm_state$next[0:0]$13864 1'1 + case + assign $2\exec_fsm_state$next[0:0]$13864 \exec_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\exec_fsm_state$next[0:0]$13863 $3\exec_fsm_state$next[0:0]$13865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$256 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\exec_fsm_state$next[0:0]$13865 $4\exec_fsm_state$next[0:0]$13866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\exec_fsm_state$next[0:0]$13866 1'0 + case + assign $4\exec_fsm_state$next[0:0]$13866 \exec_fsm_state + end + case + assign $3\exec_fsm_state$next[0:0]$13865 \exec_fsm_state + end + case + assign $1\exec_fsm_state$next[0:0]$13863 \exec_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\exec_fsm_state$next[0:0]$13867 1'0 + case + assign $5\exec_fsm_state$next[0:0]$13867 $1\exec_fsm_state$next[0:0]$13863 + end + sync always + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13862 + end + attribute \src "libresoc.v:198405.3-198420.6" + process $proc$libresoc.v:198405$13868 + assign { } { } + assign { } { } + assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:198406.5-198406.29" + switch \initial + attribute \src "libresoc.v:198406.9-198406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$258 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\exec_pc_valid_o[0:0] 1'1 + case + assign $2\exec_pc_valid_o[0:0] 1'0 + end + case + assign $1\exec_pc_valid_o[0:0] 1'0 + end + sync always + update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] + end + attribute \src "libresoc.v:198421.3-198430.6" + process $proc$libresoc.v:198421$13869 + assign { } { } + assign { } { } + assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:198422.5-198422.29" + switch \initial + attribute \src "libresoc.v:198422.9-198422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\core_dmi__addr[4:0] 5'00000 + end + sync always + update \core_dmi__addr $0\core_dmi__addr[4:0] + end + attribute \src "libresoc.v:198431.3-198440.6" + process $proc$libresoc.v:198431$13870 + assign { } { } + assign { } { } + assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:198432.5-198432.29" + switch \initial + attribute \src "libresoc.v:198432.9-198432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__ren[0:0] 1'1 + case + assign $1\core_dmi__ren[0:0] 1'0 + end + sync always + update \core_dmi__ren $0\core_dmi__ren[0:0] + end + attribute \src "libresoc.v:198441.3-198449.6" + process $proc$libresoc.v:198441$13871 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$13872 $1\d_reg_delay$next[0:0]$13873 + attribute \src "libresoc.v:198442.5-198442.29" + switch \initial + attribute \src "libresoc.v:198442.9-198442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$13873 1'0 + case + assign $1\d_reg_delay$next[0:0]$13873 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13872 + end + attribute \src "libresoc.v:198450.3-198459.6" + process $proc$libresoc.v:198450$13874 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:198451.5-198451.29" + switch \initial + attribute \src "libresoc.v:198451.9-198451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:198460.3-198469.6" + process $proc$libresoc.v:198460$13875 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:198461.5-198461.29" + switch \initial + attribute \src "libresoc.v:198461.9-198461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:198470.3-198479.6" + process $proc$libresoc.v:198470$13876 + assign { } { } + assign { } { } + assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:198471.5-198471.29" + switch \initial + attribute \src "libresoc.v:198471.9-198471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd2__ren[7:0] 8'11111111 + case + assign $1\core_full_rd2__ren[7:0] 8'00000000 + end + sync always + update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + end + attribute \src "libresoc.v:198480.3-198488.6" + process $proc$libresoc.v:198480$13877 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$13878 $1\d_cr_delay$next[0:0]$13879 + attribute \src "libresoc.v:198481.5-198481.29" + switch \initial + attribute \src "libresoc.v:198481.9-198481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$13879 1'0 + case + assign $1\d_cr_delay$next[0:0]$13879 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13878 + end + attribute \src "libresoc.v:198489.3-198498.6" + process $proc$libresoc.v:198489$13880 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:198490.5-198490.29" + switch \initial + attribute \src "libresoc.v:198490.9-198490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$260 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:198499.3-198508.6" + process $proc$libresoc.v:198499$13881 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:198500.5-198500.29" + switch \initial + attribute \src "libresoc.v:198500.9-198500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:198509.3-198518.6" + process $proc$libresoc.v:198509$13882 + assign { } { } + assign { } { } + assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:198510.5-198510.29" + switch \initial + attribute \src "libresoc.v:198510.9-198510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:964" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd__ren[2:0] 3'111 + case + assign $1\core_full_rd__ren[2:0] 3'000 + end + sync always + update \core_full_rd__ren $0\core_full_rd__ren[2:0] + end + attribute \src "libresoc.v:198519.3-198527.6" + process $proc$libresoc.v:198519$13883 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$13884 $1\d_xer_delay$next[0:0]$13885 + attribute \src "libresoc.v:198520.5-198520.29" + switch \initial + attribute \src "libresoc.v:198520.9-198520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_xer_delay$next[0:0]$13885 1'0 + case + assign $1\d_xer_delay$next[0:0]$13885 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13884 + end + attribute \src "libresoc.v:198528.3-198537.6" + process $proc$libresoc.v:198528$13886 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:198529.5-198529.29" + switch \initial + attribute \src "libresoc.v:198529.9-198529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$262 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:198538.3-198547.6" + process $proc$libresoc.v:198538$13887 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:198539.5-198539.29" + switch \initial + attribute \src "libresoc.v:198539.9-198539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:198548.3-198562.6" + process $proc$libresoc.v:198548$13888 + assign { } { } + assign { } { } + assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] + attribute \src "libresoc.v:198549.5-198549.29" + switch \initial + attribute \src "libresoc.v:198549.9-198549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__addr[2:0] 3'111 + case + assign $1\core_issue__addr[2:0] 3'000 + end + sync always + update \core_issue__addr $0\core_issue__addr[2:0] + end + attribute \src "libresoc.v:198563.3-198577.6" + process $proc$libresoc.v:198563$13889 + assign { } { } + assign { } { } + assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] + attribute \src "libresoc.v:198564.5-198564.29" + switch \initial + attribute \src "libresoc.v:198564.9-198564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + case + assign $1\core_issue__ren[0:0] 1'0 + end + sync always + update \core_issue__ren $0\core_issue__ren[0:0] + end + attribute \src "libresoc.v:198578.3-198605.6" + process $proc$libresoc.v:198578$13890 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$13891 $2\fsm_state$next[1:0]$13893 + attribute \src "libresoc.v:198579.5-198579.29" + switch \initial + attribute \src "libresoc.v:198579.9-198579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$13892 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$13892 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$13892 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$13892 2'00 + case + assign $1\fsm_state$next[1:0]$13892 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$13893 2'00 + case + assign $2\fsm_state$next[1:0]$13893 $1\fsm_state$next[1:0]$13892 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$13891 + end + attribute \src "libresoc.v:198606.3-198616.6" + process $proc$libresoc.v:198606$13894 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:198607.5-198607.29" + switch \initial + attribute \src "libresoc.v:198607.9-198607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$264 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:198617.3-198631.6" + process $proc$libresoc.v:198617$13895 + assign { } { } + assign { } { } + assign $0\core_issue__addr$13[2:0]$13896 $1\core_issue__addr$13[2:0]$13897 + attribute \src "libresoc.v:198618.5-198618.29" + switch \initial + attribute \src "libresoc.v:198618.9-198618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__addr$13[2:0]$13897 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__addr$13[2:0]$13897 3'111 + case + assign $1\core_issue__addr$13[2:0]$13897 3'000 + end + sync always + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13896 + end + attribute \src "libresoc.v:198632.3-198646.6" + process $proc$libresoc.v:198632$13898 + assign { } { } + assign { } { } + assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] + attribute \src "libresoc.v:198633.5-198633.29" + switch \initial + attribute \src "libresoc.v:198633.9-198633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + case + assign $1\core_issue__wen[0:0] 1'0 + end + sync always + update \core_issue__wen $0\core_issue__wen[0:0] + end + attribute \src "libresoc.v:198647.3-198661.6" + process $proc$libresoc.v:198647$13899 + assign { } { } + assign { } { } + assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:198648.5-198648.29" + switch \initial + attribute \src "libresoc.v:198648.9-198648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_tb + case + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_issue__data_i $0\core_issue__data_i[63:0] + end + attribute \src "libresoc.v:198662.3-198677.6" + process $proc$libresoc.v:198662$13900 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$13901 $2\dec2_cur_dec$next[63:0]$13903 + attribute \src "libresoc.v:198663.5-198663.29" + switch \initial + attribute \src "libresoc.v:198663.9-198663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$13902 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$13902 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$13903 $1\dec2_cur_dec$next[63:0]$13902 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13901 + end + attribute \src "libresoc.v:198678.3-198688.6" + process $proc$libresoc.v:198678$13904 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:198679.5-198679.29" + switch \initial + attribute \src "libresoc.v:198679.9-198679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$267 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "libresoc.v:198689.3-198697.6" + process $proc$libresoc.v:198689$13905 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$13906 $1\dbg_dmi_we_i$next[0:0]$13907 + attribute \src "libresoc.v:198690.5-198690.29" + switch \initial + attribute \src "libresoc.v:198690.9-198690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_we_i$next[0:0]$13907 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$13907 \jtag_dmi0__we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13906 + end + attribute \src "libresoc.v:198698.3-198706.6" + process $proc$libresoc.v:198698$13908 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$13909 $1\pc_ok_delay$next[0:0]$13910 + attribute \src "libresoc.v:198699.5-198699.29" + switch \initial + attribute \src "libresoc.v:198699.9-198699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$13910 1'0 + case + assign $1\pc_ok_delay$next[0:0]$13910 \$38 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13909 + end + attribute \src "libresoc.v:198707.3-198722.6" + process $proc$libresoc.v:198707$13911 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:198708.5-198708.29" + switch \initial + attribute \src "libresoc.v:198708.9-198708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \core_cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "libresoc.v:198723.3-198735.6" + process $proc$libresoc.v:198723$13912 + assign { } { } + assign { } { } + assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] + attribute \src "libresoc.v:198724.5-198724.29" + switch \initial + attribute \src "libresoc.v:198724.9-198724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\core_cia__ren[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\core_cia__ren[2:0] 3'001 + end + sync always + update \core_cia__ren $0\core_cia__ren[2:0] + end + attribute \src "libresoc.v:198736.3-198744.6" + process $proc$libresoc.v:198736$13913 + assign { } { } + assign { } { } + assign $0\svstate_ok_delay$next[0:0]$13914 $1\svstate_ok_delay$next[0:0]$13915 + attribute \src "libresoc.v:198737.5-198737.29" + switch \initial + attribute \src "libresoc.v:198737.9-198737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\svstate_ok_delay$next[0:0]$13915 1'0 + case + assign $1\svstate_ok_delay$next[0:0]$13915 \$40 + end + sync always + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13914 + end + attribute \src "libresoc.v:198745.3-198760.6" + process $proc$libresoc.v:198745$13916 + assign { } { } + assign { } { } + assign { } { } + assign $0\svstate[63:0] $2\svstate[63:0] + attribute \src "libresoc.v:198746.5-198746.29" + switch \initial + attribute \src "libresoc.v:198746.9-198746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\svstate[63:0] \$42 + case + assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" + switch \svstate_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\svstate[63:0] \core_sv__data_o + case + assign $2\svstate[63:0] $1\svstate[63:0] + end + sync always + update \svstate $0\svstate[63:0] + end + attribute \src "libresoc.v:198761.3-198773.6" + process $proc$libresoc.v:198761$13917 + assign { } { } + assign { } { } + assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] + attribute \src "libresoc.v:198762.5-198762.29" + switch \initial + attribute \src "libresoc.v:198762.9-198762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\core_sv__ren[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\core_sv__ren[2:0] 3'100 + end + sync always + update \core_sv__ren $0\core_sv__ren[2:0] + end + attribute \src "libresoc.v:198774.3-198782.6" + process $proc$libresoc.v:198774$13918 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$13919 $1\dbg_dmi_din$next[63:0]$13920 + attribute \src "libresoc.v:198775.5-198775.29" + switch \initial + attribute \src "libresoc.v:198775.9-198775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$13920 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$13920 \jtag_dmi0__din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13919 + end + attribute \src "libresoc.v:198783.3-198850.6" + process $proc$libresoc.v:198783$13921 + assign { } { } + assign { } { } + assign $0\core_wen[2:0] $1\core_wen[2:0] + attribute \src "libresoc.v:198784.5-198784.29" + switch \initial + attribute \src "libresoc.v:198784.9-198784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\core_wen[2:0] $2\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_wen[2:0] $3\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_wen[2:0] 3'001 + case + assign $3\core_wen[2:0] 3'000 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_wen[2:0] $4\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_wen[2:0] $5\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\core_wen[2:0] 3'001 + case + assign $5\core_wen[2:0] 3'000 + end + case + assign $4\core_wen[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\core_wen[2:0] $6\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\core_wen[2:0] $7\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\core_wen[2:0] $8\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$64 \$60 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $8\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $8\core_wen[2:0] 3'001 + case + assign $8\core_wen[2:0] 3'000 + end + case + assign $7\core_wen[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\core_wen[2:0] $9\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\core_wen[2:0] 3'001 + case + assign $9\core_wen[2:0] 3'000 + end + end + case + assign $1\core_wen[2:0] 3'000 + end + sync always + update \core_wen $0\core_wen[2:0] + end + attribute \src "libresoc.v:198851.3-198918.6" + process $proc$libresoc.v:198851$13922 + assign { } { } + assign { } { } + assign $0\core_data_i[63:0] $1\core_data_i[63:0] + attribute \src "libresoc.v:198852.5-198852.29" + switch \initial + attribute \src "libresoc.v:198852.9-198852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\core_data_i[63:0] $2\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$70 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_data_i[63:0] $3\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_data_i[63:0] \pc_i + case + assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_data_i[63:0] $4\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_data_i[63:0] $5\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$74 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\core_data_i[63:0] \nia + case + assign $5\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\core_data_i[63:0] $6\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$80 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\core_data_i[63:0] $7\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\core_data_i[63:0] $8\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$86 \$82 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $8\core_data_i[63:0] \nia + case + assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $7\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\core_data_i[63:0] $9\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\core_data_i[63:0] \pc_i + case + assign $9\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i $0\core_data_i[63:0] + end + attribute \src "libresoc.v:198919.3-198934.6" + process $proc$libresoc.v:198919$13923 + assign { } { } + assign { } { } + assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] + attribute \src "libresoc.v:198920.5-198920.29" + switch \initial + attribute \src "libresoc.v:198920.9-198920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_msr__ren[2:0] 3'010 + case + assign $2\core_msr__ren[2:0] 3'000 + end + case + assign $1\core_msr__ren[2:0] 3'000 + end + sync always + update \core_msr__ren $0\core_msr__ren[2:0] + end + attribute \src "libresoc.v:198935.3-198943.6" + process $proc$libresoc.v:198935$13924 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$13925 $1\jtag_dmi0__ack_o$next[0:0]$13926 + attribute \src "libresoc.v:198936.5-198936.29" + switch \initial + attribute \src "libresoc.v:198936.9-198936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__ack_o$next[0:0]$13926 1'0 + case + assign $1\jtag_dmi0__ack_o$next[0:0]$13926 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13925 + end + attribute \src "libresoc.v:198944.3-198954.6" + process $proc$libresoc.v:198944$13927 + assign { } { } + assign { } { } + assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:198945.5-198945.29" + switch \initial + attribute \src "libresoc.v:198945.9-198945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fetch_pc_ready_o[0:0] 1'1 + case + assign $1\fetch_pc_ready_o[0:0] 1'0 + end + sync always + update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] + end + attribute \src "libresoc.v:198955.3-198970.6" + process $proc$libresoc.v:198955$13928 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:198956.5-198956.29" + switch \initial + attribute \src "libresoc.v:198956.9-198956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:198971.3-199004.6" + process $proc$libresoc.v:198971$13929 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:198972.5-198972.29" + switch \initial + attribute \src "libresoc.v:198972.9-198972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\imem_a_valid_i[0:0] 1'1 + case + assign $4\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:199005.3-199038.6" + process $proc$libresoc.v:199005$13930 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:199006.5-199006.29" + switch \initial + attribute \src "libresoc.v:199006.9-199006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\imem_f_valid_i[0:0] 1'1 + case + assign $4\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "libresoc.v:199039.3-199059.6" + process $proc$libresoc.v:199039$13931 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$13932 $3\dec2_cur_pc$next[63:0]$13935 + attribute \src "libresoc.v:199040.5-199040.29" + switch \initial + attribute \src "libresoc.v:199040.9-199040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$13933 $2\dec2_cur_pc$next[63:0]$13934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$13934 \pc + case + assign $2\dec2_cur_pc$next[63:0]$13934 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$13933 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$13935 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$13935 $1\dec2_cur_pc$next[63:0]$13933 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13932 + end + attribute \src "libresoc.v:199060.3-199098.6" + process $proc$libresoc.v:199060$13936 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cur_cur_dststep$next[6:0]$13937 $4\cur_cur_dststep$next[6:0]$13961 + assign $0\cur_cur_maxvl$next[6:0]$13938 $4\cur_cur_maxvl$next[6:0]$13962 + assign $0\cur_cur_srcstep$next[6:0]$13939 $4\cur_cur_srcstep$next[6:0]$13963 + assign $0\cur_cur_subvl$next[1:0]$13940 $4\cur_cur_subvl$next[1:0]$13964 + assign $0\cur_cur_svstep$next[1:0]$13941 $4\cur_cur_svstep$next[1:0]$13965 + assign $0\cur_cur_vl$next[6:0]$13942 $4\cur_cur_vl$next[6:0]$13966 + attribute \src "libresoc.v:199061.5-199061.29" + switch \initial + attribute \src "libresoc.v:199061.9-199061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cur_cur_dststep$next[6:0]$13943 $2\cur_cur_dststep$next[6:0]$13949 + assign $1\cur_cur_maxvl$next[6:0]$13944 $2\cur_cur_maxvl$next[6:0]$13950 + assign $1\cur_cur_srcstep$next[6:0]$13945 $2\cur_cur_srcstep$next[6:0]$13951 + assign $1\cur_cur_subvl$next[1:0]$13946 $2\cur_cur_subvl$next[1:0]$13952 + assign $1\cur_cur_svstep$next[1:0]$13947 $2\cur_cur_svstep$next[1:0]$13953 + assign $1\cur_cur_vl$next[6:0]$13948 $2\cur_cur_vl$next[6:0]$13954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\cur_cur_maxvl$next[6:0]$13950 $2\cur_cur_vl$next[6:0]$13954 $2\cur_cur_srcstep$next[6:0]$13951 $2\cur_cur_dststep$next[6:0]$13949 $2\cur_cur_subvl$next[1:0]$13952 $2\cur_cur_svstep$next[1:0]$13953 } \svstate [31:0] + case + assign $2\cur_cur_dststep$next[6:0]$13949 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13950 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13951 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13952 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13953 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13954 \cur_cur_vl + end + case + assign $1\cur_cur_dststep$next[6:0]$13943 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13944 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13945 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13946 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13947 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13948 \cur_cur_vl + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\cur_cur_maxvl$next[6:0]$13956 $3\cur_cur_vl$next[6:0]$13960 $3\cur_cur_srcstep$next[6:0]$13957 $3\cur_cur_dststep$next[6:0]$13955 $3\cur_cur_subvl$next[1:0]$13958 $3\cur_cur_svstep$next[1:0]$13959 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + case + assign $3\cur_cur_dststep$next[6:0]$13955 $1\cur_cur_dststep$next[6:0]$13943 + assign $3\cur_cur_maxvl$next[6:0]$13956 $1\cur_cur_maxvl$next[6:0]$13944 + assign $3\cur_cur_srcstep$next[6:0]$13957 $1\cur_cur_srcstep$next[6:0]$13945 + assign $3\cur_cur_subvl$next[1:0]$13958 $1\cur_cur_subvl$next[1:0]$13946 + assign $3\cur_cur_svstep$next[1:0]$13959 $1\cur_cur_svstep$next[1:0]$13947 + assign $3\cur_cur_vl$next[6:0]$13960 $1\cur_cur_vl$next[6:0]$13948 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\cur_cur_svstep$next[1:0]$13965 2'00 + assign $4\cur_cur_subvl$next[1:0]$13964 2'00 + assign $4\cur_cur_dststep$next[6:0]$13961 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13963 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13966 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13962 7'0000000 + case + assign $4\cur_cur_dststep$next[6:0]$13961 $3\cur_cur_dststep$next[6:0]$13955 + assign $4\cur_cur_maxvl$next[6:0]$13962 $3\cur_cur_maxvl$next[6:0]$13956 + assign $4\cur_cur_srcstep$next[6:0]$13963 $3\cur_cur_srcstep$next[6:0]$13957 + assign $4\cur_cur_subvl$next[1:0]$13964 $3\cur_cur_subvl$next[1:0]$13958 + assign $4\cur_cur_svstep$next[1:0]$13965 $3\cur_cur_svstep$next[1:0]$13959 + assign $4\cur_cur_vl$next[6:0]$13966 $3\cur_cur_vl$next[6:0]$13960 + end + sync always + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13937 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13938 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13939 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13940 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13941 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13942 + end + attribute \src "libresoc.v:199099.3-199107.6" + process $proc$libresoc.v:199099$13967 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$13968 $1\jtag_dmi0__dout$next[63:0]$13969 + attribute \src "libresoc.v:199100.5-199100.29" + switch \initial + attribute \src "libresoc.v:199100.9-199100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$13969 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$13969 \dbg_dmi_dout + end + sync always + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13968 + end + attribute \src "libresoc.v:199108.3-199137.6" + process $proc$libresoc.v:199108$13970 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$13971 $4\msr_read$next[0:0]$13975 + attribute \src "libresoc.v:199109.5-199109.29" + switch \initial + attribute \src "libresoc.v:199109.9-199109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$13972 $2\msr_read$next[0:0]$13973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$13973 1'0 + case + assign $2\msr_read$next[0:0]$13973 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$13972 $3\msr_read$next[0:0]$13974 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + switch \$88 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$13974 1'1 + case + assign $3\msr_read$next[0:0]$13974 \msr_read + end + case + assign $1\msr_read$next[0:0]$13972 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$13975 1'1 + case + assign $4\msr_read$next[0:0]$13975 $1\msr_read$next[0:0]$13972 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$13971 + end + attribute \src "libresoc.v:199138.3-199191.6" + process $proc$libresoc.v:199138$13976 + assign { } { } + assign { } { } + assign { } { } + assign $0\fetch_fsm_state$next[1:0]$13977 $6\fetch_fsm_state$next[1:0]$13983 + attribute \src "libresoc.v:199139.5-199139.29" + switch \initial + attribute \src "libresoc.v:199139.9-199139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13978 $2\fetch_fsm_state$next[1:0]$13979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fetch_fsm_state$next[1:0]$13979 2'01 + case + assign $2\fetch_fsm_state$next[1:0]$13979 \fetch_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13978 $3\fetch_fsm_state$next[1:0]$13980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fetch_fsm_state$next[1:0]$13980 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fetch_fsm_state$next[1:0]$13980 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13978 $4\fetch_fsm_state$next[1:0]$13981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\fetch_fsm_state$next[1:0]$13981 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fetch_fsm_state$next[1:0]$13981 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13978 $5\fetch_fsm_state$next[1:0]$13982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" + switch \fetch_insn_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fetch_fsm_state$next[1:0]$13982 2'00 + case + assign $5\fetch_fsm_state$next[1:0]$13982 \fetch_fsm_state + end + case + assign $1\fetch_fsm_state$next[1:0]$13978 \fetch_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fetch_fsm_state$next[1:0]$13983 2'00 + case + assign $6\fetch_fsm_state$next[1:0]$13983 $1\fetch_fsm_state$next[1:0]$13978 + end + sync always + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13977 + end + attribute \src "libresoc.v:199192.3-199212.6" + process $proc$libresoc.v:199192$13984 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$13985 $3\dec2_cur_msr$next[63:0]$13988 + attribute \src "libresoc.v:199193.5-199193.29" + switch \initial + attribute \src "libresoc.v:199193.9-199193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$13986 $2\dec2_cur_msr$next[63:0]$13987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + switch \$90 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$13987 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$13987 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$13986 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_msr$next[63:0]$13988 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$13988 $1\dec2_cur_msr$next[63:0]$13986 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13985 + end + attribute \src "libresoc.v:199213.3-199231.6" + process $proc$libresoc.v:199213$13989 + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$13990 $1\nia$next[63:0]$13991 + attribute \src "libresoc.v:199214.5-199214.29" + switch \initial + attribute \src "libresoc.v:199214.9-199214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\nia$next[63:0]$13991 $2\nia$next[63:0]$13992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\nia$next[63:0]$13992 \nia + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\nia$next[63:0]$13992 \$92 [63:0] + end + case + assign $1\nia$next[63:0]$13991 \nia + end + sync always + update \nia$next $0\nia$next[63:0]$13990 + end + attribute \src "libresoc.v:199232.3-199262.6" + process $proc$libresoc.v:199232$13993 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in$next[31:0]$13994 $1\dec2_raw_opcode_in$next[31:0]$13995 + attribute \src "libresoc.v:199233.5-199233.29" + switch \initial + attribute \src "libresoc.v:199233.9-199233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in$next[31:0]$13995 $2\dec2_raw_opcode_in$next[31:0]$13996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in$next[31:0]$13996 \dec2_raw_opcode_in + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in$next[31:0]$13996 \$95 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\dec2_raw_opcode_in$next[31:0]$13995 $3\dec2_raw_opcode_in$next[31:0]$13997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\dec2_raw_opcode_in$next[31:0]$13997 \dec2_raw_opcode_in + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\dec2_raw_opcode_in$next[31:0]$13997 \$99 + end + case + assign $1\dec2_raw_opcode_in$next[31:0]$13995 \dec2_raw_opcode_in + end + sync always + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13994 + end + attribute \src "libresoc.v:199263.3-199273.6" + process $proc$libresoc.v:199263$13998 + assign { } { } + assign { } { } + assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:199264.5-199264.29" + switch \initial + attribute \src "libresoc.v:199264.9-199264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fetch_insn_valid_o[0:0] 1'1 + case + assign $1\fetch_insn_valid_o[0:0] 1'0 + end + sync always + update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] + end + attribute \src "libresoc.v:199274.3-199333.6" + process $proc$libresoc.v:199274$13999 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\new_svstate_dststep[6:0] $1\new_svstate_dststep[6:0] + assign $0\new_svstate_maxvl[6:0] $1\new_svstate_maxvl[6:0] + assign $0\new_svstate_srcstep[6:0] $1\new_svstate_srcstep[6:0] + assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] + assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] + assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] + attribute \src "libresoc.v:199275.5-199275.29" + switch \initial + attribute \src "libresoc.v:199275.9-199275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\new_svstate_dststep[6:0] $2\new_svstate_dststep[6:0] + assign $1\new_svstate_maxvl[6:0] $2\new_svstate_maxvl[6:0] + assign $1\new_svstate_srcstep[6:0] $2\new_svstate_srcstep[6:0] + assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] + assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] + assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$110 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\new_svstate_dststep[6:0] \cur_cur_dststep + assign $2\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $2\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $2\new_svstate_subvl[1:0] \cur_cur_subvl + assign $2\new_svstate_svstep[1:0] \cur_cur_svstep + assign $2\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\new_svstate_dststep[6:0] $3\new_svstate_dststep[6:0] + assign $2\new_svstate_maxvl[6:0] $3\new_svstate_maxvl[6:0] + assign $2\new_svstate_srcstep[6:0] $3\new_svstate_srcstep[6:0] + assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] + assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] + assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\new_svstate_maxvl[6:0] $3\new_svstate_vl[6:0] $3\new_svstate_srcstep[6:0] $3\new_svstate_dststep[6:0] $3\new_svstate_subvl[1:0] $3\new_svstate_svstep[1:0] } \svstate_i + case + assign $3\new_svstate_dststep[6:0] \cur_cur_dststep + assign $3\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $3\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $3\new_svstate_subvl[1:0] \cur_cur_subvl + assign $3\new_svstate_svstep[1:0] \cur_cur_svstep + assign $3\new_svstate_vl[6:0] \cur_cur_vl + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\new_svstate_dststep[6:0] $4\new_svstate_dststep[6:0] + assign $1\new_svstate_maxvl[6:0] $4\new_svstate_maxvl[6:0] + assign $1\new_svstate_srcstep[6:0] $4\new_svstate_srcstep[6:0] + assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] + assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] + assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign { } { } + assign $4\new_svstate_subvl[1:0] \cur_cur_subvl + assign $4\new_svstate_svstep[1:0] \cur_cur_svstep + assign $4\new_svstate_vl[6:0] \cur_cur_vl + assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] + assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] + assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$122 \$118 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $6\new_svstate_dststep[6:0] \cur_cur_dststep + assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $6\new_svstate_dststep[6:0] \cur_cur_dststep + assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $6\new_svstate_srcstep[6:0] \next_srcstep + assign $6\new_svstate_dststep[6:0] \next_dststep + end + case + assign $5\new_svstate_dststep[6:0] \cur_cur_dststep + assign $5\new_svstate_srcstep[6:0] \cur_cur_srcstep + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\new_svstate_dststep[6:0] $7\new_svstate_dststep[6:0] + assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0] + assign $4\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] + assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] + assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] + assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $7\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i + case + assign $7\new_svstate_dststep[6:0] \cur_cur_dststep + assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $5\new_svstate_subvl[1:0] \cur_cur_subvl + assign $5\new_svstate_svstep[1:0] \cur_cur_svstep + assign $5\new_svstate_vl[6:0] \cur_cur_vl + end + end + case + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + end + sync always + update \new_svstate_dststep $0\new_svstate_dststep[6:0] + update \new_svstate_maxvl $0\new_svstate_maxvl[6:0] + update \new_svstate_srcstep $0\new_svstate_srcstep[6:0] + update \new_svstate_subvl $0\new_svstate_subvl[1:0] + update \new_svstate_svstep $0\new_svstate_svstep[1:0] + update \new_svstate_vl $0\new_svstate_vl[6:0] + end + attribute \src "libresoc.v:199334.3-199349.6" + process $proc$libresoc.v:199334$14000 + assign { } { } + assign { } { } + assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:199335.5-199335.29" + switch \initial + attribute \src "libresoc.v:199335.9-199335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$134 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fetch_pc_valid_i[0:0] 1'1 + case + assign $2\fetch_pc_valid_i[0:0] 1'0 + end + case + assign $1\fetch_pc_valid_i[0:0] 1'0 + end + sync always + update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] + end + attribute \src "libresoc.v:199350.3-199448.6" + process $proc$libresoc.v:199350$14001 + assign { } { } + assign { } { } + assign { } { } + assign $0\issue_fsm_state$next[2:0]$14002 $12\issue_fsm_state$next[2:0]$14014 + attribute \src "libresoc.v:199351.5-199351.29" + switch \initial + attribute \src "libresoc.v:199351.9-199351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $2\issue_fsm_state$next[2:0]$14004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$140 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\issue_fsm_state$next[2:0]$14004 $3\issue_fsm_state$next[2:0]$14005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + switch \fetch_pc_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\issue_fsm_state$next[2:0]$14005 3'001 + case + assign $3\issue_fsm_state$next[2:0]$14005 \issue_fsm_state + end + case + assign $2\issue_fsm_state$next[2:0]$14004 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $4\issue_fsm_state$next[2:0]$14006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\issue_fsm_state$next[2:0]$14006 $5\issue_fsm_state$next[2:0]$14007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$144 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\issue_fsm_state$next[2:0]$14007 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\issue_fsm_state$next[2:0]$14007 3'010 + end + case + assign $4\issue_fsm_state$next[2:0]$14006 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $6\issue_fsm_state$next[2:0]$14008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" + switch \pred_insn_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\issue_fsm_state$next[2:0]$14008 3'100 + case + assign $6\issue_fsm_state$next[2:0]$14008 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $7\issue_fsm_state$next[2:0]$14009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" + switch \pred_mask_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\issue_fsm_state$next[2:0]$14009 3'010 + case + assign $7\issue_fsm_state$next[2:0]$14009 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $8\issue_fsm_state$next[2:0]$14010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" + switch \exec_insn_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\issue_fsm_state$next[2:0]$14010 3'101 + case + assign $8\issue_fsm_state$next[2:0]$14010 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $9\issue_fsm_state$next[2:0]$14011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$150 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\issue_fsm_state$next[2:0]$14011 $10\issue_fsm_state$next[2:0]$14012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\issue_fsm_state$next[2:0]$14012 $11\issue_fsm_state$next[2:0]$14013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$156 \$152 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $11\issue_fsm_state$next[2:0]$14013 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $11\issue_fsm_state$next[2:0]$14013 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\issue_fsm_state$next[2:0]$14013 3'110 + end + case + assign $10\issue_fsm_state$next[2:0]$14012 \issue_fsm_state + end + case + assign $9\issue_fsm_state$next[2:0]$14011 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 3'010 + case + assign $1\issue_fsm_state$next[2:0]$14003 \issue_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\issue_fsm_state$next[2:0]$14014 3'000 + case + assign $12\issue_fsm_state$next[2:0]$14014 $1\issue_fsm_state$next[2:0]$14003 + end + sync always + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$14002 + end + attribute \src "libresoc.v:199449.3-199479.6" + process $proc$libresoc.v:199449$14015 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:199450.5-199450.29" + switch \initial + attribute \src "libresoc.v:199450.9-199450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$162 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$168 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:199480.3-199510.6" + process $proc$libresoc.v:199480$14016 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:199481.5-199481.29" + switch \initial + attribute \src "libresoc.v:199481.9-199481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$174 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$180 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + attribute \src "libresoc.v:199511.3-199577.6" + process $proc$libresoc.v:199511$14017 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$14018 $9\pc_changed$next[0:0]$14027 + attribute \src "libresoc.v:199512.5-199512.29" + switch \initial + attribute \src "libresoc.v:199512.9-199512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\pc_changed$next[0:0]$14019 $2\pc_changed$next[0:0]$14020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$186 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\pc_changed$next[0:0]$14020 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\pc_changed$next[0:0]$14020 $3\pc_changed$next[0:0]$14021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$14021 1'1 + case + assign $3\pc_changed$next[0:0]$14021 \pc_changed + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\pc_changed$next[0:0]$14019 $4\pc_changed$next[0:0]$14022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$192 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\pc_changed$next[0:0]$14022 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\pc_changed$next[0:0]$14022 $5\pc_changed$next[0:0]$14023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\pc_changed$next[0:0]$14023 1'1 + case + assign $5\pc_changed$next[0:0]$14023 \pc_changed + end + end + case + assign $1\pc_changed$next[0:0]$14019 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $6\pc_changed$next[0:0]$14024 $7\pc_changed$next[0:0]$14025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\pc_changed$next[0:0]$14025 1'0 + case + assign $7\pc_changed$next[0:0]$14025 $1\pc_changed$next[0:0]$14019 + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\pc_changed$next[0:0]$14024 $8\pc_changed$next[0:0]$14026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + switch \$194 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\pc_changed$next[0:0]$14026 1'1 + case + assign $8\pc_changed$next[0:0]$14026 $1\pc_changed$next[0:0]$14019 + end + case + assign $6\pc_changed$next[0:0]$14024 $1\pc_changed$next[0:0]$14019 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\pc_changed$next[0:0]$14027 1'0 + case + assign $9\pc_changed$next[0:0]$14027 $6\pc_changed$next[0:0]$14024 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$14018 + end + attribute \src "libresoc.v:199578.3-199634.6" + process $proc$libresoc.v:199578$14028 + assign { } { } + assign { } { } + assign $0\update_svstate[0:0] $1\update_svstate[0:0] + attribute \src "libresoc.v:199579.5-199579.29" + switch \initial + attribute \src "libresoc.v:199579.9-199579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\update_svstate[0:0] $2\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$202 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\update_svstate[0:0] $3\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\update_svstate[0:0] 1'1 + case + assign $3\update_svstate[0:0] 1'0 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\update_svstate[0:0] $4\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$208 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\update_svstate[0:0] $5\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\update_svstate[0:0] $6\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$214 \$210 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $6\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $6\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\update_svstate[0:0] 1'1 + end + case + assign $5\update_svstate[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\update_svstate[0:0] $7\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\update_svstate[0:0] 1'1 + case + assign $7\update_svstate[0:0] 1'0 + end + end + case + assign $1\update_svstate[0:0] 1'0 + end + sync always + update \update_svstate $0\update_svstate[0:0] + end + attribute \src "libresoc.v:199635.3-199701.6" + process $proc$libresoc.v:199635$14029 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_changed$next[0:0]$14030 $9\sv_changed$next[0:0]$14039 + attribute \src "libresoc.v:199636.5-199636.29" + switch \initial + attribute \src "libresoc.v:199636.9-199636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\sv_changed$next[0:0]$14031 $2\sv_changed$next[0:0]$14032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$220 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\sv_changed$next[0:0]$14032 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\sv_changed$next[0:0]$14032 $3\sv_changed$next[0:0]$14033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv_changed$next[0:0]$14033 1'1 + case + assign $3\sv_changed$next[0:0]$14033 \sv_changed + end + end + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\sv_changed$next[0:0]$14031 $4\sv_changed$next[0:0]$14034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$226 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\sv_changed$next[0:0]$14034 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\sv_changed$next[0:0]$14034 $5\sv_changed$next[0:0]$14035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv_changed$next[0:0]$14035 1'1 + case + assign $5\sv_changed$next[0:0]$14035 \sv_changed + end + end + case + assign $1\sv_changed$next[0:0]$14031 \sv_changed + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign { } { } + assign $6\sv_changed$next[0:0]$14036 $7\sv_changed$next[0:0]$14037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv_changed$next[0:0]$14037 1'0 + case + assign $7\sv_changed$next[0:0]$14037 $1\sv_changed$next[0:0]$14031 + end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv_changed$next[0:0]$14036 $8\sv_changed$next[0:0]$14038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + switch \$228 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\sv_changed$next[0:0]$14038 1'1 + case + assign $8\sv_changed$next[0:0]$14038 $1\sv_changed$next[0:0]$14031 + end + case + assign $6\sv_changed$next[0:0]$14036 $1\sv_changed$next[0:0]$14031 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\sv_changed$next[0:0]$14039 1'0 + case + assign $9\sv_changed$next[0:0]$14039 $6\sv_changed$next[0:0]$14036 + end + sync always + update \sv_changed$next $0\sv_changed$next[0:0]$14030 + end + attribute \src "libresoc.v:199702.3-199712.6" + process $proc$libresoc.v:199702$14040 + assign { } { } + assign { } { } + assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:199703.5-199703.29" + switch \initial + attribute \src "libresoc.v:199703.9-199703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fetch_insn_ready_i[0:0] 1'1 + case + assign $1\fetch_insn_ready_i[0:0] 1'0 + end + sync always + update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] + end + attribute \src "libresoc.v:199713.3-199823.6" + process $proc$libresoc.v:199713$14041 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$14042 $1\core_asmcode$next[7:0]$14101 + assign $0\core_core_core_cia$next[63:0]$14043 $1\core_core_core_cia$next[63:0]$14102 + assign $0\core_core_core_cr_rd$next[7:0]$14044 $1\core_core_core_cr_rd$next[7:0]$14103 + assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$14046 $1\core_core_core_cr_wr$next[7:0]$14105 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_core_fn_unit$next[13:0]$14055 $1\core_core_core_fn_unit$next[13:0]$14114 + assign $0\core_core_core_input_carry$next[1:0]$14056 $1\core_core_core_input_carry$next[1:0]$14115 + assign $0\core_core_core_insn$next[31:0]$14057 $1\core_core_core_insn$next[31:0]$14116 + assign $0\core_core_core_insn_type$next[6:0]$14058 $1\core_core_core_insn_type$next[6:0]$14117 + assign $0\core_core_core_is_32bit$next[0:0]$14059 $1\core_core_core_is_32bit$next[0:0]$14118 + assign $0\core_core_core_msr$next[63:0]$14060 $1\core_core_core_msr$next[63:0]$14119 + assign $0\core_core_core_oe$next[0:0]$14061 $1\core_core_core_oe$next[0:0]$14120 + assign { } { } + assign $0\core_core_core_rc$next[0:0]$14063 $1\core_core_core_rc$next[0:0]$14122 + assign { } { } + assign $0\core_core_core_trapaddr$next[12:0]$14065 $1\core_core_core_trapaddr$next[12:0]$14124 + assign $0\core_core_core_traptype$next[7:0]$14066 $1\core_core_core_traptype$next[7:0]$14125 + assign $0\core_core_cr_in1$next[6:0]$14067 $1\core_core_cr_in1$next[6:0]$14126 + assign { } { } + assign $0\core_core_cr_in2$1$next[6:0]$14069 $1\core_core_cr_in2$1$next[6:0]$14128 + assign $0\core_core_cr_in2$next[6:0]$14070 $1\core_core_cr_in2$next[6:0]$14129 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[6:0]$14073 $1\core_core_cr_out$next[6:0]$14132 + assign { } { } + assign $0\core_core_ea$next[6:0]$14075 $1\core_core_ea$next[6:0]$14134 + assign $0\core_core_fast1$next[2:0]$14076 $1\core_core_fast1$next[2:0]$14135 + assign { } { } + assign $0\core_core_fast2$next[2:0]$14078 $1\core_core_fast2$next[2:0]$14137 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$14080 $1\core_core_fasto1$next[2:0]$14139 + assign $0\core_core_fasto2$next[2:0]$14081 $1\core_core_fasto2$next[2:0]$14140 + assign $0\core_core_lk$next[0:0]$14082 $1\core_core_lk$next[0:0]$14141 + assign $0\core_core_reg1$next[6:0]$14083 $1\core_core_reg1$next[6:0]$14142 + assign { } { } + assign $0\core_core_reg2$next[6:0]$14085 $1\core_core_reg2$next[6:0]$14144 + assign { } { } + assign $0\core_core_reg3$next[6:0]$14087 $1\core_core_reg3$next[6:0]$14146 + assign { } { } + assign $0\core_core_rego$next[6:0]$14089 $1\core_core_rego$next[6:0]$14148 + assign $0\core_core_spr1$next[9:0]$14090 $1\core_core_spr1$next[9:0]$14149 + assign { } { } + assign $0\core_core_spro$next[9:0]$14092 $1\core_core_spro$next[9:0]$14151 + assign $0\core_core_xer_in$next[2:0]$14093 $1\core_core_xer_in$next[2:0]$14152 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$14100 $1\core_xer_out$next[0:0]$14159 + assign $0\core_core_core_cr_rd_ok$next[0:0]$14045 $3\core_core_core_cr_rd_ok$next[0:0]$14219 + assign $0\core_core_core_exc_$signal$3$next[0:0]$14047 $3\core_core_core_exc_$signal$3$next[0:0]$14220 + assign $0\core_core_core_exc_$signal$4$next[0:0]$14048 $3\core_core_core_exc_$signal$4$next[0:0]$14221 + assign $0\core_core_core_exc_$signal$5$next[0:0]$14049 $3\core_core_core_exc_$signal$5$next[0:0]$14222 + assign $0\core_core_core_exc_$signal$6$next[0:0]$14050 $3\core_core_core_exc_$signal$6$next[0:0]$14223 + assign $0\core_core_core_exc_$signal$7$next[0:0]$14051 $3\core_core_core_exc_$signal$7$next[0:0]$14224 + assign $0\core_core_core_exc_$signal$8$next[0:0]$14052 $3\core_core_core_exc_$signal$8$next[0:0]$14225 + assign $0\core_core_core_exc_$signal$9$next[0:0]$14053 $3\core_core_core_exc_$signal$9$next[0:0]$14226 + assign $0\core_core_core_exc_$signal$next[0:0]$14054 $3\core_core_core_exc_$signal$next[0:0]$14227 + assign $0\core_core_core_oe_ok$next[0:0]$14062 $3\core_core_core_oe_ok$next[0:0]$14228 + assign $0\core_core_core_rc_ok$next[0:0]$14064 $3\core_core_core_rc_ok$next[0:0]$14229 + assign $0\core_core_cr_in1_ok$next[0:0]$14068 $3\core_core_cr_in1_ok$next[0:0]$14230 + assign $0\core_core_cr_in2_ok$2$next[0:0]$14071 $3\core_core_cr_in2_ok$2$next[0:0]$14231 + assign $0\core_core_cr_in2_ok$next[0:0]$14072 $3\core_core_cr_in2_ok$next[0:0]$14232 + assign $0\core_core_cr_wr_ok$next[0:0]$14074 $3\core_core_cr_wr_ok$next[0:0]$14233 + assign $0\core_core_fast1_ok$next[0:0]$14077 $3\core_core_fast1_ok$next[0:0]$14234 + assign $0\core_core_fast2_ok$next[0:0]$14079 $3\core_core_fast2_ok$next[0:0]$14235 + assign $0\core_core_reg1_ok$next[0:0]$14084 $3\core_core_reg1_ok$next[0:0]$14236 + assign $0\core_core_reg2_ok$next[0:0]$14086 $3\core_core_reg2_ok$next[0:0]$14237 + assign $0\core_core_reg3_ok$next[0:0]$14088 $3\core_core_reg3_ok$next[0:0]$14238 + assign $0\core_core_spr1_ok$next[0:0]$14091 $3\core_core_spr1_ok$next[0:0]$14239 + assign $0\core_cr_out_ok$next[0:0]$14094 $3\core_cr_out_ok$next[0:0]$14240 + assign $0\core_ea_ok$next[0:0]$14095 $3\core_ea_ok$next[0:0]$14241 + assign $0\core_fasto1_ok$next[0:0]$14096 $3\core_fasto1_ok$next[0:0]$14242 + assign $0\core_fasto2_ok$next[0:0]$14097 $3\core_fasto2_ok$next[0:0]$14243 + assign $0\core_rego_ok$next[0:0]$14098 $3\core_rego_ok$next[0:0]$14244 + assign $0\core_spro_ok$next[0:0]$14099 $3\core_spro_ok$next[0:0]$14245 + attribute \src "libresoc.v:199714.5-199714.29" + switch \initial + attribute \src "libresoc.v:199714.9-199714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$14101 $2\core_asmcode$next[7:0]$14160 + assign $1\core_core_core_cia$next[63:0]$14102 $2\core_core_core_cia$next[63:0]$14161 + assign $1\core_core_core_cr_rd$next[7:0]$14103 $2\core_core_core_cr_rd$next[7:0]$14162 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 $2\core_core_core_cr_rd_ok$next[0:0]$14163 + assign $1\core_core_core_cr_wr$next[7:0]$14105 $2\core_core_core_cr_wr$next[7:0]$14164 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 $2\core_core_core_exc_$signal$3$next[0:0]$14165 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 $2\core_core_core_exc_$signal$4$next[0:0]$14166 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 $2\core_core_core_exc_$signal$5$next[0:0]$14167 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 $2\core_core_core_exc_$signal$6$next[0:0]$14168 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 $2\core_core_core_exc_$signal$7$next[0:0]$14169 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 $2\core_core_core_exc_$signal$8$next[0:0]$14170 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 $2\core_core_core_exc_$signal$9$next[0:0]$14171 + assign $1\core_core_core_exc_$signal$next[0:0]$14113 $2\core_core_core_exc_$signal$next[0:0]$14172 + assign $1\core_core_core_fn_unit$next[13:0]$14114 $2\core_core_core_fn_unit$next[13:0]$14173 + assign $1\core_core_core_input_carry$next[1:0]$14115 $2\core_core_core_input_carry$next[1:0]$14174 + assign $1\core_core_core_insn$next[31:0]$14116 $2\core_core_core_insn$next[31:0]$14175 + assign $1\core_core_core_insn_type$next[6:0]$14117 $2\core_core_core_insn_type$next[6:0]$14176 + assign $1\core_core_core_is_32bit$next[0:0]$14118 $2\core_core_core_is_32bit$next[0:0]$14177 + assign $1\core_core_core_msr$next[63:0]$14119 $2\core_core_core_msr$next[63:0]$14178 + assign $1\core_core_core_oe$next[0:0]$14120 $2\core_core_core_oe$next[0:0]$14179 + assign $1\core_core_core_oe_ok$next[0:0]$14121 $2\core_core_core_oe_ok$next[0:0]$14180 + assign $1\core_core_core_rc$next[0:0]$14122 $2\core_core_core_rc$next[0:0]$14181 + assign $1\core_core_core_rc_ok$next[0:0]$14123 $2\core_core_core_rc_ok$next[0:0]$14182 + assign $1\core_core_core_trapaddr$next[12:0]$14124 $2\core_core_core_trapaddr$next[12:0]$14183 + assign $1\core_core_core_traptype$next[7:0]$14125 $2\core_core_core_traptype$next[7:0]$14184 + assign $1\core_core_cr_in1$next[6:0]$14126 $2\core_core_cr_in1$next[6:0]$14185 + assign $1\core_core_cr_in1_ok$next[0:0]$14127 $2\core_core_cr_in1_ok$next[0:0]$14186 + assign $1\core_core_cr_in2$1$next[6:0]$14128 $2\core_core_cr_in2$1$next[6:0]$14187 + assign $1\core_core_cr_in2$next[6:0]$14129 $2\core_core_cr_in2$next[6:0]$14188 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 $2\core_core_cr_in2_ok$2$next[0:0]$14189 + assign $1\core_core_cr_in2_ok$next[0:0]$14131 $2\core_core_cr_in2_ok$next[0:0]$14190 + assign $1\core_core_cr_out$next[6:0]$14132 $2\core_core_cr_out$next[6:0]$14191 + assign $1\core_core_cr_wr_ok$next[0:0]$14133 $2\core_core_cr_wr_ok$next[0:0]$14192 + assign $1\core_core_ea$next[6:0]$14134 $2\core_core_ea$next[6:0]$14193 + assign $1\core_core_fast1$next[2:0]$14135 $2\core_core_fast1$next[2:0]$14194 + assign $1\core_core_fast1_ok$next[0:0]$14136 $2\core_core_fast1_ok$next[0:0]$14195 + assign $1\core_core_fast2$next[2:0]$14137 $2\core_core_fast2$next[2:0]$14196 + assign $1\core_core_fast2_ok$next[0:0]$14138 $2\core_core_fast2_ok$next[0:0]$14197 + assign $1\core_core_fasto1$next[2:0]$14139 $2\core_core_fasto1$next[2:0]$14198 + assign $1\core_core_fasto2$next[2:0]$14140 $2\core_core_fasto2$next[2:0]$14199 + assign $1\core_core_lk$next[0:0]$14141 $2\core_core_lk$next[0:0]$14200 + assign $1\core_core_reg1$next[6:0]$14142 $2\core_core_reg1$next[6:0]$14201 + assign $1\core_core_reg1_ok$next[0:0]$14143 $2\core_core_reg1_ok$next[0:0]$14202 + assign $1\core_core_reg2$next[6:0]$14144 $2\core_core_reg2$next[6:0]$14203 + assign $1\core_core_reg2_ok$next[0:0]$14145 $2\core_core_reg2_ok$next[0:0]$14204 + assign $1\core_core_reg3$next[6:0]$14146 $2\core_core_reg3$next[6:0]$14205 + assign $1\core_core_reg3_ok$next[0:0]$14147 $2\core_core_reg3_ok$next[0:0]$14206 + assign $1\core_core_rego$next[6:0]$14148 $2\core_core_rego$next[6:0]$14207 + assign $1\core_core_spr1$next[9:0]$14149 $2\core_core_spr1$next[9:0]$14208 + assign $1\core_core_spr1_ok$next[0:0]$14150 $2\core_core_spr1_ok$next[0:0]$14209 + assign $1\core_core_spro$next[9:0]$14151 $2\core_core_spro$next[9:0]$14210 + assign $1\core_core_xer_in$next[2:0]$14152 $2\core_core_xer_in$next[2:0]$14211 + assign $1\core_cr_out_ok$next[0:0]$14153 $2\core_cr_out_ok$next[0:0]$14212 + assign $1\core_ea_ok$next[0:0]$14154 $2\core_ea_ok$next[0:0]$14213 + assign $1\core_fasto1_ok$next[0:0]$14155 $2\core_fasto1_ok$next[0:0]$14214 + assign $1\core_fasto2_ok$next[0:0]$14156 $2\core_fasto2_ok$next[0:0]$14215 + assign $1\core_rego_ok$next[0:0]$14157 $2\core_rego_ok$next[0:0]$14216 + assign $1\core_spro_ok$next[0:0]$14158 $2\core_spro_ok$next[0:0]$14217 + assign $1\core_xer_out$next[0:0]$14159 $2\core_xer_out$next[0:0]$14218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_core_is_32bit$next[0:0]$14177 $2\core_core_cr_wr_ok$next[0:0]$14192 $2\core_core_core_cr_wr$next[7:0]$14164 $2\core_core_core_cr_rd_ok$next[0:0]$14163 $2\core_core_core_cr_rd$next[7:0]$14162 $2\core_core_core_trapaddr$next[12:0]$14183 $2\core_core_core_exc_$signal$9$next[0:0]$14171 $2\core_core_core_exc_$signal$8$next[0:0]$14170 $2\core_core_core_exc_$signal$7$next[0:0]$14169 $2\core_core_core_exc_$signal$6$next[0:0]$14168 $2\core_core_core_exc_$signal$5$next[0:0]$14167 $2\core_core_core_exc_$signal$4$next[0:0]$14166 $2\core_core_core_exc_$signal$3$next[0:0]$14165 $2\core_core_core_exc_$signal$next[0:0]$14172 $2\core_core_core_traptype$next[7:0]$14184 $2\core_core_core_input_carry$next[1:0]$14174 $2\core_core_core_oe_ok$next[0:0]$14180 $2\core_core_core_oe$next[0:0]$14179 $2\core_core_core_rc_ok$next[0:0]$14182 $2\core_core_core_rc$next[0:0]$14181 $2\core_core_lk$next[0:0]$14200 $2\core_core_core_fn_unit$next[13:0]$14173 $2\core_core_core_insn_type$next[6:0]$14176 $2\core_core_core_insn$next[31:0]$14175 $2\core_core_core_cia$next[63:0]$14161 $2\core_core_core_msr$next[63:0]$14178 $2\core_cr_out_ok$next[0:0]$14212 $2\core_core_cr_out$next[6:0]$14191 $2\core_core_cr_in2_ok$2$next[0:0]$14189 $2\core_core_cr_in2$1$next[6:0]$14187 $2\core_core_cr_in2_ok$next[0:0]$14190 $2\core_core_cr_in2$next[6:0]$14188 $2\core_core_cr_in1_ok$next[0:0]$14186 $2\core_core_cr_in1$next[6:0]$14185 $2\core_fasto2_ok$next[0:0]$14215 $2\core_core_fasto2$next[2:0]$14199 $2\core_fasto1_ok$next[0:0]$14214 $2\core_core_fasto1$next[2:0]$14198 $2\core_core_fast2_ok$next[0:0]$14197 $2\core_core_fast2$next[2:0]$14196 $2\core_core_fast1_ok$next[0:0]$14195 $2\core_core_fast1$next[2:0]$14194 $2\core_xer_out$next[0:0]$14218 $2\core_core_xer_in$next[2:0]$14211 $2\core_core_spr1_ok$next[0:0]$14209 $2\core_core_spr1$next[9:0]$14208 $2\core_spro_ok$next[0:0]$14217 $2\core_core_spro$next[9:0]$14210 $2\core_core_reg3_ok$next[0:0]$14206 $2\core_core_reg3$next[6:0]$14205 $2\core_core_reg2_ok$next[0:0]$14204 $2\core_core_reg2$next[6:0]$14203 $2\core_core_reg1_ok$next[0:0]$14202 $2\core_core_reg1$next[6:0]$14201 $2\core_ea_ok$next[0:0]$14213 $2\core_core_ea$next[6:0]$14193 $2\core_rego_ok$next[0:0]$14216 $2\core_core_rego$next[6:0]$14207 $2\core_asmcode$next[7:0]$14160 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + case + assign $2\core_asmcode$next[7:0]$14160 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$14161 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$14162 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14163 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14164 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14165 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14166 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14167 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14168 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14169 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14170 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14171 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14172 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$14173 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14174 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14175 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14176 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14177 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14178 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14179 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14180 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14181 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14182 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14183 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14184 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14185 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14186 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14187 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14188 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14189 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14190 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14191 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14192 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14193 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14194 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14195 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14196 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14197 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14198 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14199 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14200 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14201 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14202 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14203 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14204 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14205 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14206 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14207 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14208 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14209 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14210 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14211 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14212 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14213 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14214 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14215 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14216 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14217 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14218 \core_xer_out + end + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_core_is_32bit$next[0:0]$14118 $1\core_core_cr_wr_ok$next[0:0]$14133 $1\core_core_core_cr_wr$next[7:0]$14105 $1\core_core_core_cr_rd_ok$next[0:0]$14104 $1\core_core_core_cr_rd$next[7:0]$14103 $1\core_core_core_trapaddr$next[12:0]$14124 $1\core_core_core_exc_$signal$9$next[0:0]$14112 $1\core_core_core_exc_$signal$8$next[0:0]$14111 $1\core_core_core_exc_$signal$7$next[0:0]$14110 $1\core_core_core_exc_$signal$6$next[0:0]$14109 $1\core_core_core_exc_$signal$5$next[0:0]$14108 $1\core_core_core_exc_$signal$4$next[0:0]$14107 $1\core_core_core_exc_$signal$3$next[0:0]$14106 $1\core_core_core_exc_$signal$next[0:0]$14113 $1\core_core_core_traptype$next[7:0]$14125 $1\core_core_core_input_carry$next[1:0]$14115 $1\core_core_core_oe_ok$next[0:0]$14121 $1\core_core_core_oe$next[0:0]$14120 $1\core_core_core_rc_ok$next[0:0]$14123 $1\core_core_core_rc$next[0:0]$14122 $1\core_core_lk$next[0:0]$14141 $1\core_core_core_fn_unit$next[13:0]$14114 $1\core_core_core_insn_type$next[6:0]$14117 $1\core_core_core_insn$next[31:0]$14116 $1\core_core_core_cia$next[63:0]$14102 $1\core_core_core_msr$next[63:0]$14119 $1\core_cr_out_ok$next[0:0]$14153 $1\core_core_cr_out$next[6:0]$14132 $1\core_core_cr_in2_ok$2$next[0:0]$14130 $1\core_core_cr_in2$1$next[6:0]$14128 $1\core_core_cr_in2_ok$next[0:0]$14131 $1\core_core_cr_in2$next[6:0]$14129 $1\core_core_cr_in1_ok$next[0:0]$14127 $1\core_core_cr_in1$next[6:0]$14126 $1\core_fasto2_ok$next[0:0]$14156 $1\core_core_fasto2$next[2:0]$14140 $1\core_fasto1_ok$next[0:0]$14155 $1\core_core_fasto1$next[2:0]$14139 $1\core_core_fast2_ok$next[0:0]$14138 $1\core_core_fast2$next[2:0]$14137 $1\core_core_fast1_ok$next[0:0]$14136 $1\core_core_fast1$next[2:0]$14135 $1\core_xer_out$next[0:0]$14159 $1\core_core_xer_in$next[2:0]$14152 $1\core_core_spr1_ok$next[0:0]$14150 $1\core_core_spr1$next[9:0]$14149 $1\core_spro_ok$next[0:0]$14158 $1\core_core_spro$next[9:0]$14151 $1\core_core_reg3_ok$next[0:0]$14147 $1\core_core_reg3$next[6:0]$14146 $1\core_core_reg2_ok$next[0:0]$14145 $1\core_core_reg2$next[6:0]$14144 $1\core_core_reg1_ok$next[0:0]$14143 $1\core_core_reg1$next[6:0]$14142 $1\core_ea_ok$next[0:0]$14154 $1\core_core_ea$next[6:0]$14134 $1\core_rego_ok$next[0:0]$14157 $1\core_core_rego$next[6:0]$14148 $1\core_asmcode$next[7:0]$14101 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + case + assign $1\core_asmcode$next[7:0]$14101 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14102 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14103 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14105 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14113 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14114 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14115 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14116 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14117 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14118 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14119 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14120 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14121 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14122 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14123 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14124 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14125 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14126 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14127 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14128 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14129 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14131 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14132 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14133 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14134 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14135 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14136 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14137 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14138 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14139 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14140 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14141 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14142 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14143 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14144 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14145 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14146 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14147 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14148 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14149 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14150 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14151 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14152 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14153 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14154 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14155 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14156 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14157 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14158 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14159 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_rego_ok$next[0:0]$14244 1'0 + assign $3\core_ea_ok$next[0:0]$14241 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14236 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14237 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14238 1'0 + assign $3\core_spro_ok$next[0:0]$14245 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14239 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14234 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14235 1'0 + assign $3\core_fasto1_ok$next[0:0]$14242 1'0 + assign $3\core_fasto2_ok$next[0:0]$14243 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14230 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14232 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 1'0 + assign $3\core_cr_out_ok$next[0:0]$14240 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14229 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14228 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14227 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14233 1'0 + case + assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 $1\core_core_core_cr_rd_ok$next[0:0]$14104 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 $1\core_core_core_exc_$signal$3$next[0:0]$14106 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 $1\core_core_core_exc_$signal$4$next[0:0]$14107 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 $1\core_core_core_exc_$signal$5$next[0:0]$14108 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 $1\core_core_core_exc_$signal$6$next[0:0]$14109 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 $1\core_core_core_exc_$signal$7$next[0:0]$14110 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 $1\core_core_core_exc_$signal$8$next[0:0]$14111 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 $1\core_core_core_exc_$signal$9$next[0:0]$14112 + assign $3\core_core_core_exc_$signal$next[0:0]$14227 $1\core_core_core_exc_$signal$next[0:0]$14113 + assign $3\core_core_core_oe_ok$next[0:0]$14228 $1\core_core_core_oe_ok$next[0:0]$14121 + assign $3\core_core_core_rc_ok$next[0:0]$14229 $1\core_core_core_rc_ok$next[0:0]$14123 + assign $3\core_core_cr_in1_ok$next[0:0]$14230 $1\core_core_cr_in1_ok$next[0:0]$14127 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 $1\core_core_cr_in2_ok$2$next[0:0]$14130 + assign $3\core_core_cr_in2_ok$next[0:0]$14232 $1\core_core_cr_in2_ok$next[0:0]$14131 + assign $3\core_core_cr_wr_ok$next[0:0]$14233 $1\core_core_cr_wr_ok$next[0:0]$14133 + assign $3\core_core_fast1_ok$next[0:0]$14234 $1\core_core_fast1_ok$next[0:0]$14136 + assign $3\core_core_fast2_ok$next[0:0]$14235 $1\core_core_fast2_ok$next[0:0]$14138 + assign $3\core_core_reg1_ok$next[0:0]$14236 $1\core_core_reg1_ok$next[0:0]$14143 + assign $3\core_core_reg2_ok$next[0:0]$14237 $1\core_core_reg2_ok$next[0:0]$14145 + assign $3\core_core_reg3_ok$next[0:0]$14238 $1\core_core_reg3_ok$next[0:0]$14147 + assign $3\core_core_spr1_ok$next[0:0]$14239 $1\core_core_spr1_ok$next[0:0]$14150 + assign $3\core_cr_out_ok$next[0:0]$14240 $1\core_cr_out_ok$next[0:0]$14153 + assign $3\core_ea_ok$next[0:0]$14241 $1\core_ea_ok$next[0:0]$14154 + assign $3\core_fasto1_ok$next[0:0]$14242 $1\core_fasto1_ok$next[0:0]$14155 + assign $3\core_fasto2_ok$next[0:0]$14243 $1\core_fasto2_ok$next[0:0]$14156 + assign $3\core_rego_ok$next[0:0]$14244 $1\core_rego_ok$next[0:0]$14157 + assign $3\core_spro_ok$next[0:0]$14245 $1\core_spro_ok$next[0:0]$14158 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$14042 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14043 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14044 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14045 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14046 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14047 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14048 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14049 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14050 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14051 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14052 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14053 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14054 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$14055 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14056 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14057 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14058 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14059 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14060 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14061 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14062 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14063 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14064 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14065 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14066 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14067 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14068 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14069 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14070 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14071 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14072 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14073 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14074 + update \core_core_ea$next $0\core_core_ea$next[6:0]$14075 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14076 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14077 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14078 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14079 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14080 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14081 + update \core_core_lk$next $0\core_core_lk$next[0:0]$14082 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14083 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14084 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14085 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14086 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14087 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14088 + update \core_core_rego$next $0\core_core_rego$next[6:0]$14089 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14090 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14091 + update \core_core_spro$next $0\core_core_spro$next[9:0]$14092 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14093 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14094 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14095 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14096 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14097 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14098 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14099 + update \core_xer_out$next $0\core_xer_out$next[0:0]$14100 + end + connect \$101 $add$libresoc.v:197083$13545_Y + connect \$103 $mul$libresoc.v:197084$13546_Y + connect \$99 $shr$libresoc.v:197085$13547_Y [31:0] + connect \$106 $not$libresoc.v:197086$13548_Y + connect \$108 $not$libresoc.v:197087$13549_Y + connect \$110 $and$libresoc.v:197088$13550_Y + connect \$112 $not$libresoc.v:197089$13551_Y + connect \$114 $not$libresoc.v:197090$13552_Y + connect \$116 $and$libresoc.v:197091$13553_Y + connect \$118 $or$libresoc.v:197092$13554_Y + connect \$120 1'1 + connect \$122 $or$libresoc.v:197094$13555_Y + connect \$125 $add$libresoc.v:197095$13556_Y + connect \$128 $add$libresoc.v:197096$13557_Y + connect \$130 $not$libresoc.v:197097$13558_Y + connect \$132 $not$libresoc.v:197098$13559_Y + connect \$134 $and$libresoc.v:197099$13560_Y + connect \$136 $not$libresoc.v:197100$13561_Y + connect \$138 $not$libresoc.v:197101$13562_Y + connect \$140 $and$libresoc.v:197102$13563_Y + connect \$142 $eq$libresoc.v:197103$13564_Y + connect \$144 $and$libresoc.v:197104$13565_Y + connect \$146 $not$libresoc.v:197105$13566_Y + connect \$148 $not$libresoc.v:197106$13567_Y + connect \$150 $and$libresoc.v:197107$13568_Y + connect \$152 $or$libresoc.v:197108$13569_Y + connect \$154 1'1 + connect \$156 $or$libresoc.v:197110$13570_Y + connect \$158 $not$libresoc.v:197111$13571_Y + connect \$160 $not$libresoc.v:197112$13572_Y + connect \$162 $and$libresoc.v:197113$13573_Y + connect \$164 $not$libresoc.v:197114$13574_Y + connect \$166 $not$libresoc.v:197115$13575_Y + connect \$168 $and$libresoc.v:197116$13576_Y + connect \$170 $not$libresoc.v:197117$13577_Y + connect \$172 $not$libresoc.v:197118$13578_Y + connect \$174 $and$libresoc.v:197119$13579_Y + connect \$176 $not$libresoc.v:197120$13580_Y + connect \$178 $not$libresoc.v:197121$13581_Y + connect \$180 $and$libresoc.v:197122$13582_Y + connect \$182 $not$libresoc.v:197123$13583_Y + connect \$184 $not$libresoc.v:197124$13584_Y + connect \$186 $and$libresoc.v:197125$13585_Y + connect \$188 $not$libresoc.v:197126$13586_Y + connect \$190 $not$libresoc.v:197127$13587_Y + connect \$192 $and$libresoc.v:197128$13588_Y + connect \$195 $and$libresoc.v:197129$13589_Y + connect \$194 $reduce_or$libresoc.v:197130$13590_Y + connect \$198 $not$libresoc.v:197131$13591_Y + connect \$200 $not$libresoc.v:197132$13592_Y + connect \$202 $and$libresoc.v:197133$13593_Y + connect \$204 $not$libresoc.v:197134$13594_Y + connect \$206 $not$libresoc.v:197135$13595_Y + connect \$208 $and$libresoc.v:197136$13596_Y + connect \$210 $or$libresoc.v:197137$13597_Y + connect \$212 1'1 + connect \$214 $or$libresoc.v:197139$13598_Y + connect \$216 $not$libresoc.v:197140$13599_Y + connect \$218 $not$libresoc.v:197141$13600_Y + connect \$220 $and$libresoc.v:197142$13601_Y + connect \$222 $not$libresoc.v:197143$13602_Y + connect \$224 $not$libresoc.v:197144$13603_Y + connect \$226 $and$libresoc.v:197145$13604_Y + connect \$229 $and$libresoc.v:197146$13605_Y + connect \$228 $reduce_or$libresoc.v:197147$13606_Y + connect \$232 $eq$libresoc.v:197148$13607_Y + connect \$234 $and$libresoc.v:197149$13608_Y + connect \$236 $not$libresoc.v:197150$13609_Y + connect \$238 $not$libresoc.v:197151$13610_Y + connect \$23 $ne$libresoc.v:197152$13611_Y + connect \$240 $not$libresoc.v:197153$13612_Y + connect \$242 $and$libresoc.v:197154$13613_Y + connect \$244 $not$libresoc.v:197155$13614_Y + connect \$246 $not$libresoc.v:197156$13615_Y + connect \$248 $and$libresoc.v:197157$13616_Y + connect \$250 $eq$libresoc.v:197158$13617_Y + connect \$252 $pos$libresoc.v:197159$13618_Y + connect \$254 $ne$libresoc.v:197160$13619_Y + connect \$256 $not$libresoc.v:197161$13620_Y + connect \$258 $not$libresoc.v:197162$13621_Y + connect \$260 $pos$libresoc.v:197163$13623_Y + connect \$262 $pos$libresoc.v:197164$13625_Y + connect \$265 $sub$libresoc.v:197165$13626_Y + connect \$268 $add$libresoc.v:197166$13627_Y + connect \$26 $sub$libresoc.v:197167$13628_Y + connect \$28 $or$libresoc.v:197168$13629_Y + connect \$30 $or$libresoc.v:197169$13630_Y + connect \$32 $ne$libresoc.v:197170$13631_Y + connect \$34 $not$libresoc.v:197171$13632_Y + connect \$36 $and$libresoc.v:197172$13633_Y + connect \$38 $not$libresoc.v:197173$13634_Y + connect \$40 $not$libresoc.v:197174$13635_Y + connect \$42 $pos$libresoc.v:197175$13637_Y + connect \$44 $not$libresoc.v:197176$13638_Y + connect \$46 $not$libresoc.v:197177$13639_Y + connect \$48 $and$libresoc.v:197178$13640_Y + connect \$50 $eq$libresoc.v:197179$13641_Y + connect \$52 $and$libresoc.v:197180$13642_Y + connect \$54 $not$libresoc.v:197181$13643_Y + connect \$56 $not$libresoc.v:197182$13644_Y + connect \$58 $and$libresoc.v:197183$13645_Y + connect \$60 $or$libresoc.v:197184$13646_Y + connect \$62 1'1 + connect \$64 $or$libresoc.v:197186$13647_Y + connect \$66 $not$libresoc.v:197187$13648_Y + connect \$68 $not$libresoc.v:197188$13649_Y + connect \$70 $and$libresoc.v:197189$13650_Y + connect \$72 $eq$libresoc.v:197190$13651_Y + connect \$74 $and$libresoc.v:197191$13652_Y + connect \$76 $not$libresoc.v:197192$13653_Y + connect \$78 $not$libresoc.v:197193$13654_Y + connect \$80 $and$libresoc.v:197194$13655_Y + connect \$82 $or$libresoc.v:197195$13656_Y + connect \$84 1'1 + connect \$86 $or$libresoc.v:197197$13657_Y + connect \$88 $not$libresoc.v:197198$13658_Y + connect \$90 $not$libresoc.v:197199$13659_Y + connect \$93 $add$libresoc.v:197200$13660_Y + connect \$96 $mul$libresoc.v:197201$13661_Y + connect \$95 $shr$libresoc.v:197202$13662_Y [31:0] + connect \$25 \$26 + connect \$92 \$93 + connect \$100 \$101 + connect \$124 \$125 + connect \$127 \$128 + connect \$264 \$265 + connect \$267 \$268 + connect \dec2_sv_a_nz 1'0 + connect \svstate_i_ok 1'0 + connect \svstate_i 0 + connect \is_svp64_mode 1'0 + connect \pred_insn_ready_o 1'0 + connect \pred_mask_valid_o 1'0 + connect \next_dststep \$128 [6:0] + connect \next_srcstep \$125 [6:0] + connect \dbg_core_dbg_msr \dec2_cur_msr + connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0] + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i \core_core_terminate_o + connect \pc_o \dec2_cur_pc + connect \core_cu_st__go_i \cu_st__rel_o_rise + connect \core_cu_ad__go_i \core_cu_ad__rel_o + connect \cu_st__rel_o_rise \$36 + connect \cu_st__rel_o_dly$next \core_cu_st__rel_o + connect \dec2_bigendian \core_bigendian_i + connect \busy_o \core_corebusy_o + connect \core_coresync_rst \ti_rst + connect \ti_rst \$32 + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } + connect \sram4k_3_enable \jtag_wb_sram_en + connect \sram4k_2_enable \jtag_wb_sram_en + connect \sram4k_1_enable \jtag_wb_sram_en + connect \sram4k_0_enable \jtag_wb_sram_en +end +attribute \src "libresoc.v:199862.1-201053.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" +attribute \generator "nMigen" +module \trap0 + attribute \src "libresoc.v:200598.3-200599.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:200596.3-200597.41" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:200956.3-200964.6" + wire $0\alu_l_r_alu$next[0:0]$14567 + attribute \src "libresoc.v:200524.3-200525.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14493 + attribute \src "libresoc.v:200564.3-200565.61" + wire width 64 $0\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 + attribute \src "libresoc.v:200558.3-200559.69" + wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14495 + attribute \src "libresoc.v:200560.3-200561.63" + wire width 32 $0\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 + attribute \src "libresoc.v:200556.3-200557.73" + wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 + attribute \src "libresoc.v:200566.3-200567.71" + wire $0\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 + attribute \src "libresoc.v:200572.3-200573.71" + wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14499 + attribute \src "libresoc.v:200562.3-200563.61" + wire width 64 $0\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 + attribute \src "libresoc.v:200570.3-200571.71" + wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14501 + attribute \src "libresoc.v:200568.3-200569.71" + wire width 8 $0\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:200947.3-200955.6" + wire $0\alui_l_r_alui$next[0:0]$14564 + attribute \src "libresoc.v:200526.3-200527.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $0\data_r0__o$next[63:0]$14512 + attribute \src "libresoc.v:200552.3-200553.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:200797.3-200818.6" + wire $0\data_r0__o_ok$next[0:0]$14513 + attribute \src "libresoc.v:200554.3-200555.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14520 + attribute \src "libresoc.v:200548.3-200549.45" + wire width 64 $0\data_r1__fast1[63:0] + attribute \src "libresoc.v:200819.3-200840.6" + wire $0\data_r1__fast1_ok$next[0:0]$14521 + attribute \src "libresoc.v:200550.3-200551.51" + wire $0\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14528 + attribute \src "libresoc.v:200544.3-200545.45" + wire width 64 $0\data_r2__fast2[63:0] + attribute \src "libresoc.v:200841.3-200862.6" + wire $0\data_r2__fast2_ok$next[0:0]$14529 + attribute \src "libresoc.v:200546.3-200547.51" + wire $0\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $0\data_r3__nia$next[63:0]$14536 + attribute \src "libresoc.v:200540.3-200541.41" + wire width 64 $0\data_r3__nia[63:0] + attribute \src "libresoc.v:200863.3-200884.6" + wire $0\data_r3__nia_ok$next[0:0]$14537 + attribute \src "libresoc.v:200542.3-200543.47" + wire $0\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $0\data_r4__msr$next[63:0]$14544 + attribute \src "libresoc.v:200536.3-200537.41" + wire width 64 $0\data_r4__msr[63:0] + attribute \src "libresoc.v:200885.3-200906.6" + wire $0\data_r4__msr_ok$next[0:0]$14545 + attribute \src "libresoc.v:200538.3-200539.47" + wire $0\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:200965.3-200974.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:200975.3-200984.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:200985.3-200994.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:200995.3-201004.6" + wire width 64 $0\dest4_o[63:0] + attribute \src "libresoc.v:201005.3-201014.6" + wire width 64 $0\dest5_o[63:0] + attribute \src "libresoc.v:199863.7-199863.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:200734.3-200742.6" + wire $0\opc_l_r_opc$next[0:0]$14478 + attribute \src "libresoc.v:200582.3-200583.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:200725.3-200733.6" + wire $0\opc_l_s_opc$next[0:0]$14475 + attribute \src "libresoc.v:200584.3-200585.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:201015.3-201023.6" + wire width 5 $0\prev_wr_go$next[4:0]$14575 + attribute \src "libresoc.v:200594.3-200595.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:200679.3-200688.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:200770.3-200778.6" + wire width 5 $0\req_l_r_req$next[4:0]$14490 + attribute \src "libresoc.v:200574.3-200575.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:200761.3-200769.6" + wire width 5 $0\req_l_s_req$next[4:0]$14487 + attribute \src "libresoc.v:200576.3-200577.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:200698.3-200706.6" + wire $0\rok_l_r_rdok$next[0:0]$14466 + attribute \src "libresoc.v:200590.3-200591.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:200689.3-200697.6" + wire $0\rok_l_s_rdok$next[0:0]$14463 + attribute \src "libresoc.v:200592.3-200593.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:200716.3-200724.6" + wire $0\rst_l_r_rst$next[0:0]$14472 + attribute \src "libresoc.v:200586.3-200587.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:200707.3-200715.6" + wire $0\rst_l_s_rst$next[0:0]$14469 + attribute \src "libresoc.v:200588.3-200589.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:200752.3-200760.6" + wire width 4 $0\src_l_r_src$next[3:0]$14484 + attribute \src "libresoc.v:200578.3-200579.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:200743.3-200751.6" + wire width 4 $0\src_l_s_src$next[3:0]$14481 + attribute \src "libresoc.v:200580.3-200581.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:200907.3-200916.6" + wire width 64 $0\src_r0$next[63:0]$14552 + attribute \src "libresoc.v:200534.3-200535.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:200917.3-200926.6" + wire width 64 $0\src_r1$next[63:0]$14555 + attribute \src "libresoc.v:200532.3-200533.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:200927.3-200936.6" + wire width 64 $0\src_r2$next[63:0]$14558 + attribute \src "libresoc.v:200530.3-200531.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:200937.3-200946.6" + wire width 64 $0\src_r3$next[63:0]$14561 + attribute \src "libresoc.v:200528.3-200529.29" + wire width 64 $0\src_r3[63:0] + attribute \src "libresoc.v:199989.7-199989.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:199999.7-199999.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:200956.3-200964.6" + wire $1\alu_l_r_alu$next[0:0]$14568 + attribute \src "libresoc.v:200007.7-200007.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14502 + attribute \src "libresoc.v:200043.14-200043.59" + wire width 64 $1\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 + attribute \src "libresoc.v:200062.14-200062.51" + wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14504 + attribute \src "libresoc.v:200066.14-200066.45" + wire width 32 $1\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 + attribute \src "libresoc.v:200145.13-200145.49" + wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 + attribute \src "libresoc.v:200149.7-200149.41" + wire $1\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 + attribute \src "libresoc.v:200153.13-200153.48" + wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14508 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:200522$14421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$93 + connect \B 4'1111 + connect \Y $and$libresoc.v:200522$14421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:200495$14394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:200495$14394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:200497$14396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:200497$14396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:200478$14377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:200478$14377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:200480$14379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:200480$14379_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:200483$14382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:200483$14382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:200486$14385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:200486$14385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:200492$14391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_ready_i + connect \Y $not$libresoc.v:200492$14391_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:200507$14406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:200507$14406_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:200523$14422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:200523$14422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:200490$14389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:200490$14389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:200501$14400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:200501$14400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:200502$14401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:200502$14401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:200503$14402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:200503$14402_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:200504$14403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:200504$14403_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:200508$14407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:200508$14407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:200518$14417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:200518$14417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:200463$14362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:200463$14362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:200485$14384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:200485$14384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:200488$14387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:200488$14387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:200489$14388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:200489$14388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:200514$14413 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:200514$14413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:200515$14414 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:200515$14414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:200516$14415 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:200516$14415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:200517$14416 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:200517$14416_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200600.14-200606.4" + cell \alu_l$45 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200607.13-200637.4" + cell \alu_trap0 \alu_trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_trap0_fast1 + connect \fast1$1 \alu_trap0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_trap0_fast2 + connect \fast2$2 \alu_trap0_fast2$2 + connect \fast2_ok \fast2_ok + connect \msr \alu_trap0_msr + connect \msr_ok \msr_ok + connect \n_ready_i \alu_trap0_n_ready_i + connect \n_valid_o \alu_trap0_n_valid_o + connect \nia \alu_trap0_nia + connect \nia_ok \nia_ok + connect \o \alu_trap0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_trap0_p_ready_o + connect \p_valid_i \alu_trap0_p_valid_i + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \trap_op__cia \alu_trap0_trap_op__cia + connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit + connect \trap_op__insn \alu_trap0_trap_op__insn + connect \trap_op__insn_type \alu_trap0_trap_op__insn_type + connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__ldst_exc \alu_trap0_trap_op__ldst_exc + connect \trap_op__msr \alu_trap0_trap_op__msr + connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr + connect \trap_op__traptype \alu_trap0_trap_op__traptype + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200638.15-200644.4" + cell \alui_l$44 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200645.14-200651.4" + cell \opc_l$40 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200652.14-200658.4" + cell \req_l$41 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200659.14-200665.4" + cell \rok_l$43 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200666.14-200671.4" + cell \rst_l$42 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200672.14-200678.4" + cell \src_l$39 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:199863.7-199863.20" + process $proc$libresoc.v:199863$14577 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:199989.7-199989.24" + process $proc$libresoc.v:199989$14578 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:199999.7-199999.26" + process $proc$libresoc.v:199999$14579 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:200007.7-200007.25" + process $proc$libresoc.v:200007$14580 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:200043.14-200043.59" + process $proc$libresoc.v:200043$14581 + assign { } { } + assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] + end + attribute \src "libresoc.v:200062.14-200062.51" + process $proc$libresoc.v:200062$14582 + assign { } { } + assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 + sync always + sync init + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] + end + attribute \src "libresoc.v:200066.14-200066.45" + process $proc$libresoc.v:200066$14583 + assign { } { } + assign $1\alu_trap0_trap_op__insn[31:0] 0 + sync always + sync init + update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] + end + attribute \src "libresoc.v:200145.13-200145.49" + process $proc$libresoc.v:200145$14584 + assign { } { } + assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:200149.7-200149.41" + process $proc$libresoc.v:200149$14585 + assign { } { } + assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:200153.13-200153.48" + process $proc$libresoc.v:200153$14586 + assign { } { } + assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 + sync always + sync init + update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:200157.14-200157.59" + process $proc$libresoc.v:200157$14587 + assign { } { } + assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] + end + attribute \src "libresoc.v:200161.14-200161.52" + process $proc$libresoc.v:200161$14588 + assign { } { } + assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:200165.13-200165.48" + process $proc$libresoc.v:200165$14589 + assign { } { } + assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 + sync always + sync init + update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] + end + attribute \src "libresoc.v:200171.7-200171.27" + process $proc$libresoc.v:200171$14590 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:200203.14-200203.47" + process $proc$libresoc.v:200203$14591 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:200207.7-200207.27" + process $proc$libresoc.v:200207$14592 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:200211.14-200211.51" + process $proc$libresoc.v:200211$14593 + assign { } { } + assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast1 $1\data_r1__fast1[63:0] + end + attribute \src "libresoc.v:200215.7-200215.31" + process $proc$libresoc.v:200215$14594 + assign { } { } + assign $1\data_r1__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] + end + attribute \src "libresoc.v:200219.14-200219.51" + process $proc$libresoc.v:200219$14595 + assign { } { } + assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast2 $1\data_r2__fast2[63:0] + end + attribute \src "libresoc.v:200223.7-200223.31" + process $proc$libresoc.v:200223$14596 + assign { } { } + assign $1\data_r2__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] + end + attribute \src "libresoc.v:200227.14-200227.49" + process $proc$libresoc.v:200227$14597 + assign { } { } + assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r3__nia $1\data_r3__nia[63:0] + end + attribute \src "libresoc.v:200231.7-200231.29" + process $proc$libresoc.v:200231$14598 + assign { } { } + assign $1\data_r3__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] + end + attribute \src "libresoc.v:200235.14-200235.49" + process $proc$libresoc.v:200235$14599 + assign { } { } + assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r4__msr $1\data_r4__msr[63:0] + end + attribute \src "libresoc.v:200239.7-200239.29" + process $proc$libresoc.v:200239$14600 + assign { } { } + assign $1\data_r4__msr_ok[0:0] 1'0 + sync always + sync init + update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] + end + attribute \src "libresoc.v:200270.7-200270.25" + process $proc$libresoc.v:200270$14601 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:200274.7-200274.25" + process $proc$libresoc.v:200274$14602 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:200386.13-200386.31" + process $proc$libresoc.v:200386$14603 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:200394.13-200394.32" + process $proc$libresoc.v:200394$14604 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:200398.13-200398.32" + process $proc$libresoc.v:200398$14605 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:200410.7-200410.26" + process $proc$libresoc.v:200410$14606 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:200414.7-200414.26" + process $proc$libresoc.v:200414$14607 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:200418.7-200418.25" + process $proc$libresoc.v:200418$14608 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:200422.7-200422.25" + process $proc$libresoc.v:200422$14609 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:200438.13-200438.31" + process $proc$libresoc.v:200438$14610 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:200442.13-200442.31" + process $proc$libresoc.v:200442$14611 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:200446.14-200446.43" + process $proc$libresoc.v:200446$14612 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:200450.14-200450.43" + process $proc$libresoc.v:200450$14613 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:200454.14-200454.43" + process $proc$libresoc.v:200454$14614 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:200458.14-200458.43" + process $proc$libresoc.v:200458$14615 + assign { } { } + assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r3 $1\src_r3[63:0] + end + attribute \src "libresoc.v:200524.3-200525.39" + process $proc$libresoc.v:200524$14423 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:200526.3-200527.43" + process $proc$libresoc.v:200526$14424 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:200528.3-200529.29" + process $proc$libresoc.v:200528$14425 + assign { } { } + assign $0\src_r3[63:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[63:0] + end + attribute \src "libresoc.v:200530.3-200531.29" + process $proc$libresoc.v:200530$14426 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:200532.3-200533.29" + process $proc$libresoc.v:200532$14427 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:200534.3-200535.29" + process $proc$libresoc.v:200534$14428 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:200536.3-200537.41" + process $proc$libresoc.v:200536$14429 + assign { } { } + assign $0\data_r4__msr[63:0] \data_r4__msr$next + sync posedge \coresync_clk + update \data_r4__msr $0\data_r4__msr[63:0] + end + attribute \src "libresoc.v:200538.3-200539.47" + process $proc$libresoc.v:200538$14430 + assign { } { } + assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next + sync posedge \coresync_clk + update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] + end + attribute \src "libresoc.v:200540.3-200541.41" + process $proc$libresoc.v:200540$14431 + assign { } { } + assign $0\data_r3__nia[63:0] \data_r3__nia$next + sync posedge \coresync_clk + update \data_r3__nia $0\data_r3__nia[63:0] + end + attribute \src "libresoc.v:200542.3-200543.47" + process $proc$libresoc.v:200542$14432 + assign { } { } + assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next + sync posedge \coresync_clk + update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] + end + attribute \src "libresoc.v:200544.3-200545.45" + process $proc$libresoc.v:200544$14433 + assign { } { } + assign $0\data_r2__fast2[63:0] \data_r2__fast2$next + sync posedge \coresync_clk + update \data_r2__fast2 $0\data_r2__fast2[63:0] + end + attribute \src "libresoc.v:200546.3-200547.51" + process $proc$libresoc.v:200546$14434 + assign { } { } + assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next + sync posedge \coresync_clk + update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] + end + attribute \src "libresoc.v:200548.3-200549.45" + process $proc$libresoc.v:200548$14435 + assign { } { } + assign $0\data_r1__fast1[63:0] \data_r1__fast1$next + sync posedge \coresync_clk + update \data_r1__fast1 $0\data_r1__fast1[63:0] + end + attribute \src "libresoc.v:200550.3-200551.51" + process $proc$libresoc.v:200550$14436 + assign { } { } + assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next + sync posedge \coresync_clk + update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] + end + attribute \src "libresoc.v:200552.3-200553.37" + process $proc$libresoc.v:200552$14437 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:200554.3-200555.43" + process $proc$libresoc.v:200554$14438 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:200556.3-200557.73" + process $proc$libresoc.v:200556$14439 + assign { } { } + assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:200558.3-200559.69" + process $proc$libresoc.v:200558$14440 + assign { } { } + assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] + end + attribute \src "libresoc.v:200560.3-200561.63" + process $proc$libresoc.v:200560$14441 + assign { } { } + assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] + end + attribute \src "libresoc.v:200562.3-200563.61" + process $proc$libresoc.v:200562$14442 + assign { } { } + assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] + end + attribute \src "libresoc.v:200564.3-200565.61" + process $proc$libresoc.v:200564$14443 + assign { } { } + assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] + end + attribute \src "libresoc.v:200566.3-200567.71" + process $proc$libresoc.v:200566$14444 + assign { } { } + assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:200568.3-200569.71" + process $proc$libresoc.v:200568$14445 + assign { } { } + assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] + end + attribute \src "libresoc.v:200570.3-200571.71" + process $proc$libresoc.v:200570$14446 + assign { } { } + assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:200572.3-200573.71" + process $proc$libresoc.v:200572$14447 + assign { } { } + assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:200574.3-200575.39" + process $proc$libresoc.v:200574$14448 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:200576.3-200577.39" + process $proc$libresoc.v:200576$14449 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:200578.3-200579.39" + process $proc$libresoc.v:200578$14450 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:200580.3-200581.39" + process $proc$libresoc.v:200580$14451 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:200582.3-200583.39" + process $proc$libresoc.v:200582$14452 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:200584.3-200585.39" + process $proc$libresoc.v:200584$14453 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:200586.3-200587.39" + process $proc$libresoc.v:200586$14454 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:200588.3-200589.39" + process $proc$libresoc.v:200588$14455 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:200590.3-200591.41" + process $proc$libresoc.v:200590$14456 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:200592.3-200593.41" + process $proc$libresoc.v:200592$14457 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:200594.3-200595.37" + process $proc$libresoc.v:200594$14458 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:200596.3-200597.41" + process $proc$libresoc.v:200596$14459 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:200598.3-200599.25" + process $proc$libresoc.v:200598$14460 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:200679.3-200688.6" + process $proc$libresoc.v:200679$14461 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:200680.5-200680.29" + switch \initial + attribute \src "libresoc.v:200680.9-200680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:200689.3-200697.6" + process $proc$libresoc.v:200689$14462 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$14463 $1\rok_l_s_rdok$next[0:0]$14464 + attribute \src "libresoc.v:200690.5-200690.29" + switch \initial + attribute \src "libresoc.v:200690.9-200690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$14464 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$14464 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14463 + end + attribute \src "libresoc.v:200698.3-200706.6" + process $proc$libresoc.v:200698$14465 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$14466 $1\rok_l_r_rdok$next[0:0]$14467 + attribute \src "libresoc.v:200699.5-200699.29" + switch \initial + attribute \src "libresoc.v:200699.9-200699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$14467 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$14467 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14466 + end + attribute \src "libresoc.v:200707.3-200715.6" + process $proc$libresoc.v:200707$14468 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$14469 $1\rst_l_s_rst$next[0:0]$14470 + attribute \src "libresoc.v:200708.5-200708.29" + switch \initial + attribute \src "libresoc.v:200708.9-200708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$14470 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$14470 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14469 + end + attribute \src "libresoc.v:200716.3-200724.6" + process $proc$libresoc.v:200716$14471 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$14472 $1\rst_l_r_rst$next[0:0]$14473 + attribute \src "libresoc.v:200717.5-200717.29" + switch \initial + attribute \src "libresoc.v:200717.9-200717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$14473 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$14473 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14472 + end + attribute \src "libresoc.v:200725.3-200733.6" + process $proc$libresoc.v:200725$14474 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$14475 $1\opc_l_s_opc$next[0:0]$14476 + attribute \src "libresoc.v:200726.5-200726.29" + switch \initial + attribute \src "libresoc.v:200726.9-200726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$14476 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$14476 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14475 + end + attribute \src "libresoc.v:200734.3-200742.6" + process $proc$libresoc.v:200734$14477 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$14478 $1\opc_l_r_opc$next[0:0]$14479 + attribute \src "libresoc.v:200735.5-200735.29" + switch \initial + attribute \src "libresoc.v:200735.9-200735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$14479 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$14479 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14478 + end + attribute \src "libresoc.v:200743.3-200751.6" + process $proc$libresoc.v:200743$14480 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$14481 $1\src_l_s_src$next[3:0]$14482 + attribute \src "libresoc.v:200744.5-200744.29" + switch \initial + attribute \src "libresoc.v:200744.9-200744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$14482 4'0000 + case + assign $1\src_l_s_src$next[3:0]$14482 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14481 + end + attribute \src "libresoc.v:200752.3-200760.6" + process $proc$libresoc.v:200752$14483 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$14484 $1\src_l_r_src$next[3:0]$14485 + attribute \src "libresoc.v:200753.5-200753.29" + switch \initial + attribute \src "libresoc.v:200753.9-200753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$14485 4'1111 + case + assign $1\src_l_r_src$next[3:0]$14485 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14484 + end + attribute \src "libresoc.v:200761.3-200769.6" + process $proc$libresoc.v:200761$14486 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$14487 $1\req_l_s_req$next[4:0]$14488 + attribute \src "libresoc.v:200762.5-200762.29" + switch \initial + attribute \src "libresoc.v:200762.9-200762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$14488 5'00000 + case + assign $1\req_l_s_req$next[4:0]$14488 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14487 + end + attribute \src "libresoc.v:200770.3-200778.6" + process $proc$libresoc.v:200770$14489 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$14490 $1\req_l_r_req$next[4:0]$14491 + attribute \src "libresoc.v:200771.5-200771.29" + switch \initial + attribute \src "libresoc.v:200771.9-200771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$14491 5'11111 + case + assign $1\req_l_r_req$next[4:0]$14491 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14490 + end + attribute \src "libresoc.v:200779.3-200796.6" + process $proc$libresoc.v:200779$14492 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_trap0_trap_op__cia$next[63:0]$14493 $1\alu_trap0_trap_op__cia$next[63:0]$14502 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14495 $1\alu_trap0_trap_op__insn$next[31:0]$14504 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14499 $1\alu_trap0_trap_op__msr$next[63:0]$14508 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14501 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 + attribute \src "libresoc.v:200780.5-200780.29" + switch \initial + attribute \src "libresoc.v:200780.9-200780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 $1\alu_trap0_trap_op__cia$next[63:0]$14502 $1\alu_trap0_trap_op__msr$next[63:0]$14508 $1\alu_trap0_trap_op__insn$next[31:0]$14504 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + case + assign $1\alu_trap0_trap_op__cia$next[63:0]$14502 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14504 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14508 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14510 \alu_trap0_trap_op__traptype + end + sync always + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14493 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14495 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14499 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14501 + end + attribute \src "libresoc.v:200797.3-200818.6" + process $proc$libresoc.v:200797$14511 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$14512 $2\data_r0__o$next[63:0]$14516 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$14513 $3\data_r0__o_ok$next[0:0]$14518 + attribute \src "libresoc.v:200798.5-200798.29" + switch \initial + attribute \src "libresoc.v:200798.9-200798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$14515 $1\data_r0__o$next[63:0]$14514 } { \o_ok \alu_trap0_o } + case + assign $1\data_r0__o$next[63:0]$14514 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14515 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$14517 $2\data_r0__o$next[63:0]$14516 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$14516 $1\data_r0__o$next[63:0]$14514 + assign $2\data_r0__o_ok$next[0:0]$14517 $1\data_r0__o_ok$next[0:0]$14515 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$14518 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$14518 $2\data_r0__o_ok$next[0:0]$14517 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$14512 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14513 + end + attribute \src "libresoc.v:200819.3-200840.6" + process $proc$libresoc.v:200819$14519 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast1$next[63:0]$14520 $2\data_r1__fast1$next[63:0]$14524 + assign { } { } + assign $0\data_r1__fast1_ok$next[0:0]$14521 $3\data_r1__fast1_ok$next[0:0]$14526 + attribute \src "libresoc.v:200820.5-200820.29" + switch \initial + attribute \src "libresoc.v:200820.9-200820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast1_ok$next[0:0]$14523 $1\data_r1__fast1$next[63:0]$14522 } { \fast1_ok \alu_trap0_fast1 } + case + assign $1\data_r1__fast1$next[63:0]$14522 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14523 \data_r1__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast1_ok$next[0:0]$14525 $2\data_r1__fast1$next[63:0]$14524 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast1$next[63:0]$14524 $1\data_r1__fast1$next[63:0]$14522 + assign $2\data_r1__fast1_ok$next[0:0]$14525 $1\data_r1__fast1_ok$next[0:0]$14523 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast1_ok$next[0:0]$14526 1'0 + case + assign $3\data_r1__fast1_ok$next[0:0]$14526 $2\data_r1__fast1_ok$next[0:0]$14525 + end + sync always + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14520 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14521 + end + attribute \src "libresoc.v:200841.3-200862.6" + process $proc$libresoc.v:200841$14527 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast2$next[63:0]$14528 $2\data_r2__fast2$next[63:0]$14532 + assign { } { } + assign $0\data_r2__fast2_ok$next[0:0]$14529 $3\data_r2__fast2_ok$next[0:0]$14534 + attribute \src "libresoc.v:200842.5-200842.29" + switch \initial + attribute \src "libresoc.v:200842.9-200842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast2_ok$next[0:0]$14531 $1\data_r2__fast2$next[63:0]$14530 } { \fast2_ok \alu_trap0_fast2 } + case + assign $1\data_r2__fast2$next[63:0]$14530 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14531 \data_r2__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast2_ok$next[0:0]$14533 $2\data_r2__fast2$next[63:0]$14532 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast2$next[63:0]$14532 $1\data_r2__fast2$next[63:0]$14530 + assign $2\data_r2__fast2_ok$next[0:0]$14533 $1\data_r2__fast2_ok$next[0:0]$14531 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast2_ok$next[0:0]$14534 1'0 + case + assign $3\data_r2__fast2_ok$next[0:0]$14534 $2\data_r2__fast2_ok$next[0:0]$14533 + end + sync always + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14528 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14529 + end + attribute \src "libresoc.v:200863.3-200884.6" + process $proc$libresoc.v:200863$14535 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__nia$next[63:0]$14536 $2\data_r3__nia$next[63:0]$14540 + assign { } { } + assign $0\data_r3__nia_ok$next[0:0]$14537 $3\data_r3__nia_ok$next[0:0]$14542 + attribute \src "libresoc.v:200864.5-200864.29" + switch \initial + attribute \src "libresoc.v:200864.9-200864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__nia_ok$next[0:0]$14539 $1\data_r3__nia$next[63:0]$14538 } { \nia_ok \alu_trap0_nia } + case + assign $1\data_r3__nia$next[63:0]$14538 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14539 \data_r3__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__nia_ok$next[0:0]$14541 $2\data_r3__nia$next[63:0]$14540 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r3__nia$next[63:0]$14540 $1\data_r3__nia$next[63:0]$14538 + assign $2\data_r3__nia_ok$next[0:0]$14541 $1\data_r3__nia_ok$next[0:0]$14539 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__nia_ok$next[0:0]$14542 1'0 + case + assign $3\data_r3__nia_ok$next[0:0]$14542 $2\data_r3__nia_ok$next[0:0]$14541 + end + sync always + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14536 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14537 + end + attribute \src "libresoc.v:200885.3-200906.6" + process $proc$libresoc.v:200885$14543 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__msr$next[63:0]$14544 $2\data_r4__msr$next[63:0]$14548 + assign { } { } + assign $0\data_r4__msr_ok$next[0:0]$14545 $3\data_r4__msr_ok$next[0:0]$14550 + attribute \src "libresoc.v:200886.5-200886.29" + switch \initial + attribute \src "libresoc.v:200886.9-200886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__msr_ok$next[0:0]$14547 $1\data_r4__msr$next[63:0]$14546 } { \msr_ok \alu_trap0_msr } + case + assign $1\data_r4__msr$next[63:0]$14546 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14547 \data_r4__msr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__msr_ok$next[0:0]$14549 $2\data_r4__msr$next[63:0]$14548 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r4__msr$next[63:0]$14548 $1\data_r4__msr$next[63:0]$14546 + assign $2\data_r4__msr_ok$next[0:0]$14549 $1\data_r4__msr_ok$next[0:0]$14547 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__msr_ok$next[0:0]$14550 1'0 + case + assign $3\data_r4__msr_ok$next[0:0]$14550 $2\data_r4__msr_ok$next[0:0]$14549 + end + sync always + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14544 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14545 + end + attribute \src "libresoc.v:200907.3-200916.6" + process $proc$libresoc.v:200907$14551 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$14552 $1\src_r0$next[63:0]$14553 + attribute \src "libresoc.v:200908.5-200908.29" + switch \initial + attribute \src "libresoc.v:200908.9-200908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$14553 \src1_i + case + assign $1\src_r0$next[63:0]$14553 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$14552 + end + attribute \src "libresoc.v:200917.3-200926.6" + process $proc$libresoc.v:200917$14554 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$14555 $1\src_r1$next[63:0]$14556 + attribute \src "libresoc.v:200918.5-200918.29" + switch \initial + attribute \src "libresoc.v:200918.9-200918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$14556 \src2_i + case + assign $1\src_r1$next[63:0]$14556 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$14555 + end + attribute \src "libresoc.v:200927.3-200936.6" + process $proc$libresoc.v:200927$14557 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$14558 $1\src_r2$next[63:0]$14559 + attribute \src "libresoc.v:200928.5-200928.29" + switch \initial + attribute \src "libresoc.v:200928.9-200928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$14559 \src3_i + case + assign $1\src_r2$next[63:0]$14559 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$14558 + end + attribute \src "libresoc.v:200937.3-200946.6" + process $proc$libresoc.v:200937$14560 + assign { } { } + assign { } { } + assign $0\src_r3$next[63:0]$14561 $1\src_r3$next[63:0]$14562 + attribute \src "libresoc.v:200938.5-200938.29" + switch \initial + attribute \src "libresoc.v:200938.9-200938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[63:0]$14562 \src4_i + case + assign $1\src_r3$next[63:0]$14562 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[63:0]$14561 + end + attribute \src "libresoc.v:200947.3-200955.6" + process $proc$libresoc.v:200947$14563 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$14564 $1\alui_l_r_alui$next[0:0]$14565 + attribute \src "libresoc.v:200948.5-200948.29" + switch \initial + attribute \src "libresoc.v:200948.9-200948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$14565 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$14565 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14564 + end + attribute \src "libresoc.v:200956.3-200964.6" + process $proc$libresoc.v:200956$14566 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$14567 $1\alu_l_r_alu$next[0:0]$14568 + attribute \src "libresoc.v:200957.5-200957.29" + switch \initial + attribute \src "libresoc.v:200957.9-200957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$14568 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$14568 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14567 + end + attribute \src "libresoc.v:200965.3-200974.6" + process $proc$libresoc.v:200965$14569 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:200966.5-200966.29" + switch \initial + attribute \src "libresoc.v:200966.9-200966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:200975.3-200984.6" + process $proc$libresoc.v:200975$14570 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:200976.5-200976.29" + switch \initial + attribute \src "libresoc.v:200976.9-200976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:200985.3-200994.6" + process $proc$libresoc.v:200985$14571 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:200986.5-200986.29" + switch \initial + attribute \src "libresoc.v:200986.9-200986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast2 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:200995.3-201004.6" + process $proc$libresoc.v:200995$14572 + assign { } { } + assign { } { } + assign $0\dest4_o[63:0] $1\dest4_o[63:0] + attribute \src "libresoc.v:200996.5-200996.29" + switch \initial + attribute \src "libresoc.v:200996.9-200996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[63:0] \data_r3__nia + case + assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest4_o $0\dest4_o[63:0] + end + attribute \src "libresoc.v:201005.3-201014.6" + process $proc$libresoc.v:201005$14573 + assign { } { } + assign { } { } + assign $0\dest5_o[63:0] $1\dest5_o[63:0] + attribute \src "libresoc.v:201006.5-201006.29" + switch \initial + attribute \src "libresoc.v:201006.9-201006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[63:0] \data_r4__msr + case + assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest5_o $0\dest5_o[63:0] + end + attribute \src "libresoc.v:201015.3-201023.6" + process $proc$libresoc.v:201015$14574 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$14575 $1\prev_wr_go$next[4:0]$14576 + attribute \src "libresoc.v:201016.5-201016.29" + switch \initial + attribute \src "libresoc.v:201016.9-201016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$14576 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14576 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14575 + end + connect \$5 $reduce_and$libresoc.v:200463$14362_Y + connect \$99 $and$libresoc.v:200464$14363_Y + connect \$101 $and$libresoc.v:200465$14364_Y + connect \$103 $and$libresoc.v:200466$14365_Y + connect \$105 $and$libresoc.v:200467$14366_Y + connect \$107 $and$libresoc.v:200468$14367_Y + connect \$109 $and$libresoc.v:200469$14368_Y + connect \$111 $and$libresoc.v:200470$14369_Y + connect \$113 $and$libresoc.v:200471$14370_Y + connect \$115 $and$libresoc.v:200472$14371_Y + connect \$117 $and$libresoc.v:200473$14372_Y + connect \$11 $and$libresoc.v:200474$14373_Y + connect \$119 $and$libresoc.v:200475$14374_Y + connect \$121 $and$libresoc.v:200476$14375_Y + connect \$123 $and$libresoc.v:200477$14376_Y + connect \$13 $not$libresoc.v:200478$14377_Y + connect \$15 $and$libresoc.v:200479$14378_Y + connect \$17 $not$libresoc.v:200480$14379_Y + connect \$19 $and$libresoc.v:200481$14380_Y + connect \$21 $and$libresoc.v:200482$14381_Y + connect \$25 $not$libresoc.v:200483$14382_Y + connect \$27 $and$libresoc.v:200484$14383_Y + connect \$24 $reduce_or$libresoc.v:200485$14384_Y + connect \$23 $not$libresoc.v:200486$14385_Y + connect \$31 $and$libresoc.v:200487$14386_Y + connect \$33 $reduce_or$libresoc.v:200488$14387_Y + connect \$35 $reduce_or$libresoc.v:200489$14388_Y + connect \$37 $or$libresoc.v:200490$14389_Y + connect \$3 $and$libresoc.v:200491$14390_Y + connect \$39 $not$libresoc.v:200492$14391_Y + connect \$41 $and$libresoc.v:200493$14392_Y + connect \$43 $and$libresoc.v:200494$14393_Y + connect \$45 $eq$libresoc.v:200495$14394_Y + connect \$47 $and$libresoc.v:200496$14395_Y + connect \$49 $eq$libresoc.v:200497$14396_Y + connect \$51 $and$libresoc.v:200498$14397_Y + connect \$53 $and$libresoc.v:200499$14398_Y + connect \$55 $and$libresoc.v:200500$14399_Y + connect \$57 $or$libresoc.v:200501$14400_Y + connect \$59 $or$libresoc.v:200502$14401_Y + connect \$61 $or$libresoc.v:200503$14402_Y + connect \$63 $or$libresoc.v:200504$14403_Y + connect \$65 $and$libresoc.v:200505$14404_Y + connect \$67 $and$libresoc.v:200506$14405_Y + connect \$6 $not$libresoc.v:200507$14406_Y + connect \$69 $or$libresoc.v:200508$14407_Y + connect \$71 $and$libresoc.v:200509$14408_Y + connect \$73 $and$libresoc.v:200510$14409_Y + connect \$75 $and$libresoc.v:200511$14410_Y + connect \$77 $and$libresoc.v:200512$14411_Y + connect \$79 $and$libresoc.v:200513$14412_Y + connect \$81 $ternary$libresoc.v:200514$14413_Y + connect \$83 $ternary$libresoc.v:200515$14414_Y + connect \$85 $ternary$libresoc.v:200516$14415_Y + connect \$87 $ternary$libresoc.v:200517$14416_Y + connect \$8 $or$libresoc.v:200518$14417_Y + connect \$89 $and$libresoc.v:200519$14418_Y + connect \$91 $and$libresoc.v:200520$14419_Y + connect \$93 $and$libresoc.v:200521$14420_Y + connect \$95 $and$libresoc.v:200522$14421_Y + connect \$97 $not$libresoc.v:200523$14422_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$113 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_trap0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_trap0_p_valid_i \alui_l_q_alui + connect \alu_trap0_fast2$2 \$87 + connect \alu_trap0_fast1$1 \$85 + connect \alu_trap0_rb \$83 + connect \alu_trap0_ra \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_trap0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:201057.1-201115.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" +attribute \generator "nMigen" +module \upd_l + attribute \src "libresoc.v:201058.7-201058.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:201103.3-201111.6" + wire $0\q_int$next[0:0]$14626 + attribute \src "libresoc.v:201101.3-201102.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:201103.3-201111.6" + wire $1\q_int$next[0:0]$14627 + attribute \src "libresoc.v:201080.7-201080.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:201093.17-201093.96" + wire $and$libresoc.v:201093$14616_Y + attribute \src "libresoc.v:201098.17-201098.96" + wire $and$libresoc.v:201098$14621_Y + attribute \src "libresoc.v:201095.18-201095.93" + wire $not$libresoc.v:201095$14618_Y + attribute \src "libresoc.v:201097.17-201097.92" + wire $not$libresoc.v:201097$14620_Y + attribute \src "libresoc.v:201100.17-201100.92" + wire $not$libresoc.v:201100$14623_Y + attribute \src "libresoc.v:201094.18-201094.98" + wire $or$libresoc.v:201094$14617_Y + attribute \src "libresoc.v:201096.18-201096.99" + wire $or$libresoc.v:201096$14619_Y + attribute \src "libresoc.v:201099.17-201099.97" + wire $or$libresoc.v:201099$14622_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:201058.7-201058.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:201093$14616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:201093$14616_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:201098$14621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:201098$14621_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:201095$14618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \Y $not$libresoc.v:201095$14618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:201097$14620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:201097$14620_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:201100$14623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:201100$14623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:201094$14617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_upd + connect \Y $or$libresoc.v:201094$14617_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:201096$14619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \B \q_int + connect \Y $or$libresoc.v:201096$14619_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:201099$14622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_upd + connect \Y $or$libresoc.v:201099$14622_Y + end + attribute \src "libresoc.v:201058.7-201058.20" + process $proc$libresoc.v:201058$14628 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:201080.7-201080.19" + process $proc$libresoc.v:201080$14629 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:201101.3-201102.27" + process $proc$libresoc.v:201101$14624 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:201103.3-201111.6" + process $proc$libresoc.v:201103$14625 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$14626 $1\q_int$next[0:0]$14627 + attribute \src "libresoc.v:201104.5-201104.29" + switch \initial + attribute \src "libresoc.v:201104.9-201104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$14627 1'0 + case + assign $1\q_int$next[0:0]$14627 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$14626 + end + connect \$9 $and$libresoc.v:201093$14616_Y + connect \$11 $or$libresoc.v:201094$14617_Y + connect \$13 $not$libresoc.v:201095$14618_Y + connect \$15 $or$libresoc.v:201096$14619_Y + connect \$1 $not$libresoc.v:201097$14620_Y + connect \$3 $and$libresoc.v:201098$14621_Y + connect \$5 $or$libresoc.v:201099$14622_Y + connect \$7 $not$libresoc.v:201100$14623_Y + connect \qlq_upd \$15 + connect \qn_upd \$13 + connect \q_upd \$11 +end +attribute \src "libresoc.v:201119.1-201177.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" +attribute \generator "nMigen" +module \valid_l + attribute \src "libresoc.v:201120.7-201120.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:201165.3-201173.6" + wire $0\q_int$next[0:0]$14640 + attribute \src "libresoc.v:201163.3-201164.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:201165.3-201173.6" + wire $1\q_int$next[0:0]$14641 + attribute \src "libresoc.v:201142.7-201142.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:201155.17-201155.96" + wire $and$libresoc.v:201155$14630_Y + attribute \src "libresoc.v:201160.17-201160.96" + wire $and$libresoc.v:201160$14635_Y + attribute \src "libresoc.v:201157.18-201157.95" + wire $not$libresoc.v:201157$14632_Y + attribute \src "libresoc.v:201159.17-201159.94" + wire $not$libresoc.v:201159$14634_Y + attribute \src "libresoc.v:201162.17-201162.94" + wire $not$libresoc.v:201162$14637_Y + attribute \src "libresoc.v:201156.18-201156.100" + wire $or$libresoc.v:201156$14631_Y + attribute \src "libresoc.v:201158.18-201158.101" + wire $or$libresoc.v:201158$14633_Y + attribute \src "libresoc.v:201161.17-201161.99" + wire $or$libresoc.v:201161$14636_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:201120.7-201120.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 3 \q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:201155$14630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:201155$14630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:201160$14635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:201160$14635_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:201157$14632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \Y $not$libresoc.v:201157$14632_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:201159$14634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:201159$14634_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:201162$14637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:201162$14637_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:201156$14631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_valid + connect \Y $or$libresoc.v:201156$14631_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:201158$14633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \B \q_int + connect \Y $or$libresoc.v:201158$14633_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:201161$14636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_valid + connect \Y $or$libresoc.v:201161$14636_Y + end + attribute \src "libresoc.v:201120.7-201120.20" + process $proc$libresoc.v:201120$14642 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:201142.7-201142.19" + process $proc$libresoc.v:201142$14643 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:201163.3-201164.27" + process $proc$libresoc.v:201163$14638 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:201165.3-201173.6" + process $proc$libresoc.v:201165$14639 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$14640 $1\q_int$next[0:0]$14641 + attribute \src "libresoc.v:201166.5-201166.29" + switch \initial + attribute \src "libresoc.v:201166.9-201166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$14641 1'0 + case + assign $1\q_int$next[0:0]$14641 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$14640 + end + connect \$9 $and$libresoc.v:201155$14630_Y + connect \$11 $or$libresoc.v:201156$14631_Y + connect \$13 $not$libresoc.v:201157$14632_Y + connect \$15 $or$libresoc.v:201158$14633_Y + connect \$1 $not$libresoc.v:201159$14634_Y + connect \$3 $and$libresoc.v:201160$14635_Y + connect \$5 $or$libresoc.v:201161$14636_Y + connect \$7 $not$libresoc.v:201162$14637_Y + connect \qlq_valid \$15 + connect \qn_valid \$13 + connect \q_valid \$11 +end +attribute \src "libresoc.v:201181.1-201239.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" +attribute \generator "nMigen" +module \wri_l + attribute \src "libresoc.v:201182.7-201182.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:201227.3-201235.6" + wire $0\q_int$next[0:0]$14654 + attribute \src "libresoc.v:201225.3-201226.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:201227.3-201235.6" + wire $1\q_int$next[0:0]$14655 + attribute \src "libresoc.v:201204.7-201204.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:201217.17-201217.96" + wire $and$libresoc.v:201217$14644_Y + attribute \src "libresoc.v:201222.17-201222.96" + wire $and$libresoc.v:201222$14649_Y + attribute \src "libresoc.v:201219.18-201219.93" + wire $not$libresoc.v:201219$14646_Y + attribute \src "libresoc.v:201221.17-201221.92" + wire $not$libresoc.v:201221$14648_Y + attribute \src "libresoc.v:201224.17-201224.92" + wire $not$libresoc.v:201224$14651_Y + attribute \src "libresoc.v:201218.18-201218.98" + wire $or$libresoc.v:201218$14645_Y + attribute \src "libresoc.v:201220.18-201220.99" + wire $or$libresoc.v:201220$14647_Y + attribute \src "libresoc.v:201223.17-201223.97" + wire $or$libresoc.v:201223$14650_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 1 \coresync_rst + attribute \src "libresoc.v:201182.7-201182.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:201217$14644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:201217$14644_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:201222$14649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:201222$14649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:201219$14646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \Y $not$libresoc.v:201219$14646_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:201221$14648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:201221$14648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:201224$14651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:201224$14651_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:201218$14645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_wri + connect \Y $or$libresoc.v:201218$14645_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:201220$14647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \B \q_int + connect \Y $or$libresoc.v:201220$14647_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:201223$14650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_wri + connect \Y $or$libresoc.v:201223$14650_Y + end + attribute \src "libresoc.v:201182.7-201182.20" + process $proc$libresoc.v:201182$14656 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:201204.7-201204.19" + process $proc$libresoc.v:201204$14657 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:201225.3-201226.27" + process $proc$libresoc.v:201225$14652 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:201227.3-201235.6" + process $proc$libresoc.v:201227$14653 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$14654 $1\q_int$next[0:0]$14655 + attribute \src "libresoc.v:201228.5-201228.29" + switch \initial + attribute \src "libresoc.v:201228.9-201228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$14655 1'0 + case + assign $1\q_int$next[0:0]$14655 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$14654 + end + connect \$9 $and$libresoc.v:201217$14644_Y + connect \$11 $or$libresoc.v:201218$14645_Y + connect \$13 $not$libresoc.v:201219$14646_Y + connect \$15 $or$libresoc.v:201220$14647_Y + connect \$1 $not$libresoc.v:201221$14648_Y + connect \$3 $and$libresoc.v:201222$14649_Y + connect \$5 $or$libresoc.v:201223$14650_Y + connect \$7 $not$libresoc.v:201224$14651_Y + connect \qlq_wri \$15 + connect \qn_wri \$13 + connect \q_wri \$11 +end +attribute \src "libresoc.v:201243.1-201309.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" +attribute \generator "nMigen" +module \wrpick_CR_cr_a + attribute \src "libresoc.v:201288.17-201288.91" + wire $not$libresoc.v:201288$14658_Y + attribute \src "libresoc.v:201290.18-201290.93" + wire $not$libresoc.v:201290$14660_Y + attribute \src "libresoc.v:201292.18-201292.93" + wire $not$libresoc.v:201292$14662_Y + attribute \src "libresoc.v:201293.17-201293.89" + wire width 6 $not$libresoc.v:201293$14663_Y + attribute \src "libresoc.v:201295.18-201295.93" + wire $not$libresoc.v:201295$14665_Y + attribute \src "libresoc.v:201298.17-201298.91" + wire $not$libresoc.v:201298$14668_Y + attribute \src "libresoc.v:201289.18-201289.106" + wire $reduce_or$libresoc.v:201289$14659_Y + attribute \src "libresoc.v:201291.18-201291.106" + wire $reduce_or$libresoc.v:201291$14661_Y + attribute \src "libresoc.v:201294.18-201294.106" + wire $reduce_or$libresoc.v:201294$14664_Y + attribute \src "libresoc.v:201296.18-201296.90" + wire $reduce_or$libresoc.v:201296$14666_Y + attribute \src "libresoc.v:201297.17-201297.103" + wire $reduce_or$libresoc.v:201297$14667_Y + attribute \src "libresoc.v:201299.17-201299.105" + wire $reduce_or$libresoc.v:201299$14669_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201288$14658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:201288$14658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201290$14660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:201290$14660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201292$14662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:201292$14662_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:201293$14663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:201293$14663_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201295$14665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:201295$14665_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201298$14668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:201298$14668_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201289$14659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:201289$14659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201291$14661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:201291$14661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201294$14664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:201294$14664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:201296$14666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:201296$14666_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201297$14667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:201297$14667_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201299$14669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:201299$14669_Y + end + connect \$7 $not$libresoc.v:201288$14658_Y + connect \$12 $reduce_or$libresoc.v:201289$14659_Y + connect \$11 $not$libresoc.v:201290$14660_Y + connect \$16 $reduce_or$libresoc.v:201291$14661_Y + connect \$15 $not$libresoc.v:201292$14662_Y + connect \$1 $not$libresoc.v:201293$14663_Y + connect \$20 $reduce_or$libresoc.v:201294$14664_Y + connect \$19 $not$libresoc.v:201295$14665_Y + connect \$23 $reduce_or$libresoc.v:201296$14666_Y + connect \$4 $reduce_or$libresoc.v:201297$14667_Y + connect \$3 $not$libresoc.v:201298$14668_Y + connect \$8 $reduce_or$libresoc.v:201299$14669_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:201313.1-201334.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" +attribute \generator "nMigen" +module \wrpick_CR_full_cr + attribute \src "libresoc.v:201328.17-201328.89" + wire $not$libresoc.v:201328$14670_Y + attribute \src "libresoc.v:201329.17-201329.89" + wire $reduce_or$libresoc.v:201329$14671_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:201328$14670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:201328$14670_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:201329$14671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:201329$14671_Y + end + connect \$1 $not$libresoc.v:201328$14670_Y + connect \$3 $reduce_or$libresoc.v:201329$14671_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:201338.1-201395.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" +attribute \generator "nMigen" +module \wrpick_FAST_fast1 + attribute \src "libresoc.v:201377.17-201377.91" + wire $not$libresoc.v:201377$14672_Y + attribute \src "libresoc.v:201379.18-201379.93" + wire $not$libresoc.v:201379$14674_Y + attribute \src "libresoc.v:201381.18-201381.93" + wire $not$libresoc.v:201381$14676_Y + attribute \src "libresoc.v:201382.17-201382.89" + wire width 5 $not$libresoc.v:201382$14677_Y + attribute \src "libresoc.v:201385.17-201385.91" + wire $not$libresoc.v:201385$14680_Y + attribute \src "libresoc.v:201378.18-201378.106" + wire $reduce_or$libresoc.v:201378$14673_Y + attribute \src "libresoc.v:201380.18-201380.106" + wire $reduce_or$libresoc.v:201380$14675_Y + attribute \src "libresoc.v:201383.18-201383.90" + wire $reduce_or$libresoc.v:201383$14678_Y + attribute \src "libresoc.v:201384.17-201384.103" + wire $reduce_or$libresoc.v:201384$14679_Y + attribute \src "libresoc.v:201386.17-201386.105" + wire $reduce_or$libresoc.v:201386$14681_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 5 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 5 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201377$14672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:201377$14672_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201379$14674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:201379$14674_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201381$14676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:201381$14676_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:201382$14677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $not$libresoc.v:201382$14677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201385$14680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:201385$14680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201378$14673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:201378$14673_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201380$14675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:201380$14675_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:201383$14678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:201383$14678_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201384$14679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:201384$14679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201386$14681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:201386$14681_Y + end + connect \$7 $not$libresoc.v:201377$14672_Y + connect \$12 $reduce_or$libresoc.v:201378$14673_Y + connect \$11 $not$libresoc.v:201379$14674_Y + connect \$16 $reduce_or$libresoc.v:201380$14675_Y + connect \$15 $not$libresoc.v:201381$14676_Y + connect \$1 $not$libresoc.v:201382$14677_Y + connect \$19 $reduce_or$libresoc.v:201383$14678_Y + connect \$4 $reduce_or$libresoc.v:201384$14679_Y + connect \$3 $not$libresoc.v:201385$14680_Y + connect \$8 $reduce_or$libresoc.v:201386$14681_Y + connect \en_o \$19 + connect \o { \t4 \t3 \t2 \t1 \t0 } + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:201399.1-201501.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" +attribute \generator "nMigen" +module \wrpick_INT_o + attribute \src "libresoc.v:201468.17-201468.91" + wire $not$libresoc.v:201468$14682_Y + attribute \src "libresoc.v:201470.18-201470.93" + wire $not$libresoc.v:201470$14684_Y + attribute \src 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"libresoc.v:201476.18-201476.106" + wire $reduce_or$libresoc.v:201476$14690_Y + attribute \src "libresoc.v:201478.18-201478.106" + wire $reduce_or$libresoc.v:201478$14692_Y + attribute \src "libresoc.v:201480.18-201480.106" + wire $reduce_or$libresoc.v:201480$14694_Y + attribute \src "libresoc.v:201482.18-201482.106" + wire $reduce_or$libresoc.v:201482$14696_Y + attribute \src "libresoc.v:201484.18-201484.90" + wire $reduce_or$libresoc.v:201484$14698_Y + attribute \src "libresoc.v:201485.17-201485.103" + wire $reduce_or$libresoc.v:201485$14699_Y + attribute \src "libresoc.v:201487.17-201487.105" + wire $reduce_or$libresoc.v:201487$14701_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 10 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 10 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 10 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 10 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201468$14682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:201468$14682_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201470$14684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:201470$14684_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201472$14686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:201472$14686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:201473$14687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 10 + connect \A \i + connect \Y $not$libresoc.v:201473$14687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201475$14689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:201475$14689_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201477$14691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:201477$14691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201479$14693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:201479$14693_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201481$14695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:201481$14695_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201483$14697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \Y $not$libresoc.v:201483$14697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201486$14700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:201486$14700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201469$14683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:201469$14683_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201471$14685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:201471$14685_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201474$14688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:201474$14688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201476$14690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:201476$14690_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201478$14692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:201478$14692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201480$14694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:201480$14694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201482$14696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A { \i [8:0] \ni [9] } + connect \Y $reduce_or$libresoc.v:201482$14696_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:201484$14698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:201484$14698_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201485$14699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:201485$14699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201487$14701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:201487$14701_Y + end + connect \$7 $not$libresoc.v:201468$14682_Y + connect \$12 $reduce_or$libresoc.v:201469$14683_Y + connect \$11 $not$libresoc.v:201470$14684_Y + connect \$16 $reduce_or$libresoc.v:201471$14685_Y + connect \$15 $not$libresoc.v:201472$14686_Y + connect \$1 $not$libresoc.v:201473$14687_Y + connect \$20 $reduce_or$libresoc.v:201474$14688_Y + connect \$19 $not$libresoc.v:201475$14689_Y + connect \$24 $reduce_or$libresoc.v:201476$14690_Y + connect \$23 $not$libresoc.v:201477$14691_Y + connect \$28 $reduce_or$libresoc.v:201478$14692_Y + connect \$27 $not$libresoc.v:201479$14693_Y + connect \$32 $reduce_or$libresoc.v:201480$14694_Y + connect \$31 $not$libresoc.v:201481$14695_Y + connect \$36 $reduce_or$libresoc.v:201482$14696_Y + connect \$35 $not$libresoc.v:201483$14697_Y + connect \$39 $reduce_or$libresoc.v:201484$14698_Y + connect \$4 $reduce_or$libresoc.v:201485$14699_Y + connect \$3 $not$libresoc.v:201486$14700_Y + connect \$8 $reduce_or$libresoc.v:201487$14701_Y + connect \en_o \$39 + connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t9 \$35 + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:201505.1-201526.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" +attribute \generator "nMigen" +module \wrpick_SPR_spr1 + attribute \src "libresoc.v:201520.17-201520.89" + wire $not$libresoc.v:201520$14702_Y + attribute \src "libresoc.v:201521.17-201521.89" + wire $reduce_or$libresoc.v:201521$14703_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:201520$14702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:201520$14702_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:201521$14703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:201521$14703_Y + end + connect \$1 $not$libresoc.v:201520$14702_Y + connect \$3 $reduce_or$libresoc.v:201521$14703_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:201530.1-201551.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" +attribute \generator "nMigen" +module \wrpick_STATE_msr + attribute \src "libresoc.v:201545.17-201545.89" + wire $not$libresoc.v:201545$14704_Y + attribute \src "libresoc.v:201546.17-201546.89" + wire $reduce_or$libresoc.v:201546$14705_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src 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"test_issuer.ti.core.wrpick_STATE_nia" +attribute \generator "nMigen" +module \wrpick_STATE_nia + attribute \src "libresoc.v:201576.17-201576.89" + wire width 2 $not$libresoc.v:201576$14706_Y + attribute \src "libresoc.v:201578.17-201578.91" + wire $not$libresoc.v:201578$14708_Y + attribute \src "libresoc.v:201577.17-201577.103" + wire $reduce_or$libresoc.v:201577$14707_Y + attribute \src "libresoc.v:201579.17-201579.89" + wire $reduce_or$libresoc.v:201579$14709_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:201576$14706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:201576$14706_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:201578$14708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:201578$14708_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:201577$14707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:201577$14707_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:201579$14709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:201579$14709_Y + end + connect \$1 $not$libresoc.v:201576$14706_Y + connect \$4 $reduce_or$libresoc.v:201577$14707_Y + connect \$3 $not$libresoc.v:201578$14708_Y + connect \$7 $reduce_or$libresoc.v:201579$14709_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:201589.1-201628.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" +attribute \generator "nMigen" +module \wrpick_XER_xer_ca + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_dest30__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_w0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_dest31__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_w1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_dest32__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 4 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 5 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 6 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 7 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 8 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 9 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 11 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 13 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \wen$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:201903$14732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src10__data_o + connect \B \$7 + connect \Y $or$libresoc.v:201903$14732_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:201905$14734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src21__data_o + connect \B \reg_2_src22__data_o + connect \Y $or$libresoc.v:201905$14734_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:201906$14735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src20__data_o + connect \B \$14 + connect \Y $or$libresoc.v:201906$14735_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:201908$14737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src31__data_o + connect \B \reg_2_src32__data_o + connect \Y $or$libresoc.v:201908$14737_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:201909$14738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src30__data_o + connect \B \$21 + connect \Y $or$libresoc.v:201909$14738_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:201911$14740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src11__data_o + connect \B \reg_2_src12__data_o + connect \Y $or$libresoc.v:201911$14740_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:201904$14733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$11 + connect \Y $reduce_or$libresoc.v:201904$14733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:201907$14736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$18 + connect \Y $reduce_or$libresoc.v:201907$14736_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:201910$14739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:201910$14739_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201918.15-201937.4" + cell \reg_0$132 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest30__data_i \reg_0_dest30__data_i + connect \dest30__wen \reg_0_dest30__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201938.15-201957.4" + cell \reg_1$133 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest31__data_i \reg_1_dest31__data_i + connect \dest31__wen \reg_1_dest31__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201958.15-201977.4" + cell \reg_2$134 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest32__data_i \reg_2_dest32__data_i + connect \dest32__wen \reg_2_dest32__wen + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \src "libresoc.v:201737.7-201737.20" + process $proc$libresoc.v:201737$14758 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:201871.13-201871.29" + process $proc$libresoc.v:201871$14759 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "libresoc.v:201873.13-201873.34" + process $proc$libresoc.v:201873$14760 + assign { } { } + assign $0\ren_delay$11[2:0]$14761 3'000 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[2:0]$14761 + end + attribute \src "libresoc.v:201877.13-201877.34" + process $proc$libresoc.v:201877$14762 + assign { } { } + assign $0\ren_delay$18[2:0]$14763 3'000 + sync always + sync init + update \ren_delay$18 $0\ren_delay$18[2:0]$14763 + end + attribute \src "libresoc.v:201912.3-201913.43" + process $proc$libresoc.v:201912$14741 + assign { } { } + assign $0\ren_delay$18[2:0]$14742 \ren_delay$18$next + sync posedge \coresync_clk + update \ren_delay$18 $0\ren_delay$18[2:0]$14742 + end + attribute \src "libresoc.v:201914.3-201915.43" + process $proc$libresoc.v:201914$14743 + assign { } { } + assign $0\ren_delay$11[2:0]$14744 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[2:0]$14744 + end + attribute \src "libresoc.v:201916.3-201917.35" + process $proc$libresoc.v:201916$14745 + assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:201978.3-201986.6" + process $proc$libresoc.v:201978$14746 + assign { } { } + assign { } { } + assign $0\ren_delay$18$next[2:0]$14747 $1\ren_delay$18$next[2:0]$14748 + attribute \src "libresoc.v:201979.5-201979.29" + switch \initial + attribute \src "libresoc.v:201979.9-201979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$18$next[2:0]$14748 3'000 + case + assign $1\ren_delay$18$next[2:0]$14748 \src3__ren + end + sync always + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14747 + end + attribute \src "libresoc.v:201987.3-201996.6" + process $proc$libresoc.v:201987$14749 + assign { } { } + assign { } { } + assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] + attribute \src "libresoc.v:201988.5-201988.29" + switch \initial + attribute \src "libresoc.v:201988.9-201988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[1:0] \$23 + case + assign $1\src3__data_o[1:0] 2'00 + end + sync always + update \src3__data_o $0\src3__data_o[1:0] + end + attribute \src "libresoc.v:201997.3-202005.6" + process $proc$libresoc.v:201997$14750 + assign { } { } + assign { } { } + assign $0\ren_delay$next[2:0]$14751 $1\ren_delay$next[2:0]$14752 + attribute \src "libresoc.v:201998.5-201998.29" + switch \initial + attribute \src "libresoc.v:201998.9-201998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[2:0]$14752 3'000 + case + assign $1\ren_delay$next[2:0]$14752 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[2:0]$14751 + end + attribute \src "libresoc.v:202006.3-202015.6" + process $proc$libresoc.v:202006$14753 + assign { } { } + assign { } { } + assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] + attribute \src "libresoc.v:202007.5-202007.29" + switch \initial + attribute \src "libresoc.v:202007.9-202007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[1:0] \$9 + case + assign $1\src1__data_o[1:0] 2'00 + end + sync always + update \src1__data_o $0\src1__data_o[1:0] + end + attribute \src "libresoc.v:202016.3-202024.6" + process $proc$libresoc.v:202016$14754 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[2:0]$14755 $1\ren_delay$11$next[2:0]$14756 + attribute \src "libresoc.v:202017.5-202017.29" + switch \initial + attribute \src "libresoc.v:202017.9-202017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[2:0]$14756 3'000 + case + assign $1\ren_delay$11$next[2:0]$14756 \src2__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14755 + end + attribute \src "libresoc.v:202025.3-202034.6" + process $proc$libresoc.v:202025$14757 + assign { } { } + assign { } { } + assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] + attribute \src "libresoc.v:202026.5-202026.29" + switch \initial + attribute \src "libresoc.v:202026.9-202026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[1:0] \$16 + case + assign $1\src2__data_o[1:0] 2'00 + end + sync always + update \src2__data_o $0\src2__data_o[1:0] + end + connect \$9 $or$libresoc.v:201903$14732_Y + connect \$12 $reduce_or$libresoc.v:201904$14733_Y + connect \$14 $or$libresoc.v:201905$14734_Y + connect \$16 $or$libresoc.v:201906$14735_Y + connect \$19 $reduce_or$libresoc.v:201907$14736_Y + connect \$21 $or$libresoc.v:201908$14737_Y + connect \$23 $or$libresoc.v:201909$14738_Y + connect \$5 $reduce_or$libresoc.v:201910$14739_Y + connect \$7 $or$libresoc.v:201911$14740_Y + connect \full_wr__data_i 6'000000 + connect \full_wr__wen 3'000 + connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 + connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 + connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_2_dest32__data_i \data_i$1 + connect \reg_1_dest31__data_i \data_i$1 + connect \reg_0_dest30__data_i \data_i$1 + connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 + connect \reg_2_dest22__data_i \data_i + connect \reg_1_dest21__data_i \data_i + connect \reg_0_dest20__data_i \data_i + connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen + connect \reg_2_dest12__data_i \data_i$3 + connect \reg_1_dest11__data_i \data_i$3 + connect \reg_0_dest10__data_i \data_i$3 + connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 + connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "libresoc.v:202060.1-202374.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" +attribute \generator "nMigen" +module \xics_icp + attribute \src "libresoc.v:202238.3-202266.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:202289.3-202297.6" + wire $0\core_irq_o$next[0:0]$14799 + attribute \src "libresoc.v:202180.3-202181.37" + wire $0\core_irq_o[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $0\cppr$10[7:0]$14803 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $0\cppr$next[7:0]$14782 + attribute \src "libresoc.v:202184.3-202185.25" + wire width 8 $0\cppr[7:0] + attribute \src "libresoc.v:202298.3-202307.6" + wire width 32 $0\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:202061.7-202061.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire $0\irq$12[0:0]$14804 + attribute \src "libresoc.v:202194.3-202209.6" + wire $0\irq$next[0:0]$14783 + attribute \src "libresoc.v:202188.3-202189.23" + wire $0\irq[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $0\mfrr$11[7:0]$14805 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $0\mfrr$next[7:0]$14784 + attribute \src "libresoc.v:202186.3-202187.25" + wire width 8 $0\mfrr[7:0] + attribute \src "libresoc.v:202277.3-202288.6" + wire width 8 $0\min_pri[7:0] + attribute \src "libresoc.v:202267.3-202276.6" + wire width 8 $0\pending_priority[7:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire $0\wb_ack$14[0:0]$14806 + attribute \src "libresoc.v:202194.3-202209.6" + wire $0\wb_ack$next[0:0]$14785 + attribute \src "libresoc.v:202192.3-202193.29" + wire $0\wb_ack[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 32 $0\wb_rd_data$13[31:0]$14807 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 32 $0\wb_rd_data$next[31:0]$14786 + attribute \src "libresoc.v:202190.3-202191.37" + wire width 32 $0\wb_rd_data[31:0] + attribute \src "libresoc.v:202210.3-202237.6" + wire $0\xirr_accept_rd[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $0\xisr$9[23:0]$14808 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 24 $0\xisr$next[23:0]$14787 + attribute \src "libresoc.v:202182.3-202183.25" + wire width 24 $0\xisr[23:0] + attribute \src "libresoc.v:202238.3-202266.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:202289.3-202297.6" + wire $1\core_irq_o$next[0:0]$14800 + attribute \src "libresoc.v:202090.7-202090.24" + wire $1\core_irq_o[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $1\cppr$10[7:0]$14809 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $1\cppr$next[7:0]$14788 + attribute \src "libresoc.v:202094.13-202094.25" + wire width 8 $1\cppr[7:0] + attribute \src "libresoc.v:202298.3-202307.6" + wire width 32 $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire $1\irq$12[0:0]$14819 + attribute \src "libresoc.v:202194.3-202209.6" + wire $1\irq$next[0:0]$14789 + attribute \src "libresoc.v:202123.7-202123.17" + wire $1\irq[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $1\mfrr$11[7:0]$14810 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $1\mfrr$next[7:0]$14790 + attribute \src "libresoc.v:202131.13-202131.25" + wire width 8 $1\mfrr[7:0] + attribute \src "libresoc.v:202277.3-202288.6" + wire width 8 $1\min_pri[7:0] + attribute \src "libresoc.v:202267.3-202276.6" + wire width 8 $1\pending_priority[7:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire $1\wb_ack$14[0:0]$14811 + attribute \src "libresoc.v:202194.3-202209.6" + wire $1\wb_ack$next[0:0]$14791 + attribute \src "libresoc.v:202145.7-202145.20" + wire $1\wb_ack[0:0] + attribute \src "libresoc.v:202194.3-202209.6" + wire width 32 $1\wb_rd_data$next[31:0]$14792 + attribute \src "libresoc.v:202153.14-202153.32" + wire width 32 $1\wb_rd_data[31:0] + attribute \src "libresoc.v:202210.3-202237.6" + wire $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $1\xisr$9[23:0]$14816 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 24 $1\xisr$next[23:0]$14793 + attribute \src "libresoc.v:202163.14-202163.31" + wire width 24 $1\xisr[23:0] + attribute \src "libresoc.v:202238.3-202266.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $2\cppr$10[7:0]$14812 + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $2\mfrr$11[7:0]$14813 + attribute \src "libresoc.v:202210.3-202237.6" + wire $2\xirr_accept_rd[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $2\xisr$9[23:0]$14817 + attribute \src "libresoc.v:202238.3-202266.6" + wire width 32 $3\be_out[31:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $3\cppr$10[7:0]$14814 + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $3\mfrr$11[7:0]$14815 + attribute \src "libresoc.v:202210.3-202237.6" + wire $3\xirr_accept_rd[0:0] + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $4\cppr$10[7:0]$14818 + attribute \src "libresoc.v:202210.3-202237.6" + wire $4\xirr_accept_rd[0:0] + attribute \src "libresoc.v:202170.18-202170.116" + wire $and$libresoc.v:202170$14764_Y + attribute \src "libresoc.v:202174.18-202174.116" + wire $and$libresoc.v:202174$14768_Y + attribute \src "libresoc.v:202176.18-202176.116" + wire $and$libresoc.v:202176$14770_Y + attribute \src "libresoc.v:202179.17-202179.109" + wire $and$libresoc.v:202179$14773_Y + attribute \src "libresoc.v:202175.18-202175.110" + wire $eq$libresoc.v:202175$14769_Y + attribute \src "libresoc.v:202172.18-202172.114" + wire $lt$libresoc.v:202172$14766_Y + attribute \src "libresoc.v:202173.18-202173.109" + wire $lt$libresoc.v:202173$14767_Y + attribute \src "libresoc.v:202178.18-202178.114" + wire $lt$libresoc.v:202178$14772_Y + attribute \src "libresoc.v:202171.18-202171.109" + wire $ne$libresoc.v:202171$14765_Y + attribute \src "libresoc.v:202177.18-202177.109" + wire $ne$libresoc.v:202177$14771_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 13 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire output 4 \core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \core_irq_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 5 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 11 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 6 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 7 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 8 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 12 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 9 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 10 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 input 3 \ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 input 2 \ics_i_src + attribute \src "libresoc.v:202061.7-202061.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" + wire width 8 \min_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" + wire width 8 \pending_priority + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" + wire \xirr_accept_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:202170$14764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:202170$14764_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:202174$14768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:202174$14768_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:202176$14770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:202176$14770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + cell $and $and$libresoc.v:202179$14773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_ack + connect \B \icp_wb__cyc + connect \Y $and$libresoc.v:202179$14773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + cell $eq $eq$libresoc.v:202175$14769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \icp_wb__sel + connect \B 4'1111 + connect \Y $eq$libresoc.v:202175$14769_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:202172$14766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:202172$14766_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + cell $lt $lt$libresoc.v:202173$14767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \min_pri + connect \B \cppr$10 + connect \Y $lt$libresoc.v:202173$14767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:202178$14772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:202178$14772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:202171$14765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:202171$14765_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:202177$14771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:202177$14771_Y + end + attribute \src "libresoc.v:202061.7-202061.20" + process $proc$libresoc.v:202061$14820 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:202090.7-202090.24" + process $proc$libresoc.v:202090$14821 + assign { } { } + assign $1\core_irq_o[0:0] 1'0 + sync always + sync init + update \core_irq_o $1\core_irq_o[0:0] + end + attribute \src "libresoc.v:202094.13-202094.25" + process $proc$libresoc.v:202094$14822 + assign { } { } + assign $1\cppr[7:0] 8'00000000 + sync always + sync init + update \cppr $1\cppr[7:0] + end + attribute \src "libresoc.v:202123.7-202123.17" + process $proc$libresoc.v:202123$14823 + assign { } { } + assign $1\irq[0:0] 1'0 + sync always + sync init + update \irq $1\irq[0:0] + end + attribute \src "libresoc.v:202131.13-202131.25" + process $proc$libresoc.v:202131$14824 + assign { } { } + assign $1\mfrr[7:0] 8'11111111 + sync always + sync init + update \mfrr $1\mfrr[7:0] + end + attribute \src "libresoc.v:202145.7-202145.20" + process $proc$libresoc.v:202145$14825 + assign { } { } + assign $1\wb_ack[0:0] 1'0 + sync always + sync init + update \wb_ack $1\wb_ack[0:0] + end + attribute \src "libresoc.v:202153.14-202153.32" + process $proc$libresoc.v:202153$14826 + assign { } { } + assign $1\wb_rd_data[31:0] 0 + sync always + sync init + update \wb_rd_data $1\wb_rd_data[31:0] + end + attribute \src "libresoc.v:202163.14-202163.31" + process $proc$libresoc.v:202163$14827 + assign { } { } + assign $1\xisr[23:0] 24'000000000000000000000000 + sync always + sync init + update \xisr $1\xisr[23:0] + end + attribute \src "libresoc.v:202180.3-202181.37" + process $proc$libresoc.v:202180$14774 + assign { } { } + assign $0\core_irq_o[0:0] \core_irq_o$next + sync posedge \clk + update \core_irq_o $0\core_irq_o[0:0] + end + attribute \src "libresoc.v:202182.3-202183.25" + process $proc$libresoc.v:202182$14775 + assign { } { } + assign $0\xisr[23:0] \xisr$next + sync posedge \clk + update \xisr $0\xisr[23:0] + end + attribute \src "libresoc.v:202184.3-202185.25" + process $proc$libresoc.v:202184$14776 + assign { } { } + assign $0\cppr[7:0] \cppr$next + sync posedge \clk + update \cppr $0\cppr[7:0] + end + attribute \src "libresoc.v:202186.3-202187.25" + process $proc$libresoc.v:202186$14777 + assign { } { } + assign $0\mfrr[7:0] \mfrr$next + sync posedge \clk + update \mfrr $0\mfrr[7:0] + end + attribute \src "libresoc.v:202188.3-202189.23" + process $proc$libresoc.v:202188$14778 + assign { } { } + assign $0\irq[0:0] \irq$next + sync posedge \clk + update \irq $0\irq[0:0] + end + attribute \src "libresoc.v:202190.3-202191.37" + process $proc$libresoc.v:202190$14779 + assign { } { } + assign $0\wb_rd_data[31:0] \wb_rd_data$next + sync posedge \clk + update \wb_rd_data $0\wb_rd_data[31:0] + end + attribute \src "libresoc.v:202192.3-202193.29" + process $proc$libresoc.v:202192$14780 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "libresoc.v:202194.3-202209.6" + process $proc$libresoc.v:202194$14781 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cppr$next[7:0]$14782 $1\cppr$next[7:0]$14788 + assign $0\irq$next[0:0]$14783 $1\irq$next[0:0]$14789 + assign $0\mfrr$next[7:0]$14784 $1\mfrr$next[7:0]$14790 + assign $0\wb_ack$next[0:0]$14785 $1\wb_ack$next[0:0]$14791 + assign $0\wb_rd_data$next[31:0]$14786 $1\wb_rd_data$next[31:0]$14792 + assign $0\xisr$next[23:0]$14787 $1\xisr$next[23:0]$14793 + attribute \src "libresoc.v:202195.5-202195.29" + switch \initial + attribute \src "libresoc.v:202195.9-202195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xisr$next[23:0]$14793 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14788 8'00000000 + assign $1\mfrr$next[7:0]$14790 8'11111111 + assign $1\irq$next[0:0]$14789 1'0 + assign $1\wb_rd_data$next[31:0]$14792 0 + assign $1\wb_ack$next[0:0]$14791 1'0 + case + assign $1\cppr$next[7:0]$14788 \cppr$2 + assign $1\irq$next[0:0]$14789 \irq$4 + assign $1\mfrr$next[7:0]$14790 \mfrr$3 + assign $1\wb_ack$next[0:0]$14791 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14792 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14793 \xisr$1 + end + sync always + update \cppr$next $0\cppr$next[7:0]$14782 + update \irq$next $0\irq$next[0:0]$14783 + update \mfrr$next $0\mfrr$next[7:0]$14784 + update \wb_ack$next $0\wb_ack$next[0:0]$14785 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14786 + update \xisr$next $0\xisr$next[23:0]$14787 + end + attribute \src "libresoc.v:202210.3-202237.6" + process $proc$libresoc.v:202210$14794 + assign { } { } + assign { } { } + assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:202211.5-202211.29" + switch \initial + attribute \src "libresoc.v:202211.9-202211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\xirr_accept_rd[0:0] 1'1 + case + assign $4\xirr_accept_rd[0:0] 1'0 + end + case + assign $3\xirr_accept_rd[0:0] 1'0 + end + end + case + assign $1\xirr_accept_rd[0:0] 1'0 + end + sync always + update \xirr_accept_rd $0\xirr_accept_rd[0:0] + end + attribute \src "libresoc.v:202238.3-202266.6" + process $proc$libresoc.v:202238$14795 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:202239.5-202239.29" + switch \initial + attribute \src "libresoc.v:202239.9-202239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\be_out[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\be_out[31:0] $3\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 + assign $3\be_out[31:0] [31:24] \mfrr + case + assign $3\be_out[31:0] 0 + end + end + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:202267.3-202276.6" + process $proc$libresoc.v:202267$14796 + assign { } { } + assign { } { } + assign $0\pending_priority[7:0] $1\pending_priority[7:0] + attribute \src "libresoc.v:202268.5-202268.29" + switch \initial + attribute \src "libresoc.v:202268.9-202268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pending_priority[7:0] \ics_i_pri + case + assign $1\pending_priority[7:0] 8'11111111 + end + sync always + update \pending_priority $0\pending_priority[7:0] + end + attribute \src "libresoc.v:202277.3-202288.6" + process $proc$libresoc.v:202277$14797 + assign { } { } + assign $0\min_pri[7:0] $1\min_pri[7:0] + attribute \src "libresoc.v:202278.5-202278.29" + switch \initial + attribute \src "libresoc.v:202278.9-202278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\min_pri[7:0] \mfrr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\min_pri[7:0] \pending_priority + end + sync always + update \min_pri $0\min_pri[7:0] + end + attribute \src "libresoc.v:202289.3-202297.6" + process $proc$libresoc.v:202289$14798 + assign { } { } + assign { } { } + assign $0\core_irq_o$next[0:0]$14799 $1\core_irq_o$next[0:0]$14800 + attribute \src "libresoc.v:202290.5-202290.29" + switch \initial + attribute \src "libresoc.v:202290.9-202290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_irq_o$next[0:0]$14800 1'0 + case + assign $1\core_irq_o$next[0:0]$14800 \irq + end + sync always + update \core_irq_o$next $0\core_irq_o$next[0:0]$14799 + end + attribute \src "libresoc.v:202298.3-202307.6" + process $proc$libresoc.v:202298$14801 + assign { } { } + assign { } { } + assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:202299.5-202299.29" + switch \initial + attribute \src "libresoc.v:202299.9-202299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" + switch \icp_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\icp_wb__dat_r[31:0] \wb_rd_data + case + assign $1\icp_wb__dat_r[31:0] 0 + end + sync always + update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] + end + attribute \src "libresoc.v:202308.3-202370.6" + process $proc$libresoc.v:202308$14802 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mfrr$11[7:0]$14805 $1\mfrr$11[7:0]$14810 + assign $0\wb_ack$14[0:0]$14806 $1\wb_ack$14[0:0]$14811 + assign { } { } + assign { } { } + assign { } { } + assign $0\xisr$9[23:0]$14808 $2\xisr$9[23:0]$14817 + assign $0\cppr$10[7:0]$14803 $4\cppr$10[7:0]$14818 + assign $0\wb_rd_data$13[31:0]$14807 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14804 $1\irq$12[0:0]$14819 + attribute \src "libresoc.v:202309.5-202309.29" + switch \initial + attribute \src "libresoc.v:202309.9-202309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1\wb_ack$14[0:0]$14811 1'1 + assign $1\cppr$10[7:0]$14809 $2\cppr$10[7:0]$14812 + assign $1\mfrr$11[7:0]$14810 $2\mfrr$11[7:0]$14813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\cppr$10[7:0]$14812 $3\cppr$10[7:0]$14814 + assign $2\mfrr$11[7:0]$14813 $3\mfrr$11[7:0]$14815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14814 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14814 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\cppr$10[7:0]$14814 \cppr + assign { } { } + assign $3\mfrr$11[7:0]$14815 \be_in [31:24] + case + assign $3\cppr$10[7:0]$14814 \cppr + assign $3\mfrr$11[7:0]$14815 \mfrr + end + case + assign $2\cppr$10[7:0]$14812 \cppr + assign $2\mfrr$11[7:0]$14813 \mfrr + end + case + assign $1\cppr$10[7:0]$14809 \cppr + assign $1\mfrr$11[7:0]$14810 \mfrr + assign $1\wb_ack$14[0:0]$14811 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xisr$9[23:0]$14816 { 20'00000000000000000001 \ics_i_src } + case + assign $1\xisr$9[23:0]$14816 24'000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xisr$9[23:0]$14817 24'000000000000000000000010 + case + assign $2\xisr$9[23:0]$14817 $1\xisr$9[23:0]$14816 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" + switch \xirr_accept_rd + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cppr$10[7:0]$14818 \min_pri + case + assign $4\cppr$10[7:0]$14818 $1\cppr$10[7:0]$14809 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + switch { \irq \$21 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\irq$12[0:0]$14819 1'1 + case + assign $1\irq$12[0:0]$14819 1'0 + end + sync always + update \cppr$10 $0\cppr$10[7:0]$14803 + update \irq$12 $0\irq$12[0:0]$14804 + update \mfrr$11 $0\mfrr$11[7:0]$14805 + update \wb_ack$14 $0\wb_ack$14[0:0]$14806 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14807 + update \xisr$9 $0\xisr$9[23:0]$14808 + end + connect \$15 $and$libresoc.v:202170$14764_Y + connect \$17 $ne$libresoc.v:202171$14765_Y + connect \$19 $lt$libresoc.v:202172$14766_Y + connect \$21 $lt$libresoc.v:202173$14767_Y + connect \$23 $and$libresoc.v:202174$14768_Y + connect \$25 $eq$libresoc.v:202175$14769_Y + connect \$27 $and$libresoc.v:202176$14770_Y + connect \$29 $ne$libresoc.v:202177$14771_Y + connect \$31 $lt$libresoc.v:202178$14772_Y + connect \$7 $and$libresoc.v:202179$14773_Y + connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } + connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } + connect \icp_wb__ack \$7 +end +attribute \src "libresoc.v:202378.1-203427.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" +attribute \generator "nMigen" +module \xics_ics + attribute \src "libresoc.v:203308.3-203357.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:203019.3-203028.6" + wire width 4 $0\cur_idx0[3:0] + attribute \src "libresoc.v:203228.3-203237.6" + wire width 4 $0\cur_idx10[3:0] + attribute \src "libresoc.v:203248.3-203257.6" + wire width 4 $0\cur_idx11[3:0] + attribute \src "libresoc.v:203268.3-203277.6" + wire width 4 $0\cur_idx12[3:0] + attribute \src "libresoc.v:203288.3-203297.6" + wire width 4 $0\cur_idx13[3:0] + attribute \src "libresoc.v:203358.3-203367.6" + wire width 4 $0\cur_idx14[3:0] + attribute \src "libresoc.v:203378.3-203387.6" + wire width 4 $0\cur_idx15[3:0] + attribute \src "libresoc.v:203039.3-203048.6" + wire width 4 $0\cur_idx1[3:0] + attribute \src "libresoc.v:203059.3-203068.6" + wire width 4 $0\cur_idx2[3:0] + attribute \src "libresoc.v:203079.3-203088.6" + wire width 4 $0\cur_idx3[3:0] + attribute \src "libresoc.v:203108.3-203117.6" + wire width 4 $0\cur_idx4[3:0] + attribute \src "libresoc.v:203128.3-203137.6" + wire width 4 $0\cur_idx5[3:0] + attribute \src "libresoc.v:203148.3-203157.6" + wire width 4 $0\cur_idx6[3:0] + attribute \src "libresoc.v:203168.3-203177.6" + wire width 4 $0\cur_idx7[3:0] + attribute \src "libresoc.v:203188.3-203197.6" + wire width 4 $0\cur_idx8[3:0] + attribute \src "libresoc.v:203208.3-203217.6" + wire width 4 $0\cur_idx9[3:0] + attribute \src "libresoc.v:203009.3-203018.6" + wire width 8 $0\cur_pri0[7:0] + attribute \src "libresoc.v:203218.3-203227.6" + wire width 8 $0\cur_pri10[7:0] + attribute \src "libresoc.v:203238.3-203247.6" + wire width 8 $0\cur_pri11[7:0] + attribute \src "libresoc.v:203258.3-203267.6" + wire width 8 $0\cur_pri12[7:0] + attribute \src "libresoc.v:203278.3-203287.6" + wire width 8 $0\cur_pri13[7:0] + attribute \src "libresoc.v:203298.3-203307.6" + wire width 8 $0\cur_pri14[7:0] + attribute \src "libresoc.v:203368.3-203377.6" + wire width 8 $0\cur_pri15[7:0] + attribute \src "libresoc.v:203029.3-203038.6" + wire width 8 $0\cur_pri1[7:0] + attribute \src "libresoc.v:203049.3-203058.6" + wire width 8 $0\cur_pri2[7:0] + attribute \src "libresoc.v:203069.3-203078.6" + wire width 8 $0\cur_pri3[7:0] + attribute \src "libresoc.v:203089.3-203098.6" + wire width 8 $0\cur_pri4[7:0] + attribute \src "libresoc.v:203118.3-203127.6" + wire width 8 $0\cur_pri5[7:0] + attribute \src "libresoc.v:203138.3-203147.6" + wire width 8 $0\cur_pri6[7:0] + attribute \src "libresoc.v:203158.3-203167.6" + wire width 8 $0\cur_pri7[7:0] + attribute \src "libresoc.v:203178.3-203187.6" + wire width 8 $0\cur_pri8[7:0] + attribute \src "libresoc.v:203198.3-203207.6" + wire width 8 $0\cur_pri9[7:0] + attribute \src "libresoc.v:203388.3-203397.6" + wire $0\ibit[0:0] + attribute \src "libresoc.v:202883.3-202884.25" + wire width 8 $0\icp_o_pri[7:0] + attribute \src "libresoc.v:202881.3-202882.28" + wire width 4 $0\icp_o_src[3:0] + attribute \src "libresoc.v:203407.3-203415.6" + wire $0\ics_wb__ack$next[0:0]$15074 + attribute \src "libresoc.v:202917.3-202918.39" + wire $0\ics_wb__ack[0:0] + attribute \src "libresoc.v:203398.3-203406.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15071 + attribute \src "libresoc.v:202919.3-202920.43" + wire width 32 $0\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:202379.7-202379.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:203099.3-203107.6" + wire width 16 $0\int_level_l$next[15:0]$15043 + attribute \src "libresoc.v:202921.3-202922.39" + wire width 16 $0\int_level_l[15:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive0_pri$next[7:0]$14953 + attribute \src "libresoc.v:202885.3-202886.35" + wire width 8 $0\xive0_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive10_pri$next[7:0]$14954 + attribute \src "libresoc.v:202905.3-202906.37" + wire width 8 $0\xive10_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive11_pri$next[7:0]$14955 + attribute \src "libresoc.v:202907.3-202908.37" + wire width 8 $0\xive11_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive12_pri$next[7:0]$14956 + attribute \src "libresoc.v:202909.3-202910.37" + wire width 8 $0\xive12_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive13_pri$next[7:0]$14957 + attribute \src "libresoc.v:202911.3-202912.37" + wire width 8 $0\xive13_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive14_pri$next[7:0]$14958 + attribute \src "libresoc.v:202913.3-202914.37" + wire width 8 $0\xive14_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive15_pri$next[7:0]$14959 + attribute \src "libresoc.v:202915.3-202916.37" + wire width 8 $0\xive15_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive1_pri$next[7:0]$14960 + attribute \src "libresoc.v:202887.3-202888.35" + wire width 8 $0\xive1_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive2_pri$next[7:0]$14961 + attribute \src "libresoc.v:202889.3-202890.35" + wire width 8 $0\xive2_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive3_pri$next[7:0]$14962 + attribute \src "libresoc.v:202891.3-202892.35" + wire width 8 $0\xive3_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive4_pri$next[7:0]$14963 + attribute \src "libresoc.v:202893.3-202894.35" + wire width 8 $0\xive4_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive5_pri$next[7:0]$14964 + attribute \src "libresoc.v:202895.3-202896.35" + wire width 8 $0\xive5_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive6_pri$next[7:0]$14965 + attribute \src "libresoc.v:202897.3-202898.35" + wire width 8 $0\xive6_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive7_pri$next[7:0]$14966 + attribute \src "libresoc.v:202899.3-202900.35" + wire width 8 $0\xive7_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive8_pri$next[7:0]$14967 + attribute \src "libresoc.v:202901.3-202902.35" + wire width 8 $0\xive8_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive9_pri$next[7:0]$14968 + attribute \src "libresoc.v:202903.3-202904.35" + wire width 8 $0\xive9_pri[7:0] + attribute \src "libresoc.v:203308.3-203357.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:203019.3-203028.6" + wire width 4 $1\cur_idx0[3:0] + attribute \src "libresoc.v:203228.3-203237.6" + wire width 4 $1\cur_idx10[3:0] + attribute \src "libresoc.v:203248.3-203257.6" + wire width 4 $1\cur_idx11[3:0] + attribute \src "libresoc.v:203268.3-203277.6" + wire width 4 $1\cur_idx12[3:0] + attribute \src "libresoc.v:203288.3-203297.6" + wire width 4 $1\cur_idx13[3:0] + attribute \src "libresoc.v:203358.3-203367.6" + wire width 4 $1\cur_idx14[3:0] + attribute \src "libresoc.v:203378.3-203387.6" + wire width 4 $1\cur_idx15[3:0] + attribute \src "libresoc.v:203039.3-203048.6" + wire width 4 $1\cur_idx1[3:0] + attribute \src "libresoc.v:203059.3-203068.6" + wire width 4 $1\cur_idx2[3:0] + attribute \src "libresoc.v:203079.3-203088.6" + wire width 4 $1\cur_idx3[3:0] + attribute \src "libresoc.v:203108.3-203117.6" + wire width 4 $1\cur_idx4[3:0] + attribute \src "libresoc.v:203128.3-203137.6" + wire width 4 $1\cur_idx5[3:0] + attribute \src "libresoc.v:203148.3-203157.6" + wire width 4 $1\cur_idx6[3:0] + attribute \src "libresoc.v:203168.3-203177.6" + wire width 4 $1\cur_idx7[3:0] + attribute \src "libresoc.v:203188.3-203197.6" + wire width 4 $1\cur_idx8[3:0] + attribute \src "libresoc.v:203208.3-203217.6" + wire width 4 $1\cur_idx9[3:0] + attribute \src "libresoc.v:203009.3-203018.6" + wire width 8 $1\cur_pri0[7:0] + attribute \src "libresoc.v:203218.3-203227.6" + wire width 8 $1\cur_pri10[7:0] + attribute \src "libresoc.v:203238.3-203247.6" + wire width 8 $1\cur_pri11[7:0] + attribute \src "libresoc.v:203258.3-203267.6" + wire width 8 $1\cur_pri12[7:0] + attribute \src "libresoc.v:203278.3-203287.6" + wire width 8 $1\cur_pri13[7:0] + attribute \src "libresoc.v:203298.3-203307.6" + wire width 8 $1\cur_pri14[7:0] + attribute \src "libresoc.v:203368.3-203377.6" + wire width 8 $1\cur_pri15[7:0] + attribute \src "libresoc.v:203029.3-203038.6" + wire width 8 $1\cur_pri1[7:0] + attribute \src "libresoc.v:203049.3-203058.6" + wire width 8 $1\cur_pri2[7:0] + attribute \src "libresoc.v:203069.3-203078.6" + wire width 8 $1\cur_pri3[7:0] + attribute \src "libresoc.v:203089.3-203098.6" + wire width 8 $1\cur_pri4[7:0] + attribute \src "libresoc.v:203118.3-203127.6" + wire width 8 $1\cur_pri5[7:0] + attribute \src "libresoc.v:203138.3-203147.6" + wire width 8 $1\cur_pri6[7:0] + attribute \src "libresoc.v:203158.3-203167.6" + wire width 8 $1\cur_pri7[7:0] + attribute \src "libresoc.v:203178.3-203187.6" + wire width 8 $1\cur_pri8[7:0] + attribute \src "libresoc.v:203198.3-203207.6" + wire width 8 $1\cur_pri9[7:0] + attribute \src "libresoc.v:203388.3-203397.6" + wire $1\ibit[0:0] + attribute \src "libresoc.v:202660.13-202660.30" + wire width 8 $1\icp_o_pri[7:0] + attribute \src "libresoc.v:202665.13-202665.29" + wire width 4 $1\icp_o_src[3:0] + attribute \src "libresoc.v:203407.3-203415.6" + wire $1\ics_wb__ack$next[0:0]$15075 + attribute \src "libresoc.v:202674.7-202674.25" + wire $1\ics_wb__ack[0:0] + attribute \src "libresoc.v:203398.3-203406.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15072 + attribute \src "libresoc.v:202683.14-202683.35" + wire width 32 $1\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:203099.3-203107.6" + wire width 16 $1\int_level_l$next[15:0]$15044 + attribute \src "libresoc.v:202695.14-202695.36" + wire width 16 $1\int_level_l[15:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive0_pri$next[7:0]$14969 + attribute \src "libresoc.v:202715.13-202715.30" + wire width 8 $1\xive0_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive10_pri$next[7:0]$14970 + attribute \src "libresoc.v:202719.13-202719.31" + wire width 8 $1\xive10_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive11_pri$next[7:0]$14971 + attribute \src "libresoc.v:202723.13-202723.31" + wire width 8 $1\xive11_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive12_pri$next[7:0]$14972 + attribute \src "libresoc.v:202727.13-202727.31" + wire width 8 $1\xive12_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive13_pri$next[7:0]$14973 + attribute \src "libresoc.v:202731.13-202731.31" + wire width 8 $1\xive13_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive14_pri$next[7:0]$14974 + attribute \src "libresoc.v:202735.13-202735.31" + wire width 8 $1\xive14_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive15_pri$next[7:0]$14975 + attribute \src "libresoc.v:202739.13-202739.31" + wire width 8 $1\xive15_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive1_pri$next[7:0]$14976 + attribute \src "libresoc.v:202743.13-202743.30" + wire width 8 $1\xive1_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive2_pri$next[7:0]$14977 + attribute \src "libresoc.v:202747.13-202747.30" + wire width 8 $1\xive2_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive3_pri$next[7:0]$14978 + attribute \src "libresoc.v:202751.13-202751.30" + wire width 8 $1\xive3_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive4_pri$next[7:0]$14979 + attribute \src "libresoc.v:202755.13-202755.30" + wire width 8 $1\xive4_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive5_pri$next[7:0]$14980 + attribute \src "libresoc.v:202759.13-202759.30" + wire width 8 $1\xive5_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive6_pri$next[7:0]$14981 + attribute \src "libresoc.v:202763.13-202763.30" + wire width 8 $1\xive6_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive7_pri$next[7:0]$14982 + attribute \src "libresoc.v:202767.13-202767.30" + wire width 8 $1\xive7_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive8_pri$next[7:0]$14983 + attribute \src "libresoc.v:202771.13-202771.30" + wire width 8 $1\xive8_pri[7:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive9_pri$next[7:0]$14984 + attribute \src "libresoc.v:202775.13-202775.30" + wire width 8 $1\xive9_pri[7:0] + attribute \src "libresoc.v:203308.3-203357.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive0_pri$next[7:0]$14985 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive10_pri$next[7:0]$14986 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive11_pri$next[7:0]$14987 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive12_pri$next[7:0]$14988 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive13_pri$next[7:0]$14989 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive14_pri$next[7:0]$14990 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive15_pri$next[7:0]$14991 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive1_pri$next[7:0]$14992 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive2_pri$next[7:0]$14993 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive3_pri$next[7:0]$14994 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive4_pri$next[7:0]$14995 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive5_pri$next[7:0]$14996 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive6_pri$next[7:0]$14997 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive7_pri$next[7:0]$14998 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive8_pri$next[7:0]$14999 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $2\xive9_pri$next[7:0]$15000 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive0_pri$next[7:0]$15001 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive10_pri$next[7:0]$15002 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive11_pri$next[7:0]$15003 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive12_pri$next[7:0]$15004 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive13_pri$next[7:0]$15005 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive14_pri$next[7:0]$15006 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive15_pri$next[7:0]$15007 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive1_pri$next[7:0]$15008 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive2_pri$next[7:0]$15009 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive3_pri$next[7:0]$15010 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive4_pri$next[7:0]$15011 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive5_pri$next[7:0]$15012 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive6_pri$next[7:0]$15013 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive7_pri$next[7:0]$15014 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive8_pri$next[7:0]$15015 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $3\xive9_pri$next[7:0]$15016 + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $4\xive0_pri$next[7:0]$15017 + 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connect \Y $lt$libresoc.v:202820$14870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202823$14873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:202823$14873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202825$14875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:202825$14875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202827$14877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:202827$14877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202829$14879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:202829$14879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202831$14881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:202831$14881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202834$14884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:202834$14884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202868$14918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:202868$14918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202870$14920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:202870$14920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202872$14922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:202872$14922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202874$14924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:202874$14924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202877$14927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:202877$14927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:202879$14929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:202879$14929_Y + end + attribute \src "libresoc.v:202866.18-202866.40" + cell $shr $shr$libresoc.v:202866$14916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \int_level_l + connect \B \reg_idx + connect \Y $shr$libresoc.v:202866$14916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202778$14828 + parameter \WIDTH 8 + connect \A \xive0_pri + connect \B 8'11111111 + connect \S \$8 + connect \Y $ternary$libresoc.v:202778$14828_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202800$14850 + parameter \WIDTH 8 + connect \A \xive1_pri + connect \B 8'11111111 + connect \S \$12 + connect \Y $ternary$libresoc.v:202800$14850_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202822$14872 + parameter \WIDTH 8 + connect \A \xive2_pri + connect \B 8'11111111 + connect \S \$16 + connect \Y $ternary$libresoc.v:202822$14872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202837$14887 + parameter \WIDTH 8 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \S \$204 + connect \Y $ternary$libresoc.v:202837$14887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202839$14889 + parameter \WIDTH 8 + connect \A \xive3_pri + connect \B 8'11111111 + connect \S \$20 + connect \Y $ternary$libresoc.v:202839$14889_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202841$14891 + parameter \WIDTH 8 + connect \A \xive4_pri + connect \B 8'11111111 + connect \S \$24 + connect \Y $ternary$libresoc.v:202841$14891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202843$14893 + parameter \WIDTH 8 + connect \A \xive5_pri + connect \B 8'11111111 + connect \S \$28 + connect \Y $ternary$libresoc.v:202843$14893_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202845$14895 + parameter \WIDTH 8 + connect \A \xive6_pri + connect \B 8'11111111 + connect \S \$32 + connect \Y $ternary$libresoc.v:202845$14895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202847$14897 + parameter \WIDTH 8 + connect \A \xive7_pri + connect \B 8'11111111 + connect \S \$36 + connect \Y $ternary$libresoc.v:202847$14897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202850$14900 + parameter \WIDTH 8 + connect \A \xive8_pri + connect \B 8'11111111 + connect \S \$40 + connect \Y $ternary$libresoc.v:202850$14900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202852$14902 + parameter \WIDTH 8 + connect \A \xive9_pri + connect \B 8'11111111 + connect \S \$44 + connect \Y $ternary$libresoc.v:202852$14902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202854$14904 + parameter \WIDTH 8 + connect \A \xive10_pri + connect \B 8'11111111 + connect \S \$48 + connect \Y $ternary$libresoc.v:202854$14904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202856$14906 + parameter \WIDTH 8 + connect \A \xive11_pri + connect \B 8'11111111 + connect \S \$52 + connect \Y $ternary$libresoc.v:202856$14906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202858$14908 + parameter \WIDTH 8 + connect \A \xive12_pri + connect \B 8'11111111 + connect \S \$56 + connect \Y $ternary$libresoc.v:202858$14908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202861$14911 + parameter \WIDTH 8 + connect \A \xive13_pri + connect \B 8'11111111 + connect \S \$60 + connect \Y $ternary$libresoc.v:202861$14911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202863$14913 + parameter \WIDTH 8 + connect \A \xive14_pri + connect \B 8'11111111 + connect \S \$64 + connect \Y $ternary$libresoc.v:202863$14913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:202865$14915 + parameter \WIDTH 8 + connect \A \xive15_pri + connect \B 8'11111111 + connect \S \$68 + connect \Y $ternary$libresoc.v:202865$14915_Y + end + attribute \src "libresoc.v:202379.7-202379.20" + process $proc$libresoc.v:202379$15076 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:202660.13-202660.30" + process $proc$libresoc.v:202660$15077 + assign { } { } + assign $1\icp_o_pri[7:0] 8'00000000 + sync always + sync init + update \icp_o_pri $1\icp_o_pri[7:0] + end + attribute \src "libresoc.v:202665.13-202665.29" + process $proc$libresoc.v:202665$15078 + assign { } { } + assign $1\icp_o_src[3:0] 4'0000 + sync always + sync init + update \icp_o_src $1\icp_o_src[3:0] + end + attribute \src "libresoc.v:202674.7-202674.25" + process $proc$libresoc.v:202674$15079 + assign { } { } + assign $1\ics_wb__ack[0:0] 1'0 + sync always + sync init + update \ics_wb__ack $1\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:202683.14-202683.35" + process $proc$libresoc.v:202683$15080 + assign { } { } + assign $1\ics_wb__dat_r[31:0] 0 + sync always + sync init + update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:202695.14-202695.36" + process $proc$libresoc.v:202695$15081 + assign { } { } + assign $1\int_level_l[15:0] 16'0000000000000000 + sync always + sync init + update \int_level_l $1\int_level_l[15:0] + end + attribute \src "libresoc.v:202715.13-202715.30" + process $proc$libresoc.v:202715$15082 + assign { } { } + assign $1\xive0_pri[7:0] 8'11111111 + sync always + sync init + update \xive0_pri $1\xive0_pri[7:0] + end + attribute \src "libresoc.v:202719.13-202719.31" + process $proc$libresoc.v:202719$15083 + assign { } { } + assign $1\xive10_pri[7:0] 8'11111111 + sync always + sync init + update \xive10_pri $1\xive10_pri[7:0] + end + attribute \src "libresoc.v:202723.13-202723.31" + process $proc$libresoc.v:202723$15084 + assign { } { } + assign $1\xive11_pri[7:0] 8'11111111 + sync always + sync init + update \xive11_pri $1\xive11_pri[7:0] + end + attribute \src "libresoc.v:202727.13-202727.31" + process $proc$libresoc.v:202727$15085 + assign { } { } + assign $1\xive12_pri[7:0] 8'11111111 + sync always + sync init + update \xive12_pri $1\xive12_pri[7:0] + end + attribute \src "libresoc.v:202731.13-202731.31" + process $proc$libresoc.v:202731$15086 + assign { } { } + assign $1\xive13_pri[7:0] 8'11111111 + sync always + sync init + update \xive13_pri $1\xive13_pri[7:0] + end + attribute \src "libresoc.v:202735.13-202735.31" + process $proc$libresoc.v:202735$15087 + assign { } { } + assign $1\xive14_pri[7:0] 8'11111111 + sync always + sync init + update \xive14_pri $1\xive14_pri[7:0] + end + attribute \src "libresoc.v:202739.13-202739.31" + process $proc$libresoc.v:202739$15088 + assign { } { } + assign $1\xive15_pri[7:0] 8'11111111 + sync always + sync init + update \xive15_pri $1\xive15_pri[7:0] + end + attribute \src "libresoc.v:202743.13-202743.30" + process $proc$libresoc.v:202743$15089 + assign { } { } + assign $1\xive1_pri[7:0] 8'11111111 + sync always + sync init + update \xive1_pri $1\xive1_pri[7:0] + end + attribute \src "libresoc.v:202747.13-202747.30" + process $proc$libresoc.v:202747$15090 + assign { } { } + assign $1\xive2_pri[7:0] 8'11111111 + sync always + sync init + update \xive2_pri $1\xive2_pri[7:0] + end + attribute \src "libresoc.v:202751.13-202751.30" + process $proc$libresoc.v:202751$15091 + assign { } { } + assign $1\xive3_pri[7:0] 8'11111111 + sync always + sync init + update \xive3_pri $1\xive3_pri[7:0] + end + attribute \src "libresoc.v:202755.13-202755.30" + process $proc$libresoc.v:202755$15092 + assign { } { } + assign $1\xive4_pri[7:0] 8'11111111 + sync always + sync init + update \xive4_pri $1\xive4_pri[7:0] + end + attribute \src "libresoc.v:202759.13-202759.30" + process $proc$libresoc.v:202759$15093 + assign { } { } + assign $1\xive5_pri[7:0] 8'11111111 + sync always + sync init + update \xive5_pri $1\xive5_pri[7:0] + end + attribute \src "libresoc.v:202763.13-202763.30" + process $proc$libresoc.v:202763$15094 + assign { } { } + assign $1\xive6_pri[7:0] 8'11111111 + sync always + sync init + update \xive6_pri $1\xive6_pri[7:0] + end + attribute \src "libresoc.v:202767.13-202767.30" + process $proc$libresoc.v:202767$15095 + assign { } { } + assign $1\xive7_pri[7:0] 8'11111111 + sync always + sync init + update \xive7_pri $1\xive7_pri[7:0] + end + attribute \src "libresoc.v:202771.13-202771.30" + process $proc$libresoc.v:202771$15096 + assign { } { } + assign $1\xive8_pri[7:0] 8'11111111 + sync always + sync init + update \xive8_pri $1\xive8_pri[7:0] + end + attribute \src "libresoc.v:202775.13-202775.30" + process $proc$libresoc.v:202775$15097 + assign { } { } + assign $1\xive9_pri[7:0] 8'11111111 + sync always + sync init + update \xive9_pri $1\xive9_pri[7:0] + end + attribute \src "libresoc.v:202881.3-202882.28" + process $proc$libresoc.v:202881$14931 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "libresoc.v:202883.3-202884.25" + process $proc$libresoc.v:202883$14932 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "libresoc.v:202885.3-202886.35" + process $proc$libresoc.v:202885$14933 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "libresoc.v:202887.3-202888.35" + process $proc$libresoc.v:202887$14934 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "libresoc.v:202889.3-202890.35" + process $proc$libresoc.v:202889$14935 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "libresoc.v:202891.3-202892.35" + process $proc$libresoc.v:202891$14936 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "libresoc.v:202893.3-202894.35" + process $proc$libresoc.v:202893$14937 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "libresoc.v:202895.3-202896.35" + process $proc$libresoc.v:202895$14938 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "libresoc.v:202897.3-202898.35" + process $proc$libresoc.v:202897$14939 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "libresoc.v:202899.3-202900.35" + process $proc$libresoc.v:202899$14940 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "libresoc.v:202901.3-202902.35" + process $proc$libresoc.v:202901$14941 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "libresoc.v:202903.3-202904.35" + process $proc$libresoc.v:202903$14942 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "libresoc.v:202905.3-202906.37" + process $proc$libresoc.v:202905$14943 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "libresoc.v:202907.3-202908.37" + process $proc$libresoc.v:202907$14944 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "libresoc.v:202909.3-202910.37" + process $proc$libresoc.v:202909$14945 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "libresoc.v:202911.3-202912.37" + process $proc$libresoc.v:202911$14946 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "libresoc.v:202913.3-202914.37" + process $proc$libresoc.v:202913$14947 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "libresoc.v:202915.3-202916.37" + process $proc$libresoc.v:202915$14948 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "libresoc.v:202917.3-202918.39" + process $proc$libresoc.v:202917$14949 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:202919.3-202920.43" + process $proc$libresoc.v:202919$14950 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:202921.3-202922.39" + process $proc$libresoc.v:202921$14951 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "libresoc.v:202923.3-203008.6" + process $proc$libresoc.v:202923$14952 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xive0_pri$next[7:0]$14953 $4\xive0_pri$next[7:0]$15017 + assign $0\xive10_pri$next[7:0]$14954 $4\xive10_pri$next[7:0]$15018 + assign $0\xive11_pri$next[7:0]$14955 $4\xive11_pri$next[7:0]$15019 + assign $0\xive12_pri$next[7:0]$14956 $4\xive12_pri$next[7:0]$15020 + assign $0\xive13_pri$next[7:0]$14957 $4\xive13_pri$next[7:0]$15021 + assign $0\xive14_pri$next[7:0]$14958 $4\xive14_pri$next[7:0]$15022 + assign $0\xive15_pri$next[7:0]$14959 $4\xive15_pri$next[7:0]$15023 + assign $0\xive1_pri$next[7:0]$14960 $4\xive1_pri$next[7:0]$15024 + assign $0\xive2_pri$next[7:0]$14961 $4\xive2_pri$next[7:0]$15025 + assign $0\xive3_pri$next[7:0]$14962 $4\xive3_pri$next[7:0]$15026 + assign $0\xive4_pri$next[7:0]$14963 $4\xive4_pri$next[7:0]$15027 + assign $0\xive5_pri$next[7:0]$14964 $4\xive5_pri$next[7:0]$15028 + assign $0\xive6_pri$next[7:0]$14965 $4\xive6_pri$next[7:0]$15029 + assign $0\xive7_pri$next[7:0]$14966 $4\xive7_pri$next[7:0]$15030 + assign $0\xive8_pri$next[7:0]$14967 $4\xive8_pri$next[7:0]$15031 + assign $0\xive9_pri$next[7:0]$14968 $4\xive9_pri$next[7:0]$15032 + attribute \src "libresoc.v:202924.5-202924.29" + switch \initial + attribute \src "libresoc.v:202924.9-202924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xive0_pri$next[7:0]$14969 $2\xive0_pri$next[7:0]$14985 + assign $1\xive10_pri$next[7:0]$14970 $2\xive10_pri$next[7:0]$14986 + assign $1\xive11_pri$next[7:0]$14971 $2\xive11_pri$next[7:0]$14987 + assign $1\xive12_pri$next[7:0]$14972 $2\xive12_pri$next[7:0]$14988 + assign $1\xive13_pri$next[7:0]$14973 $2\xive13_pri$next[7:0]$14989 + assign $1\xive14_pri$next[7:0]$14974 $2\xive14_pri$next[7:0]$14990 + assign $1\xive15_pri$next[7:0]$14975 $2\xive15_pri$next[7:0]$14991 + assign $1\xive1_pri$next[7:0]$14976 $2\xive1_pri$next[7:0]$14992 + assign $1\xive2_pri$next[7:0]$14977 $2\xive2_pri$next[7:0]$14993 + assign $1\xive3_pri$next[7:0]$14978 $2\xive3_pri$next[7:0]$14994 + assign $1\xive4_pri$next[7:0]$14979 $2\xive4_pri$next[7:0]$14995 + assign $1\xive5_pri$next[7:0]$14980 $2\xive5_pri$next[7:0]$14996 + assign $1\xive6_pri$next[7:0]$14981 $2\xive6_pri$next[7:0]$14997 + assign $1\xive7_pri$next[7:0]$14982 $2\xive7_pri$next[7:0]$14998 + assign $1\xive8_pri$next[7:0]$14983 $2\xive8_pri$next[7:0]$14999 + assign $1\xive9_pri$next[7:0]$14984 $2\xive9_pri$next[7:0]$15000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" + switch \reg_is_xive + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\xive0_pri$next[7:0]$14985 $3\xive0_pri$next[7:0]$15001 + assign $2\xive10_pri$next[7:0]$14986 $3\xive10_pri$next[7:0]$15002 + assign $2\xive11_pri$next[7:0]$14987 $3\xive11_pri$next[7:0]$15003 + assign $2\xive12_pri$next[7:0]$14988 $3\xive12_pri$next[7:0]$15004 + assign $2\xive13_pri$next[7:0]$14989 $3\xive13_pri$next[7:0]$15005 + assign $2\xive14_pri$next[7:0]$14990 $3\xive14_pri$next[7:0]$15006 + assign $2\xive15_pri$next[7:0]$14991 $3\xive15_pri$next[7:0]$15007 + assign $2\xive1_pri$next[7:0]$14992 $3\xive1_pri$next[7:0]$15008 + assign $2\xive2_pri$next[7:0]$14993 $3\xive2_pri$next[7:0]$15009 + assign $2\xive3_pri$next[7:0]$14994 $3\xive3_pri$next[7:0]$15010 + assign $2\xive4_pri$next[7:0]$14995 $3\xive4_pri$next[7:0]$15011 + assign $2\xive5_pri$next[7:0]$14996 $3\xive5_pri$next[7:0]$15012 + assign $2\xive6_pri$next[7:0]$14997 $3\xive6_pri$next[7:0]$15013 + assign $2\xive7_pri$next[7:0]$14998 $3\xive7_pri$next[7:0]$15014 + assign $2\xive8_pri$next[7:0]$14999 $3\xive8_pri$next[7:0]$15015 + assign $2\xive9_pri$next[7:0]$15000 $3\xive9_pri$next[7:0]$15016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive0_pri$next[7:0]$15001 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign { } { } + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive1_pri$next[7:0]$15008 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign { } { } + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive2_pri$next[7:0]$15009 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign { } { } + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive3_pri$next[7:0]$15010 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign { } { } + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive4_pri$next[7:0]$15011 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign { } { } + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive5_pri$next[7:0]$15012 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign { } { } + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive6_pri$next[7:0]$15013 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign { } { } + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive7_pri$next[7:0]$15014 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive8_pri$next[7:0]$15015 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$15016 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign { } { } + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive10_pri$next[7:0]$15002 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign { } { } + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive11_pri$next[7:0]$15003 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign { } { } + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive12_pri$next[7:0]$15004 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign { } { } + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive13_pri$next[7:0]$15005 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign { } { } + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive14_pri$next[7:0]$15006 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign { } { } + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive15_pri$next[7:0]$15007 \be_in [7:0] + case + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + end + case + assign $2\xive0_pri$next[7:0]$14985 \xive0_pri + assign $2\xive10_pri$next[7:0]$14986 \xive10_pri + assign $2\xive11_pri$next[7:0]$14987 \xive11_pri + assign $2\xive12_pri$next[7:0]$14988 \xive12_pri + assign $2\xive13_pri$next[7:0]$14989 \xive13_pri + assign $2\xive14_pri$next[7:0]$14990 \xive14_pri + assign $2\xive15_pri$next[7:0]$14991 \xive15_pri + assign $2\xive1_pri$next[7:0]$14992 \xive1_pri + assign $2\xive2_pri$next[7:0]$14993 \xive2_pri + assign $2\xive3_pri$next[7:0]$14994 \xive3_pri + assign $2\xive4_pri$next[7:0]$14995 \xive4_pri + assign $2\xive5_pri$next[7:0]$14996 \xive5_pri + assign $2\xive6_pri$next[7:0]$14997 \xive6_pri + assign $2\xive7_pri$next[7:0]$14998 \xive7_pri + assign $2\xive8_pri$next[7:0]$14999 \xive8_pri + assign $2\xive9_pri$next[7:0]$15000 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14969 \xive0_pri + assign $1\xive10_pri$next[7:0]$14970 \xive10_pri + assign $1\xive11_pri$next[7:0]$14971 \xive11_pri + assign $1\xive12_pri$next[7:0]$14972 \xive12_pri + assign $1\xive13_pri$next[7:0]$14973 \xive13_pri + assign $1\xive14_pri$next[7:0]$14974 \xive14_pri + assign $1\xive15_pri$next[7:0]$14975 \xive15_pri + assign $1\xive1_pri$next[7:0]$14976 \xive1_pri + assign $1\xive2_pri$next[7:0]$14977 \xive2_pri + assign $1\xive3_pri$next[7:0]$14978 \xive3_pri + assign $1\xive4_pri$next[7:0]$14979 \xive4_pri + assign $1\xive5_pri$next[7:0]$14980 \xive5_pri + assign $1\xive6_pri$next[7:0]$14981 \xive6_pri + assign $1\xive7_pri$next[7:0]$14982 \xive7_pri + assign $1\xive8_pri$next[7:0]$14983 \xive8_pri + assign $1\xive9_pri$next[7:0]$14984 \xive9_pri + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\xive0_pri$next[7:0]$15017 8'11111111 + assign $4\xive1_pri$next[7:0]$15024 8'11111111 + assign $4\xive2_pri$next[7:0]$15025 8'11111111 + assign $4\xive3_pri$next[7:0]$15026 8'11111111 + assign $4\xive4_pri$next[7:0]$15027 8'11111111 + assign $4\xive5_pri$next[7:0]$15028 8'11111111 + assign $4\xive6_pri$next[7:0]$15029 8'11111111 + assign $4\xive7_pri$next[7:0]$15030 8'11111111 + assign $4\xive8_pri$next[7:0]$15031 8'11111111 + assign $4\xive9_pri$next[7:0]$15032 8'11111111 + assign $4\xive10_pri$next[7:0]$15018 8'11111111 + assign $4\xive11_pri$next[7:0]$15019 8'11111111 + assign $4\xive12_pri$next[7:0]$15020 8'11111111 + assign $4\xive13_pri$next[7:0]$15021 8'11111111 + assign $4\xive14_pri$next[7:0]$15022 8'11111111 + assign $4\xive15_pri$next[7:0]$15023 8'11111111 + case + assign $4\xive0_pri$next[7:0]$15017 $1\xive0_pri$next[7:0]$14969 + assign $4\xive10_pri$next[7:0]$15018 $1\xive10_pri$next[7:0]$14970 + assign $4\xive11_pri$next[7:0]$15019 $1\xive11_pri$next[7:0]$14971 + assign $4\xive12_pri$next[7:0]$15020 $1\xive12_pri$next[7:0]$14972 + assign $4\xive13_pri$next[7:0]$15021 $1\xive13_pri$next[7:0]$14973 + assign $4\xive14_pri$next[7:0]$15022 $1\xive14_pri$next[7:0]$14974 + assign $4\xive15_pri$next[7:0]$15023 $1\xive15_pri$next[7:0]$14975 + assign $4\xive1_pri$next[7:0]$15024 $1\xive1_pri$next[7:0]$14976 + assign $4\xive2_pri$next[7:0]$15025 $1\xive2_pri$next[7:0]$14977 + assign $4\xive3_pri$next[7:0]$15026 $1\xive3_pri$next[7:0]$14978 + assign $4\xive4_pri$next[7:0]$15027 $1\xive4_pri$next[7:0]$14979 + assign $4\xive5_pri$next[7:0]$15028 $1\xive5_pri$next[7:0]$14980 + assign $4\xive6_pri$next[7:0]$15029 $1\xive6_pri$next[7:0]$14981 + assign $4\xive7_pri$next[7:0]$15030 $1\xive7_pri$next[7:0]$14982 + assign $4\xive8_pri$next[7:0]$15031 $1\xive8_pri$next[7:0]$14983 + assign $4\xive9_pri$next[7:0]$15032 $1\xive9_pri$next[7:0]$14984 + end + sync always + update \xive0_pri$next $0\xive0_pri$next[7:0]$14953 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14954 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14955 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14956 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14957 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14958 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14959 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14960 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14961 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14962 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14963 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14964 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14965 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14966 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14967 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14968 + end + attribute \src "libresoc.v:203009.3-203018.6" + process $proc$libresoc.v:203009$15033 + assign { } { } + assign { } { } + assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] + attribute \src "libresoc.v:203010.5-203010.29" + switch \initial + attribute \src "libresoc.v:203010.9-203010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri0[7:0] \xive0_pri + case + assign $1\cur_pri0[7:0] \max_pri + end + sync always + update \cur_pri0 $0\cur_pri0[7:0] + end + attribute \src "libresoc.v:203019.3-203028.6" + process $proc$libresoc.v:203019$15034 + assign { } { } + assign { } { } + assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] + attribute \src "libresoc.v:203020.5-203020.29" + switch \initial + attribute \src "libresoc.v:203020.9-203020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx0[3:0] 4'0000 + case + assign $1\cur_idx0[3:0] \max_idx + end + sync always + update \cur_idx0 $0\cur_idx0[3:0] + end + attribute \src "libresoc.v:203029.3-203038.6" + process $proc$libresoc.v:203029$15035 + assign { } { } + assign { } { } + assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] + attribute \src "libresoc.v:203030.5-203030.29" + switch \initial + attribute \src "libresoc.v:203030.9-203030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri1[7:0] \xive1_pri + case + assign $1\cur_pri1[7:0] \cur_pri0 + end + sync always + update \cur_pri1 $0\cur_pri1[7:0] + end + attribute \src "libresoc.v:203039.3-203048.6" + process $proc$libresoc.v:203039$15036 + assign { } { } + assign { } { } + assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] + attribute \src "libresoc.v:203040.5-203040.29" + switch \initial + attribute \src "libresoc.v:203040.9-203040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx1[3:0] 4'0001 + case + assign $1\cur_idx1[3:0] \cur_idx0 + end + sync always + update \cur_idx1 $0\cur_idx1[3:0] + end + attribute \src "libresoc.v:203049.3-203058.6" + process $proc$libresoc.v:203049$15037 + assign { } { } + assign { } { } + assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] + attribute \src "libresoc.v:203050.5-203050.29" + switch \initial + attribute \src "libresoc.v:203050.9-203050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri2[7:0] \xive2_pri + case + assign $1\cur_pri2[7:0] \cur_pri1 + end + sync always + update \cur_pri2 $0\cur_pri2[7:0] + end + attribute \src "libresoc.v:203059.3-203068.6" + process $proc$libresoc.v:203059$15038 + assign { } { } + assign { } { } + assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] + attribute \src "libresoc.v:203060.5-203060.29" + switch \initial + attribute \src "libresoc.v:203060.9-203060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx2[3:0] 4'0010 + case + assign $1\cur_idx2[3:0] \cur_idx1 + end + sync always + update \cur_idx2 $0\cur_idx2[3:0] + end + attribute \src "libresoc.v:203069.3-203078.6" + process $proc$libresoc.v:203069$15039 + assign { } { } + assign { } { } + assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] + attribute \src "libresoc.v:203070.5-203070.29" + switch \initial + attribute \src "libresoc.v:203070.9-203070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri3[7:0] \xive3_pri + case + assign $1\cur_pri3[7:0] \cur_pri2 + end + sync always + update \cur_pri3 $0\cur_pri3[7:0] + end + attribute \src "libresoc.v:203079.3-203088.6" + process $proc$libresoc.v:203079$15040 + assign { } { } + assign { } { } + assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] + attribute \src "libresoc.v:203080.5-203080.29" + switch \initial + attribute \src "libresoc.v:203080.9-203080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx3[3:0] 4'0011 + case + assign $1\cur_idx3[3:0] \cur_idx2 + end + sync always + update \cur_idx3 $0\cur_idx3[3:0] + end + attribute \src "libresoc.v:203089.3-203098.6" + process $proc$libresoc.v:203089$15041 + assign { } { } + assign { } { } + assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] + attribute \src "libresoc.v:203090.5-203090.29" + switch \initial + attribute \src "libresoc.v:203090.9-203090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri4[7:0] \xive4_pri + case + assign $1\cur_pri4[7:0] \cur_pri3 + end + sync always + update \cur_pri4 $0\cur_pri4[7:0] + end + attribute \src "libresoc.v:203099.3-203107.6" + process $proc$libresoc.v:203099$15042 + assign { } { } + assign { } { } + assign $0\int_level_l$next[15:0]$15043 $1\int_level_l$next[15:0]$15044 + attribute \src "libresoc.v:203100.5-203100.29" + switch \initial + attribute \src "libresoc.v:203100.9-203100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\int_level_l$next[15:0]$15044 16'0000000000000000 + case + assign $1\int_level_l$next[15:0]$15044 \int_level_i + end + sync always + update \int_level_l$next $0\int_level_l$next[15:0]$15043 + end + attribute \src "libresoc.v:203108.3-203117.6" + process $proc$libresoc.v:203108$15045 + assign { } { } + assign { } { } + assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] + attribute \src "libresoc.v:203109.5-203109.29" + switch \initial + attribute \src "libresoc.v:203109.9-203109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx4[3:0] 4'0100 + case + assign $1\cur_idx4[3:0] \cur_idx3 + end + sync always + update \cur_idx4 $0\cur_idx4[3:0] + end + attribute \src "libresoc.v:203118.3-203127.6" + process $proc$libresoc.v:203118$15046 + assign { } { } + assign { } { } + assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] + attribute \src "libresoc.v:203119.5-203119.29" + switch \initial + attribute \src "libresoc.v:203119.9-203119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri5[7:0] \xive5_pri + case + assign $1\cur_pri5[7:0] \cur_pri4 + end + sync always + update \cur_pri5 $0\cur_pri5[7:0] + end + attribute \src "libresoc.v:203128.3-203137.6" + process $proc$libresoc.v:203128$15047 + assign { } { } + assign { } { } + assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] + attribute \src "libresoc.v:203129.5-203129.29" + switch \initial + attribute \src "libresoc.v:203129.9-203129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx5[3:0] 4'0101 + case + assign $1\cur_idx5[3:0] \cur_idx4 + end + sync always + update \cur_idx5 $0\cur_idx5[3:0] + end + attribute \src "libresoc.v:203138.3-203147.6" + process $proc$libresoc.v:203138$15048 + assign { } { } + assign { } { } + assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] + attribute \src "libresoc.v:203139.5-203139.29" + switch \initial + attribute \src "libresoc.v:203139.9-203139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri6[7:0] \xive6_pri + case + assign $1\cur_pri6[7:0] \cur_pri5 + end + sync always + update \cur_pri6 $0\cur_pri6[7:0] + end + attribute \src "libresoc.v:203148.3-203157.6" + process $proc$libresoc.v:203148$15049 + assign { } { } + assign { } { } + assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] + attribute \src "libresoc.v:203149.5-203149.29" + switch \initial + attribute \src "libresoc.v:203149.9-203149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx6[3:0] 4'0110 + case + assign $1\cur_idx6[3:0] \cur_idx5 + end + sync always + update \cur_idx6 $0\cur_idx6[3:0] + end + attribute \src "libresoc.v:203158.3-203167.6" + process $proc$libresoc.v:203158$15050 + assign { } { } + assign { } { } + assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] + attribute \src "libresoc.v:203159.5-203159.29" + switch \initial + attribute \src "libresoc.v:203159.9-203159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri7[7:0] \xive7_pri + case + assign $1\cur_pri7[7:0] \cur_pri6 + end + sync always + update \cur_pri7 $0\cur_pri7[7:0] + end + attribute \src "libresoc.v:203168.3-203177.6" + process $proc$libresoc.v:203168$15051 + assign { } { } + assign { } { } + assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] + attribute \src "libresoc.v:203169.5-203169.29" + switch \initial + attribute \src "libresoc.v:203169.9-203169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx7[3:0] 4'0111 + case + assign $1\cur_idx7[3:0] \cur_idx6 + end + sync always + update \cur_idx7 $0\cur_idx7[3:0] + end + attribute \src "libresoc.v:203178.3-203187.6" + process $proc$libresoc.v:203178$15052 + assign { } { } + assign { } { } + assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] + attribute \src "libresoc.v:203179.5-203179.29" + switch \initial + attribute \src "libresoc.v:203179.9-203179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri8[7:0] \xive8_pri + case + assign $1\cur_pri8[7:0] \cur_pri7 + end + sync always + update \cur_pri8 $0\cur_pri8[7:0] + end + attribute \src "libresoc.v:203188.3-203197.6" + process $proc$libresoc.v:203188$15053 + assign { } { } + assign { } { } + assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] + attribute \src "libresoc.v:203189.5-203189.29" + switch \initial + attribute \src "libresoc.v:203189.9-203189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx8[3:0] 4'1000 + case + assign $1\cur_idx8[3:0] \cur_idx7 + end + sync always + update \cur_idx8 $0\cur_idx8[3:0] + end + attribute \src "libresoc.v:203198.3-203207.6" + process $proc$libresoc.v:203198$15054 + assign { } { } + assign { } { } + assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] + attribute \src "libresoc.v:203199.5-203199.29" + switch \initial + attribute \src "libresoc.v:203199.9-203199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$149 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri9[7:0] \xive9_pri + case + assign $1\cur_pri9[7:0] \cur_pri8 + end + sync always + update \cur_pri9 $0\cur_pri9[7:0] + end + attribute \src "libresoc.v:203208.3-203217.6" + process $proc$libresoc.v:203208$15055 + assign { } { } + assign { } { } + assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] + attribute \src "libresoc.v:203209.5-203209.29" + switch \initial + attribute \src "libresoc.v:203209.9-203209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx9[3:0] 4'1001 + case + assign $1\cur_idx9[3:0] \cur_idx8 + end + sync always + update \cur_idx9 $0\cur_idx9[3:0] + end + attribute \src "libresoc.v:203218.3-203227.6" + process $proc$libresoc.v:203218$15056 + assign { } { } + assign { } { } + assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] + attribute \src "libresoc.v:203219.5-203219.29" + switch \initial + attribute \src "libresoc.v:203219.9-203219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri10[7:0] \xive10_pri + case + assign $1\cur_pri10[7:0] \cur_pri9 + end + sync always + update \cur_pri10 $0\cur_pri10[7:0] + end + attribute \src "libresoc.v:203228.3-203237.6" + process $proc$libresoc.v:203228$15057 + assign { } { } + assign { } { } + assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] + attribute \src "libresoc.v:203229.5-203229.29" + switch \initial + attribute \src "libresoc.v:203229.9-203229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx10[3:0] 4'1010 + case + assign $1\cur_idx10[3:0] \cur_idx9 + end + sync always + update \cur_idx10 $0\cur_idx10[3:0] + end + attribute \src "libresoc.v:203238.3-203247.6" + process $proc$libresoc.v:203238$15058 + assign { } { } + assign { } { } + assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] + attribute \src "libresoc.v:203239.5-203239.29" + switch \initial + attribute \src "libresoc.v:203239.9-203239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri11[7:0] \xive11_pri + case + assign $1\cur_pri11[7:0] \cur_pri10 + end + sync always + update \cur_pri11 $0\cur_pri11[7:0] + end + attribute \src "libresoc.v:203248.3-203257.6" + process $proc$libresoc.v:203248$15059 + assign { } { } + assign { } { } + assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] + attribute \src "libresoc.v:203249.5-203249.29" + switch \initial + attribute \src "libresoc.v:203249.9-203249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx11[3:0] 4'1011 + case + assign $1\cur_idx11[3:0] \cur_idx10 + end + sync always + update \cur_idx11 $0\cur_idx11[3:0] + end + attribute \src "libresoc.v:203258.3-203267.6" + process $proc$libresoc.v:203258$15060 + assign { } { } + assign { } { } + assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] + attribute \src "libresoc.v:203259.5-203259.29" + switch \initial + attribute \src "libresoc.v:203259.9-203259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$173 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri12[7:0] \xive12_pri + case + assign $1\cur_pri12[7:0] \cur_pri11 + end + sync always + update \cur_pri12 $0\cur_pri12[7:0] + end + attribute \src "libresoc.v:203268.3-203277.6" + process $proc$libresoc.v:203268$15061 + assign { } { } + assign { } { } + assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] + attribute \src "libresoc.v:203269.5-203269.29" + switch \initial + attribute \src "libresoc.v:203269.9-203269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx12[3:0] 4'1100 + case + assign $1\cur_idx12[3:0] \cur_idx11 + end + sync always + update \cur_idx12 $0\cur_idx12[3:0] + end + attribute \src "libresoc.v:203278.3-203287.6" + process $proc$libresoc.v:203278$15062 + assign { } { } + assign { } { } + assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] + attribute \src "libresoc.v:203279.5-203279.29" + switch \initial + attribute \src "libresoc.v:203279.9-203279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri13[7:0] \xive13_pri + case + assign $1\cur_pri13[7:0] \cur_pri12 + end + sync always + update \cur_pri13 $0\cur_pri13[7:0] + end + attribute \src "libresoc.v:203288.3-203297.6" + process $proc$libresoc.v:203288$15063 + assign { } { } + assign { } { } + assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] + attribute \src "libresoc.v:203289.5-203289.29" + switch \initial + attribute \src "libresoc.v:203289.9-203289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$185 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx13[3:0] 4'1101 + case + assign $1\cur_idx13[3:0] \cur_idx12 + end + sync always + update \cur_idx13 $0\cur_idx13[3:0] + end + attribute \src "libresoc.v:203298.3-203307.6" + process $proc$libresoc.v:203298$15064 + assign { } { } + assign { } { } + assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] + attribute \src "libresoc.v:203299.5-203299.29" + switch \initial + attribute \src "libresoc.v:203299.9-203299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$189 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri14[7:0] \xive14_pri + case + assign $1\cur_pri14[7:0] \cur_pri13 + end + sync always + update \cur_pri14 $0\cur_pri14[7:0] + end + attribute \src "libresoc.v:203308.3-203357.6" + process $proc$libresoc.v:203308$15065 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:203309.5-203309.29" + switch \initial + attribute \src "libresoc.v:203309.9-203309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } + case + assign $2\be_out[31:0] 0 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\be_out[31:0] 134217744 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:203358.3-203367.6" + process $proc$libresoc.v:203358$15066 + assign { } { } + assign { } { } + assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] + attribute \src "libresoc.v:203359.5-203359.29" + switch \initial + attribute \src "libresoc.v:203359.9-203359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$193 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx14[3:0] 4'1110 + case + assign $1\cur_idx14[3:0] \cur_idx13 + end + sync always + update \cur_idx14 $0\cur_idx14[3:0] + end + attribute \src "libresoc.v:203368.3-203377.6" + process $proc$libresoc.v:203368$15067 + assign { } { } + assign { } { } + assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] + attribute \src "libresoc.v:203369.5-203369.29" + switch \initial + attribute \src "libresoc.v:203369.9-203369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$197 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri15[7:0] \xive15_pri + case + assign $1\cur_pri15[7:0] \cur_pri14 + end + sync always + update \cur_pri15 $0\cur_pri15[7:0] + end + attribute \src "libresoc.v:203378.3-203387.6" + process $proc$libresoc.v:203378$15068 + assign { } { } + assign { } { } + assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] + attribute \src "libresoc.v:203379.5-203379.29" + switch \initial + attribute \src "libresoc.v:203379.9-203379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$201 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx15[3:0] 4'1111 + case + assign $1\cur_idx15[3:0] \cur_idx14 + end + sync always + update \cur_idx15 $0\cur_idx15[3:0] + end + attribute \src "libresoc.v:203388.3-203397.6" + process $proc$libresoc.v:203388$15069 + assign { } { } + assign { } { } + assign $0\ibit[0:0] $1\ibit[0:0] + attribute \src "libresoc.v:203389.5-203389.29" + switch \initial + attribute \src "libresoc.v:203389.9-203389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ibit[0:0] \$71 + case + assign $1\ibit[0:0] 1'0 + end + sync always + update \ibit $0\ibit[0:0] + end + attribute \src "libresoc.v:203398.3-203406.6" + process $proc$libresoc.v:203398$15070 + assign { } { } + assign { } { } + assign $0\ics_wb__dat_r$next[31:0]$15071 $1\ics_wb__dat_r$next[31:0]$15072 + attribute \src "libresoc.v:203399.5-203399.29" + switch \initial + attribute \src "libresoc.v:203399.9-203399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__dat_r$next[31:0]$15072 0 + case + assign $1\ics_wb__dat_r$next[31:0]$15072 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + end + sync always + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15071 + end + attribute \src "libresoc.v:203407.3-203415.6" + process $proc$libresoc.v:203407$15073 + assign { } { } + assign { } { } + assign $0\ics_wb__ack$next[0:0]$15074 $1\ics_wb__ack$next[0:0]$15075 + attribute \src "libresoc.v:203408.5-203408.29" + switch \initial + attribute \src "libresoc.v:203408.9-203408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$15075 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15075 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15074 + end + connect \$7 $ternary$libresoc.v:202778$14828_Y + connect \$99 $lt$libresoc.v:202779$14829_Y + connect \$101 $and$libresoc.v:202780$14830_Y + connect \$103 $lt$libresoc.v:202781$14831_Y + connect \$105 $and$libresoc.v:202782$14832_Y + connect \$107 $lt$libresoc.v:202783$14833_Y + connect \$109 $and$libresoc.v:202784$14834_Y + connect \$111 $lt$libresoc.v:202785$14835_Y + connect \$113 $and$libresoc.v:202786$14836_Y + connect \$115 $lt$libresoc.v:202787$14837_Y + connect \$117 $and$libresoc.v:202788$14838_Y + connect \$119 $lt$libresoc.v:202789$14839_Y + connect \$121 $and$libresoc.v:202790$14840_Y + connect \$123 $lt$libresoc.v:202791$14841_Y + connect \$125 $and$libresoc.v:202792$14842_Y + connect \$127 $lt$libresoc.v:202793$14843_Y + connect \$12 $eq$libresoc.v:202794$14844_Y + connect \$129 $and$libresoc.v:202795$14845_Y + connect \$131 $lt$libresoc.v:202796$14846_Y + connect \$133 $and$libresoc.v:202797$14847_Y + connect \$135 $lt$libresoc.v:202798$14848_Y + connect \$137 $and$libresoc.v:202799$14849_Y + connect \$11 $ternary$libresoc.v:202800$14850_Y + connect \$139 $lt$libresoc.v:202801$14851_Y + connect \$141 $and$libresoc.v:202802$14852_Y + connect \$143 $lt$libresoc.v:202803$14853_Y + connect \$145 $and$libresoc.v:202804$14854_Y + connect \$147 $lt$libresoc.v:202805$14855_Y + connect \$149 $and$libresoc.v:202806$14856_Y + connect \$151 $lt$libresoc.v:202807$14857_Y + connect \$153 $and$libresoc.v:202808$14858_Y + connect \$155 $lt$libresoc.v:202809$14859_Y + connect \$157 $and$libresoc.v:202810$14860_Y + connect \$159 $lt$libresoc.v:202811$14861_Y + connect \$161 $and$libresoc.v:202812$14862_Y + connect \$163 $lt$libresoc.v:202813$14863_Y + connect \$165 $and$libresoc.v:202814$14864_Y + connect \$167 $lt$libresoc.v:202815$14865_Y + connect \$16 $eq$libresoc.v:202816$14866_Y + connect \$169 $and$libresoc.v:202817$14867_Y + connect \$171 $lt$libresoc.v:202818$14868_Y + connect \$173 $and$libresoc.v:202819$14869_Y + connect \$175 $lt$libresoc.v:202820$14870_Y + connect \$177 $and$libresoc.v:202821$14871_Y + connect \$15 $ternary$libresoc.v:202822$14872_Y + connect \$179 $lt$libresoc.v:202823$14873_Y + connect \$181 $and$libresoc.v:202824$14874_Y + connect \$183 $lt$libresoc.v:202825$14875_Y + connect \$185 $and$libresoc.v:202826$14876_Y + connect \$187 $lt$libresoc.v:202827$14877_Y + connect \$189 $and$libresoc.v:202828$14878_Y + connect \$191 $lt$libresoc.v:202829$14879_Y + connect \$193 $and$libresoc.v:202830$14880_Y + connect \$195 $lt$libresoc.v:202831$14881_Y + connect \$197 $and$libresoc.v:202832$14882_Y + connect \$1 $eq$libresoc.v:202833$14883_Y + connect \$199 $lt$libresoc.v:202834$14884_Y + connect \$201 $and$libresoc.v:202835$14885_Y + connect \$204 $eq$libresoc.v:202836$14886_Y + connect \$203 $ternary$libresoc.v:202837$14887_Y + connect \$20 $eq$libresoc.v:202838$14888_Y + connect \$19 $ternary$libresoc.v:202839$14889_Y + connect \$24 $eq$libresoc.v:202840$14890_Y + connect \$23 $ternary$libresoc.v:202841$14891_Y + connect \$28 $eq$libresoc.v:202842$14892_Y + connect \$27 $ternary$libresoc.v:202843$14893_Y + connect \$32 $eq$libresoc.v:202844$14894_Y + connect \$31 $ternary$libresoc.v:202845$14895_Y + connect \$36 $eq$libresoc.v:202846$14896_Y + connect \$35 $ternary$libresoc.v:202847$14897_Y + connect \$3 $eq$libresoc.v:202848$14898_Y + connect \$40 $eq$libresoc.v:202849$14899_Y + connect \$39 $ternary$libresoc.v:202850$14900_Y + connect \$44 $eq$libresoc.v:202851$14901_Y + connect \$43 $ternary$libresoc.v:202852$14902_Y + connect \$48 $eq$libresoc.v:202853$14903_Y + connect \$47 $ternary$libresoc.v:202854$14904_Y + connect \$52 $eq$libresoc.v:202855$14905_Y + connect \$51 $ternary$libresoc.v:202856$14906_Y + connect \$56 $eq$libresoc.v:202857$14907_Y + connect \$55 $ternary$libresoc.v:202858$14908_Y + connect \$5 $and$libresoc.v:202859$14909_Y + connect \$60 $eq$libresoc.v:202860$14910_Y + connect \$59 $ternary$libresoc.v:202861$14911_Y + connect \$64 $eq$libresoc.v:202862$14912_Y + connect \$63 $ternary$libresoc.v:202863$14913_Y + connect \$68 $eq$libresoc.v:202864$14914_Y + connect \$67 $ternary$libresoc.v:202865$14915_Y + connect \$71 $shr$libresoc.v:202866$14916_Y [0] + connect \$73 $and$libresoc.v:202867$14917_Y + connect \$75 $lt$libresoc.v:202868$14918_Y + connect \$77 $and$libresoc.v:202869$14919_Y + connect \$79 $lt$libresoc.v:202870$14920_Y + connect \$81 $and$libresoc.v:202871$14921_Y + connect \$83 $lt$libresoc.v:202872$14922_Y + connect \$85 $and$libresoc.v:202873$14923_Y + connect \$87 $lt$libresoc.v:202874$14924_Y + connect \$8 $eq$libresoc.v:202875$14925_Y + connect \$89 $and$libresoc.v:202876$14926_Y + connect \$91 $lt$libresoc.v:202877$14927_Y + connect \$93 $and$libresoc.v:202878$14928_Y + connect \$95 $lt$libresoc.v:202879$14929_Y + connect \$97 $and$libresoc.v:202880$14930_Y + connect \icp_r_pri \$203 + connect \icp_r_src \cur_idx15 + connect \max_idx 4'0000 + connect \max_pri 8'11111111 + connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } + connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } + connect \wb_valid \$5 + connect \reg_idx \ics_wb__adr [3:0] + connect \reg_is_debug \$3 + connect \reg_is_config \$1 + connect \reg_is_xive \ics_wb__adr [9] +end diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 27d000d..56e2e69 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -239066,293 +239066,293 @@ attribute \src "ls180.v:4.1-11017.10" attribute \cells_not_processed 1 module \ls180 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 + wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 + wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 + wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 + wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 + wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 + wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 + wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 + wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 + wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 + wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 + wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 + wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 + wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 + wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 + wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 + wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 + wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 + wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 + wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 + wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 + wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 + wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 + wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 + wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 + wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 + wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 + wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 + wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 + wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 + wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 + wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 + wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 + wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 + wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 + wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 + wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 + wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 + wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 + wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 + wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 + wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 + wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 + wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 + wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 + wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 + wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 + wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 + wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 + wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 + wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 + wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 + wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 + wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 + wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 + wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 + wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 attribute \src "ls180.v:10493.1-10497.4" - wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 + wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 attribute \src "ls180.v:10493.1-10497.4" - wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 + wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 attribute \src "ls180.v:10493.1-10497.4" - wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 + wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 attribute \src "ls180.v:10507.1-10511.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 + wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 attribute \src "ls180.v:10507.1-10511.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 attribute \src "ls180.v:10507.1-10511.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 attribute \src "ls180.v:10521.1-10525.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 + wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 attribute \src "ls180.v:10521.1-10525.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 attribute \src "ls180.v:10521.1-10525.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 attribute \src "ls180.v:10535.1-10539.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 + wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 attribute \src "ls180.v:10550.1-10554.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 + wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 attribute \src "ls180.v:10567.1-10571.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 + wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 attribute \src "ls180.v:10583.1-10587.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 + wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 attribute \src "ls180.v:10597.1-10601.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 + wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 attribute \src "ls180.v:3402.1-3495.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] attribute \src "ls180.v:7705.1-10349.4" @@ -239831,15 +239831,15 @@ module \ls180 wire $0\main_libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:204.12-204.74" + attribute \src "ls180.v:171.12-171.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:176.5-176.69" + attribute \src "ls180.v:175.5-175.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:181.5-181.72" + attribute \src "ls180.v:201.5-201.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:184.11-184.79" + attribute \src "ls180.v:204.11-204.79" wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:188.12-188.78" + attribute \src "ls180.v:189.12-189.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] @@ -243078,95 +243078,95 @@ module \ls180 attribute \src "ls180.v:5758.77-5758.111" wire width 32 $add$ls180.v:5758$1161_Y attribute \src "ls180.v:7765.36-7765.70" - wire width 32 $add$ls180.v:7765$2602_Y + wire width 32 $add$ls180.v:7765$2604_Y attribute \src "ls180.v:7866.37-7866.72" - wire width 4 $add$ls180.v:7866$2635_Y + wire width 4 $add$ls180.v:7866$2637_Y attribute \src "ls180.v:7883.60-7883.119" - wire width 3 $add$ls180.v:7883$2639_Y + wire width 3 $add$ls180.v:7883$2641_Y attribute \src "ls180.v:7886.60-7886.119" - wire width 3 $add$ls180.v:7886$2640_Y + wire width 3 $add$ls180.v:7886$2642_Y attribute \src "ls180.v:7890.59-7890.116" - wire width 4 $add$ls180.v:7890$2645_Y + wire width 4 $add$ls180.v:7890$2647_Y attribute \src "ls180.v:7929.60-7929.119" - wire width 3 $add$ls180.v:7929$2655_Y + wire width 3 $add$ls180.v:7929$2657_Y attribute \src "ls180.v:7932.60-7932.119" - wire width 3 $add$ls180.v:7932$2656_Y + wire width 3 $add$ls180.v:7932$2658_Y attribute \src "ls180.v:7936.59-7936.116" - wire width 4 $add$ls180.v:7936$2661_Y + wire width 4 $add$ls180.v:7936$2663_Y attribute \src "ls180.v:7975.60-7975.119" - wire width 3 $add$ls180.v:7975$2671_Y + wire width 3 $add$ls180.v:7975$2673_Y attribute \src "ls180.v:7978.60-7978.119" - wire width 3 $add$ls180.v:7978$2672_Y + wire width 3 $add$ls180.v:7978$2674_Y attribute \src "ls180.v:7982.59-7982.116" - wire width 4 $add$ls180.v:7982$2677_Y + wire width 4 $add$ls180.v:7982$2679_Y attribute \src "ls180.v:8021.60-8021.119" - wire width 3 $add$ls180.v:8021$2687_Y + wire width 3 $add$ls180.v:8021$2689_Y attribute \src "ls180.v:8024.60-8024.119" - wire width 3 $add$ls180.v:8024$2688_Y + wire width 3 $add$ls180.v:8024$2690_Y attribute \src "ls180.v:8028.59-8028.116" - wire width 4 $add$ls180.v:8028$2693_Y + wire width 4 $add$ls180.v:8028$2695_Y attribute \src "ls180.v:8258.34-8258.66" - wire width 4 $add$ls180.v:8258$2747_Y + wire width 4 $add$ls180.v:8258$2749_Y attribute \src "ls180.v:8274.73-8274.131" - wire width 33 $add$ls180.v:8274$2750_Y + wire width 33 $add$ls180.v:8274$2752_Y attribute \src "ls180.v:8287.34-8287.66" - wire width 4 $add$ls180.v:8287$2754_Y + wire width 4 $add$ls180.v:8287$2756_Y attribute \src "ls180.v:8306.73-8306.131" - wire width 33 $add$ls180.v:8306$2757_Y + wire width 33 $add$ls180.v:8306$2759_Y attribute \src "ls180.v:8332.33-8332.65" - wire width 4 $add$ls180.v:8332$2765_Y + wire width 4 $add$ls180.v:8332$2767_Y attribute \src "ls180.v:8335.33-8335.65" - wire width 4 $add$ls180.v:8335$2766_Y + wire width 4 $add$ls180.v:8335$2768_Y attribute \src "ls180.v:8339.33-8339.64" - wire width 5 $add$ls180.v:8339$2771_Y + wire width 5 $add$ls180.v:8339$2773_Y attribute \src "ls180.v:8354.33-8354.65" - wire width 4 $add$ls180.v:8354$2776_Y + wire width 4 $add$ls180.v:8354$2778_Y attribute \src "ls180.v:8357.33-8357.65" - wire width 4 $add$ls180.v:8357$2777_Y + wire width 4 $add$ls180.v:8357$2779_Y attribute \src "ls180.v:8361.33-8361.64" - wire width 5 $add$ls180.v:8361$2782_Y + wire width 5 $add$ls180.v:8361$2784_Y attribute \src "ls180.v:8382.35-8382.70" - wire width 16 $add$ls180.v:8382$2784_Y + wire width 16 $add$ls180.v:8382$2786_Y attribute \src "ls180.v:8417.34-8417.68" - wire width 16 $add$ls180.v:8417$2789_Y + wire width 16 $add$ls180.v:8417$2791_Y attribute \src "ls180.v:8453.25-8453.49" - wire width 32 $add$ls180.v:8453$2794_Y + wire width 32 $add$ls180.v:8453$2796_Y attribute \src "ls180.v:8467.25-8467.49" - wire width 32 $add$ls180.v:8467$2798_Y + wire width 32 $add$ls180.v:8467$2800_Y attribute \src "ls180.v:8481.31-8481.61" - wire width 9 $add$ls180.v:8481$2803_Y + wire width 9 $add$ls180.v:8481$2805_Y attribute \src "ls180.v:8504.45-8504.88" - wire width 3 $add$ls180.v:8504$2807_Y + wire width 3 $add$ls180.v:8504$2809_Y attribute \src "ls180.v:8550.71-8550.114" - wire width 4 $add$ls180.v:8550$2813_Y + wire width 4 $add$ls180.v:8550$2815_Y attribute \src "ls180.v:8585.46-8585.90" - wire width 3 $add$ls180.v:8585$2819_Y + wire width 3 $add$ls180.v:8585$2821_Y attribute \src "ls180.v:8631.72-8631.116" - wire width 4 $add$ls180.v:8631$2825_Y + wire width 4 $add$ls180.v:8631$2827_Y attribute \src "ls180.v:8664.47-8664.92" - wire $add$ls180.v:8664$2831_Y + wire $add$ls180.v:8664$2833_Y attribute \src "ls180.v:8692.73-8692.118" - wire width 2 $add$ls180.v:8692$2837_Y + wire width 2 $add$ls180.v:8692$2839_Y attribute \src "ls180.v:8804.39-8804.75" - wire width 4 $add$ls180.v:8804$2850_Y + wire width 4 $add$ls180.v:8804$2852_Y attribute \src "ls180.v:8865.37-8865.73" - wire width 5 $add$ls180.v:8865$2854_Y + wire width 5 $add$ls180.v:8865$2856_Y attribute \src "ls180.v:8868.37-8868.73" - wire width 5 $add$ls180.v:8868$2855_Y + wire width 5 $add$ls180.v:8868$2857_Y attribute \src "ls180.v:8872.36-8872.70" - wire width 6 $add$ls180.v:8872$2860_Y + wire width 6 $add$ls180.v:8872$2862_Y attribute \src "ls180.v:8887.41-8887.80" - wire width 3 $add$ls180.v:8887$2864_Y + wire width 3 $add$ls180.v:8887$2866_Y attribute \src "ls180.v:8933.67-8933.106" - wire width 4 $add$ls180.v:8933$2870_Y + wire width 4 $add$ls180.v:8933$2872_Y attribute \src "ls180.v:8959.39-8959.76" - wire width 3 $add$ls180.v:8959$2872_Y + wire width 3 $add$ls180.v:8959$2874_Y attribute \src "ls180.v:8963.37-8963.73" - wire width 5 $add$ls180.v:8963$2876_Y + wire width 5 $add$ls180.v:8963$2878_Y attribute \src "ls180.v:8966.37-8966.73" - wire width 5 $add$ls180.v:8966$2877_Y + wire width 5 $add$ls180.v:8966$2879_Y attribute \src "ls180.v:8970.36-8970.70" - wire width 6 $add$ls180.v:8970$2882_Y + wire width 6 $add$ls180.v:8970$2884_Y attribute \src "ls180.v:2929.9-2929.90" wire $and$ls180.v:2929$53_Y attribute \src "ls180.v:2947.9-2947.90" @@ -245427,174 +245427,178 @@ module \ls180 wire $and$ls180.v:7468$2563_Y attribute \src "ls180.v:7468.38-7468.117" wire $and$ls180.v:7468$2564_Y + attribute \src "ls180.v:7687.18-7687.68" + wire $and$ls180.v:7687$2571_Y + attribute \src "ls180.v:7688.18-7688.68" + wire $and$ls180.v:7688$2572_Y attribute \src "ls180.v:7690.17-7690.67" - wire $and$ls180.v:7690$2572_Y + wire $and$ls180.v:7690$2574_Y attribute \src "ls180.v:7769.8-7769.67" - wire $and$ls180.v:7769$2603_Y - attribute \src "ls180.v:7769.7-7769.102" wire $and$ls180.v:7769$2605_Y + attribute \src "ls180.v:7769.7-7769.102" + wire $and$ls180.v:7769$2607_Y attribute \src "ls180.v:7788.7-7788.75" - wire $and$ls180.v:7788$2609_Y + wire $and$ls180.v:7788$2611_Y attribute \src "ls180.v:7792.8-7792.65" - wire $and$ls180.v:7792$2610_Y - attribute \src "ls180.v:7792.7-7792.99" wire $and$ls180.v:7792$2612_Y + attribute \src "ls180.v:7792.7-7792.99" + wire $and$ls180.v:7792$2614_Y attribute \src "ls180.v:7796.8-7796.65" - wire $and$ls180.v:7796$2613_Y - attribute \src "ls180.v:7796.7-7796.99" wire $and$ls180.v:7796$2615_Y + attribute \src "ls180.v:7796.7-7796.99" + wire $and$ls180.v:7796$2617_Y attribute \src "ls180.v:7800.8-7800.65" - wire $and$ls180.v:7800$2616_Y - attribute \src "ls180.v:7800.7-7800.99" wire $and$ls180.v:7800$2618_Y + attribute \src "ls180.v:7800.7-7800.99" + wire $and$ls180.v:7800$2620_Y attribute \src "ls180.v:7804.8-7804.65" - wire $and$ls180.v:7804$2619_Y - attribute \src "ls180.v:7804.7-7804.99" wire $and$ls180.v:7804$2621_Y + attribute \src "ls180.v:7804.7-7804.99" + wire $and$ls180.v:7804$2623_Y attribute \src "ls180.v:7812.7-7812.56" - wire $and$ls180.v:7812$2623_Y + wire $and$ls180.v:7812$2625_Y attribute \src "ls180.v:7840.7-7840.75" - wire $and$ls180.v:7840$2630_Y + wire $and$ls180.v:7840$2632_Y attribute \src "ls180.v:7882.8-7882.131" - wire $and$ls180.v:7882$2636_Y - attribute \src "ls180.v:7882.7-7882.190" wire $and$ls180.v:7882$2638_Y + attribute \src "ls180.v:7882.7-7882.190" + wire $and$ls180.v:7882$2640_Y attribute \src "ls180.v:7888.8-7888.131" - wire $and$ls180.v:7888$2641_Y - attribute \src "ls180.v:7888.7-7888.190" wire $and$ls180.v:7888$2643_Y + attribute \src "ls180.v:7888.7-7888.190" + wire $and$ls180.v:7888$2645_Y attribute \src "ls180.v:7928.8-7928.131" - wire $and$ls180.v:7928$2652_Y - attribute \src "ls180.v:7928.7-7928.190" wire $and$ls180.v:7928$2654_Y + attribute \src "ls180.v:7928.7-7928.190" + wire $and$ls180.v:7928$2656_Y attribute \src "ls180.v:7934.8-7934.131" - wire $and$ls180.v:7934$2657_Y - attribute \src "ls180.v:7934.7-7934.190" wire $and$ls180.v:7934$2659_Y + attribute \src "ls180.v:7934.7-7934.190" + wire $and$ls180.v:7934$2661_Y attribute \src "ls180.v:7974.8-7974.131" - wire $and$ls180.v:7974$2668_Y - attribute \src "ls180.v:7974.7-7974.190" wire $and$ls180.v:7974$2670_Y + attribute \src "ls180.v:7974.7-7974.190" + wire $and$ls180.v:7974$2672_Y attribute \src "ls180.v:7980.8-7980.131" - wire $and$ls180.v:7980$2673_Y - attribute \src "ls180.v:7980.7-7980.190" wire $and$ls180.v:7980$2675_Y + attribute \src "ls180.v:7980.7-7980.190" + wire $and$ls180.v:7980$2677_Y attribute \src "ls180.v:8020.8-8020.131" - wire $and$ls180.v:8020$2684_Y - attribute \src "ls180.v:8020.7-8020.190" wire $and$ls180.v:8020$2686_Y + attribute \src "ls180.v:8020.7-8020.190" + wire $and$ls180.v:8020$2688_Y attribute \src "ls180.v:8026.8-8026.131" - wire $and$ls180.v:8026$2689_Y - attribute \src "ls180.v:8026.7-8026.190" wire $and$ls180.v:8026$2691_Y + attribute \src "ls180.v:8026.7-8026.190" + wire $and$ls180.v:8026$2693_Y attribute \src "ls180.v:8223.48-8223.124" - wire $and$ls180.v:8223$2716_Y + wire $and$ls180.v:8223$2718_Y attribute \src "ls180.v:8223.130-8223.206" - wire $and$ls180.v:8223$2719_Y + wire $and$ls180.v:8223$2721_Y attribute \src "ls180.v:8223.212-8223.288" - wire $and$ls180.v:8223$2722_Y + wire $and$ls180.v:8223$2724_Y attribute \src "ls180.v:8223.294-8223.370" - wire $and$ls180.v:8223$2725_Y + wire $and$ls180.v:8223$2727_Y attribute \src "ls180.v:8224.49-8224.125" - wire $and$ls180.v:8224$2728_Y + wire $and$ls180.v:8224$2730_Y attribute \src "ls180.v:8224.131-8224.207" - wire $and$ls180.v:8224$2731_Y + wire $and$ls180.v:8224$2733_Y attribute \src "ls180.v:8224.213-8224.289" - wire $and$ls180.v:8224$2734_Y + wire $and$ls180.v:8224$2736_Y attribute \src "ls180.v:8224.295-8224.371" - wire $and$ls180.v:8224$2737_Y + wire $and$ls180.v:8224$2739_Y attribute \src "ls180.v:8243.8-8243.49" - wire $and$ls180.v:8243$2740_Y + wire $and$ls180.v:8243$2742_Y attribute \src "ls180.v:8246.8-8246.53" - wire $and$ls180.v:8246$2741_Y + wire $and$ls180.v:8246$2743_Y attribute \src "ls180.v:8251.8-8251.59" - wire $and$ls180.v:8251$2743_Y - attribute \src "ls180.v:8251.7-8251.90" wire $and$ls180.v:8251$2745_Y + attribute \src "ls180.v:8251.7-8251.90" + wire $and$ls180.v:8251$2747_Y attribute \src "ls180.v:8257.8-8257.59" - wire $and$ls180.v:8257$2746_Y + wire $and$ls180.v:8257$2748_Y attribute \src "ls180.v:8281.8-8281.48" - wire $and$ls180.v:8281$2753_Y + wire $and$ls180.v:8281$2755_Y attribute \src "ls180.v:8314.7-8314.57" - wire $and$ls180.v:8314$2759_Y + wire $and$ls180.v:8314$2761_Y attribute \src "ls180.v:8321.7-8321.57" - wire $and$ls180.v:8321$2761_Y + wire $and$ls180.v:8321$2763_Y attribute \src "ls180.v:8331.8-8331.75" - wire $and$ls180.v:8331$2762_Y - attribute \src "ls180.v:8331.7-8331.107" wire $and$ls180.v:8331$2764_Y + attribute \src "ls180.v:8331.7-8331.107" + wire $and$ls180.v:8331$2766_Y attribute \src "ls180.v:8337.8-8337.75" - wire $and$ls180.v:8337$2767_Y - attribute \src "ls180.v:8337.7-8337.107" wire $and$ls180.v:8337$2769_Y + attribute \src "ls180.v:8337.7-8337.107" + wire $and$ls180.v:8337$2771_Y attribute \src "ls180.v:8353.8-8353.75" - wire $and$ls180.v:8353$2773_Y - attribute \src "ls180.v:8353.7-8353.107" wire $and$ls180.v:8353$2775_Y + attribute \src "ls180.v:8353.7-8353.107" + wire $and$ls180.v:8353$2777_Y attribute \src "ls180.v:8359.8-8359.75" - wire $and$ls180.v:8359$2778_Y - attribute \src "ls180.v:8359.7-8359.107" wire $and$ls180.v:8359$2780_Y + attribute \src "ls180.v:8359.7-8359.107" + wire $and$ls180.v:8359$2782_Y attribute \src "ls180.v:8507.7-8507.96" - wire $and$ls180.v:8507$2808_Y + wire $and$ls180.v:8507$2810_Y attribute \src "ls180.v:8508.8-8508.93" - wire $and$ls180.v:8508$2809_Y + wire $and$ls180.v:8508$2811_Y attribute \src "ls180.v:8516.8-8516.93" - wire $and$ls180.v:8516$2810_Y + wire $and$ls180.v:8516$2812_Y attribute \src "ls180.v:8588.7-8588.98" - wire $and$ls180.v:8588$2820_Y + wire $and$ls180.v:8588$2822_Y attribute \src "ls180.v:8589.8-8589.95" - wire $and$ls180.v:8589$2821_Y + wire $and$ls180.v:8589$2823_Y attribute \src "ls180.v:8597.8-8597.95" - wire $and$ls180.v:8597$2822_Y + wire $and$ls180.v:8597$2824_Y attribute \src "ls180.v:8667.7-8667.100" - wire $and$ls180.v:8667$2832_Y + wire $and$ls180.v:8667$2834_Y attribute \src "ls180.v:8668.8-8668.97" - wire $and$ls180.v:8668$2833_Y + wire $and$ls180.v:8668$2835_Y attribute \src "ls180.v:8676.8-8676.97" - wire $and$ls180.v:8676$2834_Y + wire $and$ls180.v:8676$2836_Y attribute \src "ls180.v:8767.7-8767.82" - wire $and$ls180.v:8767$2840_Y + wire $and$ls180.v:8767$2842_Y attribute \src "ls180.v:8770.7-8770.82" - wire $and$ls180.v:8770$2841_Y + wire $and$ls180.v:8770$2843_Y attribute \src "ls180.v:8773.7-8773.82" - wire $and$ls180.v:8773$2842_Y + wire $and$ls180.v:8773$2844_Y attribute \src "ls180.v:8776.7-8776.82" - wire $and$ls180.v:8776$2843_Y + wire $and$ls180.v:8776$2845_Y attribute \src "ls180.v:8779.7-8779.82" - wire $and$ls180.v:8779$2844_Y + wire $and$ls180.v:8779$2846_Y attribute \src "ls180.v:8784.7-8784.82" - wire $and$ls180.v:8784$2845_Y + wire $and$ls180.v:8784$2847_Y attribute \src "ls180.v:8789.7-8789.82" - wire $and$ls180.v:8789$2846_Y + wire $and$ls180.v:8789$2848_Y attribute \src "ls180.v:8794.7-8794.82" - wire $and$ls180.v:8794$2847_Y + wire $and$ls180.v:8794$2849_Y attribute \src "ls180.v:8799.7-8799.82" - wire $and$ls180.v:8799$2848_Y + wire $and$ls180.v:8799$2850_Y attribute \src "ls180.v:8864.8-8864.83" - wire $and$ls180.v:8864$2851_Y - attribute \src "ls180.v:8864.7-8864.119" wire $and$ls180.v:8864$2853_Y + attribute \src "ls180.v:8864.7-8864.119" + wire $and$ls180.v:8864$2855_Y attribute \src "ls180.v:8870.8-8870.83" - wire $and$ls180.v:8870$2856_Y - attribute \src "ls180.v:8870.7-8870.119" wire $and$ls180.v:8870$2858_Y + attribute \src "ls180.v:8870.7-8870.119" + wire $and$ls180.v:8870$2860_Y attribute \src "ls180.v:8890.7-8890.88" - wire $and$ls180.v:8890$2865_Y + wire $and$ls180.v:8890$2867_Y attribute \src "ls180.v:8891.8-8891.85" - wire $and$ls180.v:8891$2866_Y + wire $and$ls180.v:8891$2868_Y attribute \src "ls180.v:8899.8-8899.85" - wire $and$ls180.v:8899$2867_Y + wire $and$ls180.v:8899$2869_Y attribute \src "ls180.v:8955.7-8955.88" - wire $and$ls180.v:8955$2871_Y + wire $and$ls180.v:8955$2873_Y attribute \src "ls180.v:8962.8-8962.83" - wire $and$ls180.v:8962$2873_Y - attribute \src "ls180.v:8962.7-8962.119" wire $and$ls180.v:8962$2875_Y + attribute \src "ls180.v:8962.7-8962.119" + wire $and$ls180.v:8962$2877_Y attribute \src "ls180.v:8968.8-8968.83" - wire $and$ls180.v:8968$2878_Y - attribute \src "ls180.v:8968.7-8968.119" wire $and$ls180.v:8968$2880_Y + attribute \src "ls180.v:8968.7-8968.119" + wire $and$ls180.v:8968$2882_Y attribute \src "ls180.v:2930.30-2930.76" wire $eq$ls180.v:2930$54_Y attribute \src "ls180.v:2937.11-2937.42" @@ -246608,115 +246612,115 @@ module \ls180 attribute \src "ls180.v:7189.294-7189.327" wire $eq$ls180.v:7189$2514_Y attribute \src "ls180.v:7773.8-7773.38" - wire $eq$ls180.v:7773$2606_Y + wire $eq$ls180.v:7773$2608_Y attribute \src "ls180.v:7820.8-7820.42" - wire $eq$ls180.v:7820$2626_Y + wire $eq$ls180.v:7820$2628_Y attribute \src "ls180.v:7840.38-7840.74" - wire $eq$ls180.v:7840$2629_Y + wire $eq$ls180.v:7840$2631_Y attribute \src "ls180.v:7847.7-7847.43" - wire $eq$ls180.v:7847$2631_Y + wire $eq$ls180.v:7847$2633_Y attribute \src "ls180.v:7854.7-7854.43" - wire $eq$ls180.v:7854$2632_Y + wire $eq$ls180.v:7854$2634_Y attribute \src "ls180.v:7862.7-7862.43" - wire $eq$ls180.v:7862$2633_Y + wire $eq$ls180.v:7862$2635_Y attribute \src "ls180.v:7914.9-7914.54" - wire $eq$ls180.v:7914$2651_Y + wire $eq$ls180.v:7914$2653_Y attribute \src "ls180.v:7960.9-7960.54" - wire $eq$ls180.v:7960$2667_Y + wire $eq$ls180.v:7960$2669_Y attribute \src "ls180.v:8006.9-8006.54" - wire $eq$ls180.v:8006$2683_Y + wire $eq$ls180.v:8006$2685_Y attribute \src "ls180.v:8052.9-8052.54" - wire $eq$ls180.v:8052$2699_Y + wire $eq$ls180.v:8052$2701_Y attribute \src "ls180.v:8202.9-8202.41" - wire $eq$ls180.v:8202$2711_Y + wire $eq$ls180.v:8202$2713_Y attribute \src "ls180.v:8217.9-8217.41" - wire $eq$ls180.v:8217$2714_Y + wire $eq$ls180.v:8217$2716_Y attribute \src "ls180.v:8223.49-8223.82" - wire $eq$ls180.v:8223$2715_Y + wire $eq$ls180.v:8223$2717_Y attribute \src "ls180.v:8223.131-8223.164" - wire $eq$ls180.v:8223$2718_Y + wire $eq$ls180.v:8223$2720_Y attribute \src "ls180.v:8223.213-8223.246" - wire $eq$ls180.v:8223$2721_Y + wire $eq$ls180.v:8223$2723_Y attribute \src "ls180.v:8223.295-8223.328" - wire $eq$ls180.v:8223$2724_Y + wire $eq$ls180.v:8223$2726_Y attribute \src "ls180.v:8224.50-8224.83" - wire $eq$ls180.v:8224$2727_Y + wire $eq$ls180.v:8224$2729_Y attribute \src "ls180.v:8224.132-8224.165" - wire $eq$ls180.v:8224$2730_Y + wire $eq$ls180.v:8224$2732_Y attribute \src "ls180.v:8224.214-8224.247" - wire $eq$ls180.v:8224$2733_Y + wire $eq$ls180.v:8224$2735_Y attribute \src "ls180.v:8224.296-8224.329" - wire $eq$ls180.v:8224$2736_Y + wire $eq$ls180.v:8224$2738_Y attribute \src "ls180.v:8259.9-8259.42" - wire $eq$ls180.v:8259$2748_Y + wire $eq$ls180.v:8259$2750_Y attribute \src "ls180.v:8262.10-8262.43" - wire $eq$ls180.v:8262$2749_Y + wire $eq$ls180.v:8262$2751_Y attribute \src "ls180.v:8288.9-8288.42" - wire $eq$ls180.v:8288$2755_Y + wire $eq$ls180.v:8288$2757_Y attribute \src "ls180.v:8293.10-8293.43" - wire $eq$ls180.v:8293$2756_Y + wire $eq$ls180.v:8293$2758_Y attribute \src "ls180.v:8500.9-8500.53" - wire $eq$ls180.v:8500$2805_Y + wire $eq$ls180.v:8500$2807_Y attribute \src "ls180.v:8581.9-8581.54" - wire $eq$ls180.v:8581$2817_Y + wire $eq$ls180.v:8581$2819_Y attribute \src "ls180.v:8660.9-8660.55" - wire $eq$ls180.v:8660$2829_Y + wire $eq$ls180.v:8660$2831_Y attribute \src "ls180.v:8883.9-8883.49" - wire $eq$ls180.v:8883$2862_Y + wire $eq$ls180.v:8883$2864_Y attribute \src "ls180.v:8459.8-8459.54" - wire $ge$ls180.v:8459$2797_Y + wire $ge$ls180.v:8459$2799_Y attribute \src "ls180.v:8473.8-8473.54" - wire $ge$ls180.v:8473$2801_Y + wire $ge$ls180.v:8473$2803_Y attribute \src "ls180.v:5342.47-5342.83" wire $gt$ls180.v:5342$1064_Y attribute \src "ls180.v:5348.7-5348.43" wire $lt$ls180.v:5348$1067_Y attribute \src "ls180.v:8454.8-8454.43" - wire $lt$ls180.v:8454$2795_Y + wire $lt$ls180.v:8454$2797_Y attribute \src "ls180.v:8468.8-8468.43" - wire $lt$ls180.v:8468$2799_Y + wire $lt$ls180.v:8468$2801_Y attribute \src "ls180.v:10373.33-10373.36" - wire width 64 $memrd$\mem$ls180.v:10373$2916_DATA + wire width 64 $memrd$\mem$ls180.v:10373$2918_DATA attribute \src "ls180.v:10401.27-10401.32" - wire width 64 $memrd$\mem_1$ls180.v:10401$2942_DATA + wire width 64 $memrd$\mem_1$ls180.v:10401$2944_DATA attribute \src "ls180.v:10429.27-10429.32" - wire width 64 $memrd$\mem_2$ls180.v:10429$2968_DATA + wire width 64 $memrd$\mem_2$ls180.v:10429$2970_DATA attribute \src "ls180.v:10457.27-10457.32" - wire width 64 $memrd$\mem_3$ls180.v:10457$2994_DATA + wire width 64 $memrd$\mem_3$ls180.v:10457$2996_DATA attribute \src "ls180.v:10485.27-10485.32" - wire width 64 $memrd$\mem_4$ls180.v:10485$3020_DATA + wire width 64 $memrd$\mem_4$ls180.v:10485$3022_DATA attribute \src "ls180.v:10496.12-10496.19" - wire width 25 $memrd$\storage$ls180.v:10496$3025_DATA + wire width 25 $memrd$\storage$ls180.v:10496$3027_DATA attribute \src "ls180.v:10503.68-10503.75" - wire width 25 $memrd$\storage$ls180.v:10503$3027_DATA + wire width 25 $memrd$\storage$ls180.v:10503$3029_DATA attribute \src "ls180.v:10510.14-10510.23" - wire width 25 $memrd$\storage_1$ls180.v:10510$3032_DATA + wire width 25 $memrd$\storage_1$ls180.v:10510$3034_DATA attribute \src "ls180.v:10517.68-10517.77" - wire width 25 $memrd$\storage_1$ls180.v:10517$3034_DATA + wire width 25 $memrd$\storage_1$ls180.v:10517$3036_DATA attribute \src "ls180.v:10524.14-10524.23" - wire width 25 $memrd$\storage_2$ls180.v:10524$3039_DATA + wire width 25 $memrd$\storage_2$ls180.v:10524$3041_DATA attribute \src "ls180.v:10531.68-10531.77" - wire width 25 $memrd$\storage_2$ls180.v:10531$3041_DATA + wire width 25 $memrd$\storage_2$ls180.v:10531$3043_DATA attribute \src "ls180.v:10538.14-10538.23" - wire width 25 $memrd$\storage_3$ls180.v:10538$3046_DATA + wire width 25 $memrd$\storage_3$ls180.v:10538$3048_DATA attribute \src "ls180.v:10545.68-10545.77" - wire width 25 $memrd$\storage_3$ls180.v:10545$3048_DATA + wire width 25 $memrd$\storage_3$ls180.v:10545$3050_DATA attribute \src "ls180.v:10553.14-10553.23" - wire width 10 $memrd$\storage_4$ls180.v:10553$3053_DATA + wire width 10 $memrd$\storage_4$ls180.v:10553$3055_DATA attribute \src "ls180.v:10558.15-10558.24" - wire width 10 $memrd$\storage_4$ls180.v:10558$3055_DATA + wire width 10 $memrd$\storage_4$ls180.v:10558$3057_DATA attribute \src "ls180.v:10570.14-10570.23" - wire width 10 $memrd$\storage_5$ls180.v:10570$3060_DATA + wire width 10 $memrd$\storage_5$ls180.v:10570$3062_DATA attribute \src "ls180.v:10575.15-10575.24" - wire width 10 $memrd$\storage_5$ls180.v:10575$3062_DATA + wire width 10 $memrd$\storage_5$ls180.v:10575$3064_DATA attribute \src "ls180.v:10586.14-10586.23" - wire width 10 $memrd$\storage_6$ls180.v:10586$3067_DATA + wire width 10 $memrd$\storage_6$ls180.v:10586$3069_DATA attribute \src "ls180.v:10593.45-10593.54" - wire width 10 $memrd$\storage_6$ls180.v:10593$3069_DATA + wire width 10 $memrd$\storage_6$ls180.v:10593$3071_DATA attribute \src "ls180.v:10600.14-10600.23" - wire width 10 $memrd$\storage_7$ls180.v:10600$3074_DATA + wire width 10 $memrd$\storage_7$ls180.v:10600$3076_DATA attribute \src "ls180.v:10607.45-10607.54" - wire width 10 $memrd$\storage_7$ls180.v:10607$3076_DATA + wire width 10 $memrd$\storage_7$ls180.v:10607$3078_DATA attribute \src "ls180.v:0.0-0.0" wire width 6 $memwr$\mem$ls180.v:10355$1_ADDR attribute \src "ls180.v:0.0-0.0" @@ -247056,13 +247060,13 @@ module \ls180 attribute \src "ls180.v:5878.79-5878.119" wire $ne$ls180.v:5878$1177_Y attribute \src "ls180.v:7763.7-7763.52" - wire $ne$ls180.v:7763$2601_Y + wire $ne$ls180.v:7763$2603_Y attribute \src "ls180.v:7829.9-7829.43" - wire $ne$ls180.v:7829$2627_Y + wire $ne$ls180.v:7829$2629_Y attribute \src "ls180.v:7865.8-7865.44" - wire $ne$ls180.v:7865$2634_Y + wire $ne$ls180.v:7865$2636_Y attribute \src "ls180.v:8803.9-8803.47" - wire $ne$ls180.v:8803$2849_Y + wire $ne$ls180.v:8803$2851_Y attribute \src "ls180.v:2893.33-2893.73" wire $not$ls180.v:2893$50_Y attribute \src "ls180.v:2932.48-2932.69" @@ -247608,145 +247612,145 @@ module \ls180 attribute \src "ls180.v:7189.86-7189.330" wire $not$ls180.v:7189$2517_Y attribute \src "ls180.v:7690.18-7690.42" - wire $not$ls180.v:7690$2571_Y + wire $not$ls180.v:7690$2573_Y attribute \src "ls180.v:7769.72-7769.101" - wire $not$ls180.v:7769$2604_Y + wire $not$ls180.v:7769$2606_Y attribute \src "ls180.v:7788.8-7788.38" - wire $not$ls180.v:7788$2608_Y + wire $not$ls180.v:7788$2610_Y attribute \src "ls180.v:7792.70-7792.98" - wire $not$ls180.v:7792$2611_Y + wire $not$ls180.v:7792$2613_Y attribute \src "ls180.v:7796.70-7796.98" - wire $not$ls180.v:7796$2614_Y + wire $not$ls180.v:7796$2616_Y attribute \src "ls180.v:7800.70-7800.98" - wire $not$ls180.v:7800$2617_Y + wire $not$ls180.v:7800$2619_Y attribute \src "ls180.v:7804.70-7804.98" - wire $not$ls180.v:7804$2620_Y + wire $not$ls180.v:7804$2622_Y attribute \src "ls180.v:7812.32-7812.55" - wire $not$ls180.v:7812$2622_Y + wire $not$ls180.v:7812$2624_Y attribute \src "ls180.v:7882.136-7882.189" - wire $not$ls180.v:7882$2637_Y + wire $not$ls180.v:7882$2639_Y attribute \src "ls180.v:7888.136-7888.189" - wire $not$ls180.v:7888$2642_Y + wire $not$ls180.v:7888$2644_Y attribute \src "ls180.v:7889.8-7889.61" - wire $not$ls180.v:7889$2644_Y + wire $not$ls180.v:7889$2646_Y attribute \src "ls180.v:7897.8-7897.56" - wire $not$ls180.v:7897$2647_Y + wire $not$ls180.v:7897$2649_Y attribute \src "ls180.v:7912.8-7912.46" - wire $not$ls180.v:7912$2649_Y + wire $not$ls180.v:7912$2651_Y attribute \src "ls180.v:7928.136-7928.189" - wire $not$ls180.v:7928$2653_Y + wire $not$ls180.v:7928$2655_Y attribute \src "ls180.v:7934.136-7934.189" - wire $not$ls180.v:7934$2658_Y + wire $not$ls180.v:7934$2660_Y attribute \src "ls180.v:7935.8-7935.61" - wire $not$ls180.v:7935$2660_Y + wire $not$ls180.v:7935$2662_Y attribute \src "ls180.v:7943.8-7943.56" - wire $not$ls180.v:7943$2663_Y + wire $not$ls180.v:7943$2665_Y attribute \src "ls180.v:7958.8-7958.46" - wire $not$ls180.v:7958$2665_Y + wire $not$ls180.v:7958$2667_Y attribute \src "ls180.v:7974.136-7974.189" - wire $not$ls180.v:7974$2669_Y + wire $not$ls180.v:7974$2671_Y attribute \src "ls180.v:7980.136-7980.189" - wire $not$ls180.v:7980$2674_Y + wire $not$ls180.v:7980$2676_Y attribute \src "ls180.v:7981.8-7981.61" - wire $not$ls180.v:7981$2676_Y + wire $not$ls180.v:7981$2678_Y attribute \src "ls180.v:7989.8-7989.56" - wire $not$ls180.v:7989$2679_Y + wire $not$ls180.v:7989$2681_Y attribute \src "ls180.v:8004.8-8004.46" - wire $not$ls180.v:8004$2681_Y + wire $not$ls180.v:8004$2683_Y attribute \src "ls180.v:8020.136-8020.189" - wire $not$ls180.v:8020$2685_Y + wire $not$ls180.v:8020$2687_Y attribute \src "ls180.v:8026.136-8026.189" - wire $not$ls180.v:8026$2690_Y + wire $not$ls180.v:8026$2692_Y attribute \src "ls180.v:8027.8-8027.61" - wire $not$ls180.v:8027$2692_Y + wire $not$ls180.v:8027$2694_Y attribute \src "ls180.v:8035.8-8035.56" - wire $not$ls180.v:8035$2695_Y + wire $not$ls180.v:8035$2697_Y attribute \src "ls180.v:8050.8-8050.46" - wire $not$ls180.v:8050$2697_Y + wire $not$ls180.v:8050$2699_Y attribute \src "ls180.v:8058.7-8058.22" - wire $not$ls180.v:8058$2700_Y + wire $not$ls180.v:8058$2702_Y attribute \src "ls180.v:8061.8-8061.29" - wire $not$ls180.v:8061$2701_Y + wire $not$ls180.v:8061$2703_Y attribute \src "ls180.v:8065.7-8065.22" - wire $not$ls180.v:8065$2703_Y + wire $not$ls180.v:8065$2705_Y attribute \src "ls180.v:8068.8-8068.29" - wire $not$ls180.v:8068$2704_Y + wire $not$ls180.v:8068$2706_Y attribute \src "ls180.v:8187.30-8187.60" - wire $not$ls180.v:8187$2706_Y + wire $not$ls180.v:8187$2708_Y attribute \src "ls180.v:8188.30-8188.60" - wire $not$ls180.v:8188$2707_Y + wire $not$ls180.v:8188$2709_Y attribute \src "ls180.v:8189.29-8189.59" - wire $not$ls180.v:8189$2708_Y + wire $not$ls180.v:8189$2710_Y attribute \src "ls180.v:8200.8-8200.33" - wire $not$ls180.v:8200$2709_Y + wire $not$ls180.v:8200$2711_Y attribute \src "ls180.v:8215.8-8215.33" - wire $not$ls180.v:8215$2712_Y + wire $not$ls180.v:8215$2714_Y attribute \src "ls180.v:8251.36-8251.58" - wire $not$ls180.v:8251$2742_Y - attribute \src "ls180.v:8251.64-8251.89" wire $not$ls180.v:8251$2744_Y + attribute \src "ls180.v:8251.64-8251.89" + wire $not$ls180.v:8251$2746_Y attribute \src "ls180.v:8280.7-8280.29" - wire $not$ls180.v:8280$2751_Y + wire $not$ls180.v:8280$2753_Y attribute \src "ls180.v:8281.9-8281.26" - wire $not$ls180.v:8281$2752_Y + wire $not$ls180.v:8281$2754_Y attribute \src "ls180.v:8314.8-8314.29" - wire $not$ls180.v:8314$2758_Y + wire $not$ls180.v:8314$2760_Y attribute \src "ls180.v:8321.8-8321.29" - wire $not$ls180.v:8321$2760_Y + wire $not$ls180.v:8321$2762_Y attribute \src "ls180.v:8331.80-8331.106" - wire $not$ls180.v:8331$2763_Y + wire $not$ls180.v:8331$2765_Y attribute \src "ls180.v:8337.80-8337.106" - wire $not$ls180.v:8337$2768_Y + wire $not$ls180.v:8337$2770_Y attribute \src "ls180.v:8338.8-8338.34" - wire $not$ls180.v:8338$2770_Y + wire $not$ls180.v:8338$2772_Y attribute \src "ls180.v:8353.80-8353.106" - wire $not$ls180.v:8353$2774_Y + wire $not$ls180.v:8353$2776_Y attribute \src "ls180.v:8359.80-8359.106" - wire $not$ls180.v:8359$2779_Y + wire $not$ls180.v:8359$2781_Y attribute \src "ls180.v:8360.8-8360.34" - wire $not$ls180.v:8360$2781_Y + wire $not$ls180.v:8360$2783_Y attribute \src "ls180.v:8391.22-8391.41" - wire $not$ls180.v:8391$2785_Y + wire $not$ls180.v:8391$2787_Y attribute \src "ls180.v:8391.46-8391.73" - wire $not$ls180.v:8391$2786_Y + wire $not$ls180.v:8391$2788_Y attribute \src "ls180.v:8426.22-8426.40" - wire $not$ls180.v:8426$2790_Y + wire $not$ls180.v:8426$2792_Y attribute \src "ls180.v:8426.45-8426.70" - wire $not$ls180.v:8426$2791_Y + wire $not$ls180.v:8426$2793_Y attribute \src "ls180.v:8480.7-8480.31" - wire $not$ls180.v:8480$2802_Y + wire $not$ls180.v:8480$2804_Y attribute \src "ls180.v:8552.8-8552.46" - wire $not$ls180.v:8552$2814_Y + wire $not$ls180.v:8552$2816_Y attribute \src "ls180.v:8633.8-8633.47" - wire $not$ls180.v:8633$2826_Y + wire $not$ls180.v:8633$2828_Y attribute \src "ls180.v:8694.8-8694.48" - wire $not$ls180.v:8694$2838_Y + wire $not$ls180.v:8694$2840_Y attribute \src "ls180.v:8864.88-8864.118" - wire $not$ls180.v:8864$2852_Y + wire $not$ls180.v:8864$2854_Y attribute \src "ls180.v:8870.88-8870.118" - wire $not$ls180.v:8870$2857_Y + wire $not$ls180.v:8870$2859_Y attribute \src "ls180.v:8871.8-8871.38" - wire $not$ls180.v:8871$2859_Y + wire $not$ls180.v:8871$2861_Y attribute \src "ls180.v:8962.88-8962.118" - wire $not$ls180.v:8962$2874_Y + wire $not$ls180.v:8962$2876_Y attribute \src "ls180.v:8968.88-8968.118" - wire $not$ls180.v:8968$2879_Y + wire $not$ls180.v:8968$2881_Y attribute \src "ls180.v:8969.8-8969.38" - wire $not$ls180.v:8969$2881_Y + wire $not$ls180.v:8969$2883_Y attribute \src "ls180.v:8989.9-8989.28" - wire $not$ls180.v:8989$2884_Y + wire $not$ls180.v:8989$2886_Y attribute \src "ls180.v:9008.9-9008.28" - wire $not$ls180.v:9008$2885_Y + wire $not$ls180.v:9008$2887_Y attribute \src "ls180.v:9027.9-9027.28" - wire $not$ls180.v:9027$2886_Y + wire $not$ls180.v:9027$2888_Y attribute \src "ls180.v:9046.9-9046.28" - wire $not$ls180.v:9046$2887_Y + wire $not$ls180.v:9046$2889_Y attribute \src "ls180.v:9065.9-9065.28" - wire $not$ls180.v:9065$2888_Y + wire $not$ls180.v:9065$2890_Y attribute \src "ls180.v:9086.8-9086.21" - wire $not$ls180.v:9086$2889_Y + wire $not$ls180.v:9086$2891_Y attribute \src "ls180.v:10709.8-10709.51" - wire $or$ls180.v:10709$3077_Y + wire $or$ls180.v:10709$3079_Y attribute \src "ls180.v:2934.10-2934.71" wire $or$ls180.v:2934$57_Y attribute \src "ls180.v:2994.10-2994.71" @@ -248120,125 +248124,125 @@ module \ls180 attribute \src "ls180.v:7189.88-7189.329" wire $or$ls180.v:7189$2516_Y attribute \src "ls180.v:7706.20-7706.71" - wire $or$ls180.v:7706$2574_Y + wire $or$ls180.v:7706$2576_Y attribute \src "ls180.v:7707.20-7707.71" - wire $or$ls180.v:7707$2575_Y + wire $or$ls180.v:7707$2577_Y attribute \src "ls180.v:7708.20-7708.71" - wire $or$ls180.v:7708$2576_Y + wire $or$ls180.v:7708$2578_Y attribute \src "ls180.v:7709.20-7709.71" - wire $or$ls180.v:7709$2577_Y + wire $or$ls180.v:7709$2579_Y attribute \src "ls180.v:7710.20-7710.71" - wire $or$ls180.v:7710$2578_Y + wire $or$ls180.v:7710$2580_Y attribute \src "ls180.v:7711.20-7711.71" - wire $or$ls180.v:7711$2579_Y + wire $or$ls180.v:7711$2581_Y attribute \src "ls180.v:7712.20-7712.71" - wire $or$ls180.v:7712$2580_Y + wire $or$ls180.v:7712$2582_Y attribute \src "ls180.v:7713.20-7713.71" - wire $or$ls180.v:7713$2581_Y + wire $or$ls180.v:7713$2583_Y attribute \src "ls180.v:7714.20-7714.71" - wire $or$ls180.v:7714$2582_Y + wire $or$ls180.v:7714$2584_Y attribute \src "ls180.v:7715.20-7715.71" - wire $or$ls180.v:7715$2583_Y + wire $or$ls180.v:7715$2585_Y attribute \src "ls180.v:7716.21-7716.73" - wire $or$ls180.v:7716$2584_Y + wire $or$ls180.v:7716$2586_Y attribute \src "ls180.v:7717.21-7717.73" - wire $or$ls180.v:7717$2585_Y + wire $or$ls180.v:7717$2587_Y attribute \src "ls180.v:7718.21-7718.73" - wire $or$ls180.v:7718$2586_Y + wire $or$ls180.v:7718$2588_Y attribute \src "ls180.v:7719.21-7719.73" - wire $or$ls180.v:7719$2587_Y + wire $or$ls180.v:7719$2589_Y attribute \src "ls180.v:7720.21-7720.73" - wire $or$ls180.v:7720$2588_Y + wire $or$ls180.v:7720$2590_Y attribute \src "ls180.v:7721.21-7721.73" - wire $or$ls180.v:7721$2589_Y + wire $or$ls180.v:7721$2591_Y attribute \src "ls180.v:7722.21-7722.73" - wire $or$ls180.v:7722$2590_Y + wire $or$ls180.v:7722$2592_Y attribute \src "ls180.v:7723.21-7723.73" - wire $or$ls180.v:7723$2591_Y + wire $or$ls180.v:7723$2593_Y attribute \src "ls180.v:7724.21-7724.73" - wire $or$ls180.v:7724$2592_Y + wire $or$ls180.v:7724$2594_Y attribute \src "ls180.v:7725.21-7725.73" - wire $or$ls180.v:7725$2593_Y + wire $or$ls180.v:7725$2595_Y attribute \src "ls180.v:7726.21-7726.73" - wire $or$ls180.v:7726$2594_Y + wire $or$ls180.v:7726$2596_Y attribute \src "ls180.v:7727.21-7727.73" - wire $or$ls180.v:7727$2595_Y + wire $or$ls180.v:7727$2597_Y attribute \src "ls180.v:7728.21-7728.73" - wire $or$ls180.v:7728$2596_Y + wire $or$ls180.v:7728$2598_Y attribute \src "ls180.v:7729.21-7729.73" - wire $or$ls180.v:7729$2597_Y + wire $or$ls180.v:7729$2599_Y attribute \src "ls180.v:7730.7-7730.68" - wire $or$ls180.v:7730$2598_Y + wire $or$ls180.v:7730$2600_Y attribute \src "ls180.v:7741.7-7741.68" - wire $or$ls180.v:7741$2599_Y + wire $or$ls180.v:7741$2601_Y attribute \src "ls180.v:7752.7-7752.50" - wire $or$ls180.v:7752$2600_Y + wire $or$ls180.v:7752$2602_Y attribute \src "ls180.v:7897.7-7897.107" - wire $or$ls180.v:7897$2648_Y + wire $or$ls180.v:7897$2650_Y attribute \src "ls180.v:7943.7-7943.107" - wire $or$ls180.v:7943$2664_Y + wire $or$ls180.v:7943$2666_Y attribute \src "ls180.v:7989.7-7989.107" - wire $or$ls180.v:7989$2680_Y + wire $or$ls180.v:7989$2682_Y attribute \src "ls180.v:8035.7-8035.107" - wire $or$ls180.v:8035$2696_Y + wire $or$ls180.v:8035$2698_Y attribute \src "ls180.v:8223.40-8223.125" - wire $or$ls180.v:8223$2717_Y + wire $or$ls180.v:8223$2719_Y attribute \src "ls180.v:8223.39-8223.207" - wire $or$ls180.v:8223$2720_Y + wire $or$ls180.v:8223$2722_Y attribute \src "ls180.v:8223.38-8223.289" - wire $or$ls180.v:8223$2723_Y + wire $or$ls180.v:8223$2725_Y attribute \src "ls180.v:8223.37-8223.371" - wire $or$ls180.v:8223$2726_Y + wire $or$ls180.v:8223$2728_Y attribute \src "ls180.v:8224.41-8224.126" - wire $or$ls180.v:8224$2729_Y + wire $or$ls180.v:8224$2731_Y attribute \src "ls180.v:8224.40-8224.208" - wire $or$ls180.v:8224$2732_Y + wire $or$ls180.v:8224$2734_Y attribute \src "ls180.v:8224.39-8224.290" - wire $or$ls180.v:8224$2735_Y + wire $or$ls180.v:8224$2737_Y attribute \src "ls180.v:8224.38-8224.372" - wire $or$ls180.v:8224$2738_Y + wire $or$ls180.v:8224$2740_Y attribute \src "ls180.v:8228.7-8228.49" - wire $or$ls180.v:8228$2739_Y + wire $or$ls180.v:8228$2741_Y attribute \src "ls180.v:8391.21-8391.74" - wire $or$ls180.v:8391$2787_Y + wire $or$ls180.v:8391$2789_Y attribute \src "ls180.v:8426.21-8426.71" - wire $or$ls180.v:8426$2792_Y + wire $or$ls180.v:8426$2794_Y attribute \src "ls180.v:8494.32-8494.85" - wire $or$ls180.v:8494$2804_Y + wire $or$ls180.v:8494$2806_Y attribute \src "ls180.v:8500.8-8500.97" - wire $or$ls180.v:8500$2806_Y + wire $or$ls180.v:8500$2808_Y attribute \src "ls180.v:8517.52-8517.139" - wire $or$ls180.v:8517$2811_Y + wire $or$ls180.v:8517$2813_Y attribute \src "ls180.v:8518.51-8518.136" - wire $or$ls180.v:8518$2812_Y + wire $or$ls180.v:8518$2814_Y attribute \src "ls180.v:8552.7-8552.87" - wire $or$ls180.v:8552$2815_Y + wire $or$ls180.v:8552$2817_Y attribute \src "ls180.v:8575.33-8575.88" - wire $or$ls180.v:8575$2816_Y + wire $or$ls180.v:8575$2818_Y attribute \src "ls180.v:8581.8-8581.99" - wire $or$ls180.v:8581$2818_Y + wire $or$ls180.v:8581$2820_Y attribute \src "ls180.v:8598.53-8598.142" - wire $or$ls180.v:8598$2823_Y + wire $or$ls180.v:8598$2825_Y attribute \src "ls180.v:8599.52-8599.139" - wire $or$ls180.v:8599$2824_Y + wire $or$ls180.v:8599$2826_Y attribute \src "ls180.v:8633.7-8633.89" - wire $or$ls180.v:8633$2827_Y + wire $or$ls180.v:8633$2829_Y attribute \src "ls180.v:8654.34-8654.91" - wire $or$ls180.v:8654$2828_Y + wire $or$ls180.v:8654$2830_Y attribute \src "ls180.v:8660.8-8660.101" - wire $or$ls180.v:8660$2830_Y + wire $or$ls180.v:8660$2832_Y attribute \src "ls180.v:8677.54-8677.145" - wire $or$ls180.v:8677$2835_Y + wire $or$ls180.v:8677$2837_Y attribute \src "ls180.v:8678.53-8678.142" - wire $or$ls180.v:8678$2836_Y + wire $or$ls180.v:8678$2838_Y attribute \src "ls180.v:8694.7-8694.91" - wire $or$ls180.v:8694$2839_Y + wire $or$ls180.v:8694$2841_Y attribute \src "ls180.v:8883.8-8883.89" - wire $or$ls180.v:8883$2863_Y + wire $or$ls180.v:8883$2865_Y attribute \src "ls180.v:8900.48-8900.127" - wire $or$ls180.v:8900$2868_Y + wire $or$ls180.v:8900$2870_Y attribute \src "ls180.v:8901.47-8901.124" - wire $or$ls180.v:8901$2869_Y + wire $or$ls180.v:8901$2871_Y attribute \src "ls180.v:3358.46-3358.94" wire width 13 $sshl$ls180.v:3358$231_Y attribute \src "ls180.v:3515.46-3515.94" @@ -248302,55 +248306,55 @@ module \ls180 attribute \src "ls180.v:5836.40-5836.76" wire width 5 $sub$ls180.v:5836$1169_Y attribute \src "ls180.v:7776.31-7776.60" - wire width 32 $sub$ls180.v:7776$2607_Y + wire width 32 $sub$ls180.v:7776$2609_Y attribute \src "ls180.v:7813.31-7813.61" - wire width 10 $sub$ls180.v:7813$2624_Y + wire width 10 $sub$ls180.v:7813$2626_Y attribute \src "ls180.v:7819.34-7819.67" - wire $sub$ls180.v:7819$2625_Y + wire $sub$ls180.v:7819$2627_Y attribute \src "ls180.v:7830.36-7830.69" - wire $sub$ls180.v:7830$2628_Y + wire $sub$ls180.v:7830$2630_Y attribute \src "ls180.v:7894.59-7894.116" - wire width 4 $sub$ls180.v:7894$2646_Y + wire width 4 $sub$ls180.v:7894$2648_Y attribute \src "ls180.v:7913.46-7913.90" - wire width 3 $sub$ls180.v:7913$2650_Y + wire width 3 $sub$ls180.v:7913$2652_Y attribute \src "ls180.v:7940.59-7940.116" - wire width 4 $sub$ls180.v:7940$2662_Y + wire width 4 $sub$ls180.v:7940$2664_Y attribute \src "ls180.v:7959.46-7959.90" - wire width 3 $sub$ls180.v:7959$2666_Y + wire width 3 $sub$ls180.v:7959$2668_Y attribute \src "ls180.v:7986.59-7986.116" - wire width 4 $sub$ls180.v:7986$2678_Y + wire width 4 $sub$ls180.v:7986$2680_Y attribute \src "ls180.v:8005.46-8005.90" - wire width 3 $sub$ls180.v:8005$2682_Y + wire width 3 $sub$ls180.v:8005$2684_Y attribute \src "ls180.v:8032.59-8032.116" - wire width 4 $sub$ls180.v:8032$2694_Y + wire width 4 $sub$ls180.v:8032$2696_Y attribute \src "ls180.v:8051.46-8051.90" - wire width 3 $sub$ls180.v:8051$2698_Y + wire width 3 $sub$ls180.v:8051$2700_Y attribute \src "ls180.v:8062.25-8062.48" - wire width 5 $sub$ls180.v:8062$2702_Y + wire width 5 $sub$ls180.v:8062$2704_Y attribute \src "ls180.v:8069.25-8069.48" - wire width 4 $sub$ls180.v:8069$2705_Y + wire width 4 $sub$ls180.v:8069$2707_Y attribute \src "ls180.v:8201.33-8201.64" - wire $sub$ls180.v:8201$2710_Y + wire $sub$ls180.v:8201$2712_Y attribute \src "ls180.v:8216.33-8216.64" - wire width 3 $sub$ls180.v:8216$2713_Y + wire width 3 $sub$ls180.v:8216$2715_Y attribute \src "ls180.v:8343.33-8343.64" - wire width 5 $sub$ls180.v:8343$2772_Y + wire width 5 $sub$ls180.v:8343$2774_Y attribute \src "ls180.v:8365.33-8365.64" - wire width 5 $sub$ls180.v:8365$2783_Y + wire width 5 $sub$ls180.v:8365$2785_Y attribute \src "ls180.v:8400.34-8400.66" - wire width 3 $sub$ls180.v:8400$2788_Y + wire width 3 $sub$ls180.v:8400$2790_Y attribute \src "ls180.v:8435.32-8435.62" - wire width 3 $sub$ls180.v:8435$2793_Y + wire width 3 $sub$ls180.v:8435$2795_Y attribute \src "ls180.v:8459.30-8459.53" - wire width 32 $sub$ls180.v:8459$2796_Y + wire width 32 $sub$ls180.v:8459$2798_Y attribute \src "ls180.v:8473.30-8473.53" - wire width 32 $sub$ls180.v:8473$2800_Y + wire width 32 $sub$ls180.v:8473$2802_Y attribute \src "ls180.v:8876.36-8876.70" - wire width 6 $sub$ls180.v:8876$2861_Y + wire width 6 $sub$ls180.v:8876$2863_Y attribute \src "ls180.v:8974.36-8974.70" - wire width 6 $sub$ls180.v:8974$2883_Y + wire width 6 $sub$ls180.v:8974$2885_Y attribute \src "ls180.v:9087.22-9087.42" - wire width 20 $sub$ls180.v:9087$2890_Y + wire width 20 $sub$ls180.v:9087$2892_Y attribute \src "ls180.v:5113.353-5113.425" wire $xor$ls180.v:5113$860_Y attribute \src "ls180.v:5113.200-5113.272" @@ -250563,24 +250567,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:2014.6-2014.18" wire \builder_wait - attribute \src "ls180.v:13.19-13.23" - wire width 3 input 9 \eint - attribute \src "ls180.v:179.12-179.18" + attribute \src "ls180.v:16.19-16.23" + wire width 3 input 12 \eint + attribute \src "ls180.v:182.12-182.18" wire width 3 \eint_1 - attribute \src "ls180.v:40.21-40.27" - wire width 16 output 36 \gpio_i - attribute \src "ls180.v:41.20-41.26" - wire width 16 output 37 \gpio_o - attribute \src "ls180.v:42.20-42.27" - wire width 16 output 38 \gpio_oe - attribute \src "ls180.v:9.14-9.21" - wire output 5 \i2c_scl + attribute \src "ls180.v:5.21-5.27" + wire width 16 output 1 \gpio_i + attribute \src "ls180.v:6.20-6.26" + wire width 16 output 2 \gpio_o + attribute \src "ls180.v:7.20-7.27" + wire width 16 output 3 \gpio_oe + attribute \src "ls180.v:8.14-8.21" + wire output 4 \i2c_scl + attribute \src "ls180.v:9.14-9.23" + wire output 5 \i2c_sda_i attribute \src "ls180.v:10.14-10.23" - wire output 6 \i2c_sda_i - attribute \src "ls180.v:11.14-11.23" - wire output 7 \i2c_sda_o - attribute \src "ls180.v:12.14-12.24" - wire output 8 \i2c_sda_oe + wire output 6 \i2c_sda_o + attribute \src "ls180.v:11.14-11.24" + wire output 7 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -250939,71 +250943,71 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:204.12-204.66" + attribute \src "ls180.v:171.12-171.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:205.13-205.67" + attribute \src "ls180.v:172.13-172.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:206.13-206.68" + attribute \src "ls180.v:173.13-173.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:175.6-175.61" + attribute \src "ls180.v:174.6-174.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:176.5-176.62" + attribute \src "ls180.v:175.5-175.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:177.6-177.63" + attribute \src "ls180.v:176.6-176.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:178.6-178.64" + attribute \src "ls180.v:177.6-177.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:180.6-180.64" + attribute \src "ls180.v:200.6-200.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:181.5-181.65" + attribute \src "ls180.v:201.5-201.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:182.6-182.66" + attribute \src "ls180.v:202.6-202.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:183.6-183.67" + attribute \src "ls180.v:203.6-203.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:184.11-184.72" + attribute \src "ls180.v:204.11-204.72" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:185.12-185.73" + attribute \src "ls180.v:205.12-205.73" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:186.6-186.68" + attribute \src "ls180.v:206.6-206.68" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:187.13-187.68" + attribute \src "ls180.v:188.13-188.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:196.12-196.68" + attribute \src "ls180.v:197.12-197.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:193.6-193.65" + attribute \src "ls180.v:194.6-194.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:195.6-195.63" + attribute \src "ls180.v:196.6-196.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:194.6-194.64" + attribute \src "ls180.v:195.6-195.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:197.12-197.68" + attribute \src "ls180.v:198.12-198.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:188.12-188.70" + attribute \src "ls180.v:189.12-189.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:189.13-189.71" + attribute \src "ls180.v:190.13-190.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:190.6-190.65" + attribute \src "ls180.v:191.6-191.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:192.6-192.65" + attribute \src "ls180.v:193.6-193.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:191.6-191.64" + attribute \src "ls180.v:192.6-192.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:171.6-171.67" + attribute \src "ls180.v:184.6-184.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:173.6-173.68" + attribute \src "ls180.v:186.6-186.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:174.6-174.68" + attribute \src "ls180.v:187.6-187.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:172.6-172.68" + attribute \src "ls180.v:185.6-185.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:199.6-199.67" + attribute \src "ls180.v:178.6-178.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:201.6-201.68" + attribute \src "ls180.v:180.6-180.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:202.6-202.68" + attribute \src "ls180.v:181.6-181.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:200.6-200.68" + attribute \src "ls180.v:179.6-179.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -254333,50 +254337,50 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:341.6-341.13" wire \por_clk - attribute \src "ls180.v:39.19-39.22" - wire width 2 output 35 \pwm - attribute \src "ls180.v:203.12-203.17" + attribute \src "ls180.v:17.19-17.22" + wire width 2 output 13 \pwm + attribute \src "ls180.v:183.12-183.17" wire width 2 \pwm_1 - attribute \src "ls180.v:14.13-14.23" - wire output 10 \sdcard_clk - attribute \src "ls180.v:15.14-15.26" - wire output 11 \sdcard_cmd_i - attribute \src "ls180.v:16.13-16.25" - wire output 12 \sdcard_cmd_o - attribute \src "ls180.v:17.13-17.26" - wire output 13 \sdcard_cmd_oe - attribute \src "ls180.v:18.20-18.33" - wire width 4 output 14 \sdcard_data_i - attribute \src "ls180.v:19.19-19.32" - wire width 4 output 15 \sdcard_data_o - attribute \src "ls180.v:20.13-20.27" - wire output 16 \sdcard_data_oe - attribute \src "ls180.v:21.20-21.27" - wire width 13 output 17 \sdram_a - attribute \src "ls180.v:30.19-30.27" - wire width 2 output 26 \sdram_ba - attribute \src "ls180.v:27.13-27.24" - wire output 23 \sdram_cas_n - attribute \src "ls180.v:29.13-29.22" - wire output 25 \sdram_cke - attribute \src "ls180.v:32.13-32.24" - wire output 28 \sdram_clock - attribute \src "ls180.v:198.6-198.19" - wire \sdram_clock_1 - attribute \src "ls180.v:28.13-28.23" - wire output 24 \sdram_cs_n + attribute \src "ls180.v:36.13-36.23" + wire output 32 \sdcard_clk + attribute \src "ls180.v:37.14-37.26" + wire output 33 \sdcard_cmd_i + attribute \src "ls180.v:38.13-38.25" + wire output 34 \sdcard_cmd_o + attribute \src "ls180.v:39.13-39.26" + wire output 35 \sdcard_cmd_oe + attribute \src "ls180.v:40.20-40.33" + wire width 4 output 36 \sdcard_data_i + attribute \src "ls180.v:41.19-41.32" + wire width 4 output 37 \sdcard_data_o + attribute \src "ls180.v:42.13-42.27" + wire output 38 \sdcard_data_oe + attribute \src "ls180.v:22.20-22.27" + wire width 13 output 18 \sdram_a attribute \src "ls180.v:31.19-31.27" - wire width 2 output 27 \sdram_dm - attribute \src "ls180.v:22.21-22.31" - wire width 16 output 18 \sdram_dq_i - attribute \src "ls180.v:23.20-23.30" - wire width 16 output 19 \sdram_dq_o - attribute \src "ls180.v:24.13-24.24" - wire output 20 \sdram_dq_oe - attribute \src "ls180.v:26.13-26.24" - wire output 22 \sdram_ras_n - attribute \src "ls180.v:25.13-25.23" - wire output 21 \sdram_we_n + wire width 2 output 27 \sdram_ba + attribute \src "ls180.v:28.13-28.24" + wire output 24 \sdram_cas_n + attribute \src "ls180.v:30.13-30.22" + wire output 26 \sdram_cke + attribute \src "ls180.v:33.13-33.24" + wire output 29 \sdram_clock + attribute \src "ls180.v:199.6-199.19" + wire \sdram_clock_1 + attribute \src "ls180.v:29.13-29.23" + wire output 25 \sdram_cs_n + attribute \src "ls180.v:32.19-32.27" + wire width 2 output 28 \sdram_dm + attribute \src "ls180.v:23.21-23.31" + wire width 16 output 19 \sdram_dq_i + attribute \src "ls180.v:24.20-24.30" + wire width 16 output 20 \sdram_dq_o + attribute \src "ls180.v:25.13-25.24" + wire output 21 \sdram_dq_oe + attribute \src "ls180.v:27.13-27.24" + wire output 23 \sdram_ras_n + attribute \src "ls180.v:26.13-26.23" + wire output 22 \sdram_we_n attribute \src "ls180.v:2763.6-2763.15" wire \sdrio_clk attribute \src "ls180.v:2764.6-2764.17" @@ -254515,22 +254519,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2772.6-2772.17" wire \sdrio_clk_9 - attribute \src "ls180.v:5.13-5.26" - wire output 1 \spimaster_clk - attribute \src "ls180.v:7.13-7.27" - wire output 3 \spimaster_cs_n - attribute \src "ls180.v:8.13-8.27" - wire input 4 \spimaster_miso - attribute \src "ls180.v:6.13-6.27" - wire output 2 \spimaster_mosi - attribute \src "ls180.v:33.13-33.26" - wire output 29 \spisdcard_clk - attribute \src "ls180.v:35.13-35.27" - wire output 31 \spisdcard_cs_n - attribute \src "ls180.v:36.13-36.27" - wire input 32 \spisdcard_miso - attribute \src "ls180.v:34.13-34.27" - wire output 30 \spisdcard_mosi + attribute \src "ls180.v:18.13-18.26" + wire output 14 \spimaster_clk + attribute \src "ls180.v:20.13-20.27" + wire output 16 \spimaster_cs_n + attribute \src "ls180.v:21.13-21.27" + wire input 17 \spimaster_miso + attribute \src "ls180.v:19.13-19.27" + wire output 15 \spimaster_mosi + attribute \src "ls180.v:12.13-12.26" + wire output 8 \spisdcard_clk + attribute \src "ls180.v:14.13-14.27" + wire output 10 \spisdcard_cs_n + attribute \src "ls180.v:15.13-15.27" + wire input 11 \spisdcard_miso + attribute \src "ls180.v:13.13-13.27" + wire output 9 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:339.6-339.15" @@ -254545,10 +254549,10 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:340.6-340.15" wire \sys_rst_1 - attribute \src "ls180.v:38.13-38.20" - wire input 34 \uart_rx - attribute \src "ls180.v:37.13-37.20" - wire output 33 \uart_tx + attribute \src "ls180.v:35.13-35.20" + wire input 31 \uart_rx + attribute \src "ls180.v:34.13-34.20" + wire output 30 \uart_tx attribute \src "ls180.v:10351.12-10351.15" memory width 64 size 64 \mem attribute \src "ls180.v:10379.12-10379.17" @@ -254851,7 +254855,7 @@ module \ls180 connect \Y $add$ls180.v:5758$1161_Y end attribute \src "ls180.v:7765.36-7765.70" - cell $add $add$ls180.v:7765$2602 + cell $add $add$ls180.v:7765$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254859,10 +254863,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7765$2602_Y + connect \Y $add$ls180.v:7765$2604_Y end attribute \src "ls180.v:7866.37-7866.72" - cell $add $add$ls180.v:7866$2635 + cell $add $add$ls180.v:7866$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254870,10 +254874,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7866$2635_Y + connect \Y $add$ls180.v:7866$2637_Y end attribute \src "ls180.v:7883.60-7883.119" - cell $add $add$ls180.v:7883$2639 + cell $add $add$ls180.v:7883$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254881,10 +254885,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7883$2639_Y + connect \Y $add$ls180.v:7883$2641_Y end attribute \src "ls180.v:7886.60-7886.119" - cell $add $add$ls180.v:7886$2640 + cell $add $add$ls180.v:7886$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254892,10 +254896,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7886$2640_Y + connect \Y $add$ls180.v:7886$2642_Y end attribute \src "ls180.v:7890.59-7890.116" - cell $add $add$ls180.v:7890$2645 + cell $add $add$ls180.v:7890$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254903,10 +254907,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7890$2645_Y + connect \Y $add$ls180.v:7890$2647_Y end attribute \src "ls180.v:7929.60-7929.119" - cell $add $add$ls180.v:7929$2655 + cell $add $add$ls180.v:7929$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254914,10 +254918,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7929$2655_Y + connect \Y $add$ls180.v:7929$2657_Y end attribute \src "ls180.v:7932.60-7932.119" - cell $add $add$ls180.v:7932$2656 + cell $add $add$ls180.v:7932$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254925,10 +254929,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7932$2656_Y + connect \Y $add$ls180.v:7932$2658_Y end attribute \src "ls180.v:7936.59-7936.116" - cell $add $add$ls180.v:7936$2661 + cell $add $add$ls180.v:7936$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254936,10 +254940,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7936$2661_Y + connect \Y $add$ls180.v:7936$2663_Y end attribute \src "ls180.v:7975.60-7975.119" - cell $add $add$ls180.v:7975$2671 + cell $add $add$ls180.v:7975$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254947,10 +254951,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7975$2671_Y + connect \Y $add$ls180.v:7975$2673_Y end attribute \src "ls180.v:7978.60-7978.119" - cell $add $add$ls180.v:7978$2672 + cell $add $add$ls180.v:7978$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254958,10 +254962,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7978$2672_Y + connect \Y $add$ls180.v:7978$2674_Y end attribute \src "ls180.v:7982.59-7982.116" - cell $add $add$ls180.v:7982$2677 + cell $add $add$ls180.v:7982$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254969,10 +254973,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7982$2677_Y + connect \Y $add$ls180.v:7982$2679_Y end attribute \src "ls180.v:8021.60-8021.119" - cell $add $add$ls180.v:8021$2687 + cell $add $add$ls180.v:8021$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254980,10 +254984,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:8021$2687_Y + connect \Y $add$ls180.v:8021$2689_Y end attribute \src "ls180.v:8024.60-8024.119" - cell $add $add$ls180.v:8024$2688 + cell $add $add$ls180.v:8024$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254991,10 +254995,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:8024$2688_Y + connect \Y $add$ls180.v:8024$2690_Y end attribute \src "ls180.v:8028.59-8028.116" - cell $add $add$ls180.v:8028$2693 + cell $add $add$ls180.v:8028$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255002,10 +255006,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:8028$2693_Y + connect \Y $add$ls180.v:8028$2695_Y end attribute \src "ls180.v:8258.34-8258.66" - cell $add $add$ls180.v:8258$2747 + cell $add $add$ls180.v:8258$2749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255013,10 +255017,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8258$2747_Y + connect \Y $add$ls180.v:8258$2749_Y end attribute \src "ls180.v:8274.73-8274.131" - cell $add $add$ls180.v:8274$2750 + cell $add $add$ls180.v:8274$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255024,10 +255028,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8274$2750_Y + connect \Y $add$ls180.v:8274$2752_Y end attribute \src "ls180.v:8287.34-8287.66" - cell $add $add$ls180.v:8287$2754 + cell $add $add$ls180.v:8287$2756 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255035,10 +255039,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8287$2754_Y + connect \Y $add$ls180.v:8287$2756_Y end attribute \src "ls180.v:8306.73-8306.131" - cell $add $add$ls180.v:8306$2757 + cell $add $add$ls180.v:8306$2759 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255046,10 +255050,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8306$2757_Y + connect \Y $add$ls180.v:8306$2759_Y end attribute \src "ls180.v:8332.33-8332.65" - cell $add $add$ls180.v:8332$2765 + cell $add $add$ls180.v:8332$2767 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255057,10 +255061,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8332$2765_Y + connect \Y $add$ls180.v:8332$2767_Y end attribute \src "ls180.v:8335.33-8335.65" - cell $add $add$ls180.v:8335$2766 + cell $add $add$ls180.v:8335$2768 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255068,10 +255072,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8335$2766_Y + connect \Y $add$ls180.v:8335$2768_Y end attribute \src "ls180.v:8339.33-8339.64" - cell $add $add$ls180.v:8339$2771 + cell $add $add$ls180.v:8339$2773 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255079,10 +255083,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8339$2771_Y + connect \Y $add$ls180.v:8339$2773_Y end attribute \src "ls180.v:8354.33-8354.65" - cell $add $add$ls180.v:8354$2776 + cell $add $add$ls180.v:8354$2778 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255090,10 +255094,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8354$2776_Y + connect \Y $add$ls180.v:8354$2778_Y end attribute \src "ls180.v:8357.33-8357.65" - cell $add $add$ls180.v:8357$2777 + cell $add $add$ls180.v:8357$2779 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255101,10 +255105,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8357$2777_Y + connect \Y $add$ls180.v:8357$2779_Y end attribute \src "ls180.v:8361.33-8361.64" - cell $add $add$ls180.v:8361$2782 + cell $add $add$ls180.v:8361$2784 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255112,10 +255116,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8361$2782_Y + connect \Y $add$ls180.v:8361$2784_Y end attribute \src "ls180.v:8382.35-8382.70" - cell $add $add$ls180.v:8382$2784 + cell $add $add$ls180.v:8382$2786 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -255123,10 +255127,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8382$2784_Y + connect \Y $add$ls180.v:8382$2786_Y end attribute \src "ls180.v:8417.34-8417.68" - cell $add $add$ls180.v:8417$2789 + cell $add $add$ls180.v:8417$2791 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -255134,10 +255138,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8417$2789_Y + connect \Y $add$ls180.v:8417$2791_Y end attribute \src "ls180.v:8453.25-8453.49" - cell $add $add$ls180.v:8453$2794 + cell $add $add$ls180.v:8453$2796 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255145,10 +255149,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8453$2794_Y + connect \Y $add$ls180.v:8453$2796_Y end attribute \src "ls180.v:8467.25-8467.49" - cell $add $add$ls180.v:8467$2798 + cell $add $add$ls180.v:8467$2800 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255156,10 +255160,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8467$2798_Y + connect \Y $add$ls180.v:8467$2800_Y end attribute \src "ls180.v:8481.31-8481.61" - cell $add $add$ls180.v:8481$2803 + cell $add $add$ls180.v:8481$2805 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -255167,10 +255171,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8481$2803_Y + connect \Y $add$ls180.v:8481$2805_Y end attribute \src "ls180.v:8504.45-8504.88" - cell $add $add$ls180.v:8504$2807 + cell $add $add$ls180.v:8504$2809 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255178,10 +255182,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8504$2807_Y + connect \Y $add$ls180.v:8504$2809_Y end attribute \src "ls180.v:8550.71-8550.114" - cell $add $add$ls180.v:8550$2813 + cell $add $add$ls180.v:8550$2815 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255189,10 +255193,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8550$2813_Y + connect \Y $add$ls180.v:8550$2815_Y end attribute \src "ls180.v:8585.46-8585.90" - cell $add $add$ls180.v:8585$2819 + cell $add $add$ls180.v:8585$2821 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255200,10 +255204,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8585$2819_Y + connect \Y $add$ls180.v:8585$2821_Y end attribute \src "ls180.v:8631.72-8631.116" - cell $add $add$ls180.v:8631$2825 + cell $add $add$ls180.v:8631$2827 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255211,10 +255215,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8631$2825_Y + connect \Y $add$ls180.v:8631$2827_Y end attribute \src "ls180.v:8664.47-8664.92" - cell $add $add$ls180.v:8664$2831 + cell $add $add$ls180.v:8664$2833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255222,10 +255226,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8664$2831_Y + connect \Y $add$ls180.v:8664$2833_Y end attribute \src "ls180.v:8692.73-8692.118" - cell $add $add$ls180.v:8692$2837 + cell $add $add$ls180.v:8692$2839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255233,10 +255237,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8692$2837_Y + connect \Y $add$ls180.v:8692$2839_Y end attribute \src "ls180.v:8804.39-8804.75" - cell $add $add$ls180.v:8804$2850 + cell $add $add$ls180.v:8804$2852 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255244,10 +255248,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8804$2850_Y + connect \Y $add$ls180.v:8804$2852_Y end attribute \src "ls180.v:8865.37-8865.73" - cell $add $add$ls180.v:8865$2854 + cell $add $add$ls180.v:8865$2856 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255255,10 +255259,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8865$2854_Y + connect \Y $add$ls180.v:8865$2856_Y end attribute \src "ls180.v:8868.37-8868.73" - cell $add $add$ls180.v:8868$2855 + cell $add $add$ls180.v:8868$2857 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255266,10 +255270,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8868$2855_Y + connect \Y $add$ls180.v:8868$2857_Y end attribute \src "ls180.v:8872.36-8872.70" - cell $add $add$ls180.v:8872$2860 + cell $add $add$ls180.v:8872$2862 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255277,10 +255281,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8872$2860_Y + connect \Y $add$ls180.v:8872$2862_Y end attribute \src "ls180.v:8887.41-8887.80" - cell $add $add$ls180.v:8887$2864 + cell $add $add$ls180.v:8887$2866 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255288,10 +255292,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8887$2864_Y + connect \Y $add$ls180.v:8887$2866_Y end attribute \src "ls180.v:8933.67-8933.106" - cell $add $add$ls180.v:8933$2870 + cell $add $add$ls180.v:8933$2872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255299,10 +255303,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8933$2870_Y + connect \Y $add$ls180.v:8933$2872_Y end attribute \src "ls180.v:8959.39-8959.76" - cell $add $add$ls180.v:8959$2872 + cell $add $add$ls180.v:8959$2874 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255310,10 +255314,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8959$2872_Y + connect \Y $add$ls180.v:8959$2874_Y end attribute \src "ls180.v:8963.37-8963.73" - cell $add $add$ls180.v:8963$2876 + cell $add $add$ls180.v:8963$2878 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255321,10 +255325,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8963$2876_Y + connect \Y $add$ls180.v:8963$2878_Y end attribute \src "ls180.v:8966.37-8966.73" - cell $add $add$ls180.v:8966$2877 + cell $add $add$ls180.v:8966$2879 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255332,10 +255336,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8966$2877_Y + connect \Y $add$ls180.v:8966$2879_Y end attribute \src "ls180.v:8970.36-8970.70" - cell $add $add$ls180.v:8970$2882 + cell $add $add$ls180.v:8970$2884 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255343,7 +255347,7 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8970$2882_Y + connect \Y $add$ls180.v:8970$2884_Y end attribute \src "ls180.v:2929.9-2929.90" cell $and $and$ls180.v:2929$53 @@ -267775,19 +267779,41 @@ module \ls180 connect \B \main_sdram_cmd_payload_is_write connect \Y $and$ls180.v:7468$2564_Y end + attribute \src "ls180.v:7687.18-7687.68" + cell $and $and$ls180.v:7687$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_dfi_p0_wrdata_en + connect \B \main_dfi_p0_wrdata_mask [0] + connect \Y $and$ls180.v:7687$2571_Y + end + attribute \src "ls180.v:7688.18-7688.68" + cell $and $and$ls180.v:7688$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_dfi_p0_wrdata_en + connect \B \main_dfi_p0_wrdata_mask [1] + connect \Y $and$ls180.v:7688$2572_Y + end attribute \src "ls180.v:7690.17-7690.67" - cell $and $and$ls180.v:7690$2572 + cell $and $and$ls180.v:7690$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7690$2571_Y + connect \A $not$ls180.v:7690$2573_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7690$2572_Y + connect \Y $and$ls180.v:7690$2574_Y end attribute \src "ls180.v:7769.8-7769.67" - cell $and $and$ls180.v:7769$2603 + cell $and $and$ls180.v:7769$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267795,32 +267821,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7769$2603_Y + connect \Y $and$ls180.v:7769$2605_Y end attribute \src "ls180.v:7769.7-7769.102" - cell $and $and$ls180.v:7769$2605 + cell $and $and$ls180.v:7769$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7769$2603_Y - connect \B $not$ls180.v:7769$2604_Y - connect \Y $and$ls180.v:7769$2605_Y + connect \A $and$ls180.v:7769$2605_Y + connect \B $not$ls180.v:7769$2606_Y + connect \Y $and$ls180.v:7769$2607_Y end attribute \src "ls180.v:7788.7-7788.75" - cell $and $and$ls180.v:7788$2609 + cell $and $and$ls180.v:7788$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7788$2608_Y + connect \A $not$ls180.v:7788$2610_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7788$2609_Y + connect \Y $and$ls180.v:7788$2611_Y end attribute \src "ls180.v:7792.8-7792.65" - cell $and $and$ls180.v:7792$2610 + cell $and $and$ls180.v:7792$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267828,21 +267854,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7792$2610_Y + connect \Y $and$ls180.v:7792$2612_Y end attribute \src "ls180.v:7792.7-7792.99" - cell $and $and$ls180.v:7792$2612 + cell $and $and$ls180.v:7792$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7792$2610_Y - connect \B $not$ls180.v:7792$2611_Y - connect \Y $and$ls180.v:7792$2612_Y + connect \A $and$ls180.v:7792$2612_Y + connect \B $not$ls180.v:7792$2613_Y + connect \Y $and$ls180.v:7792$2614_Y end attribute \src "ls180.v:7796.8-7796.65" - cell $and $and$ls180.v:7796$2613 + cell $and $and$ls180.v:7796$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267850,21 +267876,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7796$2613_Y + connect \Y $and$ls180.v:7796$2615_Y end attribute \src "ls180.v:7796.7-7796.99" - cell $and $and$ls180.v:7796$2615 + cell $and $and$ls180.v:7796$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7796$2613_Y - connect \B $not$ls180.v:7796$2614_Y - connect \Y $and$ls180.v:7796$2615_Y + connect \A $and$ls180.v:7796$2615_Y + connect \B $not$ls180.v:7796$2616_Y + connect \Y $and$ls180.v:7796$2617_Y end attribute \src "ls180.v:7800.8-7800.65" - cell $and $and$ls180.v:7800$2616 + cell $and $and$ls180.v:7800$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267872,21 +267898,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7800$2616_Y + connect \Y $and$ls180.v:7800$2618_Y end attribute \src "ls180.v:7800.7-7800.99" - cell $and $and$ls180.v:7800$2618 + cell $and $and$ls180.v:7800$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7800$2616_Y - connect \B $not$ls180.v:7800$2617_Y - connect \Y $and$ls180.v:7800$2618_Y + connect \A $and$ls180.v:7800$2618_Y + connect \B $not$ls180.v:7800$2619_Y + connect \Y $and$ls180.v:7800$2620_Y end attribute \src "ls180.v:7804.8-7804.65" - cell $and $and$ls180.v:7804$2619 + cell $and $and$ls180.v:7804$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267894,43 +267920,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:7804$2619_Y + connect \Y $and$ls180.v:7804$2621_Y end attribute \src "ls180.v:7804.7-7804.99" - cell $and $and$ls180.v:7804$2621 + cell $and $and$ls180.v:7804$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7804$2619_Y - connect \B $not$ls180.v:7804$2620_Y - connect \Y $and$ls180.v:7804$2621_Y + connect \A $and$ls180.v:7804$2621_Y + connect \B $not$ls180.v:7804$2622_Y + connect \Y $and$ls180.v:7804$2623_Y end attribute \src "ls180.v:7812.7-7812.56" - cell $and $and$ls180.v:7812$2623 + cell $and $and$ls180.v:7812$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7812$2622_Y - connect \Y $and$ls180.v:7812$2623_Y + connect \B $not$ls180.v:7812$2624_Y + connect \Y $and$ls180.v:7812$2625_Y end attribute \src "ls180.v:7840.7-7840.75" - cell $and $and$ls180.v:7840$2630 + cell $and $and$ls180.v:7840$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7840$2629_Y - connect \Y $and$ls180.v:7840$2630_Y + connect \B $eq$ls180.v:7840$2631_Y + connect \Y $and$ls180.v:7840$2632_Y end attribute \src "ls180.v:7882.8-7882.131" - cell $and $and$ls180.v:7882$2636 + cell $and $and$ls180.v:7882$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267938,21 +267964,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7882$2636_Y + connect \Y $and$ls180.v:7882$2638_Y end attribute \src "ls180.v:7882.7-7882.190" - cell $and $and$ls180.v:7882$2638 + cell $and $and$ls180.v:7882$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7882$2636_Y - connect \B $not$ls180.v:7882$2637_Y - connect \Y $and$ls180.v:7882$2638_Y + connect \A $and$ls180.v:7882$2638_Y + connect \B $not$ls180.v:7882$2639_Y + connect \Y $and$ls180.v:7882$2640_Y end attribute \src "ls180.v:7888.8-7888.131" - cell $and $and$ls180.v:7888$2641 + cell $and $and$ls180.v:7888$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267960,21 +267986,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7888$2641_Y + connect \Y $and$ls180.v:7888$2643_Y end attribute \src "ls180.v:7888.7-7888.190" - cell $and $and$ls180.v:7888$2643 + cell $and $and$ls180.v:7888$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7888$2641_Y - connect \B $not$ls180.v:7888$2642_Y - connect \Y $and$ls180.v:7888$2643_Y + connect \A $and$ls180.v:7888$2643_Y + connect \B $not$ls180.v:7888$2644_Y + connect \Y $and$ls180.v:7888$2645_Y end attribute \src "ls180.v:7928.8-7928.131" - cell $and $and$ls180.v:7928$2652 + cell $and $and$ls180.v:7928$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267982,21 +268008,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7928$2652_Y + connect \Y $and$ls180.v:7928$2654_Y end attribute \src "ls180.v:7928.7-7928.190" - cell $and $and$ls180.v:7928$2654 + cell $and $and$ls180.v:7928$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7928$2652_Y - connect \B $not$ls180.v:7928$2653_Y - connect \Y $and$ls180.v:7928$2654_Y + connect \A $and$ls180.v:7928$2654_Y + connect \B $not$ls180.v:7928$2655_Y + connect \Y $and$ls180.v:7928$2656_Y end attribute \src "ls180.v:7934.8-7934.131" - cell $and $and$ls180.v:7934$2657 + cell $and $and$ls180.v:7934$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268004,21 +268030,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7934$2657_Y + connect \Y $and$ls180.v:7934$2659_Y end attribute \src "ls180.v:7934.7-7934.190" - cell $and $and$ls180.v:7934$2659 + cell $and $and$ls180.v:7934$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7934$2657_Y - connect \B $not$ls180.v:7934$2658_Y - connect \Y $and$ls180.v:7934$2659_Y + connect \A $and$ls180.v:7934$2659_Y + connect \B $not$ls180.v:7934$2660_Y + connect \Y $and$ls180.v:7934$2661_Y end attribute \src "ls180.v:7974.8-7974.131" - cell $and $and$ls180.v:7974$2668 + cell $and $and$ls180.v:7974$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268026,21 +268052,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7974$2668_Y + connect \Y $and$ls180.v:7974$2670_Y end attribute \src "ls180.v:7974.7-7974.190" - cell $and $and$ls180.v:7974$2670 + cell $and $and$ls180.v:7974$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7974$2668_Y - connect \B $not$ls180.v:7974$2669_Y - connect \Y $and$ls180.v:7974$2670_Y + connect \A $and$ls180.v:7974$2670_Y + connect \B $not$ls180.v:7974$2671_Y + connect \Y $and$ls180.v:7974$2672_Y end attribute \src "ls180.v:7980.8-7980.131" - cell $and $and$ls180.v:7980$2673 + cell $and $and$ls180.v:7980$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268048,21 +268074,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7980$2673_Y + connect \Y $and$ls180.v:7980$2675_Y end attribute \src "ls180.v:7980.7-7980.190" - cell $and $and$ls180.v:7980$2675 + cell $and $and$ls180.v:7980$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7980$2673_Y - connect \B $not$ls180.v:7980$2674_Y - connect \Y $and$ls180.v:7980$2675_Y + connect \A $and$ls180.v:7980$2675_Y + connect \B $not$ls180.v:7980$2676_Y + connect \Y $and$ls180.v:7980$2677_Y end attribute \src "ls180.v:8020.8-8020.131" - cell $and $and$ls180.v:8020$2684 + cell $and $and$ls180.v:8020$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268070,21 +268096,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8020$2684_Y + connect \Y $and$ls180.v:8020$2686_Y end attribute \src "ls180.v:8020.7-8020.190" - cell $and $and$ls180.v:8020$2686 + cell $and $and$ls180.v:8020$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8020$2684_Y - connect \B $not$ls180.v:8020$2685_Y - connect \Y $and$ls180.v:8020$2686_Y + connect \A $and$ls180.v:8020$2686_Y + connect \B $not$ls180.v:8020$2687_Y + connect \Y $and$ls180.v:8020$2688_Y end attribute \src "ls180.v:8026.8-8026.131" - cell $and $and$ls180.v:8026$2689 + cell $and $and$ls180.v:8026$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268092,109 +268118,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8026$2689_Y + connect \Y $and$ls180.v:8026$2691_Y end attribute \src "ls180.v:8026.7-8026.190" - cell $and $and$ls180.v:8026$2691 + cell $and $and$ls180.v:8026$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8026$2689_Y - connect \B $not$ls180.v:8026$2690_Y - connect \Y $and$ls180.v:8026$2691_Y + connect \A $and$ls180.v:8026$2691_Y + connect \B $not$ls180.v:8026$2692_Y + connect \Y $and$ls180.v:8026$2693_Y end attribute \src "ls180.v:8223.48-8223.124" - cell $and $and$ls180.v:8223$2716 + cell $and $and$ls180.v:8223$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2715_Y + connect \A $eq$ls180.v:8223$2717_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8223$2716_Y + connect \Y $and$ls180.v:8223$2718_Y end attribute \src "ls180.v:8223.130-8223.206" - cell $and $and$ls180.v:8223$2719 + cell $and $and$ls180.v:8223$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2718_Y + connect \A $eq$ls180.v:8223$2720_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8223$2719_Y + connect \Y $and$ls180.v:8223$2721_Y end attribute \src "ls180.v:8223.212-8223.288" - cell $and $and$ls180.v:8223$2722 + cell $and $and$ls180.v:8223$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2721_Y + connect \A $eq$ls180.v:8223$2723_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8223$2722_Y + connect \Y $and$ls180.v:8223$2724_Y end attribute \src "ls180.v:8223.294-8223.370" - cell $and $and$ls180.v:8223$2725 + cell $and $and$ls180.v:8223$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2724_Y + connect \A $eq$ls180.v:8223$2726_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8223$2725_Y + connect \Y $and$ls180.v:8223$2727_Y end attribute \src "ls180.v:8224.49-8224.125" - cell $and $and$ls180.v:8224$2728 + cell $and $and$ls180.v:8224$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2727_Y + connect \A $eq$ls180.v:8224$2729_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8224$2728_Y + connect \Y $and$ls180.v:8224$2730_Y end attribute \src "ls180.v:8224.131-8224.207" - cell $and $and$ls180.v:8224$2731 + cell $and $and$ls180.v:8224$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2730_Y + connect \A $eq$ls180.v:8224$2732_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8224$2731_Y + connect \Y $and$ls180.v:8224$2733_Y end attribute \src "ls180.v:8224.213-8224.289" - cell $and $and$ls180.v:8224$2734 + cell $and $and$ls180.v:8224$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2733_Y + connect \A $eq$ls180.v:8224$2735_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8224$2734_Y + connect \Y $and$ls180.v:8224$2736_Y end attribute \src "ls180.v:8224.295-8224.371" - cell $and $and$ls180.v:8224$2737 + cell $and $and$ls180.v:8224$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2736_Y + connect \A $eq$ls180.v:8224$2738_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8224$2737_Y + connect \Y $and$ls180.v:8224$2739_Y end attribute \src "ls180.v:8243.8-8243.49" - cell $and $and$ls180.v:8243$2740 + cell $and $and$ls180.v:8243$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268202,10 +268228,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8243$2740_Y + connect \Y $and$ls180.v:8243$2742_Y end attribute \src "ls180.v:8246.8-8246.53" - cell $and $and$ls180.v:8246$2741 + cell $and $and$ls180.v:8246$2743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268213,32 +268239,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8246$2741_Y + connect \Y $and$ls180.v:8246$2743_Y end attribute \src "ls180.v:8251.8-8251.59" - cell $and $and$ls180.v:8251$2743 + cell $and $and$ls180.v:8251$2745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8251$2742_Y - connect \Y $and$ls180.v:8251$2743_Y + connect \B $not$ls180.v:8251$2744_Y + connect \Y $and$ls180.v:8251$2745_Y end attribute \src "ls180.v:8251.7-8251.90" - cell $and $and$ls180.v:8251$2745 + cell $and $and$ls180.v:8251$2747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8251$2743_Y - connect \B $not$ls180.v:8251$2744_Y - connect \Y $and$ls180.v:8251$2745_Y + connect \A $and$ls180.v:8251$2745_Y + connect \B $not$ls180.v:8251$2746_Y + connect \Y $and$ls180.v:8251$2747_Y end attribute \src "ls180.v:8257.8-8257.59" - cell $and $and$ls180.v:8257$2746 + cell $and $and$ls180.v:8257$2748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268246,43 +268272,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8257$2746_Y + connect \Y $and$ls180.v:8257$2748_Y end attribute \src "ls180.v:8281.8-8281.48" - cell $and $and$ls180.v:8281$2753 + cell $and $and$ls180.v:8281$2755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8281$2752_Y + connect \A $not$ls180.v:8281$2754_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8281$2753_Y + connect \Y $and$ls180.v:8281$2755_Y end attribute \src "ls180.v:8314.7-8314.57" - cell $and $and$ls180.v:8314$2759 + cell $and $and$ls180.v:8314$2761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8314$2758_Y + connect \A $not$ls180.v:8314$2760_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8314$2759_Y + connect \Y $and$ls180.v:8314$2761_Y end attribute \src "ls180.v:8321.7-8321.57" - cell $and $and$ls180.v:8321$2761 + cell $and $and$ls180.v:8321$2763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8321$2760_Y + connect \A $not$ls180.v:8321$2762_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8321$2761_Y + connect \Y $and$ls180.v:8321$2763_Y end attribute \src "ls180.v:8331.8-8331.75" - cell $and $and$ls180.v:8331$2762 + cell $and $and$ls180.v:8331$2764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268290,21 +268316,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8331$2762_Y + connect \Y $and$ls180.v:8331$2764_Y end attribute \src "ls180.v:8331.7-8331.107" - cell $and $and$ls180.v:8331$2764 + cell $and $and$ls180.v:8331$2766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8331$2762_Y - connect \B $not$ls180.v:8331$2763_Y - connect \Y $and$ls180.v:8331$2764_Y + connect \A $and$ls180.v:8331$2764_Y + connect \B $not$ls180.v:8331$2765_Y + connect \Y $and$ls180.v:8331$2766_Y end attribute \src "ls180.v:8337.8-8337.75" - cell $and $and$ls180.v:8337$2767 + cell $and $and$ls180.v:8337$2769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268312,21 +268338,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8337$2767_Y + connect \Y $and$ls180.v:8337$2769_Y end attribute \src "ls180.v:8337.7-8337.107" - cell $and $and$ls180.v:8337$2769 + cell $and $and$ls180.v:8337$2771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8337$2767_Y - connect \B $not$ls180.v:8337$2768_Y - connect \Y $and$ls180.v:8337$2769_Y + connect \A $and$ls180.v:8337$2769_Y + connect \B $not$ls180.v:8337$2770_Y + connect \Y $and$ls180.v:8337$2771_Y end attribute \src "ls180.v:8353.8-8353.75" - cell $and $and$ls180.v:8353$2773 + cell $and $and$ls180.v:8353$2775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268334,21 +268360,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8353$2773_Y + connect \Y $and$ls180.v:8353$2775_Y end attribute \src "ls180.v:8353.7-8353.107" - cell $and $and$ls180.v:8353$2775 + cell $and $and$ls180.v:8353$2777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8353$2773_Y - connect \B $not$ls180.v:8353$2774_Y - connect \Y $and$ls180.v:8353$2775_Y + connect \A $and$ls180.v:8353$2775_Y + connect \B $not$ls180.v:8353$2776_Y + connect \Y $and$ls180.v:8353$2777_Y end attribute \src "ls180.v:8359.8-8359.75" - cell $and $and$ls180.v:8359$2778 + cell $and $and$ls180.v:8359$2780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268356,21 +268382,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8359$2778_Y + connect \Y $and$ls180.v:8359$2780_Y end attribute \src "ls180.v:8359.7-8359.107" - cell $and $and$ls180.v:8359$2780 + cell $and $and$ls180.v:8359$2782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8359$2778_Y - connect \B $not$ls180.v:8359$2779_Y - connect \Y $and$ls180.v:8359$2780_Y + connect \A $and$ls180.v:8359$2780_Y + connect \B $not$ls180.v:8359$2781_Y + connect \Y $and$ls180.v:8359$2782_Y end attribute \src "ls180.v:8507.7-8507.96" - cell $and $and$ls180.v:8507$2808 + cell $and $and$ls180.v:8507$2810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268378,10 +268404,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8507$2808_Y + connect \Y $and$ls180.v:8507$2810_Y end attribute \src "ls180.v:8508.8-8508.93" - cell $and $and$ls180.v:8508$2809 + cell $and $and$ls180.v:8508$2811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268389,10 +268415,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8508$2809_Y + connect \Y $and$ls180.v:8508$2811_Y end attribute \src "ls180.v:8516.8-8516.93" - cell $and $and$ls180.v:8516$2810 + cell $and $and$ls180.v:8516$2812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268400,10 +268426,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8516$2810_Y + connect \Y $and$ls180.v:8516$2812_Y end attribute \src "ls180.v:8588.7-8588.98" - cell $and $and$ls180.v:8588$2820 + cell $and $and$ls180.v:8588$2822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268411,10 +268437,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8588$2820_Y + connect \Y $and$ls180.v:8588$2822_Y end attribute \src "ls180.v:8589.8-8589.95" - cell $and $and$ls180.v:8589$2821 + cell $and $and$ls180.v:8589$2823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268422,10 +268448,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8589$2821_Y + connect \Y $and$ls180.v:8589$2823_Y end attribute \src "ls180.v:8597.8-8597.95" - cell $and $and$ls180.v:8597$2822 + cell $and $and$ls180.v:8597$2824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268433,10 +268459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8597$2822_Y + connect \Y $and$ls180.v:8597$2824_Y end attribute \src "ls180.v:8667.7-8667.100" - cell $and $and$ls180.v:8667$2832 + cell $and $and$ls180.v:8667$2834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268444,10 +268470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8667$2832_Y + connect \Y $and$ls180.v:8667$2834_Y end attribute \src "ls180.v:8668.8-8668.97" - cell $and $and$ls180.v:8668$2833 + cell $and $and$ls180.v:8668$2835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268455,10 +268481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8668$2833_Y + connect \Y $and$ls180.v:8668$2835_Y end attribute \src "ls180.v:8676.8-8676.97" - cell $and $and$ls180.v:8676$2834 + cell $and $and$ls180.v:8676$2836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268466,10 +268492,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8676$2834_Y + connect \Y $and$ls180.v:8676$2836_Y end attribute \src "ls180.v:8767.7-8767.82" - cell $and $and$ls180.v:8767$2840 + cell $and $and$ls180.v:8767$2842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268477,10 +268503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8767$2840_Y + connect \Y $and$ls180.v:8767$2842_Y end attribute \src "ls180.v:8770.7-8770.82" - cell $and $and$ls180.v:8770$2841 + cell $and $and$ls180.v:8770$2843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268488,10 +268514,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8770$2841_Y + connect \Y $and$ls180.v:8770$2843_Y end attribute \src "ls180.v:8773.7-8773.82" - cell $and $and$ls180.v:8773$2842 + cell $and $and$ls180.v:8773$2844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268499,10 +268525,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8773$2842_Y + connect \Y $and$ls180.v:8773$2844_Y end attribute \src "ls180.v:8776.7-8776.82" - cell $and $and$ls180.v:8776$2843 + cell $and $and$ls180.v:8776$2845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268510,10 +268536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8776$2843_Y + connect \Y $and$ls180.v:8776$2845_Y end attribute \src "ls180.v:8779.7-8779.82" - cell $and $and$ls180.v:8779$2844 + cell $and $and$ls180.v:8779$2846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268521,10 +268547,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8779$2844_Y + connect \Y $and$ls180.v:8779$2846_Y end attribute \src "ls180.v:8784.7-8784.82" - cell $and $and$ls180.v:8784$2845 + cell $and $and$ls180.v:8784$2847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268532,10 +268558,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8784$2845_Y + connect \Y $and$ls180.v:8784$2847_Y end attribute \src "ls180.v:8789.7-8789.82" - cell $and $and$ls180.v:8789$2846 + cell $and $and$ls180.v:8789$2848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268543,10 +268569,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8789$2846_Y + connect \Y $and$ls180.v:8789$2848_Y end attribute \src "ls180.v:8794.7-8794.82" - cell $and $and$ls180.v:8794$2847 + cell $and $and$ls180.v:8794$2849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268554,10 +268580,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8794$2847_Y + connect \Y $and$ls180.v:8794$2849_Y end attribute \src "ls180.v:8799.7-8799.82" - cell $and $and$ls180.v:8799$2848 + cell $and $and$ls180.v:8799$2850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268565,10 +268591,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8799$2848_Y + connect \Y $and$ls180.v:8799$2850_Y end attribute \src "ls180.v:8864.8-8864.83" - cell $and $and$ls180.v:8864$2851 + cell $and $and$ls180.v:8864$2853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268576,21 +268602,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8864$2851_Y + connect \Y $and$ls180.v:8864$2853_Y end attribute \src "ls180.v:8864.7-8864.119" - cell $and $and$ls180.v:8864$2853 + cell $and $and$ls180.v:8864$2855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8864$2851_Y - connect \B $not$ls180.v:8864$2852_Y - connect \Y $and$ls180.v:8864$2853_Y + connect \A $and$ls180.v:8864$2853_Y + connect \B $not$ls180.v:8864$2854_Y + connect \Y $and$ls180.v:8864$2855_Y end attribute \src "ls180.v:8870.8-8870.83" - cell $and $and$ls180.v:8870$2856 + cell $and $and$ls180.v:8870$2858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268598,21 +268624,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8870$2856_Y + connect \Y $and$ls180.v:8870$2858_Y end attribute \src "ls180.v:8870.7-8870.119" - cell $and $and$ls180.v:8870$2858 + cell $and $and$ls180.v:8870$2860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8870$2856_Y - connect \B $not$ls180.v:8870$2857_Y - connect \Y $and$ls180.v:8870$2858_Y + connect \A $and$ls180.v:8870$2858_Y + connect \B $not$ls180.v:8870$2859_Y + connect \Y $and$ls180.v:8870$2860_Y end attribute \src "ls180.v:8890.7-8890.88" - cell $and $and$ls180.v:8890$2865 + cell $and $and$ls180.v:8890$2867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268620,10 +268646,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8890$2865_Y + connect \Y $and$ls180.v:8890$2867_Y end attribute \src "ls180.v:8891.8-8891.85" - cell $and $and$ls180.v:8891$2866 + cell $and $and$ls180.v:8891$2868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268631,10 +268657,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8891$2866_Y + connect \Y $and$ls180.v:8891$2868_Y end attribute \src "ls180.v:8899.8-8899.85" - cell $and $and$ls180.v:8899$2867 + cell $and $and$ls180.v:8899$2869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268642,10 +268668,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8899$2867_Y + connect \Y $and$ls180.v:8899$2869_Y end attribute \src "ls180.v:8955.7-8955.88" - cell $and $and$ls180.v:8955$2871 + cell $and $and$ls180.v:8955$2873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268653,10 +268679,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8955$2871_Y + connect \Y $and$ls180.v:8955$2873_Y end attribute \src "ls180.v:8962.8-8962.83" - cell $and $and$ls180.v:8962$2873 + cell $and $and$ls180.v:8962$2875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268664,21 +268690,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8962$2873_Y + connect \Y $and$ls180.v:8962$2875_Y end attribute \src "ls180.v:8962.7-8962.119" - cell $and $and$ls180.v:8962$2875 + cell $and $and$ls180.v:8962$2877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8962$2873_Y - connect \B $not$ls180.v:8962$2874_Y - connect \Y $and$ls180.v:8962$2875_Y + connect \A $and$ls180.v:8962$2875_Y + connect \B $not$ls180.v:8962$2876_Y + connect \Y $and$ls180.v:8962$2877_Y end attribute \src "ls180.v:8968.8-8968.83" - cell $and $and$ls180.v:8968$2878 + cell $and $and$ls180.v:8968$2880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268686,18 +268712,18 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8968$2878_Y + connect \Y $and$ls180.v:8968$2880_Y end attribute \src "ls180.v:8968.7-8968.119" - cell $and $and$ls180.v:8968$2880 + cell $and $and$ls180.v:8968$2882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8968$2878_Y - connect \B $not$ls180.v:8968$2879_Y - connect \Y $and$ls180.v:8968$2880_Y + connect \A $and$ls180.v:8968$2880_Y + connect \B $not$ls180.v:8968$2881_Y + connect \Y $and$ls180.v:8968$2882_Y end attribute \src "ls180.v:2930.30-2930.76" cell $eq $eq$ls180.v:2930$54 @@ -274266,7 +274292,7 @@ module \ls180 connect \Y $eq$ls180.v:7189$2514_Y end attribute \src "ls180.v:7773.8-7773.38" - cell $eq $eq$ls180.v:7773$2606 + cell $eq $eq$ls180.v:7773$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274274,10 +274300,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7773$2606_Y + connect \Y $eq$ls180.v:7773$2608_Y end attribute \src "ls180.v:7820.8-7820.42" - cell $eq $eq$ls180.v:7820$2626 + cell $eq $eq$ls180.v:7820$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274285,10 +274311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7820$2626_Y + connect \Y $eq$ls180.v:7820$2628_Y end attribute \src "ls180.v:7840.38-7840.74" - cell $eq $eq$ls180.v:7840$2629 + cell $eq $eq$ls180.v:7840$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274296,10 +274322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7840$2629_Y + connect \Y $eq$ls180.v:7840$2631_Y end attribute \src "ls180.v:7847.7-7847.43" - cell $eq $eq$ls180.v:7847$2631 + cell $eq $eq$ls180.v:7847$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274307,10 +274333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7847$2631_Y + connect \Y $eq$ls180.v:7847$2633_Y end attribute \src "ls180.v:7854.7-7854.43" - cell $eq $eq$ls180.v:7854$2632 + cell $eq $eq$ls180.v:7854$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274318,10 +274344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7854$2632_Y + connect \Y $eq$ls180.v:7854$2634_Y end attribute \src "ls180.v:7862.7-7862.43" - cell $eq $eq$ls180.v:7862$2633 + cell $eq $eq$ls180.v:7862$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274329,10 +274355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7862$2633_Y + connect \Y $eq$ls180.v:7862$2635_Y end attribute \src "ls180.v:7914.9-7914.54" - cell $eq $eq$ls180.v:7914$2651 + cell $eq $eq$ls180.v:7914$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274340,10 +274366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7914$2651_Y + connect \Y $eq$ls180.v:7914$2653_Y end attribute \src "ls180.v:7960.9-7960.54" - cell $eq $eq$ls180.v:7960$2667 + cell $eq $eq$ls180.v:7960$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274351,10 +274377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7960$2667_Y + connect \Y $eq$ls180.v:7960$2669_Y end attribute \src "ls180.v:8006.9-8006.54" - cell $eq $eq$ls180.v:8006$2683 + cell $eq $eq$ls180.v:8006$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274362,10 +274388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8006$2683_Y + connect \Y $eq$ls180.v:8006$2685_Y end attribute \src "ls180.v:8052.9-8052.54" - cell $eq $eq$ls180.v:8052$2699 + cell $eq $eq$ls180.v:8052$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274373,10 +274399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8052$2699_Y + connect \Y $eq$ls180.v:8052$2701_Y end attribute \src "ls180.v:8202.9-8202.41" - cell $eq $eq$ls180.v:8202$2711 + cell $eq $eq$ls180.v:8202$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274384,10 +274410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8202$2711_Y + connect \Y $eq$ls180.v:8202$2713_Y end attribute \src "ls180.v:8217.9-8217.41" - cell $eq $eq$ls180.v:8217$2714 + cell $eq $eq$ls180.v:8217$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274395,10 +274421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8217$2714_Y + connect \Y $eq$ls180.v:8217$2716_Y end attribute \src "ls180.v:8223.49-8223.82" - cell $eq $eq$ls180.v:8223$2715 + cell $eq $eq$ls180.v:8223$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274406,10 +274432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2715_Y + connect \Y $eq$ls180.v:8223$2717_Y end attribute \src "ls180.v:8223.131-8223.164" - cell $eq $eq$ls180.v:8223$2718 + cell $eq $eq$ls180.v:8223$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274417,10 +274443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2718_Y + connect \Y $eq$ls180.v:8223$2720_Y end attribute \src "ls180.v:8223.213-8223.246" - cell $eq $eq$ls180.v:8223$2721 + cell $eq $eq$ls180.v:8223$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274428,10 +274454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2721_Y + connect \Y $eq$ls180.v:8223$2723_Y end attribute \src "ls180.v:8223.295-8223.328" - cell $eq $eq$ls180.v:8223$2724 + cell $eq $eq$ls180.v:8223$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274439,10 +274465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2724_Y + connect \Y $eq$ls180.v:8223$2726_Y end attribute \src "ls180.v:8224.50-8224.83" - cell $eq $eq$ls180.v:8224$2727 + cell $eq $eq$ls180.v:8224$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274450,10 +274476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2727_Y + connect \Y $eq$ls180.v:8224$2729_Y end attribute \src "ls180.v:8224.132-8224.165" - cell $eq $eq$ls180.v:8224$2730 + cell $eq $eq$ls180.v:8224$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274461,10 +274487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2730_Y + connect \Y $eq$ls180.v:8224$2732_Y end attribute \src "ls180.v:8224.214-8224.247" - cell $eq $eq$ls180.v:8224$2733 + cell $eq $eq$ls180.v:8224$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274472,10 +274498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2733_Y + connect \Y $eq$ls180.v:8224$2735_Y end attribute \src "ls180.v:8224.296-8224.329" - cell $eq $eq$ls180.v:8224$2736 + cell $eq $eq$ls180.v:8224$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274483,10 +274509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2736_Y + connect \Y $eq$ls180.v:8224$2738_Y end attribute \src "ls180.v:8259.9-8259.42" - cell $eq $eq$ls180.v:8259$2748 + cell $eq $eq$ls180.v:8259$2750 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274494,10 +274520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:8259$2748_Y + connect \Y $eq$ls180.v:8259$2750_Y end attribute \src "ls180.v:8262.10-8262.43" - cell $eq $eq$ls180.v:8262$2749 + cell $eq $eq$ls180.v:8262$2751 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274505,10 +274531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8262$2749_Y + connect \Y $eq$ls180.v:8262$2751_Y end attribute \src "ls180.v:8288.9-8288.42" - cell $eq $eq$ls180.v:8288$2755 + cell $eq $eq$ls180.v:8288$2757 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274516,10 +274542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:8288$2755_Y + connect \Y $eq$ls180.v:8288$2757_Y end attribute \src "ls180.v:8293.10-8293.43" - cell $eq $eq$ls180.v:8293$2756 + cell $eq $eq$ls180.v:8293$2758 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274527,10 +274553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8293$2756_Y + connect \Y $eq$ls180.v:8293$2758_Y end attribute \src "ls180.v:8500.9-8500.53" - cell $eq $eq$ls180.v:8500$2805 + cell $eq $eq$ls180.v:8500$2807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274538,10 +274564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8500$2805_Y + connect \Y $eq$ls180.v:8500$2807_Y end attribute \src "ls180.v:8581.9-8581.54" - cell $eq $eq$ls180.v:8581$2817 + cell $eq $eq$ls180.v:8581$2819 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274549,10 +274575,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8581$2817_Y + connect \Y $eq$ls180.v:8581$2819_Y end attribute \src "ls180.v:8660.9-8660.55" - cell $eq $eq$ls180.v:8660$2829 + cell $eq $eq$ls180.v:8660$2831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274560,10 +274586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8660$2829_Y + connect \Y $eq$ls180.v:8660$2831_Y end attribute \src "ls180.v:8883.9-8883.49" - cell $eq $eq$ls180.v:8883$2862 + cell $eq $eq$ls180.v:8883$2864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274571,29 +274597,29 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8883$2862_Y + connect \Y $eq$ls180.v:8883$2864_Y end attribute \src "ls180.v:8459.8-8459.54" - cell $ge $ge$ls180.v:8459$2797 + cell $ge $ge$ls180.v:8459$2799 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8459$2796_Y - connect \Y $ge$ls180.v:8459$2797_Y + connect \B $sub$ls180.v:8459$2798_Y + connect \Y $ge$ls180.v:8459$2799_Y end attribute \src "ls180.v:8473.8-8473.54" - cell $ge $ge$ls180.v:8473$2801 + cell $ge $ge$ls180.v:8473$2803 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8473$2800_Y - connect \Y $ge$ls180.v:8473$2801_Y + connect \B $sub$ls180.v:8473$2802_Y + connect \Y $ge$ls180.v:8473$2803_Y end attribute \src "ls180.v:5342.47-5342.83" cell $gt $gt$ls180.v:5342$1064 @@ -274618,7 +274644,7 @@ module \ls180 connect \Y $lt$ls180.v:5348$1067_Y end attribute \src "ls180.v:8454.8-8454.43" - cell $lt $lt$ls180.v:8454$2795 + cell $lt $lt$ls180.v:8454$2797 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274626,10 +274652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8454$2795_Y + connect \Y $lt$ls180.v:8454$2797_Y end attribute \src "ls180.v:8468.8-8468.43" - cell $lt $lt$ls180.v:8468$2799 + cell $lt $lt$ls180.v:8468$2801 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274637,10 +274663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8468$2799_Y + connect \Y $lt$ls180.v:8468$2801_Y end attribute \src "ls180.v:10373.33-10373.36" - cell $memrd $memrd$\mem$ls180.v:10373$2916 + cell $memrd $memrd$\mem$ls180.v:10373$2918 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274649,11 +274675,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10373$2916_DATA + connect \DATA $memrd$\mem$ls180.v:10373$2918_DATA connect \EN 1'x end attribute \src "ls180.v:10401.27-10401.32" - cell $memrd $memrd$\mem_1$ls180.v:10401$2942 + cell $memrd $memrd$\mem_1$ls180.v:10401$2944 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274662,11 +274688,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10401$2942_DATA + connect \DATA $memrd$\mem_1$ls180.v:10401$2944_DATA connect \EN 1'x end attribute \src "ls180.v:10429.27-10429.32" - cell $memrd $memrd$\mem_2$ls180.v:10429$2968 + cell $memrd $memrd$\mem_2$ls180.v:10429$2970 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274675,11 +274701,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_2 connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10429$2968_DATA + connect \DATA $memrd$\mem_2$ls180.v:10429$2970_DATA connect \EN 1'x end attribute \src "ls180.v:10457.27-10457.32" - cell $memrd $memrd$\mem_3$ls180.v:10457$2994 + cell $memrd $memrd$\mem_3$ls180.v:10457$2996 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274688,11 +274714,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_3 connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10457$2994_DATA + connect \DATA $memrd$\mem_3$ls180.v:10457$2996_DATA connect \EN 1'x end attribute \src "ls180.v:10485.27-10485.32" - cell $memrd $memrd$\mem_4$ls180.v:10485$3020 + cell $memrd $memrd$\mem_4$ls180.v:10485$3022 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274701,11 +274727,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_4 connect \CLK 1'x - connect \DATA $memrd$\mem_4$ls180.v:10485$3020_DATA + connect \DATA $memrd$\mem_4$ls180.v:10485$3022_DATA connect \EN 1'x end attribute \src "ls180.v:10496.12-10496.19" - cell $memrd $memrd$\storage$ls180.v:10496$3025 + cell $memrd $memrd$\storage$ls180.v:10496$3027 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274714,11 +274740,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10496$3025_DATA + connect \DATA $memrd$\storage$ls180.v:10496$3027_DATA connect \EN 1'x end attribute \src "ls180.v:10503.68-10503.75" - cell $memrd $memrd$\storage$ls180.v:10503$3027 + cell $memrd $memrd$\storage$ls180.v:10503$3029 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274727,11 +274753,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10503$3027_DATA + connect \DATA $memrd$\storage$ls180.v:10503$3029_DATA connect \EN 1'x end attribute \src "ls180.v:10510.14-10510.23" - cell $memrd $memrd$\storage_1$ls180.v:10510$3032 + cell $memrd $memrd$\storage_1$ls180.v:10510$3034 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274740,11 +274766,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10510$3032_DATA + connect \DATA $memrd$\storage_1$ls180.v:10510$3034_DATA connect \EN 1'x end attribute \src "ls180.v:10517.68-10517.77" - cell $memrd $memrd$\storage_1$ls180.v:10517$3034 + cell $memrd $memrd$\storage_1$ls180.v:10517$3036 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274753,11 +274779,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10517$3034_DATA + connect \DATA $memrd$\storage_1$ls180.v:10517$3036_DATA connect \EN 1'x end attribute \src "ls180.v:10524.14-10524.23" - cell $memrd $memrd$\storage_2$ls180.v:10524$3039 + cell $memrd $memrd$\storage_2$ls180.v:10524$3041 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274766,11 +274792,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10524$3039_DATA + connect \DATA $memrd$\storage_2$ls180.v:10524$3041_DATA connect \EN 1'x end attribute \src "ls180.v:10531.68-10531.77" - cell $memrd $memrd$\storage_2$ls180.v:10531$3041 + cell $memrd $memrd$\storage_2$ls180.v:10531$3043 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274779,11 +274805,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10531$3041_DATA + connect \DATA $memrd$\storage_2$ls180.v:10531$3043_DATA connect \EN 1'x end attribute \src "ls180.v:10538.14-10538.23" - cell $memrd $memrd$\storage_3$ls180.v:10538$3046 + cell $memrd $memrd$\storage_3$ls180.v:10538$3048 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274792,11 +274818,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10538$3046_DATA + connect \DATA $memrd$\storage_3$ls180.v:10538$3048_DATA connect \EN 1'x end attribute \src "ls180.v:10545.68-10545.77" - cell $memrd $memrd$\storage_3$ls180.v:10545$3048 + cell $memrd $memrd$\storage_3$ls180.v:10545$3050 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274805,11 +274831,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10545$3048_DATA + connect \DATA $memrd$\storage_3$ls180.v:10545$3050_DATA connect \EN 1'x end attribute \src "ls180.v:10553.14-10553.23" - cell $memrd $memrd$\storage_4$ls180.v:10553$3053 + cell $memrd $memrd$\storage_4$ls180.v:10553$3055 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274818,11 +274844,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10553$3053_DATA + connect \DATA $memrd$\storage_4$ls180.v:10553$3055_DATA connect \EN 1'x end attribute \src "ls180.v:10558.15-10558.24" - cell $memrd $memrd$\storage_4$ls180.v:10558$3055 + cell $memrd $memrd$\storage_4$ls180.v:10558$3057 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274831,11 +274857,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10558$3055_DATA + connect \DATA $memrd$\storage_4$ls180.v:10558$3057_DATA connect \EN 1'x end attribute \src "ls180.v:10570.14-10570.23" - cell $memrd $memrd$\storage_5$ls180.v:10570$3060 + cell $memrd $memrd$\storage_5$ls180.v:10570$3062 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274844,11 +274870,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10570$3060_DATA + connect \DATA $memrd$\storage_5$ls180.v:10570$3062_DATA connect \EN 1'x end attribute \src "ls180.v:10575.15-10575.24" - cell $memrd $memrd$\storage_5$ls180.v:10575$3062 + cell $memrd $memrd$\storage_5$ls180.v:10575$3064 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274857,11 +274883,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10575$3062_DATA + connect \DATA $memrd$\storage_5$ls180.v:10575$3064_DATA connect \EN 1'x end attribute \src "ls180.v:10586.14-10586.23" - cell $memrd $memrd$\storage_6$ls180.v:10586$3067 + cell $memrd $memrd$\storage_6$ls180.v:10586$3069 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274870,11 +274896,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10586$3067_DATA + connect \DATA $memrd$\storage_6$ls180.v:10586$3069_DATA connect \EN 1'x end attribute \src "ls180.v:10593.45-10593.54" - cell $memrd $memrd$\storage_6$ls180.v:10593$3069 + cell $memrd $memrd$\storage_6$ls180.v:10593$3071 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274883,11 +274909,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10593$3069_DATA + connect \DATA $memrd$\storage_6$ls180.v:10593$3071_DATA connect \EN 1'x end attribute \src "ls180.v:10600.14-10600.23" - cell $memrd $memrd$\storage_7$ls180.v:10600$3074 + cell $memrd $memrd$\storage_7$ls180.v:10600$3076 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274896,11 +274922,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10600$3074_DATA + connect \DATA $memrd$\storage_7$ls180.v:10600$3076_DATA connect \EN 1'x end attribute \src "ls180.v:10607.45-10607.54" - cell $memrd $memrd$\storage_7$ls180.v:10607$3076 + cell $memrd $memrd$\storage_7$ls180.v:10607$3078 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274909,16 +274935,16 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10607$3076_DATA + connect \DATA $memrd$\storage_7$ls180.v:10607$3078_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3078 + cell $memwr $memwr$\mem$ls180.v:0$3080 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3078 + parameter \PRIORITY 3080 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10355$1_ADDR connect \CLK 1'x @@ -274926,12 +274952,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10355$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3079 + cell $memwr $memwr$\mem$ls180.v:0$3081 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3079 + parameter \PRIORITY 3081 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10357$2_ADDR connect \CLK 1'x @@ -274939,12 +274965,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10357$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3080 + cell $memwr $memwr$\mem$ls180.v:0$3082 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3080 + parameter \PRIORITY 3082 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10359$3_ADDR connect \CLK 1'x @@ -274952,12 +274978,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10359$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3081 + cell $memwr $memwr$\mem$ls180.v:0$3083 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3081 + parameter \PRIORITY 3083 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10361$4_ADDR connect \CLK 1'x @@ -274965,12 +274991,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10361$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3082 + cell $memwr $memwr$\mem$ls180.v:0$3084 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3082 + parameter \PRIORITY 3084 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10363$5_ADDR connect \CLK 1'x @@ -274978,12 +275004,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10363$5_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3083 + cell $memwr $memwr$\mem$ls180.v:0$3085 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3083 + parameter \PRIORITY 3085 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10365$6_ADDR connect \CLK 1'x @@ -274991,12 +275017,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10365$6_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3084 + cell $memwr $memwr$\mem$ls180.v:0$3086 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3084 + parameter \PRIORITY 3086 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10367$7_ADDR connect \CLK 1'x @@ -275004,12 +275030,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10367$7_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3085 + cell $memwr $memwr$\mem$ls180.v:0$3087 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3085 + parameter \PRIORITY 3087 parameter \WIDTH 64 connect \ADDR $memwr$\mem$ls180.v:10369$8_ADDR connect \CLK 1'x @@ -275017,12 +275043,12 @@ module \ls180 connect \EN $memwr$\mem$ls180.v:10369$8_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3086 + cell $memwr $memwr$\mem_1$ls180.v:0$3088 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3086 + parameter \PRIORITY 3088 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10383$9_ADDR connect \CLK 1'x @@ -275030,12 +275056,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10383$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3087 + cell $memwr $memwr$\mem_1$ls180.v:0$3089 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3087 + parameter \PRIORITY 3089 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10385$10_ADDR connect \CLK 1'x @@ -275043,12 +275069,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10385$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3088 + cell $memwr $memwr$\mem_1$ls180.v:0$3090 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3088 + parameter \PRIORITY 3090 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10387$11_ADDR connect \CLK 1'x @@ -275056,12 +275082,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10387$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3089 + cell $memwr $memwr$\mem_1$ls180.v:0$3091 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3089 + parameter \PRIORITY 3091 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10389$12_ADDR connect \CLK 1'x @@ -275069,12 +275095,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10389$12_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3090 + cell $memwr $memwr$\mem_1$ls180.v:0$3092 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3090 + parameter \PRIORITY 3092 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10391$13_ADDR connect \CLK 1'x @@ -275082,12 +275108,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10391$13_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3091 + cell $memwr $memwr$\mem_1$ls180.v:0$3093 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3091 + parameter \PRIORITY 3093 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10393$14_ADDR connect \CLK 1'x @@ -275095,12 +275121,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10393$14_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3092 + cell $memwr $memwr$\mem_1$ls180.v:0$3094 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3092 + parameter \PRIORITY 3094 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10395$15_ADDR connect \CLK 1'x @@ -275108,12 +275134,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10395$15_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3093 + cell $memwr $memwr$\mem_1$ls180.v:0$3095 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3093 + parameter \PRIORITY 3095 parameter \WIDTH 64 connect \ADDR $memwr$\mem_1$ls180.v:10397$16_ADDR connect \CLK 1'x @@ -275121,12 +275147,12 @@ module \ls180 connect \EN $memwr$\mem_1$ls180.v:10397$16_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3094 + cell $memwr $memwr$\mem_2$ls180.v:0$3096 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3094 + parameter \PRIORITY 3096 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10411$17_ADDR connect \CLK 1'x @@ -275134,12 +275160,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10411$17_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3095 + cell $memwr $memwr$\mem_2$ls180.v:0$3097 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3095 + parameter \PRIORITY 3097 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10413$18_ADDR connect \CLK 1'x @@ -275147,12 +275173,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10413$18_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3096 + cell $memwr $memwr$\mem_2$ls180.v:0$3098 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3096 + parameter \PRIORITY 3098 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10415$19_ADDR connect \CLK 1'x @@ -275160,12 +275186,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10415$19_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3097 + cell $memwr $memwr$\mem_2$ls180.v:0$3099 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3097 + parameter \PRIORITY 3099 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10417$20_ADDR connect \CLK 1'x @@ -275173,12 +275199,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10417$20_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3098 + cell $memwr $memwr$\mem_2$ls180.v:0$3100 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3098 + parameter \PRIORITY 3100 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10419$21_ADDR connect \CLK 1'x @@ -275186,12 +275212,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10419$21_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3099 + cell $memwr $memwr$\mem_2$ls180.v:0$3101 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3099 + parameter \PRIORITY 3101 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10421$22_ADDR connect \CLK 1'x @@ -275199,12 +275225,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10421$22_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3100 + cell $memwr $memwr$\mem_2$ls180.v:0$3102 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3100 + parameter \PRIORITY 3102 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10423$23_ADDR connect \CLK 1'x @@ -275212,12 +275238,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10423$23_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3101 + cell $memwr $memwr$\mem_2$ls180.v:0$3103 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 3101 + parameter \PRIORITY 3103 parameter \WIDTH 64 connect \ADDR $memwr$\mem_2$ls180.v:10425$24_ADDR connect \CLK 1'x @@ -275225,12 +275251,12 @@ module \ls180 connect \EN $memwr$\mem_2$ls180.v:10425$24_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3102 + cell $memwr $memwr$\mem_3$ls180.v:0$3104 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3102 + parameter \PRIORITY 3104 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10439$25_ADDR connect \CLK 1'x @@ -275238,12 +275264,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10439$25_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3103 + cell $memwr $memwr$\mem_3$ls180.v:0$3105 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3103 + parameter \PRIORITY 3105 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10441$26_ADDR connect \CLK 1'x @@ -275251,12 +275277,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10441$26_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3104 + cell $memwr $memwr$\mem_3$ls180.v:0$3106 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3104 + parameter \PRIORITY 3106 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10443$27_ADDR connect \CLK 1'x @@ -275264,12 +275290,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10443$27_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3105 + cell $memwr $memwr$\mem_3$ls180.v:0$3107 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3105 + parameter \PRIORITY 3107 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10445$28_ADDR connect \CLK 1'x @@ -275277,12 +275303,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10445$28_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3106 + cell $memwr $memwr$\mem_3$ls180.v:0$3108 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3106 + parameter \PRIORITY 3108 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10447$29_ADDR connect \CLK 1'x @@ -275290,12 +275316,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10447$29_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3107 + cell $memwr $memwr$\mem_3$ls180.v:0$3109 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3107 + parameter \PRIORITY 3109 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10449$30_ADDR connect \CLK 1'x @@ -275303,12 +275329,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10449$30_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3108 + cell $memwr $memwr$\mem_3$ls180.v:0$3110 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3108 + parameter \PRIORITY 3110 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10451$31_ADDR connect \CLK 1'x @@ -275316,12 +275342,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10451$31_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3109 + cell $memwr $memwr$\mem_3$ls180.v:0$3111 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 3109 + parameter \PRIORITY 3111 parameter \WIDTH 64 connect \ADDR $memwr$\mem_3$ls180.v:10453$32_ADDR connect \CLK 1'x @@ -275329,12 +275355,12 @@ module \ls180 connect \EN $memwr$\mem_3$ls180.v:10453$32_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3110 + cell $memwr $memwr$\mem_4$ls180.v:0$3112 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3110 + parameter \PRIORITY 3112 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10467$33_ADDR connect \CLK 1'x @@ -275342,12 +275368,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10467$33_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3111 + cell $memwr $memwr$\mem_4$ls180.v:0$3113 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3111 + parameter \PRIORITY 3113 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10469$34_ADDR connect \CLK 1'x @@ -275355,12 +275381,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10469$34_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3112 + cell $memwr $memwr$\mem_4$ls180.v:0$3114 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3112 + parameter \PRIORITY 3114 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10471$35_ADDR connect \CLK 1'x @@ -275368,12 +275394,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10471$35_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3113 + cell $memwr $memwr$\mem_4$ls180.v:0$3115 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3113 + parameter \PRIORITY 3115 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10473$36_ADDR connect \CLK 1'x @@ -275381,12 +275407,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10473$36_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3114 + cell $memwr $memwr$\mem_4$ls180.v:0$3116 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3114 + parameter \PRIORITY 3116 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10475$37_ADDR connect \CLK 1'x @@ -275394,12 +275420,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10475$37_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3115 + cell $memwr $memwr$\mem_4$ls180.v:0$3117 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3115 + parameter \PRIORITY 3117 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10477$38_ADDR connect \CLK 1'x @@ -275407,12 +275433,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10477$38_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3116 + cell $memwr $memwr$\mem_4$ls180.v:0$3118 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3116 + parameter \PRIORITY 3118 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10479$39_ADDR connect \CLK 1'x @@ -275420,12 +275446,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10479$39_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3117 + cell $memwr $memwr$\mem_4$ls180.v:0$3119 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_4" - parameter \PRIORITY 3117 + parameter \PRIORITY 3119 parameter \WIDTH 64 connect \ADDR $memwr$\mem_4$ls180.v:10481$40_ADDR connect \CLK 1'x @@ -275433,12 +275459,12 @@ module \ls180 connect \EN $memwr$\mem_4$ls180.v:10481$40_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$3118 + cell $memwr $memwr$\storage$ls180.v:0$3120 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 3118 + parameter \PRIORITY 3120 parameter \WIDTH 25 connect \ADDR $memwr$\storage$ls180.v:10495$41_ADDR connect \CLK 1'x @@ -275446,12 +275472,12 @@ module \ls180 connect \EN $memwr$\storage$ls180.v:10495$41_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$3119 + cell $memwr $memwr$\storage_1$ls180.v:0$3121 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 3119 + parameter \PRIORITY 3121 parameter \WIDTH 25 connect \ADDR $memwr$\storage_1$ls180.v:10509$42_ADDR connect \CLK 1'x @@ -275459,12 +275485,12 @@ module \ls180 connect \EN $memwr$\storage_1$ls180.v:10509$42_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$3120 + cell $memwr $memwr$\storage_2$ls180.v:0$3122 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 3120 + parameter \PRIORITY 3122 parameter \WIDTH 25 connect \ADDR $memwr$\storage_2$ls180.v:10523$43_ADDR connect \CLK 1'x @@ -275472,12 +275498,12 @@ module \ls180 connect \EN $memwr$\storage_2$ls180.v:10523$43_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$3121 + cell $memwr $memwr$\storage_3$ls180.v:0$3123 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 3121 + parameter \PRIORITY 3123 parameter \WIDTH 25 connect \ADDR $memwr$\storage_3$ls180.v:10537$44_ADDR connect \CLK 1'x @@ -275485,12 +275511,12 @@ module \ls180 connect \EN $memwr$\storage_3$ls180.v:10537$44_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$3122 + cell $memwr $memwr$\storage_4$ls180.v:0$3124 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 3122 + parameter \PRIORITY 3124 parameter \WIDTH 10 connect \ADDR $memwr$\storage_4$ls180.v:10552$45_ADDR connect \CLK 1'x @@ -275498,12 +275524,12 @@ module \ls180 connect \EN $memwr$\storage_4$ls180.v:10552$45_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$3123 + cell $memwr $memwr$\storage_5$ls180.v:0$3125 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 3123 + parameter \PRIORITY 3125 parameter \WIDTH 10 connect \ADDR $memwr$\storage_5$ls180.v:10569$46_ADDR connect \CLK 1'x @@ -275511,12 +275537,12 @@ module \ls180 connect \EN $memwr$\storage_5$ls180.v:10569$46_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$3124 + cell $memwr $memwr$\storage_6$ls180.v:0$3126 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 3124 + parameter \PRIORITY 3126 parameter \WIDTH 10 connect \ADDR $memwr$\storage_6$ls180.v:10585$47_ADDR connect \CLK 1'x @@ -275524,12 +275550,12 @@ module \ls180 connect \EN $memwr$\storage_6$ls180.v:10585$47_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$3125 + cell $memwr $memwr$\storage_7$ls180.v:0$3127 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 3125 + parameter \PRIORITY 3127 parameter \WIDTH 10 connect \ADDR $memwr$\storage_7$ls180.v:10599$48_ADDR connect \CLK 1'x @@ -275812,7 +275838,7 @@ module \ls180 connect \Y $ne$ls180.v:5878$1177_Y end attribute \src "ls180.v:7763.7-7763.52" - cell $ne $ne$ls180.v:7763$2601 + cell $ne $ne$ls180.v:7763$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -275820,10 +275846,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7763$2601_Y + connect \Y $ne$ls180.v:7763$2603_Y end attribute \src "ls180.v:7829.9-7829.43" - cell $ne $ne$ls180.v:7829$2627 + cell $ne $ne$ls180.v:7829$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275831,10 +275857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7829$2627_Y + connect \Y $ne$ls180.v:7829$2629_Y end attribute \src "ls180.v:7865.8-7865.44" - cell $ne $ne$ls180.v:7865$2634 + cell $ne $ne$ls180.v:7865$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275842,10 +275868,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7865$2634_Y + connect \Y $ne$ls180.v:7865$2636_Y end attribute \src "ls180.v:8803.9-8803.47" - cell $ne $ne$ls180.v:8803$2849 + cell $ne $ne$ls180.v:8803$2851 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275853,7 +275879,7 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8803$2849_Y + connect \Y $ne$ls180.v:8803$2851_Y end attribute \src "ls180.v:2893.33-2893.73" cell $not $not$ls180.v:2893$50 @@ -278032,559 +278058,559 @@ module \ls180 connect \Y $not$ls180.v:7189$2517_Y end attribute \src "ls180.v:7690.18-7690.42" - cell $not $not$ls180.v:7690$2571 + cell $not $not$ls180.v:7690$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7690$2571_Y + connect \Y $not$ls180.v:7690$2573_Y end attribute \src "ls180.v:7769.72-7769.101" - cell $not $not$ls180.v:7769$2604 + cell $not $not$ls180.v:7769$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7769$2604_Y + connect \Y $not$ls180.v:7769$2606_Y end attribute \src "ls180.v:7788.8-7788.38" - cell $not $not$ls180.v:7788$2608 + cell $not $not$ls180.v:7788$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7788$2608_Y + connect \Y $not$ls180.v:7788$2610_Y end attribute \src "ls180.v:7792.70-7792.98" - cell $not $not$ls180.v:7792$2611 + cell $not $not$ls180.v:7792$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7792$2611_Y + connect \Y $not$ls180.v:7792$2613_Y end attribute \src "ls180.v:7796.70-7796.98" - cell $not $not$ls180.v:7796$2614 + cell $not $not$ls180.v:7796$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7796$2614_Y + connect \Y $not$ls180.v:7796$2616_Y end attribute \src "ls180.v:7800.70-7800.98" - cell $not $not$ls180.v:7800$2617 + cell $not $not$ls180.v:7800$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7800$2617_Y + connect \Y $not$ls180.v:7800$2619_Y end attribute \src "ls180.v:7804.70-7804.98" - cell $not $not$ls180.v:7804$2620 + cell $not $not$ls180.v:7804$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_ack - connect \Y $not$ls180.v:7804$2620_Y + connect \Y $not$ls180.v:7804$2622_Y end attribute \src "ls180.v:7812.32-7812.55" - cell $not $not$ls180.v:7812$2622 + cell $not $not$ls180.v:7812$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7812$2622_Y + connect \Y $not$ls180.v:7812$2624_Y end attribute \src "ls180.v:7882.136-7882.189" - cell $not $not$ls180.v:7882$2637 + cell $not $not$ls180.v:7882$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7882$2637_Y + connect \Y $not$ls180.v:7882$2639_Y end attribute \src "ls180.v:7888.136-7888.189" - cell $not $not$ls180.v:7888$2642 + cell $not $not$ls180.v:7888$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7888$2642_Y + connect \Y $not$ls180.v:7888$2644_Y end attribute \src "ls180.v:7889.8-7889.61" - cell $not $not$ls180.v:7889$2644 + cell $not $not$ls180.v:7889$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7889$2644_Y + connect \Y $not$ls180.v:7889$2646_Y end attribute \src "ls180.v:7897.8-7897.56" - cell $not $not$ls180.v:7897$2647 + cell $not $not$ls180.v:7897$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7897$2647_Y + connect \Y $not$ls180.v:7897$2649_Y end attribute \src "ls180.v:7912.8-7912.46" - cell $not $not$ls180.v:7912$2649 + cell $not $not$ls180.v:7912$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7912$2649_Y + connect \Y $not$ls180.v:7912$2651_Y end attribute \src "ls180.v:7928.136-7928.189" - cell $not $not$ls180.v:7928$2653 + cell $not $not$ls180.v:7928$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7928$2653_Y + connect \Y $not$ls180.v:7928$2655_Y end attribute \src "ls180.v:7934.136-7934.189" - cell $not $not$ls180.v:7934$2658 + cell $not $not$ls180.v:7934$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7934$2658_Y + connect \Y $not$ls180.v:7934$2660_Y end attribute \src "ls180.v:7935.8-7935.61" - cell $not $not$ls180.v:7935$2660 + cell $not $not$ls180.v:7935$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7935$2660_Y + connect \Y $not$ls180.v:7935$2662_Y end attribute \src "ls180.v:7943.8-7943.56" - cell $not $not$ls180.v:7943$2663 + cell $not $not$ls180.v:7943$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7943$2663_Y + connect \Y $not$ls180.v:7943$2665_Y end attribute \src "ls180.v:7958.8-7958.46" - cell $not $not$ls180.v:7958$2665 + cell $not $not$ls180.v:7958$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7958$2665_Y + connect \Y $not$ls180.v:7958$2667_Y end attribute \src "ls180.v:7974.136-7974.189" - cell $not $not$ls180.v:7974$2669 + cell $not $not$ls180.v:7974$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7974$2669_Y + connect \Y $not$ls180.v:7974$2671_Y end attribute \src "ls180.v:7980.136-7980.189" - cell $not $not$ls180.v:7980$2674 + cell $not $not$ls180.v:7980$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7980$2674_Y + connect \Y $not$ls180.v:7980$2676_Y end attribute \src "ls180.v:7981.8-7981.61" - cell $not $not$ls180.v:7981$2676 + cell $not $not$ls180.v:7981$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7981$2676_Y + connect \Y $not$ls180.v:7981$2678_Y end attribute \src "ls180.v:7989.8-7989.56" - cell $not $not$ls180.v:7989$2679 + cell $not $not$ls180.v:7989$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7989$2679_Y + connect \Y $not$ls180.v:7989$2681_Y end attribute \src "ls180.v:8004.8-8004.46" - cell $not $not$ls180.v:8004$2681 + cell $not $not$ls180.v:8004$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:8004$2681_Y + connect \Y $not$ls180.v:8004$2683_Y end attribute \src "ls180.v:8020.136-8020.189" - cell $not $not$ls180.v:8020$2685 + cell $not $not$ls180.v:8020$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8020$2685_Y + connect \Y $not$ls180.v:8020$2687_Y end attribute \src "ls180.v:8026.136-8026.189" - cell $not $not$ls180.v:8026$2690 + cell $not $not$ls180.v:8026$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8026$2690_Y + connect \Y $not$ls180.v:8026$2692_Y end attribute \src "ls180.v:8027.8-8027.61" - cell $not $not$ls180.v:8027$2692 + cell $not $not$ls180.v:8027$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:8027$2692_Y + connect \Y $not$ls180.v:8027$2694_Y end attribute \src "ls180.v:8035.8-8035.56" - cell $not $not$ls180.v:8035$2695 + cell $not $not$ls180.v:8035$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:8035$2695_Y + connect \Y $not$ls180.v:8035$2697_Y end attribute \src "ls180.v:8050.8-8050.46" - cell $not $not$ls180.v:8050$2697 + cell $not $not$ls180.v:8050$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:8050$2697_Y + connect \Y $not$ls180.v:8050$2699_Y end attribute \src "ls180.v:8058.7-8058.22" - cell $not $not$ls180.v:8058$2700 + cell $not $not$ls180.v:8058$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:8058$2700_Y + connect \Y $not$ls180.v:8058$2702_Y end attribute \src "ls180.v:8061.8-8061.29" - cell $not $not$ls180.v:8061$2701 + cell $not $not$ls180.v:8061$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:8061$2701_Y + connect \Y $not$ls180.v:8061$2703_Y end attribute \src "ls180.v:8065.7-8065.22" - cell $not $not$ls180.v:8065$2703 + cell $not $not$ls180.v:8065$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:8065$2703_Y + connect \Y $not$ls180.v:8065$2705_Y end attribute \src "ls180.v:8068.8-8068.29" - cell $not $not$ls180.v:8068$2704 + cell $not $not$ls180.v:8068$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:8068$2704_Y + connect \Y $not$ls180.v:8068$2706_Y end attribute \src "ls180.v:8187.30-8187.60" - cell $not $not$ls180.v:8187$2706 + cell $not $not$ls180.v:8187$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8187$2706_Y + connect \Y $not$ls180.v:8187$2708_Y end attribute \src "ls180.v:8188.30-8188.60" - cell $not $not$ls180.v:8188$2707 + cell $not $not$ls180.v:8188$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8188$2707_Y + connect \Y $not$ls180.v:8188$2709_Y end attribute \src "ls180.v:8189.29-8189.59" - cell $not $not$ls180.v:8189$2708 + cell $not $not$ls180.v:8189$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8189$2708_Y + connect \Y $not$ls180.v:8189$2710_Y end attribute \src "ls180.v:8200.8-8200.33" - cell $not $not$ls180.v:8200$2709 + cell $not $not$ls180.v:8200$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8200$2709_Y + connect \Y $not$ls180.v:8200$2711_Y end attribute \src "ls180.v:8215.8-8215.33" - cell $not $not$ls180.v:8215$2712 + cell $not $not$ls180.v:8215$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8215$2712_Y + connect \Y $not$ls180.v:8215$2714_Y end attribute \src "ls180.v:8251.36-8251.58" - cell $not $not$ls180.v:8251$2742 + cell $not $not$ls180.v:8251$2744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8251$2742_Y + connect \Y $not$ls180.v:8251$2744_Y end attribute \src "ls180.v:8251.64-8251.89" - cell $not $not$ls180.v:8251$2744 + cell $not $not$ls180.v:8251$2746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8251$2744_Y + connect \Y $not$ls180.v:8251$2746_Y end attribute \src "ls180.v:8280.7-8280.29" - cell $not $not$ls180.v:8280$2751 + cell $not $not$ls180.v:8280$2753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8280$2751_Y + connect \Y $not$ls180.v:8280$2753_Y end attribute \src "ls180.v:8281.9-8281.26" - cell $not $not$ls180.v:8281$2752 + cell $not $not$ls180.v:8281$2754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8281$2752_Y + connect \Y $not$ls180.v:8281$2754_Y end attribute \src "ls180.v:8314.8-8314.29" - cell $not $not$ls180.v:8314$2758 + cell $not $not$ls180.v:8314$2760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8314$2758_Y + connect \Y $not$ls180.v:8314$2760_Y end attribute \src "ls180.v:8321.8-8321.29" - cell $not $not$ls180.v:8321$2760 + cell $not $not$ls180.v:8321$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8321$2760_Y + connect \Y $not$ls180.v:8321$2762_Y end attribute \src "ls180.v:8331.80-8331.106" - cell $not $not$ls180.v:8331$2763 + cell $not $not$ls180.v:8331$2765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8331$2763_Y + connect \Y $not$ls180.v:8331$2765_Y end attribute \src "ls180.v:8337.80-8337.106" - cell $not $not$ls180.v:8337$2768 + cell $not $not$ls180.v:8337$2770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8337$2768_Y + connect \Y $not$ls180.v:8337$2770_Y end attribute \src "ls180.v:8338.8-8338.34" - cell $not $not$ls180.v:8338$2770 + cell $not $not$ls180.v:8338$2772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8338$2770_Y + connect \Y $not$ls180.v:8338$2772_Y end attribute \src "ls180.v:8353.80-8353.106" - cell $not $not$ls180.v:8353$2774 + cell $not $not$ls180.v:8353$2776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8353$2774_Y + connect \Y $not$ls180.v:8353$2776_Y end attribute \src "ls180.v:8359.80-8359.106" - cell $not $not$ls180.v:8359$2779 + cell $not $not$ls180.v:8359$2781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8359$2779_Y + connect \Y $not$ls180.v:8359$2781_Y end attribute \src "ls180.v:8360.8-8360.34" - cell $not $not$ls180.v:8360$2781 + cell $not $not$ls180.v:8360$2783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8360$2781_Y + connect \Y $not$ls180.v:8360$2783_Y end attribute \src "ls180.v:8391.22-8391.41" - cell $not $not$ls180.v:8391$2785 + cell $not $not$ls180.v:8391$2787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8391$2785_Y + connect \Y $not$ls180.v:8391$2787_Y end attribute \src "ls180.v:8391.46-8391.73" - cell $not $not$ls180.v:8391$2786 + cell $not $not$ls180.v:8391$2788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8391$2786_Y + connect \Y $not$ls180.v:8391$2788_Y end attribute \src "ls180.v:8426.22-8426.40" - cell $not $not$ls180.v:8426$2790 + cell $not $not$ls180.v:8426$2792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8426$2790_Y + connect \Y $not$ls180.v:8426$2792_Y end attribute \src "ls180.v:8426.45-8426.70" - cell $not $not$ls180.v:8426$2791 + cell $not $not$ls180.v:8426$2793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8426$2791_Y + connect \Y $not$ls180.v:8426$2793_Y end attribute \src "ls180.v:8480.7-8480.31" - cell $not $not$ls180.v:8480$2802 + cell $not $not$ls180.v:8480$2804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8480$2802_Y + connect \Y $not$ls180.v:8480$2804_Y end attribute \src "ls180.v:8552.8-8552.46" - cell $not $not$ls180.v:8552$2814 + cell $not $not$ls180.v:8552$2816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8552$2814_Y + connect \Y $not$ls180.v:8552$2816_Y end attribute \src "ls180.v:8633.8-8633.47" - cell $not $not$ls180.v:8633$2826 + cell $not $not$ls180.v:8633$2828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8633$2826_Y + connect \Y $not$ls180.v:8633$2828_Y end attribute \src "ls180.v:8694.8-8694.48" - cell $not $not$ls180.v:8694$2838 + cell $not $not$ls180.v:8694$2840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8694$2838_Y + connect \Y $not$ls180.v:8694$2840_Y end attribute \src "ls180.v:8864.88-8864.118" - cell $not $not$ls180.v:8864$2852 + cell $not $not$ls180.v:8864$2854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8864$2852_Y + connect \Y $not$ls180.v:8864$2854_Y end attribute \src "ls180.v:8870.88-8870.118" - cell $not $not$ls180.v:8870$2857 + cell $not $not$ls180.v:8870$2859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8870$2857_Y + connect \Y $not$ls180.v:8870$2859_Y end attribute \src "ls180.v:8871.8-8871.38" - cell $not $not$ls180.v:8871$2859 + cell $not $not$ls180.v:8871$2861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8871$2859_Y + connect \Y $not$ls180.v:8871$2861_Y end attribute \src "ls180.v:8962.88-8962.118" - cell $not $not$ls180.v:8962$2874 + cell $not $not$ls180.v:8962$2876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8962$2874_Y + connect \Y $not$ls180.v:8962$2876_Y end attribute \src "ls180.v:8968.88-8968.118" - cell $not $not$ls180.v:8968$2879 + cell $not $not$ls180.v:8968$2881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8968$2879_Y + connect \Y $not$ls180.v:8968$2881_Y end attribute \src "ls180.v:8969.8-8969.38" - cell $not $not$ls180.v:8969$2881 + cell $not $not$ls180.v:8969$2883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8969$2881_Y + connect \Y $not$ls180.v:8969$2883_Y end attribute \src "ls180.v:8989.9-8989.28" - cell $not $not$ls180.v:8989$2884 + cell $not $not$ls180.v:8989$2886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8989$2884_Y + connect \Y $not$ls180.v:8989$2886_Y end attribute \src "ls180.v:9008.9-9008.28" - cell $not $not$ls180.v:9008$2885 + cell $not $not$ls180.v:9008$2887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:9008$2885_Y + connect \Y $not$ls180.v:9008$2887_Y end attribute \src "ls180.v:9027.9-9027.28" - cell $not $not$ls180.v:9027$2886 + cell $not $not$ls180.v:9027$2888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:9027$2886_Y + connect \Y $not$ls180.v:9027$2888_Y end attribute \src "ls180.v:9046.9-9046.28" - cell $not $not$ls180.v:9046$2887 + cell $not $not$ls180.v:9046$2889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:9046$2887_Y + connect \Y $not$ls180.v:9046$2889_Y end attribute \src "ls180.v:9065.9-9065.28" - cell $not $not$ls180.v:9065$2888 + cell $not $not$ls180.v:9065$2890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:9065$2888_Y + connect \Y $not$ls180.v:9065$2890_Y end attribute \src "ls180.v:9086.8-9086.21" - cell $not $not$ls180.v:9086$2889 + cell $not $not$ls180.v:9086$2891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:9086$2889_Y + connect \Y $not$ls180.v:9086$2891_Y end attribute \src "ls180.v:10709.8-10709.51" - cell $or $or$ls180.v:10709$3077 + cell $or $or$ls180.v:10709$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278592,7 +278618,7 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10709$3077_Y + connect \Y $or$ls180.v:10709$3079_Y end attribute \src "ls180.v:2934.10-2934.71" cell $or $or$ls180.v:2934$57 @@ -280641,7 +280667,7 @@ module \ls180 connect \Y $or$ls180.v:7189$2516_Y end attribute \src "ls180.v:7706.20-7706.71" - cell $or $or$ls180.v:7706$2574 + cell $or $or$ls180.v:7706$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280649,10 +280675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7706$2574_Y + connect \Y $or$ls180.v:7706$2576_Y end attribute \src "ls180.v:7707.20-7707.71" - cell $or $or$ls180.v:7707$2575 + cell $or $or$ls180.v:7707$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280660,10 +280686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7707$2575_Y + connect \Y $or$ls180.v:7707$2577_Y end attribute \src "ls180.v:7708.20-7708.71" - cell $or $or$ls180.v:7708$2576 + cell $or $or$ls180.v:7708$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280671,10 +280697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7708$2576_Y + connect \Y $or$ls180.v:7708$2578_Y end attribute \src "ls180.v:7709.20-7709.71" - cell $or $or$ls180.v:7709$2577 + cell $or $or$ls180.v:7709$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280682,10 +280708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7709$2577_Y + connect \Y $or$ls180.v:7709$2579_Y end attribute \src "ls180.v:7710.20-7710.71" - cell $or $or$ls180.v:7710$2578 + cell $or $or$ls180.v:7710$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280693,10 +280719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7710$2578_Y + connect \Y $or$ls180.v:7710$2580_Y end attribute \src "ls180.v:7711.20-7711.71" - cell $or $or$ls180.v:7711$2579 + cell $or $or$ls180.v:7711$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280704,10 +280730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7711$2579_Y + connect \Y $or$ls180.v:7711$2581_Y end attribute \src "ls180.v:7712.20-7712.71" - cell $or $or$ls180.v:7712$2580 + cell $or $or$ls180.v:7712$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280715,10 +280741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7712$2580_Y + connect \Y $or$ls180.v:7712$2582_Y end attribute \src "ls180.v:7713.20-7713.71" - cell $or $or$ls180.v:7713$2581 + cell $or $or$ls180.v:7713$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280726,10 +280752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7713$2581_Y + connect \Y $or$ls180.v:7713$2583_Y end attribute \src "ls180.v:7714.20-7714.71" - cell $or $or$ls180.v:7714$2582 + cell $or $or$ls180.v:7714$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280737,10 +280763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7714$2582_Y + connect \Y $or$ls180.v:7714$2584_Y end attribute \src "ls180.v:7715.20-7715.71" - cell $or $or$ls180.v:7715$2583 + cell $or $or$ls180.v:7715$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280748,10 +280774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7715$2583_Y + connect \Y $or$ls180.v:7715$2585_Y end attribute \src "ls180.v:7716.21-7716.73" - cell $or $or$ls180.v:7716$2584 + cell $or $or$ls180.v:7716$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280759,10 +280785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7716$2584_Y + connect \Y $or$ls180.v:7716$2586_Y end attribute \src "ls180.v:7717.21-7717.73" - cell $or $or$ls180.v:7717$2585 + cell $or $or$ls180.v:7717$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280770,10 +280796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7717$2585_Y + connect \Y $or$ls180.v:7717$2587_Y end attribute \src "ls180.v:7718.21-7718.73" - cell $or $or$ls180.v:7718$2586 + cell $or $or$ls180.v:7718$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280781,10 +280807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7718$2586_Y + connect \Y $or$ls180.v:7718$2588_Y end attribute \src "ls180.v:7719.21-7719.73" - cell $or $or$ls180.v:7719$2587 + cell $or $or$ls180.v:7719$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280792,10 +280818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7719$2587_Y + connect \Y $or$ls180.v:7719$2589_Y end attribute \src "ls180.v:7720.21-7720.73" - cell $or $or$ls180.v:7720$2588 + cell $or $or$ls180.v:7720$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280803,10 +280829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7720$2588_Y + connect \Y $or$ls180.v:7720$2590_Y end attribute \src "ls180.v:7721.21-7721.73" - cell $or $or$ls180.v:7721$2589 + cell $or $or$ls180.v:7721$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280814,10 +280840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7721$2589_Y + connect \Y $or$ls180.v:7721$2591_Y end attribute \src "ls180.v:7722.21-7722.73" - cell $or $or$ls180.v:7722$2590 + cell $or $or$ls180.v:7722$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280825,10 +280851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7722$2590_Y + connect \Y $or$ls180.v:7722$2592_Y end attribute \src "ls180.v:7723.21-7723.73" - cell $or $or$ls180.v:7723$2591 + cell $or $or$ls180.v:7723$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280836,10 +280862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7723$2591_Y + connect \Y $or$ls180.v:7723$2593_Y end attribute \src "ls180.v:7724.21-7724.73" - cell $or $or$ls180.v:7724$2592 + cell $or $or$ls180.v:7724$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280847,10 +280873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7724$2592_Y + connect \Y $or$ls180.v:7724$2594_Y end attribute \src "ls180.v:7725.21-7725.73" - cell $or $or$ls180.v:7725$2593 + cell $or $or$ls180.v:7725$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280858,10 +280884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7725$2593_Y + connect \Y $or$ls180.v:7725$2595_Y end attribute \src "ls180.v:7726.21-7726.73" - cell $or $or$ls180.v:7726$2594 + cell $or $or$ls180.v:7726$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280869,10 +280895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7726$2594_Y + connect \Y $or$ls180.v:7726$2596_Y end attribute \src "ls180.v:7727.21-7727.73" - cell $or $or$ls180.v:7727$2595 + cell $or $or$ls180.v:7727$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280880,10 +280906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7727$2595_Y + connect \Y $or$ls180.v:7727$2597_Y end attribute \src "ls180.v:7728.21-7728.73" - cell $or $or$ls180.v:7728$2596 + cell $or $or$ls180.v:7728$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280891,10 +280917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7728$2596_Y + connect \Y $or$ls180.v:7728$2598_Y end attribute \src "ls180.v:7729.21-7729.73" - cell $or $or$ls180.v:7729$2597 + cell $or $or$ls180.v:7729$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280902,10 +280928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7729$2597_Y + connect \Y $or$ls180.v:7729$2599_Y end attribute \src "ls180.v:7730.7-7730.68" - cell $or $or$ls180.v:7730$2598 + cell $or $or$ls180.v:7730$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280913,10 +280939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_ack connect \B \main_converter0_skip - connect \Y $or$ls180.v:7730$2598_Y + connect \Y $or$ls180.v:7730$2600_Y end attribute \src "ls180.v:7741.7-7741.68" - cell $or $or$ls180.v:7741$2599 + cell $or $or$ls180.v:7741$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280924,10 +280950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_ack connect \B \main_converter1_skip - connect \Y $or$ls180.v:7741$2599_Y + connect \Y $or$ls180.v:7741$2601_Y end attribute \src "ls180.v:7752.7-7752.50" - cell $or $or$ls180.v:7752$2600 + cell $or $or$ls180.v:7752$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280935,142 +280961,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_ack connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7752$2600_Y + connect \Y $or$ls180.v:7752$2602_Y end attribute \src "ls180.v:7897.7-7897.107" - cell $or $or$ls180.v:7897$2648 + cell $or $or$ls180.v:7897$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7897$2647_Y + connect \A $not$ls180.v:7897$2649_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7897$2648_Y + connect \Y $or$ls180.v:7897$2650_Y end attribute \src "ls180.v:7943.7-7943.107" - cell $or $or$ls180.v:7943$2664 + cell $or $or$ls180.v:7943$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7943$2663_Y + connect \A $not$ls180.v:7943$2665_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7943$2664_Y + connect \Y $or$ls180.v:7943$2666_Y end attribute \src "ls180.v:7989.7-7989.107" - cell $or $or$ls180.v:7989$2680 + cell $or $or$ls180.v:7989$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7989$2679_Y + connect \A $not$ls180.v:7989$2681_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7989$2680_Y + connect \Y $or$ls180.v:7989$2682_Y end attribute \src "ls180.v:8035.7-8035.107" - cell $or $or$ls180.v:8035$2696 + cell $or $or$ls180.v:8035$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8035$2695_Y + connect \A $not$ls180.v:8035$2697_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:8035$2696_Y + connect \Y $or$ls180.v:8035$2698_Y end attribute \src "ls180.v:8223.40-8223.125" - cell $or $or$ls180.v:8223$2717 + cell $or $or$ls180.v:8223$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8223$2716_Y - connect \Y $or$ls180.v:8223$2717_Y + connect \B $and$ls180.v:8223$2718_Y + connect \Y $or$ls180.v:8223$2719_Y end attribute \src "ls180.v:8223.39-8223.207" - cell $or $or$ls180.v:8223$2720 + cell $or $or$ls180.v:8223$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2717_Y - connect \B $and$ls180.v:8223$2719_Y - connect \Y $or$ls180.v:8223$2720_Y + connect \A $or$ls180.v:8223$2719_Y + connect \B $and$ls180.v:8223$2721_Y + connect \Y $or$ls180.v:8223$2722_Y end attribute \src "ls180.v:8223.38-8223.289" - cell $or $or$ls180.v:8223$2723 + cell $or $or$ls180.v:8223$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2720_Y - connect \B $and$ls180.v:8223$2722_Y - connect \Y $or$ls180.v:8223$2723_Y + connect \A $or$ls180.v:8223$2722_Y + connect \B $and$ls180.v:8223$2724_Y + connect \Y $or$ls180.v:8223$2725_Y end attribute \src "ls180.v:8223.37-8223.371" - cell $or $or$ls180.v:8223$2726 + cell $or $or$ls180.v:8223$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2723_Y - connect \B $and$ls180.v:8223$2725_Y - connect \Y $or$ls180.v:8223$2726_Y + connect \A $or$ls180.v:8223$2725_Y + connect \B $and$ls180.v:8223$2727_Y + connect \Y $or$ls180.v:8223$2728_Y end attribute \src "ls180.v:8224.41-8224.126" - cell $or $or$ls180.v:8224$2729 + cell $or $or$ls180.v:8224$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8224$2728_Y - connect \Y $or$ls180.v:8224$2729_Y + connect \B $and$ls180.v:8224$2730_Y + connect \Y $or$ls180.v:8224$2731_Y end attribute \src "ls180.v:8224.40-8224.208" - cell $or $or$ls180.v:8224$2732 + cell $or $or$ls180.v:8224$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2729_Y - connect \B $and$ls180.v:8224$2731_Y - connect \Y $or$ls180.v:8224$2732_Y + connect \A $or$ls180.v:8224$2731_Y + connect \B $and$ls180.v:8224$2733_Y + connect \Y $or$ls180.v:8224$2734_Y end attribute \src "ls180.v:8224.39-8224.290" - cell $or $or$ls180.v:8224$2735 + cell $or $or$ls180.v:8224$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2732_Y - connect \B $and$ls180.v:8224$2734_Y - connect \Y $or$ls180.v:8224$2735_Y + connect \A $or$ls180.v:8224$2734_Y + connect \B $and$ls180.v:8224$2736_Y + connect \Y $or$ls180.v:8224$2737_Y end attribute \src "ls180.v:8224.38-8224.372" - cell $or $or$ls180.v:8224$2738 + cell $or $or$ls180.v:8224$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2735_Y - connect \B $and$ls180.v:8224$2737_Y - connect \Y $or$ls180.v:8224$2738_Y + connect \A $or$ls180.v:8224$2737_Y + connect \B $and$ls180.v:8224$2739_Y + connect \Y $or$ls180.v:8224$2740_Y end attribute \src "ls180.v:8228.7-8228.49" - cell $or $or$ls180.v:8228$2739 + cell $or $or$ls180.v:8228$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281078,32 +281104,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:8228$2739_Y + connect \Y $or$ls180.v:8228$2741_Y end attribute \src "ls180.v:8391.21-8391.74" - cell $or $or$ls180.v:8391$2787 + cell $or $or$ls180.v:8391$2789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8391$2785_Y - connect \B $not$ls180.v:8391$2786_Y - connect \Y $or$ls180.v:8391$2787_Y + connect \A $not$ls180.v:8391$2787_Y + connect \B $not$ls180.v:8391$2788_Y + connect \Y $or$ls180.v:8391$2789_Y end attribute \src "ls180.v:8426.21-8426.71" - cell $or $or$ls180.v:8426$2792 + cell $or $or$ls180.v:8426$2794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8426$2790_Y - connect \B $not$ls180.v:8426$2791_Y - connect \Y $or$ls180.v:8426$2792_Y + connect \A $not$ls180.v:8426$2792_Y + connect \B $not$ls180.v:8426$2793_Y + connect \Y $or$ls180.v:8426$2794_Y end attribute \src "ls180.v:8494.32-8494.85" - cell $or $or$ls180.v:8494$2804 + cell $or $or$ls180.v:8494$2806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281111,21 +281137,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8494$2804_Y + connect \Y $or$ls180.v:8494$2806_Y end attribute \src "ls180.v:8500.8-8500.97" - cell $or $or$ls180.v:8500$2806 + cell $or $or$ls180.v:8500$2808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8500$2805_Y + connect \A $eq$ls180.v:8500$2807_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8500$2806_Y + connect \Y $or$ls180.v:8500$2808_Y end attribute \src "ls180.v:8517.52-8517.139" - cell $or $or$ls180.v:8517$2811 + cell $or $or$ls180.v:8517$2813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281133,10 +281159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8517$2811_Y + connect \Y $or$ls180.v:8517$2813_Y end attribute \src "ls180.v:8518.51-8518.136" - cell $or $or$ls180.v:8518$2812 + cell $or $or$ls180.v:8518$2814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281144,21 +281170,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8518$2812_Y + connect \Y $or$ls180.v:8518$2814_Y end attribute \src "ls180.v:8552.7-8552.87" - cell $or $or$ls180.v:8552$2815 + cell $or $or$ls180.v:8552$2817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8552$2814_Y + connect \A $not$ls180.v:8552$2816_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8552$2815_Y + connect \Y $or$ls180.v:8552$2817_Y end attribute \src "ls180.v:8575.33-8575.88" - cell $or $or$ls180.v:8575$2816 + cell $or $or$ls180.v:8575$2818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281166,21 +281192,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8575$2816_Y + connect \Y $or$ls180.v:8575$2818_Y end attribute \src "ls180.v:8581.8-8581.99" - cell $or $or$ls180.v:8581$2818 + cell $or $or$ls180.v:8581$2820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8581$2817_Y + connect \A $eq$ls180.v:8581$2819_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8581$2818_Y + connect \Y $or$ls180.v:8581$2820_Y end attribute \src "ls180.v:8598.53-8598.142" - cell $or $or$ls180.v:8598$2823 + cell $or $or$ls180.v:8598$2825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281188,10 +281214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8598$2823_Y + connect \Y $or$ls180.v:8598$2825_Y end attribute \src "ls180.v:8599.52-8599.139" - cell $or $or$ls180.v:8599$2824 + cell $or $or$ls180.v:8599$2826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281199,21 +281225,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8599$2824_Y + connect \Y $or$ls180.v:8599$2826_Y end attribute \src "ls180.v:8633.7-8633.89" - cell $or $or$ls180.v:8633$2827 + cell $or $or$ls180.v:8633$2829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8633$2826_Y + connect \A $not$ls180.v:8633$2828_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8633$2827_Y + connect \Y $or$ls180.v:8633$2829_Y end attribute \src "ls180.v:8654.34-8654.91" - cell $or $or$ls180.v:8654$2828 + cell $or $or$ls180.v:8654$2830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281221,21 +281247,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8654$2828_Y + connect \Y $or$ls180.v:8654$2830_Y end attribute \src "ls180.v:8660.8-8660.101" - cell $or $or$ls180.v:8660$2830 + cell $or $or$ls180.v:8660$2832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8660$2829_Y + connect \A $eq$ls180.v:8660$2831_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8660$2830_Y + connect \Y $or$ls180.v:8660$2832_Y end attribute \src "ls180.v:8677.54-8677.145" - cell $or $or$ls180.v:8677$2835 + cell $or $or$ls180.v:8677$2837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281243,10 +281269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8677$2835_Y + connect \Y $or$ls180.v:8677$2837_Y end attribute \src "ls180.v:8678.53-8678.142" - cell $or $or$ls180.v:8678$2836 + cell $or $or$ls180.v:8678$2838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281254,32 +281280,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8678$2836_Y + connect \Y $or$ls180.v:8678$2838_Y end attribute \src "ls180.v:8694.7-8694.91" - cell $or $or$ls180.v:8694$2839 + cell $or $or$ls180.v:8694$2841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8694$2838_Y + connect \A $not$ls180.v:8694$2840_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8694$2839_Y + connect \Y $or$ls180.v:8694$2841_Y end attribute \src "ls180.v:8883.8-8883.89" - cell $or $or$ls180.v:8883$2863 + cell $or $or$ls180.v:8883$2865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8883$2862_Y + connect \A $eq$ls180.v:8883$2864_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8883$2863_Y + connect \Y $or$ls180.v:8883$2865_Y end attribute \src "ls180.v:8900.48-8900.127" - cell $or $or$ls180.v:8900$2868 + cell $or $or$ls180.v:8900$2870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281287,10 +281313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8900$2868_Y + connect \Y $or$ls180.v:8900$2870_Y end attribute \src "ls180.v:8901.47-8901.124" - cell $or $or$ls180.v:8901$2869 + cell $or $or$ls180.v:8901$2871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281298,7 +281324,7 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8901$2869_Y + connect \Y $or$ls180.v:8901$2871_Y end attribute \src "ls180.v:3358.46-3358.94" cell $sshl $sshl$ls180.v:3358$231 @@ -281642,7 +281668,7 @@ module \ls180 connect \Y $sub$ls180.v:5836$1169_Y end attribute \src "ls180.v:7776.31-7776.60" - cell $sub $sub$ls180.v:7776$2607 + cell $sub $sub$ls180.v:7776$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281650,10 +281676,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7776$2607_Y + connect \Y $sub$ls180.v:7776$2609_Y end attribute \src "ls180.v:7813.31-7813.61" - cell $sub $sub$ls180.v:7813$2624 + cell $sub $sub$ls180.v:7813$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -281661,10 +281687,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7813$2624_Y + connect \Y $sub$ls180.v:7813$2626_Y end attribute \src "ls180.v:7819.34-7819.67" - cell $sub $sub$ls180.v:7819$2625 + cell $sub $sub$ls180.v:7819$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281672,10 +281698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7819$2625_Y + connect \Y $sub$ls180.v:7819$2627_Y end attribute \src "ls180.v:7830.36-7830.69" - cell $sub $sub$ls180.v:7830$2628 + cell $sub $sub$ls180.v:7830$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281683,10 +281709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7830$2628_Y + connect \Y $sub$ls180.v:7830$2630_Y end attribute \src "ls180.v:7894.59-7894.116" - cell $sub $sub$ls180.v:7894$2646 + cell $sub $sub$ls180.v:7894$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281694,10 +281720,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7894$2646_Y + connect \Y $sub$ls180.v:7894$2648_Y end attribute \src "ls180.v:7913.46-7913.90" - cell $sub $sub$ls180.v:7913$2650 + cell $sub $sub$ls180.v:7913$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281705,10 +281731,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7913$2650_Y + connect \Y $sub$ls180.v:7913$2652_Y end attribute \src "ls180.v:7940.59-7940.116" - cell $sub $sub$ls180.v:7940$2662 + cell $sub $sub$ls180.v:7940$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281716,10 +281742,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7940$2662_Y + connect \Y $sub$ls180.v:7940$2664_Y end attribute \src "ls180.v:7959.46-7959.90" - cell $sub $sub$ls180.v:7959$2666 + cell $sub $sub$ls180.v:7959$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281727,10 +281753,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7959$2666_Y + connect \Y $sub$ls180.v:7959$2668_Y end attribute \src "ls180.v:7986.59-7986.116" - cell $sub $sub$ls180.v:7986$2678 + cell $sub $sub$ls180.v:7986$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281738,10 +281764,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7986$2678_Y + connect \Y $sub$ls180.v:7986$2680_Y end attribute \src "ls180.v:8005.46-8005.90" - cell $sub $sub$ls180.v:8005$2682 + cell $sub $sub$ls180.v:8005$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281749,10 +281775,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8005$2682_Y + connect \Y $sub$ls180.v:8005$2684_Y end attribute \src "ls180.v:8032.59-8032.116" - cell $sub $sub$ls180.v:8032$2694 + cell $sub $sub$ls180.v:8032$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281760,10 +281786,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:8032$2694_Y + connect \Y $sub$ls180.v:8032$2696_Y end attribute \src "ls180.v:8051.46-8051.90" - cell $sub $sub$ls180.v:8051$2698 + cell $sub $sub$ls180.v:8051$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281771,10 +281797,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8051$2698_Y + connect \Y $sub$ls180.v:8051$2700_Y end attribute \src "ls180.v:8062.25-8062.48" - cell $sub $sub$ls180.v:8062$2702 + cell $sub $sub$ls180.v:8062$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281782,10 +281808,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:8062$2702_Y + connect \Y $sub$ls180.v:8062$2704_Y end attribute \src "ls180.v:8069.25-8069.48" - cell $sub $sub$ls180.v:8069$2705 + cell $sub $sub$ls180.v:8069$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281793,10 +281819,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:8069$2705_Y + connect \Y $sub$ls180.v:8069$2707_Y end attribute \src "ls180.v:8201.33-8201.64" - cell $sub $sub$ls180.v:8201$2710 + cell $sub $sub$ls180.v:8201$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281804,10 +281830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8201$2710_Y + connect \Y $sub$ls180.v:8201$2712_Y end attribute \src "ls180.v:8216.33-8216.64" - cell $sub $sub$ls180.v:8216$2713 + cell $sub $sub$ls180.v:8216$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281815,10 +281841,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8216$2713_Y + connect \Y $sub$ls180.v:8216$2715_Y end attribute \src "ls180.v:8343.33-8343.64" - cell $sub $sub$ls180.v:8343$2772 + cell $sub $sub$ls180.v:8343$2774 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281826,10 +281852,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8343$2772_Y + connect \Y $sub$ls180.v:8343$2774_Y end attribute \src "ls180.v:8365.33-8365.64" - cell $sub $sub$ls180.v:8365$2783 + cell $sub $sub$ls180.v:8365$2785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281837,10 +281863,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8365$2783_Y + connect \Y $sub$ls180.v:8365$2785_Y end attribute \src "ls180.v:8400.34-8400.66" - cell $sub $sub$ls180.v:8400$2788 + cell $sub $sub$ls180.v:8400$2790 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281848,10 +281874,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8400$2788_Y + connect \Y $sub$ls180.v:8400$2790_Y end attribute \src "ls180.v:8435.32-8435.62" - cell $sub $sub$ls180.v:8435$2793 + cell $sub $sub$ls180.v:8435$2795 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281859,10 +281885,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8435$2793_Y + connect \Y $sub$ls180.v:8435$2795_Y end attribute \src "ls180.v:8459.30-8459.53" - cell $sub $sub$ls180.v:8459$2796 + cell $sub $sub$ls180.v:8459$2798 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281870,10 +281896,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8459$2796_Y + connect \Y $sub$ls180.v:8459$2798_Y end attribute \src "ls180.v:8473.30-8473.53" - cell $sub $sub$ls180.v:8473$2800 + cell $sub $sub$ls180.v:8473$2802 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281881,10 +281907,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8473$2800_Y + connect \Y $sub$ls180.v:8473$2802_Y end attribute \src "ls180.v:8876.36-8876.70" - cell $sub $sub$ls180.v:8876$2861 + cell $sub $sub$ls180.v:8876$2863 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -281892,10 +281918,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8876$2861_Y + connect \Y $sub$ls180.v:8876$2863_Y end attribute \src "ls180.v:8974.36-8974.70" - cell $sub $sub$ls180.v:8974$2883 + cell $sub $sub$ls180.v:8974$2885 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -281903,10 +281929,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8974$2883_Y + connect \Y $sub$ls180.v:8974$2885_Y end attribute \src "ls180.v:9087.22-9087.42" - cell $sub $sub$ls180.v:9087$2890 + cell $sub $sub$ls180.v:9087$2892 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -281914,7 +281940,7 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:9087$2890_Y + connect \Y $sub$ls180.v:9087$2892_Y end attribute \src "ls180.v:5113.353-5113.425" cell $xor $xor$ls180.v:5113$860 @@ -284313,7 +284339,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10709$3077_Y + connect \rst $or$ls180.v:10709$3079_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -284526,32 +284552,32 @@ module \ls180 connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4091 + process $proc$ls180.v:0$4093 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4092 + process $proc$ls180.v:0$4094 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4093 + process $proc$ls180.v:0$4095 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4094 + process $proc$ls180.v:0$4096 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4095 + process $proc$ls180.v:0$4097 sync always sync init end attribute \src "ls180.v:100.11-100.56" - process $proc$ls180.v:100$3144 + process $proc$ls180.v:100$3146 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always @@ -284559,7 +284585,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end attribute \src "ls180.v:101.5-101.50" - process $proc$ls180.v:101$3145 + process $proc$ls180.v:101$3147 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 sync always @@ -284567,7 +284593,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] end attribute \src "ls180.v:1012.5-1012.40" - process $proc$ls180.v:1012$3483 + process $proc$ls180.v:1012$3485 assign { } { } assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always @@ -284575,7 +284601,7 @@ module \ls180 sync init end attribute \src "ls180.v:1013.5-1013.39" - process $proc$ls180.v:1013$3484 + process $proc$ls180.v:1013$3486 assign { } { } assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always @@ -284583,7 +284609,7 @@ module \ls180 sync init end attribute \src "ls180.v:102.5-102.50" - process $proc$ls180.v:102$3146 + process $proc$ls180.v:102$3148 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 sync always @@ -284591,7 +284617,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] end attribute \src "ls180.v:1021.5-1021.38" - process $proc$ls180.v:1021$3485 + process $proc$ls180.v:1021$3487 assign { } { } assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always @@ -284599,7 +284625,7 @@ module \ls180 update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end attribute \src "ls180.v:1028.11-1028.42" - process $proc$ls180.v:1028$3486 + process $proc$ls180.v:1028$3488 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always @@ -284607,7 +284633,7 @@ module \ls180 update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end attribute \src "ls180.v:1029.5-1029.37" - process $proc$ls180.v:1029$3487 + process $proc$ls180.v:1029$3489 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always @@ -284615,7 +284641,7 @@ module \ls180 sync init end attribute \src "ls180.v:1030.11-1030.43" - process $proc$ls180.v:1030$3488 + process $proc$ls180.v:1030$3490 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always @@ -284623,7 +284649,7 @@ module \ls180 update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end attribute \src "ls180.v:1031.11-1031.43" - process $proc$ls180.v:1031$3489 + process $proc$ls180.v:1031$3491 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always @@ -284631,7 +284657,7 @@ module \ls180 update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end attribute \src "ls180.v:1032.11-1032.46" - process $proc$ls180.v:1032$3490 + process $proc$ls180.v:1032$3492 assign { } { } assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always @@ -284639,7 +284665,7 @@ module \ls180 update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:10353.1-10371.4" - process $proc$ls180.v:10353$2891 + process $proc$ls180.v:10353$2893 assign { } { } assign { } { } assign { } { } @@ -284665,132 +284691,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr[5:0] \main_libresocsim_adr attribute \src "ls180.v:10354.2-10355.65" switch \main_libresocsim_we [0] attribute \src "ls180.v:10354.6-10354.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10356.2-10357.67" switch \main_libresocsim_we [1] attribute \src "ls180.v:10356.6-10356.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10358.2-10359.69" switch \main_libresocsim_we [2] attribute \src "ls180.v:10358.6-10358.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10360.2-10361.69" switch \main_libresocsim_we [3] attribute \src "ls180.v:10360.6-10360.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10362.2-10363.69" switch \main_libresocsim_we [4] attribute \src "ls180.v:10362.6-10362.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10364.2-10365.69" switch \main_libresocsim_we [5] attribute \src "ls180.v:10364.6-10364.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10366.2-10367.69" switch \main_libresocsim_we [6] attribute \src "ls180.v:10366.6-10366.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10368.2-10369.69" switch \main_libresocsim_we [7] attribute \src "ls180.v:10368.6-10368.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 - update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 - update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 - update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 - update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 - update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 - update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 - update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 - update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 - update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 - update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 - update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 - update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 - update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 - update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 - update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 - update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 - update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 - update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 - update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 - update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 - update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 - update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 - update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 + update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 + update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 + update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 + update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 + update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 + update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 + update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 + update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 + update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 + update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 + update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 + update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 + update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 + update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 + update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 + update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 + update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 + update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 + update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 + update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 + update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 + update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 + update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 + update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 end attribute \src "ls180.v:10381.1-10399.4" - process $proc$ls180.v:10381$2917 + process $proc$ls180.v:10381$2919 assign { } { } assign { } { } assign { } { } @@ -284816,132 +284842,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_1[5:0] \main_sram0_adr attribute \src "ls180.v:10382.2-10383.55" switch \main_sram0_we [0] attribute \src "ls180.v:10382.6-10382.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10384.2-10385.57" switch \main_sram0_we [1] attribute \src "ls180.v:10384.6-10384.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10386.2-10387.59" switch \main_sram0_we [2] attribute \src "ls180.v:10386.6-10386.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10388.2-10389.59" switch \main_sram0_we [3] attribute \src "ls180.v:10388.6-10388.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10390.2-10391.59" switch \main_sram0_we [4] attribute \src "ls180.v:10390.6-10390.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10392.2-10393.59" switch \main_sram0_we [5] attribute \src "ls180.v:10392.6-10392.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10394.2-10395.59" switch \main_sram0_we [6] attribute \src "ls180.v:10394.6-10394.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10396.2-10397.59" switch \main_sram0_we [7] attribute \src "ls180.v:10396.6-10396.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_1 $0\memadr_1[5:0] - update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 - update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 - update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 - update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 - update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 - update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 - update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 - update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 - update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 - update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 - update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 - update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 - update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 - update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 - update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 - update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 - update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 - update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 - update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 - update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 - update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 - update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 - update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 - update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 + update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 + update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 + update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 + update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 + update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 + update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 + update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 + update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 + update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 + update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 + update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 + update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 + update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 + update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 + update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 + update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 + update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 + update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 + update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 + update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 + update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 + update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 + update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 end attribute \src "ls180.v:104.5-104.49" - process $proc$ls180.v:104$3147 + process $proc$ls180.v:104$3149 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 sync always @@ -284949,7 +284975,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] end attribute \src "ls180.v:10409.1-10427.4" - process $proc$ls180.v:10409$2943 + process $proc$ls180.v:10409$2945 assign { } { } assign { } { } assign { } { } @@ -284975,132 +285001,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_2[5:0] \main_sram1_adr attribute \src "ls180.v:10410.2-10411.55" switch \main_sram1_we [0] attribute \src "ls180.v:10410.6-10410.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10412.2-10413.57" switch \main_sram1_we [1] attribute \src "ls180.v:10412.6-10412.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10414.2-10415.59" switch \main_sram1_we [2] attribute \src "ls180.v:10414.6-10414.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10416.2-10417.59" switch \main_sram1_we [3] attribute \src "ls180.v:10416.6-10416.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10418.2-10419.59" switch \main_sram1_we [4] attribute \src "ls180.v:10418.6-10418.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10420.2-10421.59" switch \main_sram1_we [5] attribute \src "ls180.v:10420.6-10420.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10422.2-10423.59" switch \main_sram1_we [6] attribute \src "ls180.v:10422.6-10422.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10424.2-10425.59" switch \main_sram1_we [7] attribute \src "ls180.v:10424.6-10424.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_2 $0\memadr_2[5:0] - update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 - update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 - update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 - update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 - update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 - update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 - update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 - update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 - update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 - update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 - update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 - update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 - update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 - update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 - update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 - update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 - update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 - update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 - update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 - update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 - update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 - update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 - update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 - update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 + update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 + update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 + update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 + update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 + update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 + update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 + update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 + update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 + update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 + update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 + update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 + update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 + update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 + update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 + update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 + update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 + update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 + update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 + update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 + update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 + update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 + update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 + update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 + update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 end attribute \src "ls180.v:10437.1-10455.4" - process $proc$ls180.v:10437$2969 + process $proc$ls180.v:10437$2971 assign { } { } assign { } { } assign { } { } @@ -285126,132 +285152,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_3[5:0] \main_sram2_adr attribute \src "ls180.v:10438.2-10439.55" switch \main_sram2_we [0] attribute \src "ls180.v:10438.6-10438.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10440.2-10441.57" switch \main_sram2_we [1] attribute \src "ls180.v:10440.6-10440.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10442.2-10443.59" switch \main_sram2_we [2] attribute \src "ls180.v:10442.6-10442.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10444.2-10445.59" switch \main_sram2_we [3] attribute \src "ls180.v:10444.6-10444.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10446.2-10447.59" switch \main_sram2_we [4] attribute \src "ls180.v:10446.6-10446.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10448.2-10449.59" switch \main_sram2_we [5] attribute \src "ls180.v:10448.6-10448.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10450.2-10451.59" switch \main_sram2_we [6] attribute \src "ls180.v:10450.6-10450.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10452.2-10453.59" switch \main_sram2_we [7] attribute \src "ls180.v:10452.6-10452.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_3 $0\memadr_3[5:0] - update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 - update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 - update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 - update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 - update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 - update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 - update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 - update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 - update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 - update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 - update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 - update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 - update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 - update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 - update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 - update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 - update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 - update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 - update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 - update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 - update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 - update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 - update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 - update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 + update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 + update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 + update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 + update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 + update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 + update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 + update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 + update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 + update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 + update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 + update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 + update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 + update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 + update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 + update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 + update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 + update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 + update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 + update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 + update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 + update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 + update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 + update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 + update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 end attribute \src "ls180.v:10465.1-10483.4" - process $proc$ls180.v:10465$2995 + process $proc$ls180.v:10465$2997 assign { } { } assign { } { } assign { } { } @@ -285277,324 +285303,324 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_4[5:0] \main_sram3_adr attribute \src "ls180.v:10466.2-10467.55" switch \main_sram3_we [0] attribute \src "ls180.v:10466.6-10466.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000011111111 case end attribute \src "ls180.v:10468.2-10469.57" switch \main_sram3_we [1] attribute \src "ls180.v:10468.6-10468.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000001111111100000000 case end attribute \src "ls180.v:10470.2-10471.59" switch \main_sram3_we [2] attribute \src "ls180.v:10470.6-10470.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000111111110000000000000000 case end attribute \src "ls180.v:10472.2-10473.59" switch \main_sram3_we [3] attribute \src "ls180.v:10472.6-10472.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000011111111000000000000000000000000 case end attribute \src "ls180.v:10474.2-10475.59" switch \main_sram3_we [4] attribute \src "ls180.v:10474.6-10474.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000001111111100000000000000000000000000000000 case end attribute \src "ls180.v:10476.2-10477.59" switch \main_sram3_we [5] attribute \src "ls180.v:10476.6-10476.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000111111110000000000000000000000000000000000000000 case end attribute \src "ls180.v:10478.2-10479.59" switch \main_sram3_we [6] attribute \src "ls180.v:10478.6-10478.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000011111111000000000000000000000000000000000000000000000000 case end attribute \src "ls180.v:10480.2-10481.59" switch \main_sram3_we [7] attribute \src "ls180.v:10480.6-10480.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_4 $0\memadr_4[5:0] - update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 - update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 - update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 - update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 - update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 - update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 - update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 - update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 - update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 - update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 - update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 - update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 - update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 - update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 - update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 - update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 - update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 - update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 - update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 - update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 - update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 - update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 - update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 - update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 + update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 + update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 + update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 + update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 + update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 + update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 + update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 + update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 + update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 + update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 + update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 + update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 + update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 + update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 + update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 + update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 + update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 + update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 + update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 + update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 + update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 + update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 + update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 end attribute \src "ls180.v:10493.1-10497.4" - process $proc$ls180.v:10493$3021 + process $proc$ls180.v:10493$3023 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 3'xxx - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3025_DATA + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 3'xxx + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3027_DATA attribute \src "ls180.v:10494.2-10495.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10494.6-10494.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 - update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 - update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 + update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 + update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 + update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 end attribute \src "ls180.v:10499.1-10500.4" - process $proc$ls180.v:10499$3026 + process $proc$ls180.v:10499$3028 sync posedge \sys_clk_1 end attribute \src "ls180.v:10507.1-10511.4" - process $proc$ls180.v:10507$3028 + process $proc$ls180.v:10507$3030 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 3'xxx - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3032_DATA + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 3'xxx + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3034_DATA attribute \src "ls180.v:10508.2-10509.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10508.6-10508.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 - update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 - update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 + update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 + update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 + update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 end attribute \src "ls180.v:10513.1-10514.4" - process $proc$ls180.v:10513$3033 + process $proc$ls180.v:10513$3035 sync posedge \sys_clk_1 end attribute \src "ls180.v:10521.1-10525.4" - process $proc$ls180.v:10521$3035 + process $proc$ls180.v:10521$3037 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 3'xxx - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3039_DATA + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 3'xxx + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3041_DATA attribute \src "ls180.v:10522.2-10523.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10522.6-10522.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 - update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 - update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 + update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 + update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 + update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 end attribute \src "ls180.v:10527.1-10528.4" - process $proc$ls180.v:10527$3040 + process $proc$ls180.v:10527$3042 sync posedge \sys_clk_1 end attribute \src "ls180.v:10535.1-10539.4" - process $proc$ls180.v:10535$3042 + process $proc$ls180.v:10535$3044 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 3'xxx - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3046_DATA + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 3'xxx + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3048_DATA attribute \src "ls180.v:10536.2-10537.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:10536.6-10536.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 - update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 - update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 + update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 + update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 + update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 end attribute \src "ls180.v:10541.1-10542.4" - process $proc$ls180.v:10541$3047 + process $proc$ls180.v:10541$3049 sync posedge \sys_clk_1 end attribute \src "ls180.v:10550.1-10554.4" - process $proc$ls180.v:10550$3049 + process $proc$ls180.v:10550$3051 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3053_DATA + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3055_DATA attribute \src "ls180.v:10551.2-10552.77" switch \main_uart_tx_fifo_wrport_we attribute \src "ls180.v:10551.6-10551.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 - update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 - update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 + update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 + update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 + update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 end attribute \src "ls180.v:10556.1-10559.4" - process $proc$ls180.v:10556$3054 + process $proc$ls180.v:10556$3056 assign $0\memdat_5[9:0] \memdat_5 attribute \src "ls180.v:10557.2-10558.55" switch \main_uart_tx_fifo_rdport_re attribute \src "ls180.v:10557.6-10557.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3055_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3057_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end attribute \src "ls180.v:10567.1-10571.4" - process $proc$ls180.v:10567$3056 + process $proc$ls180.v:10567$3058 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3060_DATA + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3062_DATA attribute \src "ls180.v:10568.2-10569.77" switch \main_uart_rx_fifo_wrport_we attribute \src "ls180.v:10568.6-10568.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 - update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 - update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 + update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 + update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 + update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 end attribute \src "ls180.v:10573.1-10576.4" - process $proc$ls180.v:10573$3061 + process $proc$ls180.v:10573$3063 assign $0\memdat_7[9:0] \memdat_7 attribute \src "ls180.v:10574.2-10575.55" switch \main_uart_rx_fifo_rdport_re attribute \src "ls180.v:10574.6-10574.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3062_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3064_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end attribute \src "ls180.v:1058.5-1058.38" - process $proc$ls180.v:1058$3491 + process $proc$ls180.v:1058$3493 assign { } { } assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always @@ -285602,65 +285628,65 @@ module \ls180 update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end attribute \src "ls180.v:10583.1-10587.4" - process $proc$ls180.v:10583$3063 + process $proc$ls180.v:10583$3065 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3067_DATA + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3069_DATA attribute \src "ls180.v:10584.2-10585.85" switch \main_sdblock2mem_fifo_wrport_we attribute \src "ls180.v:10584.6-10584.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 - update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 - update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 + update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 + update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 + update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 end attribute \src "ls180.v:10589.1-10590.4" - process $proc$ls180.v:10589$3068 + process $proc$ls180.v:10589$3070 sync posedge \sys_clk_1 end attribute \src "ls180.v:10597.1-10601.4" - process $proc$ls180.v:10597$3070 + process $proc$ls180.v:10597$3072 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3074_DATA + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3076_DATA attribute \src "ls180.v:10598.2-10599.85" switch \main_sdmem2block_fifo_wrport_we attribute \src "ls180.v:10598.6-10598.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 - update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 - update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 + update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 + update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 end attribute \src "ls180.v:10603.1-10604.4" - process $proc$ls180.v:10603$3075 + process $proc$ls180.v:10603$3077 sync posedge \sys_clk_1 end attribute \src "ls180.v:1065.11-1065.42" - process $proc$ls180.v:1065$3492 + process $proc$ls180.v:1065$3494 assign { } { } assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always @@ -285668,7 +285694,7 @@ module \ls180 update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end attribute \src "ls180.v:1066.5-1066.37" - process $proc$ls180.v:1066$3493 + process $proc$ls180.v:1066$3495 assign { } { } assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always @@ -285676,7 +285702,7 @@ module \ls180 sync init end attribute \src "ls180.v:1067.11-1067.43" - process $proc$ls180.v:1067$3494 + process $proc$ls180.v:1067$3496 assign { } { } assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always @@ -285684,7 +285710,7 @@ module \ls180 update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end attribute \src "ls180.v:1068.11-1068.43" - process $proc$ls180.v:1068$3495 + process $proc$ls180.v:1068$3497 assign { } { } assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always @@ -285692,7 +285718,7 @@ module \ls180 update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end attribute \src "ls180.v:1069.11-1069.46" - process $proc$ls180.v:1069$3496 + process $proc$ls180.v:1069$3498 assign { } { } assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always @@ -285700,7 +285726,7 @@ module \ls180 update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:1084.5-1084.27" - process $proc$ls180.v:1084$3497 + process $proc$ls180.v:1084$3499 assign { } { } assign $0\main_uart_reset[0:0] 1'0 sync always @@ -285708,7 +285734,7 @@ module \ls180 sync init end attribute \src "ls180.v:1085.12-1085.53" - process $proc$ls180.v:1085$3498 + process $proc$ls180.v:1085$3500 assign { } { } assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 sync always @@ -285716,7 +285742,7 @@ module \ls180 sync init end attribute \src "ls180.v:1086.12-1086.49" - process $proc$ls180.v:1086$3499 + process $proc$ls180.v:1086$3501 assign { } { } assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 sync always @@ -285724,7 +285750,7 @@ module \ls180 update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] end attribute \src "ls180.v:1087.12-1087.54" - process $proc$ls180.v:1087$3500 + process $proc$ls180.v:1087$3502 assign { } { } assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 sync always @@ -285732,7 +285758,7 @@ module \ls180 sync init end attribute \src "ls180.v:1091.12-1091.53" - process $proc$ls180.v:1091$3501 + process $proc$ls180.v:1091$3503 assign { } { } assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 sync always @@ -285740,7 +285766,7 @@ module \ls180 update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] end attribute \src "ls180.v:1092.5-1092.40" - process $proc$ls180.v:1092$3502 + process $proc$ls180.v:1092$3504 assign { } { } assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 sync always @@ -285748,7 +285774,7 @@ module \ls180 update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] end attribute \src "ls180.v:1093.12-1093.49" - process $proc$ls180.v:1093$3503 + process $proc$ls180.v:1093$3505 assign { } { } assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 sync always @@ -285756,7 +285782,7 @@ module \ls180 update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] end attribute \src "ls180.v:1095.12-1095.54" - process $proc$ls180.v:1095$3504 + process $proc$ls180.v:1095$3506 assign { } { } assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 sync always @@ -285764,7 +285790,7 @@ module \ls180 update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] end attribute \src "ls180.v:1096.5-1096.41" - process $proc$ls180.v:1096$3505 + process $proc$ls180.v:1096$3507 assign { } { } assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 sync always @@ -285772,7 +285798,7 @@ module \ls180 update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] end attribute \src "ls180.v:1102.5-1102.32" - process $proc$ls180.v:1102$3506 + process $proc$ls180.v:1102$3508 assign { } { } assign $1\main_spimaster2_done[0:0] 1'0 sync always @@ -285780,7 +285806,7 @@ module \ls180 update \main_spimaster2_done $1\main_spimaster2_done[0:0] end attribute \src "ls180.v:1103.5-1103.31" - process $proc$ls180.v:1103$3507 + process $proc$ls180.v:1103$3509 assign { } { } assign $1\main_spimaster3_irq[0:0] 1'0 sync always @@ -285788,7 +285814,7 @@ module \ls180 update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end attribute \src "ls180.v:1105.11-1105.38" - process $proc$ls180.v:1105$3508 + process $proc$ls180.v:1105$3510 assign { } { } assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always @@ -285796,7 +285822,7 @@ module \ls180 update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end attribute \src "ls180.v:1108.12-1108.47" - process $proc$ls180.v:1108$3509 + process $proc$ls180.v:1108$3511 assign { } { } assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always @@ -285804,7 +285830,7 @@ module \ls180 sync init end attribute \src "ls180.v:1109.5-1109.33" - process $proc$ls180.v:1109$3510 + process $proc$ls180.v:1109$3512 assign { } { } assign $1\main_spimaster9_start[0:0] 1'0 sync always @@ -285812,7 +285838,7 @@ module \ls180 update \main_spimaster9_start $1\main_spimaster9_start[0:0] end attribute \src "ls180.v:1111.12-1111.44" - process $proc$ls180.v:1111$3511 + process $proc$ls180.v:1111$3513 assign { } { } assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 sync always @@ -285820,7 +285846,7 @@ module \ls180 update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end attribute \src "ls180.v:1112.5-1112.31" - process $proc$ls180.v:1112$3512 + process $proc$ls180.v:1112$3514 assign { } { } assign $1\main_spimaster12_re[0:0] 1'0 sync always @@ -285828,7 +285854,7 @@ module \ls180 update \main_spimaster12_re $1\main_spimaster12_re[0:0] end attribute \src "ls180.v:1116.11-1116.42" - process $proc$ls180.v:1116$3513 + process $proc$ls180.v:1116$3515 assign { } { } assign $1\main_spimaster16_storage[7:0] 8'00000000 sync always @@ -285836,7 +285862,7 @@ module \ls180 update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] end attribute \src "ls180.v:1117.5-1117.31" - process $proc$ls180.v:1117$3514 + process $proc$ls180.v:1117$3516 assign { } { } assign $1\main_spimaster17_re[0:0] 1'0 sync always @@ -285844,7 +285870,7 @@ module \ls180 update \main_spimaster17_re $1\main_spimaster17_re[0:0] end attribute \src "ls180.v:1121.5-1121.36" - process $proc$ls180.v:1121$3515 + process $proc$ls180.v:1121$3517 assign { } { } assign $1\main_spimaster21_storage[0:0] 1'1 sync always @@ -285852,7 +285878,7 @@ module \ls180 update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end attribute \src "ls180.v:1122.5-1122.31" - process $proc$ls180.v:1122$3516 + process $proc$ls180.v:1122$3518 assign { } { } assign $1\main_spimaster22_re[0:0] 1'0 sync always @@ -285860,7 +285886,7 @@ module \ls180 update \main_spimaster22_re $1\main_spimaster22_re[0:0] end attribute \src "ls180.v:1123.5-1123.36" - process $proc$ls180.v:1123$3517 + process $proc$ls180.v:1123$3519 assign { } { } assign $1\main_spimaster23_storage[0:0] 1'0 sync always @@ -285868,7 +285894,7 @@ module \ls180 update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end attribute \src "ls180.v:1124.5-1124.31" - process $proc$ls180.v:1124$3518 + process $proc$ls180.v:1124$3520 assign { } { } assign $1\main_spimaster24_re[0:0] 1'0 sync always @@ -285876,7 +285902,7 @@ module \ls180 update \main_spimaster24_re $1\main_spimaster24_re[0:0] end attribute \src "ls180.v:1125.5-1125.39" - process $proc$ls180.v:1125$3519 + process $proc$ls180.v:1125$3521 assign { } { } assign $1\main_spimaster25_clk_enable[0:0] 1'0 sync always @@ -285884,7 +285910,7 @@ module \ls180 update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] end attribute \src "ls180.v:1126.5-1126.38" - process $proc$ls180.v:1126$3520 + process $proc$ls180.v:1126$3522 assign { } { } assign $1\main_spimaster26_cs_enable[0:0] 1'0 sync always @@ -285892,7 +285918,7 @@ module \ls180 update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] end attribute \src "ls180.v:1127.11-1127.40" - process $proc$ls180.v:1127$3521 + process $proc$ls180.v:1127$3523 assign { } { } assign $1\main_spimaster27_count[2:0] 3'000 sync always @@ -285900,7 +285926,7 @@ module \ls180 update \main_spimaster27_count $1\main_spimaster27_count[2:0] end attribute \src "ls180.v:1128.5-1128.39" - process $proc$ls180.v:1128$3522 + process $proc$ls180.v:1128$3524 assign { } { } assign $1\main_spimaster28_mosi_latch[0:0] 1'0 sync always @@ -285908,7 +285934,7 @@ module \ls180 update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] end attribute \src "ls180.v:1129.5-1129.39" - process $proc$ls180.v:1129$3523 + process $proc$ls180.v:1129$3525 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always @@ -285916,7 +285942,7 @@ module \ls180 update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end attribute \src "ls180.v:1130.12-1130.48" - process $proc$ls180.v:1130$3524 + process $proc$ls180.v:1130$3526 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always @@ -285924,7 +285950,7 @@ module \ls180 update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end attribute \src "ls180.v:1133.11-1133.44" - process $proc$ls180.v:1133$3525 + process $proc$ls180.v:1133$3527 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always @@ -285932,7 +285958,7 @@ module \ls180 update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end attribute \src "ls180.v:1134.11-1134.43" - process $proc$ls180.v:1134$3526 + process $proc$ls180.v:1134$3528 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always @@ -285940,7 +285966,7 @@ module \ls180 update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end attribute \src "ls180.v:1135.11-1135.44" - process $proc$ls180.v:1135$3527 + process $proc$ls180.v:1135$3529 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always @@ -285948,7 +285974,7 @@ module \ls180 update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end attribute \src "ls180.v:1138.5-1138.32" - process $proc$ls180.v:1138$3528 + process $proc$ls180.v:1138$3530 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always @@ -285956,7 +285982,7 @@ module \ls180 update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end attribute \src "ls180.v:1139.5-1139.30" - process $proc$ls180.v:1139$3529 + process $proc$ls180.v:1139$3531 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always @@ -285964,7 +285990,7 @@ module \ls180 update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end attribute \src "ls180.v:114.11-114.55" - process $proc$ls180.v:114$3148 + process $proc$ls180.v:114$3150 assign { } { } assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 sync always @@ -285972,7 +285998,7 @@ module \ls180 sync init end attribute \src "ls180.v:1141.11-1141.37" - process $proc$ls180.v:1141$3530 + process $proc$ls180.v:1141$3532 assign { } { } assign $1\main_spisdcard_miso[7:0] 8'00000000 sync always @@ -285980,7 +286006,7 @@ module \ls180 update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] end attribute \src "ls180.v:1145.5-1145.33" - process $proc$ls180.v:1145$3531 + process $proc$ls180.v:1145$3533 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always @@ -285988,7 +286014,7 @@ module \ls180 update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end attribute \src "ls180.v:1147.12-1147.50" - process $proc$ls180.v:1147$3532 + process $proc$ls180.v:1147$3534 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always @@ -285996,7 +286022,7 @@ module \ls180 update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end attribute \src "ls180.v:1148.5-1148.37" - process $proc$ls180.v:1148$3533 + process $proc$ls180.v:1148$3535 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always @@ -286004,7 +286030,7 @@ module \ls180 update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end attribute \src "ls180.v:115.11-115.55" - process $proc$ls180.v:115$3149 + process $proc$ls180.v:115$3151 assign { } { } assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 sync always @@ -286012,7 +286038,7 @@ module \ls180 sync init end attribute \src "ls180.v:1152.11-1152.45" - process $proc$ls180.v:1152$3534 + process $proc$ls180.v:1152$3536 assign { } { } assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 sync always @@ -286020,7 +286046,7 @@ module \ls180 update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] end attribute \src "ls180.v:1153.5-1153.34" - process $proc$ls180.v:1153$3535 + process $proc$ls180.v:1153$3537 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always @@ -286028,7 +286054,7 @@ module \ls180 update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end attribute \src "ls180.v:1157.5-1157.37" - process $proc$ls180.v:1157$3536 + process $proc$ls180.v:1157$3538 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always @@ -286036,7 +286062,7 @@ module \ls180 update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end attribute \src "ls180.v:1158.5-1158.32" - process $proc$ls180.v:1158$3537 + process $proc$ls180.v:1158$3539 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always @@ -286044,7 +286070,7 @@ module \ls180 update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end attribute \src "ls180.v:1159.5-1159.43" - process $proc$ls180.v:1159$3538 + process $proc$ls180.v:1159$3540 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always @@ -286052,7 +286078,7 @@ module \ls180 update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end attribute \src "ls180.v:1160.5-1160.38" - process $proc$ls180.v:1160$3539 + process $proc$ls180.v:1160$3541 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always @@ -286060,7 +286086,7 @@ module \ls180 update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end attribute \src "ls180.v:1161.5-1161.37" - process $proc$ls180.v:1161$3540 + process $proc$ls180.v:1161$3542 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always @@ -286068,7 +286094,7 @@ module \ls180 update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end attribute \src "ls180.v:1162.5-1162.36" - process $proc$ls180.v:1162$3541 + process $proc$ls180.v:1162$3543 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always @@ -286076,7 +286102,7 @@ module \ls180 update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end attribute \src "ls180.v:1163.11-1163.38" - process $proc$ls180.v:1163$3542 + process $proc$ls180.v:1163$3544 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always @@ -286084,7 +286110,7 @@ module \ls180 update \main_spisdcard_count $1\main_spisdcard_count[2:0] end attribute \src "ls180.v:1164.5-1164.37" - process $proc$ls180.v:1164$3543 + process $proc$ls180.v:1164$3545 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always @@ -286092,7 +286118,7 @@ module \ls180 update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end attribute \src "ls180.v:1165.5-1165.37" - process $proc$ls180.v:1165$3544 + process $proc$ls180.v:1165$3546 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always @@ -286100,7 +286126,7 @@ module \ls180 update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end attribute \src "ls180.v:1166.12-1166.47" - process $proc$ls180.v:1166$3545 + process $proc$ls180.v:1166$3547 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always @@ -286108,7 +286134,7 @@ module \ls180 update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end attribute \src "ls180.v:1169.11-1169.42" - process $proc$ls180.v:1169$3546 + process $proc$ls180.v:1169$3548 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always @@ -286116,7 +286142,7 @@ module \ls180 update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end attribute \src "ls180.v:1170.11-1170.41" - process $proc$ls180.v:1170$3547 + process $proc$ls180.v:1170$3549 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always @@ -286124,7 +286150,7 @@ module \ls180 update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end attribute \src "ls180.v:1171.11-1171.42" - process $proc$ls180.v:1171$3548 + process $proc$ls180.v:1171$3550 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always @@ -286132,7 +286158,7 @@ module \ls180 update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end attribute \src "ls180.v:1172.12-1172.45" - process $proc$ls180.v:1172$3549 + process $proc$ls180.v:1172$3551 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always @@ -286140,7 +286166,7 @@ module \ls180 update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end attribute \src "ls180.v:1173.5-1173.30" - process $proc$ls180.v:1173$3550 + process $proc$ls180.v:1173$3552 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always @@ -286148,7 +286174,7 @@ module \ls180 update \main_spimaster1_re $1\main_spimaster1_re[0:0] end attribute \src "ls180.v:1175.12-1175.30" - process $proc$ls180.v:1175$3551 + process $proc$ls180.v:1175$3553 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always @@ -286156,7 +286182,7 @@ module \ls180 update \main_dummy $1\main_dummy[23:0] end attribute \src "ls180.v:1179.12-1179.37" - process $proc$ls180.v:1179$3552 + process $proc$ls180.v:1179$3554 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always @@ -286164,7 +286190,7 @@ module \ls180 update \main_pwm0_counter $1\main_pwm0_counter[31:0] end attribute \src "ls180.v:1180.5-1180.36" - process $proc$ls180.v:1180$3553 + process $proc$ls180.v:1180$3555 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always @@ -286172,7 +286198,7 @@ module \ls180 update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end attribute \src "ls180.v:1181.5-1181.31" - process $proc$ls180.v:1181$3554 + process $proc$ls180.v:1181$3556 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always @@ -286180,7 +286206,7 @@ module \ls180 update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end attribute \src "ls180.v:1182.12-1182.43" - process $proc$ls180.v:1182$3555 + process $proc$ls180.v:1182$3557 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always @@ -286188,7 +286214,7 @@ module \ls180 update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end attribute \src "ls180.v:1183.5-1183.30" - process $proc$ls180.v:1183$3556 + process $proc$ls180.v:1183$3558 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always @@ -286196,7 +286222,7 @@ module \ls180 update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end attribute \src "ls180.v:1184.12-1184.44" - process $proc$ls180.v:1184$3557 + process $proc$ls180.v:1184$3559 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always @@ -286204,7 +286230,7 @@ module \ls180 update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end attribute \src "ls180.v:1185.5-1185.31" - process $proc$ls180.v:1185$3558 + process $proc$ls180.v:1185$3560 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always @@ -286212,7 +286238,7 @@ module \ls180 update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end attribute \src "ls180.v:1189.12-1189.37" - process $proc$ls180.v:1189$3559 + process $proc$ls180.v:1189$3561 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always @@ -286220,7 +286246,7 @@ module \ls180 update \main_pwm1_counter $1\main_pwm1_counter[31:0] end attribute \src "ls180.v:1190.5-1190.36" - process $proc$ls180.v:1190$3560 + process $proc$ls180.v:1190$3562 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always @@ -286228,7 +286254,7 @@ module \ls180 update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end attribute \src "ls180.v:1191.5-1191.31" - process $proc$ls180.v:1191$3561 + process $proc$ls180.v:1191$3563 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always @@ -286236,7 +286262,7 @@ module \ls180 update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end attribute \src "ls180.v:1192.12-1192.43" - process $proc$ls180.v:1192$3562 + process $proc$ls180.v:1192$3564 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always @@ -286244,7 +286270,7 @@ module \ls180 update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end attribute \src "ls180.v:1193.5-1193.30" - process $proc$ls180.v:1193$3563 + process $proc$ls180.v:1193$3565 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always @@ -286252,7 +286278,7 @@ module \ls180 update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end attribute \src "ls180.v:1194.12-1194.44" - process $proc$ls180.v:1194$3564 + process $proc$ls180.v:1194$3566 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always @@ -286260,7 +286286,7 @@ module \ls180 update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end attribute \src "ls180.v:1195.5-1195.31" - process $proc$ls180.v:1195$3565 + process $proc$ls180.v:1195$3567 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always @@ -286268,7 +286294,7 @@ module \ls180 update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end attribute \src "ls180.v:1199.11-1199.34" - process $proc$ls180.v:1199$3566 + process $proc$ls180.v:1199$3568 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always @@ -286276,7 +286302,7 @@ module \ls180 update \main_i2c_storage $1\main_i2c_storage[2:0] end attribute \src "ls180.v:1200.5-1200.23" - process $proc$ls180.v:1200$3567 + process $proc$ls180.v:1200$3569 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always @@ -286284,7 +286310,7 @@ module \ls180 update \main_i2c_re $1\main_i2c_re[0:0] end attribute \src "ls180.v:1206.11-1206.46" - process $proc$ls180.v:1206$3568 + process $proc$ls180.v:1206$3570 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always @@ -286292,7 +286318,7 @@ module \ls180 update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end attribute \src "ls180.v:1207.5-1207.33" - process $proc$ls180.v:1207$3569 + process $proc$ls180.v:1207$3571 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always @@ -286300,7 +286326,7 @@ module \ls180 update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end attribute \src "ls180.v:1209.5-1209.35" - process $proc$ls180.v:1209$3570 + process $proc$ls180.v:1209$3572 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always @@ -286308,7 +286334,7 @@ module \ls180 update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end attribute \src "ls180.v:1211.11-1211.41" - process $proc$ls180.v:1211$3571 + process $proc$ls180.v:1211$3573 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always @@ -286316,7 +286342,7 @@ module \ls180 update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end attribute \src "ls180.v:1212.5-1212.35" - process $proc$ls180.v:1212$3572 + process $proc$ls180.v:1212$3574 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always @@ -286324,7 +286350,7 @@ module \ls180 update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end attribute \src "ls180.v:1213.5-1213.36" - process $proc$ls180.v:1213$3573 + process $proc$ls180.v:1213$3575 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always @@ -286332,7 +286358,7 @@ module \ls180 update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end attribute \src "ls180.v:1217.5-1217.40" - process $proc$ls180.v:1217$3574 + process $proc$ls180.v:1217$3576 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always @@ -286340,7 +286366,7 @@ module \ls180 sync init end attribute \src "ls180.v:1222.5-1222.48" - process $proc$ls180.v:1222$3575 + process $proc$ls180.v:1222$3577 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always @@ -286348,7 +286374,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1223.5-1223.50" - process $proc$ls180.v:1223$3576 + process $proc$ls180.v:1223$3578 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286356,7 +286382,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end attribute \src "ls180.v:1224.5-1224.51" - process $proc$ls180.v:1224$3577 + process $proc$ls180.v:1224$3579 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286364,7 +286390,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end attribute \src "ls180.v:1225.11-1225.57" - process $proc$ls180.v:1225$3578 + process $proc$ls180.v:1225$3580 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286372,7 +286398,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end attribute \src "ls180.v:1226.5-1226.52" - process $proc$ls180.v:1226$3579 + process $proc$ls180.v:1226$3581 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286380,7 +286406,7 @@ module \ls180 update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end attribute \src "ls180.v:1227.11-1227.39" - process $proc$ls180.v:1227$3580 + process $proc$ls180.v:1227$3582 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always @@ -286388,7 +286414,7 @@ module \ls180 update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end attribute \src "ls180.v:1232.5-1232.48" - process $proc$ls180.v:1232$3581 + process $proc$ls180.v:1232$3583 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always @@ -286396,7 +286422,7 @@ module \ls180 update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1233.5-1233.50" - process $proc$ls180.v:1233$3582 + process $proc$ls180.v:1233$3584 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286404,7 +286430,7 @@ module \ls180 update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end attribute \src "ls180.v:1234.5-1234.51" - process $proc$ls180.v:1234$3583 + process $proc$ls180.v:1234$3585 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286412,7 +286438,7 @@ module \ls180 update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end attribute \src "ls180.v:1235.11-1235.57" - process $proc$ls180.v:1235$3584 + process $proc$ls180.v:1235$3586 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286420,7 +286446,7 @@ module \ls180 sync init end attribute \src "ls180.v:1236.5-1236.52" - process $proc$ls180.v:1236$3585 + process $proc$ls180.v:1236$3587 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286428,7 +286454,7 @@ module \ls180 sync init end attribute \src "ls180.v:1237.5-1237.38" - process $proc$ls180.v:1237$3586 + process $proc$ls180.v:1237$3588 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always @@ -286436,7 +286462,7 @@ module \ls180 update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end attribute \src "ls180.v:1238.5-1238.38" - process $proc$ls180.v:1238$3587 + process $proc$ls180.v:1238$3589 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always @@ -286444,7 +286470,7 @@ module \ls180 update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end attribute \src "ls180.v:1239.5-1239.37" - process $proc$ls180.v:1239$3588 + process $proc$ls180.v:1239$3590 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always @@ -286452,7 +286478,7 @@ module \ls180 update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end attribute \src "ls180.v:1240.11-1240.51" - process $proc$ls180.v:1240$3589 + process $proc$ls180.v:1240$3591 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always @@ -286460,7 +286486,7 @@ module \ls180 update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end attribute \src "ls180.v:1241.5-1241.32" - process $proc$ls180.v:1241$3590 + process $proc$ls180.v:1241$3592 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always @@ -286468,7 +286494,7 @@ module \ls180 update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end attribute \src "ls180.v:1242.11-1242.39" - process $proc$ls180.v:1242$3591 + process $proc$ls180.v:1242$3593 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always @@ -286476,7 +286502,7 @@ module \ls180 update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end attribute \src "ls180.v:1245.5-1245.49" - process $proc$ls180.v:1245$3592 + process $proc$ls180.v:1245$3594 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always @@ -286484,7 +286510,7 @@ module \ls180 sync init end attribute \src "ls180.v:1246.5-1246.48" - process $proc$ls180.v:1246$3593 + process $proc$ls180.v:1246$3595 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always @@ -286492,7 +286518,7 @@ module \ls180 sync init end attribute \src "ls180.v:1247.5-1247.55" - process $proc$ls180.v:1247$3594 + process $proc$ls180.v:1247$3596 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always @@ -286500,7 +286526,7 @@ module \ls180 sync init end attribute \src "ls180.v:1249.5-1249.57" - process $proc$ls180.v:1249$3595 + process $proc$ls180.v:1249$3597 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always @@ -286508,7 +286534,7 @@ module \ls180 sync init end attribute \src "ls180.v:1250.5-1250.58" - process $proc$ls180.v:1250$3596 + process $proc$ls180.v:1250$3598 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always @@ -286516,7 +286542,7 @@ module \ls180 sync init end attribute \src "ls180.v:1252.11-1252.64" - process $proc$ls180.v:1252$3597 + process $proc$ls180.v:1252$3599 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always @@ -286524,7 +286550,7 @@ module \ls180 sync init end attribute \src "ls180.v:1253.5-1253.59" - process $proc$ls180.v:1253$3598 + process $proc$ls180.v:1253$3600 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always @@ -286532,7 +286558,7 @@ module \ls180 sync init end attribute \src "ls180.v:1255.5-1255.48" - process $proc$ls180.v:1255$3599 + process $proc$ls180.v:1255$3601 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always @@ -286540,7 +286566,7 @@ module \ls180 update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1256.5-1256.50" - process $proc$ls180.v:1256$3600 + process $proc$ls180.v:1256$3602 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286548,7 +286574,7 @@ module \ls180 update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end attribute \src "ls180.v:1257.5-1257.51" - process $proc$ls180.v:1257$3601 + process $proc$ls180.v:1257$3603 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286556,7 +286582,7 @@ module \ls180 update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end attribute \src "ls180.v:1258.11-1258.57" - process $proc$ls180.v:1258$3602 + process $proc$ls180.v:1258$3604 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286564,7 +286590,7 @@ module \ls180 sync init end attribute \src "ls180.v:1259.5-1259.52" - process $proc$ls180.v:1259$3603 + process $proc$ls180.v:1259$3605 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286572,7 +286598,7 @@ module \ls180 sync init end attribute \src "ls180.v:1260.5-1260.38" - process $proc$ls180.v:1260$3604 + process $proc$ls180.v:1260$3606 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always @@ -286580,7 +286606,7 @@ module \ls180 update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end attribute \src "ls180.v:1261.5-1261.38" - process $proc$ls180.v:1261$3605 + process $proc$ls180.v:1261$3607 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always @@ -286588,7 +286614,7 @@ module \ls180 update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end attribute \src "ls180.v:1262.5-1262.37" - process $proc$ls180.v:1262$3606 + process $proc$ls180.v:1262$3608 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always @@ -286596,7 +286622,7 @@ module \ls180 update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end attribute \src "ls180.v:1263.11-1263.53" - process $proc$ls180.v:1263$3607 + process $proc$ls180.v:1263$3609 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always @@ -286604,7 +286630,7 @@ module \ls180 update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end attribute \src "ls180.v:1264.5-1264.40" - process $proc$ls180.v:1264$3608 + process $proc$ls180.v:1264$3610 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always @@ -286612,7 +286638,7 @@ module \ls180 update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end attribute \src "ls180.v:1265.5-1265.40" - process $proc$ls180.v:1265$3609 + process $proc$ls180.v:1265$3611 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always @@ -286620,7 +286646,7 @@ module \ls180 update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end attribute \src "ls180.v:1266.5-1266.39" - process $proc$ls180.v:1266$3610 + process $proc$ls180.v:1266$3612 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always @@ -286628,7 +286654,7 @@ module \ls180 update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end attribute \src "ls180.v:1267.11-1267.53" - process $proc$ls180.v:1267$3611 + process $proc$ls180.v:1267$3613 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always @@ -286636,7 +286662,7 @@ module \ls180 update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end attribute \src "ls180.v:1268.11-1268.55" - process $proc$ls180.v:1268$3612 + process $proc$ls180.v:1268$3614 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always @@ -286644,7 +286670,7 @@ module \ls180 update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end attribute \src "ls180.v:1269.12-1269.48" - process $proc$ls180.v:1269$3613 + process $proc$ls180.v:1269$3615 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always @@ -286652,7 +286678,7 @@ module \ls180 update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end attribute \src "ls180.v:1270.11-1270.39" - process $proc$ls180.v:1270$3614 + process $proc$ls180.v:1270$3616 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always @@ -286660,7 +286686,7 @@ module \ls180 update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end attribute \src "ls180.v:1272.5-1272.46" - process $proc$ls180.v:1272$3615 + process $proc$ls180.v:1272$3617 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always @@ -286668,7 +286694,7 @@ module \ls180 sync init end attribute \src "ls180.v:1283.5-1283.53" - process $proc$ls180.v:1283$3616 + process $proc$ls180.v:1283$3618 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always @@ -286676,7 +286702,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end attribute \src "ls180.v:1288.5-1288.36" - process $proc$ls180.v:1288$3617 + process $proc$ls180.v:1288$3619 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always @@ -286684,7 +286710,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end attribute \src "ls180.v:1291.5-1291.53" - process $proc$ls180.v:1291$3618 + process $proc$ls180.v:1291$3620 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always @@ -286692,7 +286718,7 @@ module \ls180 sync init end attribute \src "ls180.v:1292.5-1292.52" - process $proc$ls180.v:1292$3619 + process $proc$ls180.v:1292$3621 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always @@ -286700,7 +286726,7 @@ module \ls180 sync init end attribute \src "ls180.v:1296.5-1296.55" - process $proc$ls180.v:1296$3620 + process $proc$ls180.v:1296$3622 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always @@ -286708,7 +286734,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end attribute \src "ls180.v:1297.5-1297.54" - process $proc$ls180.v:1297$3621 + process $proc$ls180.v:1297$3623 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always @@ -286716,7 +286742,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end attribute \src "ls180.v:1298.11-1298.68" - process $proc$ls180.v:1298$3622 + process $proc$ls180.v:1298$3624 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always @@ -286724,7 +286750,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end attribute \src "ls180.v:1299.11-1299.81" - process $proc$ls180.v:1299$3623 + process $proc$ls180.v:1299$3625 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always @@ -286732,7 +286758,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end attribute \src "ls180.v:1300.11-1300.54" - process $proc$ls180.v:1300$3624 + process $proc$ls180.v:1300$3626 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always @@ -286740,7 +286766,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end attribute \src "ls180.v:1302.5-1302.53" - process $proc$ls180.v:1302$3625 + process $proc$ls180.v:1302$3627 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always @@ -286748,7 +286774,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end attribute \src "ls180.v:1313.5-1313.49" - process $proc$ls180.v:1313$3626 + process $proc$ls180.v:1313$3628 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always @@ -286756,7 +286782,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end attribute \src "ls180.v:1315.5-1315.49" - process $proc$ls180.v:1315$3627 + process $proc$ls180.v:1315$3629 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always @@ -286764,7 +286790,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end attribute \src "ls180.v:1316.5-1316.48" - process $proc$ls180.v:1316$3628 + process $proc$ls180.v:1316$3630 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always @@ -286772,7 +286798,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end attribute \src "ls180.v:1317.11-1317.62" - process $proc$ls180.v:1317$3629 + process $proc$ls180.v:1317$3631 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always @@ -286780,7 +286806,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end attribute \src "ls180.v:1318.5-1318.38" - process $proc$ls180.v:1318$3630 + process $proc$ls180.v:1318$3632 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always @@ -286788,7 +286814,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end attribute \src "ls180.v:1323.5-1323.49" - process $proc$ls180.v:1323$3631 + process $proc$ls180.v:1323$3633 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always @@ -286796,7 +286822,7 @@ module \ls180 update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1324.5-1324.51" - process $proc$ls180.v:1324$3632 + process $proc$ls180.v:1324$3634 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -286804,7 +286830,7 @@ module \ls180 sync init end attribute \src "ls180.v:1325.5-1325.52" - process $proc$ls180.v:1325$3633 + process $proc$ls180.v:1325$3635 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -286812,7 +286838,7 @@ module \ls180 sync init end attribute \src "ls180.v:1326.11-1326.58" - process $proc$ls180.v:1326$3634 + process $proc$ls180.v:1326$3636 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -286820,7 +286846,7 @@ module \ls180 update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end attribute \src "ls180.v:1327.5-1327.53" - process $proc$ls180.v:1327$3635 + process $proc$ls180.v:1327$3637 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -286828,7 +286854,7 @@ module \ls180 update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end attribute \src "ls180.v:1328.5-1328.39" - process $proc$ls180.v:1328$3636 + process $proc$ls180.v:1328$3638 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always @@ -286836,7 +286862,7 @@ module \ls180 update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end attribute \src "ls180.v:1329.5-1329.39" - process $proc$ls180.v:1329$3637 + process $proc$ls180.v:1329$3639 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always @@ -286844,7 +286870,7 @@ module \ls180 update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end attribute \src "ls180.v:1330.5-1330.39" - process $proc$ls180.v:1330$3638 + process $proc$ls180.v:1330$3640 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always @@ -286852,7 +286878,7 @@ module \ls180 update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end attribute \src "ls180.v:1331.5-1331.38" - process $proc$ls180.v:1331$3639 + process $proc$ls180.v:1331$3641 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always @@ -286860,7 +286886,7 @@ module \ls180 update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end attribute \src "ls180.v:1332.11-1332.52" - process $proc$ls180.v:1332$3640 + process $proc$ls180.v:1332$3642 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always @@ -286868,7 +286894,7 @@ module \ls180 update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end attribute \src "ls180.v:1333.5-1333.33" - process $proc$ls180.v:1333$3641 + process $proc$ls180.v:1333$3643 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always @@ -286876,7 +286902,7 @@ module \ls180 update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end attribute \src "ls180.v:1334.11-1334.40" - process $proc$ls180.v:1334$3642 + process $proc$ls180.v:1334$3644 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always @@ -286884,7 +286910,7 @@ module \ls180 update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end attribute \src "ls180.v:1335.5-1335.50" - process $proc$ls180.v:1335$3643 + process $proc$ls180.v:1335$3645 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always @@ -286892,7 +286918,7 @@ module \ls180 sync init end attribute \src "ls180.v:1337.5-1337.50" - process $proc$ls180.v:1337$3644 + process $proc$ls180.v:1337$3646 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always @@ -286900,7 +286926,7 @@ module \ls180 sync init end attribute \src "ls180.v:1338.5-1338.49" - process $proc$ls180.v:1338$3645 + process $proc$ls180.v:1338$3647 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always @@ -286908,7 +286934,7 @@ module \ls180 sync init end attribute \src "ls180.v:1339.5-1339.56" - process $proc$ls180.v:1339$3646 + process $proc$ls180.v:1339$3648 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always @@ -286916,7 +286942,7 @@ module \ls180 sync init end attribute \src "ls180.v:1340.5-1340.58" - process $proc$ls180.v:1340$3647 + process $proc$ls180.v:1340$3649 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always @@ -286924,7 +286950,7 @@ module \ls180 sync init end attribute \src "ls180.v:1341.5-1341.58" - process $proc$ls180.v:1341$3648 + process $proc$ls180.v:1341$3650 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always @@ -286932,7 +286958,7 @@ module \ls180 sync init end attribute \src "ls180.v:1342.5-1342.59" - process $proc$ls180.v:1342$3649 + process $proc$ls180.v:1342$3651 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always @@ -286940,7 +286966,7 @@ module \ls180 sync init end attribute \src "ls180.v:1343.11-1343.65" - process $proc$ls180.v:1343$3650 + process $proc$ls180.v:1343$3652 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always @@ -286948,7 +286974,7 @@ module \ls180 sync init end attribute \src "ls180.v:1344.11-1344.65" - process $proc$ls180.v:1344$3651 + process $proc$ls180.v:1344$3653 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always @@ -286956,7 +286982,7 @@ module \ls180 sync init end attribute \src "ls180.v:1345.5-1345.60" - process $proc$ls180.v:1345$3652 + process $proc$ls180.v:1345$3654 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always @@ -286964,7 +286990,7 @@ module \ls180 sync init end attribute \src "ls180.v:1346.5-1346.34" - process $proc$ls180.v:1346$3653 + process $proc$ls180.v:1346$3655 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always @@ -286972,7 +286998,7 @@ module \ls180 update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end attribute \src "ls180.v:1347.5-1347.34" - process $proc$ls180.v:1347$3654 + process $proc$ls180.v:1347$3656 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always @@ -286980,7 +287006,7 @@ module \ls180 update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end attribute \src "ls180.v:1348.5-1348.34" - process $proc$ls180.v:1348$3655 + process $proc$ls180.v:1348$3657 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always @@ -286988,7 +287014,7 @@ module \ls180 update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end attribute \src "ls180.v:1350.5-1350.47" - process $proc$ls180.v:1350$3656 + process $proc$ls180.v:1350$3658 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always @@ -286996,7 +287022,7 @@ module \ls180 sync init end attribute \src "ls180.v:1361.5-1361.54" - process $proc$ls180.v:1361$3657 + process $proc$ls180.v:1361$3659 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always @@ -287004,7 +287030,7 @@ module \ls180 update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end attribute \src "ls180.v:1366.5-1366.37" - process $proc$ls180.v:1366$3658 + process $proc$ls180.v:1366$3660 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always @@ -287012,7 +287038,7 @@ module \ls180 update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end attribute \src "ls180.v:1369.5-1369.54" - process $proc$ls180.v:1369$3659 + process $proc$ls180.v:1369$3661 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always @@ -287020,7 +287046,7 @@ module \ls180 sync init end attribute \src "ls180.v:1370.5-1370.53" - process $proc$ls180.v:1370$3660 + process $proc$ls180.v:1370$3662 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always @@ -287028,7 +287054,7 @@ module \ls180 sync init end attribute \src "ls180.v:1374.5-1374.56" - process $proc$ls180.v:1374$3661 + process $proc$ls180.v:1374$3663 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always @@ -287036,7 +287062,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end attribute \src "ls180.v:1375.5-1375.55" - process $proc$ls180.v:1375$3662 + process $proc$ls180.v:1375$3664 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always @@ -287044,7 +287070,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end attribute \src "ls180.v:1376.11-1376.69" - process $proc$ls180.v:1376$3663 + process $proc$ls180.v:1376$3665 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always @@ -287052,7 +287078,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end attribute \src "ls180.v:1377.11-1377.82" - process $proc$ls180.v:1377$3664 + process $proc$ls180.v:1377$3666 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always @@ -287060,7 +287086,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end attribute \src "ls180.v:1378.11-1378.55" - process $proc$ls180.v:1378$3665 + process $proc$ls180.v:1378$3667 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always @@ -287068,7 +287094,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end attribute \src "ls180.v:1380.5-1380.54" - process $proc$ls180.v:1380$3666 + process $proc$ls180.v:1380$3668 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always @@ -287076,7 +287102,7 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end attribute \src "ls180.v:1391.5-1391.50" - process $proc$ls180.v:1391$3667 + process $proc$ls180.v:1391$3669 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always @@ -287084,7 +287110,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end attribute \src "ls180.v:1393.5-1393.50" - process $proc$ls180.v:1393$3668 + process $proc$ls180.v:1393$3670 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always @@ -287092,7 +287118,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end attribute \src "ls180.v:1394.5-1394.49" - process $proc$ls180.v:1394$3669 + process $proc$ls180.v:1394$3671 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always @@ -287100,7 +287126,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end attribute \src "ls180.v:1395.11-1395.63" - process $proc$ls180.v:1395$3670 + process $proc$ls180.v:1395$3672 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always @@ -287108,7 +287134,7 @@ module \ls180 update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end attribute \src "ls180.v:1396.5-1396.39" - process $proc$ls180.v:1396$3671 + process $proc$ls180.v:1396$3673 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always @@ -287116,7 +287142,7 @@ module \ls180 update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end attribute \src "ls180.v:1399.5-1399.50" - process $proc$ls180.v:1399$3672 + process $proc$ls180.v:1399$3674 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always @@ -287124,7 +287150,7 @@ module \ls180 sync init end attribute \src "ls180.v:1400.5-1400.49" - process $proc$ls180.v:1400$3673 + process $proc$ls180.v:1400$3675 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always @@ -287132,7 +287158,7 @@ module \ls180 sync init end attribute \src "ls180.v:1401.5-1401.56" - process $proc$ls180.v:1401$3674 + process $proc$ls180.v:1401$3676 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always @@ -287140,7 +287166,7 @@ module \ls180 sync init end attribute \src "ls180.v:1403.5-1403.58" - process $proc$ls180.v:1403$3675 + process $proc$ls180.v:1403$3677 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always @@ -287148,7 +287174,7 @@ module \ls180 sync init end attribute \src "ls180.v:1404.5-1404.59" - process $proc$ls180.v:1404$3676 + process $proc$ls180.v:1404$3678 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always @@ -287156,7 +287182,7 @@ module \ls180 sync init end attribute \src "ls180.v:1406.11-1406.65" - process $proc$ls180.v:1406$3677 + process $proc$ls180.v:1406$3679 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always @@ -287164,7 +287190,7 @@ module \ls180 sync init end attribute \src "ls180.v:1407.5-1407.60" - process $proc$ls180.v:1407$3678 + process $proc$ls180.v:1407$3680 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always @@ -287172,7 +287198,7 @@ module \ls180 sync init end attribute \src "ls180.v:1409.5-1409.49" - process $proc$ls180.v:1409$3679 + process $proc$ls180.v:1409$3681 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always @@ -287180,7 +287206,7 @@ module \ls180 update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end attribute \src "ls180.v:1410.5-1410.51" - process $proc$ls180.v:1410$3680 + process $proc$ls180.v:1410$3682 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always @@ -287188,7 +287214,7 @@ module \ls180 sync init end attribute \src "ls180.v:1411.5-1411.52" - process $proc$ls180.v:1411$3681 + process $proc$ls180.v:1411$3683 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always @@ -287196,7 +287222,7 @@ module \ls180 sync init end attribute \src "ls180.v:1412.11-1412.58" - process $proc$ls180.v:1412$3682 + process $proc$ls180.v:1412$3684 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always @@ -287204,7 +287230,7 @@ module \ls180 sync init end attribute \src "ls180.v:1413.5-1413.53" - process $proc$ls180.v:1413$3683 + process $proc$ls180.v:1413$3685 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always @@ -287212,7 +287238,7 @@ module \ls180 sync init end attribute \src "ls180.v:1414.5-1414.39" - process $proc$ls180.v:1414$3684 + process $proc$ls180.v:1414$3686 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always @@ -287220,7 +287246,7 @@ module \ls180 update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end attribute \src "ls180.v:1415.5-1415.39" - process $proc$ls180.v:1415$3685 + process $proc$ls180.v:1415$3687 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always @@ -287228,7 +287254,7 @@ module \ls180 update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end attribute \src "ls180.v:1416.5-1416.38" - process $proc$ls180.v:1416$3686 + process $proc$ls180.v:1416$3688 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always @@ -287236,7 +287262,7 @@ module \ls180 update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end attribute \src "ls180.v:1417.11-1417.61" - process $proc$ls180.v:1417$3687 + process $proc$ls180.v:1417$3689 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always @@ -287244,7 +287270,7 @@ module \ls180 update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end attribute \src "ls180.v:1418.5-1418.41" - process $proc$ls180.v:1418$3688 + process $proc$ls180.v:1418$3690 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always @@ -287252,7 +287278,7 @@ module \ls180 update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end attribute \src "ls180.v:1419.5-1419.41" - process $proc$ls180.v:1419$3689 + process $proc$ls180.v:1419$3691 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always @@ -287260,7 +287286,7 @@ module \ls180 update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end attribute \src "ls180.v:1420.5-1420.41" - process $proc$ls180.v:1420$3690 + process $proc$ls180.v:1420$3692 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always @@ -287268,7 +287294,7 @@ module \ls180 sync init end attribute \src "ls180.v:1421.5-1421.40" - process $proc$ls180.v:1421$3691 + process $proc$ls180.v:1421$3693 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always @@ -287276,7 +287302,7 @@ module \ls180 update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end attribute \src "ls180.v:1422.11-1422.54" - process $proc$ls180.v:1422$3692 + process $proc$ls180.v:1422$3694 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always @@ -287284,7 +287310,7 @@ module \ls180 update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end attribute \src "ls180.v:1423.11-1423.56" - process $proc$ls180.v:1423$3693 + process $proc$ls180.v:1423$3695 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always @@ -287292,7 +287318,7 @@ module \ls180 update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end attribute \src "ls180.v:1424.5-1424.33" - process $proc$ls180.v:1424$3694 + process $proc$ls180.v:1424$3696 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always @@ -287300,7 +287326,7 @@ module \ls180 update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end attribute \src "ls180.v:1425.12-1425.49" - process $proc$ls180.v:1425$3695 + process $proc$ls180.v:1425$3697 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always @@ -287308,7 +287334,7 @@ module \ls180 update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end attribute \src "ls180.v:1426.11-1426.41" - process $proc$ls180.v:1426$3696 + process $proc$ls180.v:1426$3698 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always @@ -287316,7 +287342,7 @@ module \ls180 update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end attribute \src "ls180.v:1428.5-1428.48" - process $proc$ls180.v:1428$3697 + process $proc$ls180.v:1428$3699 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always @@ -287324,7 +287350,7 @@ module \ls180 sync init end attribute \src "ls180.v:1439.5-1439.55" - process $proc$ls180.v:1439$3698 + process $proc$ls180.v:1439$3700 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always @@ -287332,7 +287358,7 @@ module \ls180 update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end attribute \src "ls180.v:1444.5-1444.38" - process $proc$ls180.v:1444$3699 + process $proc$ls180.v:1444$3701 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always @@ -287340,7 +287366,7 @@ module \ls180 update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end attribute \src "ls180.v:1447.5-1447.55" - process $proc$ls180.v:1447$3700 + process $proc$ls180.v:1447$3702 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always @@ -287348,7 +287374,7 @@ module \ls180 sync init end attribute \src "ls180.v:1448.5-1448.54" - process $proc$ls180.v:1448$3701 + process $proc$ls180.v:1448$3703 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always @@ -287356,7 +287382,7 @@ module \ls180 sync init end attribute \src "ls180.v:1452.5-1452.57" - process $proc$ls180.v:1452$3702 + process $proc$ls180.v:1452$3704 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always @@ -287364,7 +287390,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end attribute \src "ls180.v:1453.5-1453.56" - process $proc$ls180.v:1453$3703 + process $proc$ls180.v:1453$3705 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always @@ -287372,7 +287398,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end attribute \src "ls180.v:1454.11-1454.70" - process $proc$ls180.v:1454$3704 + process $proc$ls180.v:1454$3706 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always @@ -287380,7 +287406,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end attribute \src "ls180.v:1455.11-1455.83" - process $proc$ls180.v:1455$3705 + process $proc$ls180.v:1455$3707 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always @@ -287388,7 +287414,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end attribute \src "ls180.v:1456.5-1456.50" - process $proc$ls180.v:1456$3706 + process $proc$ls180.v:1456$3708 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always @@ -287396,7 +287422,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end attribute \src "ls180.v:1458.5-1458.55" - process $proc$ls180.v:1458$3707 + process $proc$ls180.v:1458$3709 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always @@ -287404,7 +287430,7 @@ module \ls180 update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end attribute \src "ls180.v:1469.5-1469.51" - process $proc$ls180.v:1469$3708 + process $proc$ls180.v:1469$3710 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always @@ -287412,7 +287438,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end attribute \src "ls180.v:1471.5-1471.51" - process $proc$ls180.v:1471$3709 + process $proc$ls180.v:1471$3711 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always @@ -287420,7 +287446,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end attribute \src "ls180.v:1472.5-1472.50" - process $proc$ls180.v:1472$3710 + process $proc$ls180.v:1472$3712 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always @@ -287428,7 +287454,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end attribute \src "ls180.v:1473.11-1473.64" - process $proc$ls180.v:1473$3711 + process $proc$ls180.v:1473$3713 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always @@ -287436,7 +287462,7 @@ module \ls180 update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end attribute \src "ls180.v:1474.5-1474.40" - process $proc$ls180.v:1474$3712 + process $proc$ls180.v:1474$3714 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always @@ -287444,7 +287470,7 @@ module \ls180 update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end attribute \src "ls180.v:1476.5-1476.35" - process $proc$ls180.v:1476$3713 + process $proc$ls180.v:1476$3715 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always @@ -287452,7 +287478,7 @@ module \ls180 update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end attribute \src "ls180.v:1479.11-1479.42" - process $proc$ls180.v:1479$3714 + process $proc$ls180.v:1479$3716 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always @@ -287460,7 +287486,7 @@ module \ls180 update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end attribute \src "ls180.v:1492.12-1492.52" - process $proc$ls180.v:1492$3715 + process $proc$ls180.v:1492$3717 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always @@ -287468,7 +287494,7 @@ module \ls180 update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end attribute \src "ls180.v:1493.5-1493.39" - process $proc$ls180.v:1493$3716 + process $proc$ls180.v:1493$3718 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always @@ -287476,7 +287502,7 @@ module \ls180 update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end attribute \src "ls180.v:1494.12-1494.51" - process $proc$ls180.v:1494$3717 + process $proc$ls180.v:1494$3719 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always @@ -287484,7 +287510,7 @@ module \ls180 update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end attribute \src "ls180.v:1495.5-1495.38" - process $proc$ls180.v:1495$3718 + process $proc$ls180.v:1495$3720 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always @@ -287492,7 +287518,7 @@ module \ls180 update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end attribute \src "ls180.v:1499.5-1499.34" - process $proc$ls180.v:1499$3719 + process $proc$ls180.v:1499$3721 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always @@ -287500,7 +287526,7 @@ module \ls180 sync init end attribute \src "ls180.v:1500.13-1500.53" - process $proc$ls180.v:1500$3720 + process $proc$ls180.v:1500$3722 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always @@ -287508,7 +287534,7 @@ module \ls180 update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end attribute \src "ls180.v:1506.11-1506.51" - process $proc$ls180.v:1506$3721 + process $proc$ls180.v:1506$3723 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always @@ -287516,7 +287542,7 @@ module \ls180 update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end attribute \src "ls180.v:1507.5-1507.39" - process $proc$ls180.v:1507$3722 + process $proc$ls180.v:1507$3724 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always @@ -287524,7 +287550,7 @@ module \ls180 update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end attribute \src "ls180.v:1508.12-1508.51" - process $proc$ls180.v:1508$3723 + process $proc$ls180.v:1508$3725 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always @@ -287532,7 +287558,7 @@ module \ls180 update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end attribute \src "ls180.v:1509.5-1509.38" - process $proc$ls180.v:1509$3724 + process $proc$ls180.v:1509$3726 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always @@ -287540,7 +287566,7 @@ module \ls180 update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end attribute \src "ls180.v:1510.11-1510.51" - process $proc$ls180.v:1510$3725 + process $proc$ls180.v:1510$3727 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always @@ -287548,7 +287574,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end attribute \src "ls180.v:1552.11-1552.47" - process $proc$ls180.v:1552$3726 + process $proc$ls180.v:1552$3728 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always @@ -287556,7 +287582,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end attribute \src "ls180.v:1556.5-1556.49" - process $proc$ls180.v:1556$3727 + process $proc$ls180.v:1556$3729 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always @@ -287564,7 +287590,7 @@ module \ls180 update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end attribute \src "ls180.v:1560.5-1560.51" - process $proc$ls180.v:1560$3728 + process $proc$ls180.v:1560$3730 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always @@ -287572,7 +287598,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end attribute \src "ls180.v:1561.5-1561.51" - process $proc$ls180.v:1561$3729 + process $proc$ls180.v:1561$3731 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always @@ -287580,7 +287606,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end attribute \src "ls180.v:1562.5-1562.51" - process $proc$ls180.v:1562$3730 + process $proc$ls180.v:1562$3732 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always @@ -287588,7 +287614,7 @@ module \ls180 sync init end attribute \src "ls180.v:1563.5-1563.50" - process $proc$ls180.v:1563$3731 + process $proc$ls180.v:1563$3733 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always @@ -287596,7 +287622,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end attribute \src "ls180.v:1564.11-1564.64" - process $proc$ls180.v:1564$3732 + process $proc$ls180.v:1564$3734 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always @@ -287604,7 +287630,7 @@ module \ls180 update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end attribute \src "ls180.v:1565.11-1565.48" - process $proc$ls180.v:1565$3733 + process $proc$ls180.v:1565$3735 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always @@ -287612,7 +287638,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end attribute \src "ls180.v:1566.12-1566.59" - process $proc$ls180.v:1566$3734 + process $proc$ls180.v:1566$3736 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always @@ -287620,7 +287646,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end attribute \src "ls180.v:1570.12-1570.55" - process $proc$ls180.v:1570$3735 + process $proc$ls180.v:1570$3737 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always @@ -287628,7 +287654,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end attribute \src "ls180.v:1573.12-1573.59" - process $proc$ls180.v:1573$3736 + process $proc$ls180.v:1573$3738 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always @@ -287636,7 +287662,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end attribute \src "ls180.v:1577.12-1577.55" - process $proc$ls180.v:1577$3737 + process $proc$ls180.v:1577$3739 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always @@ -287644,7 +287670,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end attribute \src "ls180.v:1580.12-1580.59" - process $proc$ls180.v:1580$3738 + process $proc$ls180.v:1580$3740 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always @@ -287652,7 +287678,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end attribute \src "ls180.v:1584.12-1584.55" - process $proc$ls180.v:1584$3739 + process $proc$ls180.v:1584$3741 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always @@ -287660,7 +287686,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end attribute \src "ls180.v:1587.12-1587.59" - process $proc$ls180.v:1587$3740 + process $proc$ls180.v:1587$3742 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always @@ -287668,7 +287694,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end attribute \src "ls180.v:1591.12-1591.55" - process $proc$ls180.v:1591$3741 + process $proc$ls180.v:1591$3743 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always @@ -287676,7 +287702,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end attribute \src "ls180.v:1594.12-1594.54" - process $proc$ls180.v:1594$3742 + process $proc$ls180.v:1594$3744 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always @@ -287684,7 +287710,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end attribute \src "ls180.v:1595.12-1595.54" - process $proc$ls180.v:1595$3743 + process $proc$ls180.v:1595$3745 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always @@ -287692,7 +287718,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end attribute \src "ls180.v:1596.12-1596.54" - process $proc$ls180.v:1596$3744 + process $proc$ls180.v:1596$3746 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always @@ -287700,7 +287726,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end attribute \src "ls180.v:1597.12-1597.54" - process $proc$ls180.v:1597$3745 + process $proc$ls180.v:1597$3747 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always @@ -287708,7 +287734,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end attribute \src "ls180.v:1598.5-1598.48" - process $proc$ls180.v:1598$3746 + process $proc$ls180.v:1598$3748 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always @@ -287716,7 +287742,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end attribute \src "ls180.v:1599.5-1599.48" - process $proc$ls180.v:1599$3747 + process $proc$ls180.v:1599$3749 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always @@ -287724,7 +287750,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end attribute \src "ls180.v:1600.5-1600.48" - process $proc$ls180.v:1600$3748 + process $proc$ls180.v:1600$3750 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always @@ -287732,7 +287758,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end attribute \src "ls180.v:1601.5-1601.47" - process $proc$ls180.v:1601$3749 + process $proc$ls180.v:1601$3751 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always @@ -287740,7 +287766,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end attribute \src "ls180.v:1602.11-1602.61" - process $proc$ls180.v:1602$3750 + process $proc$ls180.v:1602$3752 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always @@ -287748,7 +287774,7 @@ module \ls180 update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end attribute \src "ls180.v:1603.5-1603.50" - process $proc$ls180.v:1603$3751 + process $proc$ls180.v:1603$3753 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always @@ -287756,7 +287782,7 @@ module \ls180 update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end attribute \src "ls180.v:1605.5-1605.50" - process $proc$ls180.v:1605$3752 + process $proc$ls180.v:1605$3754 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always @@ -287764,7 +287790,7 @@ module \ls180 sync init end attribute \src "ls180.v:1608.11-1608.47" - process $proc$ls180.v:1608$3753 + process $proc$ls180.v:1608$3755 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always @@ -287772,7 +287798,7 @@ module \ls180 update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end attribute \src "ls180.v:1609.11-1609.47" - process $proc$ls180.v:1609$3754 + process $proc$ls180.v:1609$3756 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always @@ -287780,7 +287806,7 @@ module \ls180 update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end attribute \src "ls180.v:1610.12-1610.58" - process $proc$ls180.v:1610$3755 + process $proc$ls180.v:1610$3757 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always @@ -287788,7 +287814,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end attribute \src "ls180.v:1614.12-1614.54" - process $proc$ls180.v:1614$3756 + process $proc$ls180.v:1614$3758 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always @@ -287796,7 +287822,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end attribute \src "ls180.v:1615.5-1615.46" - process $proc$ls180.v:1615$3757 + process $proc$ls180.v:1615$3759 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always @@ -287804,7 +287830,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end attribute \src "ls180.v:1617.12-1617.58" - process $proc$ls180.v:1617$3758 + process $proc$ls180.v:1617$3760 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always @@ -287812,7 +287838,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end attribute \src "ls180.v:1621.12-1621.54" - process $proc$ls180.v:1621$3759 + process $proc$ls180.v:1621$3761 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always @@ -287820,7 +287846,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end attribute \src "ls180.v:1622.5-1622.46" - process $proc$ls180.v:1622$3760 + process $proc$ls180.v:1622$3762 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always @@ -287828,7 +287854,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end attribute \src "ls180.v:1624.12-1624.58" - process $proc$ls180.v:1624$3761 + process $proc$ls180.v:1624$3763 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always @@ -287836,7 +287862,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end attribute \src "ls180.v:1628.12-1628.54" - process $proc$ls180.v:1628$3762 + process $proc$ls180.v:1628$3764 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always @@ -287844,7 +287870,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end attribute \src "ls180.v:1629.5-1629.46" - process $proc$ls180.v:1629$3763 + process $proc$ls180.v:1629$3765 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always @@ -287852,7 +287878,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end attribute \src "ls180.v:1631.12-1631.58" - process $proc$ls180.v:1631$3764 + process $proc$ls180.v:1631$3766 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always @@ -287860,7 +287886,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end attribute \src "ls180.v:1635.12-1635.54" - process $proc$ls180.v:1635$3765 + process $proc$ls180.v:1635$3767 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always @@ -287868,7 +287894,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end attribute \src "ls180.v:1636.5-1636.46" - process $proc$ls180.v:1636$3766 + process $proc$ls180.v:1636$3768 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always @@ -287876,7 +287902,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end attribute \src "ls180.v:1638.12-1638.53" - process $proc$ls180.v:1638$3767 + process $proc$ls180.v:1638$3769 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always @@ -287884,7 +287910,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end attribute \src "ls180.v:1639.12-1639.53" - process $proc$ls180.v:1639$3768 + process $proc$ls180.v:1639$3770 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always @@ -287892,7 +287918,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end attribute \src "ls180.v:1640.12-1640.53" - process $proc$ls180.v:1640$3769 + process $proc$ls180.v:1640$3771 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always @@ -287900,7 +287926,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end attribute \src "ls180.v:1641.12-1641.53" - process $proc$ls180.v:1641$3770 + process $proc$ls180.v:1641$3772 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always @@ -287908,7 +287934,7 @@ module \ls180 update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end attribute \src "ls180.v:1642.5-1642.43" - process $proc$ls180.v:1642$3771 + process $proc$ls180.v:1642$3773 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always @@ -287916,7 +287942,7 @@ module \ls180 update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end attribute \src "ls180.v:1643.12-1643.51" - process $proc$ls180.v:1643$3772 + process $proc$ls180.v:1643$3774 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always @@ -287924,7 +287950,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end attribute \src "ls180.v:1644.12-1644.51" - process $proc$ls180.v:1644$3773 + process $proc$ls180.v:1644$3775 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always @@ -287932,7 +287958,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end attribute \src "ls180.v:1645.12-1645.51" - process $proc$ls180.v:1645$3774 + process $proc$ls180.v:1645$3776 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always @@ -287940,7 +287966,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end attribute \src "ls180.v:1646.12-1646.51" - process $proc$ls180.v:1646$3775 + process $proc$ls180.v:1646$3777 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always @@ -287948,7 +287974,7 @@ module \ls180 update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end attribute \src "ls180.v:1648.11-1648.39" - process $proc$ls180.v:1648$3776 + process $proc$ls180.v:1648$3778 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always @@ -287956,7 +287982,7 @@ module \ls180 update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end attribute \src "ls180.v:1649.5-1649.32" - process $proc$ls180.v:1649$3777 + process $proc$ls180.v:1649$3779 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always @@ -287964,7 +287990,7 @@ module \ls180 update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end attribute \src "ls180.v:1650.5-1650.33" - process $proc$ls180.v:1650$3778 + process $proc$ls180.v:1650$3780 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always @@ -287972,7 +287998,7 @@ module \ls180 update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end attribute \src "ls180.v:1651.5-1651.35" - process $proc$ls180.v:1651$3779 + process $proc$ls180.v:1651$3781 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always @@ -287980,7 +288006,7 @@ module \ls180 update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end attribute \src "ls180.v:1653.12-1653.42" - process $proc$ls180.v:1653$3780 + process $proc$ls180.v:1653$3782 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always @@ -287988,7 +288014,7 @@ module \ls180 update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end attribute \src "ls180.v:1654.5-1654.33" - process $proc$ls180.v:1654$3781 + process $proc$ls180.v:1654$3783 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always @@ -287996,7 +288022,7 @@ module \ls180 update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end attribute \src "ls180.v:1655.5-1655.34" - process $proc$ls180.v:1655$3782 + process $proc$ls180.v:1655$3784 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always @@ -288004,7 +288030,7 @@ module \ls180 update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end attribute \src "ls180.v:1656.5-1656.36" - process $proc$ls180.v:1656$3783 + process $proc$ls180.v:1656$3785 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always @@ -288012,7 +288038,7 @@ module \ls180 update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end attribute \src "ls180.v:1665.11-1665.41" - process $proc$ls180.v:1665$3784 + process $proc$ls180.v:1665$3786 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always @@ -288020,7 +288046,7 @@ module \ls180 sync init end attribute \src "ls180.v:1666.11-1666.41" - process $proc$ls180.v:1666$3785 + process $proc$ls180.v:1666$3787 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always @@ -288028,7 +288054,7 @@ module \ls180 sync init end attribute \src "ls180.v:1689.11-1689.45" - process $proc$ls180.v:1689$3786 + process $proc$ls180.v:1689$3788 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always @@ -288036,7 +288062,7 @@ module \ls180 update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end attribute \src "ls180.v:1690.5-1690.41" - process $proc$ls180.v:1690$3787 + process $proc$ls180.v:1690$3789 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always @@ -288044,7 +288070,7 @@ module \ls180 sync init end attribute \src "ls180.v:1691.11-1691.47" - process $proc$ls180.v:1691$3788 + process $proc$ls180.v:1691$3790 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always @@ -288052,7 +288078,7 @@ module \ls180 update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end attribute \src "ls180.v:1692.11-1692.47" - process $proc$ls180.v:1692$3789 + process $proc$ls180.v:1692$3791 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always @@ -288060,15 +288086,23 @@ module \ls180 update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end attribute \src "ls180.v:1693.11-1693.50" - process $proc$ls180.v:1693$3790 + process $proc$ls180.v:1693$3792 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end + attribute \src "ls180.v:171.12-171.74" + process $proc$ls180.v:171$3152 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end attribute \src "ls180.v:1713.5-1713.51" - process $proc$ls180.v:1713$3791 + process $proc$ls180.v:1713$3793 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always @@ -288076,7 +288110,7 @@ module \ls180 update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end attribute \src "ls180.v:1714.5-1714.50" - process $proc$ls180.v:1714$3792 + process $proc$ls180.v:1714$3794 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always @@ -288084,7 +288118,7 @@ module \ls180 update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end attribute \src "ls180.v:1715.12-1715.66" - process $proc$ls180.v:1715$3793 + process $proc$ls180.v:1715$3795 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288092,7 +288126,7 @@ module \ls180 update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end attribute \src "ls180.v:1716.11-1716.77" - process $proc$ls180.v:1716$3794 + process $proc$ls180.v:1716$3796 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always @@ -288100,7 +288134,7 @@ module \ls180 update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end attribute \src "ls180.v:1717.11-1717.50" - process $proc$ls180.v:1717$3795 + process $proc$ls180.v:1717$3797 assign { } { } assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always @@ -288108,7 +288142,7 @@ module \ls180 update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end attribute \src "ls180.v:1719.5-1719.49" - process $proc$ls180.v:1719$3796 + process $proc$ls180.v:1719$3798 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always @@ -288116,7 +288150,7 @@ module \ls180 update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end attribute \src "ls180.v:1725.5-1725.45" - process $proc$ls180.v:1725$3797 + process $proc$ls180.v:1725$3799 assign { } { } assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always @@ -288124,7 +288158,7 @@ module \ls180 update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end attribute \src "ls180.v:1727.12-1727.62" - process $proc$ls180.v:1727$3798 + process $proc$ls180.v:1727$3800 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always @@ -288132,7 +288166,7 @@ module \ls180 update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end attribute \src "ls180.v:1728.12-1728.60" - process $proc$ls180.v:1728$3799 + process $proc$ls180.v:1728$3801 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288140,7 +288174,7 @@ module \ls180 update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end attribute \src "ls180.v:1730.5-1730.57" - process $proc$ls180.v:1730$3800 + process $proc$ls180.v:1730$3802 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always @@ -288148,7 +288182,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end attribute \src "ls180.v:1734.12-1734.67" - process $proc$ls180.v:1734$3801 + process $proc$ls180.v:1734$3803 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288156,7 +288190,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end attribute \src "ls180.v:1735.5-1735.54" - process $proc$ls180.v:1735$3802 + process $proc$ls180.v:1735$3804 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always @@ -288164,7 +288198,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end attribute \src "ls180.v:1736.12-1736.69" - process $proc$ls180.v:1736$3803 + process $proc$ls180.v:1736$3805 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always @@ -288172,7 +288206,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end attribute \src "ls180.v:1737.5-1737.56" - process $proc$ls180.v:1737$3804 + process $proc$ls180.v:1737$3806 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always @@ -288180,7 +288214,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end attribute \src "ls180.v:1738.5-1738.61" - process $proc$ls180.v:1738$3805 + process $proc$ls180.v:1738$3807 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always @@ -288188,7 +288222,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end attribute \src "ls180.v:1739.5-1739.56" - process $proc$ls180.v:1739$3806 + process $proc$ls180.v:1739$3808 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always @@ -288196,7 +288230,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end attribute \src "ls180.v:1740.5-1740.53" - process $proc$ls180.v:1740$3807 + process $proc$ls180.v:1740$3809 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always @@ -288204,7 +288238,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end attribute \src "ls180.v:1742.5-1742.59" - process $proc$ls180.v:1742$3808 + process $proc$ls180.v:1742$3810 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always @@ -288212,7 +288246,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end attribute \src "ls180.v:1743.5-1743.54" - process $proc$ls180.v:1743$3809 + process $proc$ls180.v:1743$3811 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always @@ -288220,7 +288254,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end attribute \src "ls180.v:1745.12-1745.61" - process $proc$ls180.v:1745$3810 + process $proc$ls180.v:1745$3812 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always @@ -288228,7 +288262,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end attribute \src "ls180.v:1748.12-1748.43" - process $proc$ls180.v:1748$3811 + process $proc$ls180.v:1748$3813 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always @@ -288236,15 +288270,23 @@ module \ls180 update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end attribute \src "ls180.v:1749.12-1749.45" - process $proc$ls180.v:1749$3812 + process $proc$ls180.v:1749$3814 assign { } { } assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end + attribute \src "ls180.v:175.5-175.69" + process $proc$ls180.v:175$3153 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end attribute \src "ls180.v:1751.11-1751.41" - process $proc$ls180.v:1751$3813 + process $proc$ls180.v:1751$3815 assign { } { } assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always @@ -288252,7 +288294,7 @@ module \ls180 update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end attribute \src "ls180.v:1752.5-1752.35" - process $proc$ls180.v:1752$3814 + process $proc$ls180.v:1752$3816 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always @@ -288260,7 +288302,7 @@ module \ls180 update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end attribute \src "ls180.v:1753.5-1753.35" - process $proc$ls180.v:1753$3815 + process $proc$ls180.v:1753$3817 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always @@ -288268,7 +288310,7 @@ module \ls180 update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end attribute \src "ls180.v:1755.5-1755.34" - process $proc$ls180.v:1755$3816 + process $proc$ls180.v:1755$3818 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always @@ -288276,7 +288318,7 @@ module \ls180 update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end attribute \src "ls180.v:1756.11-1756.41" - process $proc$ls180.v:1756$3817 + process $proc$ls180.v:1756$3819 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always @@ -288284,23 +288326,15 @@ module \ls180 sync init end attribute \src "ls180.v:1757.11-1757.41" - process $proc$ls180.v:1757$3818 + process $proc$ls180.v:1757$3820 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:176.5-176.69" - process $proc$ls180.v:176$3150 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end attribute \src "ls180.v:1764.5-1764.43" - process $proc$ls180.v:1764$3819 + process $proc$ls180.v:1764$3821 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always @@ -288308,7 +288342,7 @@ module \ls180 update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end attribute \src "ls180.v:1765.5-1765.43" - process $proc$ls180.v:1765$3820 + process $proc$ls180.v:1765$3822 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always @@ -288316,7 +288350,7 @@ module \ls180 update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end attribute \src "ls180.v:1766.5-1766.42" - process $proc$ls180.v:1766$3821 + process $proc$ls180.v:1766$3823 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always @@ -288324,7 +288358,7 @@ module \ls180 update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end attribute \src "ls180.v:1767.12-1767.61" - process $proc$ls180.v:1767$3822 + process $proc$ls180.v:1767$3824 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always @@ -288332,7 +288366,7 @@ module \ls180 update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end attribute \src "ls180.v:1768.5-1768.45" - process $proc$ls180.v:1768$3823 + process $proc$ls180.v:1768$3825 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always @@ -288340,7 +288374,7 @@ module \ls180 update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end attribute \src "ls180.v:1770.5-1770.45" - process $proc$ls180.v:1770$3824 + process $proc$ls180.v:1770$3826 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always @@ -288348,7 +288382,7 @@ module \ls180 sync init end attribute \src "ls180.v:1771.5-1771.44" - process $proc$ls180.v:1771$3825 + process $proc$ls180.v:1771$3827 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always @@ -288356,7 +288390,7 @@ module \ls180 update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end attribute \src "ls180.v:1772.12-1772.60" - process $proc$ls180.v:1772$3826 + process $proc$ls180.v:1772$3828 assign { } { } assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288364,7 +288398,7 @@ module \ls180 update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end attribute \src "ls180.v:1773.12-1773.45" - process $proc$ls180.v:1773$3827 + process $proc$ls180.v:1773$3829 assign { } { } assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288372,7 +288406,7 @@ module \ls180 update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end attribute \src "ls180.v:1774.12-1774.53" - process $proc$ls180.v:1774$3828 + process $proc$ls180.v:1774$3830 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -288380,7 +288414,7 @@ module \ls180 update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end attribute \src "ls180.v:1775.5-1775.40" - process $proc$ls180.v:1775$3829 + process $proc$ls180.v:1775$3831 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always @@ -288388,7 +288422,7 @@ module \ls180 update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end attribute \src "ls180.v:1776.12-1776.55" - process $proc$ls180.v:1776$3830 + process $proc$ls180.v:1776$3832 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always @@ -288396,7 +288430,7 @@ module \ls180 update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end attribute \src "ls180.v:1777.5-1777.42" - process $proc$ls180.v:1777$3831 + process $proc$ls180.v:1777$3833 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always @@ -288404,7 +288438,7 @@ module \ls180 update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end attribute \src "ls180.v:1778.5-1778.47" - process $proc$ls180.v:1778$3832 + process $proc$ls180.v:1778$3834 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always @@ -288412,7 +288446,7 @@ module \ls180 update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end attribute \src "ls180.v:1779.5-1779.42" - process $proc$ls180.v:1779$3833 + process $proc$ls180.v:1779$3835 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always @@ -288420,7 +288454,7 @@ module \ls180 update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end attribute \src "ls180.v:1780.5-1780.44" - process $proc$ls180.v:1780$3834 + process $proc$ls180.v:1780$3836 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always @@ -288428,7 +288462,7 @@ module \ls180 update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end attribute \src "ls180.v:1782.5-1782.45" - process $proc$ls180.v:1782$3835 + process $proc$ls180.v:1782$3837 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always @@ -288436,7 +288470,7 @@ module \ls180 update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end attribute \src "ls180.v:1783.5-1783.40" - process $proc$ls180.v:1783$3836 + process $proc$ls180.v:1783$3838 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always @@ -288444,7 +288478,7 @@ module \ls180 update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end attribute \src "ls180.v:1787.12-1787.47" - process $proc$ls180.v:1787$3837 + process $proc$ls180.v:1787$3839 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always @@ -288452,7 +288486,7 @@ module \ls180 update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end attribute \src "ls180.v:1799.11-1799.64" - process $proc$ls180.v:1799$3838 + process $proc$ls180.v:1799$3840 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always @@ -288460,23 +288494,15 @@ module \ls180 update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end attribute \src "ls180.v:1801.11-1801.48" - process $proc$ls180.v:1801$3839 + process $proc$ls180.v:1801$3841 assign { } { } assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:181.5-181.72" - process $proc$ls180.v:181$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end attribute \src "ls180.v:1825.11-1825.45" - process $proc$ls180.v:1825$3840 + process $proc$ls180.v:1825$3842 assign { } { } assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always @@ -288484,7 +288510,7 @@ module \ls180 update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end attribute \src "ls180.v:1826.5-1826.41" - process $proc$ls180.v:1826$3841 + process $proc$ls180.v:1826$3843 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always @@ -288492,7 +288518,7 @@ module \ls180 sync init end attribute \src "ls180.v:1827.11-1827.47" - process $proc$ls180.v:1827$3842 + process $proc$ls180.v:1827$3844 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always @@ -288500,7 +288526,7 @@ module \ls180 update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end attribute \src "ls180.v:1828.11-1828.47" - process $proc$ls180.v:1828$3843 + process $proc$ls180.v:1828$3845 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always @@ -288508,23 +288534,15 @@ module \ls180 update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end attribute \src "ls180.v:1829.11-1829.50" - process $proc$ls180.v:1829$3844 + process $proc$ls180.v:1829$3846 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:184.11-184.79" - process $proc$ls180.v:184$3152 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end attribute \src "ls180.v:1842.5-1842.36" - process $proc$ls180.v:1842$3845 + process $proc$ls180.v:1842$3847 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always @@ -288532,7 +288550,7 @@ module \ls180 update \builder_converter0_state $1\builder_converter0_state[0:0] end attribute \src "ls180.v:1843.5-1843.41" - process $proc$ls180.v:1843$3846 + process $proc$ls180.v:1843$3848 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always @@ -288540,7 +288558,7 @@ module \ls180 update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end attribute \src "ls180.v:1844.5-1844.57" - process $proc$ls180.v:1844$3847 + process $proc$ls180.v:1844$3849 assign { } { } assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always @@ -288548,7 +288566,7 @@ module \ls180 update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end attribute \src "ls180.v:1845.5-1845.60" - process $proc$ls180.v:1845$3848 + process $proc$ls180.v:1845$3850 assign { } { } assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always @@ -288556,7 +288574,7 @@ module \ls180 update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end attribute \src "ls180.v:1846.5-1846.36" - process $proc$ls180.v:1846$3849 + process $proc$ls180.v:1846$3851 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always @@ -288564,7 +288582,7 @@ module \ls180 update \builder_converter1_state $1\builder_converter1_state[0:0] end attribute \src "ls180.v:1847.5-1847.41" - process $proc$ls180.v:1847$3850 + process $proc$ls180.v:1847$3852 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always @@ -288572,7 +288590,7 @@ module \ls180 update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end attribute \src "ls180.v:1848.5-1848.57" - process $proc$ls180.v:1848$3851 + process $proc$ls180.v:1848$3853 assign { } { } assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always @@ -288580,7 +288598,7 @@ module \ls180 update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end attribute \src "ls180.v:1849.5-1849.60" - process $proc$ls180.v:1849$3852 + process $proc$ls180.v:1849$3854 assign { } { } assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always @@ -288588,7 +288606,7 @@ module \ls180 update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end attribute \src "ls180.v:1850.5-1850.36" - process $proc$ls180.v:1850$3853 + process $proc$ls180.v:1850$3855 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always @@ -288596,7 +288614,7 @@ module \ls180 update \builder_converter2_state $1\builder_converter2_state[0:0] end attribute \src "ls180.v:1851.5-1851.41" - process $proc$ls180.v:1851$3854 + process $proc$ls180.v:1851$3856 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always @@ -288604,7 +288622,7 @@ module \ls180 update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end attribute \src "ls180.v:1852.5-1852.60" - process $proc$ls180.v:1852$3855 + process $proc$ls180.v:1852$3857 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always @@ -288612,7 +288630,7 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end attribute \src "ls180.v:1853.5-1853.63" - process $proc$ls180.v:1853$3856 + process $proc$ls180.v:1853$3858 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always @@ -288620,7 +288638,7 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end attribute \src "ls180.v:1854.11-1854.41" - process $proc$ls180.v:1854$3857 + process $proc$ls180.v:1854$3859 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always @@ -288628,7 +288646,7 @@ module \ls180 update \builder_refresher_state $1\builder_refresher_state[1:0] end attribute \src "ls180.v:1855.11-1855.46" - process $proc$ls180.v:1855$3858 + process $proc$ls180.v:1855$3860 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always @@ -288636,7 +288654,7 @@ module \ls180 update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end attribute \src "ls180.v:1856.11-1856.44" - process $proc$ls180.v:1856$3859 + process $proc$ls180.v:1856$3861 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always @@ -288644,7 +288662,7 @@ module \ls180 update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end attribute \src "ls180.v:1857.11-1857.49" - process $proc$ls180.v:1857$3860 + process $proc$ls180.v:1857$3862 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always @@ -288652,7 +288670,7 @@ module \ls180 update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end attribute \src "ls180.v:1858.11-1858.44" - process $proc$ls180.v:1858$3861 + process $proc$ls180.v:1858$3863 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always @@ -288660,7 +288678,7 @@ module \ls180 update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end attribute \src "ls180.v:1859.11-1859.49" - process $proc$ls180.v:1859$3862 + process $proc$ls180.v:1859$3864 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always @@ -288668,7 +288686,7 @@ module \ls180 update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end attribute \src "ls180.v:1860.11-1860.44" - process $proc$ls180.v:1860$3863 + process $proc$ls180.v:1860$3865 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always @@ -288676,7 +288694,7 @@ module \ls180 update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end attribute \src "ls180.v:1861.11-1861.49" - process $proc$ls180.v:1861$3864 + process $proc$ls180.v:1861$3866 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always @@ -288684,7 +288702,7 @@ module \ls180 update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end attribute \src "ls180.v:1862.11-1862.44" - process $proc$ls180.v:1862$3865 + process $proc$ls180.v:1862$3867 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always @@ -288692,7 +288710,7 @@ module \ls180 update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end attribute \src "ls180.v:1863.11-1863.49" - process $proc$ls180.v:1863$3866 + process $proc$ls180.v:1863$3868 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always @@ -288700,7 +288718,7 @@ module \ls180 update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end attribute \src "ls180.v:1864.11-1864.43" - process $proc$ls180.v:1864$3867 + process $proc$ls180.v:1864$3869 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always @@ -288708,7 +288726,7 @@ module \ls180 update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end attribute \src "ls180.v:1865.11-1865.48" - process $proc$ls180.v:1865$3868 + process $proc$ls180.v:1865$3870 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always @@ -288716,7 +288734,7 @@ module \ls180 update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end attribute \src "ls180.v:1878.5-1878.27" - process $proc$ls180.v:1878$3869 + process $proc$ls180.v:1878$3871 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always @@ -288724,23 +288742,15 @@ module \ls180 sync init end attribute \src "ls180.v:1879.5-1879.27" - process $proc$ls180.v:1879$3870 + process $proc$ls180.v:1879$3872 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:188.12-188.78" - process $proc$ls180.v:188$3153 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end attribute \src "ls180.v:1880.5-1880.27" - process $proc$ls180.v:1880$3871 + process $proc$ls180.v:1880$3873 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always @@ -288748,7 +288758,7 @@ module \ls180 sync init end attribute \src "ls180.v:1881.5-1881.27" - process $proc$ls180.v:1881$3872 + process $proc$ls180.v:1881$3874 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always @@ -288756,7 +288766,7 @@ module \ls180 sync init end attribute \src "ls180.v:1882.5-1882.42" - process $proc$ls180.v:1882$3873 + process $proc$ls180.v:1882$3875 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always @@ -288764,7 +288774,7 @@ module \ls180 update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end attribute \src "ls180.v:1883.5-1883.43" - process $proc$ls180.v:1883$3874 + process $proc$ls180.v:1883$3876 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always @@ -288772,7 +288782,7 @@ module \ls180 update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end attribute \src "ls180.v:1884.5-1884.43" - process $proc$ls180.v:1884$3875 + process $proc$ls180.v:1884$3877 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always @@ -288780,7 +288790,7 @@ module \ls180 update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end attribute \src "ls180.v:1885.5-1885.43" - process $proc$ls180.v:1885$3876 + process $proc$ls180.v:1885$3878 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always @@ -288788,7 +288798,7 @@ module \ls180 update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end attribute \src "ls180.v:1886.5-1886.43" - process $proc$ls180.v:1886$3877 + process $proc$ls180.v:1886$3879 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always @@ -288796,7 +288806,7 @@ module \ls180 update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end attribute \src "ls180.v:1887.5-1887.35" - process $proc$ls180.v:1887$3878 + process $proc$ls180.v:1887$3880 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always @@ -288804,7 +288814,7 @@ module \ls180 update \builder_converter_state $1\builder_converter_state[0:0] end attribute \src "ls180.v:1888.5-1888.40" - process $proc$ls180.v:1888$3879 + process $proc$ls180.v:1888$3881 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always @@ -288812,15 +288822,23 @@ module \ls180 update \builder_converter_next_state $1\builder_converter_next_state[0:0] end attribute \src "ls180.v:1889.5-1889.55" - process $proc$ls180.v:1889$3880 + process $proc$ls180.v:1889$3882 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end + attribute \src "ls180.v:189.12-189.78" + process $proc$ls180.v:189$3154 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end attribute \src "ls180.v:1890.5-1890.58" - process $proc$ls180.v:1890$3881 + process $proc$ls180.v:1890$3883 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always @@ -288828,7 +288846,7 @@ module \ls180 update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end attribute \src "ls180.v:1891.11-1891.42" - process $proc$ls180.v:1891$3882 + process $proc$ls180.v:1891$3884 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always @@ -288836,7 +288854,7 @@ module \ls180 update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end attribute \src "ls180.v:1892.11-1892.47" - process $proc$ls180.v:1892$3883 + process $proc$ls180.v:1892$3885 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always @@ -288844,7 +288862,7 @@ module \ls180 update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end attribute \src "ls180.v:1893.11-1893.62" - process $proc$ls180.v:1893$3884 + process $proc$ls180.v:1893$3886 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always @@ -288852,7 +288870,7 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end attribute \src "ls180.v:1894.5-1894.59" - process $proc$ls180.v:1894$3885 + process $proc$ls180.v:1894$3887 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always @@ -288860,7 +288878,7 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end attribute \src "ls180.v:1895.11-1895.42" - process $proc$ls180.v:1895$3886 + process $proc$ls180.v:1895$3888 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always @@ -288868,7 +288886,7 @@ module \ls180 update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end attribute \src "ls180.v:1896.11-1896.47" - process $proc$ls180.v:1896$3887 + process $proc$ls180.v:1896$3889 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always @@ -288876,7 +288894,7 @@ module \ls180 update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end attribute \src "ls180.v:1897.11-1897.60" - process $proc$ls180.v:1897$3888 + process $proc$ls180.v:1897$3890 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always @@ -288884,7 +288902,7 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end attribute \src "ls180.v:1898.5-1898.57" - process $proc$ls180.v:1898$3889 + process $proc$ls180.v:1898$3891 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always @@ -288892,7 +288910,7 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end attribute \src "ls180.v:1899.5-1899.41" - process $proc$ls180.v:1899$3890 + process $proc$ls180.v:1899$3892 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always @@ -288900,7 +288918,7 @@ module \ls180 update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end attribute \src "ls180.v:1900.5-1900.46" - process $proc$ls180.v:1900$3891 + process $proc$ls180.v:1900$3893 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always @@ -288908,7 +288926,7 @@ module \ls180 update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end attribute \src "ls180.v:1901.11-1901.66" - process $proc$ls180.v:1901$3892 + process $proc$ls180.v:1901$3894 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always @@ -288916,7 +288934,7 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end attribute \src "ls180.v:1902.5-1902.63" - process $proc$ls180.v:1902$3893 + process $proc$ls180.v:1902$3895 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always @@ -288924,7 +288942,7 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end attribute \src "ls180.v:1903.11-1903.47" - process $proc$ls180.v:1903$3894 + process $proc$ls180.v:1903$3896 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always @@ -288932,7 +288950,7 @@ module \ls180 update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end attribute \src "ls180.v:1904.11-1904.52" - process $proc$ls180.v:1904$3895 + process $proc$ls180.v:1904$3897 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always @@ -288940,7 +288958,7 @@ module \ls180 update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end attribute \src "ls180.v:1905.11-1905.66" - process $proc$ls180.v:1905$3896 + process $proc$ls180.v:1905$3898 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always @@ -288948,7 +288966,7 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end attribute \src "ls180.v:1906.5-1906.63" - process $proc$ls180.v:1906$3897 + process $proc$ls180.v:1906$3899 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always @@ -288956,7 +288974,7 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end attribute \src "ls180.v:1907.11-1907.47" - process $proc$ls180.v:1907$3898 + process $proc$ls180.v:1907$3900 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always @@ -288964,7 +288982,7 @@ module \ls180 update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end attribute \src "ls180.v:1908.11-1908.52" - process $proc$ls180.v:1908$3899 + process $proc$ls180.v:1908$3901 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always @@ -288972,7 +288990,7 @@ module \ls180 update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end attribute \src "ls180.v:1909.11-1909.67" - process $proc$ls180.v:1909$3900 + process $proc$ls180.v:1909$3902 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always @@ -288980,7 +288998,7 @@ module \ls180 update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end attribute \src "ls180.v:1910.5-1910.64" - process $proc$ls180.v:1910$3901 + process $proc$ls180.v:1910$3903 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always @@ -288988,7 +289006,7 @@ module \ls180 update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end attribute \src "ls180.v:1911.12-1911.71" - process $proc$ls180.v:1911$3902 + process $proc$ls180.v:1911$3904 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always @@ -288996,7 +289014,7 @@ module \ls180 update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end attribute \src "ls180.v:1912.5-1912.66" - process $proc$ls180.v:1912$3903 + process $proc$ls180.v:1912$3905 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always @@ -289004,7 +289022,7 @@ module \ls180 update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end attribute \src "ls180.v:1913.5-1913.66" - process $proc$ls180.v:1913$3904 + process $proc$ls180.v:1913$3906 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always @@ -289012,7 +289030,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end attribute \src "ls180.v:1914.5-1914.69" - process $proc$ls180.v:1914$3905 + process $proc$ls180.v:1914$3907 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always @@ -289020,7 +289038,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end attribute \src "ls180.v:1915.5-1915.41" - process $proc$ls180.v:1915$3906 + process $proc$ls180.v:1915$3908 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always @@ -289028,7 +289046,7 @@ module \ls180 update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end attribute \src "ls180.v:1916.5-1916.46" - process $proc$ls180.v:1916$3907 + process $proc$ls180.v:1916$3909 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always @@ -289036,7 +289054,7 @@ module \ls180 update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end attribute \src "ls180.v:1917.5-1917.66" - process $proc$ls180.v:1917$3908 + process $proc$ls180.v:1917$3910 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always @@ -289044,7 +289062,7 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end attribute \src "ls180.v:1918.5-1918.69" - process $proc$ls180.v:1918$3909 + process $proc$ls180.v:1918$3911 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always @@ -289052,7 +289070,7 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end attribute \src "ls180.v:1919.11-1919.41" - process $proc$ls180.v:1919$3910 + process $proc$ls180.v:1919$3912 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always @@ -289060,7 +289078,7 @@ module \ls180 update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end attribute \src "ls180.v:1920.11-1920.46" - process $proc$ls180.v:1920$3911 + process $proc$ls180.v:1920$3913 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always @@ -289068,7 +289086,7 @@ module \ls180 update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end attribute \src "ls180.v:1921.11-1921.61" - process $proc$ls180.v:1921$3912 + process $proc$ls180.v:1921$3914 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always @@ -289076,7 +289094,7 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end attribute \src "ls180.v:1922.5-1922.58" - process $proc$ls180.v:1922$3913 + process $proc$ls180.v:1922$3915 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always @@ -289084,7 +289102,7 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end attribute \src "ls180.v:1923.11-1923.48" - process $proc$ls180.v:1923$3914 + process $proc$ls180.v:1923$3916 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always @@ -289092,7 +289110,7 @@ module \ls180 update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end attribute \src "ls180.v:1924.11-1924.53" - process $proc$ls180.v:1924$3915 + process $proc$ls180.v:1924$3917 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always @@ -289100,7 +289118,7 @@ module \ls180 update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end attribute \src "ls180.v:1925.11-1925.70" - process $proc$ls180.v:1925$3916 + process $proc$ls180.v:1925$3918 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always @@ -289108,7 +289126,7 @@ module \ls180 update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end attribute \src "ls180.v:1926.5-1926.66" - process $proc$ls180.v:1926$3917 + process $proc$ls180.v:1926$3919 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always @@ -289116,7 +289134,7 @@ module \ls180 update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end attribute \src "ls180.v:1927.12-1927.73" - process $proc$ls180.v:1927$3918 + process $proc$ls180.v:1927$3920 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always @@ -289124,7 +289142,7 @@ module \ls180 update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end attribute \src "ls180.v:1928.5-1928.68" - process $proc$ls180.v:1928$3919 + process $proc$ls180.v:1928$3921 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always @@ -289132,7 +289150,7 @@ module \ls180 update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end attribute \src "ls180.v:1929.5-1929.69" - process $proc$ls180.v:1929$3920 + process $proc$ls180.v:1929$3922 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always @@ -289140,7 +289158,7 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end attribute \src "ls180.v:1930.5-1930.72" - process $proc$ls180.v:1930$3921 + process $proc$ls180.v:1930$3923 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always @@ -289148,7 +289166,7 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end attribute \src "ls180.v:1931.5-1931.52" - process $proc$ls180.v:1931$3922 + process $proc$ls180.v:1931$3924 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always @@ -289156,7 +289174,7 @@ module \ls180 update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end attribute \src "ls180.v:1932.5-1932.57" - process $proc$ls180.v:1932$3923 + process $proc$ls180.v:1932$3925 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always @@ -289164,7 +289182,7 @@ module \ls180 update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end attribute \src "ls180.v:1933.12-1933.93" - process $proc$ls180.v:1933$3924 + process $proc$ls180.v:1933$3926 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always @@ -289172,7 +289190,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end attribute \src "ls180.v:1934.5-1934.88" - process $proc$ls180.v:1934$3925 + process $proc$ls180.v:1934$3927 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always @@ -289180,7 +289198,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end attribute \src "ls180.v:1935.12-1935.93" - process $proc$ls180.v:1935$3926 + process $proc$ls180.v:1935$3928 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always @@ -289188,7 +289206,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end attribute \src "ls180.v:1936.5-1936.88" - process $proc$ls180.v:1936$3927 + process $proc$ls180.v:1936$3929 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always @@ -289196,7 +289214,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end attribute \src "ls180.v:1937.12-1937.93" - process $proc$ls180.v:1937$3928 + process $proc$ls180.v:1937$3930 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always @@ -289204,7 +289222,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end attribute \src "ls180.v:1938.5-1938.88" - process $proc$ls180.v:1938$3929 + process $proc$ls180.v:1938$3931 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always @@ -289212,7 +289230,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end attribute \src "ls180.v:1939.12-1939.93" - process $proc$ls180.v:1939$3930 + process $proc$ls180.v:1939$3932 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always @@ -289220,7 +289238,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end attribute \src "ls180.v:1940.5-1940.88" - process $proc$ls180.v:1940$3931 + process $proc$ls180.v:1940$3933 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always @@ -289228,7 +289246,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end attribute \src "ls180.v:1941.11-1941.87" - process $proc$ls180.v:1941$3932 + process $proc$ls180.v:1941$3934 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always @@ -289236,7 +289254,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end attribute \src "ls180.v:1942.5-1942.84" - process $proc$ls180.v:1942$3933 + process $proc$ls180.v:1942$3935 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always @@ -289244,7 +289262,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end attribute \src "ls180.v:1943.11-1943.42" - process $proc$ls180.v:1943$3934 + process $proc$ls180.v:1943$3936 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always @@ -289252,7 +289270,7 @@ module \ls180 update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end attribute \src "ls180.v:1944.11-1944.47" - process $proc$ls180.v:1944$3935 + process $proc$ls180.v:1944$3937 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always @@ -289260,7 +289278,7 @@ module \ls180 update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end attribute \src "ls180.v:1945.5-1945.55" - process $proc$ls180.v:1945$3936 + process $proc$ls180.v:1945$3938 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always @@ -289268,7 +289286,7 @@ module \ls180 update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end attribute \src "ls180.v:1946.5-1946.58" - process $proc$ls180.v:1946$3937 + process $proc$ls180.v:1946$3939 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always @@ -289276,7 +289294,7 @@ module \ls180 update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end attribute \src "ls180.v:1947.5-1947.56" - process $proc$ls180.v:1947$3938 + process $proc$ls180.v:1947$3940 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always @@ -289284,7 +289302,7 @@ module \ls180 update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end attribute \src "ls180.v:1948.5-1948.59" - process $proc$ls180.v:1948$3939 + process $proc$ls180.v:1948$3941 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always @@ -289292,7 +289310,7 @@ module \ls180 update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end attribute \src "ls180.v:1949.11-1949.62" - process $proc$ls180.v:1949$3940 + process $proc$ls180.v:1949$3942 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always @@ -289300,7 +289318,7 @@ module \ls180 update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end attribute \src "ls180.v:1950.5-1950.59" - process $proc$ls180.v:1950$3941 + process $proc$ls180.v:1950$3943 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always @@ -289308,7 +289326,7 @@ module \ls180 update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end attribute \src "ls180.v:1951.12-1951.65" - process $proc$ls180.v:1951$3942 + process $proc$ls180.v:1951$3944 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always @@ -289316,7 +289334,7 @@ module \ls180 update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end attribute \src "ls180.v:1952.5-1952.60" - process $proc$ls180.v:1952$3943 + process $proc$ls180.v:1952$3945 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always @@ -289324,7 +289342,7 @@ module \ls180 update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end attribute \src "ls180.v:1953.5-1953.56" - process $proc$ls180.v:1953$3944 + process $proc$ls180.v:1953$3946 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always @@ -289332,7 +289350,7 @@ module \ls180 update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end attribute \src "ls180.v:1954.5-1954.59" - process $proc$ls180.v:1954$3945 + process $proc$ls180.v:1954$3947 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always @@ -289340,7 +289358,7 @@ module \ls180 update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end attribute \src "ls180.v:1955.5-1955.58" - process $proc$ls180.v:1955$3946 + process $proc$ls180.v:1955$3948 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always @@ -289348,7 +289366,7 @@ module \ls180 update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end attribute \src "ls180.v:1956.5-1956.61" - process $proc$ls180.v:1956$3947 + process $proc$ls180.v:1956$3949 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always @@ -289356,7 +289374,7 @@ module \ls180 update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end attribute \src "ls180.v:1957.5-1957.57" - process $proc$ls180.v:1957$3948 + process $proc$ls180.v:1957$3950 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always @@ -289364,7 +289382,7 @@ module \ls180 update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end attribute \src "ls180.v:1958.5-1958.60" - process $proc$ls180.v:1958$3949 + process $proc$ls180.v:1958$3951 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always @@ -289372,7 +289390,7 @@ module \ls180 update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end attribute \src "ls180.v:1959.5-1959.59" - process $proc$ls180.v:1959$3950 + process $proc$ls180.v:1959$3952 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always @@ -289380,7 +289398,7 @@ module \ls180 update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end attribute \src "ls180.v:1960.5-1960.62" - process $proc$ls180.v:1960$3951 + process $proc$ls180.v:1960$3953 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always @@ -289388,7 +289406,7 @@ module \ls180 update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end attribute \src "ls180.v:1961.13-1961.76" - process $proc$ls180.v:1961$3952 + process $proc$ls180.v:1961$3954 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always @@ -289396,7 +289414,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end attribute \src "ls180.v:1962.5-1962.69" - process $proc$ls180.v:1962$3953 + process $proc$ls180.v:1962$3955 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always @@ -289404,7 +289422,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end attribute \src "ls180.v:1963.11-1963.46" - process $proc$ls180.v:1963$3954 + process $proc$ls180.v:1963$3956 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always @@ -289412,7 +289430,7 @@ module \ls180 update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end attribute \src "ls180.v:1964.11-1964.51" - process $proc$ls180.v:1964$3955 + process $proc$ls180.v:1964$3957 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always @@ -289420,7 +289438,7 @@ module \ls180 update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end attribute \src "ls180.v:1965.12-1965.87" - process $proc$ls180.v:1965$3956 + process $proc$ls180.v:1965$3958 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always @@ -289428,7 +289446,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end attribute \src "ls180.v:1966.5-1966.82" - process $proc$ls180.v:1966$3957 + process $proc$ls180.v:1966$3959 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always @@ -289436,7 +289454,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end attribute \src "ls180.v:1967.5-1967.44" - process $proc$ls180.v:1967$3958 + process $proc$ls180.v:1967$3960 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always @@ -289444,7 +289462,7 @@ module \ls180 update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end attribute \src "ls180.v:1968.5-1968.49" - process $proc$ls180.v:1968$3959 + process $proc$ls180.v:1968$3961 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always @@ -289452,7 +289470,7 @@ module \ls180 update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end attribute \src "ls180.v:1969.12-1969.75" - process $proc$ls180.v:1969$3960 + process $proc$ls180.v:1969$3962 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -289460,7 +289478,7 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end attribute \src "ls180.v:1970.5-1970.70" - process $proc$ls180.v:1970$3961 + process $proc$ls180.v:1970$3963 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always @@ -289468,7 +289486,7 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end attribute \src "ls180.v:1971.11-1971.60" - process $proc$ls180.v:1971$3962 + process $proc$ls180.v:1971$3964 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always @@ -289476,7 +289494,7 @@ module \ls180 update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end attribute \src "ls180.v:1972.11-1972.65" - process $proc$ls180.v:1972$3963 + process $proc$ls180.v:1972$3965 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always @@ -289484,7 +289502,7 @@ module \ls180 update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end attribute \src "ls180.v:1973.12-1973.87" - process $proc$ls180.v:1973$3964 + process $proc$ls180.v:1973$3966 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always @@ -289492,7 +289510,7 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end attribute \src "ls180.v:1974.5-1974.82" - process $proc$ls180.v:1974$3965 + process $proc$ls180.v:1974$3967 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always @@ -289500,7 +289518,7 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end attribute \src "ls180.v:1975.12-1975.43" - process $proc$ls180.v:1975$3966 + process $proc$ls180.v:1975$3968 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always @@ -289508,7 +289526,7 @@ module \ls180 update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end attribute \src "ls180.v:1976.5-1976.34" - process $proc$ls180.v:1976$3967 + process $proc$ls180.v:1976$3969 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always @@ -289516,7 +289534,7 @@ module \ls180 update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end attribute \src "ls180.v:1977.11-1977.43" - process $proc$ls180.v:1977$3968 + process $proc$ls180.v:1977$3970 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always @@ -289524,7 +289542,7 @@ module \ls180 update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end attribute \src "ls180.v:1979.12-1979.52" - process $proc$ls180.v:1979$3969 + process $proc$ls180.v:1979$3971 assign { } { } assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always @@ -289532,7 +289550,7 @@ module \ls180 sync init end attribute \src "ls180.v:1980.12-1980.54" - process $proc$ls180.v:1980$3970 + process $proc$ls180.v:1980$3972 assign { } { } assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 sync always @@ -289540,7 +289558,7 @@ module \ls180 sync init end attribute \src "ls180.v:1981.12-1981.54" - process $proc$ls180.v:1981$3971 + process $proc$ls180.v:1981$3973 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always @@ -289548,7 +289566,7 @@ module \ls180 update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end attribute \src "ls180.v:1982.11-1982.50" - process $proc$ls180.v:1982$3972 + process $proc$ls180.v:1982$3974 assign { } { } assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 sync always @@ -289556,7 +289574,7 @@ module \ls180 sync init end attribute \src "ls180.v:1983.5-1983.44" - process $proc$ls180.v:1983$3973 + process $proc$ls180.v:1983$3975 assign { } { } assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 sync always @@ -289564,7 +289582,7 @@ module \ls180 sync init end attribute \src "ls180.v:1984.5-1984.44" - process $proc$ls180.v:1984$3974 + process $proc$ls180.v:1984$3976 assign { } { } assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 sync always @@ -289572,7 +289590,7 @@ module \ls180 sync init end attribute \src "ls180.v:1985.5-1985.44" - process $proc$ls180.v:1985$3975 + process $proc$ls180.v:1985$3977 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always @@ -289580,7 +289598,7 @@ module \ls180 update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end attribute \src "ls180.v:1986.5-1986.43" - process $proc$ls180.v:1986$3976 + process $proc$ls180.v:1986$3978 assign { } { } assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always @@ -289588,7 +289606,7 @@ module \ls180 sync init end attribute \src "ls180.v:1989.12-1989.65" - process $proc$ls180.v:1989$3977 + process $proc$ls180.v:1989$3979 assign { } { } assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -289596,7 +289614,7 @@ module \ls180 sync init end attribute \src "ls180.v:1993.5-1993.55" - process $proc$ls180.v:1993$3978 + process $proc$ls180.v:1993$3980 assign { } { } assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always @@ -289604,7 +289622,7 @@ module \ls180 sync init end attribute \src "ls180.v:1997.5-1997.55" - process $proc$ls180.v:1997$3979 + process $proc$ls180.v:1997$3981 assign { } { } assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always @@ -289612,7 +289630,7 @@ module \ls180 sync init end attribute \src "ls180.v:2000.12-2000.40" - process $proc$ls180.v:2000$3980 + process $proc$ls180.v:2000$3982 assign { } { } assign $1\builder_shared_dat_r[31:0] 0 sync always @@ -289620,15 +289638,23 @@ module \ls180 update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end attribute \src "ls180.v:2004.5-2004.30" - process $proc$ls180.v:2004$3981 + process $proc$ls180.v:2004$3983 assign { } { } assign $1\builder_shared_ack[0:0] 1'0 sync always sync init update \builder_shared_ack $1\builder_shared_ack[0:0] end + attribute \src "ls180.v:201.5-201.72" + process $proc$ls180.v:201$3155 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + sync init + end attribute \src "ls180.v:2010.11-2010.31" - process $proc$ls180.v:2010$3982 + process $proc$ls180.v:2010$3984 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always @@ -289636,7 +289662,7 @@ module \ls180 update \builder_grant $1\builder_grant[2:0] end attribute \src "ls180.v:2011.12-2011.37" - process $proc$ls180.v:2011$3983 + process $proc$ls180.v:2011$3985 assign { } { } assign $1\builder_slave_sel[12:0] 13'0000000000000 sync always @@ -289644,7 +289670,7 @@ module \ls180 update \builder_slave_sel $1\builder_slave_sel[12:0] end attribute \src "ls180.v:2012.12-2012.39" - process $proc$ls180.v:2012$3984 + process $proc$ls180.v:2012$3986 assign { } { } assign $1\builder_slave_sel_r[12:0] 13'0000000000000 sync always @@ -289652,7 +289678,7 @@ module \ls180 update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] end attribute \src "ls180.v:2013.5-2013.25" - process $proc$ls180.v:2013$3985 + process $proc$ls180.v:2013$3987 assign { } { } assign $1\builder_error[0:0] 1'0 sync always @@ -289660,7 +289686,7 @@ module \ls180 update \builder_error $1\builder_error[0:0] end attribute \src "ls180.v:2016.12-2016.39" - process $proc$ls180.v:2016$3986 + process $proc$ls180.v:2016$3988 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always @@ -289668,23 +289694,23 @@ module \ls180 update \builder_count $1\builder_count[19:0] end attribute \src "ls180.v:2020.11-2020.51" - process $proc$ls180.v:2020$3987 + process $proc$ls180.v:2020$3989 assign { } { } assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:204.12-204.74" - process $proc$ls180.v:204$3154 + attribute \src "ls180.v:204.11-204.79" + process $proc$ls180.v:204$3156 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] sync init end attribute \src "ls180.v:2061.11-2061.51" - process $proc$ls180.v:2061$3988 + process $proc$ls180.v:2061$3990 assign { } { } assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289692,7 +289718,7 @@ module \ls180 update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2090.11-2090.51" - process $proc$ls180.v:2090$3989 + process $proc$ls180.v:2090$3991 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289700,7 +289726,7 @@ module \ls180 update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2103.11-2103.51" - process $proc$ls180.v:2103$3990 + process $proc$ls180.v:2103$3992 assign { } { } assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289708,7 +289734,7 @@ module \ls180 update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$3155 + process $proc$ls180.v:213$3157 assign { } { } assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always @@ -289716,7 +289742,7 @@ module \ls180 update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end attribute \src "ls180.v:2144.11-2144.51" - process $proc$ls180.v:2144$3991 + process $proc$ls180.v:2144$3993 assign { } { } assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289724,7 +289750,7 @@ module \ls180 update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end attribute \src "ls180.v:217.5-217.40" - process $proc$ls180.v:217$3156 + process $proc$ls180.v:217$3158 assign { } { } assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always @@ -289732,7 +289758,7 @@ module \ls180 sync init end attribute \src "ls180.v:2185.11-2185.51" - process $proc$ls180.v:2185$3992 + process $proc$ls180.v:2185$3994 assign { } { } assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289740,7 +289766,7 @@ module \ls180 update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end attribute \src "ls180.v:220.11-220.37" - process $proc$ls180.v:220$3157 + process $proc$ls180.v:220$3159 assign { } { } assign $1\main_libresocsim_we[7:0] 8'00000000 sync always @@ -289748,7 +289774,7 @@ module \ls180 update \main_libresocsim_we $1\main_libresocsim_we[7:0] end attribute \src "ls180.v:222.12-222.49" - process $proc$ls180.v:222$3158 + process $proc$ls180.v:222$3160 assign { } { } assign $1\main_libresocsim_load_storage[31:0] 0 sync always @@ -289756,7 +289782,7 @@ module \ls180 update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end attribute \src "ls180.v:223.5-223.36" - process $proc$ls180.v:223$3159 + process $proc$ls180.v:223$3161 assign { } { } assign $1\main_libresocsim_load_re[0:0] 1'0 sync always @@ -289764,7 +289790,7 @@ module \ls180 update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end attribute \src "ls180.v:224.12-224.51" - process $proc$ls180.v:224$3160 + process $proc$ls180.v:224$3162 assign { } { } assign $1\main_libresocsim_reload_storage[31:0] 0 sync always @@ -289772,7 +289798,7 @@ module \ls180 update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end attribute \src "ls180.v:225.5-225.38" - process $proc$ls180.v:225$3161 + process $proc$ls180.v:225$3163 assign { } { } assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always @@ -289780,7 +289806,7 @@ module \ls180 update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end attribute \src "ls180.v:2250.11-2250.51" - process $proc$ls180.v:2250$3993 + process $proc$ls180.v:2250$3995 assign { } { } assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289788,7 +289814,7 @@ module \ls180 update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end attribute \src "ls180.v:226.5-226.39" - process $proc$ls180.v:226$3162 + process $proc$ls180.v:226$3164 assign { } { } assign $1\main_libresocsim_en_storage[0:0] 1'0 sync always @@ -289796,7 +289822,7 @@ module \ls180 update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end attribute \src "ls180.v:227.5-227.34" - process $proc$ls180.v:227$3163 + process $proc$ls180.v:227$3165 assign { } { } assign $1\main_libresocsim_en_re[0:0] 1'0 sync always @@ -289804,7 +289830,7 @@ module \ls180 update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] end attribute \src "ls180.v:228.5-228.49" - process $proc$ls180.v:228$3164 + process $proc$ls180.v:228$3166 assign { } { } assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always @@ -289812,7 +289838,7 @@ module \ls180 update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end attribute \src "ls180.v:229.5-229.44" - process $proc$ls180.v:229$3165 + process $proc$ls180.v:229$3167 assign { } { } assign $1\main_libresocsim_update_value_re[0:0] 1'0 sync always @@ -289820,7 +289846,7 @@ module \ls180 update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] end attribute \src "ls180.v:230.12-230.49" - process $proc$ls180.v:230$3166 + process $proc$ls180.v:230$3168 assign { } { } assign $1\main_libresocsim_value_status[31:0] 0 sync always @@ -289828,7 +289854,7 @@ module \ls180 update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end attribute \src "ls180.v:234.5-234.41" - process $proc$ls180.v:234$3167 + process $proc$ls180.v:234$3169 assign { } { } assign $1\main_libresocsim_zero_pending[0:0] 1'0 sync always @@ -289836,7 +289862,7 @@ module \ls180 update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] end attribute \src "ls180.v:236.5-236.39" - process $proc$ls180.v:236$3168 + process $proc$ls180.v:236$3170 assign { } { } assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always @@ -289844,7 +289870,7 @@ module \ls180 update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end attribute \src "ls180.v:237.5-237.45" - process $proc$ls180.v:237$3169 + process $proc$ls180.v:237$3171 assign { } { } assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always @@ -289852,7 +289878,7 @@ module \ls180 update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] end attribute \src "ls180.v:2383.11-2383.51" - process $proc$ls180.v:2383$3994 + process $proc$ls180.v:2383$3996 assign { } { } assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289860,7 +289886,7 @@ module \ls180 update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end attribute \src "ls180.v:246.5-246.49" - process $proc$ls180.v:246$3170 + process $proc$ls180.v:246$3172 assign { } { } assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always @@ -289868,7 +289894,7 @@ module \ls180 update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end attribute \src "ls180.v:2464.11-2464.51" - process $proc$ls180.v:2464$3995 + process $proc$ls180.v:2464$3997 assign { } { } assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289876,7 +289902,7 @@ module \ls180 update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end attribute \src "ls180.v:247.5-247.44" - process $proc$ls180.v:247$3171 + process $proc$ls180.v:247$3173 assign { } { } assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always @@ -289884,7 +289910,7 @@ module \ls180 update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end attribute \src "ls180.v:248.12-248.42" - process $proc$ls180.v:248$3172 + process $proc$ls180.v:248$3174 assign { } { } assign $1\main_libresocsim_value[31:0] 0 sync always @@ -289892,7 +289918,7 @@ module \ls180 update \main_libresocsim_value $1\main_libresocsim_value[31:0] end attribute \src "ls180.v:2481.11-2481.51" - process $proc$ls180.v:2481$3996 + process $proc$ls180.v:2481$3998 assign { } { } assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289900,7 +289926,7 @@ module \ls180 update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2522.11-2522.52" - process $proc$ls180.v:2522$3997 + process $proc$ls180.v:2522$3999 assign { } { } assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289908,7 +289934,7 @@ module \ls180 update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end attribute \src "ls180.v:255.5-255.39" - process $proc$ls180.v:255$3173 + process $proc$ls180.v:255$3175 assign { } { } assign $1\main_interface0_ram_bus_ack[0:0] 1'0 sync always @@ -289916,7 +289942,7 @@ module \ls180 update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] end attribute \src "ls180.v:2555.11-2555.52" - process $proc$ls180.v:2555$3998 + process $proc$ls180.v:2555$4000 assign { } { } assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289924,7 +289950,7 @@ module \ls180 update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end attribute \src "ls180.v:259.5-259.39" - process $proc$ls180.v:259$3174 + process $proc$ls180.v:259$3176 assign { } { } assign $0\main_interface0_ram_bus_err[0:0] 1'0 sync always @@ -289932,7 +289958,7 @@ module \ls180 sync init end attribute \src "ls180.v:2596.11-2596.52" - process $proc$ls180.v:2596$3999 + process $proc$ls180.v:2596$4001 assign { } { } assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289940,7 +289966,7 @@ module \ls180 update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end attribute \src "ls180.v:262.11-262.31" - process $proc$ls180.v:262$3175 + process $proc$ls180.v:262$3177 assign { } { } assign $1\main_sram0_we[7:0] 8'00000000 sync always @@ -289948,7 +289974,7 @@ module \ls180 update \main_sram0_we $1\main_sram0_we[7:0] end attribute \src "ls180.v:2661.11-2661.52" - process $proc$ls180.v:2661$4000 + process $proc$ls180.v:2661$4002 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289956,7 +289982,7 @@ module \ls180 update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end attribute \src "ls180.v:2686.11-2686.52" - process $proc$ls180.v:2686$4001 + process $proc$ls180.v:2686$4003 assign { } { } assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -289964,7 +289990,7 @@ module \ls180 update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end attribute \src "ls180.v:270.5-270.39" - process $proc$ls180.v:270$3176 + process $proc$ls180.v:270$3178 assign { } { } assign $1\main_interface1_ram_bus_ack[0:0] 1'0 sync always @@ -289972,7 +289998,7 @@ module \ls180 update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] end attribute \src "ls180.v:2708.11-2708.31" - process $proc$ls180.v:2708$4002 + process $proc$ls180.v:2708$4004 assign { } { } assign $1\builder_state[1:0] 2'00 sync always @@ -289980,7 +290006,7 @@ module \ls180 update \builder_state $1\builder_state[1:0] end attribute \src "ls180.v:2709.11-2709.36" - process $proc$ls180.v:2709$4003 + process $proc$ls180.v:2709$4005 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always @@ -289988,7 +290014,7 @@ module \ls180 update \builder_next_state $1\builder_next_state[1:0] end attribute \src "ls180.v:2710.11-2710.55" - process $proc$ls180.v:2710$4004 + process $proc$ls180.v:2710$4006 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always @@ -289996,7 +290022,7 @@ module \ls180 update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end attribute \src "ls180.v:2711.5-2711.52" - process $proc$ls180.v:2711$4005 + process $proc$ls180.v:2711$4007 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always @@ -290004,7 +290030,7 @@ module \ls180 update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end attribute \src "ls180.v:2712.12-2712.55" - process $proc$ls180.v:2712$4006 + process $proc$ls180.v:2712$4008 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always @@ -290012,7 +290038,7 @@ module \ls180 update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end attribute \src "ls180.v:2713.5-2713.50" - process $proc$ls180.v:2713$4007 + process $proc$ls180.v:2713$4009 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always @@ -290020,7 +290046,7 @@ module \ls180 update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end attribute \src "ls180.v:2714.5-2714.46" - process $proc$ls180.v:2714$4008 + process $proc$ls180.v:2714$4010 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always @@ -290028,7 +290054,7 @@ module \ls180 update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end attribute \src "ls180.v:2715.5-2715.49" - process $proc$ls180.v:2715$4009 + process $proc$ls180.v:2715$4011 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always @@ -290036,7 +290062,7 @@ module \ls180 update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end attribute \src "ls180.v:2716.5-2716.41" - process $proc$ls180.v:2716$4010 + process $proc$ls180.v:2716$4012 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always @@ -290044,7 +290070,7 @@ module \ls180 update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end attribute \src "ls180.v:2717.12-2717.49" - process $proc$ls180.v:2717$4011 + process $proc$ls180.v:2717$4013 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always @@ -290052,7 +290078,7 @@ module \ls180 update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end attribute \src "ls180.v:2718.11-2718.47" - process $proc$ls180.v:2718$4012 + process $proc$ls180.v:2718$4014 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always @@ -290060,7 +290086,7 @@ module \ls180 update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end attribute \src "ls180.v:2719.5-2719.41" - process $proc$ls180.v:2719$4013 + process $proc$ls180.v:2719$4015 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always @@ -290068,7 +290094,7 @@ module \ls180 update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end attribute \src "ls180.v:2720.5-2720.41" - process $proc$ls180.v:2720$4014 + process $proc$ls180.v:2720$4016 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always @@ -290076,7 +290102,7 @@ module \ls180 update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end attribute \src "ls180.v:2721.5-2721.41" - process $proc$ls180.v:2721$4015 + process $proc$ls180.v:2721$4017 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always @@ -290084,7 +290110,7 @@ module \ls180 update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end attribute \src "ls180.v:2722.5-2722.39" - process $proc$ls180.v:2722$4016 + process $proc$ls180.v:2722$4018 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always @@ -290092,7 +290118,7 @@ module \ls180 update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end attribute \src "ls180.v:2723.5-2723.39" - process $proc$ls180.v:2723$4017 + process $proc$ls180.v:2723$4019 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always @@ -290100,7 +290126,7 @@ module \ls180 update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end attribute \src "ls180.v:2724.5-2724.39" - process $proc$ls180.v:2724$4018 + process $proc$ls180.v:2724$4020 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always @@ -290108,7 +290134,7 @@ module \ls180 update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end attribute \src "ls180.v:2725.5-2725.41" - process $proc$ls180.v:2725$4019 + process $proc$ls180.v:2725$4021 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always @@ -290116,7 +290142,7 @@ module \ls180 update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end attribute \src "ls180.v:2726.12-2726.49" - process $proc$ls180.v:2726$4020 + process $proc$ls180.v:2726$4022 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always @@ -290124,7 +290150,7 @@ module \ls180 update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end attribute \src "ls180.v:2727.11-2727.47" - process $proc$ls180.v:2727$4021 + process $proc$ls180.v:2727$4023 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always @@ -290132,7 +290158,7 @@ module \ls180 update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end attribute \src "ls180.v:2728.5-2728.41" - process $proc$ls180.v:2728$4022 + process $proc$ls180.v:2728$4024 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always @@ -290140,7 +290166,7 @@ module \ls180 update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end attribute \src "ls180.v:2729.5-2729.42" - process $proc$ls180.v:2729$4023 + process $proc$ls180.v:2729$4025 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always @@ -290148,7 +290174,7 @@ module \ls180 update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end attribute \src "ls180.v:2730.5-2730.42" - process $proc$ls180.v:2730$4024 + process $proc$ls180.v:2730$4026 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always @@ -290156,7 +290182,7 @@ module \ls180 update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end attribute \src "ls180.v:2731.5-2731.39" - process $proc$ls180.v:2731$4025 + process $proc$ls180.v:2731$4027 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always @@ -290164,7 +290190,7 @@ module \ls180 update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end attribute \src "ls180.v:2732.5-2732.39" - process $proc$ls180.v:2732$4026 + process $proc$ls180.v:2732$4028 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always @@ -290172,7 +290198,7 @@ module \ls180 update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end attribute \src "ls180.v:2733.5-2733.39" - process $proc$ls180.v:2733$4027 + process $proc$ls180.v:2733$4029 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always @@ -290180,7 +290206,7 @@ module \ls180 update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end attribute \src "ls180.v:2734.12-2734.50" - process $proc$ls180.v:2734$4028 + process $proc$ls180.v:2734$4030 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always @@ -290188,7 +290214,7 @@ module \ls180 update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end attribute \src "ls180.v:2735.5-2735.42" - process $proc$ls180.v:2735$4029 + process $proc$ls180.v:2735$4031 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always @@ -290196,7 +290222,7 @@ module \ls180 update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end attribute \src "ls180.v:2736.5-2736.42" - process $proc$ls180.v:2736$4030 + process $proc$ls180.v:2736$4032 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always @@ -290204,7 +290230,7 @@ module \ls180 update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end attribute \src "ls180.v:2737.12-2737.50" - process $proc$ls180.v:2737$4031 + process $proc$ls180.v:2737$4033 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always @@ -290212,7 +290238,7 @@ module \ls180 update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end attribute \src "ls180.v:2738.5-2738.42" - process $proc$ls180.v:2738$4032 + process $proc$ls180.v:2738$4034 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always @@ -290220,7 +290246,7 @@ module \ls180 update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end attribute \src "ls180.v:2739.5-2739.42" - process $proc$ls180.v:2739$4033 + process $proc$ls180.v:2739$4035 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always @@ -290228,7 +290254,7 @@ module \ls180 update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end attribute \src "ls180.v:274.5-274.39" - process $proc$ls180.v:274$3177 + process $proc$ls180.v:274$3179 assign { } { } assign $0\main_interface1_ram_bus_err[0:0] 1'0 sync always @@ -290236,7 +290262,7 @@ module \ls180 sync init end attribute \src "ls180.v:2740.12-2740.50" - process $proc$ls180.v:2740$4034 + process $proc$ls180.v:2740$4036 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always @@ -290244,7 +290270,7 @@ module \ls180 update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end attribute \src "ls180.v:2741.5-2741.42" - process $proc$ls180.v:2741$4035 + process $proc$ls180.v:2741$4037 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always @@ -290252,7 +290278,7 @@ module \ls180 update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end attribute \src "ls180.v:2742.5-2742.42" - process $proc$ls180.v:2742$4036 + process $proc$ls180.v:2742$4038 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always @@ -290260,7 +290286,7 @@ module \ls180 update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end attribute \src "ls180.v:2743.12-2743.50" - process $proc$ls180.v:2743$4037 + process $proc$ls180.v:2743$4039 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always @@ -290268,7 +290294,7 @@ module \ls180 update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end attribute \src "ls180.v:2744.5-2744.42" - process $proc$ls180.v:2744$4038 + process $proc$ls180.v:2744$4040 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always @@ -290276,7 +290302,7 @@ module \ls180 update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end attribute \src "ls180.v:2745.5-2745.42" - process $proc$ls180.v:2745$4039 + process $proc$ls180.v:2745$4041 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always @@ -290284,7 +290310,7 @@ module \ls180 update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end attribute \src "ls180.v:2746.12-2746.50" - process $proc$ls180.v:2746$4040 + process $proc$ls180.v:2746$4042 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always @@ -290292,7 +290318,7 @@ module \ls180 update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end attribute \src "ls180.v:2747.12-2747.50" - process $proc$ls180.v:2747$4041 + process $proc$ls180.v:2747$4043 assign { } { } assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -290300,7 +290326,7 @@ module \ls180 update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end attribute \src "ls180.v:2748.11-2748.48" - process $proc$ls180.v:2748$4042 + process $proc$ls180.v:2748$4044 assign { } { } assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always @@ -290308,7 +290334,7 @@ module \ls180 update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end attribute \src "ls180.v:2749.5-2749.42" - process $proc$ls180.v:2749$4043 + process $proc$ls180.v:2749$4045 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always @@ -290316,7 +290342,7 @@ module \ls180 update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end attribute \src "ls180.v:2750.5-2750.42" - process $proc$ls180.v:2750$4044 + process $proc$ls180.v:2750$4046 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always @@ -290324,7 +290350,7 @@ module \ls180 update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end attribute \src "ls180.v:2751.5-2751.42" - process $proc$ls180.v:2751$4045 + process $proc$ls180.v:2751$4047 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always @@ -290332,7 +290358,7 @@ module \ls180 update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end attribute \src "ls180.v:2752.11-2752.48" - process $proc$ls180.v:2752$4046 + process $proc$ls180.v:2752$4048 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always @@ -290340,7 +290366,7 @@ module \ls180 update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end attribute \src "ls180.v:2753.11-2753.48" - process $proc$ls180.v:2753$4047 + process $proc$ls180.v:2753$4049 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always @@ -290348,7 +290374,7 @@ module \ls180 update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end attribute \src "ls180.v:2754.11-2754.47" - process $proc$ls180.v:2754$4048 + process $proc$ls180.v:2754$4050 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always @@ -290356,7 +290382,7 @@ module \ls180 update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end attribute \src "ls180.v:2755.12-2755.49" - process $proc$ls180.v:2755$4049 + process $proc$ls180.v:2755$4051 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always @@ -290364,7 +290390,7 @@ module \ls180 update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end attribute \src "ls180.v:2756.5-2756.41" - process $proc$ls180.v:2756$4050 + process $proc$ls180.v:2756$4052 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always @@ -290372,7 +290398,7 @@ module \ls180 update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end attribute \src "ls180.v:2757.5-2757.41" - process $proc$ls180.v:2757$4051 + process $proc$ls180.v:2757$4053 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always @@ -290380,7 +290406,7 @@ module \ls180 update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end attribute \src "ls180.v:2758.5-2758.41" - process $proc$ls180.v:2758$4052 + process $proc$ls180.v:2758$4054 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always @@ -290388,7 +290414,7 @@ module \ls180 update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end attribute \src "ls180.v:2759.5-2759.41" - process $proc$ls180.v:2759$4053 + process $proc$ls180.v:2759$4055 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always @@ -290396,7 +290422,7 @@ module \ls180 update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end attribute \src "ls180.v:2760.5-2760.41" - process $proc$ls180.v:2760$4054 + process $proc$ls180.v:2760$4056 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always @@ -290404,7 +290430,7 @@ module \ls180 update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end attribute \src "ls180.v:2761.5-2761.39" - process $proc$ls180.v:2761$4055 + process $proc$ls180.v:2761$4057 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always @@ -290412,7 +290438,7 @@ module \ls180 update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end attribute \src "ls180.v:2762.5-2762.39" - process $proc$ls180.v:2762$4056 + process $proc$ls180.v:2762$4058 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always @@ -290420,7 +290446,7 @@ module \ls180 update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end attribute \src "ls180.v:277.11-277.31" - process $proc$ls180.v:277$3178 + process $proc$ls180.v:277$3180 assign { } { } assign $1\main_sram1_we[7:0] 8'00000000 sync always @@ -290428,7 +290454,7 @@ module \ls180 update \main_sram1_we $1\main_sram1_we[7:0] end attribute \src "ls180.v:2819.32-2819.66" - process $proc$ls180.v:2819$4057 + process $proc$ls180.v:2819$4059 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always @@ -290436,7 +290462,7 @@ module \ls180 update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end attribute \src "ls180.v:2820.32-2820.66" - process $proc$ls180.v:2820$4058 + process $proc$ls180.v:2820$4060 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always @@ -290444,7 +290470,7 @@ module \ls180 update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end attribute \src "ls180.v:2821.32-2821.66" - process $proc$ls180.v:2821$4059 + process $proc$ls180.v:2821$4061 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always @@ -290452,7 +290478,7 @@ module \ls180 update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end attribute \src "ls180.v:2822.32-2822.66" - process $proc$ls180.v:2822$4060 + process $proc$ls180.v:2822$4062 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always @@ -290460,7 +290486,7 @@ module \ls180 update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end attribute \src "ls180.v:2823.32-2823.66" - process $proc$ls180.v:2823$4061 + process $proc$ls180.v:2823$4063 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always @@ -290468,7 +290494,7 @@ module \ls180 update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end attribute \src "ls180.v:2824.32-2824.66" - process $proc$ls180.v:2824$4062 + process $proc$ls180.v:2824$4064 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always @@ -290476,7 +290502,7 @@ module \ls180 update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end attribute \src "ls180.v:2825.32-2825.66" - process $proc$ls180.v:2825$4063 + process $proc$ls180.v:2825$4065 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always @@ -290484,7 +290510,7 @@ module \ls180 update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end attribute \src "ls180.v:2826.32-2826.66" - process $proc$ls180.v:2826$4064 + process $proc$ls180.v:2826$4066 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always @@ -290492,7 +290518,7 @@ module \ls180 update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end attribute \src "ls180.v:2827.32-2827.66" - process $proc$ls180.v:2827$4065 + process $proc$ls180.v:2827$4067 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always @@ -290500,7 +290526,7 @@ module \ls180 update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end attribute \src "ls180.v:2828.32-2828.66" - process $proc$ls180.v:2828$4066 + process $proc$ls180.v:2828$4068 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always @@ -290508,7 +290534,7 @@ module \ls180 update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end attribute \src "ls180.v:2829.32-2829.66" - process $proc$ls180.v:2829$4067 + process $proc$ls180.v:2829$4069 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always @@ -290516,7 +290542,7 @@ module \ls180 update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end attribute \src "ls180.v:2830.32-2830.66" - process $proc$ls180.v:2830$4068 + process $proc$ls180.v:2830$4070 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always @@ -290524,7 +290550,7 @@ module \ls180 update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end attribute \src "ls180.v:2831.32-2831.66" - process $proc$ls180.v:2831$4069 + process $proc$ls180.v:2831$4071 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always @@ -290532,7 +290558,7 @@ module \ls180 update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end attribute \src "ls180.v:2832.32-2832.66" - process $proc$ls180.v:2832$4070 + process $proc$ls180.v:2832$4072 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always @@ -290540,7 +290566,7 @@ module \ls180 update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end attribute \src "ls180.v:2833.32-2833.66" - process $proc$ls180.v:2833$4071 + process $proc$ls180.v:2833$4073 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always @@ -290548,7 +290574,7 @@ module \ls180 update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end attribute \src "ls180.v:2834.32-2834.66" - process $proc$ls180.v:2834$4072 + process $proc$ls180.v:2834$4074 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always @@ -290556,7 +290582,7 @@ module \ls180 update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end attribute \src "ls180.v:2835.32-2835.66" - process $proc$ls180.v:2835$4073 + process $proc$ls180.v:2835$4075 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always @@ -290564,7 +290590,7 @@ module \ls180 update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end attribute \src "ls180.v:2836.32-2836.66" - process $proc$ls180.v:2836$4074 + process $proc$ls180.v:2836$4076 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always @@ -290572,7 +290598,7 @@ module \ls180 update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end attribute \src "ls180.v:2837.32-2837.66" - process $proc$ls180.v:2837$4075 + process $proc$ls180.v:2837$4077 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always @@ -290580,7 +290606,7 @@ module \ls180 update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end attribute \src "ls180.v:2838.32-2838.66" - process $proc$ls180.v:2838$4076 + process $proc$ls180.v:2838$4078 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always @@ -290588,7 +290614,7 @@ module \ls180 update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end attribute \src "ls180.v:2839.32-2839.67" - process $proc$ls180.v:2839$4077 + process $proc$ls180.v:2839$4079 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always @@ -290596,7 +290622,7 @@ module \ls180 update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end attribute \src "ls180.v:2840.32-2840.67" - process $proc$ls180.v:2840$4078 + process $proc$ls180.v:2840$4080 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always @@ -290604,7 +290630,7 @@ module \ls180 update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end attribute \src "ls180.v:2841.32-2841.67" - process $proc$ls180.v:2841$4079 + process $proc$ls180.v:2841$4081 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always @@ -290612,7 +290638,7 @@ module \ls180 update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end attribute \src "ls180.v:2842.32-2842.67" - process $proc$ls180.v:2842$4080 + process $proc$ls180.v:2842$4082 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always @@ -290620,7 +290646,7 @@ module \ls180 update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end attribute \src "ls180.v:2843.32-2843.67" - process $proc$ls180.v:2843$4081 + process $proc$ls180.v:2843$4083 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always @@ -290628,7 +290654,7 @@ module \ls180 update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end attribute \src "ls180.v:2844.32-2844.67" - process $proc$ls180.v:2844$4082 + process $proc$ls180.v:2844$4084 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always @@ -290636,7 +290662,7 @@ module \ls180 update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end attribute \src "ls180.v:2845.32-2845.67" - process $proc$ls180.v:2845$4083 + process $proc$ls180.v:2845$4085 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always @@ -290644,7 +290670,7 @@ module \ls180 update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end attribute \src "ls180.v:2846.32-2846.67" - process $proc$ls180.v:2846$4084 + process $proc$ls180.v:2846$4086 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always @@ -290652,7 +290678,7 @@ module \ls180 update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end attribute \src "ls180.v:2847.32-2847.67" - process $proc$ls180.v:2847$4085 + process $proc$ls180.v:2847$4087 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always @@ -290660,7 +290686,7 @@ module \ls180 update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end attribute \src "ls180.v:2848.32-2848.67" - process $proc$ls180.v:2848$4086 + process $proc$ls180.v:2848$4088 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always @@ -290668,7 +290694,7 @@ module \ls180 update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end attribute \src "ls180.v:2849.32-2849.67" - process $proc$ls180.v:2849$4087 + process $proc$ls180.v:2849$4089 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always @@ -290676,7 +290702,7 @@ module \ls180 update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end attribute \src "ls180.v:285.5-285.39" - process $proc$ls180.v:285$3179 + process $proc$ls180.v:285$3181 assign { } { } assign $1\main_interface2_ram_bus_ack[0:0] 1'0 sync always @@ -290684,7 +290710,7 @@ module \ls180 update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] end attribute \src "ls180.v:2850.32-2850.67" - process $proc$ls180.v:2850$4088 + process $proc$ls180.v:2850$4090 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always @@ -290692,7 +290718,7 @@ module \ls180 update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end attribute \src "ls180.v:2851.32-2851.67" - process $proc$ls180.v:2851$4089 + process $proc$ls180.v:2851$4091 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always @@ -290700,7 +290726,7 @@ module \ls180 update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end attribute \src "ls180.v:2852.32-2852.67" - process $proc$ls180.v:2852$4090 + process $proc$ls180.v:2852$4092 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always @@ -290718,7 +290744,7 @@ module \ls180 update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end attribute \src "ls180.v:289.5-289.39" - process $proc$ls180.v:289$3180 + process $proc$ls180.v:289$3182 assign { } { } assign $0\main_interface2_ram_bus_err[0:0] 1'0 sync always @@ -290831,7 +290857,7 @@ module \ls180 update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end attribute \src "ls180.v:292.11-292.31" - process $proc$ls180.v:292$3181 + process $proc$ls180.v:292$3183 assign { } { } assign $1\main_sram2_we[7:0] 8'00000000 sync always @@ -290868,10 +290894,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 @@ -290944,7 +290970,7 @@ module \ls180 update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end attribute \src "ls180.v:300.5-300.39" - process $proc$ls180.v:300$3182 + process $proc$ls180.v:300$3184 assign { } { } assign $1\main_interface3_ram_bus_ack[0:0] 1'0 sync always @@ -290980,8 +291006,9 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_we[0:0] 1'0 assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 assign $0\main_wb_sdram_sel[3:0] 4'0000 @@ -290989,7 +291016,6 @@ module \ls180 assign $0\main_wb_sdram_stb[0:0] 1'0 assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state attribute \src "ls180.v:3038.2-3071.9" switch \builder_converter2_state @@ -291057,7 +291083,7 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] end attribute \src "ls180.v:304.5-304.39" - process $proc$ls180.v:304$3183 + process $proc$ls180.v:304$3185 assign { } { } assign $0\main_interface3_ram_bus_err[0:0] 1'0 sync always @@ -291065,7 +291091,7 @@ module \ls180 sync init end attribute \src "ls180.v:307.11-307.31" - process $proc$ls180.v:307$3184 + process $proc$ls180.v:307$3186 assign { } { } assign $1\main_sram3_we[7:0] 8'00000000 sync always @@ -291162,7 +291188,7 @@ module \ls180 update \main_sram3_we $0\main_sram3_we[7:0] end attribute \src "ls180.v:315.5-315.51" - process $proc$ls180.v:315$3185 + process $proc$ls180.v:315$3187 assign { } { } assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always @@ -291170,7 +291196,7 @@ module \ls180 update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end attribute \src "ls180.v:319.5-319.51" - process $proc$ls180.v:319$3186 + process $proc$ls180.v:319$3188 assign { } { } assign $0\main_interface0_converted_interface_err[0:0] 1'0 sync always @@ -291275,7 +291301,7 @@ module \ls180 update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end attribute \src "ls180.v:320.5-320.32" - process $proc$ls180.v:320$3187 + process $proc$ls180.v:320$3189 assign { } { } assign $1\main_converter0_skip[0:0] 1'0 sync always @@ -291283,7 +291309,7 @@ module \ls180 update \main_converter0_skip $1\main_converter0_skip[0:0] end attribute \src "ls180.v:321.5-321.35" - process $proc$ls180.v:321$3188 + process $proc$ls180.v:321$3190 assign { } { } assign $1\main_converter0_counter[0:0] 1'0 sync always @@ -291291,7 +291317,7 @@ module \ls180 update \main_converter0_counter $1\main_converter0_counter[0:0] end attribute \src "ls180.v:323.12-323.41" - process $proc$ls180.v:323$3189 + process $proc$ls180.v:323$3191 assign { } { } assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -291304,10 +291330,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 attribute \src "ls180.v:3254.2-3264.5" switch \main_sdram_command_issue_re attribute \src "ls180.v:3254.6-3254.33" @@ -291330,7 +291356,7 @@ module \ls180 update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end attribute \src "ls180.v:330.5-330.51" - process $proc$ls180.v:330$3190 + process $proc$ls180.v:330$3192 assign { } { } assign $1\main_interface1_converted_interface_ack[0:0] 1'0 sync always @@ -291343,10 +291369,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\builder_refresher_next_state[1:0] \builder_refresher_state attribute \src "ls180.v:3314.2-3337.9" switch \builder_refresher_state @@ -291396,7 +291422,7 @@ module \ls180 update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end attribute \src "ls180.v:334.5-334.51" - process $proc$ls180.v:334$3191 + process $proc$ls180.v:334$3193 assign { } { } assign $0\main_interface1_converted_interface_err[0:0] 1'0 sync always @@ -291404,7 +291430,7 @@ module \ls180 sync init end attribute \src "ls180.v:335.5-335.32" - process $proc$ls180.v:335$3192 + process $proc$ls180.v:335$3194 assign { } { } assign $1\main_converter1_skip[0:0] 1'0 sync always @@ -291428,7 +291454,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end attribute \src "ls180.v:336.5-336.35" - process $proc$ls180.v:336$3193 + process $proc$ls180.v:336$3195 assign { } { } assign $1\main_converter1_counter[0:0] 1'0 sync always @@ -291456,7 +291482,7 @@ module \ls180 update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end attribute \src "ls180.v:338.12-338.41" - process $proc$ls180.v:338$3194 + process $proc$ls180.v:338$3196 assign { } { } assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -291657,7 +291683,7 @@ module \ls180 update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end attribute \src "ls180.v:342.5-342.24" - process $proc$ls180.v:342$3195 + process $proc$ls180.v:342$3197 assign { } { } assign $1\main_int_rst[0:0] 1'1 sync always @@ -291894,7 +291920,7 @@ module \ls180 update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end attribute \src "ls180.v:357.12-357.38" - process $proc$ls180.v:357$3196 + process $proc$ls180.v:357$3198 assign { } { } assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 sync always @@ -291902,7 +291928,7 @@ module \ls180 update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end attribute \src "ls180.v:358.5-358.36" - process $proc$ls180.v:358$3197 + process $proc$ls180.v:358$3199 assign { } { } assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 sync always @@ -291910,7 +291936,7 @@ module \ls180 update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] end attribute \src "ls180.v:359.11-359.32" - process $proc$ls180.v:359$3198 + process $proc$ls180.v:359$3200 assign { } { } assign $1\main_rddata_en[2:0] 3'000 sync always @@ -291918,7 +291944,7 @@ module \ls180 update \main_rddata_en $1\main_rddata_en[2:0] end attribute \src "ls180.v:362.5-362.36" - process $proc$ls180.v:362$3199 + process $proc$ls180.v:362$3201 assign { } { } assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 sync always @@ -291926,7 +291952,7 @@ module \ls180 update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end attribute \src "ls180.v:363.5-363.35" - process $proc$ls180.v:363$3200 + process $proc$ls180.v:363$3202 assign { } { } assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 sync always @@ -291934,7 +291960,7 @@ module \ls180 update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end attribute \src "ls180.v:364.5-364.36" - process $proc$ls180.v:364$3201 + process $proc$ls180.v:364$3203 assign { } { } assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 sync always @@ -291942,7 +291968,7 @@ module \ls180 update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end attribute \src "ls180.v:365.5-365.35" - process $proc$ls180.v:365$3202 + process $proc$ls180.v:365$3204 assign { } { } assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always @@ -291986,7 +292012,7 @@ module \ls180 update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end attribute \src "ls180.v:369.5-369.36" - process $proc$ls180.v:369$3203 + process $proc$ls180.v:369$3205 assign { } { } assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 sync always @@ -292025,6 +292051,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 @@ -292033,12 +292060,11 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state attribute \src "ls180.v:3732.2-3808.9" switch \builder_bankmachine2_state @@ -292187,7 +292213,7 @@ module \ls180 update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end attribute \src "ls180.v:374.12-374.45" - process $proc$ls180.v:374$3204 + process $proc$ls180.v:374$3206 assign { } { } assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always @@ -292195,7 +292221,7 @@ module \ls180 update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end attribute \src "ls180.v:375.5-375.43" - process $proc$ls180.v:375$3205 + process $proc$ls180.v:375$3207 assign { } { } assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always @@ -292270,6 +292296,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 @@ -292283,7 +292310,6 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state attribute \src "ls180.v:3889.2-3965.9" switch \builder_bankmachine3_state @@ -292432,7 +292458,7 @@ module \ls180 update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end attribute \src "ls180.v:390.12-390.46" - process $proc$ls180.v:390$3206 + process $proc$ls180.v:390$3208 assign { } { } assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always @@ -292440,7 +292466,7 @@ module \ls180 update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end attribute \src "ls180.v:391.5-391.44" - process $proc$ls180.v:391$3207 + process $proc$ls180.v:391$3209 assign { } { } assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always @@ -292448,7 +292474,7 @@ module \ls180 update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end attribute \src "ls180.v:392.12-392.48" - process $proc$ls180.v:392$3208 + process $proc$ls180.v:392$3210 assign { } { } assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always @@ -292456,7 +292482,7 @@ module \ls180 update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end attribute \src "ls180.v:393.11-393.43" - process $proc$ls180.v:393$3209 + process $proc$ls180.v:393$3211 assign { } { } assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always @@ -292464,7 +292490,7 @@ module \ls180 update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end attribute \src "ls180.v:394.5-394.38" - process $proc$ls180.v:394$3210 + process $proc$ls180.v:394$3212 assign { } { } assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 sync always @@ -292472,7 +292498,7 @@ module \ls180 update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end attribute \src "ls180.v:395.5-395.37" - process $proc$ls180.v:395$3211 + process $proc$ls180.v:395$3213 assign { } { } assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always @@ -292480,7 +292506,7 @@ module \ls180 update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end attribute \src "ls180.v:396.5-396.38" - process $proc$ls180.v:396$3212 + process $proc$ls180.v:396$3214 assign { } { } assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always @@ -292488,7 +292514,7 @@ module \ls180 update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end attribute \src "ls180.v:397.5-397.37" - process $proc$ls180.v:397$3213 + process $proc$ls180.v:397$3215 assign { } { } assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always @@ -292496,7 +292522,7 @@ module \ls180 update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end attribute \src "ls180.v:398.5-398.36" - process $proc$ls180.v:398$3214 + process $proc$ls180.v:398$3216 assign { } { } assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always @@ -292515,7 +292541,7 @@ module \ls180 update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end attribute \src "ls180.v:399.5-399.36" - process $proc$ls180.v:399$3215 + process $proc$ls180.v:399$3217 assign { } { } assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always @@ -292523,7 +292549,7 @@ module \ls180 update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end attribute \src "ls180.v:400.5-400.40" - process $proc$ls180.v:400$3216 + process $proc$ls180.v:400$3218 assign { } { } assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 sync always @@ -292559,7 +292585,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end attribute \src "ls180.v:401.5-401.38" - process $proc$ls180.v:401$3217 + process $proc$ls180.v:401$3219 assign { } { } assign $1\main_sdram_master_p0_act_n[0:0] 1'1 sync always @@ -292592,7 +292618,7 @@ module \ls180 update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end attribute \src "ls180.v:402.12-402.47" - process $proc$ls180.v:402$3218 + process $proc$ls180.v:402$3220 assign { } { } assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always @@ -292600,7 +292626,7 @@ module \ls180 update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] end attribute \src "ls180.v:403.5-403.42" - process $proc$ls180.v:403$3219 + process $proc$ls180.v:403$3221 assign { } { } assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 sync always @@ -292636,7 +292662,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end attribute \src "ls180.v:404.11-404.50" - process $proc$ls180.v:404$3220 + process $proc$ls180.v:404$3222 assign { } { } assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 sync always @@ -292658,7 +292684,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end attribute \src "ls180.v:405.5-405.42" - process $proc$ls180.v:405$3221 + process $proc$ls180.v:405$3223 assign { } { } assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 sync always @@ -292760,15 +292786,15 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_sdram_en1[0:0] 1'0 assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_en0[0:0] 1'0 - assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state attribute \src "ls180.v:4103.2-4162.9" @@ -292876,7 +292902,7 @@ module \ls180 update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end attribute \src "ls180.v:412.11-412.36" - process $proc$ls180.v:412$3222 + process $proc$ls180.v:412$3224 assign { } { } assign $1\main_sdram_storage[3:0] 4'0001 sync always @@ -292884,7 +292910,7 @@ module \ls180 update \main_sdram_storage $1\main_sdram_storage[3:0] end attribute \src "ls180.v:413.5-413.25" - process $proc$ls180.v:413$3223 + process $proc$ls180.v:413$3225 assign { } { } assign $1\main_sdram_re[0:0] 1'0 sync always @@ -292892,7 +292918,7 @@ module \ls180 update \main_sdram_re $1\main_sdram_re[0:0] end attribute \src "ls180.v:414.11-414.44" - process $proc$ls180.v:414$3224 + process $proc$ls180.v:414$3226 assign { } { } assign $1\main_sdram_command_storage[5:0] 6'000000 sync always @@ -292900,7 +292926,7 @@ module \ls180 update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] end attribute \src "ls180.v:415.5-415.33" - process $proc$ls180.v:415$3225 + process $proc$ls180.v:415$3227 assign { } { } assign $1\main_sdram_command_re[0:0] 1'0 sync always @@ -292929,7 +292955,7 @@ module \ls180 update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end attribute \src "ls180.v:419.5-419.38" - process $proc$ls180.v:419$3226 + process $proc$ls180.v:419$3228 assign { } { } assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always @@ -292937,7 +292963,7 @@ module \ls180 sync init end attribute \src "ls180.v:420.12-420.46" - process $proc$ls180.v:420$3227 + process $proc$ls180.v:420$3229 assign { } { } assign $1\main_sdram_address_storage[12:0] 13'0000000000000 sync always @@ -292962,7 +292988,7 @@ module \ls180 update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end attribute \src "ls180.v:421.5-421.33" - process $proc$ls180.v:421$3228 + process $proc$ls180.v:421$3230 assign { } { } assign $1\main_sdram_address_re[0:0] 1'0 sync always @@ -293058,7 +293084,7 @@ module \ls180 update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end attribute \src "ls180.v:422.11-422.45" - process $proc$ls180.v:422$3229 + process $proc$ls180.v:422$3231 assign { } { } assign $1\main_sdram_baddress_storage[1:0] 2'00 sync always @@ -293066,7 +293092,7 @@ module \ls180 update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] end attribute \src "ls180.v:423.5-423.34" - process $proc$ls180.v:423$3230 + process $proc$ls180.v:423$3232 assign { } { } assign $1\main_sdram_baddress_re[0:0] 1'0 sync always @@ -293074,7 +293100,7 @@ module \ls180 update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] end attribute \src "ls180.v:424.12-424.45" - process $proc$ls180.v:424$3231 + process $proc$ls180.v:424$3233 assign { } { } assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 sync always @@ -293082,7 +293108,7 @@ module \ls180 update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] end attribute \src "ls180.v:425.5-425.32" - process $proc$ls180.v:425$3232 + process $proc$ls180.v:425$3234 assign { } { } assign $1\main_sdram_wrdata_re[0:0] 1'0 sync always @@ -293090,7 +293116,7 @@ module \ls180 update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] end attribute \src "ls180.v:426.12-426.37" - process $proc$ls180.v:426$3233 + process $proc$ls180.v:426$3235 assign { } { } assign $1\main_sdram_status[15:0] 16'0000000000000000 sync always @@ -293294,6 +293320,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\main_spisdcard_clk_enable[0:0] 1'0 assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'0 @@ -293302,7 +293329,6 @@ module \ls180 assign $0\main_spisdcard_irq[0:0] 1'0 assign { } { } assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state attribute \src "ls180.v:4490.2-4526.9" switch \builder_spimaster1_state @@ -293408,7 +293434,7 @@ module \ls180 update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end attribute \src "ls180.v:456.12-456.46" - process $proc$ls180.v:456$3234 + process $proc$ls180.v:456$3236 assign { } { } assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always @@ -293416,7 +293442,7 @@ module \ls180 update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end attribute \src "ls180.v:457.11-457.47" - process $proc$ls180.v:457$3235 + process $proc$ls180.v:457$3237 assign { } { } assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always @@ -293433,6 +293459,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } @@ -293440,7 +293467,6 @@ module \ls180 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state attribute \src "ls180.v:4599.2-4621.9" switch \builder_sdphy_sdphyinit_state @@ -293489,7 +293515,7 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end attribute \src "ls180.v:459.12-459.45" - process $proc$ls180.v:459$3236 + process $proc$ls180.v:459$3238 assign { } { } assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always @@ -293497,7 +293523,7 @@ module \ls180 update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end attribute \src "ls180.v:460.11-460.40" - process $proc$ls180.v:460$3237 + process $proc$ls180.v:460$3239 assign { } { } assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 sync always @@ -293505,7 +293531,7 @@ module \ls180 update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] end attribute \src "ls180.v:461.5-461.35" - process $proc$ls180.v:461$3238 + process $proc$ls180.v:461$3240 assign { } { } assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 sync always @@ -293513,7 +293539,7 @@ module \ls180 update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end attribute \src "ls180.v:462.5-462.34" - process $proc$ls180.v:462$3239 + process $proc$ls180.v:462$3241 assign { } { } assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 sync always @@ -293530,6 +293556,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 @@ -293537,7 +293564,6 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:4633.2-4698.9" switch \builder_sdphy_sdphycmdw_state @@ -293643,7 +293669,7 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end attribute \src "ls180.v:463.5-463.35" - process $proc$ls180.v:463$3240 + process $proc$ls180.v:463$3242 assign { } { } assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always @@ -293651,7 +293677,7 @@ module \ls180 update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end attribute \src "ls180.v:464.5-464.34" - process $proc$ls180.v:464$3241 + process $proc$ls180.v:464$3243 assign { } { } assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always @@ -293659,7 +293685,7 @@ module \ls180 update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end attribute \src "ls180.v:468.5-468.35" - process $proc$ls180.v:468$3242 + process $proc$ls180.v:468$3244 assign { } { } assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always @@ -293667,7 +293693,7 @@ module \ls180 sync init end attribute \src "ls180.v:470.5-470.39" - process $proc$ls180.v:470$3243 + process $proc$ls180.v:470$3245 assign { } { } assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always @@ -293675,7 +293701,7 @@ module \ls180 update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end attribute \src "ls180.v:472.5-472.39" - process $proc$ls180.v:472$3244 + process $proc$ls180.v:472$3246 assign { } { } assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always @@ -293852,7 +293878,7 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end attribute \src "ls180.v:475.5-475.32" - process $proc$ls180.v:475$3245 + process $proc$ls180.v:475$3247 assign { } { } assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always @@ -293860,7 +293886,7 @@ module \ls180 update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end attribute \src "ls180.v:476.5-476.32" - process $proc$ls180.v:476$3246 + process $proc$ls180.v:476$3248 assign { } { } assign $1\main_sdram_cmd_ready[0:0] 1'0 sync always @@ -293868,7 +293894,7 @@ module \ls180 update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end attribute \src "ls180.v:477.5-477.31" - process $proc$ls180.v:477$3247 + process $proc$ls180.v:477$3249 assign { } { } assign $1\main_sdram_cmd_last[0:0] 1'0 sync always @@ -293876,7 +293902,7 @@ module \ls180 update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end attribute \src "ls180.v:478.12-478.44" - process $proc$ls180.v:478$3248 + process $proc$ls180.v:478$3250 assign { } { } assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -293884,7 +293910,7 @@ module \ls180 update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end attribute \src "ls180.v:479.11-479.43" - process $proc$ls180.v:479$3249 + process $proc$ls180.v:479$3251 assign { } { } assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always @@ -293892,7 +293918,7 @@ module \ls180 update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end attribute \src "ls180.v:480.5-480.38" - process $proc$ls180.v:480$3250 + process $proc$ls180.v:480$3252 assign { } { } assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always @@ -293900,7 +293926,7 @@ module \ls180 update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end attribute \src "ls180.v:481.5-481.38" - process $proc$ls180.v:481$3251 + process $proc$ls180.v:481$3253 assign { } { } assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always @@ -293908,7 +293934,7 @@ module \ls180 update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end attribute \src "ls180.v:482.5-482.37" - process $proc$ls180.v:482$3252 + process $proc$ls180.v:482$3254 assign { } { } assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always @@ -293916,7 +293942,7 @@ module \ls180 update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] end attribute \src "ls180.v:483.5-483.42" - process $proc$ls180.v:483$3253 + process $proc$ls180.v:483$3255 assign { } { } assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 sync always @@ -293924,7 +293950,7 @@ module \ls180 sync init end attribute \src "ls180.v:484.5-484.43" - process $proc$ls180.v:484$3254 + process $proc$ls180.v:484$3256 assign { } { } assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 sync always @@ -293939,12 +293965,12 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:4868.2-4886.9" switch \builder_sdphy_sdphycrcr_state @@ -294111,7 +294137,7 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end attribute \src "ls180.v:490.11-490.44" - process $proc$ls180.v:490$3255 + process $proc$ls180.v:490$3257 assign { } { } assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always @@ -294119,7 +294145,7 @@ module \ls180 update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end attribute \src "ls180.v:492.5-492.38" - process $proc$ls180.v:492$3256 + process $proc$ls180.v:492$3258 assign { } { } assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always @@ -294127,7 +294153,7 @@ module \ls180 update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end attribute \src "ls180.v:493.5-493.38" - process $proc$ls180.v:493$3257 + process $proc$ls180.v:493$3259 assign { } { } assign $1\main_sdram_postponer_count[0:0] 1'0 sync always @@ -294135,7 +294161,7 @@ module \ls180 update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end attribute \src "ls180.v:494.5-494.39" - process $proc$ls180.v:494$3258 + process $proc$ls180.v:494$3260 assign { } { } assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always @@ -294143,7 +294169,7 @@ module \ls180 update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end attribute \src "ls180.v:497.5-497.38" - process $proc$ls180.v:497$3259 + process $proc$ls180.v:497$3261 assign { } { } assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always @@ -294151,7 +294177,7 @@ module \ls180 update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end attribute \src "ls180.v:498.11-498.46" - process $proc$ls180.v:498$3260 + process $proc$ls180.v:498$3262 assign { } { } assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always @@ -294159,7 +294185,7 @@ module \ls180 update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end attribute \src "ls180.v:499.5-499.38" - process $proc$ls180.v:499$3261 + process $proc$ls180.v:499$3263 assign { } { } assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always @@ -294183,12 +294209,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 @@ -294197,7 +294224,6 @@ module \ls180 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state attribute \src "ls180.v:5011.2-5094.9" switch \builder_sdphy_sdphydatar_state @@ -294350,7 +294376,7 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end attribute \src "ls180.v:505.5-505.51" - process $proc$ls180.v:505$3262 + process $proc$ls180.v:505$3264 assign { } { } assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always @@ -294358,7 +294384,7 @@ module \ls180 update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] end attribute \src "ls180.v:506.5-506.51" - process $proc$ls180.v:506$3263 + process $proc$ls180.v:506$3265 assign { } { } assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always @@ -294366,7 +294392,7 @@ module \ls180 update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end attribute \src "ls180.v:508.5-508.47" - process $proc$ls180.v:508$3264 + process $proc$ls180.v:508$3266 assign { } { } assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always @@ -294374,7 +294400,7 @@ module \ls180 update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] end attribute \src "ls180.v:509.5-509.45" - process $proc$ls180.v:509$3265 + process $proc$ls180.v:509$3267 assign { } { } assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always @@ -294382,7 +294408,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end attribute \src "ls180.v:510.5-510.45" - process $proc$ls180.v:510$3266 + process $proc$ls180.v:510$3268 assign { } { } assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always @@ -294390,7 +294416,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end attribute \src "ls180.v:511.12-511.57" - process $proc$ls180.v:511$3267 + process $proc$ls180.v:511$3269 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -294398,7 +294424,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] end attribute \src "ls180.v:513.5-513.51" - process $proc$ls180.v:513$3268 + process $proc$ls180.v:513$3270 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always @@ -294406,7 +294432,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end attribute \src "ls180.v:514.5-514.51" - process $proc$ls180.v:514$3269 + process $proc$ls180.v:514$3271 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always @@ -294414,7 +294440,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end attribute \src "ls180.v:515.5-515.50" - process $proc$ls180.v:515$3270 + process $proc$ls180.v:515$3272 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always @@ -294438,7 +294464,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end attribute \src "ls180.v:516.5-516.54" - process $proc$ls180.v:516$3271 + process $proc$ls180.v:516$3273 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -294446,7 +294472,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:517.5-517.55" - process $proc$ls180.v:517$3272 + process $proc$ls180.v:517$3274 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always @@ -294470,7 +294496,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end attribute \src "ls180.v:518.5-518.56" - process $proc$ls180.v:518$3273 + process $proc$ls180.v:518$3275 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 sync always @@ -294494,7 +294520,7 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end attribute \src "ls180.v:519.5-519.50" - process $proc$ls180.v:519$3274 + process $proc$ls180.v:519$3276 assign { } { } assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always @@ -294550,6 +294576,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign { } { } @@ -294557,7 +294584,6 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 @@ -294665,7 +294691,7 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end attribute \src "ls180.v:522.5-522.67" - process $proc$ls180.v:522$3275 + process $proc$ls180.v:522$3277 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -294673,7 +294699,7 @@ module \ls180 sync init end attribute \src "ls180.v:523.5-523.66" - process $proc$ls180.v:523$3276 + process $proc$ls180.v:523$3278 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -294837,7 +294863,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end attribute \src "ls180.v:538.11-538.68" - process $proc$ls180.v:538$3277 + process $proc$ls180.v:538$3279 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -294861,7 +294887,7 @@ module \ls180 update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end attribute \src "ls180.v:539.5-539.64" - process $proc$ls180.v:539$3278 + process $proc$ls180.v:539$3280 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -294909,6 +294935,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -294947,7 +294974,6 @@ module \ls180 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state attribute \src "ls180.v:5436.2-5584.9" switch \builder_sdcore_fsm_state @@ -295219,7 +295245,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end attribute \src "ls180.v:540.11-540.70" - process $proc$ls180.v:540$3279 + process $proc$ls180.v:540$3281 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -295227,7 +295253,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:541.11-541.70" - process $proc$ls180.v:541$3280 + process $proc$ls180.v:541$3282 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -295235,7 +295261,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:542.11-542.73" - process $proc$ls180.v:542$3281 + process $proc$ls180.v:542$3283 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -295243,7 +295269,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$3126 + process $proc$ls180.v:55$3128 assign { } { } assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always @@ -295251,7 +295277,7 @@ module \ls180 update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$3127 + process $proc$ls180.v:56$3129 assign { } { } assign $1\main_libresocsim_reset_re[0:0] 1'0 sync always @@ -295275,7 +295301,7 @@ module \ls180 update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end attribute \src "ls180.v:563.5-563.59" - process $proc$ls180.v:563$3282 + process $proc$ls180.v:563$3284 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -295354,7 +295380,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end attribute \src "ls180.v:565.5-565.59" - process $proc$ls180.v:565$3283 + process $proc$ls180.v:565$3285 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always @@ -295362,7 +295388,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:566.5-566.58" - process $proc$ls180.v:566$3284 + process $proc$ls180.v:566$3286 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always @@ -295370,7 +295396,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:567.5-567.64" - process $proc$ls180.v:567$3285 + process $proc$ls180.v:567$3287 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -295378,7 +295404,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:568.12-568.74" - process $proc$ls180.v:568$3286 + process $proc$ls180.v:568$3288 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -295386,7 +295412,7 @@ module \ls180 update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:569.12-569.47" - process $proc$ls180.v:569$3287 + process $proc$ls180.v:569$3289 assign { } { } assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 sync always @@ -295394,7 +295420,7 @@ module \ls180 update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$3128 + process $proc$ls180.v:57$3130 assign { } { } assign $1\main_libresocsim_scratch_storage[31:0] 305419896 sync always @@ -295402,7 +295428,7 @@ module \ls180 update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end attribute \src "ls180.v:570.5-570.46" - process $proc$ls180.v:570$3288 + process $proc$ls180.v:570$3290 assign { } { } assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 sync always @@ -295423,6 +295449,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 assign { } { } assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 @@ -295431,10 +295459,8 @@ module \ls180 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:5719.2-5741.9" switch \builder_sdmem2blockdma_fsm_state @@ -295483,7 +295509,7 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end attribute \src "ls180.v:572.5-572.44" - process $proc$ls180.v:572$3289 + process $proc$ls180.v:572$3291 assign { } { } assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 sync always @@ -295491,7 +295517,7 @@ module \ls180 update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] end attribute \src "ls180.v:573.5-573.45" - process $proc$ls180.v:573$3290 + process $proc$ls180.v:573$3292 assign { } { } assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always @@ -295499,7 +295525,7 @@ module \ls180 update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end attribute \src "ls180.v:574.5-574.54" - process $proc$ls180.v:574$3291 + process $proc$ls180.v:574$3293 assign { } { } assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always @@ -295515,13 +295541,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign { } { } assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:5752.2-5778.9" switch \builder_sdmem2blockdma_resetinserter_state @@ -295573,7 +295599,7 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end attribute \src "ls180.v:576.32-576.76" - process $proc$ls180.v:576$3292 + process $proc$ls180.v:576$3294 assign { } { } assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always @@ -295581,7 +295607,7 @@ module \ls180 update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end attribute \src "ls180.v:577.11-577.55" - process $proc$ls180.v:577$3293 + process $proc$ls180.v:577$3295 assign { } { } assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always @@ -295589,7 +295615,7 @@ module \ls180 update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end attribute \src "ls180.v:579.32-579.75" - process $proc$ls180.v:579$3294 + process $proc$ls180.v:579$3296 assign { } { } assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always @@ -295631,7 +295657,7 @@ module \ls180 update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$3129 + process $proc$ls180.v:58$3131 assign { } { } assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always @@ -295639,7 +295665,7 @@ module \ls180 update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end attribute \src "ls180.v:581.32-581.76" - process $proc$ls180.v:581$3295 + process $proc$ls180.v:581$3297 assign { } { } assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always @@ -295725,7 +295751,7 @@ module \ls180 update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end attribute \src "ls180.v:587.5-587.51" - process $proc$ls180.v:587$3296 + process $proc$ls180.v:587$3298 assign { } { } assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always @@ -295733,7 +295759,7 @@ module \ls180 update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end attribute \src "ls180.v:588.5-588.51" - process $proc$ls180.v:588$3297 + process $proc$ls180.v:588$3299 assign { } { } assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always @@ -295741,7 +295767,7 @@ module \ls180 update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end attribute \src "ls180.v:590.5-590.47" - process $proc$ls180.v:590$3298 + process $proc$ls180.v:590$3300 assign { } { } assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always @@ -295769,7 +295795,7 @@ module \ls180 update \builder_slave_sel $0\builder_slave_sel[12:0] end attribute \src "ls180.v:591.5-591.45" - process $proc$ls180.v:591$3299 + process $proc$ls180.v:591$3301 assign { } { } assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always @@ -295777,7 +295803,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] end attribute \src "ls180.v:592.5-592.45" - process $proc$ls180.v:592$3300 + process $proc$ls180.v:592$3302 assign { } { } assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always @@ -295785,7 +295811,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end attribute \src "ls180.v:593.12-593.57" - process $proc$ls180.v:593$3301 + process $proc$ls180.v:593$3303 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -295793,7 +295819,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end attribute \src "ls180.v:595.5-595.51" - process $proc$ls180.v:595$3302 + process $proc$ls180.v:595$3304 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always @@ -295801,7 +295827,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end attribute \src "ls180.v:596.5-596.51" - process $proc$ls180.v:596$3303 + process $proc$ls180.v:596$3305 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always @@ -295809,7 +295835,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end attribute \src "ls180.v:597.5-597.50" - process $proc$ls180.v:597$3304 + process $proc$ls180.v:597$3306 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always @@ -295817,7 +295843,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end attribute \src "ls180.v:598.5-598.54" - process $proc$ls180.v:598$3305 + process $proc$ls180.v:598$3307 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -295825,7 +295851,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:599.5-599.55" - process $proc$ls180.v:599$3306 + process $proc$ls180.v:599$3308 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always @@ -295833,7 +295859,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] end attribute \src "ls180.v:600.5-600.56" - process $proc$ls180.v:600$3307 + process $proc$ls180.v:600$3309 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always @@ -295841,7 +295867,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end attribute \src "ls180.v:601.5-601.50" - process $proc$ls180.v:601$3308 + process $proc$ls180.v:601$3310 assign { } { } assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always @@ -295873,7 +295899,7 @@ module \ls180 update \builder_error $0\builder_error[0:0] end attribute \src "ls180.v:604.5-604.67" - process $proc$ls180.v:604$3309 + process $proc$ls180.v:604$3311 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -295881,7 +295907,7 @@ module \ls180 sync init end attribute \src "ls180.v:605.5-605.66" - process $proc$ls180.v:605$3310 + process $proc$ls180.v:605$3312 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -295889,7 +295915,7 @@ module \ls180 sync init end attribute \src "ls180.v:620.11-620.68" - process $proc$ls180.v:620$3311 + process $proc$ls180.v:620$3313 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -295897,7 +295923,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:621.5-621.64" - process $proc$ls180.v:621$3312 + process $proc$ls180.v:621$3314 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -295905,7 +295931,7 @@ module \ls180 sync init end attribute \src "ls180.v:622.11-622.70" - process $proc$ls180.v:622$3313 + process $proc$ls180.v:622$3315 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -295913,7 +295939,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:623.11-623.70" - process $proc$ls180.v:623$3314 + process $proc$ls180.v:623$3316 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -295921,7 +295947,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:624.11-624.73" - process $proc$ls180.v:624$3315 + process $proc$ls180.v:624$3317 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -295929,7 +295955,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$3130 + process $proc$ls180.v:63$3132 assign { } { } assign $1\main_libresocsim_bus_errors[31:0] 0 sync always @@ -295937,7 +295963,7 @@ module \ls180 update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end attribute \src "ls180.v:645.5-645.59" - process $proc$ls180.v:645$3316 + process $proc$ls180.v:645$3318 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -295945,7 +295971,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:647.5-647.59" - process $proc$ls180.v:647$3317 + process $proc$ls180.v:647$3319 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always @@ -295953,7 +295979,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:648.5-648.58" - process $proc$ls180.v:648$3318 + process $proc$ls180.v:648$3320 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always @@ -295961,7 +295987,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:649.5-649.64" - process $proc$ls180.v:649$3319 + process $proc$ls180.v:649$3321 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -295969,7 +295995,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$3131 + process $proc$ls180.v:65$3133 assign { } { } assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always @@ -295977,7 +296003,7 @@ module \ls180 update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end attribute \src "ls180.v:650.12-650.74" - process $proc$ls180.v:650$3320 + process $proc$ls180.v:650$3322 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -295985,7 +296011,7 @@ module \ls180 update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:651.12-651.47" - process $proc$ls180.v:651$3321 + process $proc$ls180.v:651$3323 assign { } { } assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always @@ -295993,7 +296019,7 @@ module \ls180 update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end attribute \src "ls180.v:652.5-652.46" - process $proc$ls180.v:652$3322 + process $proc$ls180.v:652$3324 assign { } { } assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always @@ -296001,7 +296027,7 @@ module \ls180 update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end attribute \src "ls180.v:654.5-654.44" - process $proc$ls180.v:654$3323 + process $proc$ls180.v:654$3325 assign { } { } assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always @@ -296009,7 +296035,7 @@ module \ls180 update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end attribute \src "ls180.v:655.5-655.45" - process $proc$ls180.v:655$3324 + process $proc$ls180.v:655$3326 assign { } { } assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always @@ -296031,7 +296057,7 @@ module \ls180 update \main_spimaster9_start $0\main_spimaster9_start[0:0] end attribute \src "ls180.v:656.5-656.54" - process $proc$ls180.v:656$3325 + process $proc$ls180.v:656$3327 assign { } { } assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always @@ -296039,7 +296065,7 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:658.32-658.76" - process $proc$ls180.v:658$3326 + process $proc$ls180.v:658$3328 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always @@ -296047,7 +296073,7 @@ module \ls180 update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end attribute \src "ls180.v:659.11-659.55" - process $proc$ls180.v:659$3327 + process $proc$ls180.v:659$3329 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always @@ -296069,7 +296095,7 @@ module \ls180 update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] end attribute \src "ls180.v:661.32-661.75" - process $proc$ls180.v:661$3328 + process $proc$ls180.v:661$3330 assign { } { } assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always @@ -296077,7 +296103,7 @@ module \ls180 sync init end attribute \src "ls180.v:663.32-663.76" - process $proc$ls180.v:663$3329 + process $proc$ls180.v:663$3331 assign { } { } assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always @@ -296085,7 +296111,7 @@ module \ls180 sync init end attribute \src "ls180.v:669.5-669.51" - process $proc$ls180.v:669$3330 + process $proc$ls180.v:669$3332 assign { } { } assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always @@ -296093,7 +296119,7 @@ module \ls180 update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end attribute \src "ls180.v:670.5-670.51" - process $proc$ls180.v:670$3331 + process $proc$ls180.v:670$3333 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always @@ -296101,7 +296127,7 @@ module \ls180 update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end attribute \src "ls180.v:672.5-672.47" - process $proc$ls180.v:672$3332 + process $proc$ls180.v:672$3334 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always @@ -296109,7 +296135,7 @@ module \ls180 update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end attribute \src "ls180.v:673.5-673.45" - process $proc$ls180.v:673$3333 + process $proc$ls180.v:673$3335 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always @@ -296117,7 +296143,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end attribute \src "ls180.v:674.5-674.45" - process $proc$ls180.v:674$3334 + process $proc$ls180.v:674$3336 assign { } { } assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always @@ -296125,7 +296151,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end attribute \src "ls180.v:675.12-675.57" - process $proc$ls180.v:675$3335 + process $proc$ls180.v:675$3337 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -296133,7 +296159,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end attribute \src "ls180.v:677.5-677.51" - process $proc$ls180.v:677$3336 + process $proc$ls180.v:677$3338 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always @@ -296141,7 +296167,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end attribute \src "ls180.v:678.5-678.51" - process $proc$ls180.v:678$3337 + process $proc$ls180.v:678$3339 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always @@ -296149,7 +296175,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end attribute \src "ls180.v:679.5-679.50" - process $proc$ls180.v:679$3338 + process $proc$ls180.v:679$3340 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always @@ -296179,7 +296205,7 @@ module \ls180 update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end attribute \src "ls180.v:680.5-680.54" - process $proc$ls180.v:680$3339 + process $proc$ls180.v:680$3341 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -296209,7 +296235,7 @@ module \ls180 update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end attribute \src "ls180.v:681.5-681.55" - process $proc$ls180.v:681$3340 + process $proc$ls180.v:681$3342 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always @@ -296217,7 +296243,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end attribute \src "ls180.v:682.5-682.56" - process $proc$ls180.v:682$3341 + process $proc$ls180.v:682$3343 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always @@ -296247,7 +296273,7 @@ module \ls180 update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end attribute \src "ls180.v:683.5-683.50" - process $proc$ls180.v:683$3342 + process $proc$ls180.v:683$3344 assign { } { } assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always @@ -296299,7 +296325,7 @@ module \ls180 update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end attribute \src "ls180.v:686.5-686.67" - process $proc$ls180.v:686$3343 + process $proc$ls180.v:686$3345 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -296307,7 +296333,7 @@ module \ls180 sync init end attribute \src "ls180.v:687.5-687.66" - process $proc$ls180.v:687$3344 + process $proc$ls180.v:687$3346 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -296513,7 +296539,7 @@ module \ls180 update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end attribute \src "ls180.v:702.11-702.68" - process $proc$ls180.v:702$3345 + process $proc$ls180.v:702$3347 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -296543,7 +296569,7 @@ module \ls180 update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end attribute \src "ls180.v:703.5-703.64" - process $proc$ls180.v:703$3346 + process $proc$ls180.v:703$3348 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -296551,7 +296577,7 @@ module \ls180 sync init end attribute \src "ls180.v:704.11-704.70" - process $proc$ls180.v:704$3347 + process $proc$ls180.v:704$3349 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -296581,7 +296607,7 @@ module \ls180 update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end attribute \src "ls180.v:705.11-705.70" - process $proc$ls180.v:705$3348 + process $proc$ls180.v:705$3350 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -296589,7 +296615,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:706.11-706.73" - process $proc$ls180.v:706$3349 + process $proc$ls180.v:706$3351 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -296897,7 +296923,7 @@ module \ls180 update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end attribute \src "ls180.v:727.5-727.59" - process $proc$ls180.v:727$3350 + process $proc$ls180.v:727$3352 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -296930,7 +296956,7 @@ module \ls180 update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end attribute \src "ls180.v:729.5-729.59" - process $proc$ls180.v:729$3351 + process $proc$ls180.v:729$3353 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always @@ -296963,7 +296989,7 @@ module \ls180 update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end attribute \src "ls180.v:730.5-730.58" - process $proc$ls180.v:730$3352 + process $proc$ls180.v:730$3354 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always @@ -296971,7 +296997,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:731.5-731.64" - process $proc$ls180.v:731$3353 + process $proc$ls180.v:731$3355 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -297004,7 +297030,7 @@ module \ls180 update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end attribute \src "ls180.v:732.12-732.74" - process $proc$ls180.v:732$3354 + process $proc$ls180.v:732$3356 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -297012,7 +297038,7 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:733.12-733.47" - process $proc$ls180.v:733$3355 + process $proc$ls180.v:733$3357 assign { } { } assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always @@ -297045,7 +297071,7 @@ module \ls180 update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end attribute \src "ls180.v:734.5-734.46" - process $proc$ls180.v:734$3356 + process $proc$ls180.v:734$3358 assign { } { } assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always @@ -297075,7 +297101,7 @@ module \ls180 update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end attribute \src "ls180.v:736.5-736.44" - process $proc$ls180.v:736$3357 + process $proc$ls180.v:736$3359 assign { } { } assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 sync always @@ -297083,7 +297109,7 @@ module \ls180 update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end attribute \src "ls180.v:737.5-737.45" - process $proc$ls180.v:737$3358 + process $proc$ls180.v:737$3360 assign { } { } assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 sync always @@ -297113,7 +297139,7 @@ module \ls180 update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end attribute \src "ls180.v:738.5-738.54" - process $proc$ls180.v:738$3359 + process $proc$ls180.v:738$3361 assign { } { } assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always @@ -297143,7 +297169,7 @@ module \ls180 update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end attribute \src "ls180.v:74.11-74.52" - process $proc$ls180.v:74$3132 + process $proc$ls180.v:74$3134 assign { } { } assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 sync always @@ -297151,7 +297177,7 @@ module \ls180 sync init end attribute \src "ls180.v:740.32-740.76" - process $proc$ls180.v:740$3360 + process $proc$ls180.v:740$3362 assign { } { } assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always @@ -297181,7 +297207,7 @@ module \ls180 update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end attribute \src "ls180.v:741.11-741.55" - process $proc$ls180.v:741$3361 + process $proc$ls180.v:741$3363 assign { } { } assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always @@ -297211,7 +297237,7 @@ module \ls180 update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end attribute \src "ls180.v:743.32-743.75" - process $proc$ls180.v:743$3362 + process $proc$ls180.v:743$3364 assign { } { } assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always @@ -297241,7 +297267,7 @@ module \ls180 update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end attribute \src "ls180.v:745.32-745.76" - process $proc$ls180.v:745$3363 + process $proc$ls180.v:745$3365 assign { } { } assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always @@ -297305,7 +297331,7 @@ module \ls180 update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$3133 + process $proc$ls180.v:75$3135 assign { } { } assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 sync always @@ -297347,7 +297373,7 @@ module \ls180 update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end attribute \src "ls180.v:751.5-751.51" - process $proc$ls180.v:751$3364 + process $proc$ls180.v:751$3366 assign { } { } assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always @@ -297355,7 +297381,7 @@ module \ls180 update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end attribute \src "ls180.v:752.5-752.51" - process $proc$ls180.v:752$3365 + process $proc$ls180.v:752$3367 assign { } { } assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always @@ -297363,7 +297389,7 @@ module \ls180 update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end attribute \src "ls180.v:754.5-754.47" - process $proc$ls180.v:754$3366 + process $proc$ls180.v:754$3368 assign { } { } assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always @@ -297371,7 +297397,7 @@ module \ls180 update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end attribute \src "ls180.v:755.5-755.45" - process $proc$ls180.v:755$3367 + process $proc$ls180.v:755$3369 assign { } { } assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always @@ -297379,7 +297405,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end attribute \src "ls180.v:756.5-756.45" - process $proc$ls180.v:756$3368 + process $proc$ls180.v:756$3370 assign { } { } assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always @@ -297387,7 +297413,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end attribute \src "ls180.v:757.12-757.57" - process $proc$ls180.v:757$3369 + process $proc$ls180.v:757$3371 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always @@ -297410,7 +297436,7 @@ module \ls180 update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] end attribute \src "ls180.v:759.5-759.51" - process $proc$ls180.v:759$3370 + process $proc$ls180.v:759$3372 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always @@ -297433,7 +297459,7 @@ module \ls180 update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] end attribute \src "ls180.v:760.5-760.51" - process $proc$ls180.v:760$3371 + process $proc$ls180.v:760$3373 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 sync always @@ -297441,7 +297467,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end attribute \src "ls180.v:761.5-761.50" - process $proc$ls180.v:761$3372 + process $proc$ls180.v:761$3374 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always @@ -297449,7 +297475,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end attribute \src "ls180.v:762.5-762.54" - process $proc$ls180.v:762$3373 + process $proc$ls180.v:762$3375 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always @@ -297464,7 +297490,7 @@ module \ls180 update \main_int_rst $0\main_int_rst[0:0] end attribute \src "ls180.v:763.5-763.55" - process $proc$ls180.v:763$3374 + process $proc$ls180.v:763$3376 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always @@ -297545,10 +297571,10 @@ module \ls180 assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] - assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_dm[1:0] [0] $and$ls180.v:7687$2571_Y + assign $0\sdram_dm[1:0] [1] $and$ls180.v:7688$2572_Y assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2572_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2574_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -297562,11 +297588,6 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -297578,12 +297599,17 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end attribute \src "ls180.v:764.5-764.56" - process $proc$ls180.v:764$3375 + process $proc$ls180.v:764$3377 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 sync always @@ -297591,7 +297617,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end attribute \src "ls180.v:765.5-765.50" - process $proc$ls180.v:765$3376 + process $proc$ls180.v:765$3378 assign { } { } assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 sync always @@ -297599,7 +297625,7 @@ module \ls180 update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end attribute \src "ls180.v:768.5-768.67" - process $proc$ls180.v:768$3377 + process $proc$ls180.v:768$3379 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always @@ -297607,7 +297633,7 @@ module \ls180 sync init end attribute \src "ls180.v:769.5-769.66" - process $proc$ls180.v:769$3378 + process $proc$ls180.v:769$3380 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always @@ -297615,15 +297641,15 @@ module \ls180 sync init end attribute \src "ls180.v:7705.1-10349.4" - process $proc$ls180.v:7705$2573 - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi - assign { } { } + process $proc$ls180.v:7705$2575 assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } - assign $0\uart_tx[0:0] \uart_tx assign $0\pwm[1:0] \pwm + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\uart_tx[0:0] \uart_tx assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage @@ -298032,30 +298058,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2574_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2575_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2576_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2577_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2578_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2579_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2580_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2581_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2582_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2583_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2584_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2585_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2586_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2587_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2588_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2589_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2590_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2591_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2592_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2593_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2594_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2595_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2596_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2597_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2576_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2577_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2578_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2579_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2580_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2581_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2582_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2583_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2584_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2585_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2586_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2587_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2588_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2589_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2590_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2591_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2592_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2593_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2594_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2595_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2596_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2597_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2598_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2599_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state @@ -298082,14 +298108,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2706_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2707_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2708_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2708_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2709_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2710_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2726_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2738_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2728_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2740_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -298099,11 +298125,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2784_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2787_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2786_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2789_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2789_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2792_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2791_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2794_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -298215,7 +298241,7 @@ module \ls180 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 attribute \src "ls180.v:7730.2-7732.5" - switch $or$ls180.v:7730$2598_Y + switch $or$ls180.v:7730$2600_Y attribute \src "ls180.v:7730.6-7730.69" case 1'1 assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r @@ -298237,7 +298263,7 @@ module \ls180 case end attribute \src "ls180.v:7741.2-7743.5" - switch $or$ls180.v:7741$2599_Y + switch $or$ls180.v:7741$2601_Y attribute \src "ls180.v:7741.6-7741.69" case 1'1 assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r @@ -298259,7 +298285,7 @@ module \ls180 case end attribute \src "ls180.v:7752.2-7754.5" - switch $or$ls180.v:7752$2600_Y + switch $or$ls180.v:7752$2602_Y attribute \src "ls180.v:7752.6-7752.51" case 1'1 assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r @@ -298281,20 +298307,20 @@ module \ls180 case end attribute \src "ls180.v:7763.2-7767.5" - switch $ne$ls180.v:7763$2601_Y + switch $ne$ls180.v:7763$2603_Y attribute \src "ls180.v:7763.6-7763.53" case 1'1 attribute \src "ls180.v:7764.3-7766.6" switch \main_libresocsim_bus_error attribute \src "ls180.v:7764.7-7764.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2602_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2604_Y case end case end attribute \src "ls180.v:7769.2-7771.5" - switch $and$ls180.v:7769$2605_Y + switch $and$ls180.v:7769$2607_Y attribute \src "ls180.v:7769.6-7769.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 @@ -298305,13 +298331,13 @@ module \ls180 attribute \src "ls180.v:7772.6-7772.33" case 1'1 attribute \src "ls180.v:7773.3-7777.6" - switch $eq$ls180.v:7773$2606_Y + switch $eq$ls180.v:7773$2608_Y attribute \src "ls180.v:7773.7-7773.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage attribute \src "ls180.v:7775.7-7775.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2607_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2609_Y end attribute \src "ls180.v:7778.6-7778.10" case @@ -298332,35 +298358,35 @@ module \ls180 case end attribute \src "ls180.v:7788.2-7790.5" - switch $and$ls180.v:7788$2609_Y + switch $and$ls180.v:7788$2611_Y attribute \src "ls180.v:7788.6-7788.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end attribute \src "ls180.v:7792.2-7794.5" - switch $and$ls180.v:7792$2612_Y + switch $and$ls180.v:7792$2614_Y attribute \src "ls180.v:7792.6-7792.100" case 1'1 assign $0\main_interface0_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:7796.2-7798.5" - switch $and$ls180.v:7796$2615_Y + switch $and$ls180.v:7796$2617_Y attribute \src "ls180.v:7796.6-7796.100" case 1'1 assign $0\main_interface1_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:7800.2-7802.5" - switch $and$ls180.v:7800$2618_Y + switch $and$ls180.v:7800$2620_Y attribute \src "ls180.v:7800.6-7800.100" case 1'1 assign $0\main_interface2_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:7804.2-7806.5" - switch $and$ls180.v:7804$2621_Y + switch $and$ls180.v:7804$2623_Y attribute \src "ls180.v:7804.6-7804.100" case 1'1 assign $0\main_interface3_ram_bus_ack[0:0] 1'1 @@ -298374,10 +298400,10 @@ module \ls180 case end attribute \src "ls180.v:7812.2-7816.5" - switch $and$ls180.v:7812$2623_Y + switch $and$ls180.v:7812$2625_Y attribute \src "ls180.v:7812.6-7812.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2624_Y + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2626_Y attribute \src "ls180.v:7814.6-7814.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 @@ -298386,9 +298412,9 @@ module \ls180 switch \main_sdram_postponer_req_i attribute \src "ls180.v:7818.6-7818.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2625_Y + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2627_Y attribute \src "ls180.v:7820.3-7823.6" - switch $eq$ls180.v:7820$2626_Y + switch $eq$ls180.v:7820$2628_Y attribute \src "ls180.v:7820.7-7820.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 @@ -298409,17 +298435,17 @@ module \ls180 attribute \src "ls180.v:7828.7-7828.33" case 1'1 attribute \src "ls180.v:7829.4-7831.7" - switch $ne$ls180.v:7829$2627_Y + switch $ne$ls180.v:7829$2629_Y attribute \src "ls180.v:7829.8-7829.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2628_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2630_Y case end case end end attribute \src "ls180.v:7840.2-7846.5" - switch $and$ls180.v:7840$2630_Y + switch $and$ls180.v:7840$2632_Y attribute \src "ls180.v:7840.6-7840.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 @@ -298430,7 +298456,7 @@ module \ls180 case end attribute \src "ls180.v:7847.2-7853.5" - switch $eq$ls180.v:7847$2631_Y + switch $eq$ls180.v:7847$2633_Y attribute \src "ls180.v:7847.6-7847.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 @@ -298441,7 +298467,7 @@ module \ls180 case end attribute \src "ls180.v:7854.2-7861.5" - switch $eq$ls180.v:7854$2632_Y + switch $eq$ls180.v:7854$2634_Y attribute \src "ls180.v:7854.6-7854.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 @@ -298453,17 +298479,17 @@ module \ls180 case end attribute \src "ls180.v:7862.2-7872.5" - switch $eq$ls180.v:7862$2633_Y + switch $eq$ls180.v:7862$2635_Y attribute \src "ls180.v:7862.6-7862.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 attribute \src "ls180.v:7864.6-7864.10" case attribute \src "ls180.v:7865.3-7871.6" - switch $ne$ls180.v:7865$2634_Y + switch $ne$ls180.v:7865$2636_Y attribute \src "ls180.v:7865.7-7865.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2635_Y + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2637_Y attribute \src "ls180.v:7867.7-7867.11" case attribute \src "ls180.v:7868.4-7870.7" @@ -298492,28 +298518,28 @@ module \ls180 end end attribute \src "ls180.v:7882.2-7884.5" - switch $and$ls180.v:7882$2638_Y + switch $and$ls180.v:7882$2640_Y attribute \src "ls180.v:7882.6-7882.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2639_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2641_Y case end attribute \src "ls180.v:7885.2-7887.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7885.6-7885.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2640_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2642_Y case end attribute \src "ls180.v:7888.2-7896.5" - switch $and$ls180.v:7888$2643_Y + switch $and$ls180.v:7888$2645_Y attribute \src "ls180.v:7888.6-7888.191" case 1'1 attribute \src "ls180.v:7889.3-7891.6" - switch $not$ls180.v:7889$2644_Y + switch $not$ls180.v:7889$2646_Y attribute \src "ls180.v:7889.7-7889.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2645_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2647_Y case end attribute \src "ls180.v:7892.6-7892.10" @@ -298522,12 +298548,12 @@ module \ls180 switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7893.7-7893.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2646_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2648_Y case end end attribute \src "ls180.v:7897.2-7903.5" - switch $or$ls180.v:7897$2648_Y + switch $or$ls180.v:7897$2650_Y attribute \src "ls180.v:7897.6-7897.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid @@ -298551,12 +298577,12 @@ module \ls180 attribute \src "ls180.v:7911.6-7911.10" case attribute \src "ls180.v:7912.3-7917.6" - switch $not$ls180.v:7912$2649_Y + switch $not$ls180.v:7912$2651_Y attribute \src "ls180.v:7912.7-7912.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2650_Y + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2652_Y attribute \src "ls180.v:7914.4-7916.7" - switch $eq$ls180.v:7914$2651_Y + switch $eq$ls180.v:7914$2653_Y attribute \src "ls180.v:7914.8-7914.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 @@ -298582,28 +298608,28 @@ module \ls180 end end attribute \src "ls180.v:7928.2-7930.5" - switch $and$ls180.v:7928$2654_Y + switch $and$ls180.v:7928$2656_Y attribute \src "ls180.v:7928.6-7928.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2655_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2657_Y case end attribute \src "ls180.v:7931.2-7933.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7931.6-7931.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2656_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2658_Y case end attribute \src "ls180.v:7934.2-7942.5" - switch $and$ls180.v:7934$2659_Y + switch $and$ls180.v:7934$2661_Y attribute \src "ls180.v:7934.6-7934.191" case 1'1 attribute \src "ls180.v:7935.3-7937.6" - switch $not$ls180.v:7935$2660_Y + switch $not$ls180.v:7935$2662_Y attribute \src "ls180.v:7935.7-7935.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2661_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2663_Y case end attribute \src "ls180.v:7938.6-7938.10" @@ -298612,12 +298638,12 @@ module \ls180 switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7939.7-7939.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2662_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2664_Y case end end attribute \src "ls180.v:7943.2-7949.5" - switch $or$ls180.v:7943$2664_Y + switch $or$ls180.v:7943$2666_Y attribute \src "ls180.v:7943.6-7943.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid @@ -298641,12 +298667,12 @@ module \ls180 attribute \src "ls180.v:7957.6-7957.10" case attribute \src "ls180.v:7958.3-7963.6" - switch $not$ls180.v:7958$2665_Y + switch $not$ls180.v:7958$2667_Y attribute \src "ls180.v:7958.7-7958.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2666_Y + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2668_Y attribute \src "ls180.v:7960.4-7962.7" - switch $eq$ls180.v:7960$2667_Y + switch $eq$ls180.v:7960$2669_Y attribute \src "ls180.v:7960.8-7960.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 @@ -298672,28 +298698,28 @@ module \ls180 end end attribute \src "ls180.v:7974.2-7976.5" - switch $and$ls180.v:7974$2670_Y + switch $and$ls180.v:7974$2672_Y attribute \src "ls180.v:7974.6-7974.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2671_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2673_Y case end attribute \src "ls180.v:7977.2-7979.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7977.6-7977.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2672_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2674_Y case end attribute \src "ls180.v:7980.2-7988.5" - switch $and$ls180.v:7980$2675_Y + switch $and$ls180.v:7980$2677_Y attribute \src "ls180.v:7980.6-7980.191" case 1'1 attribute \src "ls180.v:7981.3-7983.6" - switch $not$ls180.v:7981$2676_Y + switch $not$ls180.v:7981$2678_Y attribute \src "ls180.v:7981.7-7981.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2677_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2679_Y case end attribute \src "ls180.v:7984.6-7984.10" @@ -298702,12 +298728,12 @@ module \ls180 switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:7985.7-7985.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2678_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2680_Y case end end attribute \src "ls180.v:7989.2-7995.5" - switch $or$ls180.v:7989$2680_Y + switch $or$ls180.v:7989$2682_Y attribute \src "ls180.v:7989.6-7989.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid @@ -298731,12 +298757,12 @@ module \ls180 attribute \src "ls180.v:8003.6-8003.10" case attribute \src "ls180.v:8004.3-8009.6" - switch $not$ls180.v:8004$2681_Y + switch $not$ls180.v:8004$2683_Y attribute \src "ls180.v:8004.7-8004.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2682_Y + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2684_Y attribute \src "ls180.v:8006.4-8008.7" - switch $eq$ls180.v:8006$2683_Y + switch $eq$ls180.v:8006$2685_Y attribute \src "ls180.v:8006.8-8006.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 @@ -298762,28 +298788,28 @@ module \ls180 end end attribute \src "ls180.v:8020.2-8022.5" - switch $and$ls180.v:8020$2686_Y + switch $and$ls180.v:8020$2688_Y attribute \src "ls180.v:8020.6-8020.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2687_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2689_Y case end attribute \src "ls180.v:8023.2-8025.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:8023.6-8023.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2688_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2690_Y case end attribute \src "ls180.v:8026.2-8034.5" - switch $and$ls180.v:8026$2691_Y + switch $and$ls180.v:8026$2693_Y attribute \src "ls180.v:8026.6-8026.191" case 1'1 attribute \src "ls180.v:8027.3-8029.6" - switch $not$ls180.v:8027$2692_Y + switch $not$ls180.v:8027$2694_Y attribute \src "ls180.v:8027.7-8027.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2693_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2695_Y case end attribute \src "ls180.v:8030.6-8030.10" @@ -298792,12 +298818,12 @@ module \ls180 switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:8031.7-8031.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2694_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2696_Y case end end attribute \src "ls180.v:8035.2-8041.5" - switch $or$ls180.v:8035$2696_Y + switch $or$ls180.v:8035$2698_Y attribute \src "ls180.v:8035.6-8035.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid @@ -298821,12 +298847,12 @@ module \ls180 attribute \src "ls180.v:8049.6-8049.10" case attribute \src "ls180.v:8050.3-8055.6" - switch $not$ls180.v:8050$2697_Y + switch $not$ls180.v:8050$2699_Y attribute \src "ls180.v:8050.7-8050.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2698_Y + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2700_Y attribute \src "ls180.v:8052.4-8054.7" - switch $eq$ls180.v:8052$2699_Y + switch $eq$ls180.v:8052$2701_Y attribute \src "ls180.v:8052.8-8052.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 @@ -298836,32 +298862,32 @@ module \ls180 end end attribute \src "ls180.v:8058.2-8064.5" - switch $not$ls180.v:8058$2700_Y + switch $not$ls180.v:8058$2702_Y attribute \src "ls180.v:8058.6-8058.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 attribute \src "ls180.v:8060.6-8060.10" case attribute \src "ls180.v:8061.3-8063.6" - switch $not$ls180.v:8061$2701_Y + switch $not$ls180.v:8061$2703_Y attribute \src "ls180.v:8061.7-8061.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2702_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2704_Y case end end attribute \src "ls180.v:8065.2-8071.5" - switch $not$ls180.v:8065$2703_Y + switch $not$ls180.v:8065$2705_Y attribute \src "ls180.v:8065.6-8065.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 attribute \src "ls180.v:8067.6-8067.10" case attribute \src "ls180.v:8068.3-8070.6" - switch $not$ls180.v:8068$2704_Y + switch $not$ls180.v:8068$2706_Y attribute \src "ls180.v:8068.7-8068.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2705_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2707_Y case end end @@ -299100,12 +299126,12 @@ module \ls180 attribute \src "ls180.v:8199.6-8199.10" case attribute \src "ls180.v:8200.3-8205.6" - switch $not$ls180.v:8200$2709_Y + switch $not$ls180.v:8200$2711_Y attribute \src "ls180.v:8200.7-8200.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2710_Y + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2712_Y attribute \src "ls180.v:8202.4-8204.7" - switch $eq$ls180.v:8202$2711_Y + switch $eq$ls180.v:8202$2713_Y attribute \src "ls180.v:8202.8-8202.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 @@ -299128,12 +299154,12 @@ module \ls180 attribute \src "ls180.v:8214.6-8214.10" case attribute \src "ls180.v:8215.3-8220.6" - switch $not$ls180.v:8215$2712_Y + switch $not$ls180.v:8215$2714_Y attribute \src "ls180.v:8215.7-8215.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2713_Y + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2715_Y attribute \src "ls180.v:8217.4-8219.7" - switch $eq$ls180.v:8217$2714_Y + switch $eq$ls180.v:8217$2716_Y attribute \src "ls180.v:8217.8-8217.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 @@ -299143,7 +299169,7 @@ module \ls180 end end attribute \src "ls180.v:8228.2-8230.5" - switch $or$ls180.v:8228$2739_Y + switch $or$ls180.v:8228$2741_Y attribute \src "ls180.v:8228.6-8228.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r @@ -299173,14 +299199,14 @@ module \ls180 attribute \src "ls180.v:8242.6-8242.10" case attribute \src "ls180.v:8243.3-8245.6" - switch $and$ls180.v:8243$2740_Y + switch $and$ls180.v:8243$2742_Y attribute \src "ls180.v:8243.7-8243.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end attribute \src "ls180.v:8246.3-8248.6" - switch $and$ls180.v:8246$2741_Y + switch $and$ls180.v:8246$2743_Y attribute \src "ls180.v:8246.7-8246.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 @@ -299188,7 +299214,7 @@ module \ls180 end end attribute \src "ls180.v:8251.2-8272.5" - switch $and$ls180.v:8251$2745_Y + switch $and$ls180.v:8251$2747_Y attribute \src "ls180.v:8251.6-8251.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data @@ -299198,19 +299224,19 @@ module \ls180 attribute \src "ls180.v:8256.6-8256.10" case attribute \src "ls180.v:8257.3-8271.6" - switch $and$ls180.v:8257$2746_Y + switch $and$ls180.v:8257$2748_Y attribute \src "ls180.v:8257.7-8257.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2747_Y + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2749_Y attribute \src "ls180.v:8259.4-8270.7" - switch $eq$ls180.v:8259$2748_Y + switch $eq$ls180.v:8259$2750_Y attribute \src "ls180.v:8259.8-8259.43" case 1'1 assign $0\uart_tx[0:0] 1'1 attribute \src "ls180.v:8261.8-8261.12" case attribute \src "ls180.v:8262.5-8269.8" - switch $eq$ls180.v:8262$2749_Y + switch $eq$ls180.v:8262$2751_Y attribute \src "ls180.v:8262.9-8262.44" case 1'1 assign $0\uart_tx[0:0] 1'1 @@ -299229,17 +299255,17 @@ module \ls180 switch \main_uart_phy_tx_busy attribute \src "ls180.v:8273.6-8273.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2750_Y + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2752_Y attribute \src "ls180.v:8275.6-8275.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end attribute \src "ls180.v:8280.2-8304.5" - switch $not$ls180.v:8280$2751_Y + switch $not$ls180.v:8280$2753_Y attribute \src "ls180.v:8280.6-8280.30" case 1'1 attribute \src "ls180.v:8281.3-8284.6" - switch $and$ls180.v:8281$2753_Y + switch $and$ls180.v:8281$2755_Y attribute \src "ls180.v:8281.7-8281.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 @@ -299252,9 +299278,9 @@ module \ls180 switch \main_uart_phy_uart_clk_rxen attribute \src "ls180.v:8286.7-8286.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2754_Y + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2756_Y attribute \src "ls180.v:8288.4-8302.7" - switch $eq$ls180.v:8288$2755_Y + switch $eq$ls180.v:8288$2757_Y attribute \src "ls180.v:8288.8-8288.43" case 1'1 attribute \src "ls180.v:8289.5-8291.8" @@ -299267,7 +299293,7 @@ module \ls180 attribute \src "ls180.v:8292.8-8292.12" case attribute \src "ls180.v:8293.5-8301.8" - switch $eq$ls180.v:8293$2756_Y + switch $eq$ls180.v:8293$2758_Y attribute \src "ls180.v:8293.9-8293.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 @@ -299291,7 +299317,7 @@ module \ls180 switch \main_uart_phy_rx_busy attribute \src "ls180.v:8305.6-8305.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2757_Y + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2759_Y attribute \src "ls180.v:8307.6-8307.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 @@ -299304,7 +299330,7 @@ module \ls180 case end attribute \src "ls180.v:8314.2-8316.5" - switch $and$ls180.v:8314$2759_Y + switch $and$ls180.v:8314$2761_Y attribute \src "ls180.v:8314.6-8314.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 @@ -299318,7 +299344,7 @@ module \ls180 case end attribute \src "ls180.v:8321.2-8323.5" - switch $and$ls180.v:8321$2761_Y + switch $and$ls180.v:8321$2763_Y attribute \src "ls180.v:8321.6-8321.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 @@ -299340,28 +299366,28 @@ module \ls180 end end attribute \src "ls180.v:8331.2-8333.5" - switch $and$ls180.v:8331$2764_Y + switch $and$ls180.v:8331$2766_Y attribute \src "ls180.v:8331.6-8331.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2765_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2767_Y case end attribute \src "ls180.v:8334.2-8336.5" switch \main_uart_tx_fifo_do_read attribute \src "ls180.v:8334.6-8334.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2766_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2768_Y case end attribute \src "ls180.v:8337.2-8345.5" - switch $and$ls180.v:8337$2769_Y + switch $and$ls180.v:8337$2771_Y attribute \src "ls180.v:8337.6-8337.108" case 1'1 attribute \src "ls180.v:8338.3-8340.6" - switch $not$ls180.v:8338$2770_Y + switch $not$ls180.v:8338$2772_Y attribute \src "ls180.v:8338.7-8338.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2771_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2773_Y case end attribute \src "ls180.v:8341.6-8341.10" @@ -299370,7 +299396,7 @@ module \ls180 switch \main_uart_tx_fifo_do_read attribute \src "ls180.v:8342.7-8342.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2772_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2774_Y case end end @@ -299390,28 +299416,28 @@ module \ls180 end end attribute \src "ls180.v:8353.2-8355.5" - switch $and$ls180.v:8353$2775_Y + switch $and$ls180.v:8353$2777_Y attribute \src "ls180.v:8353.6-8353.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2776_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2778_Y case end attribute \src "ls180.v:8356.2-8358.5" switch \main_uart_rx_fifo_do_read attribute \src "ls180.v:8356.6-8356.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2777_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2779_Y case end attribute \src "ls180.v:8359.2-8367.5" - switch $and$ls180.v:8359$2780_Y + switch $and$ls180.v:8359$2782_Y attribute \src "ls180.v:8359.6-8359.108" case 1'1 attribute \src "ls180.v:8360.3-8362.6" - switch $not$ls180.v:8360$2781_Y + switch $not$ls180.v:8360$2783_Y attribute \src "ls180.v:8360.7-8360.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2782_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2784_Y case end attribute \src "ls180.v:8363.6-8363.10" @@ -299420,7 +299446,7 @@ module \ls180 switch \main_uart_rx_fifo_do_read attribute \src "ls180.v:8364.7-8364.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2783_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2785_Y case end end @@ -299470,7 +299496,7 @@ module \ls180 switch \main_spimaster32_clk_fall attribute \src "ls180.v:8396.7-8396.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2788_Y + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2790_Y attribute \src "ls180.v:8397.4-8399.7" switch \main_spimaster26_cs_enable attribute \src "ls180.v:8397.8-8397.34" @@ -299538,7 +299564,7 @@ module \ls180 switch \main_spisdcard_clk_fall attribute \src "ls180.v:8431.7-8431.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2793_Y + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2795_Y attribute \src "ls180.v:8432.4-8434.7" switch \main_spisdcard_cs_enable attribute \src "ls180.v:8432.8-8432.32" @@ -299582,9 +299608,9 @@ module \ls180 switch \main_pwm0_enable attribute \src "ls180.v:8452.6-8452.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2794_Y + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2796_Y attribute \src "ls180.v:8454.3-8458.6" - switch $lt$ls180.v:8454$2795_Y + switch $lt$ls180.v:8454$2797_Y attribute \src "ls180.v:8454.7-8454.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 @@ -299593,7 +299619,7 @@ module \ls180 assign $0\pwm[1:0] [0] 1'0 end attribute \src "ls180.v:8459.3-8461.6" - switch $ge$ls180.v:8459$2797_Y + switch $ge$ls180.v:8459$2799_Y attribute \src "ls180.v:8459.7-8459.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 @@ -299608,9 +299634,9 @@ module \ls180 switch \main_pwm1_enable attribute \src "ls180.v:8466.6-8466.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2798_Y + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2800_Y attribute \src "ls180.v:8468.3-8472.6" - switch $lt$ls180.v:8468$2799_Y + switch $lt$ls180.v:8468$2801_Y attribute \src "ls180.v:8468.7-8468.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 @@ -299619,7 +299645,7 @@ module \ls180 assign $0\pwm[1:0] [1] 1'0 end attribute \src "ls180.v:8473.3-8475.6" - switch $ge$ls180.v:8473$2801_Y + switch $ge$ls180.v:8473$2803_Y attribute \src "ls180.v:8473.7-8473.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 @@ -299631,10 +299657,10 @@ module \ls180 assign $0\pwm[1:0] [1] 1'0 end attribute \src "ls180.v:8480.2-8482.5" - switch $not$ls180.v:8480$2802_Y + switch $not$ls180.v:8480$2804_Y attribute \src "ls180.v:8480.6-8480.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2803_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2805_Y case end attribute \src "ls180.v:8486.2-8488.5" @@ -299655,7 +299681,7 @@ module \ls180 switch \main_sdphy_cmdr_cmdr_pads_in_valid attribute \src "ls180.v:8493.6-8493.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2804_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2806_Y case end attribute \src "ls180.v:8496.2-8498.5" @@ -299670,23 +299696,23 @@ module \ls180 attribute \src "ls180.v:8499.6-8499.46" case 1'1 attribute \src "ls180.v:8500.3-8505.6" - switch $or$ls180.v:8500$2806_Y + switch $or$ls180.v:8500$2808_Y attribute \src "ls180.v:8500.7-8500.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8503.7-8503.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2807_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2809_Y end case end attribute \src "ls180.v:8507.2-8520.5" - switch $and$ls180.v:8507$2808_Y + switch $and$ls180.v:8507$2810_Y attribute \src "ls180.v:8507.6-8507.97" case 1'1 attribute \src "ls180.v:8508.3-8514.6" - switch $and$ls180.v:8508$2809_Y + switch $and$ls180.v:8508$2811_Y attribute \src "ls180.v:8508.7-8508.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first @@ -299699,11 +299725,11 @@ module \ls180 attribute \src "ls180.v:8515.6-8515.10" case attribute \src "ls180.v:8516.3-8519.6" - switch $and$ls180.v:8516$2810_Y + switch $and$ls180.v:8516$2812_Y attribute \src "ls180.v:8516.7-8516.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2811_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2812_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2813_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2814_Y case end end @@ -299745,11 +299771,11 @@ module \ls180 switch \main_sdphy_cmdr_cmdr_converter_load_part attribute \src "ls180.v:8549.6-8549.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2813_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2815_Y case end attribute \src "ls180.v:8552.2-8557.5" - switch $or$ls180.v:8552$2815_Y + switch $or$ls180.v:8552$2817_Y attribute \src "ls180.v:8552.6-8552.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid @@ -299793,7 +299819,7 @@ module \ls180 switch \main_sdphy_dataw_crcr_pads_in_valid attribute \src "ls180.v:8574.6-8574.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2816_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2818_Y case end attribute \src "ls180.v:8577.2-8579.5" @@ -299808,23 +299834,23 @@ module \ls180 attribute \src "ls180.v:8580.6-8580.47" case 1'1 attribute \src "ls180.v:8581.3-8586.6" - switch $or$ls180.v:8581$2818_Y + switch $or$ls180.v:8581$2820_Y attribute \src "ls180.v:8581.7-8581.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8584.7-8584.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2819_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2821_Y end case end attribute \src "ls180.v:8588.2-8601.5" - switch $and$ls180.v:8588$2820_Y + switch $and$ls180.v:8588$2822_Y attribute \src "ls180.v:8588.6-8588.99" case 1'1 attribute \src "ls180.v:8589.3-8595.6" - switch $and$ls180.v:8589$2821_Y + switch $and$ls180.v:8589$2823_Y attribute \src "ls180.v:8589.7-8589.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first @@ -299837,11 +299863,11 @@ module \ls180 attribute \src "ls180.v:8596.6-8596.10" case attribute \src "ls180.v:8597.3-8600.6" - switch $and$ls180.v:8597$2822_Y + switch $and$ls180.v:8597$2824_Y attribute \src "ls180.v:8597.7-8597.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2823_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2824_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2825_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2826_Y case end end @@ -299883,11 +299909,11 @@ module \ls180 switch \main_sdphy_dataw_crcr_converter_load_part attribute \src "ls180.v:8630.6-8630.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2825_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2827_Y case end attribute \src "ls180.v:8633.2-8638.5" - switch $or$ls180.v:8633$2827_Y + switch $or$ls180.v:8633$2829_Y attribute \src "ls180.v:8633.6-8633.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid @@ -299924,7 +299950,7 @@ module \ls180 switch \main_sdphy_datar_datar_pads_in_valid attribute \src "ls180.v:8653.6-8653.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2828_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2830_Y case end attribute \src "ls180.v:8656.2-8658.5" @@ -299939,23 +299965,23 @@ module \ls180 attribute \src "ls180.v:8659.6-8659.48" case 1'1 attribute \src "ls180.v:8660.3-8665.6" - switch $or$ls180.v:8660$2830_Y + switch $or$ls180.v:8660$2832_Y attribute \src "ls180.v:8660.7-8660.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8663.7-8663.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2831_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2833_Y end case end attribute \src "ls180.v:8667.2-8680.5" - switch $and$ls180.v:8667$2832_Y + switch $and$ls180.v:8667$2834_Y attribute \src "ls180.v:8667.6-8667.101" case 1'1 attribute \src "ls180.v:8668.3-8674.6" - switch $and$ls180.v:8668$2833_Y + switch $and$ls180.v:8668$2835_Y attribute \src "ls180.v:8668.7-8668.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first @@ -299968,11 +299994,11 @@ module \ls180 attribute \src "ls180.v:8675.6-8675.10" case attribute \src "ls180.v:8676.3-8679.6" - switch $and$ls180.v:8676$2834_Y + switch $and$ls180.v:8676$2836_Y attribute \src "ls180.v:8676.7-8676.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2835_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2836_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2837_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2838_Y case end end @@ -299996,11 +300022,11 @@ module \ls180 switch \main_sdphy_datar_datar_converter_load_part attribute \src "ls180.v:8691.6-8691.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2837_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2839_Y case end attribute \src "ls180.v:8694.2-8699.5" - switch $or$ls180.v:8694$2839_Y + switch $or$ls180.v:8694$2841_Y attribute \src "ls180.v:8694.6-8694.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid @@ -300151,35 +300177,35 @@ module \ls180 case end attribute \src "ls180.v:8767.2-8769.5" - switch $and$ls180.v:8767$2840_Y + switch $and$ls180.v:8767$2842_Y attribute \src "ls180.v:8767.6-8767.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2841_Y + switch $and$ls180.v:8770$2843_Y attribute \src "ls180.v:8770.6-8770.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end attribute \src "ls180.v:8773.2-8775.5" - switch $and$ls180.v:8773$2842_Y + switch $and$ls180.v:8773$2844_Y attribute \src "ls180.v:8773.6-8773.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end attribute \src "ls180.v:8776.2-8778.5" - switch $and$ls180.v:8776$2843_Y + switch $and$ls180.v:8776$2845_Y attribute \src "ls180.v:8776.6-8776.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end attribute \src "ls180.v:8779.2-8783.5" - switch $and$ls180.v:8779$2844_Y + switch $and$ls180.v:8779$2846_Y attribute \src "ls180.v:8779.6-8779.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } @@ -300188,7 +300214,7 @@ module \ls180 case end attribute \src "ls180.v:8784.2-8788.5" - switch $and$ls180.v:8784$2845_Y + switch $and$ls180.v:8784$2847_Y attribute \src "ls180.v:8784.6-8784.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } @@ -300197,7 +300223,7 @@ module \ls180 case end attribute \src "ls180.v:8789.2-8793.5" - switch $and$ls180.v:8789$2846_Y + switch $and$ls180.v:8789$2848_Y attribute \src "ls180.v:8789.6-8789.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } @@ -300206,7 +300232,7 @@ module \ls180 case end attribute \src "ls180.v:8794.2-8798.5" - switch $and$ls180.v:8794$2847_Y + switch $and$ls180.v:8794$2849_Y attribute \src "ls180.v:8794.6-8794.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } @@ -300215,7 +300241,7 @@ module \ls180 case end attribute \src "ls180.v:8799.2-8807.5" - switch $and$ls180.v:8799$2848_Y + switch $and$ls180.v:8799$2850_Y attribute \src "ls180.v:8799.6-8799.83" case 1'1 attribute \src "ls180.v:8800.3-8806.6" @@ -300226,10 +300252,10 @@ module \ls180 attribute \src "ls180.v:8802.7-8802.11" case attribute \src "ls180.v:8803.4-8805.7" - switch $ne$ls180.v:8803$2849_Y + switch $ne$ls180.v:8803$2851_Y attribute \src "ls180.v:8803.8-8803.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2850_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2852_Y case end end @@ -300359,28 +300385,28 @@ module \ls180 case end attribute \src "ls180.v:8864.2-8866.5" - switch $and$ls180.v:8864$2853_Y + switch $and$ls180.v:8864$2855_Y attribute \src "ls180.v:8864.6-8864.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2854_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2856_Y case end attribute \src "ls180.v:8867.2-8869.5" switch \main_sdblock2mem_fifo_do_read attribute \src "ls180.v:8867.6-8867.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2855_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2857_Y case end attribute \src "ls180.v:8870.2-8878.5" - switch $and$ls180.v:8870$2858_Y + switch $and$ls180.v:8870$2860_Y attribute \src "ls180.v:8870.6-8870.120" case 1'1 attribute \src "ls180.v:8871.3-8873.6" - switch $not$ls180.v:8871$2859_Y + switch $not$ls180.v:8871$2861_Y attribute \src "ls180.v:8871.7-8871.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2860_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2862_Y case end attribute \src "ls180.v:8874.6-8874.10" @@ -300389,7 +300415,7 @@ module \ls180 switch \main_sdblock2mem_fifo_do_read attribute \src "ls180.v:8875.7-8875.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2861_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2863_Y case end end @@ -300405,23 +300431,23 @@ module \ls180 attribute \src "ls180.v:8882.6-8882.42" case 1'1 attribute \src "ls180.v:8883.3-8888.6" - switch $or$ls180.v:8883$2863_Y + switch $or$ls180.v:8883$2865_Y attribute \src "ls180.v:8883.7-8883.90" case 1'1 assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 attribute \src "ls180.v:8886.7-8886.11" case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2864_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2866_Y end case end attribute \src "ls180.v:8890.2-8903.5" - switch $and$ls180.v:8890$2865_Y + switch $and$ls180.v:8890$2867_Y attribute \src "ls180.v:8890.6-8890.89" case 1'1 attribute \src "ls180.v:8891.3-8897.6" - switch $and$ls180.v:8891$2866_Y + switch $and$ls180.v:8891$2868_Y attribute \src "ls180.v:8891.7-8891.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first @@ -300434,11 +300460,11 @@ module \ls180 attribute \src "ls180.v:8898.6-8898.10" case attribute \src "ls180.v:8899.3-8902.6" - switch $and$ls180.v:8899$2867_Y + switch $and$ls180.v:8899$2869_Y attribute \src "ls180.v:8899.7-8899.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2868_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2869_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2870_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2871_Y case end end @@ -300480,7 +300506,7 @@ module \ls180 switch \main_sdblock2mem_converter_load_part attribute \src "ls180.v:8932.6-8932.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2870_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2872_Y case end attribute \src "ls180.v:8936.2-8938.5" @@ -300521,7 +300547,7 @@ module \ls180 case end attribute \src "ls180.v:8955.2-8961.5" - switch $and$ls180.v:8955$2871_Y + switch $and$ls180.v:8955$2873_Y attribute \src "ls180.v:8955.6-8955.89" case 1'1 attribute \src "ls180.v:8956.3-8960.6" @@ -300531,33 +300557,33 @@ module \ls180 assign $0\main_sdmem2block_converter_mux[2:0] 3'000 attribute \src "ls180.v:8958.7-8958.11" case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2872_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2874_Y end case end attribute \src "ls180.v:8962.2-8964.5" - switch $and$ls180.v:8962$2875_Y + switch $and$ls180.v:8962$2877_Y attribute \src "ls180.v:8962.6-8962.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2876_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2878_Y case end attribute \src "ls180.v:8965.2-8967.5" switch \main_sdmem2block_fifo_do_read attribute \src "ls180.v:8965.6-8965.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2877_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2879_Y case end attribute \src "ls180.v:8968.2-8976.5" - switch $and$ls180.v:8968$2880_Y + switch $and$ls180.v:8968$2882_Y attribute \src "ls180.v:8968.6-8968.120" case 1'1 attribute \src "ls180.v:8969.3-8971.6" - switch $not$ls180.v:8969$2881_Y + switch $not$ls180.v:8969$2883_Y attribute \src "ls180.v:8969.7-8969.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2882_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2884_Y case end attribute \src "ls180.v:8972.6-8972.10" @@ -300566,7 +300592,7 @@ module \ls180 switch \main_sdmem2block_fifo_do_read attribute \src "ls180.v:8973.7-8973.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2883_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2885_Y case end end @@ -300596,7 +300622,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'000 attribute \src "ls180.v:8989.4-9005.7" - switch $not$ls180.v:8989$2884_Y + switch $not$ls180.v:8989$2886_Y attribute \src "ls180.v:8989.8-8989.29" case 1'1 attribute \src "ls180.v:8990.5-9004.8" @@ -300635,7 +300661,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'001 attribute \src "ls180.v:9008.4-9024.7" - switch $not$ls180.v:9008$2885_Y + switch $not$ls180.v:9008$2887_Y attribute \src "ls180.v:9008.8-9008.29" case 1'1 attribute \src "ls180.v:9009.5-9023.8" @@ -300674,7 +300700,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 attribute \src "ls180.v:9027.4-9043.7" - switch $not$ls180.v:9027$2886_Y + switch $not$ls180.v:9027$2888_Y attribute \src "ls180.v:9027.8-9027.29" case 1'1 attribute \src "ls180.v:9028.5-9042.8" @@ -300713,7 +300739,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:9046.4-9062.7" - switch $not$ls180.v:9046$2887_Y + switch $not$ls180.v:9046$2889_Y attribute \src "ls180.v:9046.8-9046.29" case 1'1 attribute \src "ls180.v:9047.5-9061.8" @@ -300752,7 +300778,7 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 attribute \src "ls180.v:9065.4-9081.7" - switch $not$ls180.v:9065$2888_Y + switch $not$ls180.v:9065$2890_Y attribute \src "ls180.v:9065.8-9065.29" case 1'1 attribute \src "ls180.v:9066.5-9080.8" @@ -300795,10 +300821,10 @@ module \ls180 attribute \src "ls180.v:9085.6-9085.18" case 1'1 attribute \src "ls180.v:9086.3-9088.6" - switch $not$ls180.v:9086$2889_Y + switch $not$ls180.v:9086$2891_Y attribute \src "ls180.v:9086.7-9086.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:9087$2890_Y + assign $0\builder_count[19:0] $sub$ls180.v:9087$2892_Y case end attribute \src "ls180.v:9089.6-9089.10" @@ -302196,14 +302222,14 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 assign $0\pwm[1:0] 2'00 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -302491,14 +302517,14 @@ module \ls180 case end sync posedge \sys_clk_1 - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] update \pwm $0\pwm[1:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] @@ -302909,7 +302935,7 @@ module \ls180 update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end attribute \src "ls180.v:784.11-784.68" - process $proc$ls180.v:784$3379 + process $proc$ls180.v:784$3381 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always @@ -302917,7 +302943,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:785.5-785.64" - process $proc$ls180.v:785$3380 + process $proc$ls180.v:785$3382 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 sync always @@ -302925,7 +302951,7 @@ module \ls180 sync init end attribute \src "ls180.v:786.11-786.70" - process $proc$ls180.v:786$3381 + process $proc$ls180.v:786$3383 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always @@ -302933,7 +302959,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:787.11-787.70" - process $proc$ls180.v:787$3382 + process $proc$ls180.v:787$3384 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always @@ -302941,7 +302967,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:788.11-788.73" - process $proc$ls180.v:788$3383 + process $proc$ls180.v:788$3385 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -302949,7 +302975,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:809.5-809.59" - process $proc$ls180.v:809$3384 + process $proc$ls180.v:809$3386 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always @@ -302957,7 +302983,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:811.5-811.59" - process $proc$ls180.v:811$3385 + process $proc$ls180.v:811$3387 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always @@ -302965,7 +302991,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:812.5-812.58" - process $proc$ls180.v:812$3386 + process $proc$ls180.v:812$3388 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always @@ -302973,7 +302999,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:813.5-813.64" - process $proc$ls180.v:813$3387 + process $proc$ls180.v:813$3389 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always @@ -302981,7 +303007,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:814.12-814.74" - process $proc$ls180.v:814$3388 + process $proc$ls180.v:814$3390 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always @@ -302989,7 +303015,7 @@ module \ls180 update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:815.12-815.47" - process $proc$ls180.v:815$3389 + process $proc$ls180.v:815$3391 assign { } { } assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always @@ -302997,7 +303023,7 @@ module \ls180 update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end attribute \src "ls180.v:816.5-816.46" - process $proc$ls180.v:816$3390 + process $proc$ls180.v:816$3392 assign { } { } assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always @@ -303005,7 +303031,7 @@ module \ls180 update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end attribute \src "ls180.v:818.5-818.44" - process $proc$ls180.v:818$3391 + process $proc$ls180.v:818$3393 assign { } { } assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always @@ -303013,7 +303039,7 @@ module \ls180 update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end attribute \src "ls180.v:819.5-819.45" - process $proc$ls180.v:819$3392 + process $proc$ls180.v:819$3394 assign { } { } assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 sync always @@ -303021,7 +303047,7 @@ module \ls180 update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end attribute \src "ls180.v:820.5-820.54" - process $proc$ls180.v:820$3393 + process $proc$ls180.v:820$3395 assign { } { } assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always @@ -303029,7 +303055,7 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:822.32-822.76" - process $proc$ls180.v:822$3394 + process $proc$ls180.v:822$3396 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always @@ -303037,7 +303063,7 @@ module \ls180 update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end attribute \src "ls180.v:823.11-823.55" - process $proc$ls180.v:823$3395 + process $proc$ls180.v:823$3397 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always @@ -303045,7 +303071,7 @@ module \ls180 update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end attribute \src "ls180.v:825.32-825.75" - process $proc$ls180.v:825$3396 + process $proc$ls180.v:825$3398 assign { } { } assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always @@ -303053,7 +303079,7 @@ module \ls180 sync init end attribute \src "ls180.v:827.32-827.76" - process $proc$ls180.v:827$3397 + process $proc$ls180.v:827$3399 assign { } { } assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always @@ -303061,7 +303087,7 @@ module \ls180 sync init end attribute \src "ls180.v:830.5-830.44" - process $proc$ls180.v:830$3398 + process $proc$ls180.v:830$3400 assign { } { } assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always @@ -303069,7 +303095,7 @@ module \ls180 sync init end attribute \src "ls180.v:831.5-831.45" - process $proc$ls180.v:831$3399 + process $proc$ls180.v:831$3401 assign { } { } assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always @@ -303077,7 +303103,7 @@ module \ls180 sync init end attribute \src "ls180.v:832.5-832.43" - process $proc$ls180.v:832$3400 + process $proc$ls180.v:832$3402 assign { } { } assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always @@ -303085,7 +303111,7 @@ module \ls180 sync init end attribute \src "ls180.v:833.5-833.48" - process $proc$ls180.v:833$3401 + process $proc$ls180.v:833$3403 assign { } { } assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always @@ -303093,7 +303119,7 @@ module \ls180 sync init end attribute \src "ls180.v:835.5-835.43" - process $proc$ls180.v:835$3402 + process $proc$ls180.v:835$3404 assign { } { } assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always @@ -303101,7 +303127,7 @@ module \ls180 sync init end attribute \src "ls180.v:838.5-838.49" - process $proc$ls180.v:838$3403 + process $proc$ls180.v:838$3405 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always @@ -303109,7 +303135,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end attribute \src "ls180.v:839.5-839.49" - process $proc$ls180.v:839$3404 + process $proc$ls180.v:839$3406 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always @@ -303117,7 +303143,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end attribute \src "ls180.v:840.5-840.48" - process $proc$ls180.v:840$3405 + process $proc$ls180.v:840$3407 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always @@ -303125,7 +303151,7 @@ module \ls180 update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end attribute \src "ls180.v:844.11-844.46" - process $proc$ls180.v:844$3406 + process $proc$ls180.v:844$3408 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always @@ -303133,7 +303159,7 @@ module \ls180 update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end attribute \src "ls180.v:846.11-846.45" - process $proc$ls180.v:846$3407 + process $proc$ls180.v:846$3409 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always @@ -303141,7 +303167,7 @@ module \ls180 update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end attribute \src "ls180.v:848.5-848.44" - process $proc$ls180.v:848$3408 + process $proc$ls180.v:848$3410 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always @@ -303149,7 +303175,7 @@ module \ls180 update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end attribute \src "ls180.v:849.5-849.45" - process $proc$ls180.v:849$3409 + process $proc$ls180.v:849$3411 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always @@ -303157,7 +303183,7 @@ module \ls180 update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end attribute \src "ls180.v:85.11-85.52" - process $proc$ls180.v:85$3134 + process $proc$ls180.v:85$3136 assign { } { } assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 sync always @@ -303165,7 +303191,7 @@ module \ls180 sync init end attribute \src "ls180.v:851.5-851.48" - process $proc$ls180.v:851$3410 + process $proc$ls180.v:851$3412 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always @@ -303173,7 +303199,7 @@ module \ls180 update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end attribute \src "ls180.v:853.5-853.43" - process $proc$ls180.v:853$3411 + process $proc$ls180.v:853$3413 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always @@ -303181,7 +303207,7 @@ module \ls180 update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end attribute \src "ls180.v:856.5-856.49" - process $proc$ls180.v:856$3412 + process $proc$ls180.v:856$3414 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always @@ -303189,7 +303215,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end attribute \src "ls180.v:857.5-857.49" - process $proc$ls180.v:857$3413 + process $proc$ls180.v:857$3415 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always @@ -303197,7 +303223,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end attribute \src "ls180.v:858.5-858.48" - process $proc$ls180.v:858$3414 + process $proc$ls180.v:858$3416 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always @@ -303205,7 +303231,7 @@ module \ls180 update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end attribute \src "ls180.v:86.11-86.52" - process $proc$ls180.v:86$3135 + process $proc$ls180.v:86$3137 assign { } { } assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 sync always @@ -303213,7 +303239,7 @@ module \ls180 sync init end attribute \src "ls180.v:862.11-862.46" - process $proc$ls180.v:862$3415 + process $proc$ls180.v:862$3417 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always @@ -303221,7 +303247,7 @@ module \ls180 update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end attribute \src "ls180.v:864.11-864.45" - process $proc$ls180.v:864$3416 + process $proc$ls180.v:864$3418 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always @@ -303229,7 +303255,7 @@ module \ls180 update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end attribute \src "ls180.v:866.12-866.36" - process $proc$ls180.v:866$3417 + process $proc$ls180.v:866$3419 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always @@ -303237,7 +303263,7 @@ module \ls180 sync init end attribute \src "ls180.v:867.11-867.35" - process $proc$ls180.v:867$3418 + process $proc$ls180.v:867$3420 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always @@ -303245,7 +303271,7 @@ module \ls180 sync init end attribute \src "ls180.v:868.11-868.40" - process $proc$ls180.v:868$3419 + process $proc$ls180.v:868$3421 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always @@ -303253,7 +303279,7 @@ module \ls180 update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end attribute \src "ls180.v:869.5-869.31" - process $proc$ls180.v:869$3420 + process $proc$ls180.v:869$3422 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always @@ -303261,7 +303287,7 @@ module \ls180 sync init end attribute \src "ls180.v:870.5-870.31" - process $proc$ls180.v:870$3421 + process $proc$ls180.v:870$3423 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always @@ -303269,7 +303295,7 @@ module \ls180 sync init end attribute \src "ls180.v:872.32-872.63" - process $proc$ls180.v:872$3422 + process $proc$ls180.v:872$3424 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always @@ -303277,7 +303303,7 @@ module \ls180 sync init end attribute \src "ls180.v:874.32-874.63" - process $proc$ls180.v:874$3423 + process $proc$ls180.v:874$3425 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always @@ -303285,7 +303311,7 @@ module \ls180 sync init end attribute \src "ls180.v:876.32-876.63" - process $proc$ls180.v:876$3424 + process $proc$ls180.v:876$3426 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always @@ -303293,7 +303319,7 @@ module \ls180 update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end attribute \src "ls180.v:877.5-877.36" - process $proc$ls180.v:877$3425 + process $proc$ls180.v:877$3427 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always @@ -303301,7 +303327,7 @@ module \ls180 update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end attribute \src "ls180.v:879.32-879.63" - process $proc$ls180.v:879$3426 + process $proc$ls180.v:879$3428 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always @@ -303309,7 +303335,7 @@ module \ls180 update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end attribute \src "ls180.v:88.12-88.58" - process $proc$ls180.v:88$3136 + process $proc$ls180.v:88$3138 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303317,7 +303343,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] end attribute \src "ls180.v:880.11-880.42" - process $proc$ls180.v:880$3427 + process $proc$ls180.v:880$3429 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always @@ -303325,7 +303351,7 @@ module \ls180 update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end attribute \src "ls180.v:883.5-883.26" - process $proc$ls180.v:883$3428 + process $proc$ls180.v:883$3430 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always @@ -303333,7 +303359,7 @@ module \ls180 update \main_sdram_en0 $1\main_sdram_en0[0:0] end attribute \src "ls180.v:885.11-885.34" - process $proc$ls180.v:885$3429 + process $proc$ls180.v:885$3431 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always @@ -303341,7 +303367,7 @@ module \ls180 update \main_sdram_time0 $1\main_sdram_time0[4:0] end attribute \src "ls180.v:886.5-886.26" - process $proc$ls180.v:886$3430 + process $proc$ls180.v:886$3432 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always @@ -303349,7 +303375,7 @@ module \ls180 update \main_sdram_en1 $1\main_sdram_en1[0:0] end attribute \src "ls180.v:888.11-888.34" - process $proc$ls180.v:888$3431 + process $proc$ls180.v:888$3433 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always @@ -303357,7 +303383,7 @@ module \ls180 update \main_sdram_time1 $1\main_sdram_time1[3:0] end attribute \src "ls180.v:89.12-89.60" - process $proc$ls180.v:89$3137 + process $proc$ls180.v:89$3139 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 sync always @@ -303365,7 +303391,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end attribute \src "ls180.v:903.12-903.37" - process $proc$ls180.v:903$3432 + process $proc$ls180.v:903$3434 assign { } { } assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303373,7 +303399,7 @@ module \ls180 update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] end attribute \src "ls180.v:904.12-904.39" - process $proc$ls180.v:904$3433 + process $proc$ls180.v:904$3435 assign { } { } assign $1\main_wb_sdram_dat_w[31:0] 0 sync always @@ -303381,7 +303407,7 @@ module \ls180 update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] end attribute \src "ls180.v:906.11-906.35" - process $proc$ls180.v:906$3434 + process $proc$ls180.v:906$3436 assign { } { } assign $1\main_wb_sdram_sel[3:0] 4'0000 sync always @@ -303389,7 +303415,7 @@ module \ls180 update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] end attribute \src "ls180.v:907.5-907.29" - process $proc$ls180.v:907$3435 + process $proc$ls180.v:907$3437 assign { } { } assign $1\main_wb_sdram_cyc[0:0] 1'0 sync always @@ -303397,7 +303423,7 @@ module \ls180 update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] end attribute \src "ls180.v:908.5-908.29" - process $proc$ls180.v:908$3436 + process $proc$ls180.v:908$3438 assign { } { } assign $1\main_wb_sdram_stb[0:0] 1'0 sync always @@ -303405,7 +303431,7 @@ module \ls180 update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] end attribute \src "ls180.v:909.5-909.29" - process $proc$ls180.v:909$3437 + process $proc$ls180.v:909$3439 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always @@ -303413,7 +303439,7 @@ module \ls180 update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end attribute \src "ls180.v:91.11-91.56" - process $proc$ls180.v:91$3138 + process $proc$ls180.v:91$3140 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 sync always @@ -303421,7 +303447,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] end attribute \src "ls180.v:910.5-910.28" - process $proc$ls180.v:910$3438 + process $proc$ls180.v:910$3440 assign { } { } assign $1\main_wb_sdram_we[0:0] 1'0 sync always @@ -303429,7 +303455,7 @@ module \ls180 update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] end attribute \src "ls180.v:917.5-917.54" - process $proc$ls180.v:917$3439 + process $proc$ls180.v:917$3441 assign { } { } assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 sync always @@ -303437,7 +303463,7 @@ module \ls180 update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] end attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$3139 + process $proc$ls180.v:92$3141 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 sync always @@ -303445,7 +303471,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] end attribute \src "ls180.v:921.5-921.54" - process $proc$ls180.v:921$3440 + process $proc$ls180.v:921$3442 assign { } { } assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 sync always @@ -303453,7 +303479,7 @@ module \ls180 sync init end attribute \src "ls180.v:922.5-922.35" - process $proc$ls180.v:922$3441 + process $proc$ls180.v:922$3443 assign { } { } assign $1\main_socbushandler_skip[0:0] 1'0 sync always @@ -303461,7 +303487,7 @@ module \ls180 update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] end attribute \src "ls180.v:923.5-923.38" - process $proc$ls180.v:923$3442 + process $proc$ls180.v:923$3444 assign { } { } assign $1\main_socbushandler_counter[0:0] 1'0 sync always @@ -303469,7 +303495,7 @@ module \ls180 update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] end attribute \src "ls180.v:925.12-925.44" - process $proc$ls180.v:925$3443 + process $proc$ls180.v:925$3445 assign { } { } assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always @@ -303477,7 +303503,7 @@ module \ls180 update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] end attribute \src "ls180.v:926.12-926.40" - process $proc$ls180.v:926$3444 + process $proc$ls180.v:926$3446 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303485,7 +303511,7 @@ module \ls180 update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end attribute \src "ls180.v:927.12-927.42" - process $proc$ls180.v:927$3445 + process $proc$ls180.v:927$3447 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always @@ -303493,7 +303519,7 @@ module \ls180 update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end attribute \src "ls180.v:929.11-929.38" - process $proc$ls180.v:929$3446 + process $proc$ls180.v:929$3448 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always @@ -303501,7 +303527,7 @@ module \ls180 update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$3140 + process $proc$ls180.v:93$3142 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 sync always @@ -303509,7 +303535,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] end attribute \src "ls180.v:930.5-930.32" - process $proc$ls180.v:930$3447 + process $proc$ls180.v:930$3449 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always @@ -303517,7 +303543,7 @@ module \ls180 update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end attribute \src "ls180.v:931.5-931.32" - process $proc$ls180.v:931$3448 + process $proc$ls180.v:931$3450 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always @@ -303525,7 +303551,7 @@ module \ls180 update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end attribute \src "ls180.v:933.5-933.31" - process $proc$ls180.v:933$3449 + process $proc$ls180.v:933$3451 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always @@ -303533,7 +303559,7 @@ module \ls180 update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end attribute \src "ls180.v:934.5-934.31" - process $proc$ls180.v:934$3450 + process $proc$ls180.v:934$3452 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always @@ -303541,7 +303567,7 @@ module \ls180 update \main_converter_skip $1\main_converter_skip[0:0] end attribute \src "ls180.v:935.5-935.34" - process $proc$ls180.v:935$3451 + process $proc$ls180.v:935$3453 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always @@ -303549,7 +303575,7 @@ module \ls180 update \main_converter_counter $1\main_converter_counter[0:0] end attribute \src "ls180.v:937.12-937.40" - process $proc$ls180.v:937$3452 + process $proc$ls180.v:937$3454 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always @@ -303557,7 +303583,7 @@ module \ls180 update \main_converter_dat_r $1\main_converter_dat_r[31:0] end attribute \src "ls180.v:938.5-938.29" - process $proc$ls180.v:938$3453 + process $proc$ls180.v:938$3455 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always @@ -303565,7 +303591,7 @@ module \ls180 update \main_cmd_consumed $1\main_cmd_consumed[0:0] end attribute \src "ls180.v:939.5-939.31" - process $proc$ls180.v:939$3454 + process $proc$ls180.v:939$3456 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always @@ -303573,7 +303599,7 @@ module \ls180 update \main_wdata_consumed $1\main_wdata_consumed[0:0] end attribute \src "ls180.v:943.12-943.47" - process $proc$ls180.v:943$3455 + process $proc$ls180.v:943$3457 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always @@ -303581,7 +303607,7 @@ module \ls180 update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end attribute \src "ls180.v:944.5-944.28" - process $proc$ls180.v:944$3456 + process $proc$ls180.v:944$3458 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always @@ -303589,7 +303615,7 @@ module \ls180 update \main_uart_phy_re $1\main_uart_phy_re[0:0] end attribute \src "ls180.v:946.5-946.36" - process $proc$ls180.v:946$3457 + process $proc$ls180.v:946$3459 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always @@ -303597,7 +303623,7 @@ module \ls180 update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$3141 + process $proc$ls180.v:95$3143 assign { } { } assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 sync always @@ -303605,7 +303631,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] end attribute \src "ls180.v:950.5-950.39" - process $proc$ls180.v:950$3458 + process $proc$ls180.v:950$3460 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always @@ -303613,7 +303639,7 @@ module \ls180 update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end attribute \src "ls180.v:951.12-951.54" - process $proc$ls180.v:951$3459 + process $proc$ls180.v:951$3461 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always @@ -303621,7 +303647,7 @@ module \ls180 update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end attribute \src "ls180.v:952.11-952.38" - process $proc$ls180.v:952$3460 + process $proc$ls180.v:952$3462 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always @@ -303629,7 +303655,7 @@ module \ls180 update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end attribute \src "ls180.v:953.11-953.43" - process $proc$ls180.v:953$3461 + process $proc$ls180.v:953$3463 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always @@ -303637,7 +303663,7 @@ module \ls180 update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end attribute \src "ls180.v:954.5-954.33" - process $proc$ls180.v:954$3462 + process $proc$ls180.v:954$3464 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always @@ -303645,7 +303671,7 @@ module \ls180 update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end attribute \src "ls180.v:955.5-955.38" - process $proc$ls180.v:955$3463 + process $proc$ls180.v:955$3465 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always @@ -303653,7 +303679,7 @@ module \ls180 update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end attribute \src "ls180.v:957.5-957.38" - process $proc$ls180.v:957$3464 + process $proc$ls180.v:957$3466 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always @@ -303661,7 +303687,7 @@ module \ls180 sync init end attribute \src "ls180.v:958.5-958.37" - process $proc$ls180.v:958$3465 + process $proc$ls180.v:958$3467 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always @@ -303669,7 +303695,7 @@ module \ls180 sync init end attribute \src "ls180.v:959.11-959.51" - process $proc$ls180.v:959$3466 + process $proc$ls180.v:959$3468 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always @@ -303677,7 +303703,7 @@ module \ls180 update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end attribute \src "ls180.v:960.5-960.39" - process $proc$ls180.v:960$3467 + process $proc$ls180.v:960$3469 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always @@ -303685,7 +303711,7 @@ module \ls180 update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end attribute \src "ls180.v:961.12-961.54" - process $proc$ls180.v:961$3468 + process $proc$ls180.v:961$3470 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always @@ -303693,7 +303719,7 @@ module \ls180 update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end attribute \src "ls180.v:963.5-963.30" - process $proc$ls180.v:963$3469 + process $proc$ls180.v:963$3471 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always @@ -303701,7 +303727,7 @@ module \ls180 update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end attribute \src "ls180.v:964.11-964.38" - process $proc$ls180.v:964$3470 + process $proc$ls180.v:964$3472 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always @@ -303709,7 +303735,7 @@ module \ls180 update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end attribute \src "ls180.v:965.11-965.43" - process $proc$ls180.v:965$3471 + process $proc$ls180.v:965$3473 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always @@ -303717,7 +303743,7 @@ module \ls180 update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end attribute \src "ls180.v:966.5-966.33" - process $proc$ls180.v:966$3472 + process $proc$ls180.v:966$3474 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always @@ -303725,7 +303751,7 @@ module \ls180 update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end attribute \src "ls180.v:97.12-97.58" - process $proc$ls180.v:97$3142 + process $proc$ls180.v:97$3144 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 sync always @@ -303733,7 +303759,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] end attribute \src "ls180.v:977.5-977.32" - process $proc$ls180.v:977$3473 + process $proc$ls180.v:977$3475 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always @@ -303741,7 +303767,7 @@ module \ls180 update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end attribute \src "ls180.v:979.5-979.30" - process $proc$ls180.v:979$3474 + process $proc$ls180.v:979$3476 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always @@ -303749,7 +303775,7 @@ module \ls180 update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$3143 + process $proc$ls180.v:98$3145 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 sync always @@ -303757,7 +303783,7 @@ module \ls180 update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end attribute \src "ls180.v:980.5-980.36" - process $proc$ls180.v:980$3475 + process $proc$ls180.v:980$3477 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always @@ -303765,7 +303791,7 @@ module \ls180 update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end attribute \src "ls180.v:982.5-982.32" - process $proc$ls180.v:982$3476 + process $proc$ls180.v:982$3478 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always @@ -303773,7 +303799,7 @@ module \ls180 update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end attribute \src "ls180.v:984.5-984.30" - process $proc$ls180.v:984$3477 + process $proc$ls180.v:984$3479 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always @@ -303781,7 +303807,7 @@ module \ls180 update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end attribute \src "ls180.v:985.5-985.36" - process $proc$ls180.v:985$3478 + process $proc$ls180.v:985$3480 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always @@ -303789,7 +303815,7 @@ module \ls180 update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end attribute \src "ls180.v:989.11-989.49" - process $proc$ls180.v:989$3479 + process $proc$ls180.v:989$3481 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always @@ -303797,7 +303823,7 @@ module \ls180 update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end attribute \src "ls180.v:993.11-993.50" - process $proc$ls180.v:993$3480 + process $proc$ls180.v:993$3482 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always @@ -303805,7 +303831,7 @@ module \ls180 update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end attribute \src "ls180.v:994.11-994.48" - process $proc$ls180.v:994$3481 + process $proc$ls180.v:994$3483 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always @@ -303813,7 +303839,7 @@ module \ls180 update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end attribute \src "ls180.v:995.5-995.37" - process $proc$ls180.v:995$3482 + process $proc$ls180.v:995$3484 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always @@ -305558,27 +305584,27 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2916_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2942_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2968_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2994_DATA - connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3020_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2918_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2944_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2970_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2996_DATA + connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3022_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3027_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3029_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3034_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3036_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3041_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3043_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3048_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3050_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3069_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3071_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3076_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3078_DATA end attribute \src "libresoc.v:146562.1-146620.10" attribute \cells_not_processed 1 -- 2.30.2